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"https://conda.anaconda.org/conda-forge/linux-64/sdl3-3.2.18-h68140b3_0.conda", + "version": "3.2.18" +} \ No newline at end of file diff --git a/man/man1/bzcmp.1 b/man/man1/bzcmp.1 new file mode 100644 index 0000000000000000000000000000000000000000..2ba7e12e201289270ebfa24ff05319546d9acccd --- /dev/null +++ b/man/man1/bzcmp.1 @@ -0,0 +1 @@ +.so man1/bzdiff.1 diff --git a/man/man1/bzdiff.1 b/man/man1/bzdiff.1 new file mode 100644 index 0000000000000000000000000000000000000000..adb7a8e724ef28af51c53562132e7fdb2a433fba --- /dev/null +++ b/man/man1/bzdiff.1 @@ -0,0 +1,47 @@ +\"Shamelessly copied from zmore.1 by Philippe Troin +\"for Debian GNU/Linux +.TH BZDIFF 1 +.SH NAME +bzcmp, bzdiff \- compare bzip2 compressed files +.SH SYNOPSIS +.B bzcmp +[ cmp_options ] file1 +[ file2 ] +.br +.B bzdiff +[ diff_options ] file1 +[ file2 ] +.SH DESCRIPTION +.I Bzcmp +and +.I bzdiff +are used to invoke the +.I cmp +or the +.I diff +program on bzip2 compressed files. All options specified are passed +directly to +.I cmp +or +.IR diff "." +If only 1 file is specified, then the files compared are +.I file1 +and an uncompressed +.IR file1 ".bz2." +If two files are specified, then they are uncompressed if necessary and fed to +.I cmp +or +.IR diff "." +The exit status from +.I cmp +or +.I diff +is preserved. +.SH "SEE ALSO" +cmp(1), diff(1), bzmore(1), bzless(1), bzgrep(1), bzip2(1) +.SH BUGS +Messages from the +.I cmp +or +.I diff +programs refer to temporary filenames instead of those specified. diff --git a/man/man1/bzegrep.1 b/man/man1/bzegrep.1 new file mode 100644 index 0000000000000000000000000000000000000000..b208cf5aec12ae399a3b00a8a94228171186f070 --- /dev/null +++ b/man/man1/bzegrep.1 @@ -0,0 +1 @@ +.so man1/bzgrep.1 diff --git a/man/man1/bzfgrep.1 b/man/man1/bzfgrep.1 new file mode 100644 index 0000000000000000000000000000000000000000..b208cf5aec12ae399a3b00a8a94228171186f070 --- /dev/null +++ b/man/man1/bzfgrep.1 @@ -0,0 +1 @@ +.so man1/bzgrep.1 diff --git a/man/man1/bzgrep.1 b/man/man1/bzgrep.1 new file mode 100644 index 0000000000000000000000000000000000000000..930af8c7fcb8205c91befbc33f0ef99cd85f6e1a --- /dev/null +++ b/man/man1/bzgrep.1 @@ -0,0 +1,56 @@ +\"Shamelessly copied from zmore.1 by Philippe Troin +\"for Debian GNU/Linux +.TH BZGREP 1 +.SH NAME +bzgrep, bzfgrep, bzegrep \- search possibly bzip2 compressed files for a regular expression +.SH SYNOPSIS +.B bzgrep +[ grep_options ] +.BI [\ -e\ ] " pattern" +.IR filename ".\|.\|." +.br +.B bzegrep +[ egrep_options ] +.BI [\ -e\ ] " pattern" +.IR filename ".\|.\|." +.br +.B bzfgrep +[ fgrep_options ] +.BI [\ -e\ ] " pattern" +.IR filename ".\|.\|." +.SH DESCRIPTION +.IR Bzgrep +is used to invoke the +.I grep +on bzip2-compressed files. All options specified are passed directly to +.I grep. +If no file is specified, then the standard input is decompressed +if necessary and fed to grep. +Otherwise the given files are uncompressed if necessary and fed to +.I grep. +.PP +If +.I bzgrep +is invoked as +.I bzegrep +or +.I bzfgrep +then +.I egrep +or +.I fgrep +is used instead of +.I grep. +If the GREP environment variable is set, +.I bzgrep +uses it as the +.I grep +program to be invoked. For example: + + for sh: GREP=fgrep bzgrep string files + for csh: (setenv GREP fgrep; bzgrep string files) +.SH AUTHOR +Charles Levert (charles@comm.polymtl.ca). Adapted to bzip2 by Philippe +Troin for Debian GNU/Linux. +.SH "SEE ALSO" +grep(1), egrep(1), fgrep(1), bzdiff(1), bzmore(1), bzless(1), bzip2(1) diff --git a/man/man1/bzip2.1 b/man/man1/bzip2.1 new file mode 100644 index 0000000000000000000000000000000000000000..0cbcdab00ed82151a5b06951c837692785184082 --- /dev/null +++ b/man/man1/bzip2.1 @@ -0,0 +1,454 @@ +.PU +.TH bzip2 1 +.SH NAME +bzip2, bunzip2 \- a block-sorting file compressor, v1.0.8 +.br +bzcat \- decompresses files to stdout +.br +bzip2recover \- recovers data from damaged bzip2 files + +.SH SYNOPSIS +.ll +8 +.B bzip2 +.RB [ " \-cdfkqstvzVL123456789 " ] +[ +.I "filenames \&..." +] +.ll -8 +.br +.B bunzip2 +.RB [ " \-fkvsVL " ] +[ +.I "filenames \&..." +] +.br +.B bzcat +.RB [ " \-s " ] +[ +.I "filenames \&..." +] +.br +.B bzip2recover +.I "filename" + +.SH DESCRIPTION +.I bzip2 +compresses files using the Burrows-Wheeler block sorting +text compression algorithm, and Huffman coding. Compression is +generally considerably better than that achieved by more conventional +LZ77/LZ78-based compressors, and approaches the performance of the PPM +family of statistical compressors. + +The command-line options are deliberately very similar to +those of +.I GNU gzip, +but they are not identical. + +.I bzip2 +expects a list of file names to accompany the +command-line flags. Each file is replaced by a compressed version of +itself, with the name "original_name.bz2". +Each compressed file +has the same modification date, permissions, and, when possible, +ownership as the corresponding original, so that these properties can +be correctly restored at decompression time. File name handling is +naive in the sense that there is no mechanism for preserving original +file names, permissions, ownerships or dates in filesystems which lack +these concepts, or have serious file name length restrictions, such as +MS-DOS. + +.I bzip2 +and +.I bunzip2 +will by default not overwrite existing +files. If you want this to happen, specify the \-f flag. + +If no file names are specified, +.I bzip2 +compresses from standard +input to standard output. In this case, +.I bzip2 +will decline to +write compressed output to a terminal, as this would be entirely +incomprehensible and therefore pointless. + +.I bunzip2 +(or +.I bzip2 \-d) +decompresses all +specified files. Files which were not created by +.I bzip2 +will be detected and ignored, and a warning issued. +.I bzip2 +attempts to guess the filename for the decompressed file +from that of the compressed file as follows: + + filename.bz2 becomes filename + filename.bz becomes filename + filename.tbz2 becomes filename.tar + filename.tbz becomes filename.tar + anyothername becomes anyothername.out + +If the file does not end in one of the recognised endings, +.I .bz2, +.I .bz, +.I .tbz2 +or +.I .tbz, +.I bzip2 +complains that it cannot +guess the name of the original file, and uses the original name +with +.I .out +appended. + +As with compression, supplying no +filenames causes decompression from +standard input to standard output. + +.I bunzip2 +will correctly decompress a file which is the +concatenation of two or more compressed files. The result is the +concatenation of the corresponding uncompressed files. Integrity +testing (\-t) +of concatenated +compressed files is also supported. + +You can also compress or decompress files to the standard output by +giving the \-c flag. Multiple files may be compressed and +decompressed like this. The resulting outputs are fed sequentially to +stdout. Compression of multiple files +in this manner generates a stream +containing multiple compressed file representations. Such a stream +can be decompressed correctly only by +.I bzip2 +version 0.9.0 or +later. Earlier versions of +.I bzip2 +will stop after decompressing +the first file in the stream. + +.I bzcat +(or +.I bzip2 -dc) +decompresses all specified files to +the standard output. + +.I bzip2 +will read arguments from the environment variables +.I BZIP2 +and +.I BZIP, +in that order, and will process them +before any arguments read from the command line. This gives a +convenient way to supply default arguments. + +Compression is always performed, even if the compressed +file is slightly +larger than the original. Files of less than about one hundred bytes +tend to get larger, since the compression mechanism has a constant +overhead in the region of 50 bytes. Random data (including the output +of most file compressors) is coded at about 8.05 bits per byte, giving +an expansion of around 0.5%. + +As a self-check for your protection, +.I +bzip2 +uses 32-bit CRCs to +make sure that the decompressed version of a file is identical to the +original. This guards against corruption of the compressed data, and +against undetected bugs in +.I bzip2 +(hopefully very unlikely). The +chances of data corruption going undetected is microscopic, about one +chance in four billion for each file processed. Be aware, though, that +the check occurs upon decompression, so it can only tell you that +something is wrong. It can't help you +recover the original uncompressed +data. You can use +.I bzip2recover +to try to recover data from +damaged files. + +Return values: 0 for a normal exit, 1 for environmental problems (file +not found, invalid flags, I/O errors, &c), 2 to indicate a corrupt +compressed file, 3 for an internal consistency error (eg, bug) which +caused +.I bzip2 +to panic. + +.SH OPTIONS +.TP +.B \-c --stdout +Compress or decompress to standard output. +.TP +.B \-d --decompress +Force decompression. +.I bzip2, +.I bunzip2 +and +.I bzcat +are +really the same program, and the decision about what actions to take is +done on the basis of which name is used. This flag overrides that +mechanism, and forces +.I bzip2 +to decompress. +.TP +.B \-z --compress +The complement to \-d: forces compression, regardless of the +invocation name. +.TP +.B \-t --test +Check integrity of the specified file(s), but don't decompress them. +This really performs a trial decompression and throws away the result. +.TP +.B \-f --force +Force overwrite of output files. Normally, +.I bzip2 +will not overwrite +existing output files. Also forces +.I bzip2 +to break hard links +to files, which it otherwise wouldn't do. + +bzip2 normally declines to decompress files which don't have the +correct magic header bytes. If forced (-f), however, it will pass +such files through unmodified. This is how GNU gzip behaves. +.TP +.B \-k --keep +Keep (don't delete) input files during compression +or decompression. +.TP +.B \-s --small +Reduce memory usage, for compression, decompression and testing. Files +are decompressed and tested using a modified algorithm which only +requires 2.5 bytes per block byte. This means any file can be +decompressed in 2300k of memory, albeit at about half the normal speed. + +During compression, \-s selects a block size of 200k, which limits +memory use to around the same figure, at the expense of your compression +ratio. In short, if your machine is low on memory (8 megabytes or +less), use \-s for everything. See MEMORY MANAGEMENT below. +.TP +.B \-q --quiet +Suppress non-essential warning messages. Messages pertaining to +I/O errors and other critical events will not be suppressed. +.TP +.B \-v --verbose +Verbose mode -- show the compression ratio for each file processed. +Further \-v's increase the verbosity level, spewing out lots of +information which is primarily of interest for diagnostic purposes. +.TP +.B \-L --license -V --version +Display the software version, license terms and conditions. +.TP +.B \-1 (or \-\-fast) to \-9 (or \-\-best) +Set the block size to 100 k, 200 k .. 900 k when compressing. Has no +effect when decompressing. See MEMORY MANAGEMENT below. +The \-\-fast and \-\-best aliases are primarily for GNU gzip +compatibility. In particular, \-\-fast doesn't make things +significantly faster. +And \-\-best merely selects the default behaviour. +.TP +.B \-- +Treats all subsequent arguments as file names, even if they start +with a dash. This is so you can handle files with names beginning +with a dash, for example: bzip2 \-- \-myfilename. +.TP +.B \--repetitive-fast --repetitive-best +These flags are redundant in versions 0.9.5 and above. They provided +some coarse control over the behaviour of the sorting algorithm in +earlier versions, which was sometimes useful. 0.9.5 and above have an +improved algorithm which renders these flags irrelevant. + +.SH MEMORY MANAGEMENT +.I bzip2 +compresses large files in blocks. The block size affects +both the compression ratio achieved, and the amount of memory needed for +compression and decompression. The flags \-1 through \-9 +specify the block size to be 100,000 bytes through 900,000 bytes (the +default) respectively. At decompression time, the block size used for +compression is read from the header of the compressed file, and +.I bunzip2 +then allocates itself just enough memory to decompress +the file. Since block sizes are stored in compressed files, it follows +that the flags \-1 to \-9 are irrelevant to and so ignored +during decompression. + +Compression and decompression requirements, +in bytes, can be estimated as: + + Compression: 400k + ( 8 x block size ) + + Decompression: 100k + ( 4 x block size ), or + 100k + ( 2.5 x block size ) + +Larger block sizes give rapidly diminishing marginal returns. Most of +the compression comes from the first two or three hundred k of block +size, a fact worth bearing in mind when using +.I bzip2 +on small machines. +It is also important to appreciate that the decompression memory +requirement is set at compression time by the choice of block size. + +For files compressed with the default 900k block size, +.I bunzip2 +will require about 3700 kbytes to decompress. To support decompression +of any file on a 4 megabyte machine, +.I bunzip2 +has an option to +decompress using approximately half this amount of memory, about 2300 +kbytes. Decompression speed is also halved, so you should use this +option only where necessary. The relevant flag is -s. + +In general, try and use the largest block size memory constraints allow, +since that maximises the compression achieved. Compression and +decompression speed are virtually unaffected by block size. + +Another significant point applies to files which fit in a single block +-- that means most files you'd encounter using a large block size. The +amount of real memory touched is proportional to the size of the file, +since the file is smaller than a block. For example, compressing a file +20,000 bytes long with the flag -9 will cause the compressor to +allocate around 7600k of memory, but only touch 400k + 20000 * 8 = 560 +kbytes of it. Similarly, the decompressor will allocate 3700k but only +touch 100k + 20000 * 4 = 180 kbytes. + +Here is a table which summarises the maximum memory usage for different +block sizes. Also recorded is the total compressed size for 14 files of +the Calgary Text Compression Corpus totalling 3,141,622 bytes. This +column gives some feel for how compression varies with block size. +These figures tend to understate the advantage of larger block sizes for +larger files, since the Corpus is dominated by smaller files. + + Compress Decompress Decompress Corpus + Flag usage usage -s usage Size + + -1 1200k 500k 350k 914704 + -2 2000k 900k 600k 877703 + -3 2800k 1300k 850k 860338 + -4 3600k 1700k 1100k 846899 + -5 4400k 2100k 1350k 845160 + -6 5200k 2500k 1600k 838626 + -7 6100k 2900k 1850k 834096 + -8 6800k 3300k 2100k 828642 + -9 7600k 3700k 2350k 828642 + +.SH RECOVERING DATA FROM DAMAGED FILES +.I bzip2 +compresses files in blocks, usually 900kbytes long. Each +block is handled independently. If a media or transmission error causes +a multi-block .bz2 +file to become damaged, it may be possible to +recover data from the undamaged blocks in the file. + +The compressed representation of each block is delimited by a 48-bit +pattern, which makes it possible to find the block boundaries with +reasonable certainty. Each block also carries its own 32-bit CRC, so +damaged blocks can be distinguished from undamaged ones. + +.I bzip2recover +is a simple program whose purpose is to search for +blocks in .bz2 files, and write each block out into its own .bz2 +file. You can then use +.I bzip2 +\-t +to test the +integrity of the resulting files, and decompress those which are +undamaged. + +.I bzip2recover +takes a single argument, the name of the damaged file, +and writes a number of files "rec00001file.bz2", +"rec00002file.bz2", etc, containing the extracted blocks. +The output filenames are designed so that the use of +wildcards in subsequent processing -- for example, +"bzip2 -dc rec*file.bz2 > recovered_data" -- processes the files in +the correct order. + +.I bzip2recover +should be of most use dealing with large .bz2 +files, as these will contain many blocks. It is clearly +futile to use it on damaged single-block files, since a +damaged block cannot be recovered. If you wish to minimise +any potential data loss through media or transmission errors, +you might consider compressing with a smaller +block size. + +.SH PERFORMANCE NOTES +The sorting phase of compression gathers together similar strings in the +file. Because of this, files containing very long runs of repeated +symbols, like "aabaabaabaab ..." (repeated several hundred times) may +compress more slowly than normal. Versions 0.9.5 and above fare much +better than previous versions in this respect. The ratio between +worst-case and average-case compression time is in the region of 10:1. +For previous versions, this figure was more like 100:1. You can use the +\-vvvv option to monitor progress in great detail, if you want. + +Decompression speed is unaffected by these phenomena. + +.I bzip2 +usually allocates several megabytes of memory to operate +in, and then charges all over it in a fairly random fashion. This means +that performance, both for compressing and decompressing, is largely +determined by the speed at which your machine can service cache misses. +Because of this, small changes to the code to reduce the miss rate have +been observed to give disproportionately large performance improvements. +I imagine +.I bzip2 +will perform best on machines with very large caches. + +.SH CAVEATS +I/O error messages are not as helpful as they could be. +.I bzip2 +tries hard to detect I/O errors and exit cleanly, but the details of +what the problem is sometimes seem rather misleading. + +This manual page pertains to version 1.0.8 of +.I bzip2. +Compressed data created by this version is entirely forwards and +backwards compatible with the previous public releases, versions +0.1pl2, 0.9.0, 0.9.5, 1.0.0, 1.0.1, 1.0.2 and above, but with the following +exception: 0.9.0 and above can correctly decompress multiple +concatenated compressed files. 0.1pl2 cannot do this; it will stop +after decompressing just the first file in the stream. + +.I bzip2recover +versions prior to 1.0.2 used 32-bit integers to represent +bit positions in compressed files, so they could not handle compressed +files more than 512 megabytes long. Versions 1.0.2 and above use +64-bit ints on some platforms which support them (GNU supported +targets, and Windows). To establish whether or not bzip2recover was +built with such a limitation, run it without arguments. In any event +you can build yourself an unlimited version if you can recompile it +with MaybeUInt64 set to be an unsigned 64-bit integer. + + + +.SH AUTHOR +Julian Seward, jseward@acm.org. + +https://sourceware.org/bzip2/ + +The ideas embodied in +.I bzip2 +are due to (at least) the following +people: Michael Burrows and David Wheeler (for the block sorting +transformation), David Wheeler (again, for the Huffman coder), Peter +Fenwick (for the structured coding model in the original +.I bzip, +and many refinements), and Alistair Moffat, Radford Neal and Ian Witten +(for the arithmetic coder in the original +.I bzip). +I am much +indebted for their help, support and advice. See the manual in the +source distribution for pointers to sources of documentation. Christian +von Roques encouraged me to look for faster sorting algorithms, so as to +speed up compression. Bela Lubkin encouraged me to improve the +worst-case compression performance. +Donna Robinson XMLised the documentation. +The bz* scripts are derived from those of GNU gzip. +Many people sent patches, helped +with portability problems, lent machines, gave advice and were generally +helpful. diff --git a/man/man1/bzless.1 b/man/man1/bzless.1 new file mode 100644 index 0000000000000000000000000000000000000000..b849965938bed4048b65f842a3dc7f69770e66a3 --- /dev/null +++ b/man/man1/bzless.1 @@ -0,0 +1 @@ +.so man1/bzmore.1 diff --git a/man/man1/bzmore.1 b/man/man1/bzmore.1 new file mode 100644 index 0000000000000000000000000000000000000000..b437d3b031f5dc1290359496971d2c2545b188ff --- /dev/null +++ b/man/man1/bzmore.1 @@ -0,0 +1,152 @@ +.\"Shamelessly copied from zmore.1 by Philippe Troin +.\"for Debian GNU/Linux +.TH BZMORE 1 +.SH NAME +bzmore, bzless \- file perusal filter for crt viewing of bzip2 compressed text +.SH SYNOPSIS +.B bzmore +[ name ... ] +.br +.B bzless +[ name ... ] +.SH NOTE +In the following description, +.I bzless +and +.I less +can be used interchangeably with +.I bzmore +and +.I more. +.SH DESCRIPTION +.I Bzmore +is a filter which allows examination of compressed or plain text files +one screenful at a time on a soft-copy terminal. +.I bzmore +works on files compressed with +.I bzip2 +and also on uncompressed files. +If a file does not exist, +.I bzmore +looks for a file of the same name with the addition of a .bz2 suffix. +.PP +.I Bzmore +normally pauses after each screenful, printing --More-- +at the bottom of the screen. +If the user then types a carriage return, one more line is displayed. +If the user hits a space, +another screenful is displayed. Other possibilities are enumerated later. +.PP +.I Bzmore +looks in the file +.I /etc/termcap +to determine terminal characteristics, +and to determine the default window size. +On a terminal capable of displaying 24 lines, +the default window size is 22 lines. +Other sequences which may be typed when +.I bzmore +pauses, and their effects, are as follows (\fIi\fP is an optional integer +argument, defaulting to 1) : +.PP +.IP \fIi\|\fP +display +.I i +more lines, (or another screenful if no argument is given) +.PP +.IP ^D +display 11 more lines (a ``scroll''). +If +.I i +is given, then the scroll size is set to \fIi\|\fP. +.PP +.IP d +same as ^D (control-D) +.PP +.IP \fIi\|\fPz +same as typing a space except that \fIi\|\fP, if present, becomes the new +window size. Note that the window size reverts back to the default at the +end of the current file. +.PP +.IP \fIi\|\fPs +skip \fIi\|\fP lines and print a screenful of lines +.PP +.IP \fIi\|\fPf +skip \fIi\fP screenfuls and print a screenful of lines +.PP +.IP "q or Q" +quit reading the current file; go on to the next (if any) +.PP +.IP "e or q" +When the prompt --More--(Next file: +.IR file ) +is printed, this command causes bzmore to exit. +.PP +.IP s +When the prompt --More--(Next file: +.IR file ) +is printed, this command causes bzmore to skip the next file and continue. +.PP +.IP = +Display the current line number. +.PP +.IP \fIi\|\fP/expr +search for the \fIi\|\fP-th occurrence of the regular expression \fIexpr.\fP +If the pattern is not found, +.I bzmore +goes on to the next file (if any). +Otherwise, a screenful is displayed, starting two lines before the place +where the expression was found. +The user's erase and kill characters may be used to edit the regular +expression. +Erasing back past the first column cancels the search command. +.PP +.IP \fIi\|\fPn +search for the \fIi\|\fP-th occurrence of the last regular expression entered. +.PP +.IP !command +invoke a shell with \fIcommand\|\fP. +The character `!' in "command" are replaced with the +previous shell command. The sequence "\\!" is replaced by "!". +.PP +.IP ":q or :Q" +quit reading the current file; go on to the next (if any) +(same as q or Q). +.PP +.IP . +(dot) repeat the previous command. +.PP +The commands take effect immediately, i.e., it is not necessary to +type a carriage return. +Up to the time when the command character itself is given, +the user may hit the line kill character to cancel the numerical +argument being formed. +In addition, the user may hit the erase character to redisplay the +--More-- message. +.PP +At any time when output is being sent to the terminal, the user can +hit the quit key (normally control\-\\). +.I Bzmore +will stop sending output, and will display the usual --More-- +prompt. +The user may then enter one of the above commands in the normal manner. +Unfortunately, some output is lost when this is done, due to the +fact that any characters waiting in the terminal's output queue +are flushed when the quit signal occurs. +.PP +The terminal is set to +.I noecho +mode by this program so that the output can be continuous. +What you type will thus not show on your terminal, except for the / and ! +commands. +.PP +If the standard output is not a teletype, then +.I bzmore +acts just like +.I bzcat, +except that a header is printed before each file. +.SH FILES +.DT +/etc/termcap Terminal data base +.SH "SEE ALSO" +more(1), less(1), bzip2(1), bzdiff(1), bzgrep(1) diff --git a/man/man1/cpp.1 b/man/man1/cpp.1 new file mode 100644 index 0000000000000000000000000000000000000000..0e0cb0c98c6d2a96a67d97439b4673a60021ecb4 --- /dev/null +++ b/man/man1/cpp.1 @@ -0,0 +1,941 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. 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Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +cpp \- The C Preprocessor +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +cpp [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-iquote\fR\fIdir\fR...] + [\fB\-M\fR|\fB\-MM\fR] [\fB\-MG\fR] [\fB\-MF\fR \fIfilename\fR] + [\fB\-MP\fR] [\fB\-MQ\fR \fItarget\fR...] + [\fB\-MT\fR \fItarget\fR...] + \fIinfile\fR [[\fB\-o\fR] \fIoutfile\fR] +.PP +Only the most useful options are given above; see below for a more +complete list of preprocessor-specific options. +In addition, \fBcpp\fR accepts most \fBgcc\fR driver options, which +are not listed here. Refer to the \s-1GCC\s0 documentation for details. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The C preprocessor, often known as \fIcpp\fR, is a \fImacro processor\fR +that is used automatically by the C compiler to transform your program +before compilation. It is called a macro processor because it allows +you to define \fImacros\fR, which are brief abbreviations for longer +constructs. +.PP +The C preprocessor is intended to be used only with C, \*(C+, and +Objective-C source code. In the past, it has been abused as a general +text processor. It will choke on input which does not obey C's lexical +rules. For example, apostrophes will be interpreted as the beginning of +character constants, and cause errors. Also, you cannot rely on it +preserving characteristics of the input which are not significant to +C\-family languages. If a Makefile is preprocessed, all the hard tabs +will be removed, and the Makefile will not work. +.PP +Having said that, you can often get away with using cpp on things which +are not C. Other Algol-ish programming languages are often safe +(Ada, etc.) So is assembly, with caution. \fB\-traditional\-cpp\fR +mode preserves more white space, and is otherwise more permissive. Many +of the problems can be avoided by writing C or \*(C+ style comments +instead of native language comments, and keeping macros simple. +.PP +Wherever possible, you should use a preprocessor geared to the language +you are writing in. Modern versions of the \s-1GNU\s0 assembler have macro +facilities. Most high level programming languages have their own +conditional compilation and inclusion mechanism. If all else fails, +try a true general text processor, such as \s-1GNU M4.\s0 +.PP +C preprocessors vary in some details. This manual discusses the \s-1GNU C\s0 +preprocessor, which provides a small superset of the features of \s-1ISO\s0 +Standard C. In its default mode, the \s-1GNU C\s0 preprocessor does not do a +few things required by the standard. These are features which are +rarely, if ever, used, and may cause surprising changes to the meaning +of a program which does not expect them. To get strict \s-1ISO\s0 Standard C, +you should use the \fB\-std=c90\fR, \fB\-std=c99\fR, +\&\fB\-std=c11\fR or \fB\-std=c17\fR options, depending +on which version of the standard you want. To get all the mandatory +diagnostics, you must also use \fB\-pedantic\fR. +.PP +This manual describes the behavior of the \s-1ISO\s0 preprocessor. To +minimize gratuitous differences, where the \s-1ISO\s0 preprocessor's +behavior does not conflict with traditional semantics, the +traditional preprocessor should behave the same way. The various +differences that do exist are detailed in the section \fBTraditional +Mode\fR. +.PP +For clarity, unless noted otherwise, references to \fB\s-1CPP\s0\fR in this +manual refer to \s-1GNU CPP.\s0 +.SH "OPTIONS" +.IX Header "OPTIONS" +The \fBcpp\fR command expects two file names as arguments, \fIinfile\fR and +\&\fIoutfile\fR. The preprocessor reads \fIinfile\fR together with any +other files it specifies with \fB#include\fR. All the output generated +by the combined input files is written in \fIoutfile\fR. +.PP +Either \fIinfile\fR or \fIoutfile\fR may be \fB\-\fR, which as +\&\fIinfile\fR means to read from standard input and as \fIoutfile\fR +means to write to standard output. If either file is omitted, it +means the same as if \fB\-\fR had been specified for that file. +You can also use the \fB\-o\fR \fIoutfile\fR option to specify the +output file. +.PP +Unless otherwise noted, or the option ends in \fB=\fR, all options +which take an argument may have that argument appear either immediately +after the option, or with a space between option and argument: +\&\fB\-Ifoo\fR and \fB\-I foo\fR have the same effect. +.PP +Many options have multi-letter names; therefore multiple single-letter +options may \fInot\fR be grouped: \fB\-dM\fR is very different from +\&\fB\-d\ \-M\fR. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +Predefine \fIname\fR as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-D name=definition" +The contents of \fIdefinition\fR are tokenized and processed as if +they appeared during translation phase three in a \fB#define\fR +directive. In particular, the definition is truncated by +embedded newline characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like +program you may need to use the shell's quoting syntax to protect +characters such as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you should +quote the option. With \fBsh\fR and \fBcsh\fR, +\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they +are given on the command line. All \fB\-imacros\fR \fIfile\fR and +\&\fB\-include\fR \fIfile\fR options are processed after all +\&\fB\-D\fR and \fB\-U\fR options. +.IP "\fB\-U\fR \fIname\fR" 4 +.IX Item "-U name" +Cancel any previous definition of \fIname\fR, either built in or +provided with a \fB\-D\fR option. +.IP "\fB\-include\fR \fIfile\fR" 4 +.IX Item "-include file" +Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first +line of the primary source file. However, the first directory searched +for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR +the directory containing the main source file. If not found there, it +is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search +chain as normal. +.Sp +If multiple \fB\-include\fR options are given, the files are included +in the order they appear on the command line. +.IP "\fB\-imacros\fR \fIfile\fR" 4 +.IX Item "-imacros file" +Exactly like \fB\-include\fR, except that any output produced by +scanning \fIfile\fR is thrown away. Macros it defines remain defined. +This allows you to acquire all the macros from a header without also +processing its declarations. +.Sp +All files specified by \fB\-imacros\fR are processed before all files +specified by \fB\-include\fR. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. The +standard predefined macros remain defined. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Define additional macros required for using the \s-1POSIX\s0 threads library. +You should use this option consistently for both compilation and linking. +This option is supported on GNU/Linux targets, most other Unix derivatives, +and also on x86 Cygwin and MinGW targets. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +Instead of outputting the result of preprocessing, output a rule +suitable for \fBmake\fR describing the dependencies of the main +source file. The preprocessor outputs one \fBmake\fR rule containing +the object file name for that source file, a colon, and the names of all +the included files, including those coming from \fB\-include\fR or +\&\fB\-imacros\fR command-line options. +.Sp +Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the +object file name consists of the name of the source file with any +suffix replaced with object file suffix and with any leading directory +parts removed. If there are many included files then the rule is +split into several lines using \fB\e\fR\-newline. The rule has no +commands. +.Sp +This option does not suppress the preprocessor's debug output, such as +\&\fB\-dM\fR. To avoid mixing such debug output with the dependency +rules you should explicitly specify the dependency output file with +\&\fB\-MF\fR, or use an environment variable like +\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output +is still sent to the regular output stream as normal. +.Sp +Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses +warnings with an implicit \fB\-w\fR. +.IP "\fB\-MM\fR" 4 +.IX Item "-MM" +Like \fB\-M\fR but do not mention header files that are found in +system header directories, nor header files that are included, +directly or indirectly, from such a header. +.Sp +This implies that the choice of angle brackets or double quotes in an +\&\fB#include\fR directive does not in itself determine whether that +header appears in \fB\-MM\fR dependency output. +.IP "\fB\-MF\fR \fIfile\fR" 4 +.IX Item "-MF file" +When used with \fB\-M\fR or \fB\-MM\fR, specifies a +file to write the dependencies to. If no \fB\-MF\fR switch is given +the preprocessor sends the rules to the same place it would send +preprocessed output. +.Sp +When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, +\&\fB\-MF\fR overrides the default dependency output file. +.Sp +If \fIfile\fR is \fI\-\fR, then the dependencies are written to \fIstdout\fR. +.IP "\fB\-MG\fR" 4 +.IX Item "-MG" +In conjunction with an option such as \fB\-M\fR requesting +dependency generation, \fB\-MG\fR assumes missing header files are +generated files and adds them to the dependency list without raising +an error. The dependency filename is taken directly from the +\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR +also suppresses preprocessed output, as a missing header file renders +this useless. +.Sp +This feature is used in automatic updating of makefiles. +.IP "\fB\-MP\fR" 4 +.IX Item "-MP" +This option instructs \s-1CPP\s0 to add a phony target for each dependency +other than the main file, causing each to depend on nothing. These +dummy rules work around errors \fBmake\fR gives if you remove header +files without updating the \fIMakefile\fR to match. +.Sp +This is typical output: +.Sp +.Vb 1 +\& test.o: test.c test.h +\& +\& test.h: +.Ve +.IP "\fB\-MT\fR \fItarget\fR" 4 +.IX Item "-MT target" +Change the target of the rule emitted by dependency generation. By +default \s-1CPP\s0 takes the name of the main input file, deletes any +directory components and any file suffix such as \fB.c\fR, and +appends the platform's usual object suffix. The result is the target. +.Sp +An \fB\-MT\fR option sets the target to be exactly the string you +specify. If you want multiple targets, you can specify them as a single +argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. +.Sp +For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give +.Sp +.Vb 1 +\& $(objpfx)foo.o: foo.c +.Ve +.IP "\fB\-MQ\fR \fItarget\fR" 4 +.IX Item "-MQ target" +Same as \fB\-MT\fR, but it quotes any characters which are special to +Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives +.Sp +.Vb 1 +\& $$(objpfx)foo.o: foo.c +.Ve +.Sp +The default target is automatically quoted, as if it were given with +\&\fB\-MQ\fR. +.IP "\fB\-MD\fR" 4 +.IX Item "-MD" +\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that +\&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on +whether an \fB\-o\fR option is given. If it is, the driver uses its +argument but with a suffix of \fI.d\fR, otherwise it takes the name +of the input file, removes any directory components and suffix, and +applies a \fI.d\fR suffix. +.Sp +If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any +\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR +is understood to specify a target object file. +.Sp +Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate +a dependency output file as a side effect of the compilation process. +.IP "\fB\-MMD\fR" 4 +.IX Item "-MMD" +Like \fB\-MD\fR except mention only user header files, not system +header files. +.IP "\fB\-fpreprocessed\fR" 4 +.IX Item "-fpreprocessed" +Indicate to the preprocessor that the input file has already been +preprocessed. This suppresses things like macro expansion, trigraph +conversion, escaped newline splicing, and processing of most directives. +The preprocessor still recognizes and removes comments, so that you can +pass a file preprocessed with \fB\-C\fR to the compiler without +problems. In this mode the integrated preprocessor is little more than +a tokenizer for the front ends. +.Sp +\&\fB\-fpreprocessed\fR is implicit if the input file has one of the +extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the +extensions that \s-1GCC\s0 uses for preprocessed files created by +\&\fB\-save\-temps\fR. +.IP "\fB\-fdirectives\-only\fR" 4 +.IX Item "-fdirectives-only" +When preprocessing, handle directives, but do not expand macros. +.Sp +The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR +options. +.Sp +With \fB\-E\fR, preprocessing is limited to the handling of directives +such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other +preprocessor operations, such as macro expansion and trigraph +conversion are not performed. In addition, the \fB\-dD\fR option is +implicitly enabled. +.Sp +With \fB\-fpreprocessed\fR, predefinition of command line and most +builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are +contextually dependent, are handled normally. This enables compilation of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.Sp +With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for +\&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.IP "\fB\-fdollars\-in\-identifiers\fR" 4 +.IX Item "-fdollars-in-identifiers" +Accept \fB$\fR in identifiers. +.IP "\fB\-fextended\-identifiers\fR" 4 +.IX Item "-fextended-identifiers" +Accept universal character names in identifiers. This option is +enabled by default for C99 (and later C standard versions) and \*(C+. +.IP "\fB\-fno\-canonical\-system\-headers\fR" 4 +.IX Item "-fno-canonical-system-headers" +When preprocessing, do not shorten system header paths with canonicalization. +.IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 +.IX Item "-ftabstop=width" +Set the distance between tab stops. This helps the preprocessor report +correct column numbers in warnings or errors, even if tabs appear on the +line. If the value is less than 1 or greater than 100, the option is +ignored. The default is 8. +.IP "\fB\-ftrack\-macro\-expansion\fR[\fB=\fR\fIlevel\fR]" 4 +.IX Item "-ftrack-macro-expansion[=level]" +Track locations of tokens across macro expansions. This allows the +compiler to emit diagnostic about the current macro expansion stack +when a compilation error occurs in a macro expansion. Using this +option makes the preprocessor and the compiler consume more +memory. The \fIlevel\fR parameter can be used to choose the level of +precision of token location tracking thus decreasing the memory +consumption if necessary. Value \fB0\fR of \fIlevel\fR de-activates +this option. Value \fB1\fR tracks tokens locations in a +degraded mode for the sake of minimal memory overhead. In this mode +all tokens resulting from the expansion of an argument of a +function-like macro have the same location. Value \fB2\fR tracks +tokens locations completely. This value is the most memory hungry. +When this option is given no argument, the default parameter value is +\&\fB2\fR. +.Sp +Note that \f(CW\*(C`\-ftrack\-macro\-expansion=2\*(C'\fR is activated by default. +.IP "\fB\-fmacro\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fmacro-prefix-map=old=new" +When preprocessing files residing in directory \fI\fIold\fI\fR, +expand the \f(CW\*(C`_\|_FILE_\|_\*(C'\fR and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR macros as if the +files resided in directory \fI\fInew\fI\fR instead. This can be used +to change an absolute path to a relative path by using \fI.\fR for +\&\fInew\fR which can result in more reproducible builds that are +location independent. This option also affects +\&\f(CW\*(C`_\|_builtin_FILE()\*(C'\fR during compilation. See also +\&\fB\-ffile\-prefix\-map\fR. +.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fexec-charset=charset" +Set the execution character set, used for string and character +constants. The default is \s-1UTF\-8.\s0 \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fwide-exec-charset=charset" +Set the wide execution character set, used for wide string and +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16,\s0 whichever +corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with +\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported +by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have +problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. +.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 +.IX Item "-finput-charset=charset" +Set the input character set, used for translation from the character +set of the input file to the source character set used by \s-1GCC.\s0 If the +locale does not specify, or \s-1GCC\s0 cannot get this information from the +locale, the default is \s-1UTF\-8.\s0 This can be overridden by either the locale +or this command-line option. Currently the command-line option takes +precedence if there's a conflict. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor +emits, after the initial linemarker, a second linemarker with the +current working directory followed by two slashes. \s-1GCC\s0 uses this +directory, when it's present in the preprocessed input, as the +directory emitted as the current working directory in some debugging +information formats. This option is implicitly enabled if debugging +information is enabled, but this can be inhibited with the negated +form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is +present in the command line, this option has no effect, since no +\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. +.IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A predicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR +\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because +it does not use shell special characters. +.IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A -predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it +causes the preprocessor to treat comments as tokens in their own right. +For example, comments appearing at the start of what would be a +directive line have the effect of turning that line into an ordinary +source line, since the first token on the line is no longer a \fB#\fR. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is +like \fB\-C\fR, except that comments contained within macros are +also passed through to the output file where the macro is expanded. +.Sp +In addition to the side effects of the \fB\-C\fR option, the +\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro +to be converted to C\-style comments. This is to prevent later use +of that macro from inadvertently commenting out the remainder of +the source line. +.Sp +The \fB\-CC\fR option is generally used to support lint comments. +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that is +not C code, and will be sent to a program which might be confused by the +linemarkers. +.IP "\fB\-traditional\fR" 4 +.IX Item "-traditional" +.PD 0 +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +.PD +Try to imitate the behavior of pre-standard C preprocessors, as +opposed to \s-1ISO C\s0 preprocessors. +.Sp +Note that \s-1GCC\s0 does not otherwise attempt to emulate a pre-standard +C compiler, and these options are only supported with the \fB\-E\fR +switch, or when invoking \s-1CPP\s0 explicitly. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Support \s-1ISO C\s0 trigraphs. +These are three-character sequences, all starting with \fB??\fR, that +are defined by \s-1ISO C\s0 to stand for single characters. For example, +\&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character +constant for a newline. +.Sp +By default, \s-1GCC\s0 ignores trigraphs, but in +standard-conforming modes it converts them. See the \fB\-std\fR and +\&\fB\-ansi\fR options. +.IP "\fB\-remap\fR" 4 +.IX Item "-remap" +Enable special code to work around file systems which only permit very +short file names, such as MS-DOS. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the +\&\fB#include\fR stack it is. Precompiled header files are also +printed, even if they are found to be invalid; an invalid precompiled +header file is printed with \fB...x\fR and a valid one with \fB...!\fR . +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +Says to make debugging dumps during compilation as specified by +\&\fIletters\fR. The flags documented here are those relevant to the +preprocessor. Other \fIletters\fR are interpreted +by the compiler proper, or reserved for future versions of \s-1GCC,\s0 and so +are silently ignored. If you specify \fIletters\fR whose behavior +conflicts, the result is undefined. +.RS 4 +.IP "\fB\-dM\fR" 4 +.IX Item "-dM" +Instead of the normal output, generate a list of \fB#define\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way of +finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.h\fR, the command +.Sp +.Vb 1 +\& touch foo.h; cpp \-dM foo.h +.Ve +.Sp +shows all the predefined macros. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Like \fB\-dM\fR except in two respects: it does \fInot\fR include the +predefined macros, and it outputs \fIboth\fR the \fB#define\fR +directives and the result of preprocessing. Both kinds of output go to +the standard output file. +.IP "\fB\-dN\fR" 4 +.IX Item "-dN" +Like \fB\-dD\fR, but emit only the macro names, not their expansions. +.IP "\fB\-dI\fR" 4 +.IX Item "-dI" +Output \fB#include\fR directives in addition to the result of +preprocessing. +.IP "\fB\-dU\fR" 4 +.IX Item "-dU" +Like \fB\-dD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and +\&\fB#undef\fR directives are also output for macros tested but +undefined at the time. +.RE +.RS 4 +.RE +.IP "\fB\-fdebug\-cpp\fR" 4 +.IX Item "-fdebug-cpp" +This option is only useful for debugging \s-1GCC.\s0 When used from \s-1CPP\s0 or with +\&\fB\-E\fR, it dumps debugging information about location maps. Every +token in the output is preceded by the dump of the map its location +belongs to. +.Sp +When used from \s-1GCC\s0 without \fB\-E\fR, this option has no effect. +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +.PD 0 +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +.PD +Add the directory \fIdir\fR to the list of directories to be searched +for header files during preprocessing. +.Sp +If \fIdir\fR begins with \fB=\fR or \f(CW$SYSROOT\fR, then the \fB=\fR +or \f(CW$SYSROOT\fR is replaced by the sysroot prefix; see +\&\fB\-\-sysroot\fR and \fB\-isysroot\fR. +.Sp +Directories specified with \fB\-iquote\fR apply only to the quote +form of the directive, \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. +Directories specified with \fB\-I\fR, \fB\-isystem\fR, +or \fB\-idirafter\fR apply to lookup for both the +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR and +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR directives. +.Sp +You can specify any number or combination of these options on the +command line to search for header files in several directories. +The lookup order is as follows: +.RS 4 +.IP "1." 4 +.IX Item "1." +For the quote form of the include directive, the directory of the current +file is searched first. +.IP "2." 4 +.IX Item "2." +For the quote form of the include directive, the directories specified +by \fB\-iquote\fR options are searched in left-to-right order, +as they appear on the command line. +.IP "3." 4 +.IX Item "3." +Directories specified with \fB\-I\fR options are scanned in +left-to-right order. +.IP "4." 4 +.IX Item "4." +Directories specified with \fB\-isystem\fR options are scanned in +left-to-right order. +.IP "5." 4 +.IX Item "5." +Standard system directories are scanned. +.IP "6." 4 +.IX Item "6." +Directories specified with \fB\-idirafter\fR options are scanned in +left-to-right order. +.RE +.RS 4 +.Sp +You can use \fB\-I\fR to override a system header +file, substituting your own version, since these directories are +searched before the standard system header file directories. +However, you should +not use this option to add directories that contain vendor-supplied +system header files; use \fB\-isystem\fR for that. +.Sp +The \fB\-isystem\fR and \fB\-idirafter\fR options also mark the directory +as a system directory, so that it gets the same special treatment that +is applied to the standard system directories. +.Sp +If a standard system include directory, or a directory specified with +\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR +option is ignored. The directory is still searched but as a +system directory at its normal position in the system include chain. +This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and +the ordering for the \f(CW\*(C`#include_next\*(C'\fR directive are not inadvertently +changed. +If you really need to change the search order for system directories, +use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options. +.RE +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +Split the include path. +This option has been deprecated. Please use \fB\-iquote\fR instead for +\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR +option. +.Sp +Any directories specified with \fB\-I\fR +options before \fB\-I\-\fR are searched only for headers requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are +specified with \fB\-I\fR options after the \fB\-I\-\fR, those +directories are searched for all \fB#include\fR directives. +.Sp +In addition, \fB\-I\-\fR inhibits the use of the directory of the current +file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. There is no way to override this effect of \fB\-I\-\fR. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the prefix represents a directory, you should include the +final \fB/\fR. +.IP "\fB\-iwithprefix\fR \fIdir\fR" 4 +.IX Item "-iwithprefix dir" +.PD 0 +.IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 +.IX Item "-iwithprefixbefore dir" +.PD +Append \fIdir\fR to the prefix specified previously with +\&\fB\-iprefix\fR, and add the resulting directory to the include search +path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR +would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files (except for Darwin targets, where it applies to both header +files and libraries). See the \fB\-\-sysroot\fR option for more +information. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing +target-specific \*(C+ headers. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. +Only the directories explicitly specified with \fB\-I\fR, +\&\fB\-iquote\fR, \fB\-isystem\fR, and/or \fB\-idirafter\fR +options (and the directory of the current file, if appropriate) +are searched. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the \*(C+\-specific standard directories, +but do still search the other standard directories. (This option is +used when building the \*(C+ library.) +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +.PD 0 +.IP "\fB\-Wcomments\fR" 4 +.IX Item "-Wcomments" +.PD +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a backslash-newline appears in a \fB//\fR comment. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Warn if any trigraphs are encountered that might change the meaning of +the program. Trigraphs within comments are not warned about, +except those that would form escaped newlines. +.Sp +This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not +given, this option is still enabled unless trigraphs are enabled. To +get trigraph conversion without warnings, but get the other +\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn if an undefined identifier is evaluated in an \f(CW\*(C`#if\*(C'\fR directive. +Such identifiers are replaced with zero. +.IP "\fB\-Wexpansion\-to\-defined\fR" 4 +.IX Item "-Wexpansion-to-defined" +Warn whenever \fBdefined\fR is encountered in the expansion of a macro +(including the case where the macro is expanded by an \fB#if\fR directive). +Such usage is not portable. +This warning is also enabled by \fB\-Wpedantic\fR and \fB\-Wextra\fR. +.IP "\fB\-Wunused\-macros\fR" 4 +.IX Item "-Wunused-macros" +Warn about macros defined in the main file that are unused. A macro +is \fIused\fR if it is expanded or tested for existence at least once. +The preprocessor also warns if the macro has not been used at the +time it is redefined or undefined. +.Sp +Built-in macros, macros defined on the command line, and macros +defined in include files are not warned about. +.Sp +\&\fINote:\fR If a macro is actually used, but only used in skipped +conditional blocks, then the preprocessor reports it as unused. To avoid the +warning in such a case, you might improve the scope of the macro's +definition by, for example, moving it into the first skipped block. +Alternatively, you could provide a dummy use with something like: +.Sp +.Vb 2 +\& #if defined the_macro_causing_the_warning +\& #endif +.Ve +.IP "\fB\-Wno\-endif\-labels\fR" 4 +.IX Item "-Wno-endif-labels" +Do not warn whenever an \f(CW\*(C`#else\*(C'\fR or an \f(CW\*(C`#endif\*(C'\fR are followed by text. +This sometimes happens in older programs with code of the form +.Sp +.Vb 5 +\& #if FOO +\& ... +\& #else FOO +\& ... +\& #endif FOO +.Ve +.Sp +The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments. +This warning is on by default. +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +This section describes the environment variables that affect how \s-1CPP\s0 +operates. You can use them to specify directories or prefixes to use +when searching for include files, or to control dependency output. +.PP +Note that you can also specify places to search using options such as +\&\fB\-I\fR, and control dependency output with options like +\&\fB\-M\fR. These take precedence over +environment variables, which in turn take precedence over the +configuration of \s-1GCC.\s0 +.IP "\fB\s-1CPATH\s0\fR" 4 +.IX Item "CPATH" +.PD 0 +.IP "\fBC_INCLUDE_PATH\fR" 4 +.IX Item "C_INCLUDE_PATH" +.IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 +.IX Item "CPLUS_INCLUDE_PATH" +.IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 +.IX Item "OBJC_INCLUDE_PATH" +.PD +Each variable's value is a list of directories separated by a special +character, much like \fB\s-1PATH\s0\fR, in which to look for header files. +The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and +determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a +semicolon, and for almost all other targets it is a colon. +.Sp +\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if +specified with \fB\-I\fR, but after any paths given with \fB\-I\fR +options on the command line. This environment variable is used +regardless of which language is being preprocessed. +.Sp +The remaining environment variables apply only when preprocessing the +particular language indicated. Each specifies a list of directories +to be searched as if specified with \fB\-isystem\fR, but after any +paths given with \fB\-isystem\fR options on the command line. +.Sp +In all these variables, an empty element instructs the compiler to +search its current working directory. Empty elements can appear at the +beginning or end of a path. For instance, if the value of +\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same +effect as \fB\-I.\ \-I/special/include\fR. +.IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 +.IX Item "DEPENDENCIES_OUTPUT" +If this variable is set, its value specifies how to output +dependencies for Make based on the non-system header files processed +by the compiler. System header files are ignored in the dependency +output. +.Sp +The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in +which case the Make rules are written to that file, guessing the target +name from the source file name. Or the value can have the form +\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to +file \fIfile\fR using \fItarget\fR as the target name. +.Sp +In other words, this environment variable is equivalent to combining +the options \fB\-MM\fR and \fB\-MF\fR, +with an optional \fB\-MT\fR switch too. +.IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 +.IX Item "SUNPRO_DEPENDENCIES" +This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), +except that system header files are not ignored, so it implies +\&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the +main input file is omitted. +.IP "\fB\s-1SOURCE_DATE_EPOCH\s0\fR" 4 +.IX Item "SOURCE_DATE_EPOCH" +If this variable is set, its value specifies a \s-1UNIX\s0 timestamp to be +used in replacement of the current date and time in the \f(CW\*(C`_\|_DATE_\|_\*(C'\fR +and \f(CW\*(C`_\|_TIME_\|_\*(C'\fR macros, so that the embedded timestamps become +reproducible. +.Sp +The value of \fB\s-1SOURCE_DATE_EPOCH\s0\fR must be a \s-1UNIX\s0 timestamp, +defined as the number of seconds (excluding leap seconds) since +01 Jan 1970 00:00:00 represented in \s-1ASCII\s0; identical to the output of +\&\fB\f(CB@command\fB{date +%s\fR} on GNU/Linux and other systems that support the +\&\f(CW%s\fR extension in the \f(CW\*(C`date\*(C'\fR command. +.Sp +The value should be a known timestamp such as the last modification +time of the source or package and it should be set by the build +process. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), +\&\fIgcc\fR\|(1), and the Info entries for \fIcpp\fR and \fIgcc\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1987\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation. A copy of +the license is included in the +man page \fIgfdl\fR\|(7). +This manual contains no Invariant Sections. The Front-Cover Texts are +(a) (see below), and the Back-Cover Texts are (b) (see below). +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man1/g++.1 b/man/man1/g++.1 new file mode 100644 index 0000000000000000000000000000000000000000..f1c604aec1d8b38d8b6c8bba37d37153aa75ff44 --- /dev/null +++ b/man/man1/g++.1 @@ -0,0 +1,28260 @@ +.\" Automatically generated by Pod::Man 4.14 (Pod::Simple 3.40) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{\ +. if \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +. \} +.\} +.rr rF +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCC 1" +.TH GCC 1 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcc \- GNU project C and C++ compiler +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] + [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] + [\fB\-W\fR\fIwarn\fR...] [\fB\-Wpedantic\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] + [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...] + [\fB\-o\fR \fIoutfile\fR] [@\fIfile\fR] \fIinfile\fR... +.PP +Only the most useful options are listed here; see below for the +remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +When you invoke \s-1GCC,\s0 it normally does preprocessing, compilation, +assembly and linking. The \*(L"overall options\*(R" allow you to stop this +process at an intermediate stage. For example, the \fB\-c\fR option +says not to run the linker. Then the output consists of object files +output by the assembler. +.PP +Other options are passed on to one or more stages of processing. Some options +control the preprocessor and others the compiler itself. Yet other +options control the assembler and linker; most of these are not +documented here, since you rarely need to use any of them. +.PP +Most of the command-line options that you can use with \s-1GCC\s0 are useful +for C programs; when an option is only useful with another language +(usually \*(C+), the explanation says so explicitly. If the description +for a particular option does not mention a source language, you can use +that option with all supported languages. +.PP +The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or +\&\fImachine\fR\fB\-gcc\fR when cross-compiling, or +\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a specific version of \s-1GCC.\s0 +When you compile \*(C+ programs, you should invoke \s-1GCC\s0 as \fBg++\fR +instead. +.PP +The \fBgcc\fR program accepts options and file names as operands. Many +options have multi-letter names; therefore multiple single-letter options +may \fInot\fR be grouped: \fB\-dv\fR is very different from \fB\-d\ \-v\fR. +.PP +You can mix options and other arguments. For the most part, the order +you use doesn't matter. Order does matter when you use several +options of the same kind; for example, if you specify \fB\-L\fR more +than once, the directories are searched in the order specified. Also, +the placement of the \fB\-l\fR option is significant. +.PP +Many options have long names starting with \fB\-f\fR or with +\&\fB\-W\fR\-\-\-for example, +\&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of +these have both positive and negative forms; the negative form of +\&\fB\-ffoo\fR is \fB\-fno\-foo\fR. This manual documents +only one of these two forms, whichever one is not the default. +.PP +Some options take one or more arguments typically separated either +by a space or by the equals sign (\fB=\fR) from the option name. +Unless documented otherwise, an argument can be either numeric or +a string. Numeric arguments must typically be small unsigned decimal +or hexadecimal integers. Hexadecimal arguments must begin with +the \fB0x\fR prefix. Arguments to options that specify a size +threshold of some sort may be arbitrarily large decimal or hexadecimal +integers followed by a byte size suffix designating a multiple of bytes +such as \f(CW\*(C`kB\*(C'\fR and \f(CW\*(C`KiB\*(C'\fR for kilobyte and kibibyte, respectively, +\&\f(CW\*(C`MB\*(C'\fR and \f(CW\*(C`MiB\*(C'\fR for megabyte and mebibyte, \f(CW\*(C`GB\*(C'\fR and +\&\f(CW\*(C`GiB\*(C'\fR for gigabyte and gigibyte, and so on. Such arguments are +designated by \fIbyte-size\fR in the following text. Refer to the \s-1NIST, +IEC,\s0 and other relevant national and international standards for the full +listing and explanation of the binary and decimal byte size prefixes. +.SH "OPTIONS" +.IX Header "OPTIONS" +.SS "Option Summary" +.IX Subsection "Option Summary" +Here is a summary of all the options, grouped by type. Explanations are +in the following sections. +.IP "\fIOverall Options\fR" 4 +.IX Item "Overall Options" +\&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-x\fR \fIlanguage\fR +\&\fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \-\-version +\&\-pass\-exit\-codes \-pipe \-specs=\fR\fIfile\fR \fB\-wrapper +@\fR\fIfile\fR \fB\-ffile\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR +\&\fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +.IP "\fIC Language Options\fR" 4 +.IX Item "C Language Options" +\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline +\&\-fpermitted\-flt\-eval\-methods=\fR\fIstandard\fR +\&\fB\-aux\-info\fR \fIfilename\fR \fB\-fallow\-parameterless\-variadic\-functions +\&\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR \fB\-fgimple +\&\-fhosted \-ffreestanding +\&\-fopenacc \-fopenacc\-dim=\fR\fIgeom\fR +\&\fB\-fopenmp \-fopenmp\-simd +\&\-fms\-extensions \-fplan9\-extensions \-fsso\-struct=\fR\fIendianness\fR +\&\fB\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions +\&\-fsigned\-bitfields \-fsigned\-char +\&\-funsigned\-bitfields \-funsigned\-char\fR +.IP "\fI\*(C+ Language Options\fR" 4 +.IX Item " Language Options" +\&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control +\&\-faligned\-new=\fR\fIn\fR \fB\-fargs\-in\-order=\fR\fIn\fR \fB\-fchar8_t \-fcheck\-new +\&\-fconstexpr\-depth=\fR\fIn\fR \fB\-fconstexpr\-loop\-limit=\fR\fIn\fR +\&\fB\-fconstexpr\-ops\-limit=\fR\fIn\fR \fB\-fno\-elide\-constructors +\&\-fno\-enforce\-eh\-specs +\&\-fno\-gnu\-keywords +\&\-fno\-implicit\-templates +\&\-fno\-implicit\-inline\-templates +\&\-fno\-implement\-inlines \-fms\-extensions +\&\-fnew\-inheriting\-ctors +\&\-fnew\-ttp\-matching +\&\-fno\-nonansi\-builtins \-fnothrow\-opt \-fno\-operator\-names +\&\-fno\-optional\-diags \-fpermissive +\&\-fno\-pretty\-templates +\&\-frepo \-fno\-rtti \-fsized\-deallocation +\&\-ftemplate\-backtrace\-limit=\fR\fIn\fR +\&\fB\-ftemplate\-depth=\fR\fIn\fR +\&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit +\&\-fno\-weak \-nostdinc++ +\&\-fvisibility\-inlines\-hidden +\&\-fvisibility\-ms\-compat +\&\-fext\-numeric\-literals +\&\-Wabi=\fR\fIn\fR \fB\-Wabi\-tag \-Wconversion\-null \-Wctor\-dtor\-privacy +\&\-Wdelete\-non\-virtual\-dtor \-Wdeprecated\-copy \-Wdeprecated\-copy\-dtor +\&\-Wliteral\-suffix +\&\-Wmultiple\-inheritance \-Wno\-init\-list\-lifetime +\&\-Wnamespaces \-Wnarrowing +\&\-Wpessimizing\-move \-Wredundant\-move +\&\-Wnoexcept \-Wnoexcept\-type \-Wclass\-memaccess +\&\-Wnon\-virtual\-dtor \-Wreorder \-Wregister +\&\-Weffc++ \-Wstrict\-null\-sentinel \-Wtemplates +\&\-Wno\-non\-template\-friend \-Wold\-style\-cast +\&\-Woverloaded\-virtual \-Wno\-pmf\-conversions +\&\-Wno\-class\-conversion \-Wno\-terminate +\&\-Wsign\-promo \-Wvirtual\-inheritance\fR +.IP "\fIObjective-C and Objective\-\*(C+ Language Options\fR" 4 +.IX Item "Objective-C and Objective- Language Options" +\&\fB\-fconstant\-string\-class=\fR\fIclass-name\fR +\&\fB\-fgnu\-runtime \-fnext\-runtime +\&\-fno\-nil\-receivers +\&\-fobjc\-abi\-version=\fR\fIn\fR +\&\fB\-fobjc\-call\-cxx\-cdtors +\&\-fobjc\-direct\-dispatch +\&\-fobjc\-exceptions +\&\-fobjc\-gc +\&\-fobjc\-nilcheck +\&\-fobjc\-std=objc1 +\&\-fno\-local\-ivars +\&\-fivar\-visibility=\fR[\fBpublic\fR|\fBprotected\fR|\fBprivate\fR|\fBpackage\fR] +\&\fB\-freplace\-objc\-classes +\&\-fzero\-link +\&\-gen\-decls +\&\-Wassign\-intercept +\&\-Wno\-protocol \-Wselector +\&\-Wstrict\-selector\-match +\&\-Wundeclared\-selector\fR +.IP "\fIDiagnostic Message Formatting Options\fR" 4 +.IX Item "Diagnostic Message Formatting Options" +\&\fB\-fmessage\-length=\fR\fIn\fR +\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR] +\&\fB\-fdiagnostics\-color=\fR[\fBauto\fR|\fBnever\fR|\fBalways\fR] +\&\fB\-fdiagnostics\-format=\fR[\fBtext\fR|\fBjson\fR] +\&\fB\-fno\-diagnostics\-show\-option \-fno\-diagnostics\-show\-caret +\&\-fno\-diagnostics\-show\-labels \-fno\-diagnostics\-show\-line\-numbers +\&\-fdiagnostics\-minimum\-margin\-width=\fR\fIwidth\fR +\&\fB\-fdiagnostics\-parseable\-fixits \-fdiagnostics\-generate\-patch +\&\-fdiagnostics\-show\-template\-tree \-fno\-elide\-type +\&\-fno\-show\-column\fR +.IP "\fIWarning Options\fR" 4 +.IX Item "Warning Options" +\&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-Wpedantic +\&\-pedantic\-errors +\&\-w \-Wextra \-Wall \-Waddress \-Waddress\-of\-packed\-member +\&\-Waggregate\-return \-Waligned\-new +\&\-Walloc\-zero \-Walloc\-size\-larger\-than=\fR\fIbyte-size\fR +\&\fB\-Walloca \-Walloca\-larger\-than=\fR\fIbyte-size\fR +\&\fB\-Wno\-aggressive\-loop\-optimizations \-Warray\-bounds \-Warray\-bounds=\fR\fIn\fR +\&\fB\-Wno\-attributes \-Wattribute\-alias=\fR\fIn\fR +\&\fB\-Wbool\-compare \-Wbool\-operation +\&\-Wno\-builtin\-declaration\-mismatch +\&\-Wno\-builtin\-macro\-redefined \-Wc90\-c99\-compat \-Wc99\-c11\-compat +\&\-Wc11\-c2x\-compat +\&\-Wc++\-compat \-Wc++11\-compat \-Wc++14\-compat \-Wc++17\-compat +\&\-Wcast\-align \-Wcast\-align=strict \-Wcast\-function\-type \-Wcast\-qual +\&\-Wchar\-subscripts \-Wcatch\-value \-Wcatch\-value=\fR\fIn\fR +\&\fB\-Wclobbered \-Wcomment \-Wconditionally\-supported +\&\-Wconversion \-Wcoverage\-mismatch \-Wno\-cpp \-Wdangling\-else \-Wdate\-time +\&\-Wdelete\-incomplete +\&\-Wno\-attribute\-warning +\&\-Wno\-deprecated \-Wno\-deprecated\-declarations \-Wno\-designated\-init +\&\-Wdisabled\-optimization +\&\-Wno\-discarded\-qualifiers \-Wno\-discarded\-array\-qualifiers +\&\-Wno\-div\-by\-zero \-Wdouble\-promotion +\&\-Wduplicated\-branches \-Wduplicated\-cond +\&\-Wempty\-body \-Wenum\-compare \-Wno\-endif\-labels \-Wexpansion\-to\-defined +\&\-Werror \-Werror=* \-Wextra\-semi \-Wfatal\-errors +\&\-Wfloat\-equal \-Wformat \-Wformat=2 +\&\-Wno\-format\-contains\-nul \-Wno\-format\-extra\-args +\&\-Wformat\-nonliteral \-Wformat\-overflow=\fR\fIn\fR +\&\fB\-Wformat\-security \-Wformat\-signedness \-Wformat\-truncation=\fR\fIn\fR +\&\fB\-Wformat\-y2k \-Wframe\-address +\&\-Wframe\-larger\-than=\fR\fIbyte-size\fR \fB\-Wno\-free\-nonheap\-object +\&\-Wjump\-misses\-init +\&\-Whsa \-Wif\-not\-aligned +\&\-Wignored\-qualifiers \-Wignored\-attributes \-Wincompatible\-pointer\-types +\&\-Wimplicit \-Wimplicit\-fallthrough \-Wimplicit\-fallthrough=\fR\fIn\fR +\&\fB\-Wimplicit\-function\-declaration \-Wimplicit\-int +\&\-Winit\-self \-Winline \-Wno\-int\-conversion \-Wint\-in\-bool\-context +\&\-Wno\-int\-to\-pointer\-cast \-Winvalid\-memory\-model \-Wno\-invalid\-offsetof +\&\-Winvalid\-pch \-Wlarger\-than=\fR\fIbyte-size\fR +\&\fB\-Wlogical\-op \-Wlogical\-not\-parentheses \-Wlong\-long +\&\-Wmain \-Wmaybe\-uninitialized \-Wmemset\-elt\-size \-Wmemset\-transposed\-args +\&\-Wmisleading\-indentation \-Wmissing\-attributes \-Wmissing\-braces +\&\-Wmissing\-field\-initializers \-Wmissing\-format\-attribute +\&\-Wmissing\-include\-dirs \-Wmissing\-noreturn \-Wmissing\-profile +\&\-Wno\-multichar \-Wmultistatement\-macros \-Wnonnull \-Wnonnull\-compare +\&\-Wnormalized=\fR[\fBnone\fR|\fBid\fR|\fBnfc\fR|\fBnfkc\fR] +\&\fB\-Wnull\-dereference \-Wodr \-Wno\-overflow \-Wopenmp\-simd +\&\-Woverride\-init\-side\-effects \-Woverlength\-strings +\&\-Wpacked \-Wpacked\-bitfield\-compat \-Wpacked\-not\-aligned \-Wpadded +\&\-Wparentheses \-Wno\-pedantic\-ms\-format +\&\-Wplacement\-new \-Wplacement\-new=\fR\fIn\fR +\&\fB\-Wpointer\-arith \-Wpointer\-compare \-Wno\-pointer\-to\-int\-cast +\&\-Wno\-pragmas \-Wno\-prio\-ctor\-dtor \-Wredundant\-decls +\&\-Wrestrict \-Wno\-return\-local\-addr +\&\-Wreturn\-type \-Wsequence\-point \-Wshadow \-Wno\-shadow\-ivar +\&\-Wshadow=global, \-Wshadow=local, \-Wshadow=compatible\-local +\&\-Wshift\-overflow \-Wshift\-overflow=\fR\fIn\fR +\&\fB\-Wshift\-count\-negative \-Wshift\-count\-overflow \-Wshift\-negative\-value +\&\-Wsign\-compare \-Wsign\-conversion \-Wfloat\-conversion +\&\-Wno\-scalar\-storage\-order \-Wsizeof\-pointer\-div +\&\-Wsizeof\-pointer\-memaccess \-Wsizeof\-array\-argument +\&\-Wstack\-protector \-Wstack\-usage=\fR\fIbyte-size\fR \fB\-Wstrict\-aliasing +\&\-Wstrict\-aliasing=n \-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR +\&\fB\-Wstringop\-overflow=\fR\fIn\fR \fB\-Wstringop\-truncation \-Wsubobject\-linkage +\&\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR|\fBformat\fR|\fBmalloc\fR] +\&\fB\-Wsuggest\-final\-types \-Wsuggest\-final\-methods \-Wsuggest\-override +\&\-Wswitch \-Wswitch\-bool \-Wswitch\-default \-Wswitch\-enum +\&\-Wswitch\-unreachable \-Wsync\-nand +\&\-Wsystem\-headers \-Wtautological\-compare \-Wtrampolines \-Wtrigraphs +\&\-Wtype\-limits \-Wundef +\&\-Wuninitialized \-Wunknown\-pragmas +\&\-Wunsuffixed\-float\-constants \-Wunused \-Wunused\-function +\&\-Wunused\-label \-Wunused\-local\-typedefs \-Wunused\-macros +\&\-Wunused\-parameter \-Wno\-unused\-result +\&\-Wunused\-value \-Wunused\-variable +\&\-Wunused\-const\-variable \-Wunused\-const\-variable=\fR\fIn\fR +\&\fB\-Wunused\-but\-set\-parameter \-Wunused\-but\-set\-variable +\&\-Wuseless\-cast \-Wvariadic\-macros \-Wvector\-operation\-performance +\&\-Wvla \-Wvla\-larger\-than=\fR\fIbyte-size\fR \fB\-Wvolatile\-register\-var +\&\-Wwrite\-strings +\&\-Wzero\-as\-null\-pointer\-constant\fR +.IP "\fIC and Objective-C-only Warning Options\fR" 4 +.IX Item "C and Objective-C-only Warning Options" +\&\fB\-Wbad\-function\-cast \-Wmissing\-declarations +\&\-Wmissing\-parameter\-type \-Wmissing\-prototypes \-Wnested\-externs +\&\-Wold\-style\-declaration \-Wold\-style\-definition +\&\-Wstrict\-prototypes \-Wtraditional \-Wtraditional\-conversion +\&\-Wdeclaration\-after\-statement \-Wpointer\-sign\fR +.IP "\fIDebugging Options\fR" 4 +.IX Item "Debugging Options" +\&\fB\-g \-g\fR\fIlevel\fR \fB\-gdwarf \-gdwarf\-\fR\fIversion\fR +\&\fB\-ggdb \-grecord\-gcc\-switches \-gno\-record\-gcc\-switches +\&\-gstabs \-gstabs+ \-gstrict\-dwarf \-gno\-strict\-dwarf +\&\-gas\-loc\-support \-gno\-as\-loc\-support +\&\-gas\-locview\-support \-gno\-as\-locview\-support +\&\-gcolumn\-info \-gno\-column\-info +\&\-gstatement\-frontiers \-gno\-statement\-frontiers +\&\-gvariable\-location\-views \-gno\-variable\-location\-views +\&\-ginternal\-reset\-location\-views \-gno\-internal\-reset\-location\-views +\&\-ginline\-points \-gno\-inline\-points +\&\-gvms \-gxcoff \-gxcoff+ \-gz\fR[\fB=\fR\fItype\fR] +\&\fB\-gsplit\-dwarf \-gdescribe\-dies \-gno\-describe\-dies +\&\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR \fB\-fdebug\-types\-section +\&\-fno\-eliminate\-unused\-debug\-types +\&\-femit\-struct\-debug\-baseonly \-femit\-struct\-debug\-reduced +\&\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR] +\&\fB\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always +\&\-fno\-merge\-debug\-strings \-fno\-dwarf2\-cfi\-asm +\&\-fvar\-tracking \-fvar\-tracking\-assignments\fR +.IP "\fIOptimization Options\fR" 4 +.IX Item "Optimization Options" +\&\fB\-faggressive\-loop\-optimizations +\&\-falign\-functions[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-falign\-jumps[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-falign\-labels[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-falign\-loops[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-fassociative\-math \-fauto\-profile \-fauto\-profile[=\fR\fIpath\fR\fB] +\&\-fauto\-inc\-dec \-fbranch\-probabilities +\&\-fbranch\-target\-load\-optimize \-fbranch\-target\-load\-optimize2 +\&\-fbtr\-bb\-exclusive \-fcaller\-saves +\&\-fcombine\-stack\-adjustments \-fconserve\-stack +\&\-fcompare\-elim \-fcprop\-registers \-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fcx\-fortran\-rules +\&\-fcx\-limited\-range +\&\-fdata\-sections \-fdce \-fdelayed\-branch +\&\-fdelete\-null\-pointer\-checks \-fdevirtualize \-fdevirtualize\-speculatively +\&\-fdevirtualize\-at\-ltrans \-fdse +\&\-fearly\-inlining \-fipa\-sra \-fexpensive\-optimizations \-ffat\-lto\-objects +\&\-ffast\-math \-ffinite\-math\-only \-ffloat\-store \-fexcess\-precision=\fR\fIstyle\fR +\&\fB\-fforward\-propagate \-ffp\-contract=\fR\fIstyle\fR \fB\-ffunction\-sections +\&\-fgcse \-fgcse\-after\-reload \-fgcse\-las \-fgcse\-lm \-fgraphite\-identity +\&\-fgcse\-sm \-fhoist\-adjacent\-loads \-fif\-conversion +\&\-fif\-conversion2 \-findirect\-inlining +\&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR +\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone +\&\-fipa\-bit\-cp \-fipa\-vrp \-fipa\-pta \-fipa\-profile \-fipa\-pure\-const +\&\-fipa\-reference \-fipa\-reference\-addressable +\&\-fipa\-stack\-alignment \-fipa\-icf \-fira\-algorithm=\fR\fIalgorithm\fR +\&\fB\-flive\-patching=\fR\fIlevel\fR +\&\fB\-fira\-region=\fR\fIregion\fR \fB\-fira\-hoist\-pressure +\&\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots +\&\-fno\-ira\-share\-spill\-slots +\&\-fisolate\-erroneous\-paths\-dereference \-fisolate\-erroneous\-paths\-attribute +\&\-fivopts \-fkeep\-inline\-functions \-fkeep\-static\-functions +\&\-fkeep\-static\-consts \-flimit\-function\-alignment \-flive\-range\-shrinkage +\&\-floop\-block \-floop\-interchange \-floop\-strip\-mine +\&\-floop\-unroll\-and\-jam \-floop\-nest\-optimize +\&\-floop\-parallelize\-all \-flra\-remat \-flto \-flto\-compression\-level +\&\-flto\-partition=\fR\fIalg\fR \fB\-fmerge\-all\-constants +\&\-fmerge\-constants \-fmodulo\-sched \-fmodulo\-sched\-allow\-regmoves +\&\-fmove\-loop\-invariants \-fno\-branch\-count\-reg +\&\-fno\-defer\-pop \-fno\-fp\-int\-builtin\-inexact \-fno\-function\-cse +\&\-fno\-guess\-branch\-probability \-fno\-inline \-fno\-math\-errno \-fno\-peephole +\&\-fno\-peephole2 \-fno\-printf\-return\-value \-fno\-sched\-interblock +\&\-fno\-sched\-spec \-fno\-signed\-zeros +\&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss +\&\-fomit\-frame\-pointer \-foptimize\-sibling\-calls +\&\-fpartial\-inlining \-fpeel\-loops \-fpredictive\-commoning +\&\-fprefetch\-loop\-arrays +\&\-fprofile\-correction +\&\-fprofile\-use \-fprofile\-use=\fR\fIpath\fR \fB\-fprofile\-values +\&\-fprofile\-reorder\-functions +\&\-freciprocal\-math \-free \-frename\-registers \-freorder\-blocks +\&\-freorder\-blocks\-algorithm=\fR\fIalgorithm\fR +\&\fB\-freorder\-blocks\-and\-partition \-freorder\-functions +\&\-frerun\-cse\-after\-loop \-freschedule\-modulo\-scheduled\-loops +\&\-frounding\-math \-fsave\-optimization\-record +\&\-fsched2\-use\-superblocks \-fsched\-pressure +\&\-fsched\-spec\-load \-fsched\-spec\-load\-dangerous +\&\-fsched\-stalled\-insns\-dep[=\fR\fIn\fR\fB] \-fsched\-stalled\-insns[=\fR\fIn\fR\fB] +\&\-fsched\-group\-heuristic \-fsched\-critical\-path\-heuristic +\&\-fsched\-spec\-insn\-heuristic \-fsched\-rank\-heuristic +\&\-fsched\-last\-insn\-heuristic \-fsched\-dep\-count\-heuristic +\&\-fschedule\-fusion +\&\-fschedule\-insns \-fschedule\-insns2 \-fsection\-anchors +\&\-fselective\-scheduling \-fselective\-scheduling2 +\&\-fsel\-sched\-pipelining \-fsel\-sched\-pipelining\-outer\-loops +\&\-fsemantic\-interposition \-fshrink\-wrap \-fshrink\-wrap\-separate +\&\-fsignaling\-nans +\&\-fsingle\-precision\-constant \-fsplit\-ivs\-in\-unroller \-fsplit\-loops +\&\-fsplit\-paths +\&\-fsplit\-wide\-types \-fssa\-backprop \-fssa\-phiopt +\&\-fstdarg\-opt \-fstore\-merging \-fstrict\-aliasing +\&\-fthread\-jumps \-ftracer \-ftree\-bit\-ccp +\&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch +\&\-ftree\-coalesce\-vars \-ftree\-copy\-prop \-ftree\-dce \-ftree\-dominator\-opts +\&\-ftree\-dse \-ftree\-forwprop \-ftree\-fre \-fcode\-hoisting +\&\-ftree\-loop\-if\-convert \-ftree\-loop\-im +\&\-ftree\-phiprop \-ftree\-loop\-distribution \-ftree\-loop\-distribute\-patterns +\&\-ftree\-loop\-ivcanon \-ftree\-loop\-linear \-ftree\-loop\-optimize +\&\-ftree\-loop\-vectorize +\&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-partial\-pre \-ftree\-pta +\&\-ftree\-reassoc \-ftree\-scev\-cprop \-ftree\-sink \-ftree\-slsr \-ftree\-sra +\&\-ftree\-switch\-conversion \-ftree\-tail\-merge +\&\-ftree\-ter \-ftree\-vectorize \-ftree\-vrp \-funconstrained\-commons +\&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops +\&\-funsafe\-math\-optimizations \-funswitch\-loops +\&\-fipa\-ra \-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt +\&\-fweb \-fwhole\-program \-fwpa \-fuse\-linker\-plugin +\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR +\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast \-Og\fR +.IP "\fIProgram Instrumentation Options\fR" 4 +.IX Item "Program Instrumentation Options" +\&\fB\-p \-pg \-fprofile\-arcs \-\-coverage \-ftest\-coverage +\&\-fprofile\-abs\-path +\&\-fprofile\-dir=\fR\fIpath\fR \fB\-fprofile\-generate \-fprofile\-generate=\fR\fIpath\fR +\&\fB\-fprofile\-update=\fR\fImethod\fR \fB\-fprofile\-filter\-files=\fR\fIregex\fR +\&\fB\-fprofile\-exclude\-files=\fR\fIregex\fR +\&\fB\-fsanitize=\fR\fIstyle\fR \fB\-fsanitize\-recover \-fsanitize\-recover=\fR\fIstyle\fR +\&\fB\-fasan\-shadow\-offset=\fR\fInumber\fR \fB\-fsanitize\-sections=\fR\fIs1\fR\fB,\fR\fIs2\fR\fB,... +\&\-fsanitize\-undefined\-trap\-on\-error \-fbounds\-check +\&\-fcf\-protection=\fR[\fBfull\fR|\fBbranch\fR|\fBreturn\fR|\fBnone\fR] +\&\fB\-fstack\-protector \-fstack\-protector\-all \-fstack\-protector\-strong +\&\-fstack\-protector\-explicit \-fstack\-check +\&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR +\&\fB\-fno\-stack\-limit \-fsplit\-stack +\&\-fvtable\-verify=\fR[\fBstd\fR|\fBpreinit\fR|\fBnone\fR] +\&\fB\-fvtv\-counts \-fvtv\-debug +\&\-finstrument\-functions +\&\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,... +\&\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR +.IP "\fIPreprocessor Options\fR" 4 +.IX Item "Preprocessor Options" +\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR +\&\fB\-A\-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] +\&\fB\-C \-CC \-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR] +\&\fB\-dD \-dI \-dM \-dN \-dU +\&\-fdebug\-cpp \-fdirectives\-only \-fdollars\-in\-identifiers +\&\-fexec\-charset=\fR\fIcharset\fR \fB\-fextended\-identifiers +\&\-finput\-charset=\fR\fIcharset\fR \fB\-fmacro\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR +\&\fB\-fno\-canonical\-system\-headers \-fpch\-deps \-fpch\-preprocess +\&\-fpreprocessed \-ftabstop=\fR\fIwidth\fR \fB\-ftrack\-macro\-expansion +\&\-fwide\-exec\-charset=\fR\fIcharset\fR \fB\-fworking\-directory +\&\-H \-imacros\fR \fIfile\fR \fB\-include\fR \fIfile\fR +\&\fB\-M \-MD \-MF \-MG \-MM \-MMD \-MP \-MQ \-MT +\&\-no\-integrated\-cpp \-P \-pthread \-remap +\&\-traditional \-traditional\-cpp \-trigraphs +\&\-U\fR\fImacro\fR \fB\-undef +\&\-Wp,\fR\fIoption\fR \fB\-Xpreprocessor\fR \fIoption\fR +.IP "\fIAssembler Options\fR" 4 +.IX Item "Assembler Options" +\&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR +.IP "\fILinker Options\fR" 4 +.IX Item "Linker Options" +\&\fIobject-file-name\fR \fB\-fuse\-ld=\fR\fIlinker\fR \fB\-l\fR\fIlibrary\fR +\&\fB\-nostartfiles \-nodefaultlibs \-nolibc \-nostdlib +\&\-e\fR \fIentry\fR \fB\-\-entry=\fR\fIentry\fR +\&\fB\-pie \-pthread \-r \-rdynamic +\&\-s \-static \-static\-pie \-static\-libgcc \-static\-libstdc++ +\&\-static\-libasan \-static\-libtsan \-static\-liblsan \-static\-libubsan +\&\-shared \-shared\-libgcc \-symbolic +\&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR +\&\fB\-u\fR \fIsymbol\fR \fB\-z\fR \fIkeyword\fR +.IP "\fIDirectory Options\fR" 4 +.IX Item "Directory Options" +\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-I\- +\&\-idirafter\fR \fIdir\fR +\&\fB\-imacros\fR \fIfile\fR \fB\-imultilib\fR \fIdir\fR +\&\fB\-iplugindir=\fR\fIdir\fR \fB\-iprefix\fR \fIfile\fR +\&\fB\-iquote\fR \fIdir\fR \fB\-isysroot\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR +\&\fB\-iwithprefix\fR \fIdir\fR \fB\-iwithprefixbefore\fR \fIdir\fR +\&\fB\-L\fR\fIdir\fR \fB\-no\-canonical\-prefixes \-\-no\-sysroot\-suffix +\&\-nostdinc \-nostdinc++ \-\-sysroot=\fR\fIdir\fR +.IP "\fICode Generation Options\fR" 4 +.IX Item "Code Generation Options" +\&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR +\&\fB\-ffixed\-\fR\fIreg\fR \fB\-fexceptions +\&\-fnon\-call\-exceptions \-fdelete\-dead\-exceptions \-funwind\-tables +\&\-fasynchronous\-unwind\-tables +\&\-fno\-gnu\-unique +\&\-finhibit\-size\-directive \-fno\-common \-fno\-ident +\&\-fpcc\-struct\-return \-fpic \-fPIC \-fpie \-fPIE \-fno\-plt +\&\-fno\-jump\-tables +\&\-frecord\-gcc\-switches +\&\-freg\-struct\-return \-fshort\-enums \-fshort\-wchar +\&\-fverbose\-asm \-fpack\-struct[=\fR\fIn\fR\fB] +\&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR +\&\fB\-fstack\-reuse=\fR\fIreuse_level\fR +\&\fB\-ftrampolines \-ftrapv \-fwrapv +\&\-fvisibility=\fR[\fBdefault\fR|\fBinternal\fR|\fBhidden\fR|\fBprotected\fR] +\&\fB\-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR +.IP "\fIDeveloper Options\fR" 4 +.IX Item "Developer Options" +\&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion +\&\-dumpfullversion \-fchecking \-fchecking=\fR\fIn\fR \fB\-fdbg\-cnt\-list +\&\-fdbg\-cnt=\fR\fIcounter-value-list\fR +\&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdisable\-tree\-\fR\fIpass_name\fR +\&\fB\-fdisable\-tree\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdump\-debug \-fdump\-earlydebug +\&\-fdump\-noaddr \-fdump\-unnumbered \-fdump\-unnumbered\-links +\&\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR] +\&\fB\-fdump\-ipa\-all \-fdump\-ipa\-cgraph \-fdump\-ipa\-inline +\&\-fdump\-lang\-all +\&\-fdump\-lang\-\fR\fIswitch\fR +\&\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR +\&\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR +\&\fB\-fdump\-passes +\&\-fdump\-rtl\-\fR\fIpass\fR \fB\-fdump\-rtl\-\fR\fIpass\fR\fB=\fR\fIfilename\fR +\&\fB\-fdump\-statistics +\&\-fdump\-tree\-all +\&\-fdump\-tree\-\fR\fIswitch\fR +\&\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR +\&\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR +\&\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR] \fB\-fcompare\-debug\-second +\&\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR +\&\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR +\&\fB\-fira\-verbose=\fR\fIn\fR +\&\fB\-flto\-report \-flto\-report\-wpa \-fmem\-report\-wpa +\&\-fmem\-report \-fpre\-ipa\-mem\-report \-fpost\-ipa\-mem\-report +\&\-fopt\-info \-fopt\-info\-\fR\fIoptions\fR[\fB=\fR\fIfile\fR] +\&\fB\-fprofile\-report +\&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR +\&\fB\-fsel\-sched\-verbose \-fsel\-sched\-dump\-cfg \-fsel\-sched\-pipelining\-verbose +\&\-fstats \-fstack\-usage \-ftime\-report \-ftime\-report\-details +\&\-fvar\-tracking\-assignments\-toggle \-gtoggle +\&\-print\-file\-name=\fR\fIlibrary\fR \fB\-print\-libgcc\-file\-name +\&\-print\-multi\-directory \-print\-multi\-lib \-print\-multi\-os\-directory +\&\-print\-prog\-name=\fR\fIprogram\fR \fB\-print\-search\-dirs \-Q +\&\-print\-sysroot \-print\-sysroot\-headers\-suffix +\&\-save\-temps \-save\-temps=cwd \-save\-temps=obj \-time\fR[\fB=\fR\fIfile\fR] +.IP "\fIMachine-Dependent Options\fR" 4 +.IX Item "Machine-Dependent Options" +\&\fIAArch64 Options\fR +\&\fB\-mabi=\fR\fIname\fR \fB\-mbig\-endian \-mlittle\-endian +\&\-mgeneral\-regs\-only +\&\-mcmodel=tiny \-mcmodel=small \-mcmodel=large +\&\-mstrict\-align \-mno\-strict\-align +\&\-momit\-leaf\-frame\-pointer +\&\-mtls\-dialect=desc \-mtls\-dialect=traditional +\&\-mtls\-size=\fR\fIsize\fR +\&\fB\-mfix\-cortex\-a53\-835769 \-mfix\-cortex\-a53\-843419 +\&\-mlow\-precision\-recip\-sqrt \-mlow\-precision\-sqrt \-mlow\-precision\-div +\&\-mpc\-relative\-literal\-loads +\&\-msign\-return\-address=\fR\fIscope\fR +\&\fB\-mbranch\-protection=\fR\fInone\fR\fB|\fR\fIstandard\fR\fB|\fR\fIpac-ret\fR\fB[+\fR\fIleaf\fR\fB]|\fR\fIbti\fR +\&\fB\-mharden\-sls=\fR\fIopts\fR +\&\fB\-march=\fR\fIname\fR \fB\-mcpu=\fR\fIname\fR \fB\-mtune=\fR\fIname\fR +\&\fB\-moverride=\fR\fIstring\fR \fB\-mverbose\-cost\-dump +\&\-mstack\-protector\-guard=\fR\fIguard\fR \fB\-mstack\-protector\-guard\-reg=\fR\fIsysreg\fR +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR \fB\-mtrack\-speculation +\&\-moutline\-atomics\fR +.Sp +\&\fIAdapteva Epiphany Options\fR +\&\fB\-mhalf\-reg\-file \-mprefer\-short\-insn\-regs +\&\-mbranch\-cost=\fR\fInum\fR \fB\-mcmove \-mnops=\fR\fInum\fR \fB\-msoft\-cmpsf +\&\-msplit\-lohi \-mpost\-inc \-mpost\-modify \-mstack\-offset=\fR\fInum\fR +\&\fB\-mround\-nearest \-mlong\-calls \-mshort\-calls \-msmall16 +\&\-mfp\-mode=\fR\fImode\fR \fB\-mvect\-double \-max\-vect\-align=\fR\fInum\fR +\&\fB\-msplit\-vecmove\-early \-m1reg\-\fR\fIreg\fR +.Sp +\&\fI\s-1AMD GCN\s0 Options\fR +\&\fB\-march=\fR\fIgpu\fR \fB\-mtune=\fR\fIgpu\fR \fB\-mstack\-size=\fR\fIbytes\fR +.Sp +\&\fI\s-1ARC\s0 Options\fR +\&\fB\-mbarrel\-shifter \-mjli\-always +\&\-mcpu=\fR\fIcpu\fR \fB\-mA6 \-mARC600 \-mA7 \-mARC700 +\&\-mdpfp \-mdpfp\-compact \-mdpfp\-fast \-mno\-dpfp\-lrsr +\&\-mea \-mno\-mpy \-mmul32x16 \-mmul64 \-matomic +\&\-mnorm \-mspfp \-mspfp\-compact \-mspfp\-fast \-msimd \-msoft\-float \-mswap +\&\-mcrc \-mdsp\-packa \-mdvbf \-mlock \-mmac\-d16 \-mmac\-24 \-mrtsc \-mswape +\&\-mtelephony \-mxy \-misize \-mannotate\-align \-marclinux \-marclinux_prof +\&\-mlong\-calls \-mmedium\-calls \-msdata \-mirq\-ctrl\-saved +\&\-mrgf\-banked\-regs \-mlpc\-width=\fR\fIwidth\fR \fB\-G\fR \fInum\fR +\&\fB\-mvolatile\-cache \-mtp\-regno=\fR\fIregno\fR +\&\fB\-malign\-call \-mauto\-modify\-reg \-mbbit\-peephole \-mno\-brcc +\&\-mcase\-vector\-pcrel \-mcompact\-casesi \-mno\-cond\-exec \-mearly\-cbranchsi +\&\-mexpand\-adddi \-mindexed\-loads \-mlra \-mlra\-priority\-none +\&\-mlra\-priority\-compact mlra-priority-noncompact \-mmillicode +\&\-mmixed\-code \-mq\-class \-mRcq \-mRcw \-msize\-level=\fR\fIlevel\fR +\&\fB\-mtune=\fR\fIcpu\fR \fB\-mmultcost=\fR\fInum\fR \fB\-mcode\-density\-frame +\&\-munalign\-prob\-threshold=\fR\fIprobability\fR \fB\-mmpy\-option=\fR\fImulto\fR +\&\fB\-mdiv\-rem \-mcode\-density \-mll64 \-mfpu=\fR\fIfpu\fR \fB\-mrf16 \-mbranch\-index\fR +.Sp +\&\fI\s-1ARM\s0 Options\fR +\&\fB\-mapcs\-frame \-mno\-apcs\-frame +\&\-mabi=\fR\fIname\fR +\&\fB\-mapcs\-stack\-check \-mno\-apcs\-stack\-check +\&\-mapcs\-reentrant \-mno\-apcs\-reentrant +\&\-mgeneral\-regs\-only +\&\-msched\-prolog \-mno\-sched\-prolog +\&\-mlittle\-endian \-mbig\-endian +\&\-mbe8 \-mbe32 +\&\-mfloat\-abi=\fR\fIname\fR +\&\fB\-mfp16\-format=\fR\fIname\fR +\&\fB\-mthumb\-interwork \-mno\-thumb\-interwork +\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR +\&\fB\-mtune=\fR\fIname\fR \fB\-mprint\-tune\-info +\&\-mstructure\-size\-boundary=\fR\fIn\fR +\&\fB\-mabort\-on\-noreturn +\&\-mlong\-calls \-mno\-long\-calls +\&\-msingle\-pic\-base \-mno\-single\-pic\-base +\&\-mpic\-register=\fR\fIreg\fR +\&\fB\-mnop\-fun\-dllimport +\&\-mpoke\-function\-name +\&\-mthumb \-marm \-mflip\-thumb +\&\-mtpcs\-frame \-mtpcs\-leaf\-frame +\&\-mcaller\-super\-interworking \-mcallee\-super\-interworking +\&\-mtp=\fR\fIname\fR \fB\-mtls\-dialect=\fR\fIdialect\fR +\&\fB\-mword\-relocations +\&\-mfix\-cortex\-m3\-ldrd +\&\-munaligned\-access +\&\-mneon\-for\-64bits +\&\-mslow\-flash\-data +\&\-masm\-syntax\-unified +\&\-mrestrict\-it +\&\-mverbose\-cost\-dump +\&\-mpure\-code +\&\-mcmse\fR +.Sp +\&\fI\s-1AVR\s0 Options\fR +\&\fB\-mmcu=\fR\fImcu\fR \fB\-mabsdata \-maccumulate\-args +\&\-mbranch\-cost=\fR\fIcost\fR +\&\fB\-mcall\-prologues \-mgas\-isr\-prologues \-mint8 +\&\-mn_flash=\fR\fIsize\fR \fB\-mno\-interrupts +\&\-mmain\-is\-OS_task \-mrelax \-mrmw \-mstrict\-X \-mtiny\-stack +\&\-mfract\-convert\-truncate +\&\-mshort\-calls \-nodevicelib \-nodevicespecs +\&\-Waddr\-space\-convert \-Wmisspelled\-isr\fR +.Sp +\&\fIBlackfin Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR] +\&\fB\-msim \-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer +\&\-mspecld\-anomaly \-mno\-specld\-anomaly \-mcsync\-anomaly \-mno\-csync\-anomaly +\&\-mlow\-64k \-mno\-low64k \-mstack\-check\-l1 \-mid\-shared\-library +\&\-mno\-id\-shared\-library \-mshared\-library\-id=\fR\fIn\fR +\&\fB\-mleaf\-id\-shared\-library \-mno\-leaf\-id\-shared\-library +\&\-msep\-data \-mno\-sep\-data \-mlong\-calls \-mno\-long\-calls +\&\-mfast\-fp \-minline\-plt \-mmulticore \-mcorea \-mcoreb \-msdram +\&\-micplb\fR +.Sp +\&\fIC6X Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian \-march=\fR\fIcpu\fR +\&\fB\-msim \-msdata=\fR\fIsdata-type\fR +.Sp +\&\fI\s-1CRIS\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR +\&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR +\&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects +\&\-mstack\-align \-mdata\-align \-mconst\-align +\&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt +\&\-melf \-maout \-melinux \-mlinux \-sim \-sim2 +\&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR +.Sp +\&\fI\s-1CR16\s0 Options\fR +\&\fB\-mmac +\&\-mcr16cplus \-mcr16c +\&\-msim \-mint32 \-mbit\-ops +\&\-mdata\-model=\fR\fImodel\fR +.Sp +\&\fIC\-SKY Options\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR +\&\fB\-mbig\-endian \-EB \-mlittle\-endian \-EL +\&\-mhard\-float \-msoft\-float \-mfpu=\fR\fIfpu\fR \fB\-mdouble\-float \-mfdivdu +\&\-melrw \-mistack \-mmp \-mcp \-mcache \-msecurity \-mtrust +\&\-mdsp \-medsp \-mvdsp +\&\-mdiv \-msmart \-mhigh\-registers \-manchor +\&\-mpushpop \-mmultiple\-stld \-mconstpool \-mstack\-size \-mccrt +\&\-mbranch\-cost=\fR\fIn\fR \fB\-mcse\-cc \-msched\-prolog\fR +.Sp +\&\fIDarwin Options\fR +\&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal +\&\-arch_only \-bind_at_load \-bundle \-bundle_loader +\&\-client_name \-compatibility_version \-current_version +\&\-dead_strip +\&\-dependency\-file \-dylib_file \-dylinker_install_name +\&\-dynamic \-dynamiclib \-exported_symbols_list +\&\-filelist \-flat_namespace \-force_cpusubtype_ALL +\&\-force_flat_namespace \-headerpad_max_install_names +\&\-iframework +\&\-image_base \-init \-install_name \-keep_private_externs +\&\-multi_module \-multiply_defined \-multiply_defined_unused +\&\-noall_load \-no_dead_strip_inits_and_terms +\&\-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit +\&\-pagezero_size \-prebind \-prebind_all_twolevel_modules +\&\-private_bundle \-read_only_relocs \-sectalign +\&\-sectobjectsymbols \-whyload \-seg1addr +\&\-sectcreate \-sectobjectsymbols \-sectorder +\&\-segaddr \-segs_read_only_addr \-segs_read_write_addr +\&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit +\&\-segprot \-segs_read_only_addr \-segs_read_write_addr +\&\-single_module \-static \-sub_library \-sub_umbrella +\&\-twolevel_namespace \-umbrella \-undefined +\&\-unexported_symbols_list \-weak_reference_mismatches +\&\-whatsloaded \-F \-gused \-gfull \-mmacosx\-version\-min=\fR\fIversion\fR +\&\fB\-mkernel \-mone\-byte\-bool\fR +.Sp +\&\fI\s-1DEC\s0 Alpha Options\fR +\&\fB\-mno\-fp\-regs \-msoft\-float +\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant +\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR +\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants +\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mbwx \-mmax \-mfix \-mcix +\&\-mfloat\-vax \-mfloat\-ieee +\&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data +\&\-msmall\-text \-mlarge\-text +\&\-mmemory\-latency=\fR\fItime\fR +.Sp +\&\fI\s-1FR30\s0 Options\fR +\&\fB\-msmall\-model \-mno\-lsim\fR +.Sp +\&\fI\s-1FT32\s0 Options\fR +\&\fB\-msim \-mlra \-mnodiv \-mft32b \-mcompress \-mnopm\fR +.Sp +\&\fI\s-1FRV\s0 Options\fR +\&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64 +\&\-mhard\-float \-msoft\-float +\&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword +\&\-mdouble \-mno\-double +\&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd +\&\-mfdpic \-minline\-plt \-mgprel\-ro \-multilib\-library\-pic +\&\-mlinked\-fp \-mlong\-calls \-malign\-labels +\&\-mlibrary\-pic \-macc\-4 \-macc\-8 +\&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move +\&\-moptimize\-membar \-mno\-optimize\-membar +\&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec +\&\-mvliw\-branch \-mno\-vliw\-branch +\&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec +\&\-mno\-nested\-cond\-exec \-mtomcat\-stats +\&\-mTLS \-mtls +\&\-mcpu=\fR\fIcpu\fR +.Sp +\&\fIGNU/Linux Options\fR +\&\fB\-mglibc \-muclibc \-mmusl \-mbionic \-mandroid +\&\-tno\-android\-cc \-tno\-android\-ld\fR +.Sp +\&\fIH8/300 Options\fR +\&\fB\-mrelax \-mh \-ms \-mn \-mexr \-mno\-exr \-mint32 \-malign\-300\fR +.Sp +\&\fI\s-1HPPA\s0 Options\fR +\&\fB\-march=\fR\fIarchitecture-type\fR +\&\fB\-mcaller\-copies \-mdisable\-fpregs \-mdisable\-indexing +\&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls +\&\-mlong\-load\-store \-mno\-disable\-fpregs +\&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas +\&\-mno\-jump\-in\-delay \-mno\-long\-load\-store +\&\-mno\-portable\-runtime \-mno\-soft\-float +\&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0 +\&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime +\&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio +\&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR +.Sp +\&\fI\s-1IA\-64\s0 Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic +\&\-mvolatile\-asm\-stop \-mregister\-names \-msdata \-mno\-sdata +\&\-mconstant\-gp \-mauto\-pic \-mfused\-madd +\&\-minline\-float\-divide\-min\-latency +\&\-minline\-float\-divide\-max\-throughput +\&\-mno\-inline\-float\-divide +\&\-minline\-int\-divide\-min\-latency +\&\-minline\-int\-divide\-max\-throughput +\&\-mno\-inline\-int\-divide +\&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput +\&\-mno\-inline\-sqrt +\&\-mdwarf2\-asm \-mearly\-stop\-bits +\&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-milp32 \-mlp64 +\&\-msched\-br\-data\-spec \-msched\-ar\-data\-spec \-msched\-control\-spec +\&\-msched\-br\-in\-data\-spec \-msched\-ar\-in\-data\-spec \-msched\-in\-control\-spec +\&\-msched\-spec\-ldc \-msched\-spec\-control\-ldc +\&\-msched\-prefer\-non\-data\-spec\-insns \-msched\-prefer\-non\-control\-spec\-insns +\&\-msched\-stop\-bits\-after\-every\-cycle \-msched\-count\-spec\-in\-critical\-path +\&\-msel\-sched\-dont\-check\-control\-spec \-msched\-fp\-mem\-deps\-zero\-cost +\&\-msched\-max\-memory\-insns\-hard\-limit \-msched\-max\-memory\-insns=\fR\fImax-insns\fR +.Sp +\&\fI\s-1LM32\s0 Options\fR +\&\fB\-mbarrel\-shift\-enabled \-mdivide\-enabled \-mmultiply\-enabled +\&\-msign\-extend\-enabled \-muser\-enabled\fR +.Sp +\&\fIM32R/D Options\fR +\&\fB\-m32r2 \-m32rx \-m32r +\&\-mdebug +\&\-malign\-loops \-mno\-align\-loops +\&\-missue\-rate=\fR\fInumber\fR +\&\fB\-mbranch\-cost=\fR\fInumber\fR +\&\fB\-mmodel=\fR\fIcode-size-model-type\fR +\&\fB\-msdata=\fR\fIsdata-type\fR +\&\fB\-mno\-flush\-func \-mflush\-func=\fR\fIname\fR +\&\fB\-mno\-flush\-trap \-mflush\-trap=\fR\fInumber\fR +\&\fB\-G\fR \fInum\fR +.Sp +\&\fIM32C Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-msim \-memregs=\fR\fInumber\fR +.Sp +\&\fIM680x0 Options\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR \fB\-mtune=\fR\fItune\fR +\&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040 +\&\-m68060 \-mcpu32 \-m5200 \-m5206e \-m528x \-m5307 \-m5407 +\&\-mcfv4e \-mbitfield \-mno\-bitfield \-mc68000 \-mc68020 +\&\-mnobitfield \-mrtd \-mno\-rtd \-mdiv \-mno\-div \-mshort +\&\-mno\-short \-mhard\-float \-m68881 \-msoft\-float \-mpcrel +\&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data +\&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library +\&\-mxgot \-mno\-xgot \-mlong\-jump\-table\-offsets\fR +.Sp +\&\fIMCore Options\fR +\&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates +\&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields +\&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data +\&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim +\&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR +.Sp +\&\fIMeP Options\fR +\&\fB\-mabsdiff \-mall\-opts \-maverage \-mbased=\fR\fIn\fR \fB\-mbitops +\&\-mc=\fR\fIn\fR \fB\-mclip \-mconfig=\fR\fIname\fR \fB\-mcop \-mcop32 \-mcop64 \-mivc2 +\&\-mdc \-mdiv \-meb \-mel \-mio\-volatile \-ml \-mleadz \-mm \-mminmax +\&\-mmult \-mno\-opts \-mrepeat \-ms \-msatur \-msdram \-msim \-msimnovec \-mtf +\&\-mtiny=\fR\fIn\fR +.Sp +\&\fIMicroBlaze Options\fR +\&\fB\-msoft\-float \-mhard\-float \-msmall\-divides \-mcpu=\fR\fIcpu\fR +\&\fB\-mmemcpy \-mxl\-soft\-mul \-mxl\-soft\-div \-mxl\-barrel\-shift +\&\-mxl\-pattern\-compare \-mxl\-stack\-check \-mxl\-gp\-opt \-mno\-clearbss +\&\-mxl\-multiply\-high \-mxl\-float\-convert \-mxl\-float\-sqrt +\&\-mbig\-endian \-mlittle\-endian \-mxl\-reorder \-mxl\-mode\-\fR\fIapp-model\fR +\&\fB\-mpic\-data\-is\-text\-relative\fR +.Sp +\&\fI\s-1MIPS\s0 Options\fR +\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR +\&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 \-mips32r3 \-mips32r5 +\&\-mips32r6 \-mips64 \-mips64r2 \-mips64r3 \-mips64r5 \-mips64r6 +\&\-mips16 \-mno\-mips16 \-mflip\-mips16 +\&\-minterlink\-compressed \-mno\-interlink\-compressed +\&\-minterlink\-mips16 \-mno\-interlink\-mips16 +\&\-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls +\&\-mshared \-mno\-shared \-mplt \-mno\-plt \-mxgot \-mno\-xgot +\&\-mgp32 \-mgp64 \-mfp32 \-mfpxx \-mfp64 \-mhard\-float \-msoft\-float +\&\-mno\-float \-msingle\-float \-mdouble\-float +\&\-modd\-spreg \-mno\-odd\-spreg +\&\-mabs=\fR\fImode\fR \fB\-mnan=\fR\fIencoding\fR +\&\fB\-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2 +\&\-mmcu \-mmno\-mcu +\&\-meva \-mno\-eva +\&\-mvirt \-mno\-virt +\&\-mxpa \-mno\-xpa +\&\-mcrc \-mno\-crc +\&\-mginv \-mno\-ginv +\&\-mmicromips \-mno\-micromips +\&\-mmsa \-mno\-msa +\&\-mloongson\-mmi \-mno\-loongson\-mmi +\&\-mloongson\-ext \-mno\-loongson\-ext +\&\-mloongson\-ext2 \-mno\-loongson\-ext2 +\&\-mfpu=\fR\fIfpu-type\fR +\&\fB\-msmartmips \-mno\-smartmips +\&\-mpaired\-single \-mno\-paired\-single \-mdmx \-mno\-mdmx +\&\-mips3d \-mno\-mips3d \-mmt \-mno\-mt \-mllsc \-mno\-llsc +\&\-mlong64 \-mlong32 \-msym32 \-mno\-sym32 +\&\-G\fR\fInum\fR \fB\-mlocal\-sdata \-mno\-local\-sdata +\&\-mextern\-sdata \-mno\-extern\-sdata \-mgpopt \-mno\-gopt +\&\-membedded\-data \-mno\-embedded\-data +\&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata +\&\-mcode\-readable=\fR\fIsetting\fR +\&\fB\-msplit\-addresses \-mno\-split\-addresses +\&\-mexplicit\-relocs \-mno\-explicit\-relocs +\&\-mcheck\-zero\-division \-mno\-check\-zero\-division +\&\-mdivide\-traps \-mdivide\-breaks +\&\-mload\-store\-pairs \-mno\-load\-store\-pairs +\&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls +\&\-mmad \-mno\-mad \-mimadd \-mno\-imadd \-mfused\-madd \-mno\-fused\-madd \-nocpp +\&\-mfix\-24k \-mno\-fix\-24k +\&\-mfix\-r4000 \-mno\-fix\-r4000 \-mfix\-r4400 \-mno\-fix\-r4400 +\&\-mfix\-r5900 \-mno\-fix\-r5900 +\&\-mfix\-r10000 \-mno\-fix\-r10000 \-mfix\-rm7000 \-mno\-fix\-rm7000 +\&\-mfix\-vr4120 \-mno\-fix\-vr4120 +\&\-mfix\-vr4130 \-mno\-fix\-vr4130 \-mfix\-sb1 \-mno\-fix\-sb1 +\&\-mflush\-func=\fR\fIfunc\fR \fB\-mno\-flush\-func +\&\-mbranch\-cost=\fR\fInum\fR \fB\-mbranch\-likely \-mno\-branch\-likely +\&\-mcompact\-branches=\fR\fIpolicy\fR +\&\fB\-mfp\-exceptions \-mno\-fp\-exceptions +\&\-mvr4130\-align \-mno\-vr4130\-align \-msynci \-mno\-synci +\&\-mlxc1\-sxc1 \-mno\-lxc1\-sxc1 \-mmadd4 \-mno\-madd4 +\&\-mrelax\-pic\-calls \-mno\-relax\-pic\-calls \-mmcount\-ra\-address +\&\-mframe\-header\-opt \-mno\-frame\-header\-opt\fR +.Sp +\&\fI\s-1MMIX\s0 Options\fR +\&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu +\&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols +\&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses +\&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR +.Sp +\&\fI\s-1MN10300\s0 Options\fR +\&\fB\-mmult\-bug \-mno\-mult\-bug +\&\-mno\-am33 \-mam33 \-mam33\-2 \-mam34 +\&\-mtune=\fR\fIcpu-type\fR +\&\fB\-mreturn\-pointer\-on\-d0 +\&\-mno\-crt0 \-mrelax \-mliw \-msetlb\fR +.Sp +\&\fIMoxie Options\fR +\&\fB\-meb \-mel \-mmul.x \-mno\-crt0\fR +.Sp +\&\fI\s-1MSP430\s0 Options\fR +\&\fB\-msim \-masm\-hex \-mmcu= \-mcpu= \-mlarge \-msmall \-mrelax +\&\-mwarn\-mcu +\&\-mcode\-region= \-mdata\-region= +\&\-msilicon\-errata= \-msilicon\-errata\-warn= +\&\-mhwmult= \-minrt\fR +.Sp +\&\fI\s-1NDS32\s0 Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian +\&\-mreduced\-regs \-mfull\-regs +\&\-mcmov \-mno\-cmov +\&\-mext\-perf \-mno\-ext\-perf +\&\-mext\-perf2 \-mno\-ext\-perf2 +\&\-mext\-string \-mno\-ext\-string +\&\-mv3push \-mno\-v3push +\&\-m16bit \-mno\-16bit +\&\-misr\-vector\-size=\fR\fInum\fR +\&\fB\-mcache\-block\-size=\fR\fInum\fR +\&\fB\-march=\fR\fIarch\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mctor\-dtor \-mrelax\fR +.Sp +\&\fINios \s-1II\s0 Options\fR +\&\fB\-G\fR \fInum\fR \fB\-mgpopt=\fR\fIoption\fR \fB\-mgpopt \-mno\-gpopt +\&\-mgprel\-sec=\fR\fIregexp\fR \fB\-mr0rel\-sec=\fR\fIregexp\fR +\&\fB\-mel \-meb +\&\-mno\-bypass\-cache \-mbypass\-cache +\&\-mno\-cache\-volatile \-mcache\-volatile +\&\-mno\-fast\-sw\-div \-mfast\-sw\-div +\&\-mhw\-mul \-mno\-hw\-mul \-mhw\-mulx \-mno\-hw\-mulx \-mno\-hw\-div \-mhw\-div +\&\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR \fB\-mno\-custom\-\fR\fIinsn\fR +\&\fB\-mcustom\-fpu\-cfg=\fR\fIname\fR +\&\fB\-mhal \-msmallc \-msys\-crt0=\fR\fIname\fR \fB\-msys\-lib=\fR\fIname\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mbmx \-mno\-bmx \-mcdx \-mno\-cdx\fR +.Sp +\&\fINvidia \s-1PTX\s0 Options\fR +\&\fB\-m32 \-m64 \-mmainkernel \-moptimize\fR +.Sp +\&\fIOpenRISC Options\fR +\&\fB\-mboard=\fR\fIname\fR \fB\-mnewlib \-mhard\-mul \-mhard\-div +\&\-msoft\-mul \-msoft\-div +\&\-mcmov \-mror \-msext \-msfimm \-mshftimm\fR +.Sp +\&\fI\s-1PDP\-11\s0 Options\fR +\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10 +\&\-mint32 \-mno\-int16 \-mint16 \-mno\-int32 +\&\-msplit \-munix\-asm \-mdec\-asm \-mgnu\-asm \-mlra\fR +.Sp +\&\fIpicoChip Options\fR +\&\fB\-mae=\fR\fIae_type\fR \fB\-mvliw\-lookahead=\fR\fIN\fR +\&\fB\-msymbol\-as\-address \-mno\-inefficient\-warnings\fR +.Sp +\&\fIPowerPC Options\fR +See \s-1RS/6000\s0 and PowerPC Options. +.Sp +\&\fIRISC-V Options\fR +\&\fB\-mbranch\-cost=\fR\fIN\-instruction\fR +\&\fB\-mplt \-mno\-plt +\&\-mabi=\fR\fIABI-string\fR +\&\fB\-mfdiv \-mno\-fdiv +\&\-mdiv \-mno\-div +\&\-march=\fR\fIISA-string\fR +\&\fB\-mtune=\fR\fIprocessor-string\fR +\&\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-msmall\-data\-limit=\fR\fIN\-bytes\fR +\&\fB\-msave\-restore \-mno\-save\-restore +\&\-mstrict\-align \-mno\-strict\-align +\&\-mcmodel=medlow \-mcmodel=medany +\&\-mexplicit\-relocs \-mno\-explicit\-relocs +\&\-mrelax \-mno\-relax +\&\-mriscv\-attribute \-mmo\-riscv\-attribute\fR +.Sp +\&\fI\s-1RL78\s0 Options\fR +\&\fB\-msim \-mmul=none \-mmul=g13 \-mmul=g14 \-mallregs +\&\-mcpu=g10 \-mcpu=g13 \-mcpu=g14 \-mg10 \-mg13 \-mg14 +\&\-m64bit\-doubles \-m32bit\-doubles \-msave\-mduc\-in\-interrupts\fR +.Sp +\&\fI\s-1RS/6000\s0 and PowerPC Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mpowerpc64 +\&\-maltivec \-mno\-altivec +\&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt +\&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt +\&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mpopcntd \-mno\-popcntd +\&\-mfprnd \-mno\-fprnd +\&\-mcmpb \-mno\-cmpb \-mmfpgpr \-mno\-mfpgpr \-mhard\-dfp \-mno\-hard\-dfp +\&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc +\&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe +\&\-malign\-power \-malign\-natural +\&\-msoft\-float \-mhard\-float \-mmultiple \-mno\-multiple +\&\-mupdate \-mno\-update +\&\-mavoid\-indexed\-addresses \-mno\-avoid\-indexed\-addresses +\&\-mfused\-madd \-mno\-fused\-madd \-mbit\-align \-mno\-bit\-align +\&\-mstrict\-align \-mno\-strict\-align \-mrelocatable +\&\-mno\-relocatable \-mrelocatable\-lib \-mno\-relocatable\-lib +\&\-mtoc \-mno\-toc \-mlittle \-mlittle\-endian \-mbig \-mbig\-endian +\&\-mdynamic\-no\-pic \-mswdiv \-msingle\-pic\-base +\&\-mprioritize\-restricted\-insns=\fR\fIpriority\fR +\&\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR +\&\fB\-minsert\-sched\-nops=\fR\fIscheme\fR +\&\fB\-mcall\-aixdesc \-mcall\-eabi \-mcall\-freebsd +\&\-mcall\-linux \-mcall\-netbsd \-mcall\-openbsd +\&\-mcall\-sysv \-mcall\-sysv\-eabi \-mcall\-sysv\-noeabi +\&\-mtraceback=\fR\fItraceback_type\fR +\&\fB\-maix\-struct\-return \-msvr4\-struct\-return +\&\-mabi=\fR\fIabi-type\fR \fB\-msecure\-plt \-mbss\-plt +\&\-mlongcall \-mno\-longcall \-mpltseq \-mno\-pltseq +\&\-mblock\-move\-inline\-limit=\fR\fInum\fR +\&\fB\-mblock\-compare\-inline\-limit=\fR\fInum\fR +\&\fB\-mblock\-compare\-inline\-loop\-limit=\fR\fInum\fR +\&\fB\-mstring\-compare\-inline\-limit=\fR\fInum\fR +\&\fB\-misel \-mno\-isel +\&\-mvrsave \-mno\-vrsave +\&\-mmulhw \-mno\-mulhw +\&\-mdlmzb \-mno\-dlmzb +\&\-mprototype \-mno\-prototype +\&\-msim \-mmvme \-mads \-myellowknife \-memb \-msdata +\&\-msdata=\fR\fIopt\fR \fB\-mreadonly\-in\-sdata \-mvxworks \-G\fR \fInum\fR +\&\fB\-mrecip \-mrecip=\fR\fIopt\fR \fB\-mno\-recip \-mrecip\-precision +\&\-mno\-recip\-precision +\&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz +\&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mhtm \-mno\-htm +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm +\&\-mfloat128 \-mno\-float128 \-mfloat128\-hardware \-mno\-float128\-hardware +\&\-mgnu\-attribute \-mno\-gnu\-attribute +\&\-mstack\-protector\-guard=\fR\fIguard\fR \fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR +.Sp +\&\fI\s-1RX\s0 Options\fR +\&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu +\&\-mcpu= +\&\-mbig\-endian\-data \-mlittle\-endian\-data +\&\-msmall\-data +\&\-msim \-mno\-sim +\&\-mas100\-syntax \-mno\-as100\-syntax +\&\-mrelax +\&\-mmax\-constant\-size= +\&\-mint\-register= +\&\-mpid +\&\-mallow\-string\-insns \-mno\-allow\-string\-insns +\&\-mjsr +\&\-mno\-warn\-multiple\-fast\-interrupts +\&\-msave\-acc\-in\-interrupts\fR +.Sp +\&\fIS/390 and zSeries Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mhard\-float \-msoft\-float \-mhard\-dfp \-mno\-hard\-dfp +\&\-mlong\-double\-64 \-mlong\-double\-128 +\&\-mbackchain \-mno\-backchain \-mpacked\-stack \-mno\-packed\-stack +\&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle +\&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch +\&\-mhtm \-mvx \-mzvector +\&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch=\fR\fIhalfwords\fR\fB,\fR\fIhalfwords\fR +.Sp +\&\fIScore Options\fR +\&\fB\-meb \-mel +\&\-mnhwloop +\&\-muls +\&\-mmac +\&\-mscore5 \-mscore5u \-mscore7 \-mscore7d\fR +.Sp +\&\fI\s-1SH\s0 Options\fR +\&\fB\-m1 \-m2 \-m2e +\&\-m2a\-nofpu \-m2a\-single\-only \-m2a\-single \-m2a +\&\-m3 \-m3e +\&\-m4\-nofpu \-m4\-single\-only \-m4\-single \-m4 +\&\-m4a\-nofpu \-m4a\-single\-only \-m4a\-single \-m4a \-m4al +\&\-mb \-ml \-mdalign \-mrelax +\&\-mbigtable \-mfmovd \-mrenesas \-mno\-renesas \-mnomacsave +\&\-mieee \-mno\-ieee \-mbitops \-misize \-minline\-ic_invalidate \-mpadstruct +\&\-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR +\&\fB\-mdivsi3_libfunc=\fR\fIname\fR \fB\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-maccumulate\-outgoing\-args +\&\-matomic\-model=\fR\fIatomic-model\fR +\&\fB\-mbranch\-cost=\fR\fInum\fR \fB\-mzdcbranch \-mno\-zdcbranch +\&\-mcbranch\-force\-delay\-slot +\&\-mfused\-madd \-mno\-fused\-madd \-mfsca \-mno\-fsca \-mfsrra \-mno\-fsrra +\&\-mpretend\-cmove \-mtas\fR +.Sp +\&\fISolaris 2 Options\fR +\&\fB\-mclear\-hwcap \-mno\-clear\-hwcap \-mimpure\-text \-mno\-impure\-text +\&\-pthreads\fR +.Sp +\&\fI\s-1SPARC\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mmemory\-model=\fR\fImem-model\fR +\&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs +\&\-mfaster\-structs \-mno\-faster\-structs \-mflat \-mno\-flat +\&\-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float +\&\-mhard\-quad\-float \-msoft\-quad\-float +\&\-mstack\-bias \-mno\-stack\-bias +\&\-mstd\-struct\-return \-mno\-std\-struct\-return +\&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode +\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis +\&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 +\&\-mvis4 \-mno\-vis4 \-mvis4b \-mno\-vis4b +\&\-mcbcond \-mno\-cbcond \-mfmaf \-mno\-fmaf \-mfsmuld \-mno\-fsmuld +\&\-mpopc \-mno\-popc \-msubxc \-mno\-subxc +\&\-mfix\-at697f \-mfix\-ut699 \-mfix\-ut700 \-mfix\-gr712rc +\&\-mlra \-mno\-lra\fR +.Sp +\&\fI\s-1SPU\s0 Options\fR +\&\fB\-mwarn\-reloc \-merror\-reloc +\&\-msafe\-dma \-munsafe\-dma +\&\-mbranch\-hints +\&\-msmall\-mem \-mlarge\-mem \-mstdmain +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mea32 \-mea64 +\&\-maddress\-space\-conversion \-mno\-address\-space\-conversion +\&\-mcache\-size=\fR\fIcache-size\fR +\&\fB\-matomic\-updates \-mno\-atomic\-updates\fR +.Sp +\&\fISystem V Options\fR +\&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR +.Sp +\&\fITILE-Gx Options\fR +\&\fB\-mcpu=CPU \-m32 \-m64 \-mbig\-endian \-mlittle\-endian +\&\-mcmodel=\fR\fIcode-model\fR +.Sp +\&\fITILEPro Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32\fR +.Sp +\&\fIV850 Options\fR +\&\fB\-mlong\-calls \-mno\-long\-calls \-mep \-mno\-ep +\&\-mprolog\-function \-mno\-prolog\-function \-mspace +\&\-mtda=\fR\fIn\fR \fB\-msda=\fR\fIn\fR \fB\-mzda=\fR\fIn\fR +\&\fB\-mapp\-regs \-mno\-app\-regs +\&\-mdisable\-callt \-mno\-disable\-callt +\&\-mv850e2v3 \-mv850e2 \-mv850e1 \-mv850es +\&\-mv850e \-mv850 \-mv850e3v5 +\&\-mloop +\&\-mrelax +\&\-mlong\-jumps +\&\-msoft\-float +\&\-mhard\-float +\&\-mgcc\-abi +\&\-mrh850\-abi +\&\-mbig\-switch\fR +.Sp +\&\fI\s-1VAX\s0 Options\fR +\&\fB\-mg \-mgnu \-munix\fR +.Sp +\&\fIVisium Options\fR +\&\fB\-mdebug \-msim \-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float +\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR \fB\-msv\-mode \-muser\-mode\fR +.Sp +\&\fI\s-1VMS\s0 Options\fR +\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64 +\&\-mpointer\-size=\fR\fIsize\fR +.Sp +\&\fIVxWorks Options\fR +\&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic +\&\-Xbind\-lazy \-Xbind\-now\fR +.Sp +\&\fIx86 Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR \fB\-mdump\-tune\-features \-mno\-default +\&\-mfpmath=\fR\fIunit\fR +\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 +\&\-mno\-fp\-ret\-in\-387 \-m80387 \-mhard\-float \-msoft\-float +\&\-mno\-wide\-multiply \-mrtd \-malign\-double +\&\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR +\&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 +\&\-mrecip \-mrecip=\fR\fIopt\fR +\&\fB\-mvzeroupper \-mprefer\-avx128 \-mprefer\-vector\-width=\fR\fIopt\fR +\&\fB\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx +\&\-mavx2 \-mavx512f \-mavx512pf \-mavx512er \-mavx512cd \-mavx512vl +\&\-mavx512bw \-mavx512dq \-mavx512ifma \-mavx512vbmi \-msha \-maes +\&\-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfma \-mpconfig \-mwbnoinvd +\&\-mptwrite \-mprefetchwt1 \-mclflushopt \-mclwb \-mxsavec \-mxsaves +\&\-msse4a \-m3dnow \-m3dnowa \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop +\&\-madx \-mlzcnt \-mbmi2 \-mfxsr \-mxsave \-mxsaveopt \-mrtm \-mhle \-mlwp +\&\-mmwaitx \-mclzero \-mpku \-mthreads \-mgfni \-mvaes \-mwaitpkg +\&\-mshstk \-mmanual\-endbr \-mforce\-indirect\-call \-mavx512vbmi2 +\&\-mvpclmulqdq \-mavx512bitalg \-mmovdiri \-mmovdir64b \-mavx512vpopcntdq +\&\-mavx5124fmaps \-mavx512vnni \-mavx5124vnniw \-mprfchw \-mrdpid +\&\-mrdseed \-msgx +\&\-mcldemote \-mms\-bitfields \-mno\-align\-stringops \-minline\-all\-stringops +\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR +\&\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR \fB\-mmemset\-strategy=\fR\fIstrategy\fR +\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double +\&\-m96bit\-long\-double \-mlong\-double\-64 \-mlong\-double\-80 \-mlong\-double\-128 +\&\-mregparm=\fR\fInum\fR \fB\-msseregparm +\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem +\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign +\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs +\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR \fB\-maddress\-mode=\fR\fImode\fR +\&\fB\-m32 \-m64 \-mx32 \-m16 \-miamcu \-mlarge\-data\-threshold=\fR\fInum\fR +\&\fB\-msse2avx \-mfentry \-mrecord\-mcount \-mnop\-mcount \-m8bit\-idiv +\&\-minstrument\-return=\fR\fItype\fR \fB\-mfentry\-name=\fR\fIname\fR \fB\-mfentry\-section=\fR\fIname\fR +\&\fB\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store +\&\-malign\-data=\fR\fItype\fR \fB\-mstack\-protector\-guard=\fR\fIguard\fR +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR +\&\fB\-mstack\-protector\-guard\-symbol=\fR\fIsymbol\fR +\&\fB\-mgeneral\-regs\-only \-mcall\-ms2sysv\-xlogues +\&\-mindirect\-branch=\fR\fIchoice\fR \fB\-mfunction\-return=\fR\fIchoice\fR +\&\fB\-mindirect\-branch\-register\fR +.Sp +\&\fIx86 Windows Options\fR +\&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll +\&\-mnop\-fun\-dllimport \-mthread +\&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR +.Sp +\&\fIXstormy16 Options\fR +\&\fB\-msim\fR +.Sp +\&\fIXtensa Options\fR +\&\fB\-mconst16 \-mno\-const16 +\&\-mfused\-madd \-mno\-fused\-madd +\&\-mforce\-no\-pic +\&\-mserialize\-volatile \-mno\-serialize\-volatile +\&\-mtext\-section\-literals \-mno\-text\-section\-literals +\&\-mauto\-litpools \-mno\-auto\-litpools +\&\-mtarget\-align \-mno\-target\-align +\&\-mlongcalls \-mno\-longcalls\fR +.Sp +\&\fIzSeries Options\fR +See S/390 and zSeries Options. +.SS "Options Controlling the Kind of Output" +.IX Subsection "Options Controlling the Kind of Output" +Compilation can involve up to four stages: preprocessing, compilation +proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of +preprocessing and compiling several files either into several +assembler input files, or into one assembler input file; then each +assembler input file produces an object file, and linking combines all +the object files (those newly compiled, and those specified as input) +into an executable file. +.PP +For any given input file, the file name suffix determines what kind of +compilation is done: +.IP "\fIfile\fR\fB.c\fR" 4 +.IX Item "file.c" +C source code that must be preprocessed. +.IP "\fIfile\fR\fB.i\fR" 4 +.IX Item "file.i" +C source code that should not be preprocessed. +.IP "\fIfile\fR\fB.ii\fR" 4 +.IX Item "file.ii" +\&\*(C+ source code that should not be preprocessed. +.IP "\fIfile\fR\fB.m\fR" 4 +.IX Item "file.m" +Objective-C source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective-C program work. +.IP "\fIfile\fR\fB.mi\fR" 4 +.IX Item "file.mi" +Objective-C source code that should not be preprocessed. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective\-\*(C+ program work. Note that \fB.M\fR refers +to a literal capital M. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code that should not be preprocessed. +.IP "\fIfile\fR\fB.h\fR" 4 +.IX Item "file.h" +C, \*(C+, Objective-C or Objective\-\*(C+ header file to be turned into a +precompiled header (default), or C, \*(C+ header file to be turned into an +Ada spec (via the \fB\-fdump\-ada\-spec\fR switch). +.IP "\fIfile\fR\fB.cc\fR" 4 +.IX Item "file.cc" +.PD 0 +.IP "\fIfile\fR\fB.cp\fR" 4 +.IX Item "file.cp" +.IP "\fIfile\fR\fB.cxx\fR" 4 +.IX Item "file.cxx" +.IP "\fIfile\fR\fB.cpp\fR" 4 +.IX Item "file.cpp" +.IP "\fIfile\fR\fB.CPP\fR" 4 +.IX Item "file.CPP" +.IP "\fIfile\fR\fB.c++\fR" 4 +.IX Item "file.c++" +.IP "\fIfile\fR\fB.C\fR" 4 +.IX Item "file.C" +.PD +\&\*(C+ source code that must be preprocessed. Note that in \fB.cxx\fR, +the last two letters must both be literally \fBx\fR. Likewise, +\&\fB.C\fR refers to a literal capital C. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code that must be preprocessed. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code that should not be preprocessed. +.IP "\fIfile\fR\fB.hh\fR" 4 +.IX Item "file.hh" +.PD 0 +.IP "\fIfile\fR\fB.H\fR" 4 +.IX Item "file.H" +.IP "\fIfile\fR\fB.hp\fR" 4 +.IX Item "file.hp" +.IP "\fIfile\fR\fB.hxx\fR" 4 +.IX Item "file.hxx" +.IP "\fIfile\fR\fB.hpp\fR" 4 +.IX Item "file.hpp" +.IP "\fIfile\fR\fB.HPP\fR" 4 +.IX Item "file.HPP" +.IP "\fIfile\fR\fB.h++\fR" 4 +.IX Item "file.h++" +.IP "\fIfile\fR\fB.tcc\fR" 4 +.IX Item "file.tcc" +.PD +\&\*(C+ header file to be turned into a precompiled header or Ada spec. +.IP "\fIfile\fR\fB.f\fR" 4 +.IX Item "file.f" +.PD 0 +.IP "\fIfile\fR\fB.for\fR" 4 +.IX Item "file.for" +.IP "\fIfile\fR\fB.ftn\fR" 4 +.IX Item "file.ftn" +.PD +Fixed form Fortran source code that should not be preprocessed. +.IP "\fIfile\fR\fB.F\fR" 4 +.IX Item "file.F" +.PD 0 +.IP "\fIfile\fR\fB.FOR\fR" 4 +.IX Item "file.FOR" +.IP "\fIfile\fR\fB.fpp\fR" 4 +.IX Item "file.fpp" +.IP "\fIfile\fR\fB.FPP\fR" 4 +.IX Item "file.FPP" +.IP "\fIfile\fR\fB.FTN\fR" 4 +.IX Item "file.FTN" +.PD +Fixed form Fortran source code that must be preprocessed (with the traditional +preprocessor). +.IP "\fIfile\fR\fB.f90\fR" 4 +.IX Item "file.f90" +.PD 0 +.IP "\fIfile\fR\fB.f95\fR" 4 +.IX Item "file.f95" +.IP "\fIfile\fR\fB.f03\fR" 4 +.IX Item "file.f03" +.IP "\fIfile\fR\fB.f08\fR" 4 +.IX Item "file.f08" +.PD +Free form Fortran source code that should not be preprocessed. +.IP "\fIfile\fR\fB.F90\fR" 4 +.IX Item "file.F90" +.PD 0 +.IP "\fIfile\fR\fB.F95\fR" 4 +.IX Item "file.F95" +.IP "\fIfile\fR\fB.F03\fR" 4 +.IX Item "file.F03" +.IP "\fIfile\fR\fB.F08\fR" 4 +.IX Item "file.F08" +.PD +Free form Fortran source code that must be preprocessed (with the +traditional preprocessor). +.IP "\fIfile\fR\fB.go\fR" 4 +.IX Item "file.go" +Go source code. +.IP "\fIfile\fR\fB.brig\fR" 4 +.IX Item "file.brig" +\&\s-1BRIG\s0 files (binary representation of \s-1HSAIL\s0). +.IP "\fIfile\fR\fB.d\fR" 4 +.IX Item "file.d" +D source code. +.IP "\fIfile\fR\fB.di\fR" 4 +.IX Item "file.di" +D interface file. +.IP "\fIfile\fR\fB.dd\fR" 4 +.IX Item "file.dd" +D documentation code (Ddoc). +.IP "\fIfile\fR\fB.ads\fR" 4 +.IX Item "file.ads" +Ada source code file that contains a library unit declaration (a +declaration of a package, subprogram, or generic, or a generic +instantiation), or a library unit renaming declaration (a package, +generic, or subprogram renaming declaration). Such files are also +called \fIspecs\fR. +.IP "\fIfile\fR\fB.adb\fR" 4 +.IX Item "file.adb" +Ada source code file containing a library unit body (a subprogram or +package body). Such files are also called \fIbodies\fR. +.IP "\fIfile\fR\fB.s\fR" 4 +.IX Item "file.s" +Assembler code. +.IP "\fIfile\fR\fB.S\fR" 4 +.IX Item "file.S" +.PD 0 +.IP "\fIfile\fR\fB.sx\fR" 4 +.IX Item "file.sx" +.PD +Assembler code that must be preprocessed. +.IP "\fIother\fR" 4 +.IX Item "other" +An object file to be fed straight into linking. +Any file name with no recognized suffix is treated this way. +.PP +You can specify the input language explicitly with the \fB\-x\fR option: +.IP "\fB\-x\fR \fIlanguage\fR" 4 +.IX Item "-x language" +Specify explicitly the \fIlanguage\fR for the following input files +(rather than letting the compiler choose a default based on the file +name suffix). This option applies to all following input files until +the next \fB\-x\fR option. Possible values for \fIlanguage\fR are: +.Sp +.Vb 10 +\& c c\-header cpp\-output +\& c++ c++\-header c++\-cpp\-output +\& objective\-c objective\-c\-header objective\-c\-cpp\-output +\& objective\-c++ objective\-c++\-header objective\-c++\-cpp\-output +\& assembler assembler\-with\-cpp +\& ada +\& d +\& f77 f77\-cpp\-input f95 f95\-cpp\-input +\& go +\& brig +.Ve +.IP "\fB\-x none\fR" 4 +.IX Item "-x none" +Turn off any specification of a language, so that subsequent files are +handled according to their file name suffixes (as they are if \fB\-x\fR +has not been used at all). +.PP +If you only want some of the stages of compilation, you can use +\&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and +one of the options \fB\-c\fR, \fB\-S\fR, or \fB\-E\fR to say where +\&\fBgcc\fR is to stop. Note that some combinations (for example, +\&\fB\-x cpp-output \-E\fR) instruct \fBgcc\fR to do nothing at all. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +Compile or assemble the source files, but do not link. The linking +stage simply is not done. The ultimate output is in the form of an +object file for each source file. +.Sp +By default, the object file name for a source file is made by replacing +the suffix \fB.c\fR, \fB.i\fR, \fB.s\fR, etc., with \fB.o\fR. +.Sp +Unrecognized input files, not requiring compilation or assembly, are +ignored. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +Stop after the stage of compilation proper; do not assemble. The output +is in the form of an assembler code file for each non-assembler input +file specified. +.Sp +By default, the assembler file name for a source file is made by +replacing the suffix \fB.c\fR, \fB.i\fR, etc., with \fB.s\fR. +.Sp +Input files that don't require compilation are ignored. +.IP "\fB\-E\fR" 4 +.IX Item "-E" +Stop after the preprocessing stage; do not run the compiler proper. The +output is in the form of preprocessed source code, which is sent to the +standard output. +.Sp +Input files that don't require preprocessing are ignored. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Place output in file \fIfile\fR. This applies to whatever +sort of output is being produced, whether it be an executable file, +an object file, an assembler file or preprocessed C code. +.Sp +If \fB\-o\fR is not specified, the default is to put an executable +file in \fIa.out\fR, the object file for +\&\fI\fIsource\fI.\fIsuffix\fI\fR in \fI\fIsource\fI.o\fR, its +assembler file in \fI\fIsource\fI.s\fR, a precompiled header file in +\&\fI\fIsource\fI.\fIsuffix\fI.gch\fR, and all preprocessed C source on +standard output. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Print (on standard error output) the commands executed to run the stages +of compilation. Also print the version number of the compiler driver +program and of the preprocessor and the compiler proper. +.IP "\fB\-###\fR" 4 +.IX Item "-###" +Like \fB\-v\fR except the commands are not executed and arguments +are quoted unless they contain only alphanumeric characters or \f(CW\*(C`./\-_\*(C'\fR. +This is useful for shell scripts to capture the driver-generated command lines. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print (on the standard output) a description of the command-line options +understood by \fBgcc\fR. If the \fB\-v\fR option is also specified +then \fB\-\-help\fR is also passed on to the various processes +invoked by \fBgcc\fR, so that they can display the command-line options +they accept. If the \fB\-Wextra\fR option has also been specified +(prior to the \fB\-\-help\fR option), then command-line options that +have no documentation associated with them are also displayed. +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +Print (on the standard output) a description of target-specific command-line +options for each tool. For some targets extra target-specific +information may also be printed. +.IP "\fB\-\-help={\fR\fIclass\fR|[\fB^\fR]\fIqualifier\fR\fB}\fR[\fB,...\fR]" 4 +.IX Item "--help={class|[^]qualifier}[,...]" +Print (on the standard output) a description of the command-line +options understood by the compiler that fit into all specified classes +and qualifiers. These are the supported classes: +.RS 4 +.IP "\fBoptimizers\fR" 4 +.IX Item "optimizers" +Display all of the optimization options supported by the +compiler. +.IP "\fBwarnings\fR" 4 +.IX Item "warnings" +Display all of the options controlling warning messages +produced by the compiler. +.IP "\fBtarget\fR" 4 +.IX Item "target" +Display target-specific options. Unlike the +\&\fB\-\-target\-help\fR option however, target-specific options of the +linker and assembler are not displayed. This is because those +tools do not currently support the extended \fB\-\-help=\fR syntax. +.IP "\fBparams\fR" 4 +.IX Item "params" +Display the values recognized by the \fB\-\-param\fR +option. +.IP "\fIlanguage\fR" 4 +.IX Item "language" +Display the options supported for \fIlanguage\fR, where +\&\fIlanguage\fR is the name of one of the languages supported in this +version of \s-1GCC.\s0 +.IP "\fBcommon\fR" 4 +.IX Item "common" +Display the options that are common to all languages. +.RE +.RS 4 +.Sp +These are the supported qualifiers: +.IP "\fBundocumented\fR" 4 +.IX Item "undocumented" +Display only those options that are undocumented. +.IP "\fBjoined\fR" 4 +.IX Item "joined" +Display options taking an argument that appears after an equal +sign in the same continuous piece of text, such as: +\&\fB\-\-help=target\fR. +.IP "\fBseparate\fR" 4 +.IX Item "separate" +Display options taking an argument that appears as a separate word +following the original option, such as: \fB\-o output-file\fR. +.RE +.RS 4 +.Sp +Thus for example to display all the undocumented target-specific +switches supported by the compiler, use: +.Sp +.Vb 1 +\& \-\-help=target,undocumented +.Ve +.Sp +The sense of a qualifier can be inverted by prefixing it with the +\&\fB^\fR character, so for example to display all binary warning +options (i.e., ones that are either on or off and that do not take an +argument) that have a description, use: +.Sp +.Vb 1 +\& \-\-help=warnings,^joined,^undocumented +.Ve +.Sp +The argument to \fB\-\-help=\fR should not consist solely of inverted +qualifiers. +.Sp +Combining several classes is possible, although this usually +restricts the output so much that there is nothing to display. One +case where it does work, however, is when one of the classes is +\&\fItarget\fR. For example, to display all the target-specific +optimization options, use: +.Sp +.Vb 1 +\& \-\-help=target,optimizers +.Ve +.Sp +The \fB\-\-help=\fR option can be repeated on the command line. Each +successive use displays its requested class of options, skipping +those that have already been displayed. If \fB\-\-help\fR is also +specified anywhere on the command line then this takes precedence +over any \fB\-\-help=\fR option. +.Sp +If the \fB\-Q\fR option appears on the command line before the +\&\fB\-\-help=\fR option, then the descriptive text displayed by +\&\fB\-\-help=\fR is changed. Instead of describing the displayed +options, an indication is given as to whether the option is enabled, +disabled or set to a specific value (assuming that the compiler +knows this at the point where the \fB\-\-help=\fR option is used). +.Sp +Here is a truncated example from the \s-1ARM\s0 port of \fBgcc\fR: +.Sp +.Vb 5 +\& % gcc \-Q \-mabi=2 \-\-help=target \-c +\& The following options are target specific: +\& \-mabi= 2 +\& \-mabort\-on\-noreturn [disabled] +\& \-mapcs [disabled] +.Ve +.Sp +The output is sensitive to the effects of previous command-line +options, so for example it is possible to find out which optimizations +are enabled at \fB\-O2\fR by using: +.Sp +.Vb 1 +\& \-Q \-O2 \-\-help=optimizers +.Ve +.Sp +Alternatively you can discover which binary optimizations are enabled +by \fB\-O3\fR by using: +.Sp +.Vb 3 +\& gcc \-c \-Q \-O3 \-\-help=optimizers > /tmp/O3\-opts +\& gcc \-c \-Q \-O2 \-\-help=optimizers > /tmp/O2\-opts +\& diff /tmp/O2\-opts /tmp/O3\-opts | grep enabled +.Ve +.RE +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +Display the version number and copyrights of the invoked \s-1GCC.\s0 +.IP "\fB\-pass\-exit\-codes\fR" 4 +.IX Item "-pass-exit-codes" +Normally the \fBgcc\fR program exits with the code of 1 if any +phase of the compiler returns a non-success return code. If you specify +\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program instead returns with +the numerically highest error produced by any phase returning an error +indication. The C, \*(C+, and Fortran front ends return 4 if an internal +compiler error is encountered. +.IP "\fB\-pipe\fR" 4 +.IX Item "-pipe" +Use pipes rather than temporary files for communication between the +various stages of compilation. This fails to work on some systems where +the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has +no trouble. +.IP "\fB\-specs=\fR\fIfile\fR" 4 +.IX Item "-specs=file" +Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR +file, in order to override the defaults which the \fBgcc\fR driver +program uses when determining what switches to pass to \fBcc1\fR, +\&\fBcc1plus\fR, \fBas\fR, \fBld\fR, etc. More than one +\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they +are processed in order, from left to right. +.IP "\fB\-wrapper\fR" 4 +.IX Item "-wrapper" +Invoke all subcommands under a wrapper program. The name of the +wrapper program and its parameters are passed as a comma separated +list. +.Sp +.Vb 1 +\& gcc \-c t.c \-wrapper gdb,\-\-args +.Ve +.Sp +This invokes all subprograms of \fBgcc\fR under +\&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR is +\&\fBgdb \-\-args cc1 ...\fR. +.IP "\fB\-ffile\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-ffile-prefix-map=old=new" +When compiling files residing in directory \fI\fIold\fI\fR, record +any references to them in the result of the compilation as if the +files resided in directory \fI\fInew\fI\fR instead. Specifying this +option is equivalent to specifying all the individual +\&\fB\-f*\-prefix\-map\fR options. This can be used to make reproducible +builds that are location independent. See also +\&\fB\-fmacro\-prefix\-map\fR and \fB\-fdebug\-prefix\-map\fR. +.IP "\fB\-fplugin=\fR\fIname\fR\fB.so\fR" 4 +.IX Item "-fplugin=name.so" +Load the plugin code in file \fIname\fR.so, assumed to be a +shared object to be dlopen'd by the compiler. The base name of +the shared object file is used to identify the plugin for the +purposes of argument parsing (See +\&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). +Each plugin should define the callback functions specified in the +Plugins \s-1API.\s0 +.IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "-fplugin-arg-name-key=value" +Define an argument called \fIkey\fR with a value of \fIvalue\fR +for the plugin called \fIname\fR. +.IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 +.IX Item "-fdump-ada-spec[-slim]" +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. +.IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 +.IX Item "-fdump-go-spec=file" +For input files in any language, generate corresponding Go +declarations in \fIfile\fR. This generates Go \f(CW\*(C`const\*(C'\fR, +\&\f(CW\*(C`type\*(C'\fR, \f(CW\*(C`var\*(C'\fR, and \f(CW\*(C`func\*(C'\fR declarations which may be a +useful way to start writing a Go interface to code written in some +other language. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SS "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" +\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, +\&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or +\&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, +\&\fB.H\fR, or (for shared template code) \fB.tcc\fR; and +preprocessed \*(C+ files use the suffix \fB.ii\fR. \s-1GCC\s0 recognizes +files with these names and compiles them as \*(C+ programs even if you +call the compiler the same way as for compiling C programs (usually +with the name \fBgcc\fR). +.PP +However, the use of \fBgcc\fR does not add the \*(C+ library. +\&\fBg++\fR is a program that calls \s-1GCC\s0 and automatically specifies linking +against the \*(C+ library. It treats \fB.c\fR, +\&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source +files unless \fB\-x\fR is used. This program is also useful when +precompiling a C header file with a \fB.h\fR extension for use in \*(C+ +compilations. On many systems, \fBg++\fR is also installed with +the name \fBc++\fR. +.PP +When you compile \*(C+ programs, you may specify many of the same +command-line options that you use for compiling programs in any +language; or command-line options meaningful for C and related +languages; or options that are meaningful only for \*(C+ programs. +.SS "Options Controlling C Dialect" +.IX Subsection "Options Controlling C Dialect" +The following options control the dialect of C (or languages derived +from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler +accepts: +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is +equivalent to \fB\-std=c++98\fR. +.Sp +This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO +C90\s0 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and +predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the +type of system you are using. It also enables the undesirable and +rarely used \s-1ISO\s0 trigraph feature. For the C compiler, +it disables recognition of \*(C+ style \fB//\fR comments as well as +the \f(CW\*(C`inline\*(C'\fR keyword. +.Sp +The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite +\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO C\s0 program, of +course, but it is useful to put them in header files that might be included +in compilations done with \fB\-ansi\fR. Alternate predefined macros +such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or +without \fB\-ansi\fR. +.Sp +The \fB\-ansi\fR option does not cause non-ISO programs to be +rejected gratuitously. For that, \fB\-Wpedantic\fR is required in +addition to \fB\-ansi\fR. +.Sp +The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR +option is used. Some header files may notice this macro and refrain +from declaring certain functions or defining certain macros that the +\&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any +programs that might use these names for other things. +.Sp +Functions that are normally built in but do not have semantics +defined by \s-1ISO C\s0 (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +functions when \fB\-ansi\fR is used. +.IP "\fB\-std=\fR" 4 +.IX Item "-std=" +Determine the language standard. This option +is currently only supported when compiling C or \*(C+. +.Sp +The compiler can accept several base standards, such as \fBc90\fR or +\&\fBc++98\fR, and \s-1GNU\s0 dialects of those standards, such as +\&\fBgnu90\fR or \fBgnu++98\fR. When a base standard is specified, the +compiler accepts all programs following that standard plus those +using \s-1GNU\s0 extensions that do not contradict it. For example, +\&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are +incompatible with \s-1ISO C90,\s0 such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR +keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in +\&\s-1ISO C90,\s0 such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR +expression. On the other hand, when a \s-1GNU\s0 dialect of a standard is +specified, all features supported by the compiler are enabled, even when +those features change the meaning of the base standard. As a result, some +strict-conforming programs may be rejected. The particular standard +is used by \fB\-Wpedantic\fR to identify which features are \s-1GNU\s0 +extensions given that version of the standard. For example +\&\fB\-std=gnu90 \-Wpedantic\fR warns about \*(C+ style \fB//\fR +comments, while \fB\-std=gnu99 \-Wpedantic\fR does not. +.Sp +A value for this option must be provided; possible values are +.RS 4 +.IP "\fBc90\fR" 4 +.IX Item "c90" +.PD 0 +.IP "\fBc89\fR" 4 +.IX Item "c89" +.IP "\fBiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +Support all \s-1ISO C90\s0 programs (certain \s-1GNU\s0 extensions that conflict +with \s-1ISO C90\s0 are disabled). Same as \fB\-ansi\fR for C code. +.IP "\fBiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +\&\s-1ISO C90\s0 as modified in amendment 1. +.IP "\fBc99\fR" 4 +.IX Item "c99" +.PD 0 +.IP "\fBc9x\fR" 4 +.IX Item "c9x" +.IP "\fBiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.IP "\fBiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.PD +\&\s-1ISO C99.\s0 This standard is substantially completely supported, modulo +bugs and floating-point issues +(mainly but not entirely relating to optional C99 features from +Annexes F and G). See +<\fBhttp://gcc.gnu.org/c99status.html\fR> for more information. The +names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. +.IP "\fBc11\fR" 4 +.IX Item "c11" +.PD 0 +.IP "\fBc1x\fR" 4 +.IX Item "c1x" +.IP "\fBiso9899:2011\fR" 4 +.IX Item "iso9899:2011" +.PD +\&\s-1ISO C11,\s0 the 2011 revision of the \s-1ISO C\s0 standard. This standard is +substantially completely supported, modulo bugs, floating-point issues +(mainly but not entirely relating to optional C11 features from +Annexes F and G) and the optional Annexes K (Bounds-checking +interfaces) and L (Analyzability). The name \fBc1x\fR is deprecated. +.IP "\fBc17\fR" 4 +.IX Item "c17" +.PD 0 +.IP "\fBc18\fR" 4 +.IX Item "c18" +.IP "\fBiso9899:2017\fR" 4 +.IX Item "iso9899:2017" +.IP "\fBiso9899:2018\fR" 4 +.IX Item "iso9899:2018" +.PD +\&\s-1ISO C17,\s0 the 2017 revision of the \s-1ISO C\s0 standard +(published in 2018). This standard is +same as C11 except for corrections of defects (all of which are also +applied with \fB\-std=c11\fR) and a new value of +\&\f(CW\*(C`_\|_STDC_VERSION_\|_\*(C'\fR, and so is supported to the same extent as C11. +.IP "\fBc2x\fR" 4 +.IX Item "c2x" +The next version of the \s-1ISO C\s0 standard, still under development. The +support for this version is experimental and incomplete. +.IP "\fBgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.IP "\fBgnu89\fR" 4 +.IX Item "gnu89" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C90\s0 (including some C99 features). +.IP "\fBgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.IP "\fBgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C99.\s0 The name \fBgnu9x\fR is deprecated. +.IP "\fBgnu11\fR" 4 +.IX Item "gnu11" +.PD 0 +.IP "\fBgnu1x\fR" 4 +.IX Item "gnu1x" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C11.\s0 +The name \fBgnu1x\fR is deprecated. +.IP "\fBgnu17\fR" 4 +.IX Item "gnu17" +.PD 0 +.IP "\fBgnu18\fR" 4 +.IX Item "gnu18" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C17.\s0 This is the default for C code. +.IP "\fBgnu2x\fR" 4 +.IX Item "gnu2x" +The next version of the \s-1ISO C\s0 standard, still under development, plus +\&\s-1GNU\s0 extensions. The support for this version is experimental and +incomplete. +.IP "\fBc++98\fR" 4 +.IX Item "c++98" +.PD 0 +.IP "\fBc++03\fR" 4 +.IX Item "c++03" +.PD +The 1998 \s-1ISO \*(C+\s0 standard plus the 2003 technical corrigendum and some +additional defect reports. Same as \fB\-ansi\fR for \*(C+ code. +.IP "\fBgnu++98\fR" 4 +.IX Item "gnu++98" +.PD 0 +.IP "\fBgnu++03\fR" 4 +.IX Item "gnu++03" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++98\fR. +.IP "\fBc++11\fR" 4 +.IX Item "c++11" +.PD 0 +.IP "\fBc++0x\fR" 4 +.IX Item "c++0x" +.PD +The 2011 \s-1ISO \*(C+\s0 standard plus amendments. +The name \fBc++0x\fR is deprecated. +.IP "\fBgnu++11\fR" 4 +.IX Item "gnu++11" +.PD 0 +.IP "\fBgnu++0x\fR" 4 +.IX Item "gnu++0x" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++11\fR. +The name \fBgnu++0x\fR is deprecated. +.IP "\fBc++14\fR" 4 +.IX Item "c++14" +.PD 0 +.IP "\fBc++1y\fR" 4 +.IX Item "c++1y" +.PD +The 2014 \s-1ISO \*(C+\s0 standard plus amendments. +The name \fBc++1y\fR is deprecated. +.IP "\fBgnu++14\fR" 4 +.IX Item "gnu++14" +.PD 0 +.IP "\fBgnu++1y\fR" 4 +.IX Item "gnu++1y" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++14\fR. +This is the default for \*(C+ code. +The name \fBgnu++1y\fR is deprecated. +.IP "\fBc++17\fR" 4 +.IX Item "c++17" +.PD 0 +.IP "\fBc++1z\fR" 4 +.IX Item "c++1z" +.PD +The 2017 \s-1ISO \*(C+\s0 standard plus amendments. +The name \fBc++1z\fR is deprecated. +.IP "\fBgnu++17\fR" 4 +.IX Item "gnu++17" +.PD 0 +.IP "\fBgnu++1z\fR" 4 +.IX Item "gnu++1z" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++17\fR. +The name \fBgnu++1z\fR is deprecated. +.IP "\fBc++2a\fR" 4 +.IX Item "c++2a" +The next revision of the \s-1ISO \*(C+\s0 standard, tentatively planned for +2020. Support is highly experimental, and will almost certainly +change in incompatible ways in future releases. +.IP "\fBgnu++2a\fR" 4 +.IX Item "gnu++2a" +\&\s-1GNU\s0 dialect of \fB\-std=c++2a\fR. Support is highly experimental, +and will almost certainly change in incompatible ways in future +releases. +.RE +.RS 4 +.RE +.IP "\fB\-fgnu89\-inline\fR" 4 +.IX Item "-fgnu89-inline" +The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional +\&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode. +.Sp +Using this option is roughly equivalent to adding the +\&\f(CW\*(C`gnu_inline\*(C'\fR function attribute to all inline functions. +.Sp +The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the +C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it +specifies the default behavior). +This option is not supported in \fB\-std=c90\fR or +\&\fB\-std=gnu90\fR mode. +.Sp +The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and +\&\f(CW\*(C`_\|_GNUC_STDC_INLINE_\|_\*(C'\fR may be used to check which semantics are +in effect for \f(CW\*(C`inline\*(C'\fR functions. +.IP "\fB\-fpermitted\-flt\-eval\-methods=\fR\fIstyle\fR" 4 +.IX Item "-fpermitted-flt-eval-methods=style" +\&\s-1ISO/IEC TS 18661\-3\s0 defines new permissible values for +\&\f(CW\*(C`FLT_EVAL_METHOD\*(C'\fR that indicate that operations and constants with +a semantic type that is an interchange or extended format should be +evaluated to the precision and range of that type. These new values are +a superset of those permitted under C99/C11, which does not specify the +meaning of other positive values of \f(CW\*(C`FLT_EVAL_METHOD\*(C'\fR. As such, code +conforming to C11 may not have been written expecting the possibility of +the new values. +.Sp +\&\fB\-fpermitted\-flt\-eval\-methods\fR specifies whether the compiler +should allow only the values of \f(CW\*(C`FLT_EVAL_METHOD\*(C'\fR specified in C99/C11, +or the extended set of values specified in \s-1ISO/IEC TS 18661\-3.\s0 +.Sp +\&\fIstyle\fR is either \f(CW\*(C`c11\*(C'\fR or \f(CW\*(C`ts\-18661\-3\*(C'\fR as appropriate. +.Sp +The default when in a standards compliant mode (\fB\-std=c11\fR or similar) +is \fB\-fpermitted\-flt\-eval\-methods=c11\fR. The default when in a \s-1GNU\s0 +dialect (\fB\-std=gnu11\fR or similar) is +\&\fB\-fpermitted\-flt\-eval\-methods=ts\-18661\-3\fR. +.IP "\fB\-aux\-info\fR \fIfilename\fR" 4 +.IX Item "-aux-info filename" +Output to the given filename prototyped declarations for all functions +declared and/or defined in a translation unit, including those in header +files. This option is silently ignored in any language other than C. +.Sp +Besides declarations, the file indicates, in comments, the origin of +each declaration (source file and line), whether the declaration was +implicit, prototyped or unprototyped (\fBI\fR, \fBN\fR for new or +\&\fBO\fR for old, respectively, in the first character after the line +number and the colon), and whether it came from a declaration or a +definition (\fBC\fR or \fBF\fR, respectively, in the following +character). In the case of function definitions, a K&R\-style list of +arguments followed by their declarations is also provided, inside +comments, after the declaration. +.IP "\fB\-fallow\-parameterless\-variadic\-functions\fR" 4 +.IX Item "-fallow-parameterless-variadic-functions" +Accept variadic functions without named parameters. +.Sp +Although it is possible to define such a function, this is not very +useful as it is not possible to read the arguments. This is only +supported for C as this construct is allowed by \*(C+. +.IP "\fB\-fno\-asm\fR" 4 +.IX Item "-fno-asm" +Do not recognize \f(CW\*(C`asm\*(C'\fR, \f(CW\*(C`inline\*(C'\fR or \f(CW\*(C`typeof\*(C'\fR as a +keyword, so that code can use these words as identifiers. You can use +the keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR +instead. \fB\-ansi\fR implies \fB\-fno\-asm\fR. +.Sp +In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since +\&\f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`inline\*(C'\fR are standard keywords. You may want to +use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same +effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this +switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since +\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO C99.\s0 +.IP "\fB\-fno\-builtin\fR" 4 +.IX Item "-fno-builtin" +.PD 0 +.IP "\fB\-fno\-builtin\-\fR\fIfunction\fR" 4 +.IX Item "-fno-builtin-function" +.PD +Don't recognize built-in functions that do not begin with +\&\fB_\|_builtin_\fR as prefix. +.Sp +\&\s-1GCC\s0 normally generates special code to handle certain built-in functions +more efficiently; for instance, calls to \f(CW\*(C`alloca\*(C'\fR may become single +instructions which adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\fR +may become inline copy loops. The resulting code is often both smaller +and faster, but since the function calls no longer appear as such, you +cannot set a breakpoint on those calls, nor can you change the behavior +of the functions by linking with a different library. In addition, +when a function is recognized as a built-in function, \s-1GCC\s0 may use +information about that function to warn about problems with calls to +that function, or to generate more efficient code, even if the +resulting code still contains calls to that function. For example, +warnings are given with \fB\-Wformat\fR for bad calls to +\&\f(CW\*(C`printf\*(C'\fR when \f(CW\*(C`printf\*(C'\fR is built in and \f(CW\*(C`strlen\*(C'\fR is +known not to modify global memory. +.Sp +With the \fB\-fno\-builtin\-\fR\fIfunction\fR option +only the built-in function \fIfunction\fR is +disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a +function is named that is not built-in in this version of \s-1GCC,\s0 this +option is ignored. There is no corresponding +\&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable +built-in functions selectively when using \fB\-fno\-builtin\fR or +\&\fB\-ffreestanding\fR, you may define macros such as: +.Sp +.Vb 2 +\& #define abs(n) _\|_builtin_abs ((n)) +\& #define strcpy(d, s) _\|_builtin_strcpy ((d), (s)) +.Ve +.IP "\fB\-fgimple\fR" 4 +.IX Item "-fgimple" +Enable parsing of function definitions marked with \f(CW\*(C`_\|_GIMPLE\*(C'\fR. +This is an experimental feature that allows unit testing of \s-1GIMPLE\s0 +passes. +.IP "\fB\-fhosted\fR" 4 +.IX Item "-fhosted" +Assert that compilation targets a hosted environment. This implies +\&\fB\-fbuiltin\fR. A hosted environment is one in which the +entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return +type of \f(CW\*(C`int\*(C'\fR. Examples are nearly everything except a kernel. +This is equivalent to \fB\-fno\-freestanding\fR. +.IP "\fB\-ffreestanding\fR" 4 +.IX Item "-ffreestanding" +Assert that compilation targets a freestanding environment. This +implies \fB\-fno\-builtin\fR. A freestanding environment +is one in which the standard library may not exist, and program startup may +not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel. +This is equivalent to \fB\-fno\-hosted\fR. +.IP "\fB\-fopenacc\fR" 4 +.IX Item "-fopenacc" +Enable handling of OpenACC directives \f(CW\*(C`#pragma acc\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$acc\*(C'\fR in Fortran. When \fB\-fopenacc\fR is specified, the +compiler generates accelerated code according to the OpenACC Application +Programming Interface v2.0 <\fBhttps://www.openacc.org\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. +.IP "\fB\-fopenacc\-dim=\fR\fIgeom\fR" 4 +.IX Item "-fopenacc-dim=geom" +Specify default compute dimensions for parallel offload regions that do +not explicitly specify. The \fIgeom\fR value is a triple of +\&':'\-separated sizes, in order 'gang', 'worker' and, 'vector'. A size +can be omitted, to use a target-specific default value. +.IP "\fB\-fopenmp\fR" 4 +.IX Item "-fopenmp" +Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$omp\*(C'\fR in Fortran. When \fB\-fopenmp\fR is specified, the +compiler generates parallel code according to the OpenMP Application +Program Interface v4.5 <\fBhttps://www.openmp.org\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. \fB\-fopenmp\fR implies +\&\fB\-fopenmp\-simd\fR. +.IP "\fB\-fopenmp\-simd\fR" 4 +.IX Item "-fopenmp-simd" +Enable handling of OpenMP's \s-1SIMD\s0 directives with \f(CW\*(C`#pragma omp\*(C'\fR +in C/\*(C+ and \f(CW\*(C`!$omp\*(C'\fR in Fortran. Other OpenMP directives +are ignored. +.IP "\fB\-fgnu\-tm\fR" 4 +.IX Item "-fgnu-tm" +When the option \fB\-fgnu\-tm\fR is specified, the compiler +generates code for the Linux variant of Intel's current Transactional +Memory \s-1ABI\s0 specification document (Revision 1.1, May 6 2009). This is +an experimental feature whose interface may change in future versions +of \s-1GCC,\s0 as the official specification changes. Please note that not +all architectures are supported for this feature. +.Sp +For more information on \s-1GCC\s0's support for transactional memory, +.Sp +Note that the transactional memory feature is not supported with +non-call exceptions (\fB\-fnon\-call\-exceptions\fR). +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Accept some non-standard constructs used in Microsoft header files. +.Sp +In \*(C+ code, this allows member names in structures to be similar +to previous types declarations. +.Sp +.Vb 4 +\& typedef int UOW; +\& struct ABC { +\& UOW UOW; +\& }; +.Ve +.Sp +Some cases of unnamed fields in structures and unions are only +accepted with this option. +.Sp +Note that this option is off for all targets but x86 +targets using ms-abi. +.IP "\fB\-fplan9\-extensions\fR" 4 +.IX Item "-fplan9-extensions" +Accept some non-standard constructs used in Plan 9 code. +.Sp +This enables \fB\-fms\-extensions\fR, permits passing pointers to +structures with anonymous fields to functions that expect pointers to +elements of the type of the field, and permits referring to anonymous +fields declared using a typedef. This is only +supported for C, not \*(C+. +.IP "\fB\-fcond\-mismatch\fR" 4 +.IX Item "-fcond-mismatch" +Allow conditional expressions with mismatched types in the second and +third arguments. The value of such an expression is void. This option +is not supported for \*(C+. +.IP "\fB\-flax\-vector\-conversions\fR" 4 +.IX Item "-flax-vector-conversions" +Allow implicit conversions between vectors with differing numbers of +elements and/or incompatible element types. This option should not be +used for new code. +.IP "\fB\-funsigned\-char\fR" 4 +.IX Item "-funsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be unsigned, like \f(CW\*(C`unsigned char\*(C'\fR. +.Sp +Each kind of machine has a default for what \f(CW\*(C`char\*(C'\fR should +be. It is either like \f(CW\*(C`unsigned char\*(C'\fR by default or like +\&\f(CW\*(C`signed char\*(C'\fR by default. +.Sp +Ideally, a portable program should always use \f(CW\*(C`signed char\*(C'\fR or +\&\f(CW\*(C`unsigned char\*(C'\fR when it depends on the signedness of an object. +But many programs have been written to use plain \f(CW\*(C`char\*(C'\fR and +expect it to be signed, or expect it to be unsigned, depending on the +machines they were written for. This option, and its inverse, let you +make such a program work with the opposite default. +.Sp +The type \f(CW\*(C`char\*(C'\fR is always a distinct type from each of +\&\f(CW\*(C`signed char\*(C'\fR or \f(CW\*(C`unsigned char\*(C'\fR, even though its behavior +is always just like one of those two. +.IP "\fB\-fsigned\-char\fR" 4 +.IX Item "-fsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be signed, like \f(CW\*(C`signed char\*(C'\fR. +.Sp +Note that this is equivalent to \fB\-fno\-unsigned\-char\fR, which is +the negative form of \fB\-funsigned\-char\fR. Likewise, the option +\&\fB\-fno\-signed\-char\fR is equivalent to \fB\-funsigned\-char\fR. +.IP "\fB\-fsigned\-bitfields\fR" 4 +.IX Item "-fsigned-bitfields" +.PD 0 +.IP "\fB\-funsigned\-bitfields\fR" 4 +.IX Item "-funsigned-bitfields" +.IP "\fB\-fno\-signed\-bitfields\fR" 4 +.IX Item "-fno-signed-bitfields" +.IP "\fB\-fno\-unsigned\-bitfields\fR" 4 +.IX Item "-fno-unsigned-bitfields" +.PD +These options control whether a bit-field is signed or unsigned, when the +declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By +default, such a bit-field is signed, because this is consistent: the +basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. +.IP "\fB\-fsso\-struct=\fR\fIendianness\fR" 4 +.IX Item "-fsso-struct=endianness" +Set the default scalar storage order of structures and unions to the +specified endianness. The accepted values are \fBbig-endian\fR, +\&\fBlittle-endian\fR and \fBnative\fR for the native endianness of +the target (the default). This option is not supported for \*(C+. +.Sp +\&\fBWarning:\fR the \fB\-fsso\-struct\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without it if the +specified endianness is not the native endianness of the target. +.SS "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" +This section describes the command-line options that are only meaningful +for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options +regardless of what language your program is in. For example, you +might compile a file \fIfirstClass.C\fR like this: +.PP +.Vb 1 +\& g++ \-g \-fstrict\-enums \-O \-c firstClass.C +.Ve +.PP +In this example, only \fB\-fstrict\-enums\fR is an option meant +only for \*(C+ programs; you can use the other options with any +language supported by \s-1GCC.\s0 +.PP +Some options for compiling C programs, such as \fB\-std\fR, are also +relevant for \*(C+ programs. +.PP +Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: +.IP "\fB\-fabi\-version=\fR\fIn\fR" 4 +.IX Item "-fabi-version=n" +Use version \fIn\fR of the \*(C+ \s-1ABI.\s0 The default is version 0. +.Sp +Version 0 refers to the version conforming most closely to +the \*(C+ \s-1ABI\s0 specification. Therefore, the \s-1ABI\s0 obtained using version 0 +will change in different versions of G++ as \s-1ABI\s0 bugs are fixed. +.Sp +Version 1 is the version of the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2. +.Sp +Version 2 is the version of the \*(C+ \s-1ABI\s0 that first appeared in G++ +3.4, and was the default through G++ 4.9. +.Sp +Version 3 corrects an error in mangling a constant address as a +template argument. +.Sp +Version 4, which first appeared in G++ 4.5, implements a standard +mangling for vector types. +.Sp +Version 5, which first appeared in G++ 4.6, corrects the mangling of +attribute const/volatile on function pointer types, decltype of a +plain decl, and use of a function parameter in the declaration of +another parameter. +.Sp +Version 6, which first appeared in G++ 4.7, corrects the promotion +behavior of \*(C+11 scoped enums and the mangling of template argument +packs, const/static_cast, prefix ++ and \-\-, and a class scope function +used as a template argument. +.Sp +Version 7, which first appeared in G++ 4.8, that treats nullptr_t as a +builtin type and corrects the mangling of lambdas in default argument +scope. +.Sp +Version 8, which first appeared in G++ 4.9, corrects the substitution +behavior of function types with function-cv-qualifiers. +.Sp +Version 9, which first appeared in G++ 5.2, corrects the alignment of +\&\f(CW\*(C`nullptr_t\*(C'\fR. +.Sp +Version 10, which first appeared in G++ 6.1, adds mangling of +attributes that affect type identity, such as ia32 calling convention +attributes (e.g. \fBstdcall\fR). +.Sp +Version 11, which first appeared in G++ 7, corrects the mangling of +sizeof... expressions and operator names. For multiple entities with +the same name within a function, that are declared in different scopes, +the mangling now changes starting with the twelfth occurrence. It also +implies \fB\-fnew\-inheriting\-ctors\fR. +.Sp +Version 12, which first appeared in G++ 8, corrects the calling +conventions for empty classes on the x86_64 target and for classes +with only deleted copy/move constructors. It accidentally changes the +calling convention for classes with a deleted copy constructor and a +trivial move constructor. +.Sp +Version 13, which first appeared in G++ 8.2, fixes the accidental +change in version 12. +.Sp +See also \fB\-Wabi\fR. +.IP "\fB\-fabi\-compat\-version=\fR\fIn\fR" 4 +.IX Item "-fabi-compat-version=n" +On targets that support strong aliases, G++ +works around mangling changes by creating an alias with the correct +mangled name when defining a symbol with an incorrect mangled name. +This switch specifies which \s-1ABI\s0 version to use for the alias. +.Sp +With \fB\-fabi\-version=0\fR (the default), this defaults to 11 (\s-1GCC 7\s0 +compatibility). If another \s-1ABI\s0 version is explicitly selected, this +defaults to 0. For compatibility with \s-1GCC\s0 versions 3.2 through 4.9, +use \fB\-fabi\-compat\-version=2\fR. +.Sp +If this option is not provided but \fB\-Wabi=\fR\fIn\fR is, that +version is used for compatibility aliases. If this option is provided +along with \fB\-Wabi\fR (without the version), the version from this +option is used for the warning. +.IP "\fB\-fno\-access\-control\fR" 4 +.IX Item "-fno-access-control" +Turn off all access checking. This switch is mainly useful for working +around bugs in the access control code. +.IP "\fB\-faligned\-new\fR" 4 +.IX Item "-faligned-new" +Enable support for \*(C+17 \f(CW\*(C`new\*(C'\fR of types that require more +alignment than \f(CW\*(C`void* ::operator new(std::size_t)\*(C'\fR provides. A +numeric argument such as \f(CW\*(C`\-faligned\-new=32\*(C'\fR can be used to +specify how much alignment (in bytes) is provided by that function, +but few users will need to override the default of +\&\f(CW\*(C`alignof(std::max_align_t)\*(C'\fR. +.Sp +This flag is enabled by default for \fB\-std=c++17\fR. +.IP "\fB\-fchar8_t\fR" 4 +.IX Item "-fchar8_t" +.PD 0 +.IP "\fB\-fno\-char8_t\fR" 4 +.IX Item "-fno-char8_t" +.PD +Enable support for \f(CW\*(C`char8_t\*(C'\fR as adopted for \*(C+2a. This includes +the addition of a new \f(CW\*(C`char8_t\*(C'\fR fundamental type, changes to the +types of \s-1UTF\-8\s0 string and character literals, new signatures for +user-defined literals, associated standard library updates, and new +\&\f(CW\*(C`_\|_cpp_char8_t\*(C'\fR and \f(CW\*(C`_\|_cpp_lib_char8_t\*(C'\fR feature test macros. +.Sp +This option enables functions to be overloaded for ordinary and \s-1UTF\-8\s0 +strings: +.Sp +.Vb 4 +\& int f(const char *); // #1 +\& int f(const char8_t *); // #2 +\& int v1 = f("text"); // Calls #1 +\& int v2 = f(u8"text"); // Calls #2 +.Ve +.Sp +and introduces new signatures for user-defined literals: +.Sp +.Vb 6 +\& int operator""_udl1(char8_t); +\& int v3 = u8\*(Aqx\*(Aq_udl1; +\& int operator""_udl2(const char8_t*, std::size_t); +\& int v4 = u8"text"_udl2; +\& template int operator""_udl3(); +\& int v5 = u8"text"_udl3; +.Ve +.Sp +The change to the types of \s-1UTF\-8\s0 string and character literals introduces +incompatibilities with \s-1ISO \*(C+11\s0 and later standards. For example, the +following code is well-formed under \s-1ISO \*(C+11,\s0 but is ill-formed when +\&\fB\-fchar8_t\fR is specified. +.Sp +.Vb 10 +\& char ca[] = u8"xx"; // error: char\-array initialized from wide +\& // string +\& const char *cp = u8"xx";// error: invalid conversion from +\& // \`const char8_t*\*(Aq to \`const char*\*(Aq +\& int f(const char*); +\& auto v = f(u8"xx"); // error: invalid conversion from +\& // \`const char8_t*\*(Aq to \`const char*\*(Aq +\& std::string s{u8"xx"}; // error: no matching function for call to +\& // \`std::basic_string::basic_string()\*(Aq +\& using namespace std::literals; +\& s = u8"xx"s; // error: conversion from +\& // \`basic_string\*(Aq to non\-scalar +\& // type \`basic_string\*(Aq requested +.Ve +.IP "\fB\-fcheck\-new\fR" 4 +.IX Item "-fcheck-new" +Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null +before attempting to modify the storage allocated. This check is +normally unnecessary because the \*(C+ standard specifies that +\&\f(CW\*(C`operator new\*(C'\fR only returns \f(CW0\fR if it is declared +\&\f(CW\*(C`throw()\*(C'\fR, in which case the compiler always checks the +return value even without this option. In all other cases, when +\&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory +exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also +\&\fBnew (nothrow)\fR. +.IP "\fB\-fconcepts\fR" 4 +.IX Item "-fconcepts" +Enable support for the \*(C+ Extensions for Concepts Technical +Specification, \s-1ISO 19217\s0 (2015), which allows code like +.Sp +.Vb 2 +\& template concept bool Addable = requires (T t) { t + t; }; +\& template T add (T a, T b) { return a + b; } +.Ve +.IP "\fB\-fconstexpr\-depth=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-depth=n" +Set the maximum nested evaluation depth for \*(C+11 constexpr functions +to \fIn\fR. A limit is needed to detect endless recursion during +constant expression evaluation. The minimum specified by the standard +is 512. +.IP "\fB\-fconstexpr\-loop\-limit=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-loop-limit=n" +Set the maximum number of iterations for a loop in \*(C+14 constexpr functions +to \fIn\fR. A limit is needed to detect infinite loops during +constant expression evaluation. The default is 262144 (1<<18). +.IP "\fB\-fconstexpr\-ops\-limit=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-ops-limit=n" +Set the maximum number of operations during a single constexpr evaluation. +Even when number of iterations of a single loop is limited with the above limit, +if there are several nested loops and each of them has many iterations but still +smaller than the above limit, or if in a body of some loop or even outside +of a loop too many expressions need to be evaluated, the resulting constexpr +evaluation might take too long. +The default is 33554432 (1<<25). +.IP "\fB\-fdeduce\-init\-list\fR" 4 +.IX Item "-fdeduce-init-list" +Enable deduction of a template type parameter as +\&\f(CW\*(C`std::initializer_list\*(C'\fR from a brace-enclosed initializer list, i.e. +.Sp +.Vb 4 +\& template auto forward(T t) \-> decltype (realfn (t)) +\& { +\& return realfn (t); +\& } +\& +\& void f() +\& { +\& forward({1,2}); // call forward> +\& } +.Ve +.Sp +This deduction was implemented as a possible extension to the +originally proposed semantics for the \*(C+11 standard, but was not part +of the final standard, so it is disabled by default. This option is +deprecated, and may be removed in a future version of G++. +.IP "\fB\-fno\-elide\-constructors\fR" 4 +.IX Item "-fno-elide-constructors" +The \*(C+ standard allows an implementation to omit creating a temporary +that is only used to initialize another object of the same type. +Specifying this option disables that optimization, and forces G++ to +call the copy constructor in all cases. This option also causes G++ +to call trivial member functions which otherwise would be expanded inline. +.Sp +In \*(C+17, the compiler is required to omit these temporaries, but this +option still affects trivial member functions. +.IP "\fB\-fno\-enforce\-eh\-specs\fR" 4 +.IX Item "-fno-enforce-eh-specs" +Don't generate code to check for violation of exception specifications +at run time. This option violates the \*(C+ standard, but may be useful +for reducing code size in production builds, much like defining +\&\f(CW\*(C`NDEBUG\*(C'\fR. This does not give user code permission to throw +exceptions in violation of the exception specifications; the compiler +still optimizes based on the specifications, so throwing an +unexpected exception results in undefined behavior at run time. +.IP "\fB\-fextern\-tls\-init\fR" 4 +.IX Item "-fextern-tls-init" +.PD 0 +.IP "\fB\-fno\-extern\-tls\-init\fR" 4 +.IX Item "-fno-extern-tls-init" +.PD +The \*(C+11 and OpenMP standards allow \f(CW\*(C`thread_local\*(C'\fR and +\&\f(CW\*(C`threadprivate\*(C'\fR variables to have dynamic (runtime) +initialization. To support this, any use of such a variable goes +through a wrapper function that performs any necessary initialization. +When the use and definition of the variable are in the same +translation unit, this overhead can be optimized away, but when the +use is in a different translation unit there is significant overhead +even if the variable doesn't actually need dynamic initialization. If +the programmer can be sure that no use of the variable in a +non-defining \s-1TU\s0 needs to trigger dynamic initialization (either +because the variable is statically initialized, or a use of the +variable in the defining \s-1TU\s0 will be executed before any uses in +another \s-1TU\s0), they can avoid this overhead with the +\&\fB\-fno\-extern\-tls\-init\fR option. +.Sp +On targets that support symbol aliases, the default is +\&\fB\-fextern\-tls\-init\fR. On targets that do not support symbol +aliases, the default is \fB\-fno\-extern\-tls\-init\fR. +.IP "\fB\-fno\-gnu\-keywords\fR" 4 +.IX Item "-fno-gnu-keywords" +Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this +word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead. +This option is implied by the strict \s-1ISO \*(C+\s0 dialects: \fB\-ansi\fR, +\&\fB\-std=c++98\fR, \fB\-std=c++11\fR, etc. +.IP "\fB\-fno\-implicit\-templates\fR" 4 +.IX Item "-fno-implicit-templates" +Never emit code for non-inline templates that are instantiated +implicitly (i.e. by use); only emit code for explicit instantiations. +If you use this option, you must take care to structure your code to +include all the necessary explicit instantiations to avoid getting +undefined symbols at link time. +.IP "\fB\-fno\-implicit\-inline\-templates\fR" 4 +.IX Item "-fno-implicit-inline-templates" +Don't emit code for implicit instantiations of inline templates, either. +The default is to handle inlines differently so that compiles with and +without optimization need the same set of explicit instantiations. +.IP "\fB\-fno\-implement\-inlines\fR" 4 +.IX Item "-fno-implement-inlines" +To save space, do not emit out-of-line copies of inline functions +controlled by \f(CW\*(C`#pragma implementation\*(C'\fR. This causes linker +errors if these functions are not inlined everywhere they are called. +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Disable Wpedantic warnings about constructs used in \s-1MFC,\s0 such as implicit +int and getting a pointer to member function via non-standard syntax. +.IP "\fB\-fnew\-inheriting\-ctors\fR" 4 +.IX Item "-fnew-inheriting-ctors" +Enable the P0136 adjustment to the semantics of \*(C+11 constructor +inheritance. This is part of \*(C+17 but also considered to be a Defect +Report against \*(C+11 and \*(C+14. This flag is enabled by default +unless \fB\-fabi\-version=10\fR or lower is specified. +.IP "\fB\-fnew\-ttp\-matching\fR" 4 +.IX Item "-fnew-ttp-matching" +Enable the P0522 resolution to Core issue 150, template template +parameters and default arguments: this allows a template with default +template arguments as an argument for a template template parameter +with fewer template parameters. This flag is enabled by default for +\&\fB\-std=c++17\fR. +.IP "\fB\-fno\-nonansi\-builtins\fR" 4 +.IX Item "-fno-nonansi-builtins" +Disable built-in declarations of functions that are not mandated by +\&\s-1ANSI/ISO C.\s0 These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. +.IP "\fB\-fnothrow\-opt\fR" 4 +.IX Item "-fnothrow-opt" +Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as if it were a +\&\f(CW\*(C`noexcept\*(C'\fR specification to reduce or eliminate the text size +overhead relative to a function with no exception specification. If +the function has local variables of types with non-trivial +destructors, the exception specification actually makes the +function smaller because the \s-1EH\s0 cleanups for those variables can be +optimized away. The semantic effect is that an exception thrown out of +a function with such an exception specification results in a call +to \f(CW\*(C`terminate\*(C'\fR rather than \f(CW\*(C`unexpected\*(C'\fR. +.IP "\fB\-fno\-operator\-names\fR" 4 +.IX Item "-fno-operator-names" +Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR, +\&\f(CW\*(C`bitor\*(C'\fR, \f(CW\*(C`compl\*(C'\fR, \f(CW\*(C`not\*(C'\fR, \f(CW\*(C`or\*(C'\fR and \f(CW\*(C`xor\*(C'\fR as +synonyms as keywords. +.IP "\fB\-fno\-optional\-diags\fR" 4 +.IX Item "-fno-optional-diags" +Disable diagnostics that the standard says a compiler does not need to +issue. Currently, the only such diagnostic issued by G++ is the one for +a name having multiple meanings within a class. +.IP "\fB\-fpermissive\fR" 4 +.IX Item "-fpermissive" +Downgrade some diagnostics about nonconformant code from errors to +warnings. Thus, using \fB\-fpermissive\fR allows some +nonconforming code to compile. +.IP "\fB\-fno\-pretty\-templates\fR" 4 +.IX Item "-fno-pretty-templates" +When an error message refers to a specialization of a function +template, the compiler normally prints the signature of the +template followed by the template arguments and any typedefs or +typenames in the signature (e.g. \f(CW\*(C`void f(T) [with T = int]\*(C'\fR +rather than \f(CW\*(C`void f(int)\*(C'\fR) so that it's clear which template is +involved. When an error message refers to a specialization of a class +template, the compiler omits any template arguments that match +the default template arguments for that template. If either of these +behaviors make it harder to understand the error message rather than +easier, you can use \fB\-fno\-pretty\-templates\fR to disable them. +.IP "\fB\-frepo\fR" 4 +.IX Item "-frepo" +Enable automatic template instantiation at link time. This option also +implies \fB\-fno\-implicit\-templates\fR. +.IP "\fB\-fno\-rtti\fR" 4 +.IX Item "-fno-rtti" +Disable generation of information about every class with virtual +functions for use by the \*(C+ run-time type identification features +(\f(CW\*(C`dynamic_cast\*(C'\fR and \f(CW\*(C`typeid\*(C'\fR). If you don't use those parts +of the language, you can save some space by using this flag. Note that +exception handling uses the same information, but G++ generates it as +needed. The \f(CW\*(C`dynamic_cast\*(C'\fR operator can still be used for casts that +do not require run-time type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to +unambiguous base classes. +.Sp +Mixing code compiled with \fB\-frtti\fR with that compiled with +\&\fB\-fno\-rtti\fR may not work. For example, programs may +fail to link if a class compiled with \fB\-fno\-rtti\fR is used as a base +for a class compiled with \fB\-frtti\fR. +.IP "\fB\-fsized\-deallocation\fR" 4 +.IX Item "-fsized-deallocation" +Enable the built-in global declarations +.Sp +.Vb 2 +\& void operator delete (void *, std::size_t) noexcept; +\& void operator delete[] (void *, std::size_t) noexcept; +.Ve +.Sp +as introduced in \*(C+14. This is useful for user-defined replacement +deallocation functions that, for example, use the size of the object +to make deallocation faster. Enabled by default under +\&\fB\-std=c++14\fR and above. The flag \fB\-Wsized\-deallocation\fR +warns about places that might want to add a definition. +.IP "\fB\-fstrict\-enums\fR" 4 +.IX Item "-fstrict-enums" +Allow the compiler to optimize using the assumption that a value of +enumerated type can only be one of the values of the enumeration (as +defined in the \*(C+ standard; basically, a value that can be +represented in the minimum number of bits needed to represent all the +enumerators). This assumption may not be valid if the program uses a +cast to convert an arbitrary integer value to the enumerated type. +.IP "\fB\-fstrong\-eval\-order\fR" 4 +.IX Item "-fstrong-eval-order" +Evaluate member access, array subscripting, and shift expressions in +left-to-right order, and evaluate assignment in right-to-left order, +as adopted for \*(C+17. Enabled by default with \fB\-std=c++17\fR. +\&\fB\-fstrong\-eval\-order=some\fR enables just the ordering of member +access and shift expressions, and is the default without +\&\fB\-std=c++17\fR. +.IP "\fB\-ftemplate\-backtrace\-limit=\fR\fIn\fR" 4 +.IX Item "-ftemplate-backtrace-limit=n" +Set the maximum number of template instantiation notes for a single +warning or error to \fIn\fR. The default value is 10. +.IP "\fB\-ftemplate\-depth=\fR\fIn\fR" 4 +.IX Item "-ftemplate-depth=n" +Set the maximum instantiation depth for template classes to \fIn\fR. +A limit on the template instantiation depth is needed to detect +endless recursions during template class instantiation. \s-1ANSI/ISO \*(C+\s0 +conforming programs must not rely on a maximum depth greater than 17 +(changed to 1024 in \*(C+11). The default value is 900, as the compiler +can run out of stack space before hitting 1024 in some situations. +.IP "\fB\-fno\-threadsafe\-statics\fR" 4 +.IX Item "-fno-threadsafe-statics" +Do not emit the extra code to use the routines specified in the \*(C+ +\&\s-1ABI\s0 for thread-safe initialization of local statics. You can use this +option to reduce code size slightly in code that doesn't need to be +thread-safe. +.IP "\fB\-fuse\-cxa\-atexit\fR" 4 +.IX Item "-fuse-cxa-atexit" +Register destructors for objects with static storage duration with the +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function. +This option is required for fully standards-compliant handling of static +destructors, but only works if your C library supports +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR. +.IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4 +.IX Item "-fno-use-cxa-get-exception-ptr" +Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This +causes \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary +if the runtime routine is not available. +.IP "\fB\-fvisibility\-inlines\-hidden\fR" 4 +.IX Item "-fvisibility-inlines-hidden" +This switch declares that the user does not attempt to compare +pointers to inline functions or methods where the addresses of the two functions +are taken in different shared objects. +.Sp +The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with +\&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not +appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection +when used within the \s-1DSO.\s0 Enabling this option can have a dramatic effect +on load and link times of a \s-1DSO\s0 as it massively reduces the size of the +dynamic export table when the library makes heavy use of templates. +.Sp +The behavior of this switch is not quite the same as marking the +methods as hidden directly, because it does not affect static variables +local to the function or cause the compiler to deduce that +the function is defined in only one shared object. +.Sp +You may mark a method as having a visibility explicitly to negate the +effect of the switch for that method. For example, if you do want to +compare pointers to a particular inline method, you might mark it as +having default visibility. Marking the enclosing class with explicit +visibility has no effect. +.Sp +Explicitly instantiated inline methods are unaffected by this option +as their linkage might otherwise cross a shared library boundary. +.IP "\fB\-fvisibility\-ms\-compat\fR" 4 +.IX Item "-fvisibility-ms-compat" +This flag attempts to use visibility settings to make \s-1GCC\s0's \*(C+ +linkage model compatible with that of Microsoft Visual Studio. +.Sp +The flag makes these changes to \s-1GCC\s0's linkage model: +.RS 4 +.IP "1." 4 +.IX Item "1." +It sets the default visibility to \f(CW\*(C`hidden\*(C'\fR, like +\&\fB\-fvisibility=hidden\fR. +.IP "2." 4 +.IX Item "2." +Types, but not their members, are not hidden by default. +.IP "3." 4 +.IX Item "3." +The One Definition Rule is relaxed for types without explicit +visibility specifications that are defined in more than one +shared object: those declarations are permitted if they are +permitted when this option is not used. +.RE +.RS 4 +.Sp +In new code it is better to use \fB\-fvisibility=hidden\fR and +export those classes that are intended to be externally visible. +Unfortunately it is possible for code to rely, perhaps accidentally, +on the Visual Studio behavior. +.Sp +Among the consequences of these changes are that static data members +of the same type with the same name but defined in different shared +objects are different, so changing one does not change the other; +and that pointers to function members defined in different shared +objects may not compare equal. When this flag is given, it is a +violation of the \s-1ODR\s0 to define types with the same name differently. +.RE +.IP "\fB\-fno\-weak\fR" 4 +.IX Item "-fno-weak" +Do not use weak symbol support, even if it is provided by the linker. +By default, G++ uses weak symbols if they are available. This +option exists only for testing, and should not be used by end-users; +it results in inferior code and has no benefits. This option may +be removed in a future release of G++. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the standard directories specific to +\&\*(C+, but do still search the other standard directories. (This option +is used when building the \*(C+ library.) +.PP +In addition, these optimization, warning, and code generation options +have meanings only for \*(C+ programs: +.IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi (C, Objective-C, and Objective- only)" +Warn when G++ it generates code that is probably not compatible with +the vendor-neutral \*(C+ \s-1ABI.\s0 Since G++ now defaults to updating the +\&\s-1ABI\s0 with each major release, normally \fB\-Wabi\fR will warn only if +there is a check added later in a release series for an \s-1ABI\s0 issue +discovered since the initial release. \fB\-Wabi\fR will warn about +more things if an older \s-1ABI\s0 version is selected (with +\&\fB\-fabi\-version=\fR\fIn\fR). +.Sp +\&\fB\-Wabi\fR can also be used with an explicit version number to +warn about compatibility with a particular \fB\-fabi\-version\fR +level, e.g. \fB\-Wabi=2\fR to warn about changes relative to +\&\fB\-fabi\-version=2\fR. +.Sp +If an explicit version number is provided and +\&\fB\-fabi\-compat\-version\fR is not specified, the version number +from this option is used for compatibility aliases. If no explicit +version number is provided with this option, but +\&\fB\-fabi\-compat\-version\fR is specified, that version number is +used for \s-1ABI\s0 warnings. +.Sp +Although an effort has been made to warn about +all such cases, there are probably some cases that are not warned about, +even though G++ is generating incompatible code. There may also be +cases where warnings are emitted even though the code that is generated +is compatible. +.Sp +You should rewrite your code to avoid these warnings if you are +concerned about the fact that code generated by G++ may not be binary +compatible with code generated by other compilers. +.Sp +Known incompatibilities in \fB\-fabi\-version=2\fR (which was the +default from \s-1GCC 3.4\s0 to 4.9) include: +.RS 4 +.IP "*" 4 +A template with a non-type template parameter of reference type was +mangled incorrectly: +.Sp +.Vb 3 +\& extern int N; +\& template struct S {}; +\& void n (S) {2} +.Ve +.Sp +This was fixed in \fB\-fabi\-version=3\fR. +.IP "*" 4 +\&\s-1SIMD\s0 vector types declared using \f(CW\*(C`_\|_attribute ((vector_size))\*(C'\fR were +mangled in a non-standard way that does not allow for overloading of +functions taking vectors of different sizes. +.Sp +The mangling was changed in \fB\-fabi\-version=4\fR. +.IP "*" 4 +\&\f(CW\*(C`_\|_attribute ((const))\*(C'\fR and \f(CW\*(C`noreturn\*(C'\fR were mangled as type +qualifiers, and \f(CW\*(C`decltype\*(C'\fR of a plain declaration was folded away. +.Sp +These mangling issues were fixed in \fB\-fabi\-version=5\fR. +.IP "*" 4 +Scoped enumerators passed as arguments to a variadic function are +promoted like unscoped enumerators, causing \f(CW\*(C`va_arg\*(C'\fR to complain. +On most targets this does not actually affect the parameter passing +\&\s-1ABI,\s0 as there is no way to pass an argument smaller than \f(CW\*(C`int\*(C'\fR. +.Sp +Also, the \s-1ABI\s0 changed the mangling of template argument packs, +\&\f(CW\*(C`const_cast\*(C'\fR, \f(CW\*(C`static_cast\*(C'\fR, prefix increment/decrement, and +a class scope function used as a template argument. +.Sp +These issues were corrected in \fB\-fabi\-version=6\fR. +.IP "*" 4 +Lambdas in default argument scope were mangled incorrectly, and the +\&\s-1ABI\s0 changed the mangling of \f(CW\*(C`nullptr_t\*(C'\fR. +.Sp +These issues were corrected in \fB\-fabi\-version=7\fR. +.IP "*" 4 +When mangling a function type with function-cv-qualifiers, the +un-qualified function type was incorrectly treated as a substitution +candidate. +.Sp +This was fixed in \fB\-fabi\-version=8\fR, the default for \s-1GCC 5.1.\s0 +.IP "*" 4 +\&\f(CW\*(C`decltype(nullptr)\*(C'\fR incorrectly had an alignment of 1, leading to +unaligned accesses. Note that this did not affect the \s-1ABI\s0 of a +function with a \f(CW\*(C`nullptr_t\*(C'\fR parameter, as parameters have a +minimum alignment. +.Sp +This was fixed in \fB\-fabi\-version=9\fR, the default for \s-1GCC 5.2.\s0 +.IP "*" 4 +Target-specific attributes that affect the identity of a type, such as +ia32 calling conventions on a function type (stdcall, regparm, etc.), +did not affect the mangled name, leading to name collisions when +function pointers were used as template arguments. +.Sp +This was fixed in \fB\-fabi\-version=10\fR, the default for \s-1GCC 6.1.\s0 +.RE +.RS 4 +.Sp +It also warns about psABI-related changes. The known psABI changes at this +point include: +.IP "*" 4 +For SysV/x86\-64, unions with \f(CW\*(C`long double\*(C'\fR members are +passed in memory as specified in psABI. For example: +.Sp +.Vb 4 +\& union U { +\& long double ld; +\& int i; +\& }; +.Ve +.Sp +\&\f(CW\*(C`union U\*(C'\fR is always passed in memory. +.RE +.RS 4 +.RE +.IP "\fB\-Wabi\-tag\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi-tag ( and Objective- only)" +Warn when a type with an \s-1ABI\s0 tag is used in a context that does not +have that \s-1ABI\s0 tag. See \fB\*(C+ Attributes\fR for more information +about \s-1ABI\s0 tags. +.IP "\fB\-Wctor\-dtor\-privacy\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wctor-dtor-privacy ( and Objective- only)" +Warn when a class seems unusable because all the constructors or +destructors in that class are private, and it has neither friends nor +public static member functions. Also warn if there are no non-private +methods, and there's at least one private member function that isn't +a constructor or destructor. +.IP "\fB\-Wdelete\-non\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wdelete-non-virtual-dtor ( and Objective- only)" +Warn when \f(CW\*(C`delete\*(C'\fR is used to destroy an instance of a class that +has virtual functions and non-virtual destructor. It is unsafe to delete +an instance of a derived class through a pointer to a base class if the +base class does not have a virtual destructor. This warning is enabled +by \fB\-Wall\fR. +.IP "\fB\-Wdeprecated\-copy\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wdeprecated-copy ( and Objective- only)" +Warn that the implicit declaration of a copy constructor or copy +assignment operator is deprecated if the class has a user-provided +copy constructor or copy assignment operator, in \*(C+11 and up. This +warning is enabled by \fB\-Wextra\fR. With +\&\fB\-Wdeprecated\-copy\-dtor\fR, also deprecate if the class has a +user-provided destructor. +.IP "\fB\-Wno\-init\-list\-lifetime\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-init-list-lifetime ( and Objective- only)" +Do not warn about uses of \f(CW\*(C`std::initializer_list\*(C'\fR that are likely +to result in dangling pointers. Since the underlying array for an +\&\f(CW\*(C`initializer_list\*(C'\fR is handled like a normal \*(C+ temporary object, +it is easy to inadvertently keep a pointer to the array past the end +of the array's lifetime. For example: +.RS 4 +.IP "*" 4 +If a function returns a temporary \f(CW\*(C`initializer_list\*(C'\fR, or a local +\&\f(CW\*(C`initializer_list\*(C'\fR variable, the array's lifetime ends at the end +of the return statement, so the value returned has a dangling pointer. +.IP "*" 4 +If a new-expression creates an \f(CW\*(C`initializer_list\*(C'\fR, the array only +lives until the end of the enclosing full-expression, so the +\&\f(CW\*(C`initializer_list\*(C'\fR in the heap has a dangling pointer. +.IP "*" 4 +When an \f(CW\*(C`initializer_list\*(C'\fR variable is assigned from a +brace-enclosed initializer list, the temporary array created for the +right side of the assignment only lives until the end of the +full-expression, so at the next statement the \f(CW\*(C`initializer_list\*(C'\fR +variable has a dangling pointer. +.Sp +.Vb 6 +\& // li\*(Aqs initial underlying array lives as long as li +\& std::initializer_list li = { 1,2,3 }; +\& // assignment changes li to point to a temporary array +\& li = { 4, 5 }; +\& // now the temporary is gone and li has a dangling pointer +\& int i = li.begin()[0] // undefined behavior +.Ve +.IP "*" 4 +When a list constructor stores the \f(CW\*(C`begin\*(C'\fR pointer from the +\&\f(CW\*(C`initializer_list\*(C'\fR argument, this doesn't extend the lifetime of +the array, so if a class variable is constructed from a temporary +\&\f(CW\*(C`initializer_list\*(C'\fR, the pointer is left dangling by the end of +the variable declaration statement. +.RE +.RS 4 +.RE +.IP "\fB\-Wliteral\-suffix\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wliteral-suffix ( and Objective- only)" +Warn when a string or character literal is followed by a ud-suffix which does +not begin with an underscore. As a conforming extension, \s-1GCC\s0 treats such +suffixes as separate preprocessing tokens in order to maintain backwards +compatibility with code that uses formatting macros from \f(CW\*(C`\*(C'\fR. +For example: +.Sp +.Vb 3 +\& #define _\|_STDC_FORMAT_MACROS +\& #include +\& #include +\& +\& int main() { +\& int64_t i64 = 123; +\& printf("My int64: %" PRId64"\en", i64); +\& } +.Ve +.Sp +In this case, \f(CW\*(C`PRId64\*(C'\fR is treated as a separate preprocessing token. +.Sp +Additionally, warn when a user-defined literal operator is declared with +a literal suffix identifier that doesn't begin with an underscore. Literal +suffix identifiers that don't begin with an underscore are reserved for +future standardization. +.Sp +This warning is enabled by default. +.IP "\fB\-Wlto\-type\-mismatch\fR" 4 +.IX Item "-Wlto-type-mismatch" +During the link-time optimization warn about type mismatches in +global declarations from different compilation units. +Requires \fB\-flto\fR to be enabled. Enabled by default. +.IP "\fB\-Wno\-narrowing\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-narrowing ( and Objective- only)" +For \*(C+11 and later standards, narrowing conversions are diagnosed by default, +as required by the standard. A narrowing conversion from a constant produces +an error, and a narrowing conversion from a non-constant produces a warning, +but \fB\-Wno\-narrowing\fR suppresses the diagnostic. +Note that this does not affect the meaning of well-formed code; +narrowing conversions are still considered ill-formed in \s-1SFINAE\s0 contexts. +.Sp +With \fB\-Wnarrowing\fR in \*(C+98, warn when a narrowing +conversion prohibited by \*(C+11 occurs within +\&\fB{ }\fR, e.g. +.Sp +.Vb 1 +\& int i = { 2.2 }; // error: narrowing from double to int +.Ve +.Sp +This flag is included in \fB\-Wall\fR and \fB\-Wc++11\-compat\fR. +.IP "\fB\-Wnoexcept\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnoexcept ( and Objective- only)" +Warn when a noexcept-expression evaluates to false because of a call +to a function that does not have a non-throwing exception +specification (i.e. \f(CW\*(C`throw()\*(C'\fR or \f(CW\*(C`noexcept\*(C'\fR) but is known by +the compiler to never throw an exception. +.IP "\fB\-Wnoexcept\-type\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnoexcept-type ( and Objective- only)" +Warn if the \*(C+17 feature making \f(CW\*(C`noexcept\*(C'\fR part of a function +type changes the mangled name of a symbol relative to \*(C+14. Enabled +by \fB\-Wabi\fR and \fB\-Wc++17\-compat\fR. +.Sp +As an example: +.Sp +.Vb 3 +\& template void f(T t) { t(); }; +\& void g() noexcept; +\& void h() { f(g); } +.Ve +.Sp +In \*(C+14, \f(CW\*(C`f\*(C'\fR calls \f(CW\*(C`f\*(C'\fR, but in +\&\*(C+17 it calls \f(CW\*(C`f\*(C'\fR. +.IP "\fB\-Wclass\-memaccess\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wclass-memaccess ( and Objective- only)" +Warn when the destination of a call to a raw memory function such as +\&\f(CW\*(C`memset\*(C'\fR or \f(CW\*(C`memcpy\*(C'\fR is an object of class type, and when writing +into such an object might bypass the class non-trivial or deleted constructor +or copy assignment, violate const-correctness or encapsulation, or corrupt +virtual table pointers. Modifying the representation of such objects may +violate invariants maintained by member functions of the class. For example, +the call to \f(CW\*(C`memset\*(C'\fR below is undefined because it modifies a non-trivial +class object and is, therefore, diagnosed. The safe way to either initialize +or clear the storage of objects of such types is by using the appropriate +constructor or assignment operator, if one is available. +.Sp +.Vb 2 +\& std::string str = "abc"; +\& memset (&str, 0, sizeof str); +.Ve +.Sp +The \fB\-Wclass\-memaccess\fR option is enabled by \fB\-Wall\fR. +Explicitly casting the pointer to the class object to \f(CW\*(C`void *\*(C'\fR or +to a type that can be safely accessed by the raw memory function suppresses +the warning. +.IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnon-virtual-dtor ( and Objective- only)" +Warn when a class has virtual functions and an accessible non-virtual +destructor itself or in an accessible polymorphic base class, in which +case it is possible but unsafe to delete an instance of a derived +class through a pointer to the class itself or base class. This +warning is automatically enabled if \fB\-Weffc++\fR is specified. +.IP "\fB\-Wregister\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wregister ( and Objective- only)" +Warn on uses of the \f(CW\*(C`register\*(C'\fR storage class specifier, except +when it is part of the \s-1GNU\s0 \fBExplicit Register Variables\fR extension. +The use of the \f(CW\*(C`register\*(C'\fR keyword as storage class specifier has +been deprecated in \*(C+11 and removed in \*(C+17. +Enabled by default with \fB\-std=c++17\fR. +.IP "\fB\-Wreorder\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wreorder ( and Objective- only)" +Warn when the order of member initializers given in the code does not +match the order in which they must be executed. For instance: +.Sp +.Vb 5 +\& struct A { +\& int i; +\& int j; +\& A(): j (0), i (1) { } +\& }; +.Ve +.Sp +The compiler rearranges the member initializers for \f(CW\*(C`i\*(C'\fR +and \f(CW\*(C`j\*(C'\fR to match the declaration order of the members, emitting +a warning to that effect. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-pessimizing\-move\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-pessimizing-move ( and Objective- only)" +This warning warns when a call to \f(CW\*(C`std::move\*(C'\fR prevents copy +elision. A typical scenario when copy elision can occur is when returning in +a function with a class return type, when the expression being returned is the +name of a non-volatile automatic object, and is not a function parameter, and +has the same type as the function return type. +.Sp +.Vb 9 +\& struct T { +\& ... +\& }; +\& T fn() +\& { +\& T t; +\& ... +\& return std::move (t); +\& } +.Ve +.Sp +But in this example, the \f(CW\*(C`std::move\*(C'\fR call prevents copy elision. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-redundant\-move\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-redundant-move ( and Objective- only)" +This warning warns about redundant calls to \f(CW\*(C`std::move\*(C'\fR; that is, when +a move operation would have been performed even without the \f(CW\*(C`std::move\*(C'\fR +call. This happens because the compiler is forced to treat the object as if +it were an rvalue in certain situations such as returning a local variable, +where copy elision isn't applicable. Consider: +.Sp +.Vb 8 +\& struct T { +\& ... +\& }; +\& T fn(T t) +\& { +\& ... +\& return std::move (t); +\& } +.Ve +.Sp +Here, the \f(CW\*(C`std::move\*(C'\fR call is redundant. Because G++ implements Core +Issue 1579, another example is: +.Sp +.Vb 12 +\& struct T { // convertible to U +\& ... +\& }; +\& struct U { +\& ... +\& }; +\& U fn() +\& { +\& T t; +\& ... +\& return std::move (t); +\& } +.Ve +.Sp +In this example, copy elision isn't applicable because the type of the +expression being returned and the function return type differ, yet G++ +treats the return value as if it were designated by an rvalue. +.Sp +This warning is enabled by \fB\-Wextra\fR. +.IP "\fB\-fext\-numeric\-literals\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-fext-numeric-literals ( and Objective- only)" +Accept imaginary, fixed-point, or machine-defined +literal number suffixes as \s-1GNU\s0 extensions. +When this option is turned off these suffixes are treated +as \*(C+11 user-defined literal numeric suffixes. +This is on by default for all pre\-\*(C+11 dialects and all \s-1GNU\s0 dialects: +\&\fB\-std=c++98\fR, \fB\-std=gnu++98\fR, \fB\-std=gnu++11\fR, +\&\fB\-std=gnu++14\fR. +This option is off by default +for \s-1ISO \*(C+11\s0 onwards (\fB\-std=c++11\fR, ...). +.PP +The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. +.IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Weffc++ ( and Objective- only)" +Warn about violations of the following style guidelines from Scott Meyers' +\&\fIEffective \*(C+\fR series of books: +.RS 4 +.IP "*" 4 +Define a copy constructor and an assignment operator for classes +with dynamically-allocated memory. +.IP "*" 4 +Prefer initialization to assignment in constructors. +.IP "*" 4 +Have \f(CW\*(C`operator=\*(C'\fR return a reference to \f(CW*this\fR. +.IP "*" 4 +Don't try to return a reference when you must return an object. +.IP "*" 4 +Distinguish between prefix and postfix forms of increment and +decrement operators. +.IP "*" 4 +Never overload \f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, or \f(CW\*(C`,\*(C'\fR. +.RE +.RS 4 +.Sp +This option also enables \fB\-Wnon\-virtual\-dtor\fR, which is also +one of the effective \*(C+ recommendations. However, the check is +extended to warn about the lack of virtual destructor in accessible +non-polymorphic bases classes too. +.Sp +When selecting this option, be aware that the standard library +headers do not obey all of these guidelines; use \fBgrep \-v\fR +to filter out those warnings. +.RE +.IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-null-sentinel ( and Objective- only)" +Warn about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When +compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined +to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant rather than a +null pointer, it is guaranteed to be of the same size as a pointer. +But this use is not portable across different compilers. +.IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-non-template-friend ( and Objective- only)" +Disable warnings when non-template friend functions are declared +within a template. In very old versions of \s-1GCC\s0 that predate implementation +of the \s-1ISO\s0 standard, declarations such as +\&\fBfriend int foo(int)\fR, where the name of the friend is an unqualified-id, +could be interpreted as a particular specialization of a template +function; the warning exists to diagnose compatibility problems, +and is enabled by default. +.IP "\fB\-Wold\-style\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wold-style-cast ( and Objective- only)" +Warn if an old-style (C\-style) cast to a non-void type is used within +a \*(C+ program. The new-style casts (\f(CW\*(C`dynamic_cast\*(C'\fR, +\&\f(CW\*(C`static_cast\*(C'\fR, \f(CW\*(C`reinterpret_cast\*(C'\fR, and \f(CW\*(C`const_cast\*(C'\fR) are +less vulnerable to unintended effects and much easier to search for. +.IP "\fB\-Woverloaded\-virtual\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Woverloaded-virtual ( and Objective- only)" +Warn when a function declaration hides virtual functions from a +base class. For example, in: +.Sp +.Vb 3 +\& struct A { +\& virtual void f(); +\& }; +\& +\& struct B: public A { +\& void f(int); +\& }; +.Ve +.Sp +the \f(CW\*(C`A\*(C'\fR class version of \f(CW\*(C`f\*(C'\fR is hidden in \f(CW\*(C`B\*(C'\fR, and code +like: +.Sp +.Vb 2 +\& B* b; +\& b\->f(); +.Ve +.Sp +fails to compile. +.IP "\fB\-Wno\-pmf\-conversions\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-pmf-conversions ( and Objective- only)" +Disable the diagnostic for converting a bound pointer to member function +to a plain pointer. +.IP "\fB\-Wsign\-promo\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsign-promo ( and Objective- only)" +Warn when overload resolution chooses a promotion from unsigned or +enumerated type to a signed type, over a conversion to an unsigned type of +the same size. Previous versions of G++ tried to preserve +unsignedness, but the standard mandates the current behavior. +.IP "\fB\-Wtemplates\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wtemplates ( and Objective- only)" +Warn when a primary template declaration is encountered. Some coding +rules disallow templates, and this may be used to enforce that rule. +The warning is inactive inside a system header file, such as the \s-1STL,\s0 so +one can still use the \s-1STL.\s0 One may also instantiate or specialize +templates. +.IP "\fB\-Wmultiple\-inheritance\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wmultiple-inheritance ( and Objective- only)" +Warn when a class is defined with multiple direct base classes. Some +coding rules disallow multiple inheritance, and this may be used to +enforce that rule. The warning is inactive inside a system header file, +such as the \s-1STL,\s0 so one can still use the \s-1STL.\s0 One may also define +classes that indirectly use multiple inheritance. +.IP "\fB\-Wvirtual\-inheritance\fR" 4 +.IX Item "-Wvirtual-inheritance" +Warn when a class is defined with a virtual direct base class. Some +coding rules disallow multiple inheritance, and this may be used to +enforce that rule. The warning is inactive inside a system header file, +such as the \s-1STL,\s0 so one can still use the \s-1STL.\s0 One may also define +classes that indirectly use virtual inheritance. +.IP "\fB\-Wnamespaces\fR" 4 +.IX Item "-Wnamespaces" +Warn when a namespace definition is opened. Some coding rules disallow +namespaces, and this may be used to enforce that rule. The warning is +inactive inside a system header file, such as the \s-1STL,\s0 so one can still +use the \s-1STL.\s0 One may also use using directives and qualified names. +.IP "\fB\-Wno\-terminate\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-terminate ( and Objective- only)" +Disable the warning about a throw-expression that will immediately +result in a call to \f(CW\*(C`terminate\*(C'\fR. +.IP "\fB\-Wno\-class\-conversion\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-class-conversion ( and Objective- only)" +Disable the warning about the case when a conversion function converts an +object to the same type, to a base class of that type, or to void; such +a conversion function will never be called. +.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.IX Subsection "Options Controlling Objective-C and Objective- Dialects" +(\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ +languages themselves. +.PP +This section describes the command-line options that are only meaningful +for Objective-C and Objective\-\*(C+ programs. You can also use most of +the language-independent \s-1GNU\s0 compiler options. +For example, you might compile a file \fIsome_class.m\fR like this: +.PP +.Vb 1 +\& gcc \-g \-fgnu\-runtime \-O \-c some_class.m +.Ve +.PP +In this example, \fB\-fgnu\-runtime\fR is an option meant only for +Objective-C and Objective\-\*(C+ programs; you can use the other options with +any language supported by \s-1GCC.\s0 +.PP +Note that since Objective-C is an extension of the C language, Objective-C +compilations may also use options specific to the C front-end (e.g., +\&\fB\-Wtraditional\fR). Similarly, Objective\-\*(C+ compilations may use +\&\*(C+\-specific options (e.g., \fB\-Wabi\fR). +.PP +Here is a list of options that are \fIonly\fR for compiling Objective-C +and Objective\-\*(C+ programs: +.IP "\fB\-fconstant\-string\-class=\fR\fIclass-name\fR" 4 +.IX Item "-fconstant-string-class=class-name" +Use \fIclass-name\fR as the name of the class to instantiate for each +literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default +class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and +\&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below). The +\&\fB\-fconstant\-cfstrings\fR option, if also present, overrides the +\&\fB\-fconstant\-string\-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals +to be laid out as constant CoreFoundation strings. +.IP "\fB\-fgnu\-runtime\fR" 4 +.IX Item "-fgnu-runtime" +Generate object code compatible with the standard \s-1GNU\s0 Objective-C +runtime. This is the default for most types of systems. +.IP "\fB\-fnext\-runtime\fR" 4 +.IX Item "-fnext-runtime" +Generate output compatible with the NeXT runtime. This is the default +for NeXT-based systems, including Darwin and Mac \s-1OS X.\s0 The macro +\&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is +used. +.IP "\fB\-fno\-nil\-receivers\fR" 4 +.IX Item "-fno-nil-receivers" +Assume that all Objective-C message dispatches (\f(CW\*(C`[receiver +message:arg]\*(C'\fR) in this translation unit ensure that the receiver is +not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the +runtime to be used. This option is only available in conjunction with +the NeXT runtime and \s-1ABI\s0 version 0 or 1. +.IP "\fB\-fobjc\-abi\-version=\fR\fIn\fR" 4 +.IX Item "-fobjc-abi-version=n" +Use version \fIn\fR of the Objective-C \s-1ABI\s0 for the selected runtime. +This option is currently supported only for the NeXT runtime. In that +case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for +properties and other Objective-C 2.0 additions. Version 1 is the +traditional (32\-bit) \s-1ABI\s0 with support for properties and other +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI.\s0 If +nothing is specified, the default is Version 0 on 32\-bit target +machines, and Version 2 on 64\-bit target machines. +.IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 +.IX Item "-fobjc-call-cxx-cdtors" +For each Objective-C class, check if any of its instance variables is a +\&\*(C+ object with a non-trivial default constructor. If so, synthesize a +special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method which runs +non-trivial default constructors on any such instance variables, in order, +and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable +is a \*(C+ object with a non-trivial destructor, and if so, synthesize a +special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method which runs +all such default destructors, in reverse order. +.Sp +The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR +methods thusly generated only operate on instance variables +declared in the current Objective-C class, and not those inherited +from superclasses. It is the responsibility of the Objective-C +runtime to invoke all such methods in an object's inheritance +hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods are invoked +by the runtime immediately after a new object instance is allocated; +the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods are invoked immediately +before the runtime deallocates an object instance. +.Sp +As of this writing, only the NeXT runtime on Mac \s-1OS X 10.4\s0 and later has +support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and +\&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. +.IP "\fB\-fobjc\-direct\-dispatch\fR" 4 +.IX Item "-fobjc-direct-dispatch" +Allow fast jumps to the message dispatcher. On Darwin this is +accomplished via the comm page. +.IP "\fB\-fobjc\-exceptions\fR" 4 +.IX Item "-fobjc-exceptions" +Enable syntactic support for structured exception handling in +Objective-C, similar to what is offered by \*(C+. This option +is required to use the Objective-C keywords \f(CW@try\fR, +\&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and +\&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 +runtime and the NeXT runtime (but not available in conjunction with +the NeXT runtime on Mac \s-1OS X 10.2\s0 and earlier). +.IP "\fB\-fobjc\-gc\fR" 4 +.IX Item "-fobjc-gc" +Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ +programs. This option is only available with the NeXT runtime; the +\&\s-1GNU\s0 runtime has a different garbage collection implementation that +does not require special compiler flags. +.IP "\fB\-fobjc\-nilcheck\fR" 4 +.IX Item "-fobjc-nilcheck" +For the NeXT runtime with version 2 of the \s-1ABI,\s0 check for a nil +receiver in method invocations before doing the actual method call. +This is the default and can be disabled using +\&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never +checked for nil in this way no matter what this flag is set to. +Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older +version of the NeXT runtime \s-1ABI,\s0 is used. +.IP "\fB\-fobjc\-std=objc1\fR" 4 +.IX Item "-fobjc-std=objc1" +Conform to the language syntax of Objective-C 1.0, the language +recognized by \s-1GCC 4.0.\s0 This only affects the Objective-C additions to +the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, +which is controlled by the separate C/\*(C+ dialect option flags. When +this option is used with the Objective-C or Objective\-\*(C+ compiler, +any Objective-C syntax that is not recognized by \s-1GCC 4.0\s0 is rejected. +This is useful if you need to make sure that your Objective-C code can +be compiled with older versions of \s-1GCC.\s0 +.IP "\fB\-freplace\-objc\-classes\fR" 4 +.IX Item "-freplace-objc-classes" +Emit a special marker instructing \fB\fBld\fB\|(1)\fR not to statically link in +the resulting object file, and allow \fB\fBdyld\fB\|(1)\fR to load it in at +run time instead. This is used in conjunction with the Fix-and-Continue +debugging mode, where the object file in question may be recompiled and +dynamically reloaded in the course of program execution, without the need +to restart the program itself. Currently, Fix-and-Continue functionality +is only available in conjunction with the NeXT runtime on Mac \s-1OS X 10.3\s0 +and later. +.IP "\fB\-fzero\-link\fR" 4 +.IX Item "-fzero-link" +When compiling for the NeXT runtime, the compiler ordinarily replaces calls +to \f(CW\*(C`objc_getClass("...")\*(C'\fR (when the name of the class is known at +compile time) with static class references that get initialized at load time, +which improves run-time performance. Specifying the \fB\-fzero\-link\fR flag +suppresses this behavior and causes calls to \f(CW\*(C`objc_getClass("...")\*(C'\fR +to be retained. This is useful in Zero-Link debugging mode, since it allows +for individual class implementations to be modified during program execution. +The \s-1GNU\s0 runtime currently always retains calls to \f(CW\*(C`objc_get_class("...")\*(C'\fR +regardless of command-line options. +.IP "\fB\-fno\-local\-ivars\fR" 4 +.IX Item "-fno-local-ivars" +By default instance variables in Objective-C can be accessed as if +they were local variables from within the methods of the class they're +declared in. This can lead to shadowing between instance variables +and other variables declared either locally inside a class method or +globally with the same name. Specifying the \fB\-fno\-local\-ivars\fR +flag disables this behavior thus avoiding variable shadowing issues. +.IP "\fB\-fivar\-visibility=\fR[\fBpublic\fR|\fBprotected\fR|\fBprivate\fR|\fBpackage\fR]" 4 +.IX Item "-fivar-visibility=[public|protected|private|package]" +Set the default instance variable visibility to the specified option +so that instance variables declared outside the scope of any access +modifier directives default to the specified visibility. +.IP "\fB\-gen\-decls\fR" 4 +.IX Item "-gen-decls" +Dump interface declarations for all classes seen in the source file to a +file named \fI\fIsourcename\fI.decl\fR. +.IP "\fB\-Wassign\-intercept\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wassign-intercept (Objective-C and Objective- only)" +Warn whenever an Objective-C assignment is being intercepted by the +garbage collector. +.IP "\fB\-Wno\-protocol\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-protocol (Objective-C and Objective- only)" +If a class is declared to implement a protocol, a warning is issued for +every method in the protocol that is not implemented by the class. The +default behavior is to issue a warning for every method not explicitly +implemented in the class, even if a method implementation is inherited +from the superclass. If you use the \fB\-Wno\-protocol\fR option, then +methods inherited from the superclass are considered to be implemented, +and no warning is issued for them. +.IP "\fB\-Wselector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wselector (Objective-C and Objective- only)" +Warn if multiple methods of different types for the same selector are +found during compilation. The check is performed on the list of methods +in the final stage of compilation. Additionally, a check is performed +for each selector appearing in a \f(CW\*(C`@selector(...)\*(C'\fR +expression, and a corresponding method for that selector has been found +during compilation. Because these checks scan the method table only at +the end of compilation, these warnings are not produced if the final +stage of compilation is not reached, for example because an error is +found during compilation, or because the \fB\-fsyntax\-only\fR option is +being used. +.IP "\fB\-Wstrict\-selector\-match\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-selector-match (Objective-C and Objective- only)" +Warn if multiple methods with differing argument and/or return types are +found for a given selector when attempting to send a message using this +selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag +is off (which is the default behavior), the compiler omits such warnings +if any differences found are confined to types that share the same size +and alignment. +.IP "\fB\-Wundeclared\-selector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wundeclared-selector (Objective-C and Objective- only)" +Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an +undeclared selector is found. A selector is considered undeclared if no +method with that name has been declared before the +\&\f(CW\*(C`@selector(...)\*(C'\fR expression, either explicitly in an +\&\f(CW@interface\fR or \f(CW@protocol\fR declaration, or implicitly in +an \f(CW@implementation\fR section. This option always performs its +checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found, +while \fB\-Wselector\fR only performs its checks in the final stage of +compilation. This also enforces the coding style convention +that methods and selectors must be declared before being used. +.IP "\fB\-print\-objc\-runtime\-info\fR" 4 +.IX Item "-print-objc-runtime-info" +Generate C header describing the largest structure that is passed by +value, if any. +.SS "Options to Control Diagnostic Messages Formatting" +.IX Subsection "Options to Control Diagnostic Messages Formatting" +Traditionally, diagnostic messages have been formatted irrespective of +the output device's aspect (e.g. its width, ...). You can use the +options described below +to control the formatting algorithm for diagnostic messages, +e.g. how many characters per line, how often source location +information should be reported. Note that some language front ends may not +honor these options. +.IP "\fB\-fmessage\-length=\fR\fIn\fR" 4 +.IX Item "-fmessage-length=n" +Try to format error messages so that they fit on lines of about +\&\fIn\fR characters. If \fIn\fR is zero, then no line-wrapping is +done; each error message appears on a single line. This is the +default for all front ends. +.Sp +Note \- this option also affects the display of the \fB#error\fR and +\&\fB#warning\fR pre-processor directives, and the \fBdeprecated\fR +function/type/variable attribute. It does not however affect the +\&\fBpragma \s-1GCC\s0 warning\fR and \fBpragma \s-1GCC\s0 error\fR pragmas. +.IP "\fB\-fdiagnostics\-show\-location=once\fR" 4 +.IX Item "-fdiagnostics-show-location=once" +Only meaningful in line-wrapping mode. Instructs the diagnostic messages +reporter to emit source location information \fIonce\fR; that is, in +case the message is too long to fit on a single physical line and has to +be wrapped, the source location won't be emitted (as prefix) again, +over and over, in subsequent continuation lines. This is the default +behavior. +.IP "\fB\-fdiagnostics\-show\-location=every\-line\fR" 4 +.IX Item "-fdiagnostics-show-location=every-line" +Only meaningful in line-wrapping mode. Instructs the diagnostic +messages reporter to emit the same source location information (as +prefix) for physical lines that result from the process of breaking +a message which is too long to fit on a single line. +.IP "\fB\-fdiagnostics\-color[=\fR\fI\s-1WHEN\s0\fR\fB]\fR" 4 +.IX Item "-fdiagnostics-color[=WHEN]" +.PD 0 +.IP "\fB\-fno\-diagnostics\-color\fR" 4 +.IX Item "-fno-diagnostics-color" +.PD +Use color in diagnostics. \fI\s-1WHEN\s0\fR is \fBnever\fR, \fBalways\fR, +or \fBauto\fR. The default depends on how the compiler has been configured, +it can be any of the above \fI\s-1WHEN\s0\fR options or also \fBnever\fR +if \fB\s-1GCC_COLORS\s0\fR environment variable isn't present in the environment, +and \fBauto\fR otherwise. +\&\fBauto\fR means to use color only when the standard error is a terminal. +The forms \fB\-fdiagnostics\-color\fR and \fB\-fno\-diagnostics\-color\fR are +aliases for \fB\-fdiagnostics\-color=always\fR and +\&\fB\-fdiagnostics\-color=never\fR, respectively. +.Sp +The colors are defined by the environment variable \fB\s-1GCC_COLORS\s0\fR. +Its value is a colon-separated list of capabilities and Select Graphic +Rendition (\s-1SGR\s0) substrings. \s-1SGR\s0 commands are interpreted by the +terminal or terminal emulator. (See the section in the documentation +of your text terminal for permitted values and their meanings as +character attributes.) These substring values are integers in decimal +representation and can be concatenated with semicolons. +Common values to concatenate include +\&\fB1\fR for bold, +\&\fB4\fR for underline, +\&\fB5\fR for blink, +\&\fB7\fR for inverse, +\&\fB39\fR for default foreground color, +\&\fB30\fR to \fB37\fR for foreground colors, +\&\fB90\fR to \fB97\fR for 16\-color mode foreground colors, +\&\fB38;5;0\fR to \fB38;5;255\fR +for 88\-color and 256\-color modes foreground colors, +\&\fB49\fR for default background color, +\&\fB40\fR to \fB47\fR for background colors, +\&\fB100\fR to \fB107\fR for 16\-color mode background colors, +and \fB48;5;0\fR to \fB48;5;255\fR +for 88\-color and 256\-color modes background colors. +.Sp +The default \fB\s-1GCC_COLORS\s0\fR is +.Sp +.Vb 4 +\& error=01;31:warning=01;35:note=01;36:range1=32:range2=34:locus=01:\e +\& quote=01:fixit\-insert=32:fixit\-delete=31:\e +\& diff\-filename=01:diff\-hunk=32:diff\-delete=31:diff\-insert=32:\e +\& type\-diff=01;32 +.Ve +.Sp +where \fB01;31\fR is bold red, \fB01;35\fR is bold magenta, +\&\fB01;36\fR is bold cyan, \fB32\fR is green, \fB34\fR is blue, +\&\fB01\fR is bold, and \fB31\fR is red. +Setting \fB\s-1GCC_COLORS\s0\fR to the empty string disables colors. +Supported capabilities are as follows. +.RS 4 +.ie n .IP """error=""" 4 +.el .IP "\f(CWerror=\fR" 4 +.IX Item "error=" +\&\s-1SGR\s0 substring for error: markers. +.ie n .IP """warning=""" 4 +.el .IP "\f(CWwarning=\fR" 4 +.IX Item "warning=" +\&\s-1SGR\s0 substring for warning: markers. +.ie n .IP """note=""" 4 +.el .IP "\f(CWnote=\fR" 4 +.IX Item "note=" +\&\s-1SGR\s0 substring for note: markers. +.ie n .IP """range1=""" 4 +.el .IP "\f(CWrange1=\fR" 4 +.IX Item "range1=" +\&\s-1SGR\s0 substring for first additional range. +.ie n .IP """range2=""" 4 +.el .IP "\f(CWrange2=\fR" 4 +.IX Item "range2=" +\&\s-1SGR\s0 substring for second additional range. +.ie n .IP """locus=""" 4 +.el .IP "\f(CWlocus=\fR" 4 +.IX Item "locus=" +\&\s-1SGR\s0 substring for location information, \fBfile:line\fR or +\&\fBfile:line:column\fR etc. +.ie n .IP """quote=""" 4 +.el .IP "\f(CWquote=\fR" 4 +.IX Item "quote=" +\&\s-1SGR\s0 substring for information printed within quotes. +.ie n .IP """fixit\-insert=""" 4 +.el .IP "\f(CWfixit\-insert=\fR" 4 +.IX Item "fixit-insert=" +\&\s-1SGR\s0 substring for fix-it hints suggesting text to +be inserted or replaced. +.ie n .IP """fixit\-delete=""" 4 +.el .IP "\f(CWfixit\-delete=\fR" 4 +.IX Item "fixit-delete=" +\&\s-1SGR\s0 substring for fix-it hints suggesting text to +be deleted. +.ie n .IP """diff\-filename=""" 4 +.el .IP "\f(CWdiff\-filename=\fR" 4 +.IX Item "diff-filename=" +\&\s-1SGR\s0 substring for filename headers within generated patches. +.ie n .IP """diff\-hunk=""" 4 +.el .IP "\f(CWdiff\-hunk=\fR" 4 +.IX Item "diff-hunk=" +\&\s-1SGR\s0 substring for the starts of hunks within generated patches. +.ie n .IP """diff\-delete=""" 4 +.el .IP "\f(CWdiff\-delete=\fR" 4 +.IX Item "diff-delete=" +\&\s-1SGR\s0 substring for deleted lines within generated patches. +.ie n .IP """diff\-insert=""" 4 +.el .IP "\f(CWdiff\-insert=\fR" 4 +.IX Item "diff-insert=" +\&\s-1SGR\s0 substring for inserted lines within generated patches. +.ie n .IP """type\-diff=""" 4 +.el .IP "\f(CWtype\-diff=\fR" 4 +.IX Item "type-diff=" +\&\s-1SGR\s0 substring for highlighting mismatching types within template +arguments in the \*(C+ frontend. +.RE +.RS 4 +.RE +.IP "\fB\-fno\-diagnostics\-show\-option\fR" 4 +.IX Item "-fno-diagnostics-show-option" +By default, each diagnostic emitted includes text indicating the +command-line option that directly controls the diagnostic (if such an +option is known to the diagnostic machinery). Specifying the +\&\fB\-fno\-diagnostics\-show\-option\fR flag suppresses that behavior. +.IP "\fB\-fno\-diagnostics\-show\-caret\fR" 4 +.IX Item "-fno-diagnostics-show-caret" +By default, each diagnostic emitted includes the original source line +and a caret \fB^\fR indicating the column. This option suppresses this +information. The source line is truncated to \fIn\fR characters, if +the \fB\-fmessage\-length=n\fR option is given. When the output is done +to the terminal, the width is limited to the width given by the +\&\fB\s-1COLUMNS\s0\fR environment variable or, if not set, to the terminal width. +.IP "\fB\-fno\-diagnostics\-show\-labels\fR" 4 +.IX Item "-fno-diagnostics-show-labels" +By default, when printing source code (via \fB\-fdiagnostics\-show\-caret\fR), +diagnostics can label ranges of source code with pertinent information, such +as the types of expressions: +.Sp +.Vb 4 +\& printf ("foo %s bar", long_i + long_j); +\& ~^ ~~~~~~~~~~~~~~~ +\& | | +\& char * long int +.Ve +.Sp +This option suppresses the printing of these labels (in the example above, +the vertical bars and the \*(L"char *\*(R" and \*(L"long int\*(R" text). +.IP "\fB\-fno\-diagnostics\-show\-line\-numbers\fR" 4 +.IX Item "-fno-diagnostics-show-line-numbers" +By default, when printing source code (via \fB\-fdiagnostics\-show\-caret\fR), +a left margin is printed, showing line numbers. This option suppresses this +left margin. +.IP "\fB\-fdiagnostics\-minimum\-margin\-width=\fR\fIwidth\fR" 4 +.IX Item "-fdiagnostics-minimum-margin-width=width" +This option controls the minimum width of the left margin printed by +\&\fB\-fdiagnostics\-show\-line\-numbers\fR. It defaults to 6. +.IP "\fB\-fdiagnostics\-parseable\-fixits\fR" 4 +.IX Item "-fdiagnostics-parseable-fixits" +Emit fix-it hints in a machine-parseable format, suitable for consumption +by IDEs. For each fix-it, a line will be printed after the relevant +diagnostic, starting with the string \*(L"fix-it:\*(R". For example: +.Sp +.Vb 1 +\& fix\-it:"test.c":{45:3\-45:21}:"gtk_widget_show_all" +.Ve +.Sp +The location is expressed as a half-open range, expressed as a count of +bytes, starting at byte 1 for the initial column. In the above example, +bytes 3 through 20 of line 45 of \*(L"test.c\*(R" are to be replaced with the +given string: +.Sp +.Vb 5 +\& 00000000011111111112222222222 +\& 12345678901234567890123456789 +\& gtk_widget_showall (dlg); +\& ^^^^^^^^^^^^^^^^^^ +\& gtk_widget_show_all +.Ve +.Sp +The filename and replacement string escape backslash as \*(L"\e\e\*(R", tab as \*(L"\et\*(R", +newline as \*(L"\en\*(R", double quotes as \*(L"\e\*(R"\*(L", non-printable characters as octal +(e.g. vertical tab as \*(R"\e013"). +.Sp +An empty replacement string indicates that the given range is to be removed. +An empty range (e.g. \*(L"45:3\-45:3\*(R") indicates that the string is to +be inserted at the given position. +.IP "\fB\-fdiagnostics\-generate\-patch\fR" 4 +.IX Item "-fdiagnostics-generate-patch" +Print fix-it hints to stderr in unified diff format, after any diagnostics +are printed. For example: +.Sp +.Vb 3 +\& \-\-\- test.c +\& +++ test.c +\& @ \-42,5 +42,5 @ +\& +\& void show_cb(GtkDialog *dlg) +\& { +\& \- gtk_widget_showall(dlg); +\& + gtk_widget_show_all(dlg); +\& } +.Ve +.Sp +The diff may or may not be colorized, following the same rules +as for diagnostics (see \fB\-fdiagnostics\-color\fR). +.IP "\fB\-fdiagnostics\-show\-template\-tree\fR" 4 +.IX Item "-fdiagnostics-show-template-tree" +In the \*(C+ frontend, when printing diagnostics showing mismatching +template types, such as: +.Sp +.Vb 2 +\& could not convert \*(Aqstd::map >()\*(Aq +\& from \*(Aqmap<[...],vector>\*(Aq to \*(Aqmap<[...],vector> +.Ve +.Sp +the \fB\-fdiagnostics\-show\-template\-tree\fR flag enables printing a +tree-like structure showing the common and differing parts of the types, +such as: +.Sp +.Vb 4 +\& map< +\& [...], +\& vector< +\& [double != float]>> +.Ve +.Sp +The parts that differ are highlighted with color (\*(L"double\*(R" and +\&\*(L"float\*(R" in this case). +.IP "\fB\-fno\-elide\-type\fR" 4 +.IX Item "-fno-elide-type" +By default when the \*(C+ frontend prints diagnostics showing mismatching +template types, common parts of the types are printed as \*(L"[...]\*(R" to +simplify the error message. For example: +.Sp +.Vb 2 +\& could not convert \*(Aqstd::map >()\*(Aq +\& from \*(Aqmap<[...],vector>\*(Aq to \*(Aqmap<[...],vector> +.Ve +.Sp +Specifying the \fB\-fno\-elide\-type\fR flag suppresses that behavior. +This flag also affects the output of the +\&\fB\-fdiagnostics\-show\-template\-tree\fR flag. +.IP "\fB\-fno\-show\-column\fR" 4 +.IX Item "-fno-show-column" +Do not print column numbers in diagnostics. This may be necessary if +diagnostics are being scanned by a program that does not understand the +column numbers, such as \fBdejagnu\fR. +.IP "\fB\-fdiagnostics\-format=\fR\fI\s-1FORMAT\s0\fR" 4 +.IX Item "-fdiagnostics-format=FORMAT" +Select a different format for printing diagnostics. +\&\fI\s-1FORMAT\s0\fR is \fBtext\fR or \fBjson\fR. +The default is \fBtext\fR. +.Sp +The \fBjson\fR format consists of a top-level \s-1JSON\s0 array containing \s-1JSON\s0 +objects representing the diagnostics. +.Sp +The \s-1JSON\s0 is emitted as one line, without formatting; the examples below +have been formatted for clarity. +.Sp +Diagnostics can have child diagnostics. For example, this error and note: +.Sp +.Vb 8 +\& misleading\-indentation.c:15:3: warning: this \*(Aqif\*(Aq clause does not +\& guard... [\-Wmisleading\-indentation] +\& 15 | if (flag) +\& | ^~ +\& misleading\-indentation.c:17:5: note: ...this statement, but the latter +\& is misleadingly indented as if it were guarded by the \*(Aqif\*(Aq +\& 17 | y = 2; +\& | ^ +.Ve +.Sp +might be printed in \s-1JSON\s0 form (after formatting) like this: +.Sp +.Vb 10 +\& [ +\& { +\& "kind": "warning", +\& "locations": [ +\& { +\& "caret": { +\& "column": 3, +\& "file": "misleading\-indentation.c", +\& "line": 15 +\& }, +\& "finish": { +\& "column": 4, +\& "file": "misleading\-indentation.c", +\& "line": 15 +\& } +\& } +\& ], +\& "message": "this \eu2018if\eu2019 clause does not guard...", +\& "option": "\-Wmisleading\-indentation", +\& "children": [ +\& { +\& "kind": "note", +\& "locations": [ +\& { +\& "caret": { +\& "column": 5, +\& "file": "misleading\-indentation.c", +\& "line": 17 +\& } +\& } +\& ], +\& "message": "...this statement, but the latter is ..." +\& } +\& ] +\& }, +\& ... +\& ] +.Ve +.Sp +where the \f(CW\*(C`note\*(C'\fR is a child of the \f(CW\*(C`warning\*(C'\fR. +.Sp +A diagnostic has a \f(CW\*(C`kind\*(C'\fR. If this is \f(CW\*(C`warning\*(C'\fR, then there is +an \f(CW\*(C`option\*(C'\fR key describing the command-line option controlling the +warning. +.Sp +A diagnostic can contain zero or more locations. Each location has up +to three positions within it: a \f(CW\*(C`caret\*(C'\fR position and optional +\&\f(CW\*(C`start\*(C'\fR and \f(CW\*(C`finish\*(C'\fR positions. A location can also have +an optional \f(CW\*(C`label\*(C'\fR string. For example, this error: +.Sp +.Vb 7 +\& bad\-binary\-ops.c:64:23: error: invalid operands to binary + (have \*(AqS\*(Aq {aka +\& \*(Aqstruct s\*(Aq} and \*(AqT\*(Aq {aka \*(Aqstruct t\*(Aq}) +\& 64 | return callee_4a () + callee_4b (); +\& | ~~~~~~~~~~~~ ^ ~~~~~~~~~~~~ +\& | | | +\& | | T {aka struct t} +\& | S {aka struct s} +.Ve +.Sp +has three locations. Its primary location is at the \*(L"+\*(R" token at column +23. It has two secondary locations, describing the left and right-hand sides +of the expression, which have labels. It might be printed in \s-1JSON\s0 form as: +.Sp +.Vb 10 +\& { +\& "children": [], +\& "kind": "error", +\& "locations": [ +\& { +\& "caret": { +\& "column": 23, "file": "bad\-binary\-ops.c", "line": 64 +\& } +\& }, +\& { +\& "caret": { +\& "column": 10, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "finish": { +\& "column": 21, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "label": "S {aka struct s}" +\& }, +\& { +\& "caret": { +\& "column": 25, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "finish": { +\& "column": 36, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "label": "T {aka struct t}" +\& } +\& ], +\& "message": "invalid operands to binary + ..." +\& } +.Ve +.Sp +If a diagnostic contains fix-it hints, it has a \f(CW\*(C`fixits\*(C'\fR array, +consisting of half-open intervals, similar to the output of +\&\fB\-fdiagnostics\-parseable\-fixits\fR. For example, this diagnostic +with a replacement fix-it hint: +.Sp +.Vb 5 +\& demo.c:8:15: error: \*(Aqstruct s\*(Aq has no member named \*(Aqcolour\*(Aq; did you +\& mean \*(Aqcolor\*(Aq? +\& 8 | return ptr\->colour; +\& | ^~~~~~ +\& | color +.Ve +.Sp +might be printed in \s-1JSON\s0 form as: +.Sp +.Vb 10 +\& { +\& "children": [], +\& "fixits": [ +\& { +\& "next": { +\& "column": 21, +\& "file": "demo.c", +\& "line": 8 +\& }, +\& "start": { +\& "column": 15, +\& "file": "demo.c", +\& "line": 8 +\& }, +\& "string": "color" +\& } +\& ], +\& "kind": "error", +\& "locations": [ +\& { +\& "caret": { +\& "column": 15, +\& "file": "demo.c", +\& "line": 8 +\& }, +\& "finish": { +\& "column": 20, +\& "file": "demo.c", +\& "line": 8 +\& } +\& } +\& ], +\& "message": "\eu2018struct s\eu2019 has no member named ..." +\& } +.Ve +.Sp +where the fix-it hint suggests replacing the text from \f(CW\*(C`start\*(C'\fR up +to but not including \f(CW\*(C`next\*(C'\fR with \f(CW\*(C`string\*(C'\fR's value. Deletions +are expressed via an empty value for \f(CW\*(C`string\*(C'\fR, insertions by +having \f(CW\*(C`start\*(C'\fR equal \f(CW\*(C`next\*(C'\fR. +.SS "Options to Request or Suppress Warnings" +.IX Subsection "Options to Request or Suppress Warnings" +Warnings are diagnostic messages that report constructions that +are not inherently erroneous but that are risky or suggest there +may have been an error. +.PP +The following language-independent options do not enable specific +warnings but control the kinds of diagnostics produced by \s-1GCC.\s0 +.IP "\fB\-fsyntax\-only\fR" 4 +.IX Item "-fsyntax-only" +Check the code for syntax errors, but don't do anything beyond that. +.IP "\fB\-fmax\-errors=\fR\fIn\fR" 4 +.IX Item "-fmax-errors=n" +Limits the maximum number of error messages to \fIn\fR, at which point +\&\s-1GCC\s0 bails out rather than attempting to continue processing the source +code. If \fIn\fR is 0 (the default), there is no limit on the number +of error messages produced. If \fB\-Wfatal\-errors\fR is also +specified, then \fB\-Wfatal\-errors\fR takes precedence over this +option. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Inhibit all warning messages. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into errors. +.IP "\fB\-Werror=\fR" 4 +.IX Item "-Werror=" +Make the specified warning into an error. The specifier for a warning +is appended; for example \fB\-Werror=switch\fR turns the warnings +controlled by \fB\-Wswitch\fR into errors. This switch takes a +negative form, to be used to negate \fB\-Werror\fR for specific +warnings; for example \fB\-Wno\-error=switch\fR makes +\&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR +is in effect. +.Sp +The warning message for each controllable warning includes the +option that controls the warning. That option can then be used with +\&\fB\-Werror=\fR and \fB\-Wno\-error=\fR as described above. +(Printing of the option in the warning message can be disabled using the +\&\fB\-fno\-diagnostics\-show\-option\fR flag.) +.Sp +Note that specifying \fB\-Werror=\fR\fIfoo\fR automatically implies +\&\fB\-W\fR\fIfoo\fR. However, \fB\-Wno\-error=\fR\fIfoo\fR does not +imply anything. +.IP "\fB\-Wfatal\-errors\fR" 4 +.IX Item "-Wfatal-errors" +This option causes the compiler to abort compilation on the first error +occurred rather than trying to keep going and printing further error +messages. +.PP +You can request many specific warnings with options beginning with +\&\fB\-W\fR, for example \fB\-Wimplicit\fR to request warnings on +implicit declarations. Each of these specific warning options also +has a negative form beginning \fB\-Wno\-\fR to turn off warnings; for +example, \fB\-Wno\-implicit\fR. This manual lists only one of the +two forms, whichever is not the default. For further +language-specific options also refer to \fB\*(C+ Dialect Options\fR and +\&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.PP +Some options, such as \fB\-Wall\fR and \fB\-Wextra\fR, turn on other +options, such as \fB\-Wunused\fR, which may turn on further options, +such as \fB\-Wunused\-value\fR. The combined effect of positive and +negative forms is that more specific options have priority over less +specific ones, independently of their position in the command-line. For +options of the same specificity, the last one takes effect. Options +enabled or disabled via pragmas take effect +as if they appeared at the end of the command-line. +.PP +When an unrecognized warning option is requested (e.g., +\&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 emits a diagnostic stating +that the option is not recognized. However, if the \fB\-Wno\-\fR form +is used, the behavior is slightly different: no diagnostic is +produced for \fB\-Wno\-unknown\-warning\fR unless other diagnostics +are being produced. This allows the use of new \fB\-Wno\-\fR options +with old compilers, but if something goes wrong, the compiler +warns that an unrecognized option is present. +.PP +The effectiveness of some warnings depends on optimizations also being +enabled. For example \fB\-Wsuggest\-final\-types\fR is more effective +with link-time optimization and \fB\-Wmaybe\-uninitialized\fR will not +warn at all unless optimization is enabled. +.IP "\fB\-Wpedantic\fR" 4 +.IX Item "-Wpedantic" +.PD 0 +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +.PD +Issue all the warnings demanded by strict \s-1ISO C\s0 and \s-1ISO \*(C+\s0; +reject all programs that use forbidden extensions, and some other +programs that do not follow \s-1ISO C\s0 and \s-1ISO \*(C+.\s0 For \s-1ISO C,\s0 follows the +version of the \s-1ISO C\s0 standard specified by any \fB\-std\fR option used. +.Sp +Valid \s-1ISO C\s0 and \s-1ISO \*(C+\s0 programs should compile properly with or without +this option (though a rare few require \fB\-ansi\fR or a +\&\fB\-std\fR option specifying the required version of \s-1ISO C\s0). However, +without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ +features are supported as well. With this option, they are rejected. +.Sp +\&\fB\-Wpedantic\fR does not cause warning messages for use of the +alternate keywords whose names begin and end with \fB_\|_\fR. Pedantic +warnings are also disabled in the expression that follows +\&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use +these escape routes; application programs should avoid them. +.Sp +Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO +C\s0 conformance. They soon find that it does not do quite what they want: +it finds some non-ISO practices, but not all\-\-\-only those for which +\&\s-1ISO C\s0 \fIrequires\fR a diagnostic, and some others for which +diagnostics have been added. +.Sp +A feature to report any failure to conform to \s-1ISO C\s0 might be useful in +some instances, but would require considerable additional work and would +be quite different from \fB\-Wpedantic\fR. We don't have plans to +support such a feature in the near future. +.Sp +Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 +extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a +corresponding \fIbase standard\fR, the version of \s-1ISO C\s0 on which the \s-1GNU\s0 +extended dialect is based. Warnings from \fB\-Wpedantic\fR are given +where they are required by the base standard. (It does not make sense +for such warnings to be given only for features not in the specified \s-1GNU +C\s0 dialect, since by definition the \s-1GNU\s0 dialects of C include all +features the compiler supports with the given option, and there would be +nothing to warn about.) +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Give an error whenever the \fIbase standard\fR (see \fB\-Wpedantic\fR) +requires a diagnostic, in some cases where there is undefined behavior +at compile-time and in some other cases that do not prevent compilation +of programs that are valid according to the standard. This is not +equivalent to \fB\-Werror=pedantic\fR, since there are errors enabled +by this option and not enabled by the latter and vice versa. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +This enables all the warnings about constructions that some users +consider questionable, and that are easy to avoid (or modify to +prevent the warning), even in conjunction with macros. This also +enables some language-specific warnings described in \fB\*(C+ Dialect +Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.Sp +\&\fB\-Wall\fR turns on the following warning flags: +.Sp +\&\fB\-Waddress +\&\-Warray\-bounds=1\fR (only with\fB \fR\fB\-O2\fR) +\&\fB\-Wbool\-compare +\&\-Wbool\-operation +\&\-Wc++11\-compat \-Wc++14\-compat +\&\-Wcatch\-value\fR (\*(C+ and Objective\-\*(C+ only) +\&\fB\-Wchar\-subscripts +\&\-Wcomment +\&\-Wduplicate\-decl\-specifier\fR (C and Objective-C only) +\&\fB\-Wenum\-compare\fR (in C/ObjC; this is on by default in \*(C+) +\&\fB\-Wformat +\&\-Wint\-in\-bool\-context +\&\-Wimplicit\fR (C and Objective-C only) +\&\fB\-Wimplicit\-int\fR (C and Objective-C only) +\&\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only) +\&\fB\-Winit\-self\fR (only for \*(C+) +\&\fB\-Wlogical\-not\-parentheses +\&\-Wmain\fR (only for C/ObjC and unless\fB \fR\fB\-ffreestanding\fR) +\&\fB\-Wmaybe\-uninitialized +\&\-Wmemset\-elt\-size +\&\-Wmemset\-transposed\-args +\&\-Wmisleading\-indentation\fR (only for C/\*(C+) +\&\fB\-Wmissing\-attributes +\&\-Wmissing\-braces\fR (only for C/ObjC) +\&\fB\-Wmultistatement\-macros +\&\-Wnarrowing\fR (only for \*(C+) +\&\fB\-Wnonnull +\&\-Wnonnull\-compare +\&\-Wopenmp\-simd +\&\-Wparentheses +\&\-Wpessimizing\-move\fR (only for \*(C+) +\&\fB\-Wpointer\-sign +\&\-Wreorder +\&\-Wrestrict +\&\-Wreturn\-type +\&\-Wsequence\-point +\&\-Wsign\-compare\fR (only in \*(C+) +\&\fB\-Wsizeof\-pointer\-div +\&\-Wsizeof\-pointer\-memaccess +\&\-Wstrict\-aliasing +\&\-Wstrict\-overflow=1 +\&\-Wswitch +\&\-Wtautological\-compare +\&\-Wtrigraphs +\&\-Wuninitialized +\&\-Wunknown\-pragmas +\&\-Wunused\-function +\&\-Wunused\-label +\&\-Wunused\-value +\&\-Wunused\-variable +\&\-Wvolatile\-register\-var\fR +.Sp +Note that some warning flags are not implied by \fB\-Wall\fR. Some of +them warn about constructions that users generally do not consider +questionable, but which occasionally you might wish to check for; +others warn about constructions that are necessary or hard to avoid in +some cases, and there is no simple way to modify the code to suppress +the warning. Some of them are enabled by \fB\-Wextra\fR but many of +them must be enabled individually. +.IP "\fB\-Wextra\fR" 4 +.IX Item "-Wextra" +This enables some extra warning flags that are not enabled by +\&\fB\-Wall\fR. (This option used to be called \fB\-W\fR. The older +name is still supported, but the newer name is more descriptive.) +.Sp +\&\fB\-Wclobbered +\&\-Wcast\-function\-type +\&\-Wdeprecated\-copy\fR (\*(C+ only) +\&\fB\-Wempty\-body +\&\-Wignored\-qualifiers +\&\-Wimplicit\-fallthrough=3 +\&\-Wmissing\-field\-initializers +\&\-Wmissing\-parameter\-type\fR (C only) +\&\fB\-Wold\-style\-declaration\fR (C only) +\&\fB\-Woverride\-init +\&\-Wsign\-compare\fR (C only) +\&\fB\-Wredundant\-move\fR (only for \*(C+) +\&\fB\-Wtype\-limits +\&\-Wuninitialized +\&\-Wshift\-negative\-value\fR (in \*(C+11 to \*(C+17 and in C99 and newer) +\&\fB\-Wunused\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) +\&\fB\-Wunused\-but\-set\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) +.Sp +The option \fB\-Wextra\fR also prints warning messages for the +following cases: +.RS 4 +.IP "*" 4 +A pointer is compared against integer zero with \f(CW\*(C`<\*(C'\fR, \f(CW\*(C`<=\*(C'\fR, +\&\f(CW\*(C`>\*(C'\fR, or \f(CW\*(C`>=\*(C'\fR. +.IP "*" 4 +(\*(C+ only) An enumerator and a non-enumerator both appear in a +conditional expression. +.IP "*" 4 +(\*(C+ only) Ambiguous virtual bases. +.IP "*" 4 +(\*(C+ only) Subscripting an array that has been declared \f(CW\*(C`register\*(C'\fR. +.IP "*" 4 +(\*(C+ only) Taking the address of a variable that has been declared +\&\f(CW\*(C`register\*(C'\fR. +.IP "*" 4 +(\*(C+ only) A base class is not initialized in the copy constructor +of a derived class. +.RE +.RS 4 +.RE +.IP "\fB\-Wchar\-subscripts\fR" 4 +.IX Item "-Wchar-subscripts" +Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR. This is a common cause +of error, as programmers often forget that this type is signed on some +machines. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-coverage\-mismatch\fR" 4 +.IX Item "-Wno-coverage-mismatch" +Warn if feedback profiles do not match when using the +\&\fB\-fprofile\-use\fR option. +If a source file is changed between compiling with \fB\-fprofile\-generate\fR +and with \fB\-fprofile\-use\fR, the files with the profile feedback can fail +to match the source file and \s-1GCC\s0 cannot use the profile feedback +information. By default, this warning is enabled and is treated as an +error. \fB\-Wno\-coverage\-mismatch\fR can be used to disable the +warning or \fB\-Wno\-error=coverage\-mismatch\fR can be used to +disable the error. Disabling the error for this warning can result in +poorly optimized code and is useful only in the +case of very minor changes such as bug fixes to an existing code-base. +Completely disabling the warning is not recommended. +.IP "\fB\-Wno\-cpp\fR" 4 +.IX Item "-Wno-cpp" +(C, Objective-C, \*(C+, Objective\-\*(C+ and Fortran only) +.Sp +Suppress warning messages emitted by \f(CW\*(C`#warning\*(C'\fR directives. +.IP "\fB\-Wdouble\-promotion\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wdouble-promotion (C, , Objective-C and Objective- only)" +Give a warning when a value of type \f(CW\*(C`float\*(C'\fR is implicitly +promoted to \f(CW\*(C`double\*(C'\fR. CPUs with a 32\-bit \*(L"single-precision\*(R" +floating-point unit implement \f(CW\*(C`float\*(C'\fR in hardware, but emulate +\&\f(CW\*(C`double\*(C'\fR in software. On such a machine, doing computations +using \f(CW\*(C`double\*(C'\fR values is much more expensive because of the +overhead required for software emulation. +.Sp +It is easy to accidentally do computations with \f(CW\*(C`double\*(C'\fR because +floating-point literals are implicitly of type \f(CW\*(C`double\*(C'\fR. For +example, in: +.Sp +.Vb 4 +\& float area(float radius) +\& { +\& return 3.14159 * radius * radius; +\& } +.Ve +.Sp +the compiler performs the entire computation with \f(CW\*(C`double\*(C'\fR +because the floating-point literal is a \f(CW\*(C`double\*(C'\fR. +.IP "\fB\-Wduplicate\-decl\-specifier\fR (C and Objective-C only)" 4 +.IX Item "-Wduplicate-decl-specifier (C and Objective-C only)" +Warn if a declaration has duplicate \f(CW\*(C`const\*(C'\fR, \f(CW\*(C`volatile\*(C'\fR, +\&\f(CW\*(C`restrict\*(C'\fR or \f(CW\*(C`_Atomic\*(C'\fR specifier. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wformat\fR" 4 +.IX Item "-Wformat" +.PD 0 +.IP "\fB\-Wformat=\fR\fIn\fR" 4 +.IX Item "-Wformat=n" +.PD +Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that +the arguments supplied have types appropriate to the format string +specified, and that the conversions specified in the format string make +sense. This includes standard functions, and others specified by format +attributes, in the \f(CW\*(C`printf\*(C'\fR, +\&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension, +not in the C standard) families (or other target-specific families). +Which functions are checked without format attributes having been +specified depends on the standard version selected, and such checks of +functions without the attribute specified are disabled by +\&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. +.Sp +The formats are checked against the format features supported by \s-1GNU\s0 +libc version 2.2. These include all \s-1ISO C90\s0 and C99 features, as well +as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 +extensions. Other library implementations may not support all these +features; \s-1GCC\s0 does not support warning about features that go beyond a +particular library's limitations. However, if \fB\-Wpedantic\fR is used +with \fB\-Wformat\fR, warnings are given about format features not +in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats, +since those are not in any version of the C standard). +.RS 4 +.IP "\fB\-Wformat=1\fR" 4 +.IX Item "-Wformat=1" +.PD 0 +.IP "\fB\-Wformat\fR" 4 +.IX Item "-Wformat" +.PD +Option \fB\-Wformat\fR is equivalent to \fB\-Wformat=1\fR, and +\&\fB\-Wno\-format\fR is equivalent to \fB\-Wformat=0\fR. Since +\&\fB\-Wformat\fR also checks for null format arguments for several +functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR. Some +aspects of this level of format checking can be disabled by the +options: \fB\-Wno\-format\-contains\-nul\fR, +\&\fB\-Wno\-format\-extra\-args\fR, and \fB\-Wno\-format\-zero\-length\fR. +\&\fB\-Wformat\fR is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-format\-contains\-nul\fR" 4 +.IX Item "-Wno-format-contains-nul" +If \fB\-Wformat\fR is specified, do not warn about format strings that +contain \s-1NUL\s0 bytes. +.IP "\fB\-Wno\-format\-extra\-args\fR" 4 +.IX Item "-Wno-format-extra-args" +If \fB\-Wformat\fR is specified, do not warn about excess arguments to a +\&\f(CW\*(C`printf\*(C'\fR or \f(CW\*(C`scanf\*(C'\fR format function. The C standard specifies +that such arguments are ignored. +.Sp +Where the unused arguments lie between used arguments that are +specified with \fB$\fR operand number specifications, normally +warnings are still given, since the implementation could not know what +type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments. However, +in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option suppresses the +warning if the unused arguments are all pointers, since the Single +Unix Specification says that such unused arguments are allowed. +.IP "\fB\-Wformat\-overflow\fR" 4 +.IX Item "-Wformat-overflow" +.PD 0 +.IP "\fB\-Wformat\-overflow=\fR\fIlevel\fR" 4 +.IX Item "-Wformat-overflow=level" +.PD +Warn about calls to formatted input/output functions such as \f(CW\*(C`sprintf\*(C'\fR +and \f(CW\*(C`vsprintf\*(C'\fR that might overflow the destination buffer. When the +exact number of bytes written by a format directive cannot be determined +at compile-time it is estimated based on heuristics that depend on the +\&\fIlevel\fR argument and on optimization. While enabling optimization +will in most cases improve the accuracy of the warning, it may also +result in false positives. +.RS 4 +.IP "\fB\-Wformat\-overflow\fR" 4 +.IX Item "-Wformat-overflow" +.PD 0 +.IP "\fB\-Wformat\-overflow=1\fR" 4 +.IX Item "-Wformat-overflow=1" +.PD +Level \fI1\fR of \fB\-Wformat\-overflow\fR enabled by \fB\-Wformat\fR +employs a conservative approach that warns only about calls that most +likely overflow the buffer. At this level, numeric arguments to format +directives with unknown values are assumed to have the value of one, and +strings of unknown length to be empty. Numeric arguments that are known +to be bounded to a subrange of their type, or string arguments whose output +is bounded either by their directive's precision or by a finite set of +string literals, are assumed to take on the value within the range that +results in the most bytes on output. For example, the call to \f(CW\*(C`sprintf\*(C'\fR +below is diagnosed because even with both \fIa\fR and \fIb\fR equal to zero, +the terminating \s-1NUL\s0 character (\f(CW\*(Aq\e0\*(Aq\fR) appended by the function +to the destination buffer will be written past its end. Increasing +the size of the buffer by a single byte is sufficient to avoid the +warning, though it may not be sufficient to avoid the overflow. +.Sp +.Vb 5 +\& void f (int a, int b) +\& { +\& char buf [13]; +\& sprintf (buf, "a = %i, b = %i\en", a, b); +\& } +.Ve +.IP "\fB\-Wformat\-overflow=2\fR" 4 +.IX Item "-Wformat-overflow=2" +Level \fI2\fR warns also about calls that might overflow the destination +buffer given an argument of sufficient length or magnitude. At level +\&\fI2\fR, unknown numeric arguments are assumed to have the minimum +representable value for signed types with a precision greater than 1, and +the maximum representable value otherwise. Unknown string arguments whose +length cannot be assumed to be bounded either by the directive's precision, +or by a finite set of string literals they may evaluate to, or the character +array they may point to, are assumed to be 1 character long. +.Sp +At level \fI2\fR, the call in the example above is again diagnosed, but +this time because with \fIa\fR equal to a 32\-bit \f(CW\*(C`INT_MIN\*(C'\fR the first +\&\f(CW%i\fR directive will write some of its digits beyond the end of +the destination buffer. To make the call safe regardless of the values +of the two variables, the size of the destination buffer must be increased +to at least 34 bytes. \s-1GCC\s0 includes the minimum size of the buffer in +an informational note following the warning. +.Sp +An alternative to increasing the size of the destination buffer is to +constrain the range of formatted values. The maximum length of string +arguments can be bounded by specifying the precision in the format +directive. When numeric arguments of format directives can be assumed +to be bounded by less than the precision of their type, choosing +an appropriate length modifier to the format specifier will reduce +the required buffer size. For example, if \fIa\fR and \fIb\fR in the +example above can be assumed to be within the precision of +the \f(CW\*(C`short int\*(C'\fR type then using either the \f(CW%hi\fR format +directive or casting the argument to \f(CW\*(C`short\*(C'\fR reduces the maximum +required size of the buffer to 24 bytes. +.Sp +.Vb 5 +\& void f (int a, int b) +\& { +\& char buf [23]; +\& sprintf (buf, "a = %hi, b = %i\en", a, (short)b); +\& } +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-Wno\-format\-zero\-length\fR" 4 +.IX Item "-Wno-format-zero-length" +If \fB\-Wformat\fR is specified, do not warn about zero-length formats. +The C standard specifies that zero-length formats are allowed. +.IP "\fB\-Wformat=2\fR" 4 +.IX Item "-Wformat=2" +Enable \fB\-Wformat\fR plus additional format checks. Currently +equivalent to \fB\-Wformat \-Wformat\-nonliteral \-Wformat\-security +\&\-Wformat\-y2k\fR. +.IP "\fB\-Wformat\-nonliteral\fR" 4 +.IX Item "-Wformat-nonliteral" +If \fB\-Wformat\fR is specified, also warn if the format string is not a +string literal and so cannot be checked, unless the format function +takes its format arguments as a \f(CW\*(C`va_list\*(C'\fR. +.IP "\fB\-Wformat\-security\fR" 4 +.IX Item "-Wformat-security" +If \fB\-Wformat\fR is specified, also warn about uses of format +functions that represent possible security problems. At present, this +warns about calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR functions where the +format string is not a string literal and there are no format arguments, +as in \f(CW\*(C`printf (foo);\*(C'\fR. This may be a security hole if the format +string came from untrusted input and contains \fB\f(CB%n\fB\fR. (This is +currently a subset of what \fB\-Wformat\-nonliteral\fR warns about, but +in future warnings may be added to \fB\-Wformat\-security\fR that are not +included in \fB\-Wformat\-nonliteral\fR.) +.IP "\fB\-Wformat\-signedness\fR" 4 +.IX Item "-Wformat-signedness" +If \fB\-Wformat\fR is specified, also warn if the format string +requires an unsigned argument and the argument is signed and vice versa. +.IP "\fB\-Wformat\-truncation\fR" 4 +.IX Item "-Wformat-truncation" +.PD 0 +.IP "\fB\-Wformat\-truncation=\fR\fIlevel\fR" 4 +.IX Item "-Wformat-truncation=level" +.PD +Warn about calls to formatted input/output functions such as \f(CW\*(C`snprintf\*(C'\fR +and \f(CW\*(C`vsnprintf\*(C'\fR that might result in output truncation. When the exact +number of bytes written by a format directive cannot be determined at +compile-time it is estimated based on heuristics that depend on +the \fIlevel\fR argument and on optimization. While enabling optimization +will in most cases improve the accuracy of the warning, it may also result +in false positives. Except as noted otherwise, the option uses the same +logic \fB\-Wformat\-overflow\fR. +.RS 4 +.IP "\fB\-Wformat\-truncation\fR" 4 +.IX Item "-Wformat-truncation" +.PD 0 +.IP "\fB\-Wformat\-truncation=1\fR" 4 +.IX Item "-Wformat-truncation=1" +.PD +Level \fI1\fR of \fB\-Wformat\-truncation\fR enabled by \fB\-Wformat\fR +employs a conservative approach that warns only about calls to bounded +functions whose return value is unused and that will most likely result +in output truncation. +.IP "\fB\-Wformat\-truncation=2\fR" 4 +.IX Item "-Wformat-truncation=2" +Level \fI2\fR warns also about calls to bounded functions whose return +value is used and that might result in truncation given an argument of +sufficient length or magnitude. +.RE +.RS 4 +.RE +.IP "\fB\-Wformat\-y2k\fR" 4 +.IX Item "-Wformat-y2k" +If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR +formats that may yield only a two-digit year. +.RE +.RS 4 +.RE +.IP "\fB\-Wnonnull\fR" 4 +.IX Item "-Wnonnull" +Warn about passing a null pointer for arguments marked as +requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute. +.Sp +\&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR. It +can be disabled with the \fB\-Wno\-nonnull\fR option. +.IP "\fB\-Wnonnull\-compare\fR" 4 +.IX Item "-Wnonnull-compare" +Warn when comparing an argument marked with the \f(CW\*(C`nonnull\*(C'\fR +function attribute against null inside the function. +.Sp +\&\fB\-Wnonnull\-compare\fR is included in \fB\-Wall\fR. It +can be disabled with the \fB\-Wno\-nonnull\-compare\fR option. +.IP "\fB\-Wnull\-dereference\fR" 4 +.IX Item "-Wnull-dereference" +Warn if the compiler detects paths that trigger erroneous or +undefined behavior due to dereferencing a null pointer. This option +is only active when \fB\-fdelete\-null\-pointer\-checks\fR is active, +which is enabled by optimizations in most targets. The precision of +the warnings depends on the optimization options used. +.IP "\fB\-Winit\-self\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Winit-self (C, , Objective-C and Objective- only)" +Warn about uninitialized variables that are initialized with themselves. +Note this option can only be used with the \fB\-Wuninitialized\fR option. +.Sp +For example, \s-1GCC\s0 warns about \f(CW\*(C`i\*(C'\fR being uninitialized in the +following snippet only when \fB\-Winit\-self\fR has been specified: +.Sp +.Vb 5 +\& int f() +\& { +\& int i = i; +\& return i; +\& } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR in \*(C+. +.IP "\fB\-Wimplicit\-int\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-int (C and Objective-C only)" +Warn when a declaration does not specify a type. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-function-declaration (C and Objective-C only)" +Give a warning whenever a function is used before being declared. In +C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this warning is +enabled by default and it is made into an error by +\&\fB\-pedantic\-errors\fR. This warning is also enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wimplicit\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit (C and Objective-C only)" +Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wimplicit\-fallthrough\fR" 4 +.IX Item "-Wimplicit-fallthrough" +\&\fB\-Wimplicit\-fallthrough\fR is the same as \fB\-Wimplicit\-fallthrough=3\fR +and \fB\-Wno\-implicit\-fallthrough\fR is the same as +\&\fB\-Wimplicit\-fallthrough=0\fR. +.IP "\fB\-Wimplicit\-fallthrough=\fR\fIn\fR" 4 +.IX Item "-Wimplicit-fallthrough=n" +Warn when a switch case falls through. For example: +.Sp +.Vb 11 +\& switch (cond) +\& { +\& case 1: +\& a = 1; +\& break; +\& case 2: +\& a = 2; +\& case 3: +\& a = 3; +\& break; +\& } +.Ve +.Sp +This warning does not warn when the last statement of a case cannot +fall through, e.g. when there is a return statement or a call to function +declared with the noreturn attribute. \fB\-Wimplicit\-fallthrough=\fR +also takes into account control flow statements, such as ifs, and only +warns when appropriate. E.g. +.Sp +.Vb 10 +\& switch (cond) +\& { +\& case 1: +\& if (i > 3) { +\& bar (5); +\& break; +\& } else if (i < 1) { +\& bar (0); +\& } else +\& return; +\& default: +\& ... +\& } +.Ve +.Sp +Since there are occasions where a switch case fall through is desirable, +\&\s-1GCC\s0 provides an attribute, \f(CW\*(C`_\|_attribute_\|_ ((fallthrough))\*(C'\fR, that is +to be used along with a null statement to suppress this warning that +would normally occur: +.Sp +.Vb 8 +\& switch (cond) +\& { +\& case 1: +\& bar (0); +\& _\|_attribute_\|_ ((fallthrough)); +\& default: +\& ... +\& } +.Ve +.Sp +\&\*(C+17 provides a standard way to suppress the \fB\-Wimplicit\-fallthrough\fR +warning using \f(CW\*(C`[[fallthrough]];\*(C'\fR instead of the \s-1GNU\s0 attribute. In \*(C+11 +or \*(C+14 users can use \f(CW\*(C`[[gnu::fallthrough]];\*(C'\fR, which is a \s-1GNU\s0 extension. +Instead of these attributes, it is also possible to add a fallthrough comment +to silence the warning. The whole body of the C or \*(C+ style comment should +match the given regular expressions listed below. The option argument \fIn\fR +specifies what kind of comments are accepted: +.RS 4 +.IP "*<\fB\-Wimplicit\-fallthrough=0\fR disables the warning altogether.>" 4 +.IX Item "*<-Wimplicit-fallthrough=0 disables the warning altogether.>" +.PD 0 +.ie n .IP "*<\fB\-Wimplicit\-fallthrough=1\fR matches "".*"" regular>" 4 +.el .IP "*<\fB\-Wimplicit\-fallthrough=1\fR matches \f(CW.*\fR regular>" 4 +.IX Item "*<-Wimplicit-fallthrough=1 matches .* regular>" +.PD +expression, any comment is used as fallthrough comment. +.IP "*<\fB\-Wimplicit\-fallthrough=2\fR case insensitively matches>" 4 +.IX Item "*<-Wimplicit-fallthrough=2 case insensitively matches>" +\&\f(CW\*(C`.*falls?[ \et\-]*thr(ough|u).*\*(C'\fR regular expression. +.IP "*<\fB\-Wimplicit\-fallthrough=3\fR case sensitively matches one of the>" 4 +.IX Item "*<-Wimplicit-fallthrough=3 case sensitively matches one of the>" +following regular expressions: +.RS 4 +.ie n .IP "*<""\-fallthrough"">" 4 +.el .IP "*<\f(CW\-fallthrough\fR>" 4 +.IX Item "*<-fallthrough>" +.PD 0 +.ie n .IP "*<""@fallthrough@"">" 4 +.el .IP "*<\f(CW@fallthrough@\fR>" 4 +.IX Item "*<@fallthrough@>" +.ie n .IP "*<""lint \-fallthrough[ \et]*"">" 4 +.el .IP "*<\f(CWlint \-fallthrough[ \et]*\fR>" 4 +.IX Item "*" +.ie n .IP "*<""[ \et.!]*(ELSE,? |INTENTIONAL(LY)? )?FALL(S | |\-)?THR(OUGH|U)[ \et.!]*(\-[^\en\er]*)?"">" 4 +.el .IP "*<\f(CW[ \et.!]*(ELSE,? |INTENTIONAL(LY)? )?FALL(S | |\-)?THR(OUGH|U)[ \et.!]*(\-[^\en\er]*)?\fR>" 4 +.IX Item "*<[ t.!]*(ELSE,? |INTENTIONAL(LY)? )?FALL(S | |-)?THR(OUGH|U)[ t.!]*(-[^nr]*)?>" +.ie n .IP "*<""[ \et.!]*(Else,? |Intentional(ly)? )?Fall((s | |\-)[Tt]|t)hr(ough|u)[ \et.!]*(\-[^\en\er]*)?"">" 4 +.el .IP "*<\f(CW[ \et.!]*(Else,? |Intentional(ly)? )?Fall((s | |\-)[Tt]|t)hr(ough|u)[ \et.!]*(\-[^\en\er]*)?\fR>" 4 +.IX Item "*<[ t.!]*(Else,? |Intentional(ly)? )?Fall((s | |-)[Tt]|t)hr(ough|u)[ t.!]*(-[^nr]*)?>" +.ie n .IP "*<""[ \et.!]*([Ee]lse,? |[Ii]ntentional(ly)? )?fall(s | |\-)?thr(ough|u)[ \et.!]*(\-[^\en\er]*)?"">" 4 +.el .IP "*<\f(CW[ \et.!]*([Ee]lse,? |[Ii]ntentional(ly)? )?fall(s | |\-)?thr(ough|u)[ \et.!]*(\-[^\en\er]*)?\fR>" 4 +.IX Item "*<[ t.!]*([Ee]lse,? |[Ii]ntentional(ly)? )?fall(s | |-)?thr(ough|u)[ t.!]*(-[^nr]*)?>" +.RE +.RS 4 +.RE +.IP "*<\fB\-Wimplicit\-fallthrough=4\fR case sensitively matches one of the>" 4 +.IX Item "*<-Wimplicit-fallthrough=4 case sensitively matches one of the>" +.PD +following regular expressions: +.RS 4 +.ie n .IP "*<""\-fallthrough"">" 4 +.el .IP "*<\f(CW\-fallthrough\fR>" 4 +.IX Item "*<-fallthrough>" +.PD 0 +.ie n .IP "*<""@fallthrough@"">" 4 +.el .IP "*<\f(CW@fallthrough@\fR>" 4 +.IX Item "*<@fallthrough@>" +.ie n .IP "*<""lint \-fallthrough[ \et]*"">" 4 +.el .IP "*<\f(CWlint \-fallthrough[ \et]*\fR>" 4 +.IX Item "*" +.ie n .IP "*<""[ \et]*FALLTHR(OUGH|U)[ \et]*"">" 4 +.el .IP "*<\f(CW[ \et]*FALLTHR(OUGH|U)[ \et]*\fR>" 4 +.IX Item "*<[ t]*FALLTHR(OUGH|U)[ t]*>" +.RE +.RS 4 +.RE +.IP "*<\fB\-Wimplicit\-fallthrough=5\fR doesn't recognize any comments as>" 4 +.IX Item "*<-Wimplicit-fallthrough=5 doesn't recognize any comments as>" +.PD +fallthrough comments, only attributes disable the warning. +.RE +.RS 4 +.Sp +The comment needs to be followed after optional whitespace and other comments +by \f(CW\*(C`case\*(C'\fR or \f(CW\*(C`default\*(C'\fR keywords or by a user label that precedes some +\&\f(CW\*(C`case\*(C'\fR or \f(CW\*(C`default\*(C'\fR label. +.Sp +.Vb 8 +\& switch (cond) +\& { +\& case 1: +\& bar (0); +\& /* FALLTHRU */ +\& default: +\& ... +\& } +.Ve +.Sp +The \fB\-Wimplicit\-fallthrough=3\fR warning is enabled by \fB\-Wextra\fR. +.RE +.IP "\fB\-Wif\-not\-aligned\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wif-not-aligned (C, , Objective-C and Objective- only)" +Control if warning triggered by the \f(CW\*(C`warn_if_not_aligned\*(C'\fR attribute +should be issued. This is enabled by default. +Use \fB\-Wno\-if\-not\-aligned\fR to disable it. +.IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 +.IX Item "-Wignored-qualifiers (C and only)" +Warn if the return type of a function has a type qualifier +such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO C\s0 such a type qualifier has no effect, +since the value returned by a function is not an lvalue. +For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. +\&\s-1ISO C\s0 prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function +definitions, so such return types always receive a warning +even without this option. +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wignored\-attributes\fR (C and \*(C+ only)" 4 +.IX Item "-Wignored-attributes (C and only)" +Warn when an attribute is ignored. This is different from the +\&\fB\-Wattributes\fR option in that it warns whenever the compiler decides +to drop an attribute, not that the attribute is either unknown, used in a +wrong place, etc. This warning is enabled by default. +.IP "\fB\-Wmain\fR" 4 +.IX Item "-Wmain" +Warn if the type of \f(CW\*(C`main\*(C'\fR is suspicious. \f(CW\*(C`main\*(C'\fR should be +a function with external linkage, returning int, taking either zero +arguments, two, or three arguments of appropriate types. This warning +is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR +or \fB\-Wpedantic\fR. +.IP "\fB\-Wmisleading\-indentation\fR (C and \*(C+ only)" 4 +.IX Item "-Wmisleading-indentation (C and only)" +Warn when the indentation of the code does not reflect the block structure. +Specifically, a warning is issued for \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR, \f(CW\*(C`while\*(C'\fR, and +\&\f(CW\*(C`for\*(C'\fR clauses with a guarded statement that does not use braces, +followed by an unguarded statement with the same indentation. +.Sp +In the following example, the call to \*(L"bar\*(R" is misleadingly indented as +if it were guarded by the \*(L"if\*(R" conditional. +.Sp +.Vb 3 +\& if (some_condition ()) +\& foo (); +\& bar (); /* Gotcha: this is not guarded by the "if". */ +.Ve +.Sp +In the case of mixed tabs and spaces, the warning uses the +\&\fB\-ftabstop=\fR option to determine if the statements line up +(defaulting to 8). +.Sp +The warning is not issued for code involving multiline preprocessor logic +such as the following example. +.Sp +.Vb 6 +\& if (flagA) +\& foo (0); +\& #if SOME_CONDITION_THAT_DOES_NOT_HOLD +\& if (flagB) +\& #endif +\& foo (1); +.Ve +.Sp +The warning is not issued after a \f(CW\*(C`#line\*(C'\fR directive, since this +typically indicates autogenerated code, and no assumptions can be made +about the layout of the file that the directive references. +.Sp +This warning is enabled by \fB\-Wall\fR in C and \*(C+. +.IP "\fB\-Wmissing\-attributes\fR" 4 +.IX Item "-Wmissing-attributes" +Warn when a declaration of a function is missing one or more attributes +that a related function is declared with and whose absence may adversely +affect the correctness or efficiency of generated code. For example, +the warning is issued for declarations of aliases that use attributes +to specify less restrictive requirements than those of their targets. +This typically represents a potential optimization opportunity. +By contrast, the \fB\-Wattribute\-alias=2\fR option controls warnings +issued when the alias is more restrictive than the target, which could +lead to incorrect code generation. +Attributes considered include \f(CW\*(C`alloc_align\*(C'\fR, \f(CW\*(C`alloc_size\*(C'\fR, +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`const\*(C'\fR, \f(CW\*(C`hot\*(C'\fR, \f(CW\*(C`leaf\*(C'\fR, \f(CW\*(C`malloc\*(C'\fR, +\&\f(CW\*(C`nonnull\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, \f(CW\*(C`nothrow\*(C'\fR, \f(CW\*(C`pure\*(C'\fR, +\&\f(CW\*(C`returns_nonnull\*(C'\fR, and \f(CW\*(C`returns_twice\*(C'\fR. +.Sp +In \*(C+, the warning is issued when an explicit specialization of a primary +template declared with attribute \f(CW\*(C`alloc_align\*(C'\fR, \f(CW\*(C`alloc_size\*(C'\fR, +\&\f(CW\*(C`assume_aligned\*(C'\fR, \f(CW\*(C`format\*(C'\fR, \f(CW\*(C`format_arg\*(C'\fR, \f(CW\*(C`malloc\*(C'\fR, +or \f(CW\*(C`nonnull\*(C'\fR is declared without it. Attributes \f(CW\*(C`deprecated\*(C'\fR, +\&\f(CW\*(C`error\*(C'\fR, and \f(CW\*(C`warning\*(C'\fR suppress the warning.. +.Sp +You can use the \f(CW\*(C`copy\*(C'\fR attribute to apply the same +set of attributes to a declaration as that on another declaration without +explicitly enumerating the attributes. This attribute can be applied +to declarations of functions, +variables, or types. +.Sp +\&\fB\-Wmissing\-attributes\fR is enabled by \fB\-Wall\fR. +.Sp +For example, since the declaration of the primary function template +below makes use of both attribute \f(CW\*(C`malloc\*(C'\fR and \f(CW\*(C`alloc_size\*(C'\fR +the declaration of the explicit specialization of the template is +diagnosed because it is missing one of the attributes. +.Sp +.Vb 3 +\& template +\& T* _\|_attribute_\|_ ((malloc, alloc_size (1))) +\& allocate (size_t); +\& +\& template <> +\& void* _\|_attribute_\|_ ((malloc)) // missing alloc_size +\& allocate (size_t); +.Ve +.IP "\fB\-Wmissing\-braces\fR" 4 +.IX Item "-Wmissing-braces" +Warn if an aggregate or union initializer is not fully bracketed. In +the following example, the initializer for \f(CW\*(C`a\*(C'\fR is not fully +bracketed, but that for \f(CW\*(C`b\*(C'\fR is fully bracketed. This warning is +enabled by \fB\-Wall\fR in C. +.Sp +.Vb 2 +\& int a[2][2] = { 0, 1, 2, 3 }; +\& int b[2][2] = { { 0, 1 }, { 2, 3 } }; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wmissing\-include\-dirs\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wmissing-include-dirs (C, , Objective-C and Objective- only)" +Warn if a user-supplied include directory does not exist. +.IP "\fB\-Wmissing\-profile\fR" 4 +.IX Item "-Wmissing-profile" +Warn if feedback profiles are missing when using the +\&\fB\-fprofile\-use\fR option. +This option diagnoses those cases where a new function or a new file is added +to the user code between compiling with \fB\-fprofile\-generate\fR and with +\&\fB\-fprofile\-use\fR, without regenerating the profiles. In these cases, the +profile feedback data files do not contain any profile feedback information for +the newly added function or file respectively. Also, in the case when profile +count data (.gcda) files are removed, \s-1GCC\s0 cannot use any profile feedback +information. In all these cases, warnings are issued to inform the user that a +profile generation step is due. \fB\-Wno\-missing\-profile\fR can be used to +disable the warning. Ignoring the warning can result in poorly optimized code. +Completely disabling the warning is not recommended and should be done only +when non-existent profile data is justified. +.IP "\fB\-Wmultistatement\-macros\fR" 4 +.IX Item "-Wmultistatement-macros" +Warn about unsafe multiple statement macros that appear to be guarded +by a clause such as \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR, \f(CW\*(C`for\*(C'\fR, \f(CW\*(C`switch\*(C'\fR, or +\&\f(CW\*(C`while\*(C'\fR, in which only the first statement is actually guarded after +the macro is expanded. +.Sp +For example: +.Sp +.Vb 3 +\& #define DOIT x++; y++ +\& if (c) +\& DOIT; +.Ve +.Sp +will increment \f(CW\*(C`y\*(C'\fR unconditionally, not just when \f(CW\*(C`c\*(C'\fR holds. +The can usually be fixed by wrapping the macro in a do-while loop: +.Sp +.Vb 3 +\& #define DOIT do { x++; y++; } while (0) +\& if (c) +\& DOIT; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR in C and \*(C+. +.IP "\fB\-Wparentheses\fR" 4 +.IX Item "-Wparentheses" +Warn if parentheses are omitted in certain contexts, such +as when there is an assignment in a context where a truth value +is expected, or when operators are nested whose precedence people +often get confused about. +.Sp +Also warn if a comparison like \f(CW\*(C`x<=y<=z\*(C'\fR appears; this is +equivalent to \f(CW\*(C`(x<=y ? 1 : 0) <= z\*(C'\fR, which is a different +interpretation from that of ordinary mathematical notation. +.Sp +Also warn for dangerous uses of the \s-1GNU\s0 extension to +\&\f(CW\*(C`?:\*(C'\fR with omitted middle operand. When the condition +in the \f(CW\*(C`?\*(C'\fR: operator is a boolean expression, the omitted value is +always 1. Often programmers expect it to be a value computed +inside the conditional expression instead. +.Sp +For \*(C+ this also warns for some cases of unnecessary parentheses in +declarations, which can indicate an attempt at a function call instead +of a declaration: +.Sp +.Vb 5 +\& { +\& // Declares a local variable called mymutex. +\& std::unique_lock (mymutex); +\& // User meant std::unique_lock lock (mymutex); +\& } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsequence\-point\fR" 4 +.IX Item "-Wsequence-point" +Warn about code that may have undefined semantics because of violations +of sequence point rules in the C and \*(C+ standards. +.Sp +The C and \*(C+ standards define the order in which expressions in a C/\*(C+ +program are evaluated in terms of \fIsequence points\fR, which represent +a partial ordering between the execution of parts of the program: those +executed before the sequence point, and those executed after it. These +occur after the evaluation of a full expression (one which is not part +of a larger expression), after the evaluation of the first operand of a +\&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a +function is called (but after the evaluation of its arguments and the +expression denoting the called function), and in certain other places. +Other than as expressed by the sequence point rules, the order of +evaluation of subexpressions of an expression is not specified. All +these rules describe only a partial order rather than a total order, +since, for example, if two functions are called within one expression +with no sequence point between them, the order in which the functions +are called is not specified. However, the standards committee have +ruled that function calls do not overlap. +.Sp +It is not specified when between sequence points modifications to the +values of objects take effect. Programs whose behavior depends on this +have undefined behavior; the C and \*(C+ standards specify that \*(L"Between +the previous and next sequence point an object shall have its stored +value modified at most once by the evaluation of an expression. +Furthermore, the prior value shall be read only to determine the value +to be stored.\*(R". If a program breaks these rules, the results on any +particular implementation are entirely unpredictable. +.Sp +Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n] += b[n++]\*(C'\fR and \f(CW\*(C`a[i++] = i;\*(C'\fR. Some more complicated cases are not +diagnosed by this option, and it may give an occasional false positive +result, but in general it has been found fairly effective at detecting +this sort of problem in programs. +.Sp +The \*(C+17 standard will define the order of evaluation of operands in +more cases: in particular it requires that the right-hand side of an +assignment be evaluated before the left-hand side, so the above +examples are no longer undefined. But this warning will still warn +about them, to help people avoid writing code that is undefined in C +and earlier revisions of \*(C+. +.Sp +The standard is worded confusingly, therefore there is some debate +over the precise meaning of the sequence point rules in subtle cases. +Links to discussions of the problem, including proposed formal +definitions, may be found on the \s-1GCC\s0 readings page, at +<\fBhttp://gcc.gnu.org/readings.html\fR>. +.Sp +This warning is enabled by \fB\-Wall\fR for C and \*(C+. +.IP "\fB\-Wno\-return\-local\-addr\fR" 4 +.IX Item "-Wno-return-local-addr" +Do not warn about returning a pointer (or in \*(C+, a reference) to a +variable that goes out of scope after the function returns. +.IP "\fB\-Wreturn\-type\fR" 4 +.IX Item "-Wreturn-type" +Warn whenever a function is defined with a return type that defaults +to \f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no +return value in a function whose return type is not \f(CW\*(C`void\*(C'\fR +(falling off the end of the function body is considered returning +without a value). +.Sp +For C only, warn about a \f(CW\*(C`return\*(C'\fR statement with an expression in a +function whose return type is \f(CW\*(C`void\*(C'\fR, unless the expression type is +also \f(CW\*(C`void\*(C'\fR. As a \s-1GNU\s0 extension, the latter case is accepted +without a warning unless \fB\-Wpedantic\fR is used. Attempting +to use the return value of a non\-\f(CW\*(C`void\*(C'\fR function other than \f(CW\*(C`main\*(C'\fR +that flows off the end by reaching the closing curly brace that terminates +the function is undefined. +.Sp +Unlike in C, in \*(C+, flowing off the end of a non\-\f(CW\*(C`void\*(C'\fR function other +than \f(CW\*(C`main\*(C'\fR results in undefined behavior even when the value of +the function is not used. +.Sp +This warning is enabled by default in \*(C+ and by \fB\-Wall\fR otherwise. +.IP "\fB\-Wshift\-count\-negative\fR" 4 +.IX Item "-Wshift-count-negative" +Warn if shift count is negative. This warning is enabled by default. +.IP "\fB\-Wshift\-count\-overflow\fR" 4 +.IX Item "-Wshift-count-overflow" +Warn if shift count >= width of type. This warning is enabled by default. +.IP "\fB\-Wshift\-negative\-value\fR" 4 +.IX Item "-Wshift-negative-value" +Warn if left shifting a negative value. This warning is enabled by +\&\fB\-Wextra\fR in C99 (and newer) and \*(C+11 to \*(C+17 modes. +.IP "\fB\-Wshift\-overflow\fR" 4 +.IX Item "-Wshift-overflow" +.PD 0 +.IP "\fB\-Wshift\-overflow=\fR\fIn\fR" 4 +.IX Item "-Wshift-overflow=n" +.PD +Warn about left shift overflows. This warning is enabled by +default in C99 and \*(C+11 modes (and newer). +.RS 4 +.IP "\fB\-Wshift\-overflow=1\fR" 4 +.IX Item "-Wshift-overflow=1" +This is the warning level of \fB\-Wshift\-overflow\fR and is enabled +by default in C99 and \*(C+11 modes (and newer). This warning level does +not warn about left-shifting 1 into the sign bit. (However, in C, such +an overflow is still rejected in contexts where an integer constant expression +is required.) No warning is emitted in \*(C+2A mode (and newer), as signed left +shifts always wrap. +.IP "\fB\-Wshift\-overflow=2\fR" 4 +.IX Item "-Wshift-overflow=2" +This warning level also warns about left-shifting 1 into the sign bit, +unless \*(C+14 mode (or newer) is active. +.RE +.RS 4 +.RE +.IP "\fB\-Wswitch\fR" 4 +.IX Item "-Wswitch" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this +warning.) \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used (even if there is a +\&\f(CW\*(C`default\*(C'\fR label). +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wswitch\-default\fR" 4 +.IX Item "-Wswitch-default" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR +case. +.IP "\fB\-Wswitch\-enum\fR" 4 +.IX Item "-Wswitch-enum" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used. The only difference +between \fB\-Wswitch\fR and this option is that this option gives a +warning about an omitted enumeration code even if there is a +\&\f(CW\*(C`default\*(C'\fR label. +.IP "\fB\-Wswitch\-bool\fR" 4 +.IX Item "-Wswitch-bool" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of boolean type +and the case values are outside the range of a boolean type. +It is possible to suppress this warning by casting the controlling +expression to a type other than \f(CW\*(C`bool\*(C'\fR. For example: +.Sp +.Vb 4 +\& switch ((int) (a == 4)) +\& { +\& ... +\& } +.Ve +.Sp +This warning is enabled by default for C and \*(C+ programs. +.IP "\fB\-Wswitch\-unreachable\fR" 4 +.IX Item "-Wswitch-unreachable" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement contains statements between the +controlling expression and the first case label, which will never be +executed. For example: +.Sp +.Vb 7 +\& switch (cond) +\& { +\& i = 15; +\& ... +\& case 5: +\& ... +\& } +.Ve +.Sp +\&\fB\-Wswitch\-unreachable\fR does not warn if the statement between the +controlling expression and the first case label is just a declaration: +.Sp +.Vb 8 +\& switch (cond) +\& { +\& int i; +\& ... +\& case 5: +\& i = 5; +\& ... +\& } +.Ve +.Sp +This warning is enabled by default for C and \*(C+ programs. +.IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 +.IX Item "-Wsync-nand (C and only)" +Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR +built-in functions are used. These functions changed semantics in \s-1GCC 4.4.\s0 +.IP "\fB\-Wunused\-but\-set\-parameter\fR" 4 +.IX Item "-Wunused-but-set-parameter" +Warn whenever a function parameter is assigned to, but otherwise unused +(aside from its declaration). +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR together with +\&\fB\-Wextra\fR. +.IP "\fB\-Wunused\-but\-set\-variable\fR" 4 +.IX Item "-Wunused-but-set-variable" +Warn whenever a local variable is assigned to, but otherwise unused +(aside from its declaration). +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR, which is enabled +by \fB\-Wall\fR. +.IP "\fB\-Wunused\-function\fR" 4 +.IX Item "-Wunused-function" +Warn whenever a static function is declared but not defined or a +non-inline static function is unused. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-label\fR" 4 +.IX Item "-Wunused-label" +Warn whenever a label is declared but not used. +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +Warn when a typedef locally defined in a function is not used. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-parameter\fR" 4 +.IX Item "-Wunused-parameter" +Warn whenever a function parameter is unused aside from its declaration. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.IP "\fB\-Wno\-unused\-result\fR" 4 +.IX Item "-Wno-unused-result" +Do not warn if a caller of a function marked with attribute +\&\f(CW\*(C`warn_unused_result\*(C'\fR does not use +its return value. The default is \fB\-Wunused\-result\fR. +.IP "\fB\-Wunused\-variable\fR" 4 +.IX Item "-Wunused-variable" +Warn whenever a local or static variable is unused aside from its +declaration. This option implies \fB\-Wunused\-const\-variable=1\fR for C, +but not for \*(C+. This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.IP "\fB\-Wunused\-const\-variable\fR" 4 +.IX Item "-Wunused-const-variable" +.PD 0 +.IP "\fB\-Wunused\-const\-variable=\fR\fIn\fR" 4 +.IX Item "-Wunused-const-variable=n" +.PD +Warn whenever a constant static variable is unused aside from its declaration. +\&\fB\-Wunused\-const\-variable=1\fR is enabled by \fB\-Wunused\-variable\fR +for C, but not for \*(C+. In C this declares variable storage, but in \*(C+ this +is not an error since const variables take the place of \f(CW\*(C`#define\*(C'\fRs. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.RS 4 +.IP "\fB\-Wunused\-const\-variable=1\fR" 4 +.IX Item "-Wunused-const-variable=1" +This is the warning level that is enabled by \fB\-Wunused\-variable\fR for +C. It warns only about unused static const variables defined in the main +compilation unit, but not about static const variables declared in any +header included. +.IP "\fB\-Wunused\-const\-variable=2\fR" 4 +.IX Item "-Wunused-const-variable=2" +This warning level also warns for unused constant static variables in +headers (excluding system headers). This is the warning level of +\&\fB\-Wunused\-const\-variable\fR and must be explicitly requested since +in \*(C+ this isn't an error and in C it might be harder to clean up all +headers included. +.RE +.RS 4 +.RE +.IP "\fB\-Wunused\-value\fR" 4 +.IX Item "-Wunused-value" +Warn whenever a statement computes a result that is explicitly not +used. To suppress this warning cast the unused expression to +\&\f(CW\*(C`void\*(C'\fR. This includes an expression-statement or the left-hand +side of a comma expression that contains no side effects. For example, +an expression such as \f(CW\*(C`x[i,j]\*(C'\fR causes a warning, while +\&\f(CW\*(C`x[(void)i,j]\*(C'\fR does not. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\fR" 4 +.IX Item "-Wunused" +All the above \fB\-Wunused\fR options combined. +.Sp +In order to get a warning about an unused function parameter, you must +either specify \fB\-Wextra \-Wunused\fR (note that \fB\-Wall\fR implies +\&\fB\-Wunused\fR), or separately specify \fB\-Wunused\-parameter\fR. +.IP "\fB\-Wuninitialized\fR" 4 +.IX Item "-Wuninitialized" +Warn if an automatic variable is used without first being initialized +or if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call. In \*(C+, +warn if a non-static reference or non-static \f(CW\*(C`const\*(C'\fR member +appears in a class without constructors. +.Sp +If you want to warn about code that uses the uninitialized value of the +variable in its own initializer, use the \fB\-Winit\-self\fR option. +.Sp +These warnings occur for individual uninitialized or clobbered +elements of structure, union or array variables as well as for +variables that are uninitialized or clobbered as a whole. They do +not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because +these warnings depend on optimization, the exact variables or elements +for which there are warnings depends on the precise optimization +options and version of \s-1GCC\s0 used. +.Sp +Note that there may be no warning about a variable that is used only +to compute a value that itself is never used, because such +computations may be deleted by data flow analysis before the warnings +are printed. +.IP "\fB\-Winvalid\-memory\-model\fR" 4 +.IX Item "-Winvalid-memory-model" +Warn for invocations of \fB_\|_atomic Builtins\fR, \fB_\|_sync Builtins\fR, +and the C11 atomic generic functions with a memory consistency argument +that is either invalid for the operation or outside the range of values +of the \f(CW\*(C`memory_order\*(C'\fR enumeration. For example, since the +\&\f(CW\*(C`_\|_atomic_store\*(C'\fR and \f(CW\*(C`_\|_atomic_store_n\*(C'\fR built-ins are only +defined for the relaxed, release, and sequentially consistent memory +orders the following code is diagnosed: +.Sp +.Vb 4 +\& void store (int *i) +\& { +\& _\|_atomic_store_n (i, 0, memory_order_consume); +\& } +.Ve +.Sp +\&\fB\-Winvalid\-memory\-model\fR is enabled by default. +.IP "\fB\-Wmaybe\-uninitialized\fR" 4 +.IX Item "-Wmaybe-uninitialized" +For an automatic (i.e. local) variable, if there exists a path from the +function entry to a use of the variable that is initialized, but there exist +some other paths for which the variable is not initialized, the compiler +emits a warning if it cannot prove the uninitialized paths are not +executed at run time. +.Sp +These warnings are only possible in optimizing compilation, because otherwise +\&\s-1GCC\s0 does not keep track of the state of variables. +.Sp +These warnings are made optional because \s-1GCC\s0 may not be able to determine when +the code is correct in spite of appearing to have an error. Here is one +example of how this can happen: +.Sp +.Vb 12 +\& { +\& int x; +\& switch (y) +\& { +\& case 1: x = 1; +\& break; +\& case 2: x = 4; +\& break; +\& case 3: x = 5; +\& } +\& foo (x); +\& } +.Ve +.Sp +If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is +always initialized, but \s-1GCC\s0 doesn't know this. To suppress the +warning, you need to provide a default case with \fBassert\fR\|(0) or +similar code. +.Sp +This option also warns when a non-volatile automatic variable might be +changed by a call to \f(CW\*(C`longjmp\*(C'\fR. +The compiler sees only the calls to \f(CW\*(C`setjmp\*(C'\fR. It cannot know +where \f(CW\*(C`longjmp\*(C'\fR will be called; in fact, a signal handler could +call it at any point in the code. As a result, you may get a warning +even when there is in fact no problem because \f(CW\*(C`longjmp\*(C'\fR cannot +in fact be called at the place that would cause a problem. +.Sp +Some spurious warnings can be avoided if you declare all the functions +you use that never return as \f(CW\*(C`noreturn\*(C'\fR. +.Sp +This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. +.IP "\fB\-Wunknown\-pragmas\fR" 4 +.IX Item "-Wunknown-pragmas" +Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by +\&\s-1GCC.\s0 If this command-line option is used, warnings are even issued +for unknown pragmas in system header files. This is not the case if +the warnings are only enabled by the \fB\-Wall\fR command-line option. +.IP "\fB\-Wno\-pragmas\fR" 4 +.IX Item "-Wno-pragmas" +Do not warn about misuses of pragmas, such as incorrect parameters, +invalid syntax, or conflicts between pragmas. See also +\&\fB\-Wunknown\-pragmas\fR. +.IP "\fB\-Wno\-prio\-ctor\-dtor\fR" 4 +.IX Item "-Wno-prio-ctor-dtor" +Do not warn if a priority from 0 to 100 is used for constructor or destructor. +The use of constructor and destructor attributes allow you to assign a +priority to the constructor/destructor to control its order of execution +before \f(CW\*(C`main\*(C'\fR is called or after it returns. The priority values must be +greater than 100 as the compiler reserves priority values between 0\-\-100 for +the implementation. +.IP "\fB\-Wstrict\-aliasing\fR" 4 +.IX Item "-Wstrict-aliasing" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code that might break the strict aliasing rules that the +compiler is using for optimization. The warning does not catch all +cases, but does attempt to catch the more common pitfalls. It is +included in \fB\-Wall\fR. +It is equivalent to \fB\-Wstrict\-aliasing=3\fR +.IP "\fB\-Wstrict\-aliasing=n\fR" 4 +.IX Item "-Wstrict-aliasing=n" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code that might break the strict aliasing rules that the +compiler is using for optimization. +Higher levels correspond to higher accuracy (fewer false positives). +Higher levels also correspond to more effort, similar to the way \fB\-O\fR +works. +\&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=3\fR. +.Sp +Level 1: Most aggressive, quick, least accurate. +Possibly useful when higher levels +do not warn but \fB\-fstrict\-aliasing\fR still breaks the code, as it has very few +false negatives. However, it has many false positives. +Warns for all pointer conversions between possibly incompatible types, +even if never dereferenced. Runs in the front end only. +.Sp +Level 2: Aggressive, quick, not too precise. +May still have many false positives (not as many as level 1 though), +and few false negatives (but possibly more than level 1). +Unlike level 1, it only warns when an address is taken. Warns about +incomplete types. Runs in the front end only. +.Sp +Level 3 (default for \fB\-Wstrict\-aliasing\fR): +Should have very few false positives and few false +negatives. Slightly slower than levels 1 or 2 when optimization is enabled. +Takes care of the common pun+dereference pattern in the front end: +\&\f(CW\*(C`*(int*)&some_float\*(C'\fR. +If optimization is enabled, it also runs in the back end, where it deals +with multiple statement cases using flow-sensitive points-to information. +Only warns when the converted pointer is dereferenced. +Does not warn about incomplete types. +.IP "\fB\-Wstrict\-overflow\fR" 4 +.IX Item "-Wstrict-overflow" +.PD 0 +.IP "\fB\-Wstrict\-overflow=\fR\fIn\fR" 4 +.IX Item "-Wstrict-overflow=n" +.PD +This option is only active when signed overflow is undefined. +It warns about cases where the compiler optimizes based on the +assumption that signed overflow does not occur. Note that it does not +warn about all cases where the code might overflow: it only warns +about cases where the compiler implements some optimization. Thus +this warning depends on the optimization level. +.Sp +An optimization that assumes that signed overflow does not occur is +perfectly safe if the values of the variables involved are such that +overflow never does, in fact, occur. Therefore this warning can +easily give a false positive: a warning about code that is not +actually a problem. To help focus on important issues, several +warning levels are defined. No warnings are issued for the use of +undefined signed overflow when estimating how many iterations a loop +requires, in particular when determining whether a loop will be +executed at all. +.RS 4 +.IP "\fB\-Wstrict\-overflow=1\fR" 4 +.IX Item "-Wstrict-overflow=1" +Warn about cases that are both questionable and easy to avoid. For +example the compiler simplifies +\&\f(CW\*(C`x + 1 > x\*(C'\fR to \f(CW1\fR. This level of +\&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels +are not, and must be explicitly requested. +.IP "\fB\-Wstrict\-overflow=2\fR" 4 +.IX Item "-Wstrict-overflow=2" +Also warn about other cases where a comparison is simplified to a +constant. For example: \f(CW\*(C`abs (x) >= 0\*(C'\fR. This can only be +simplified when signed integer overflow is undefined, because +\&\f(CW\*(C`abs (INT_MIN)\*(C'\fR overflows to \f(CW\*(C`INT_MIN\*(C'\fR, which is less than +zero. \fB\-Wstrict\-overflow\fR (with no level) is the same as +\&\fB\-Wstrict\-overflow=2\fR. +.IP "\fB\-Wstrict\-overflow=3\fR" 4 +.IX Item "-Wstrict-overflow=3" +Also warn about other cases where a comparison is simplified. For +example: \f(CW\*(C`x + 1 > 1\*(C'\fR is simplified to \f(CW\*(C`x > 0\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=4\fR" 4 +.IX Item "-Wstrict-overflow=4" +Also warn about other simplifications not covered by the above cases. +For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR is simplified to \f(CW\*(C`x * 2\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=5\fR" 4 +.IX Item "-Wstrict-overflow=5" +Also warn about cases where the compiler reduces the magnitude of a +constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR is +simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the +highest warning level because this simplification applies to many +comparisons, so this warning level gives a very large number of +false positives. +.RE +.RS 4 +.RE +.IP "\fB\-Wstringop\-overflow\fR" 4 +.IX Item "-Wstringop-overflow" +.PD 0 +.IP "\fB\-Wstringop\-overflow=\fR\fItype\fR" 4 +.IX Item "-Wstringop-overflow=type" +.PD +Warn for calls to string manipulation functions such as \f(CW\*(C`memcpy\*(C'\fR and +\&\f(CW\*(C`strcpy\*(C'\fR that are determined to overflow the destination buffer. The +optional argument is one greater than the type of Object Size Checking to +perform to determine the size of the destination. +The argument is meaningful only for functions that operate on character arrays +but not for raw memory functions like \f(CW\*(C`memcpy\*(C'\fR which always make use +of Object Size type\-0. The option also warns for calls that specify a size +in excess of the largest possible object or at most \f(CW\*(C`SIZE_MAX / 2\*(C'\fR bytes. +The option produces the best results with optimization enabled but can detect +a small subset of simple buffer overflows even without optimization in +calls to the \s-1GCC\s0 built-in functions like \f(CW\*(C`_\|_builtin_memcpy\*(C'\fR that +correspond to the standard functions. In any case, the option warns about +just a subset of buffer overflows detected by the corresponding overflow +checking built-ins. For example, the option will issue a warning for +the \f(CW\*(C`strcpy\*(C'\fR call below because it copies at least 5 characters +(the string \f(CW"blue"\fR including the terminating \s-1NUL\s0) into the buffer +of size 4. +.Sp +.Vb 11 +\& enum Color { blue, purple, yellow }; +\& const char* f (enum Color clr) +\& { +\& static char buf [4]; +\& const char *str; +\& switch (clr) +\& { +\& case blue: str = "blue"; break; +\& case purple: str = "purple"; break; +\& case yellow: str = "yellow"; break; +\& } +\& +\& return strcpy (buf, str); // warning here +\& } +.Ve +.Sp +Option \fB\-Wstringop\-overflow=2\fR is enabled by default. +.RS 4 +.IP "\fB\-Wstringop\-overflow\fR" 4 +.IX Item "-Wstringop-overflow" +.PD 0 +.IP "\fB\-Wstringop\-overflow=1\fR" 4 +.IX Item "-Wstringop-overflow=1" +.PD +The \fB\-Wstringop\-overflow=1\fR option uses type-zero Object Size Checking +to determine the sizes of destination objects. This is the default setting +of the option. At this setting the option will not warn for writes past +the end of subobjects of larger objects accessed by pointers unless the +size of the largest surrounding object is known. When the destination may +be one of several objects it is assumed to be the largest one of them. On +Linux systems, when optimization is enabled at this setting the option warns +for the same code as when the \f(CW\*(C`_FORTIFY_SOURCE\*(C'\fR macro is defined to +a non-zero value. +.IP "\fB\-Wstringop\-overflow=2\fR" 4 +.IX Item "-Wstringop-overflow=2" +The \fB\-Wstringop\-overflow=2\fR option uses type-one Object Size Checking +to determine the sizes of destination objects. At this setting the option +will warn about overflows when writing to members of the largest complete +objects whose exact size is known. It will, however, not warn for excessive +writes to the same members of unknown objects referenced by pointers since +they may point to arrays containing unknown numbers of elements. +.IP "\fB\-Wstringop\-overflow=3\fR" 4 +.IX Item "-Wstringop-overflow=3" +The \fB\-Wstringop\-overflow=3\fR option uses type-two Object Size Checking +to determine the sizes of destination objects. At this setting the option +warns about overflowing the smallest object or data member. This is the +most restrictive setting of the option that may result in warnings for safe +code. +.IP "\fB\-Wstringop\-overflow=4\fR" 4 +.IX Item "-Wstringop-overflow=4" +The \fB\-Wstringop\-overflow=4\fR option uses type-three Object Size Checking +to determine the sizes of destination objects. At this setting the option +will warn about overflowing any data members, and when the destination is +one of several objects it uses the size of the largest of them to decide +whether to issue a warning. Similarly to \fB\-Wstringop\-overflow=3\fR this +setting of the option may result in warnings for benign code. +.RE +.RS 4 +.RE +.IP "\fB\-Wstringop\-truncation\fR" 4 +.IX Item "-Wstringop-truncation" +Warn for calls to bounded string manipulation functions such as \f(CW\*(C`strncat\*(C'\fR, +\&\f(CW\*(C`strncpy\*(C'\fR, and \f(CW\*(C`stpncpy\*(C'\fR that may either truncate the copied string +or leave the destination unchanged. +.Sp +In the following example, the call to \f(CW\*(C`strncat\*(C'\fR specifies a bound that +is less than the length of the source string. As a result, the copy of +the source will be truncated and so the call is diagnosed. To avoid the +warning use \f(CW\*(C`bufsize \- strlen (buf) \- 1)\*(C'\fR as the bound. +.Sp +.Vb 4 +\& void append (char *buf, size_t bufsize) +\& { +\& strncat (buf, ".txt", 3); +\& } +.Ve +.Sp +As another example, the following call to \f(CW\*(C`strncpy\*(C'\fR results in copying +to \f(CW\*(C`d\*(C'\fR just the characters preceding the terminating \s-1NUL,\s0 without +appending the \s-1NUL\s0 to the end. Assuming the result of \f(CW\*(C`strncpy\*(C'\fR is +necessarily a NUL-terminated string is a common mistake, and so the call +is diagnosed. To avoid the warning when the result is not expected to be +NUL-terminated, call \f(CW\*(C`memcpy\*(C'\fR instead. +.Sp +.Vb 4 +\& void copy (char *d, const char *s) +\& { +\& strncpy (d, s, strlen (s)); +\& } +.Ve +.Sp +In the following example, the call to \f(CW\*(C`strncpy\*(C'\fR specifies the size +of the destination buffer as the bound. If the length of the source +string is equal to or greater than this size the result of the copy will +not be NUL-terminated. Therefore, the call is also diagnosed. To avoid +the warning, specify \f(CW\*(C`sizeof buf \- 1\*(C'\fR as the bound and set the last +element of the buffer to \f(CW\*(C`NUL\*(C'\fR. +.Sp +.Vb 6 +\& void copy (const char *s) +\& { +\& char buf[80]; +\& strncpy (buf, s, sizeof buf); +\& ... +\& } +.Ve +.Sp +In situations where a character array is intended to store a sequence +of bytes with no terminating \f(CW\*(C`NUL\*(C'\fR such an array may be annotated +with attribute \f(CW\*(C`nonstring\*(C'\fR to avoid this warning. Such arrays, +however, are not suitable arguments to functions that expect +\&\f(CW\*(C`NUL\*(C'\fR\-terminated strings. To help detect accidental misuses of +such arrays \s-1GCC\s0 issues warnings unless it can prove that the use is +safe. +.IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR|\fBformat\fR|\fBcold\fR|\fBmalloc\fR]" 4 +.IX Item "-Wsuggest-attribute=[pure|const|noreturn|format|cold|malloc]" +Warn for cases where adding an attribute may be beneficial. The +attributes currently supported are listed below. +.RS 4 +.IP "\fB\-Wsuggest\-attribute=pure\fR" 4 +.IX Item "-Wsuggest-attribute=pure" +.PD 0 +.IP "\fB\-Wsuggest\-attribute=const\fR" 4 +.IX Item "-Wsuggest-attribute=const" +.IP "\fB\-Wsuggest\-attribute=noreturn\fR" 4 +.IX Item "-Wsuggest-attribute=noreturn" +.IP "\fB\-Wmissing\-noreturn\fR" 4 +.IX Item "-Wmissing-noreturn" +.IP "\fB\-Wsuggest\-attribute=malloc\fR" 4 +.IX Item "-Wsuggest-attribute=malloc" +.PD +Warn about functions that might be candidates for attributes +\&\f(CW\*(C`pure\*(C'\fR, \f(CW\*(C`const\*(C'\fR or \f(CW\*(C`noreturn\*(C'\fR or \f(CW\*(C`malloc\*(C'\fR. The compiler +only warns for functions visible in other compilation units or (in the case of +\&\f(CW\*(C`pure\*(C'\fR and \f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns +normally. A function returns normally if it doesn't contain an infinite loop or +return abnormally by throwing, calling \f(CW\*(C`abort\*(C'\fR or trapping. This analysis +requires option \fB\-fipa\-pure\-const\fR, which is enabled by default at +\&\fB\-O\fR and higher. Higher optimization levels improve the accuracy +of the analysis. +.IP "\fB\-Wsuggest\-attribute=format\fR" 4 +.IX Item "-Wsuggest-attribute=format" +.PD 0 +.IP "\fB\-Wmissing\-format\-attribute\fR" 4 +.IX Item "-Wmissing-format-attribute" +.PD +Warn about function pointers that might be candidates for \f(CW\*(C`format\*(C'\fR +attributes. Note these are only possible candidates, not absolute ones. +\&\s-1GCC\s0 guesses that function pointers with \f(CW\*(C`format\*(C'\fR attributes that +are used in assignment, initialization, parameter passing or return +statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the +resulting type. I.e. the left-hand side of the assignment or +initialization, the type of the parameter variable, or the return type +of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR +attribute to avoid the warning. +.Sp +\&\s-1GCC\s0 also warns about function definitions that might be +candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only +possible candidates. \s-1GCC\s0 guesses that \f(CW\*(C`format\*(C'\fR attributes +might be appropriate for any function that calls a function like +\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the +case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are +appropriate may not be detected. +.IP "\fB\-Wsuggest\-attribute=cold\fR" 4 +.IX Item "-Wsuggest-attribute=cold" +Warn about functions that might be candidates for \f(CW\*(C`cold\*(C'\fR attribute. This +is based on static detection and generally will only warn about functions which +always leads to a call to another \f(CW\*(C`cold\*(C'\fR function such as wrappers of +\&\*(C+ \f(CW\*(C`throw\*(C'\fR or fatal error reporting functions leading to \f(CW\*(C`abort\*(C'\fR. +.RE +.RS 4 +.RE +.IP "\fB\-Wsuggest\-final\-types\fR" 4 +.IX Item "-Wsuggest-final-types" +Warn about types with virtual methods where code quality would be improved +if the type were declared with the \*(C+11 \f(CW\*(C`final\*(C'\fR specifier, +or, if possible, +declared in an anonymous namespace. This allows \s-1GCC\s0 to more aggressively +devirtualize the polymorphic calls. This warning is more effective with link +time optimization, where the information about the class hierarchy graph is +more complete. +.IP "\fB\-Wsuggest\-final\-methods\fR" 4 +.IX Item "-Wsuggest-final-methods" +Warn about virtual methods where code quality would be improved if the method +were declared with the \*(C+11 \f(CW\*(C`final\*(C'\fR specifier, +or, if possible, its type were +declared in an anonymous namespace or with the \f(CW\*(C`final\*(C'\fR specifier. +This warning is +more effective with link-time optimization, where the information about the +class hierarchy graph is more complete. It is recommended to first consider +suggestions of \fB\-Wsuggest\-final\-types\fR and then rebuild with new +annotations. +.IP "\fB\-Wsuggest\-override\fR" 4 +.IX Item "-Wsuggest-override" +Warn about overriding virtual functions that are not marked with the override +keyword. +.IP "\fB\-Walloc\-zero\fR" 4 +.IX Item "-Walloc-zero" +Warn about calls to allocation functions decorated with attribute +\&\f(CW\*(C`alloc_size\*(C'\fR that specify zero bytes, including those to the built-in +forms of the functions \f(CW\*(C`aligned_alloc\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`calloc\*(C'\fR, +\&\f(CW\*(C`malloc\*(C'\fR, and \f(CW\*(C`realloc\*(C'\fR. Because the behavior of these functions +when called with a zero size differs among implementations (and in the case +of \f(CW\*(C`realloc\*(C'\fR has been deprecated) relying on it may result in subtle +portability bugs and should be avoided. +.IP "\fB\-Walloc\-size\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Walloc-size-larger-than=byte-size" +Warn about calls to functions decorated with attribute \f(CW\*(C`alloc_size\*(C'\fR +that attempt to allocate objects larger than the specified number of bytes, +or where the result of the size computation in an integer type with infinite +precision would exceed the value of \fB\s-1PTRDIFF_MAX\s0\fR on the target. +\&\fB\-Walloc\-size\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-alloc\-size\-larger\-than\fR. +.IP "\fB\-Wno\-alloc\-size\-larger\-than\fR" 4 +.IX Item "-Wno-alloc-size-larger-than" +Disable \fB\-Walloc\-size\-larger\-than=\fR warnings. The option is +equivalent to \fB\-Walloc\-size\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or +larger. +.IP "\fB\-Walloca\fR" 4 +.IX Item "-Walloca" +This option warns on all uses of \f(CW\*(C`alloca\*(C'\fR in the source. +.IP "\fB\-Walloca\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Walloca-larger-than=byte-size" +This option warns on calls to \f(CW\*(C`alloca\*(C'\fR with an integer argument whose +value is either zero, or that is not bounded by a controlling predicate +that limits its value to at most \fIbyte-size\fR. It also warns for calls +to \f(CW\*(C`alloca\*(C'\fR where the bound value is unknown. Arguments of non-integer +types are considered unbounded even if they appear to be constrained to +the expected range. +.Sp +For example, a bounded case of \f(CW\*(C`alloca\*(C'\fR could be: +.Sp +.Vb 9 +\& void func (size_t n) +\& { +\& void *p; +\& if (n <= 1000) +\& p = alloca (n); +\& else +\& p = malloc (n); +\& f (p); +\& } +.Ve +.Sp +In the above example, passing \f(CW\*(C`\-Walloca\-larger\-than=1000\*(C'\fR would not +issue a warning because the call to \f(CW\*(C`alloca\*(C'\fR is known to be at most +1000 bytes. However, if \f(CW\*(C`\-Walloca\-larger\-than=500\*(C'\fR were passed, +the compiler would emit a warning. +.Sp +Unbounded uses, on the other hand, are uses of \f(CW\*(C`alloca\*(C'\fR with no +controlling predicate constraining its integer argument. For example: +.Sp +.Vb 5 +\& void func () +\& { +\& void *p = alloca (n); +\& f (p); +\& } +.Ve +.Sp +If \f(CW\*(C`\-Walloca\-larger\-than=500\*(C'\fR were passed, the above would trigger +a warning, but this time because of the lack of bounds checking. +.Sp +Note, that even seemingly correct code involving signed integers could +cause a warning: +.Sp +.Vb 8 +\& void func (signed int n) +\& { +\& if (n < 500) +\& { +\& p = alloca (n); +\& f (p); +\& } +\& } +.Ve +.Sp +In the above example, \fIn\fR could be negative, causing a larger than +expected argument to be implicitly cast into the \f(CW\*(C`alloca\*(C'\fR call. +.Sp +This option also warns when \f(CW\*(C`alloca\*(C'\fR is used in a loop. +.Sp +\&\fB\-Walloca\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default +but is usually only effective when \fB\-ftree\-vrp\fR is active (default +for \fB\-O2\fR and above). +.Sp +See also \fB\-Wvla\-larger\-than=\fR\fBbyte-size\fR. +.IP "\fB\-Wno\-alloca\-larger\-than\fR" 4 +.IX Item "-Wno-alloca-larger-than" +Disable \fB\-Walloca\-larger\-than=\fR warnings. The option is +equivalent to \fB\-Walloca\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Warray\-bounds\fR" 4 +.IX Item "-Warray-bounds" +.PD 0 +.IP "\fB\-Warray\-bounds=\fR\fIn\fR" 4 +.IX Item "-Warray-bounds=n" +.PD +This option is only active when \fB\-ftree\-vrp\fR is active +(default for \fB\-O2\fR and above). It warns about subscripts to arrays +that are always out of bounds. This warning is enabled by \fB\-Wall\fR. +.RS 4 +.IP "\fB\-Warray\-bounds=1\fR" 4 +.IX Item "-Warray-bounds=1" +This is the warning level of \fB\-Warray\-bounds\fR and is enabled +by \fB\-Wall\fR; higher levels are not, and must be explicitly requested. +.IP "\fB\-Warray\-bounds=2\fR" 4 +.IX Item "-Warray-bounds=2" +This warning level also warns about out of bounds access for +arrays at the end of a struct and for arrays accessed through +pointers. This warning level may give a larger number of +false positives and is deactivated by default. +.RE +.RS 4 +.RE +.IP "\fB\-Wattribute\-alias=\fR\fIn\fR" 4 +.IX Item "-Wattribute-alias=n" +.PD 0 +.IP "\fB\-Wno\-attribute\-alias\fR" 4 +.IX Item "-Wno-attribute-alias" +.PD +Warn about declarations using the \f(CW\*(C`alias\*(C'\fR and similar attributes whose +target is incompatible with the type of the alias. +.RS 4 +.IP "\fB\-Wattribute\-alias=1\fR" 4 +.IX Item "-Wattribute-alias=1" +The default warning level of the \fB\-Wattribute\-alias\fR option diagnoses +incompatibilities between the type of the alias declaration and that of its +target. Such incompatibilities are typically indicative of bugs. +.IP "\fB\-Wattribute\-alias=2\fR" 4 +.IX Item "-Wattribute-alias=2" +At this level \fB\-Wattribute\-alias\fR also diagnoses cases where +the attributes of the alias declaration are more restrictive than the +attributes applied to its target. These mismatches can potentially +result in incorrect code generation. In other cases they may be +benign and could be resolved simply by adding the missing attribute to +the target. For comparison, see the \fB\-Wmissing\-attributes\fR +option, which controls diagnostics when the alias declaration is less +restrictive than the target, rather than more restrictive. +.Sp +Attributes considered include \f(CW\*(C`alloc_align\*(C'\fR, \f(CW\*(C`alloc_size\*(C'\fR, +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`const\*(C'\fR, \f(CW\*(C`hot\*(C'\fR, \f(CW\*(C`leaf\*(C'\fR, \f(CW\*(C`malloc\*(C'\fR, +\&\f(CW\*(C`nonnull\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, \f(CW\*(C`nothrow\*(C'\fR, \f(CW\*(C`pure\*(C'\fR, +\&\f(CW\*(C`returns_nonnull\*(C'\fR, and \f(CW\*(C`returns_twice\*(C'\fR. +.RE +.RS 4 +.Sp +\&\fB\-Wattribute\-alias\fR is equivalent to \fB\-Wattribute\-alias=1\fR. +This is the default. You can disable these warnings with either +\&\fB\-Wno\-attribute\-alias\fR or \fB\-Wattribute\-alias=0\fR. +.RE +.IP "\fB\-Wbool\-compare\fR" 4 +.IX Item "-Wbool-compare" +Warn about boolean expression compared with an integer value different from +\&\f(CW\*(C`true\*(C'\fR/\f(CW\*(C`false\*(C'\fR. For instance, the following comparison is +always false: +.Sp +.Vb 3 +\& int n = 5; +\& ... +\& if ((n > 1) == 2) { ... } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wbool\-operation\fR" 4 +.IX Item "-Wbool-operation" +Warn about suspicious operations on expressions of a boolean type. For +instance, bitwise negation of a boolean is very likely a bug in the program. +For C, this warning also warns about incrementing or decrementing a boolean, +which rarely makes sense. (In \*(C+, decrementing a boolean is always invalid. +Incrementing a boolean is invalid in \*(C+17, and deprecated otherwise.) +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wduplicated\-branches\fR" 4 +.IX Item "-Wduplicated-branches" +Warn when an if-else has identical branches. This warning detects cases like +.Sp +.Vb 4 +\& if (p != NULL) +\& return 0; +\& else +\& return 0; +.Ve +.Sp +It doesn't warn when both branches contain just a null statement. This warning +also warn for conditional operators: +.Sp +.Vb 1 +\& int i = x ? *p : *p; +.Ve +.IP "\fB\-Wduplicated\-cond\fR" 4 +.IX Item "-Wduplicated-cond" +Warn about duplicated conditions in an if-else-if chain. For instance, +warn for the following code: +.Sp +.Vb 2 +\& if (p\->q != NULL) { ... } +\& else if (p\->q != NULL) { ... } +.Ve +.IP "\fB\-Wframe\-address\fR" 4 +.IX Item "-Wframe-address" +Warn when the \fB_\|_builtin_frame_address\fR or \fB_\|_builtin_return_address\fR +is called with an argument greater than 0. Such calls may return indeterminate +values or crash the program. The warning is included in \fB\-Wall\fR. +.IP "\fB\-Wno\-discarded\-qualifiers\fR (C and Objective-C only)" 4 +.IX Item "-Wno-discarded-qualifiers (C and Objective-C only)" +Do not warn if type qualifiers on pointers are being discarded. +Typically, the compiler warns if a \f(CW\*(C`const char *\*(C'\fR variable is +passed to a function that takes a \f(CW\*(C`char *\*(C'\fR parameter. This option +can be used to suppress such a warning. +.IP "\fB\-Wno\-discarded\-array\-qualifiers\fR (C and Objective-C only)" 4 +.IX Item "-Wno-discarded-array-qualifiers (C and Objective-C only)" +Do not warn if type qualifiers on arrays which are pointer targets +are being discarded. Typically, the compiler warns if a +\&\f(CW\*(C`const int (*)[]\*(C'\fR variable is passed to a function that +takes a \f(CW\*(C`int (*)[]\*(C'\fR parameter. This option can be used to +suppress such a warning. +.IP "\fB\-Wno\-incompatible\-pointer\-types\fR (C and Objective-C only)" 4 +.IX Item "-Wno-incompatible-pointer-types (C and Objective-C only)" +Do not warn when there is a conversion between pointers that have incompatible +types. This warning is for cases not covered by \fB\-Wno\-pointer\-sign\fR, +which warns for pointer argument passing or assignment with different +signedness. +.IP "\fB\-Wno\-int\-conversion\fR (C and Objective-C only)" 4 +.IX Item "-Wno-int-conversion (C and Objective-C only)" +Do not warn about incompatible integer to pointer and pointer to integer +conversions. This warning is about implicit conversions; for explicit +conversions the warnings \fB\-Wno\-int\-to\-pointer\-cast\fR and +\&\fB\-Wno\-pointer\-to\-int\-cast\fR may be used. +.IP "\fB\-Wno\-div\-by\-zero\fR" 4 +.IX Item "-Wno-div-by-zero" +Do not warn about compile-time integer division by zero. Floating-point +division by zero is not warned about, as it can be a legitimate way of +obtaining infinities and NaNs. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Print warning messages for constructs found in system header files. +Warnings from system headers are normally suppressed, on the assumption +that they usually do not indicate real problems and would only make the +compiler output harder to read. Using this command-line option tells +\&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user +code. However, note that using \fB\-Wall\fR in conjunction with this +option does \fInot\fR warn about unknown pragmas in system +headers\-\-\-for that, \fB\-Wunknown\-pragmas\fR must also be used. +.IP "\fB\-Wtautological\-compare\fR" 4 +.IX Item "-Wtautological-compare" +Warn if a self-comparison always evaluates to true or false. This +warning detects various mistakes such as: +.Sp +.Vb 3 +\& int i = 1; +\& ... +\& if (i > i) { ... } +.Ve +.Sp +This warning also warns about bitwise comparisons that always evaluate +to true or false, for instance: +.Sp +.Vb 1 +\& if ((a & 16) == 10) { ... } +.Ve +.Sp +will always be false. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wtrampolines\fR" 4 +.IX Item "-Wtrampolines" +Warn about trampolines generated for pointers to nested functions. +A trampoline is a small piece of data or code that is created at run +time on the stack when the address of a nested function is taken, and is +used to call the nested function indirectly. For some targets, it is +made up of data only and thus requires no special treatment. But, for +most targets, it is made up of code and thus requires the stack to be +made executable in order for the program to work properly. +.IP "\fB\-Wfloat\-equal\fR" 4 +.IX Item "-Wfloat-equal" +Warn if floating-point values are used in equality comparisons. +.Sp +The idea behind this is that sometimes it is convenient (for the +programmer) to consider floating-point values as approximations to +infinitely precise real numbers. If you are doing this, then you need +to compute (by analyzing the code, or in some other way) the maximum or +likely maximum error that the computation introduces, and allow for it +when performing comparisons (and when producing output, but that's a +different problem). In particular, instead of testing for equality, you +should check to see whether the two values have ranges that overlap; and +this is done with the relational operators, so equality comparisons are +probably mistaken. +.IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional (C and Objective-C only)" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO C.\s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C +equivalent, and/or problematic constructs that should be avoided. +.RS 4 +.IP "*" 4 +Macro parameters that appear within string literals in the macro body. +In traditional C macro replacement takes place within string literals, +but in \s-1ISO C\s0 it does not. +.IP "*" 4 +In traditional C, some preprocessor directives did not exist. +Traditional preprocessors only considered a line to be a directive +if the \fB#\fR appeared in column 1 on the line. Therefore +\&\fB\-Wtraditional\fR warns about directives that traditional C +understands but ignores because the \fB#\fR does not appear as the +first character on the line. It also suggests you hide directives like +\&\f(CW\*(C`#pragma\*(C'\fR not understood by traditional C by indenting them. Some +traditional implementations do not recognize \f(CW\*(C`#elif\*(C'\fR, so this option +suggests avoiding it altogether. +.IP "*" 4 +A function-like macro that appears without arguments. +.IP "*" 4 +The unary plus operator. +.IP "*" 4 +The \fBU\fR integer constant suffix, or the \fBF\fR or \fBL\fR floating-point +constant suffixes. (Traditional C does support the \fBL\fR suffix on integer +constants.) Note, these suffixes appear in macros defined in the system +headers of most modern systems, e.g. the \fB_MIN\fR/\fB_MAX\fR macros in \f(CW\*(C`\*(C'\fR. +Use of these macros in user code might normally lead to spurious +warnings, however \s-1GCC\s0's integrated preprocessor has enough context to +avoid warning in these cases. +.IP "*" 4 +A function declared external in one block and then used after the end of +the block. +.IP "*" 4 +A \f(CW\*(C`switch\*(C'\fR statement has an operand of type \f(CW\*(C`long\*(C'\fR. +.IP "*" 4 +A non\-\f(CW\*(C`static\*(C'\fR function declaration follows a \f(CW\*(C`static\*(C'\fR one. +This construct is not accepted by some traditional C compilers. +.IP "*" 4 +The \s-1ISO\s0 type of an integer constant has a different width or +signedness from its traditional type. This warning is only issued if +the base of the constant is ten. I.e. hexadecimal or octal values, which +typically represent bit patterns, are not warned about. +.IP "*" 4 +Usage of \s-1ISO\s0 string concatenation is detected. +.IP "*" 4 +Initialization of automatic aggregates. +.IP "*" 4 +Identifier conflicts with labels. Traditional C lacks a separate +namespace for labels. +.IP "*" 4 +Initialization of unions. If the initializer is zero, the warning is +omitted. This is done under the assumption that the zero initializer in +user code appears conditioned on e.g. \f(CW\*(C`_\|_STDC_\|_\*(C'\fR to avoid missing +initializer warnings and relies on default initialization to zero in the +traditional C case. +.IP "*" 4 +Conversions by prototypes between fixed/floating\-point values and vice +versa. The absence of these prototypes when compiling with traditional +C causes serious problems. This is a subset of the possible +conversion warnings; for the full set use \fB\-Wtraditional\-conversion\fR. +.IP "*" 4 +Use of \s-1ISO C\s0 style function definitions. This warning intentionally is +\&\fInot\fR issued for prototype declarations or variadic functions +because these \s-1ISO C\s0 features appear in your code when using +libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and +\&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions +because that feature is already a \s-1GCC\s0 extension and thus not relevant to +traditional C compatibility. +.RE +.RS 4 +.RE +.IP "\fB\-Wtraditional\-conversion\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional-conversion (C and Objective-C only)" +Warn if a prototype causes a type conversion that is different from what +would happen to the same argument in the absence of a prototype. This +includes conversions of fixed point to floating and vice versa, and +conversions changing the width or signedness of a fixed-point argument +except when the same as the default promotion. +.IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 +.IX Item "-Wdeclaration-after-statement (C and Objective-C only)" +Warn when a declaration is found after a statement in a block. This +construct, known from \*(C+, was introduced with \s-1ISO C99\s0 and is by default +allowed in \s-1GCC.\s0 It is not supported by \s-1ISO C90.\s0 +.IP "\fB\-Wshadow\fR" 4 +.IX Item "-Wshadow" +Warn whenever a local variable or type declaration shadows another +variable, parameter, type, class member (in \*(C+), or instance variable +(in Objective-C) or whenever a built-in function is shadowed. Note +that in \*(C+, the compiler warns if a local variable shadows an +explicit typedef, but not if it shadows a struct/class/enum. +Same as \fB\-Wshadow=global\fR. +.IP "\fB\-Wno\-shadow\-ivar\fR (Objective-C only)" 4 +.IX Item "-Wno-shadow-ivar (Objective-C only)" +Do not warn whenever a local variable shadows an instance variable in an +Objective-C method. +.IP "\fB\-Wshadow=global\fR" 4 +.IX Item "-Wshadow=global" +The default for \fB\-Wshadow\fR. Warns for any (global) shadowing. +.IP "\fB\-Wshadow=local\fR" 4 +.IX Item "-Wshadow=local" +Warn when a local variable shadows another local variable or parameter. +This warning is enabled by \fB\-Wshadow=global\fR. +.IP "\fB\-Wshadow=compatible\-local\fR" 4 +.IX Item "-Wshadow=compatible-local" +Warn when a local variable shadows another local variable or parameter +whose type is compatible with that of the shadowing variable. In \*(C+, +type compatibility here means the type of the shadowing variable can be +converted to that of the shadowed variable. The creation of this flag +(in addition to \fB\-Wshadow=local\fR) is based on the idea that when +a local variable shadows another one of incompatible type, it is most +likely intentional, not a bug or typo, as shown in the following example: +.Sp +.Vb 8 +\& for (SomeIterator i = SomeObj.begin(); i != SomeObj.end(); ++i) +\& { +\& for (int i = 0; i < N; ++i) +\& { +\& ... +\& } +\& ... +\& } +.Ve +.Sp +Since the two variable \f(CW\*(C`i\*(C'\fR in the example above have incompatible types, +enabling only \fB\-Wshadow=compatible\-local\fR will not emit a warning. +Because their types are incompatible, if a programmer accidentally uses one +in place of the other, type checking will catch that and emit an error or +warning. So not warning (about shadowing) in this case will not lead to +undetected bugs. Use of this flag instead of \fB\-Wshadow=local\fR can +possibly reduce the number of warnings triggered by intentional shadowing. +.Sp +This warning is enabled by \fB\-Wshadow=local\fR. +.IP "\fB\-Wlarger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Wlarger-than=byte-size" +Warn whenever an object is defined whose size exceeds \fIbyte-size\fR. +\&\fB\-Wlarger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-larger\-than\fR. +.IP "\fB\-Wno\-larger\-than\fR" 4 +.IX Item "-Wno-larger-than" +Disable \fB\-Wlarger\-than=\fR warnings. The option is equivalent +to \fB\-Wlarger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wframe\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Wframe-larger-than=byte-size" +Warn if the size of a function frame exceeds \fIbyte-size\fR. +The computation done to determine the stack frame size is approximate +and not conservative. +The actual requirements may be somewhat greater than \fIbyte-size\fR +even if you do not get a warning. In addition, any space allocated +via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related constructs +is not included by the compiler when determining +whether or not to issue a warning. +\&\fB\-Wframe\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-frame\-larger\-than\fR. +.IP "\fB\-Wno\-frame\-larger\-than\fR" 4 +.IX Item "-Wno-frame-larger-than" +Disable \fB\-Wframe\-larger\-than=\fR warnings. The option is equivalent +to \fB\-Wframe\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wno\-free\-nonheap\-object\fR" 4 +.IX Item "-Wno-free-nonheap-object" +Do not warn when attempting to free an object that was not allocated +on the heap. +.IP "\fB\-Wstack\-usage=\fR\fIbyte-size\fR" 4 +.IX Item "-Wstack-usage=byte-size" +Warn if the stack usage of a function might exceed \fIbyte-size\fR. +The computation done to determine the stack usage is conservative. +Any space allocated via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related +constructs is included by the compiler when determining whether or not to +issue a warning. +.Sp +The message is in keeping with the output of \fB\-fstack\-usage\fR. +.RS 4 +.IP "*" 4 +If the stack usage is fully static but exceeds the specified amount, it's: +.Sp +.Vb 1 +\& warning: stack usage is 1120 bytes +.Ve +.IP "*" 4 +If the stack usage is (partly) dynamic but bounded, it's: +.Sp +.Vb 1 +\& warning: stack usage might be 1648 bytes +.Ve +.IP "*" 4 +If the stack usage is (partly) dynamic and not bounded, it's: +.Sp +.Vb 1 +\& warning: stack usage might be unbounded +.Ve +.RE +.RS 4 +.Sp +\&\fB\-Wstack\-usage=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-stack\-usage\fR. +.RE +.IP "\fB\-Wno\-stack\-usage\fR" 4 +.IX Item "-Wno-stack-usage" +Disable \fB\-Wstack\-usage=\fR warnings. The option is equivalent +to \fB\-Wstack\-usage=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4 +.IX Item "-Wunsafe-loop-optimizations" +Warn if the loop cannot be optimized because the compiler cannot +assume anything on the bounds of the loop indices. With +\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler makes +such assumptions. +.IP "\fB\-Wno\-pedantic\-ms\-format\fR (MinGW targets only)" 4 +.IX Item "-Wno-pedantic-ms-format (MinGW targets only)" +When used in combination with \fB\-Wformat\fR +and \fB\-pedantic\fR without \s-1GNU\s0 extensions, this option +disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format +width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets, +which depend on the \s-1MS\s0 runtime. +.IP "\fB\-Waligned\-new\fR" 4 +.IX Item "-Waligned-new" +Warn about a new-expression of a type that requires greater alignment +than the \f(CW\*(C`alignof(std::max_align_t)\*(C'\fR but uses an allocation +function without an explicit alignment parameter. This option is +enabled by \fB\-Wall\fR. +.Sp +Normally this only warns about global allocation functions, but +\&\fB\-Waligned\-new=all\fR also warns about class member allocation +functions. +.IP "\fB\-Wplacement\-new\fR" 4 +.IX Item "-Wplacement-new" +.PD 0 +.IP "\fB\-Wplacement\-new=\fR\fIn\fR" 4 +.IX Item "-Wplacement-new=n" +.PD +Warn about placement new expressions with undefined behavior, such as +constructing an object in a buffer that is smaller than the type of +the object. For example, the placement new expression below is diagnosed +because it attempts to construct an array of 64 integers in a buffer only +64 bytes large. +.Sp +.Vb 2 +\& char buf [64]; +\& new (buf) int[64]; +.Ve +.Sp +This warning is enabled by default. +.RS 4 +.IP "\fB\-Wplacement\-new=1\fR" 4 +.IX Item "-Wplacement-new=1" +This is the default warning level of \fB\-Wplacement\-new\fR. At this +level the warning is not issued for some strictly undefined constructs that +\&\s-1GCC\s0 allows as extensions for compatibility with legacy code. For example, +the following \f(CW\*(C`new\*(C'\fR expression is not diagnosed at this level even +though it has undefined behavior according to the \*(C+ standard because +it writes past the end of the one-element array. +.Sp +.Vb 3 +\& struct S { int n, a[1]; }; +\& S *s = (S *)malloc (sizeof *s + 31 * sizeof s\->a[0]); +\& new (s\->a)int [32](); +.Ve +.IP "\fB\-Wplacement\-new=2\fR" 4 +.IX Item "-Wplacement-new=2" +At this level, in addition to diagnosing all the same constructs as at level +1, a diagnostic is also issued for placement new expressions that construct +an object in the last member of structure whose type is an array of a single +element and whose size is less than the size of the object being constructed. +While the previous example would be diagnosed, the following construct makes +use of the flexible member array extension to avoid the warning at level 2. +.Sp +.Vb 3 +\& struct S { int n, a[]; }; +\& S *s = (S *)malloc (sizeof *s + 32 * sizeof s\->a[0]); +\& new (s\->a)int [32](); +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-Wpointer\-arith\fR" 4 +.IX Item "-Wpointer-arith" +Warn about anything that depends on the \*(L"size of\*(R" a function type or +of \f(CW\*(C`void\*(C'\fR. \s-1GNU C\s0 assigns these types a size of 1, for +convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers +to functions. In \*(C+, warn also when an arithmetic operation involves +\&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-Wpedantic\fR. +.IP "\fB\-Wpointer\-compare\fR" 4 +.IX Item "-Wpointer-compare" +Warn if a pointer is compared with a zero character constant. This usually +means that the pointer was meant to be dereferenced. For example: +.Sp +.Vb 3 +\& const char *p = foo (); +\& if (p == \*(Aq\e0\*(Aq) +\& return 42; +.Ve +.Sp +Note that the code above is invalid in \*(C+11. +.Sp +This warning is enabled by default. +.IP "\fB\-Wtype\-limits\fR" 4 +.IX Item "-Wtype-limits" +Warn if a comparison is always true or always false due to the limited +range of the data type, but do not warn for constant expressions. For +example, warn if an unsigned variable is compared against zero with +\&\f(CW\*(C`<\*(C'\fR or \f(CW\*(C`>=\*(C'\fR. This warning is also enabled by +\&\fB\-Wextra\fR. +.IP "\fB\-Wabsolute\-value\fR (C and Objective-C only)" 4 +.IX Item "-Wabsolute-value (C and Objective-C only)" +Warn for calls to standard functions that compute the absolute value +of an argument when a more appropriate standard function is available. +For example, calling \f(CW\*(C`abs(3.14)\*(C'\fR triggers the warning because the +appropriate function to call to compute the absolute value of a double +argument is \f(CW\*(C`fabs\*(C'\fR. The option also triggers warnings when the +argument in a call to such a function has an unsigned type. This +warning can be suppressed with an explicit type cast and it is also +enabled by \fB\-Wextra\fR. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +.PD 0 +.IP "\fB\-Wcomments\fR" 4 +.IX Item "-Wcomments" +.PD +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a backslash-newline appears in a \fB//\fR comment. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Warn if any trigraphs are encountered that might change the meaning of +the program. Trigraphs within comments are not warned about, +except those that would form escaped newlines. +.Sp +This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not +given, this option is still enabled unless trigraphs are enabled. To +get trigraph conversion without warnings, but get the other +\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn if an undefined identifier is evaluated in an \f(CW\*(C`#if\*(C'\fR directive. +Such identifiers are replaced with zero. +.IP "\fB\-Wexpansion\-to\-defined\fR" 4 +.IX Item "-Wexpansion-to-defined" +Warn whenever \fBdefined\fR is encountered in the expansion of a macro +(including the case where the macro is expanded by an \fB#if\fR directive). +Such usage is not portable. +This warning is also enabled by \fB\-Wpedantic\fR and \fB\-Wextra\fR. +.IP "\fB\-Wunused\-macros\fR" 4 +.IX Item "-Wunused-macros" +Warn about macros defined in the main file that are unused. A macro +is \fIused\fR if it is expanded or tested for existence at least once. +The preprocessor also warns if the macro has not been used at the +time it is redefined or undefined. +.Sp +Built-in macros, macros defined on the command line, and macros +defined in include files are not warned about. +.Sp +\&\fINote:\fR If a macro is actually used, but only used in skipped +conditional blocks, then the preprocessor reports it as unused. To avoid the +warning in such a case, you might improve the scope of the macro's +definition by, for example, moving it into the first skipped block. +Alternatively, you could provide a dummy use with something like: +.Sp +.Vb 2 +\& #if defined the_macro_causing_the_warning +\& #endif +.Ve +.IP "\fB\-Wno\-endif\-labels\fR" 4 +.IX Item "-Wno-endif-labels" +Do not warn whenever an \f(CW\*(C`#else\*(C'\fR or an \f(CW\*(C`#endif\*(C'\fR are followed by text. +This sometimes happens in older programs with code of the form +.Sp +.Vb 5 +\& #if FOO +\& ... +\& #else FOO +\& ... +\& #endif FOO +.Ve +.Sp +The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments. +This warning is on by default. +.IP "\fB\-Wbad\-function\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wbad-function-cast (C and Objective-C only)" +Warn when a function call is cast to a non-matching type. +For example, warn if a call to a function returning an integer type +is cast to a pointer type. +.IP "\fB\-Wc90\-c99\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc90-c99-compat (C and Objective-C only)" +Warn about features not present in \s-1ISO C90,\s0 but present in \s-1ISO C99.\s0 +For instance, warn about use of variable length arrays, \f(CW\*(C`long long\*(C'\fR +type, \f(CW\*(C`bool\*(C'\fR type, compound literals, designated initializers, and so +on. This option is independent of the standards mode. Warnings are disabled +in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. +.IP "\fB\-Wc99\-c11\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc99-c11-compat (C and Objective-C only)" +Warn about features not present in \s-1ISO C99,\s0 but present in \s-1ISO C11.\s0 +For instance, warn about use of anonymous structures and unions, +\&\f(CW\*(C`_Atomic\*(C'\fR type qualifier, \f(CW\*(C`_Thread_local\*(C'\fR storage-class specifier, +\&\f(CW\*(C`_Alignas\*(C'\fR specifier, \f(CW\*(C`Alignof\*(C'\fR operator, \f(CW\*(C`_Generic\*(C'\fR keyword, +and so on. This option is independent of the standards mode. Warnings are +disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. +.IP "\fB\-Wc11\-c2x\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc11-c2x-compat (C and Objective-C only)" +Warn about features not present in \s-1ISO C11,\s0 but present in \s-1ISO C2X.\s0 +For instance, warn about omitting the string in \f(CW\*(C`_Static_assert\*(C'\fR. +This option is independent of the standards mode. Warnings are +disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. +.IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc++-compat (C and Objective-C only)" +Warn about \s-1ISO C\s0 constructs that are outside of the common subset of +\&\s-1ISO C\s0 and \s-1ISO \*(C+,\s0 e.g. request for implicit conversion from +\&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. +.IP "\fB\-Wc++11\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++11-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 1998\s0 +and \s-1ISO \*(C+ 2011,\s0 e.g., identifiers in \s-1ISO \*(C+ 1998\s0 that are keywords +in \s-1ISO \*(C+ 2011.\s0 This warning turns on \fB\-Wnarrowing\fR and is +enabled by \fB\-Wall\fR. +.IP "\fB\-Wc++14\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++14-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 2011\s0 +and \s-1ISO \*(C+ 2014.\s0 This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wc++17\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++17-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 2014\s0 +and \s-1ISO \*(C+ 2017.\s0 This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wcast\-qual\fR" 4 +.IX Item "-Wcast-qual" +Warn whenever a pointer is cast so as to remove a type qualifier from +the target type. For example, warn if a \f(CW\*(C`const char *\*(C'\fR is cast +to an ordinary \f(CW\*(C`char *\*(C'\fR. +.Sp +Also warn when making a cast that introduces a type qualifier in an +unsafe way. For example, casting \f(CW\*(C`char **\*(C'\fR to \f(CW\*(C`const char **\*(C'\fR +is unsafe, as in this example: +.Sp +.Vb 6 +\& /* p is char ** value. */ +\& const char **q = (const char **) p; +\& /* Assignment of readonly string to const char * is OK. */ +\& *q = "string"; +\& /* Now char** pointer points to read\-only memory. */ +\& **p = \*(Aqb\*(Aq; +.Ve +.IP "\fB\-Wcast\-align\fR" 4 +.IX Item "-Wcast-align" +Warn whenever a pointer is cast such that the required alignment of the +target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to +an \f(CW\*(C`int *\*(C'\fR on machines where integers can only be accessed at +two\- or four-byte boundaries. +.IP "\fB\-Wcast\-align=strict\fR" 4 +.IX Item "-Wcast-align=strict" +Warn whenever a pointer is cast such that the required alignment of the +target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to +an \f(CW\*(C`int *\*(C'\fR regardless of the target machine. +.IP "\fB\-Wcast\-function\-type\fR" 4 +.IX Item "-Wcast-function-type" +Warn when a function pointer is cast to an incompatible function pointer. +In a cast involving function types with a variable argument list only +the types of initial arguments that are provided are considered. +Any parameter of pointer-type matches any other pointer-type. Any benign +differences in integral types are ignored, like \f(CW\*(C`int\*(C'\fR vs. \f(CW\*(C`long\*(C'\fR +on \s-1ILP32\s0 targets. Likewise type qualifiers are ignored. The function +type \f(CW\*(C`void (*) (void)\*(C'\fR is special and matches everything, which can +be used to suppress this warning. +In a cast involving pointer to member types this warning warns whenever +the type cast is changing the pointer to member type. +This warning is enabled by \fB\-Wextra\fR. +.IP "\fB\-Wwrite\-strings\fR" 4 +.IX Item "-Wwrite-strings" +When compiling C, give string constants the type \f(CW\*(C`const +char[\f(CIlength\f(CW]\*(C'\fR so that copying the address of one into a +non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer produces a warning. These +warnings help you find at compile time code that can try to write +into a string constant, but only if you have been very careful about +using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it is +just a nuisance. This is why we did not make \fB\-Wall\fR request +these warnings. +.Sp +When compiling \*(C+, warn about the deprecated conversion from string +literals to \f(CW\*(C`char *\*(C'\fR. This warning is enabled by default for \*(C+ +programs. +.IP "\fB\-Wcatch\-value\fR" 4 +.IX Item "-Wcatch-value" +.PD 0 +.IP "\fB\-Wcatch\-value=\fR\fIn\fR\fB \fR(\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wcatch-value=n ( and Objective- only)" +.PD +Warn about catch handlers that do not catch via reference. +With \fB\-Wcatch\-value=1\fR (or \fB\-Wcatch\-value\fR for short) +warn about polymorphic class types that are caught by value. +With \fB\-Wcatch\-value=2\fR warn about all class types that are caught +by value. With \fB\-Wcatch\-value=3\fR warn about all types that are +not caught by reference. \fB\-Wcatch\-value\fR is enabled by \fB\-Wall\fR. +.IP "\fB\-Wclobbered\fR" 4 +.IX Item "-Wclobbered" +Warn for variables that might be changed by \f(CW\*(C`longjmp\*(C'\fR or +\&\f(CW\*(C`vfork\*(C'\fR. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wconditionally\-supported\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wconditionally-supported ( and Objective- only)" +Warn for conditionally-supported (\*(C+11 [intro.defs]) constructs. +.IP "\fB\-Wconversion\fR" 4 +.IX Item "-Wconversion" +Warn for implicit conversions that may alter a value. This includes +conversions between real and integer, like \f(CW\*(C`abs (x)\*(C'\fR when +\&\f(CW\*(C`x\*(C'\fR is \f(CW\*(C`double\*(C'\fR; conversions between signed and unsigned, +like \f(CW\*(C`unsigned ui = \-1\*(C'\fR; and conversions to smaller types, like +\&\f(CW\*(C`sqrtf (M_PI)\*(C'\fR. Do not warn for explicit casts like \f(CW\*(C`abs +((int) x)\*(C'\fR and \f(CW\*(C`ui = (unsigned) \-1\*(C'\fR, or if the value is not +changed by the conversion like in \f(CW\*(C`abs (2.0)\*(C'\fR. Warnings about +conversions between signed and unsigned integers can be disabled by +using \fB\-Wno\-sign\-conversion\fR. +.Sp +For \*(C+, also warn for confusing overload resolution for user-defined +conversions; and conversions that never use a type conversion +operator: conversions to \f(CW\*(C`void\*(C'\fR, the same type, a base class or a +reference to them. Warnings about conversions between signed and +unsigned integers are disabled by default in \*(C+ unless +\&\fB\-Wsign\-conversion\fR is explicitly enabled. +.IP "\fB\-Wno\-conversion\-null\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-conversion-null ( and Objective- only)" +Do not warn for conversions between \f(CW\*(C`NULL\*(C'\fR and non-pointer +types. \fB\-Wconversion\-null\fR is enabled by default. +.IP "\fB\-Wzero\-as\-null\-pointer\-constant\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wzero-as-null-pointer-constant ( and Objective- only)" +Warn when a literal \fB0\fR is used as null pointer constant. This can +be useful to facilitate the conversion to \f(CW\*(C`nullptr\*(C'\fR in \*(C+11. +.IP "\fB\-Wsubobject\-linkage\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsubobject-linkage ( and Objective- only)" +Warn if a class type has a base or a field whose type uses the anonymous +namespace or depends on a type with no linkage. If a type A depends on +a type B with no or internal linkage, defining it in multiple +translation units would be an \s-1ODR\s0 violation because the meaning of B +is different in each translation unit. If A only appears in a single +translation unit, the best way to silence the warning is to give it +internal linkage by putting it in an anonymous namespace as well. The +compiler doesn't give this warning for types defined in the main .C +file, as those are unlikely to have multiple definitions. +\&\fB\-Wsubobject\-linkage\fR is enabled by default. +.IP "\fB\-Wdangling\-else\fR" 4 +.IX Item "-Wdangling-else" +Warn about constructions where there may be confusion to which +\&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs. Here is an example of +such a case: +.Sp +.Vb 7 +\& { +\& if (a) +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +.Ve +.Sp +In C/\*(C+, every \f(CW\*(C`else\*(C'\fR branch belongs to the innermost possible +\&\f(CW\*(C`if\*(C'\fR statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR. This is +often not what the programmer expected, as illustrated in the above +example by indentation the programmer chose. When there is the +potential for this confusion, \s-1GCC\s0 issues a warning when this flag +is specified. To eliminate the warning, add explicit braces around +the innermost \f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR +can belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code +looks like this: +.Sp +.Vb 9 +\& { +\& if (a) +\& { +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +\& } +.Ve +.Sp +This warning is enabled by \fB\-Wparentheses\fR. +.IP "\fB\-Wdate\-time\fR" 4 +.IX Item "-Wdate-time" +Warn when macros \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, \f(CW\*(C`_\|_DATE_\|_\*(C'\fR or \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR +are encountered as they might prevent bit-wise-identical reproducible +compilations. +.IP "\fB\-Wdelete\-incomplete\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wdelete-incomplete ( and Objective- only)" +Warn when deleting a pointer to incomplete type, which may cause +undefined behavior at runtime. This warning is enabled by default. +.IP "\fB\-Wuseless\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wuseless-cast ( and Objective- only)" +Warn when an expression is casted to its own type. +.IP "\fB\-Wempty\-body\fR" 4 +.IX Item "-Wempty-body" +Warn if an empty body occurs in an \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR or \f(CW\*(C`do +while\*(C'\fR statement. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wenum\-compare\fR" 4 +.IX Item "-Wenum-compare" +Warn about a comparison between values of different enumerated types. +In \*(C+ enumerated type mismatches in conditional expressions are also +diagnosed and the warning is enabled by default. In C this warning is +enabled by \fB\-Wall\fR. +.IP "\fB\-Wextra\-semi\fR (\*(C+, Objective\-\*(C+ only)" 4 +.IX Item "-Wextra-semi (, Objective- only)" +Warn about redundant semicolon after in-class function definition. +.IP "\fB\-Wjump\-misses\-init\fR (C, Objective-C only)" 4 +.IX Item "-Wjump-misses-init (C, Objective-C only)" +Warn if a \f(CW\*(C`goto\*(C'\fR statement or a \f(CW\*(C`switch\*(C'\fR statement jumps +forward across the initialization of a variable, or jumps backward to a +label after the variable has been initialized. This only warns about +variables that are initialized when they are declared. This warning is +only supported for C and Objective-C; in \*(C+ this sort of branch is an +error in any case. +.Sp +\&\fB\-Wjump\-misses\-init\fR is included in \fB\-Wc++\-compat\fR. It +can be disabled with the \fB\-Wno\-jump\-misses\-init\fR option. +.IP "\fB\-Wsign\-compare\fR" 4 +.IX Item "-Wsign-compare" +Warn when a comparison between signed and unsigned values could produce +an incorrect result when the signed value is converted to unsigned. +In \*(C+, this warning is also enabled by \fB\-Wall\fR. In C, it is +also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wsign\-conversion\fR" 4 +.IX Item "-Wsign-conversion" +Warn for implicit conversions that may change the sign of an integer +value, like assigning a signed integer expression to an unsigned +integer variable. An explicit cast silences the warning. In C, this +option is enabled also by \fB\-Wconversion\fR. +.IP "\fB\-Wfloat\-conversion\fR" 4 +.IX Item "-Wfloat-conversion" +Warn for implicit conversions that reduce the precision of a real value. +This includes conversions from real to integer, and from higher precision +real to lower precision real values. This option is also enabled by +\&\fB\-Wconversion\fR. +.IP "\fB\-Wno\-scalar\-storage\-order\fR" 4 +.IX Item "-Wno-scalar-storage-order" +Do not warn on suspicious constructs involving reverse scalar storage order. +.IP "\fB\-Wsized\-deallocation\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsized-deallocation ( and Objective- only)" +Warn about a definition of an unsized deallocation function +.Sp +.Vb 2 +\& void operator delete (void *) noexcept; +\& void operator delete[] (void *) noexcept; +.Ve +.Sp +without a definition of the corresponding sized deallocation function +.Sp +.Vb 2 +\& void operator delete (void *, std::size_t) noexcept; +\& void operator delete[] (void *, std::size_t) noexcept; +.Ve +.Sp +or vice versa. Enabled by \fB\-Wextra\fR along with +\&\fB\-fsized\-deallocation\fR. +.IP "\fB\-Wsizeof\-pointer\-div\fR" 4 +.IX Item "-Wsizeof-pointer-div" +Warn for suspicious divisions of two sizeof expressions that divide +the pointer size by the element size, which is the usual way to compute +the array size but won't work out correctly with pointers. This warning +warns e.g. about \f(CW\*(C`sizeof (ptr) / sizeof (ptr[0])\*(C'\fR if \f(CW\*(C`ptr\*(C'\fR is +not an array, but a pointer. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsizeof\-pointer\-memaccess\fR" 4 +.IX Item "-Wsizeof-pointer-memaccess" +Warn for suspicious length parameters to certain string and memory built-in +functions if the argument uses \f(CW\*(C`sizeof\*(C'\fR. This warning triggers for +example for \f(CW\*(C`memset (ptr, 0, sizeof (ptr));\*(C'\fR if \f(CW\*(C`ptr\*(C'\fR is not +an array, but a pointer, and suggests a possible fix, or about +\&\f(CW\*(C`memcpy (&foo, ptr, sizeof (&foo));\*(C'\fR. \fB\-Wsizeof\-pointer\-memaccess\fR +also warns about calls to bounded string copy functions like \f(CW\*(C`strncat\*(C'\fR +or \f(CW\*(C`strncpy\*(C'\fR that specify as the bound a \f(CW\*(C`sizeof\*(C'\fR expression of +the source array. For example, in the following function the call to +\&\f(CW\*(C`strncat\*(C'\fR specifies the size of the source string as the bound. That +is almost certainly a mistake and so the call is diagnosed. +.Sp +.Vb 7 +\& void make_file (const char *name) +\& { +\& char path[PATH_MAX]; +\& strncpy (path, name, sizeof path \- 1); +\& strncat (path, ".text", sizeof ".text"); +\& ... +\& } +.Ve +.Sp +The \fB\-Wsizeof\-pointer\-memaccess\fR option is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsizeof\-array\-argument\fR" 4 +.IX Item "-Wsizeof-array-argument" +Warn when the \f(CW\*(C`sizeof\*(C'\fR operator is applied to a parameter that is +declared as an array in a function definition. This warning is enabled by +default for C and \*(C+ programs. +.IP "\fB\-Wmemset\-elt\-size\fR" 4 +.IX Item "-Wmemset-elt-size" +Warn for suspicious calls to the \f(CW\*(C`memset\*(C'\fR built-in function, if the +first argument references an array, and the third argument is a number +equal to the number of elements, but not equal to the size of the array +in memory. This indicates that the user has omitted a multiplication by +the element size. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wmemset\-transposed\-args\fR" 4 +.IX Item "-Wmemset-transposed-args" +Warn for suspicious calls to the \f(CW\*(C`memset\*(C'\fR built-in function where +the second argument is not zero and the third argument is zero. For +example, the call \f(CW\*(C`memset (buf, sizeof buf, 0)\*(C'\fR is diagnosed because +\&\f(CW\*(C`memset (buf, 0, sizeof buf)\*(C'\fR was meant instead. The diagnostic +is only emitted if the third argument is a literal zero. Otherwise, if +it is an expression that is folded to zero, or a cast of zero to some +type, it is far less likely that the arguments have been mistakenly +transposed and no warning is emitted. This warning is enabled +by \fB\-Wall\fR. +.IP "\fB\-Waddress\fR" 4 +.IX Item "-Waddress" +Warn about suspicious uses of memory addresses. These include using +the address of a function in a conditional expression, such as +\&\f(CW\*(C`void func(void); if (func)\*(C'\fR, and comparisons against the memory +address of a string literal, such as \f(CW\*(C`if (x == "abc")\*(C'\fR. Such +uses typically indicate a programmer error: the address of a function +always evaluates to true, so their use in a conditional usually +indicate that the programmer forgot the parentheses in a function +call; and comparisons against string literals result in unspecified +behavior and are not portable in C, so they usually indicate that the +programmer intended to use \f(CW\*(C`strcmp\*(C'\fR. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Waddress\-of\-packed\-member\fR" 4 +.IX Item "-Waddress-of-packed-member" +Warn when the address of packed member of struct or union is taken, +which usually results in an unaligned pointer value. This is +enabled by default. +.IP "\fB\-Wlogical\-op\fR" 4 +.IX Item "-Wlogical-op" +Warn about suspicious uses of logical operators in expressions. +This includes using logical operators in contexts where a +bit-wise operator is likely to be expected. Also warns when +the operands of a logical operator are the same: +.Sp +.Vb 2 +\& extern int a; +\& if (a < 0 && a < 0) { ... } +.Ve +.IP "\fB\-Wlogical\-not\-parentheses\fR" 4 +.IX Item "-Wlogical-not-parentheses" +Warn about logical not used on the left hand side operand of a comparison. +This option does not warn if the right operand is considered to be a boolean +expression. Its purpose is to detect suspicious code like the following: +.Sp +.Vb 3 +\& int a; +\& ... +\& if (!a > 1) { ... } +.Ve +.Sp +It is possible to suppress the warning by wrapping the \s-1LHS\s0 into +parentheses: +.Sp +.Vb 1 +\& if ((!a) > 1) { ... } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Waggregate\-return\fR" 4 +.IX Item "-Waggregate-return" +Warn if any functions that return structures or unions are defined or +called. (In languages where you can return an array, this also elicits +a warning.) +.IP "\fB\-Wno\-aggressive\-loop\-optimizations\fR" 4 +.IX Item "-Wno-aggressive-loop-optimizations" +Warn if in a loop with constant number of iterations the compiler detects +undefined behavior in some statement during one or more of the iterations. +.IP "\fB\-Wno\-attributes\fR" 4 +.IX Item "-Wno-attributes" +Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as +unrecognized attributes, function attributes applied to variables, +etc. This does not stop errors for incorrect use of supported +attributes. +.IP "\fB\-Wno\-builtin\-declaration\-mismatch\fR" 4 +.IX Item "-Wno-builtin-declaration-mismatch" +Warn if a built-in function is declared with an incompatible signature +or as a non-function, or when a built-in function declared with a type +that does not include a prototype is called with arguments whose promoted +types do not match those expected by the function. When \fB\-Wextra\fR +is specified, also warn when a built-in function that takes arguments is +declared without a prototype. The \fB\-Wno\-builtin\-declaration\-mismatch\fR +warning is enabled by default. To avoid the warning include the appropriate +header to bring the prototypes of built-in functions into scope. +.Sp +For example, the call to \f(CW\*(C`memset\*(C'\fR below is diagnosed by the warning +because the function expects a value of type \f(CW\*(C`size_t\*(C'\fR as its argument +but the type of \f(CW32\fR is \f(CW\*(C`int\*(C'\fR. With \fB\-Wextra\fR, +the declaration of the function is diagnosed as well. +.Sp +.Vb 5 +\& extern void* memset (); +\& void f (void *d) +\& { +\& memset (d, \*(Aq\e0\*(Aq, 32); +\& } +.Ve +.IP "\fB\-Wno\-builtin\-macro\-redefined\fR" 4 +.IX Item "-Wno-builtin-macro-redefined" +Do not warn if certain built-in macros are redefined. This suppresses +warnings for redefinition of \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR, \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_DATE_\|_\*(C'\fR, \f(CW\*(C`_\|_FILE_\|_\*(C'\fR, and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR. +.IP "\fB\-Wstrict\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wstrict-prototypes (C and Objective-C only)" +Warn if a function is declared or defined without specifying the +argument types. (An old-style function definition is permitted without +a warning if preceded by a declaration that specifies the argument +types.) +.IP "\fB\-Wold\-style\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-declaration (C and Objective-C only)" +Warn for obsolescent usages, according to the C Standard, in a +declaration. For example, warn if storage-class specifiers like +\&\f(CW\*(C`static\*(C'\fR are not the first things in a declaration. This warning +is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wold\-style\-definition\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-definition (C and Objective-C only)" +Warn if an old-style function definition is used. A warning is given +even if there is a previous prototype. +.IP "\fB\-Wmissing\-parameter\-type\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-parameter-type (C and Objective-C only)" +A function parameter is declared without a type specifier in K&R\-style +functions: +.Sp +.Vb 1 +\& void foo(bar) { } +.Ve +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wmissing\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-prototypes (C and Objective-C only)" +Warn if a global function is defined without a previous prototype +declaration. This warning is issued even if the definition itself +provides a prototype. Use this option to detect global functions +that do not have a matching prototype declaration in a header file. +This option is not valid for \*(C+ because all function declarations +provide prototypes and a non-matching declaration declares an +overload rather than conflict with an earlier declaration. +Use \fB\-Wmissing\-declarations\fR to detect missing declarations in \*(C+. +.IP "\fB\-Wmissing\-declarations\fR" 4 +.IX Item "-Wmissing-declarations" +Warn if a global function is defined without a previous declaration. +Do so even if the definition itself provides a prototype. +Use this option to detect global functions that are not declared in +header files. In C, no warnings are issued for functions with previous +non-prototype declarations; use \fB\-Wmissing\-prototypes\fR to detect +missing prototypes. In \*(C+, no warnings are issued for function templates, +or for inline functions, or for functions in anonymous namespaces. +.IP "\fB\-Wmissing\-field\-initializers\fR" 4 +.IX Item "-Wmissing-field-initializers" +Warn if a structure's initializer has some fields missing. For +example, the following code causes such a warning, because +\&\f(CW\*(C`x.h\*(C'\fR is implicitly zero: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { 3, 4 }; +.Ve +.Sp +This option does not warn about designated initializers, so the following +modification does not trigger a warning: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { .f = 3, .g = 4 }; +.Ve +.Sp +In C this option does not warn about the universal zero initializer +\&\fB{ 0 }\fR: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { 0 }; +.Ve +.Sp +Likewise, in \*(C+ this option does not warn about the empty { } +initializer, for example: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& s x = { }; +.Ve +.Sp +This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR +warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR. +.IP "\fB\-Wno\-multichar\fR" 4 +.IX Item "-Wno-multichar" +Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used. +Usually they indicate a typo in the user's code, as they have +implementation-defined values, and should not be used in portable code. +.IP "\fB\-Wnormalized=\fR[\fBnone\fR|\fBid\fR|\fBnfc\fR|\fBnfkc\fR]" 4 +.IX Item "-Wnormalized=[none|id|nfc|nfkc]" +In \s-1ISO C\s0 and \s-1ISO \*(C+,\s0 two identifiers are different if they are +different sequences of characters. However, sometimes when characters +outside the basic \s-1ASCII\s0 character set are used, you can have two +different character sequences that look the same. To avoid confusion, +the \s-1ISO 10646\s0 standard sets out some \fInormalization rules\fR which +when applied ensure that two sequences that look the same are turned into +the same sequence. \s-1GCC\s0 can warn you if you are using identifiers that +have not been normalized; this option controls that warning. +.Sp +There are four levels of warning supported by \s-1GCC.\s0 The default is +\&\fB\-Wnormalized=nfc\fR, which warns about any identifier that is +not in the \s-1ISO 10646 \*(L"C\*(R"\s0 normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the +recommended form for most uses. It is equivalent to +\&\fB\-Wnormalized\fR. +.Sp +Unfortunately, there are some characters allowed in identifiers by +\&\s-1ISO C\s0 and \s-1ISO \*(C+\s0 that, when turned into \s-1NFC,\s0 are not allowed in +identifiers. That is, there's no way to use these symbols in portable +\&\s-1ISO C\s0 or \*(C+ and have all your identifiers in \s-1NFC.\s0 +\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. +It is hoped that future versions of the standards involved will correct +this, which is why this option is not the default. +.Sp +You can switch the warning off for all characters by writing +\&\fB\-Wnormalized=none\fR or \fB\-Wno\-normalized\fR. You should +only do this if you are using some other normalization scheme (like +\&\*(L"D\*(R"), because otherwise you can easily create bugs that are +literally impossible to see. +.Sp +Some characters in \s-1ISO 10646\s0 have distinct meanings but look identical +in some fonts or display methodologies, especially once formatting has +been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT LATIN SMALL +LETTER N\*(R",\s0 displays just like a regular \f(CW\*(C`n\*(C'\fR that has been +placed in a superscript. \s-1ISO 10646\s0 defines the \fI\s-1NFKC\s0\fR +normalization scheme to convert all these into a standard form as +well, and \s-1GCC\s0 warns if your code is not in \s-1NFKC\s0 if you use +\&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning +about every identifier that contains the letter O because it might be +confused with the digit 0, and so is not the default, but may be +useful as a local coding convention if the programming environment +cannot be fixed to display these characters distinctly. +.IP "\fB\-Wno\-attribute\-warning\fR" 4 +.IX Item "-Wno-attribute-warning" +Do not warn about usage of functions +declared with \f(CW\*(C`warning\*(C'\fR attribute. By default, this warning is +enabled. \fB\-Wno\-attribute\-warning\fR can be used to disable the +warning or \fB\-Wno\-error=attribute\-warning\fR can be used to +disable the error when compiled with \fB\-Werror\fR flag. +.IP "\fB\-Wno\-deprecated\fR" 4 +.IX Item "-Wno-deprecated" +Do not warn about usage of deprecated features. +.IP "\fB\-Wno\-deprecated\-declarations\fR" 4 +.IX Item "-Wno-deprecated-declarations" +Do not warn about uses of functions, +variables, and types marked as deprecated by using the \f(CW\*(C`deprecated\*(C'\fR +attribute. +.IP "\fB\-Wno\-overflow\fR" 4 +.IX Item "-Wno-overflow" +Do not warn about compile-time overflow in constant expressions. +.IP "\fB\-Wno\-odr\fR" 4 +.IX Item "-Wno-odr" +Warn about One Definition Rule violations during link-time optimization. +Requires \fB\-flto\-odr\-type\-merging\fR to be enabled. Enabled by default. +.IP "\fB\-Wopenmp\-simd\fR" 4 +.IX Item "-Wopenmp-simd" +Warn if the vectorizer cost model overrides the OpenMP +simd directive set by user. The \fB\-fsimd\-cost\-model=unlimited\fR +option can be used to relax the cost model. +.IP "\fB\-Woverride\-init\fR (C and Objective-C only)" 4 +.IX Item "-Woverride-init (C and Objective-C only)" +Warn if an initialized field without side effects is overridden when +using designated initializers. +.Sp +This warning is included in \fB\-Wextra\fR. To get other +\&\fB\-Wextra\fR warnings without this one, use \fB\-Wextra +\&\-Wno\-override\-init\fR. +.IP "\fB\-Woverride\-init\-side\-effects\fR (C and Objective-C only)" 4 +.IX Item "-Woverride-init-side-effects (C and Objective-C only)" +Warn if an initialized field with side effects is overridden when +using designated initializers. This warning is enabled by default. +.IP "\fB\-Wpacked\fR" 4 +.IX Item "-Wpacked" +Warn if a structure is given the packed attribute, but the packed +attribute has no effect on the layout or size of the structure. +Such structures may be mis-aligned for little benefit. For +instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR +is misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself +have the packed attribute: +.Sp +.Vb 8 +\& struct foo { +\& int x; +\& char a, b, c, d; +\& } _\|_attribute_\|_((packed)); +\& struct bar { +\& char z; +\& struct foo f; +\& }; +.Ve +.IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 +.IX Item "-Wpacked-bitfield-compat" +The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute +on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC 4.4\s0 but +the change can lead to differences in the structure layout. \s-1GCC\s0 +informs you when the offset of such a field has changed in \s-1GCC 4.4.\s0 +For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR +and \f(CW\*(C`b\*(C'\fR in this structure: +.Sp +.Vb 5 +\& struct foo +\& { +\& char a:4; +\& char b:8; +\& } _\|_attribute_\|_ ((packed)); +.Ve +.Sp +This warning is enabled by default. Use +\&\fB\-Wno\-packed\-bitfield\-compat\fR to disable this warning. +.IP "\fB\-Wpacked\-not\-aligned\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wpacked-not-aligned (C, , Objective-C and Objective- only)" +Warn if a structure field with explicitly specified alignment in a +packed struct or union is misaligned. For example, a warning will +be issued on \f(CW\*(C`struct S\*(C'\fR, like, \f(CW\*(C`warning: alignment 1 of +\&\*(Aqstruct S\*(Aq is less than 8\*(C'\fR, in this code: +.Sp +.Vb 4 +\& struct _\|_attribute_\|_ ((aligned (8))) S8 { char a[8]; }; +\& struct _\|_attribute_\|_ ((packed)) S { +\& struct S8 s8; +\& }; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wpadded\fR" 4 +.IX Item "-Wpadded" +Warn if padding is included in a structure, either to align an element +of the structure or to align the whole structure. Sometimes when this +happens it is possible to rearrange the fields of the structure to +reduce the padding and so make the structure smaller. +.IP "\fB\-Wredundant\-decls\fR" 4 +.IX Item "-Wredundant-decls" +Warn if anything is declared more than once in the same scope, even in +cases where multiple declaration is valid and changes nothing. +.IP "\fB\-Wno\-restrict\fR" 4 +.IX Item "-Wno-restrict" +Warn when an object referenced by a \f(CW\*(C`restrict\*(C'\fR\-qualified parameter +(or, in \*(C+, a \f(CW\*(C`_\|_restrict\*(C'\fR\-qualified parameter) is aliased by another +argument, or when copies between such objects overlap. For example, +the call to the \f(CW\*(C`strcpy\*(C'\fR function below attempts to truncate the string +by replacing its initial characters with the last four. However, because +the call writes the terminating \s-1NUL\s0 into \f(CW\*(C`a[4]\*(C'\fR, the copies overlap and +the call is diagnosed. +.Sp +.Vb 6 +\& void foo (void) +\& { +\& char a[] = "abcd1234"; +\& strcpy (a, a + 4); +\& ... +\& } +.Ve +.Sp +The \fB\-Wrestrict\fR option detects some instances of simple overlap +even without optimization but works best at \fB\-O2\fR and above. It +is included in \fB\-Wall\fR. +.IP "\fB\-Wnested\-externs\fR (C and Objective-C only)" 4 +.IX Item "-Wnested-externs (C and Objective-C only)" +Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function. +.IP "\fB\-Wno\-inherited\-variadic\-ctor\fR" 4 +.IX Item "-Wno-inherited-variadic-ctor" +Suppress warnings about use of \*(C+11 inheriting constructors when the +base class inherited from has a C variadic constructor; the warning is +on by default because the ellipsis is not inherited. +.IP "\fB\-Winline\fR" 4 +.IX Item "-Winline" +Warn if a function that is declared as inline cannot be inlined. +Even with this option, the compiler does not warn about failures to +inline functions declared in system headers. +.Sp +The compiler uses a variety of heuristics to determine whether or not +to inline a function. For example, the compiler takes into account +the size of the function being inlined and the amount of inlining +that has already been done in the current function. Therefore, +seemingly insignificant changes in the source program can cause the +warnings produced by \fB\-Winline\fR to appear or disappear. +.IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-invalid-offsetof ( and Objective- only)" +Suppress warnings from applying the \f(CW\*(C`offsetof\*(C'\fR macro to a non-POD +type. According to the 2014 \s-1ISO \*(C+\s0 standard, applying \f(CW\*(C`offsetof\*(C'\fR +to a non-standard-layout type is undefined. In existing \*(C+ implementations, +however, \f(CW\*(C`offsetof\*(C'\fR typically gives meaningful results. +This flag is for users who are aware that they are +writing nonportable code and who have deliberately chosen to ignore the +warning about it. +.Sp +The restrictions on \f(CW\*(C`offsetof\*(C'\fR may be relaxed in a future version +of the \*(C+ standard. +.IP "\fB\-Wint\-in\-bool\-context\fR" 4 +.IX Item "-Wint-in-bool-context" +Warn for suspicious use of integer values where boolean values are expected, +such as conditional expressions (?:) using non-boolean integer constants in +boolean context, like \f(CW\*(C`if (a <= b ? 2 : 3)\*(C'\fR. Or left shifting of signed +integers in boolean context, like \f(CW\*(C`for (a = 0; 1 << a; a++);\*(C'\fR. Likewise +for all kinds of multiplications regardless of the data type. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-int\-to\-pointer\-cast\fR" 4 +.IX Item "-Wno-int-to-pointer-cast" +Suppress warnings from casts to pointer type of an integer of a +different size. In \*(C+, casting to a pointer type of smaller size is +an error. \fBWint-to-pointer-cast\fR is enabled by default. +.IP "\fB\-Wno\-pointer\-to\-int\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wno-pointer-to-int-cast (C and Objective-C only)" +Suppress warnings from casts from a pointer to an integer type of a +different size. +.IP "\fB\-Winvalid\-pch\fR" 4 +.IX Item "-Winvalid-pch" +Warn if a precompiled header is found in +the search path but cannot be used. +.IP "\fB\-Wlong\-long\fR" 4 +.IX Item "-Wlong-long" +Warn if \f(CW\*(C`long long\*(C'\fR type is used. This is enabled by either +\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO C90\s0 and \*(C+98 +modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. +.IP "\fB\-Wvariadic\-macros\fR" 4 +.IX Item "-Wvariadic-macros" +Warn if variadic macros are used in \s-1ISO C90\s0 mode, or if the \s-1GNU\s0 +alternate syntax is used in \s-1ISO C99\s0 mode. This is enabled by either +\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR. To inhibit the warning +messages, use \fB\-Wno\-variadic\-macros\fR. +.IP "\fB\-Wvarargs\fR" 4 +.IX Item "-Wvarargs" +Warn upon questionable usage of the macros used to handle variable +arguments like \f(CW\*(C`va_start\*(C'\fR. This is default. To inhibit the +warning messages, use \fB\-Wno\-varargs\fR. +.IP "\fB\-Wvector\-operation\-performance\fR" 4 +.IX Item "-Wvector-operation-performance" +Warn if vector operation is not implemented via \s-1SIMD\s0 capabilities of the +architecture. Mainly useful for the performance tuning. +Vector operation can be implemented \f(CW\*(C`piecewise\*(C'\fR, which means that the +scalar operation is performed on every vector element; +\&\f(CW\*(C`in parallel\*(C'\fR, which means that the vector operation is implemented +using scalars of wider type, which normally is more performance efficient; +and \f(CW\*(C`as a single scalar\*(C'\fR, which means that vector fits into a +scalar type. +.IP "\fB\-Wno\-virtual\-move\-assign\fR" 4 +.IX Item "-Wno-virtual-move-assign" +Suppress warnings about inheriting from a virtual base with a +non-trivial \*(C+11 move assignment operator. This is dangerous because +if the virtual base is reachable along more than one path, it is +moved multiple times, which can mean both objects end up in the +moved-from state. If the move assignment operator is written to avoid +moving from a moved-from object, this warning can be disabled. +.IP "\fB\-Wvla\fR" 4 +.IX Item "-Wvla" +Warn if a variable-length array is used in the code. +\&\fB\-Wno\-vla\fR prevents the \fB\-Wpedantic\fR warning of +the variable-length array. +.IP "\fB\-Wvla\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Wvla-larger-than=byte-size" +If this option is used, the compiler will warn for declarations of +variable-length arrays whose size is either unbounded, or bounded +by an argument that allows the array size to exceed \fIbyte-size\fR +bytes. This is similar to how \fB\-Walloca\-larger\-than=\fR\fIbyte-size\fR +works, but with variable-length arrays. +.Sp +Note that \s-1GCC\s0 may optimize small variable-length arrays of a known +value into plain arrays, so this warning may not get triggered for +such arrays. +.Sp +\&\fB\-Wvla\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default but +is typically only effective when \fB\-ftree\-vrp\fR is active (default +for \fB\-O2\fR and above). +.Sp +See also \fB\-Walloca\-larger\-than=\fR\fIbyte-size\fR. +.IP "\fB\-Wno\-vla\-larger\-than\fR" 4 +.IX Item "-Wno-vla-larger-than" +Disable \fB\-Wvla\-larger\-than=\fR warnings. The option is equivalent +to \fB\-Wvla\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wvolatile\-register\-var\fR" 4 +.IX Item "-Wvolatile-register-var" +Warn if a register variable is declared volatile. The volatile +modifier does not inhibit all optimizations that may eliminate reads +and/or writes to register variables. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wdisabled\-optimization\fR" 4 +.IX Item "-Wdisabled-optimization" +Warn if a requested optimization pass is disabled. This warning does +not generally indicate that there is anything wrong with your code; it +merely indicates that \s-1GCC\s0's optimizers are unable to handle the code +effectively. Often, the problem is that your code is too big or too +complex; \s-1GCC\s0 refuses to optimize programs when the optimization +itself is likely to take inordinate amounts of time. +.IP "\fB\-Wpointer\-sign\fR (C and Objective-C only)" 4 +.IX Item "-Wpointer-sign (C and Objective-C only)" +Warn for pointer argument passing or assignment with different signedness. +This option is only supported for C and Objective-C. It is implied by +\&\fB\-Wall\fR and by \fB\-Wpedantic\fR, which can be disabled with +\&\fB\-Wno\-pointer\-sign\fR. +.IP "\fB\-Wstack\-protector\fR" 4 +.IX Item "-Wstack-protector" +This option is only active when \fB\-fstack\-protector\fR is active. It +warns about functions that are not protected against stack smashing. +.IP "\fB\-Woverlength\-strings\fR" 4 +.IX Item "-Woverlength-strings" +Warn about string constants that are longer than the \*(L"minimum +maximum\*(R" length specified in the C standard. Modern compilers +generally allow string constants that are much longer than the +standard's minimum limit, but very portable programs should avoid +using longer strings. +.Sp +The limit applies \fIafter\fR string constant concatenation, and does +not count the trailing \s-1NUL.\s0 In C90, the limit was 509 characters; in +C99, it was raised to 4095. \*(C+98 does not specify a normative +minimum maximum, so we do not diagnose overlength strings in \*(C+. +.Sp +This option is implied by \fB\-Wpedantic\fR, and can be disabled with +\&\fB\-Wno\-overlength\-strings\fR. +.IP "\fB\-Wunsuffixed\-float\-constants\fR (C and Objective-C only)" 4 +.IX Item "-Wunsuffixed-float-constants (C and Objective-C only)" +Issue a warning for any floating constant that does not have +a suffix. When used together with \fB\-Wsystem\-headers\fR it +warns about such constants in system header files. This can be useful +when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma +from the decimal floating-point extension to C99. +.IP "\fB\-Wno\-designated\-init\fR (C and Objective-C only)" 4 +.IX Item "-Wno-designated-init (C and Objective-C only)" +Suppress warnings when a positional initializer is used to initialize +a structure that has been marked with the \f(CW\*(C`designated_init\*(C'\fR +attribute. +.IP "\fB\-Whsa\fR" 4 +.IX Item "-Whsa" +Issue a warning when \s-1HSAIL\s0 cannot be emitted for the compiled function or +OpenMP construct. +.SS "Options for Debugging Your Program" +.IX Subsection "Options for Debugging Your Program" +To tell \s-1GCC\s0 to emit extra information for use by a debugger, in almost +all cases you need only to add \fB\-g\fR to your other options. +.PP +\&\s-1GCC\s0 allows you to use \fB\-g\fR with +\&\fB\-O\fR. The shortcuts taken by optimized code may occasionally +be surprising: some variables you declared may not exist +at all; flow of control may briefly move where you did not expect it; +some statements may not be executed because they compute constant +results or their values are already at hand; some statements may +execute in different places because they have been moved out of loops. +Nevertheless it is possible to debug optimized output. This makes +it reasonable to use the optimizer for programs that might have bugs. +.PP +If you are not using some other optimization option, consider +using \fB\-Og\fR with \fB\-g\fR. +With no \fB\-O\fR option at all, some compiler passes that collect +information useful for debugging do not run at all, so that +\&\fB\-Og\fR may result in a better debugging experience. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +Produce debugging information in the operating system's native format +(stabs, \s-1COFF, XCOFF,\s0 or \s-1DWARF\s0). \s-1GDB\s0 can work with this debugging +information. +.Sp +On most systems that use stabs format, \fB\-g\fR enables use of extra +debugging information that only \s-1GDB\s0 can use; this extra information +makes debugging work better in \s-1GDB\s0 but probably makes other debuggers +crash or +refuse to read the program. If you want to control for certain whether +to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR, +\&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below). +.IP "\fB\-ggdb\fR" 4 +.IX Item "-ggdb" +Produce debugging information for use by \s-1GDB.\s0 This means to use the +most expressive format available (\s-1DWARF,\s0 stabs, or the native format +if neither of those are supported), including \s-1GDB\s0 extensions if at all +possible. +.IP "\fB\-gdwarf\fR" 4 +.IX Item "-gdwarf" +.PD 0 +.IP "\fB\-gdwarf\-\fR\fIversion\fR" 4 +.IX Item "-gdwarf-version" +.PD +Produce debugging information in \s-1DWARF\s0 format (if that is supported). +The value of \fIversion\fR may be either 2, 3, 4 or 5; the default version +for most targets is 4. \s-1DWARF\s0 Version 5 is only experimental. +.Sp +Note that with \s-1DWARF\s0 Version 2, some ports require and always +use some non-conflicting \s-1DWARF 3\s0 extensions in the unwind tables. +.Sp +Version 4 may require \s-1GDB 7.0\s0 and \fB\-fvar\-tracking\-assignments\fR +for maximum benefit. +.Sp +\&\s-1GCC\s0 no longer supports \s-1DWARF\s0 Version 1, which is substantially +different than Version 2 and later. For historical reasons, some +other DWARF-related options such as +\&\fB\-fno\-dwarf2\-cfi\-asm\fR) retain a reference to \s-1DWARF\s0 Version 2 +in their names, but apply to all currently-supported versions of \s-1DWARF.\s0 +.IP "\fB\-gstabs\fR" 4 +.IX Item "-gstabs" +Produce debugging information in stabs format (if that is supported), +without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 +systems. On \s-1MIPS,\s0 Alpha and System V Release 4 systems this option +produces stabs debugging output that is not understood by \s-1DBX.\s0 +On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. +.IP "\fB\-gstabs+\fR" 4 +.IX Item "-gstabs+" +Produce debugging information in stabs format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program. +.IP "\fB\-gxcoff\fR" 4 +.IX Item "-gxcoff" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported). +This is the format used by the \s-1DBX\s0 debugger on \s-1IBM RS/6000\s0 systems. +.IP "\fB\-gxcoff+\fR" 4 +.IX Item "-gxcoff+" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program, and may cause assemblers other than the \s-1GNU\s0 +assembler (\s-1GAS\s0) to fail with an error. +.IP "\fB\-gvms\fR" 4 +.IX Item "-gvms" +Produce debugging information in Alpha/VMS debug format (if that is +supported). This is the format used by \s-1DEBUG\s0 on Alpha/VMS systems. +.IP "\fB\-g\fR\fIlevel\fR" 4 +.IX Item "-glevel" +.PD 0 +.IP "\fB\-ggdb\fR\fIlevel\fR" 4 +.IX Item "-ggdblevel" +.IP "\fB\-gstabs\fR\fIlevel\fR" 4 +.IX Item "-gstabslevel" +.IP "\fB\-gxcoff\fR\fIlevel\fR" 4 +.IX Item "-gxcofflevel" +.IP "\fB\-gvms\fR\fIlevel\fR" 4 +.IX Item "-gvmslevel" +.PD +Request debugging information and also use \fIlevel\fR to specify how +much information. The default level is 2. +.Sp +Level 0 produces no debug information at all. Thus, \fB\-g0\fR negates +\&\fB\-g\fR. +.Sp +Level 1 produces minimal information, enough for making backtraces in +parts of the program that you don't plan to debug. This includes +descriptions of functions and external variables, and line number +tables, but no information about local variables. +.Sp +Level 3 includes extra information, such as all the macro definitions +present in the program. Some debuggers support macro expansion when +you use \fB\-g3\fR. +.Sp +If you use multiple \fB\-g\fR options, with or without level numbers, +the last such option is the one that is effective. +.Sp +\&\fB\-gdwarf\fR does not accept a concatenated debug level, to avoid +confusion with \fB\-gdwarf\-\fR\fIlevel\fR. +Instead use an additional \fB\-g\fR\fIlevel\fR option to change the +debug level for \s-1DWARF.\s0 +.IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 +.IX Item "-feliminate-unused-debug-symbols" +Produce debugging information in stabs format (if that is supported), +for only symbols that are actually used. +.IP "\fB\-femit\-class\-debug\-always\fR" 4 +.IX Item "-femit-class-debug-always" +Instead of emitting debugging information for a \*(C+ class in only one +object file, emit it in all object files using the class. This option +should be used only with debuggers that are unable to handle the way \s-1GCC\s0 +normally emits debugging information for classes because using this +option increases the size of debugging information by as much as a +factor of two. +.IP "\fB\-fno\-merge\-debug\-strings\fR" 4 +.IX Item "-fno-merge-debug-strings" +Direct the linker to not merge together strings in the debugging +information that are identical in different object files. Merging is +not supported by all assemblers or linkers. Merging decreases the size +of the debug information in the output file at the cost of increasing +link processing time. Merging is enabled by default. +.IP "\fB\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fdebug-prefix-map=old=new" +When compiling files residing in directory \fI\fIold\fI\fR, record +debugging information describing them as if the files resided in +directory \fI\fInew\fI\fR instead. This can be used to replace a +build-time path with an install-time path in the debug info. It can +also be used to change an absolute path to a relative path by using +\&\fI.\fR for \fInew\fR. This can give more reproducible builds, which +are location independent, but may require an extra command to tell \s-1GDB\s0 +where to find the source files. See also \fB\-ffile\-prefix\-map\fR. +.IP "\fB\-fvar\-tracking\fR" 4 +.IX Item "-fvar-tracking" +Run variable tracking pass. It computes where variables are stored at each +position in code. Better debugging information is then generated +(if the debugging information format supports this information). +.Sp +It is enabled by default when compiling with optimization (\fB\-Os\fR, +\&\fB\-O\fR, \fB\-O2\fR, ...), debugging information (\fB\-g\fR) and +the debug info format supports it. +.IP "\fB\-fvar\-tracking\-assignments\fR" 4 +.IX Item "-fvar-tracking-assignments" +Annotate assignments to user variables early in the compilation and +attempt to carry the annotations over throughout the compilation all the +way to the end, in an attempt to improve debug information while +optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it. +.Sp +It can be enabled even if var-tracking is disabled, in which case +annotations are created and maintained, but discarded at the end. +By default, this flag is enabled together with \fB\-fvar\-tracking\fR, +except when selective scheduling is enabled. +.IP "\fB\-gsplit\-dwarf\fR" 4 +.IX Item "-gsplit-dwarf" +Separate as much \s-1DWARF\s0 debugging information as possible into a +separate output file with the extension \fI.dwo\fR. This option allows +the build system to avoid linking files with debug information. To +be useful, this option requires a debugger capable of reading \fI.dwo\fR +files. +.IP "\fB\-gdescribe\-dies\fR" 4 +.IX Item "-gdescribe-dies" +Add description attributes to some \s-1DWARF\s0 DIEs that have no name attribute, +such as artificial variables, external references and call site +parameter DIEs. +.IP "\fB\-gpubnames\fR" 4 +.IX Item "-gpubnames" +Generate \s-1DWARF\s0 \f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections. +.IP "\fB\-ggnu\-pubnames\fR" 4 +.IX Item "-ggnu-pubnames" +Generate \f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections in a format +suitable for conversion into a \s-1GDB\s0 index. This option is only useful +with a linker that can produce \s-1GDB\s0 index version 7. +.IP "\fB\-fdebug\-types\-section\fR" 4 +.IX Item "-fdebug-types-section" +When using \s-1DWARF\s0 Version 4 or higher, type DIEs can be put into +their own \f(CW\*(C`.debug_types\*(C'\fR section instead of making them part of the +\&\f(CW\*(C`.debug_info\*(C'\fR section. It is more efficient to put them in a separate +comdat section since the linker can then remove duplicates. +But not all \s-1DWARF\s0 consumers support \f(CW\*(C`.debug_types\*(C'\fR sections yet +and on some objects \f(CW\*(C`.debug_types\*(C'\fR produces larger instead of smaller +debugging information. +.IP "\fB\-grecord\-gcc\-switches\fR" 4 +.IX Item "-grecord-gcc-switches" +.PD 0 +.IP "\fB\-gno\-record\-gcc\-switches\fR" 4 +.IX Item "-gno-record-gcc-switches" +.PD +This switch causes the command-line options used to invoke the +compiler that may affect code generation to be appended to the +DW_AT_producer attribute in \s-1DWARF\s0 debugging information. The options +are concatenated with spaces separating them from each other and from +the compiler version. +It is enabled by default. +See also \fB\-frecord\-gcc\-switches\fR for another +way of storing compiler options into the object file. +.IP "\fB\-gstrict\-dwarf\fR" 4 +.IX Item "-gstrict-dwarf" +Disallow using extensions of later \s-1DWARF\s0 standard version than selected +with \fB\-gdwarf\-\fR\fIversion\fR. On most targets using non-conflicting +\&\s-1DWARF\s0 extensions from later standard versions is allowed. +.IP "\fB\-gno\-strict\-dwarf\fR" 4 +.IX Item "-gno-strict-dwarf" +Allow using extensions of later \s-1DWARF\s0 standard version than selected with +\&\fB\-gdwarf\-\fR\fIversion\fR. +.IP "\fB\-gas\-loc\-support\fR" 4 +.IX Item "-gas-loc-support" +Inform the compiler that the assembler supports \f(CW\*(C`.loc\*(C'\fR directives. +It may then use them for the assembler to generate \s-1DWARF2+\s0 line number +tables. +.Sp +This is generally desirable, because assembler-generated line-number +tables are a lot more compact than those the compiler can generate +itself. +.Sp +This option will be enabled by default if, at \s-1GCC\s0 configure time, the +assembler was found to support such directives. +.IP "\fB\-gno\-as\-loc\-support\fR" 4 +.IX Item "-gno-as-loc-support" +Force \s-1GCC\s0 to generate \s-1DWARF2+\s0 line number tables internally, if \s-1DWARF2+\s0 +line number tables are to be generated. +.IP "\fBgas-locview-support\fR" 4 +.IX Item "gas-locview-support" +Inform the compiler that the assembler supports \f(CW\*(C`view\*(C'\fR assignment +and reset assertion checking in \f(CW\*(C`.loc\*(C'\fR directives. +.Sp +This option will be enabled by default if, at \s-1GCC\s0 configure time, the +assembler was found to support them. +.IP "\fBgno-as-locview-support\fR" 4 +.IX Item "gno-as-locview-support" +Force \s-1GCC\s0 to assign view numbers internally, if +\&\fB\-gvariable\-location\-views\fR are explicitly requested. +.IP "\fB\-gcolumn\-info\fR" 4 +.IX Item "-gcolumn-info" +.PD 0 +.IP "\fB\-gno\-column\-info\fR" 4 +.IX Item "-gno-column-info" +.PD +Emit location column information into \s-1DWARF\s0 debugging information, rather +than just file and line. +This option is enabled by default. +.IP "\fB\-gstatement\-frontiers\fR" 4 +.IX Item "-gstatement-frontiers" +.PD 0 +.IP "\fB\-gno\-statement\-frontiers\fR" 4 +.IX Item "-gno-statement-frontiers" +.PD +This option causes \s-1GCC\s0 to create markers in the internal representation +at the beginning of statements, and to keep them roughly in place +throughout compilation, using them to guide the output of \f(CW\*(C`is_stmt\*(C'\fR +markers in the line number table. This is enabled by default when +compiling with optimization (\fB\-Os\fR, \fB\-O\fR, \fB\-O2\fR, +\&...), and outputting \s-1DWARF 2\s0 debug information at the normal level. +.IP "\fB\-gvariable\-location\-views\fR" 4 +.IX Item "-gvariable-location-views" +.PD 0 +.IP "\fB\-gvariable\-location\-views=incompat5\fR" 4 +.IX Item "-gvariable-location-views=incompat5" +.IP "\fB\-gno\-variable\-location\-views\fR" 4 +.IX Item "-gno-variable-location-views" +.PD +Augment variable location lists with progressive view numbers implied +from the line number table. This enables debug information consumers to +inspect state at certain points of the program, even if no instructions +associated with the corresponding source locations are present at that +point. If the assembler lacks support for view numbers in line number +tables, this will cause the compiler to emit the line number table, +which generally makes them somewhat less compact. The augmented line +number tables and location lists are fully backward-compatible, so they +can be consumed by debug information consumers that are not aware of +these augmentations, but they won't derive any benefit from them either. +.Sp +This is enabled by default when outputting \s-1DWARF 2\s0 debug information at +the normal level, as long as there is assembler support, +\&\fB\-fvar\-tracking\-assignments\fR is enabled and +\&\fB\-gstrict\-dwarf\fR is not. When assembler support is not +available, this may still be enabled, but it will force \s-1GCC\s0 to output +internal line number tables, and if +\&\fB\-ginternal\-reset\-location\-views\fR is not enabled, that will most +certainly lead to silently mismatching location views. +.Sp +There is a proposed representation for view numbers that is not backward +compatible with the location list format introduced in \s-1DWARF 5,\s0 that can +be enabled with \fB\-gvariable\-location\-views=incompat5\fR. This +option may be removed in the future, is only provided as a reference +implementation of the proposed representation. Debug information +consumers are not expected to support this extended format, and they +would be rendered unable to decode location lists using it. +.IP "\fB\-ginternal\-reset\-location\-views\fR" 4 +.IX Item "-ginternal-reset-location-views" +.PD 0 +.IP "\fB\-gno\-internal\-reset\-location\-views\fR" 4 +.IX Item "-gno-internal-reset-location-views" +.PD +Attempt to determine location views that can be omitted from location +view lists. This requires the compiler to have very accurate insn +length estimates, which isn't always the case, and it may cause +incorrect view lists to be generated silently when using an assembler +that does not support location view lists. The \s-1GNU\s0 assembler will flag +any such error as a \f(CW\*(C`view number mismatch\*(C'\fR. This is only enabled +on ports that define a reliable estimation function. +.IP "\fB\-ginline\-points\fR" 4 +.IX Item "-ginline-points" +.PD 0 +.IP "\fB\-gno\-inline\-points\fR" 4 +.IX Item "-gno-inline-points" +.PD +Generate extended debug information for inlined functions. Location +view tracking markers are inserted at inlined entry points, so that +address and view numbers can be computed and output in debug +information. This can be enabled independently of location views, in +which case the view numbers won't be output, but it can only be enabled +along with statement frontiers, and it is only enabled by default if +location views are enabled. +.IP "\fB\-gz\fR[\fB=\fR\fItype\fR]" 4 +.IX Item "-gz[=type]" +Produce compressed debug sections in \s-1DWARF\s0 format, if that is supported. +If \fItype\fR is not given, the default type depends on the capabilities +of the assembler and linker used. \fItype\fR may be one of +\&\fBnone\fR (don't compress debug sections), \fBzlib\fR (use zlib +compression in \s-1ELF\s0 gABI format), or \fBzlib-gnu\fR (use zlib +compression in traditional \s-1GNU\s0 format). If the linker doesn't support +writing compressed debug sections, the option is rejected. Otherwise, +if the assembler does not support them, \fB\-gz\fR is silently ignored +when producing object files. +.IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4 +.IX Item "-femit-struct-debug-baseonly" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the struct is defined. +.Sp +This option substantially reduces the size of debugging information, +but at significant potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-reduced\fR for a less aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 debug output. +.IP "\fB\-femit\-struct\-debug\-reduced\fR" 4 +.IX Item "-femit-struct-debug-reduced" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the type is defined, +unless the struct is a template or defined in a system header. +.Sp +This option significantly reduces the size of debugging information, +with some potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-baseonly\fR for a more aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 debug output. +.IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4 +.IX Item "-femit-struct-debug-detailed[=spec-list]" +Specify the struct-like types +for which the compiler generates debug information. +The intent is to reduce duplicate struct debug information +between different object files within the same program. +.Sp +This option is a detailed version of +\&\fB\-femit\-struct\-debug\-reduced\fR and \fB\-femit\-struct\-debug\-baseonly\fR, +which serves for most needs. +.Sp +A specification has the syntax[\fBdir:\fR|\fBind:\fR][\fBord:\fR|\fBgen:\fR](\fBany\fR|\fBsys\fR|\fBbase\fR|\fBnone\fR) +.Sp +The optional first word limits the specification to +structs that are used directly (\fBdir:\fR) or used indirectly (\fBind:\fR). +A struct type is used directly when it is the type of a variable, member. +Indirect uses arise through pointers to structs. +That is, when use of an incomplete struct is valid, the use is indirect. +An example is +\&\fBstruct one direct; struct two * indirect;\fR. +.Sp +The optional second word limits the specification to +ordinary structs (\fBord:\fR) or generic structs (\fBgen:\fR). +Generic structs are a bit complicated to explain. +For \*(C+, these are non-explicit specializations of template classes, +or non-template classes within the above. +Other programming languages have generics, +but \fB\-femit\-struct\-debug\-detailed\fR does not yet implement them. +.Sp +The third word specifies the source files for those +structs for which the compiler should emit debug information. +The values \fBnone\fR and \fBany\fR have the normal meaning. +The value \fBbase\fR means that +the base of name of the file in which the type declaration appears +must match the base of the name of the main compilation file. +In practice, this means that when compiling \fIfoo.c\fR, debug information +is generated for types declared in that file and \fIfoo.h\fR, +but not other header files. +The value \fBsys\fR means those types satisfying \fBbase\fR +or declared in system or compiler headers. +.Sp +You may need to experiment to determine the best settings for your application. +.Sp +The default is \fB\-femit\-struct\-debug\-detailed=all\fR. +.Sp +This option works only with \s-1DWARF\s0 debug output. +.IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 +.IX Item "-fno-dwarf2-cfi-asm" +Emit \s-1DWARF\s0 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section +instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. +.IP "\fB\-fno\-eliminate\-unused\-debug\-types\fR" 4 +.IX Item "-fno-eliminate-unused-debug-types" +Normally, when producing \s-1DWARF\s0 output, \s-1GCC\s0 avoids producing debug symbol +output for types that are nowhere used in the source file being compiled. +Sometimes it is useful to have \s-1GCC\s0 emit debugging +information for all types declared in a compilation +unit, regardless of whether or not they are actually used +in that compilation unit, for example +if, in the debugger, you want to cast a value to a type that is +not actually used in your program (but is declared). More often, +however, this results in a significant amount of wasted space. +.SS "Options That Control Optimization" +.IX Subsection "Options That Control Optimization" +These options control various sorts of optimizations. +.PP +Without any optimization option, the compiler's goal is to reduce the +cost of compilation and to make debugging produce the expected +results. Statements are independent: if you stop the program with a +breakpoint between statements, you can then assign a new value to any +variable or change the program counter to any other statement in the +function and get exactly the results you expect from the source +code. +.PP +Turning on optimization flags makes the compiler attempt to improve +the performance and/or code size at the expense of compilation time +and possibly the ability to debug the program. +.PP +The compiler performs optimization based on the knowledge it has of the +program. Compiling multiple files at once to a single output file mode allows +the compiler to use information gained from all of the files when compiling +each of them. +.PP +Not all optimizations are controlled directly by a flag. Only +optimizations that have a flag are listed in this section. +.PP +Most optimizations are completely disabled at \fB\-O0\fR or if an +\&\fB\-O\fR level is not set on the command line, even if individual +optimization flags are specified. Similarly, \fB\-Og\fR suppresses +many optimization passes. +.PP +Depending on the target and how \s-1GCC\s0 was configured, a slightly different +set of optimizations may be enabled at each \fB\-O\fR level than +those listed here. You can invoke \s-1GCC\s0 with \fB\-Q \-\-help=optimizers\fR +to find out the exact set of optimizations that are enabled at each level. +.IP "\fB\-O\fR" 4 +.IX Item "-O" +.PD 0 +.IP "\fB\-O1\fR" 4 +.IX Item "-O1" +.PD +Optimize. Optimizing compilation takes somewhat more time, and a lot +more memory for a large function. +.Sp +With \fB\-O\fR, the compiler tries to reduce code size and execution +time, without performing any optimizations that take a great deal of +compilation time. +.Sp +\&\fB\-O\fR turns on the following optimization flags: +.Sp +\&\fB\-fauto\-inc\-dec +\&\-fbranch\-count\-reg +\&\-fcombine\-stack\-adjustments +\&\-fcompare\-elim +\&\-fcprop\-registers +\&\-fdce +\&\-fdefer\-pop +\&\-fdelayed\-branch +\&\-fdse +\&\-fforward\-propagate +\&\-fguess\-branch\-probability +\&\-fif\-conversion +\&\-fif\-conversion2 +\&\-finline\-functions\-called\-once +\&\-fipa\-profile +\&\-fipa\-pure\-const +\&\-fipa\-reference +\&\-fipa\-reference\-addressable +\&\-fmerge\-constants +\&\-fmove\-loop\-invariants +\&\-fomit\-frame\-pointer +\&\-freorder\-blocks +\&\-fshrink\-wrap +\&\-fshrink\-wrap\-separate +\&\-fsplit\-wide\-types +\&\-fssa\-backprop +\&\-fssa\-phiopt +\&\-ftree\-bit\-ccp +\&\-ftree\-ccp +\&\-ftree\-ch +\&\-ftree\-coalesce\-vars +\&\-ftree\-copy\-prop +\&\-ftree\-dce +\&\-ftree\-dominator\-opts +\&\-ftree\-dse +\&\-ftree\-forwprop +\&\-ftree\-fre +\&\-ftree\-phiprop +\&\-ftree\-pta +\&\-ftree\-scev\-cprop +\&\-ftree\-sink +\&\-ftree\-slsr +\&\-ftree\-sra +\&\-ftree\-ter +\&\-funit\-at\-a\-time\fR +.IP "\fB\-O2\fR" 4 +.IX Item "-O2" +Optimize even more. \s-1GCC\s0 performs nearly all supported optimizations +that do not involve a space-speed tradeoff. +As compared to \fB\-O\fR, this option increases both compilation time +and the performance of the generated code. +.Sp +\&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR. It +also turns on the following optimization flags: +.Sp +\&\fB\-falign\-functions \-falign\-jumps +\&\-falign\-labels \-falign\-loops +\&\-fcaller\-saves +\&\-fcode\-hoisting +\&\-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks +\&\-fdelete\-null\-pointer\-checks +\&\-fdevirtualize \-fdevirtualize\-speculatively +\&\-fexpensive\-optimizations +\&\-fgcse \-fgcse\-lm +\&\-fhoist\-adjacent\-loads +\&\-finline\-small\-functions +\&\-findirect\-inlining +\&\-fipa\-bit\-cp \-fipa\-cp \-fipa\-icf +\&\-fipa\-ra \-fipa\-sra \-fipa\-vrp +\&\-fisolate\-erroneous\-paths\-dereference +\&\-flra\-remat +\&\-foptimize\-sibling\-calls +\&\-foptimize\-strlen +\&\-fpartial\-inlining +\&\-fpeephole2 +\&\-freorder\-blocks\-algorithm=stc +\&\-freorder\-blocks\-and\-partition \-freorder\-functions +\&\-frerun\-cse\-after\-loop +\&\-fschedule\-insns \-fschedule\-insns2 +\&\-fsched\-interblock \-fsched\-spec +\&\-fstore\-merging +\&\-fstrict\-aliasing +\&\-fthread\-jumps +\&\-ftree\-builtin\-call\-dce +\&\-ftree\-pre +\&\-ftree\-switch\-conversion \-ftree\-tail\-merge +\&\-ftree\-vrp\fR +.Sp +Please note the warning under \fB\-fgcse\fR about +invoking \fB\-O2\fR on programs that use computed gotos. +.IP "\fB\-O3\fR" 4 +.IX Item "-O3" +Optimize yet more. \fB\-O3\fR turns on all optimizations specified +by \fB\-O2\fR and also turns on the following optimization flags: +.Sp +\&\fB\-fgcse\-after\-reload +\&\-finline\-functions +\&\-fipa\-cp\-clone +\&\-floop\-interchange +\&\-floop\-unroll\-and\-jam +\&\-fpeel\-loops +\&\-fpredictive\-commoning +\&\-fsplit\-paths +\&\-ftree\-loop\-distribute\-patterns +\&\-ftree\-loop\-distribution +\&\-ftree\-loop\-vectorize +\&\-ftree\-partial\-pre +\&\-ftree\-slp\-vectorize +\&\-funswitch\-loops +\&\-fvect\-cost\-model +\&\-fversion\-loops\-for\-strides\fR +.IP "\fB\-O0\fR" 4 +.IX Item "-O0" +Reduce compilation time and make debugging produce the expected +results. This is the default. +.IP "\fB\-Os\fR" 4 +.IX Item "-Os" +Optimize for size. \fB\-Os\fR enables all \fB\-O2\fR optimizations +except those that often increase code size: +.Sp +\&\fB\-falign\-functions \-falign\-jumps +\&\-falign\-labels \-falign\-loops +\&\-fprefetch\-loop\-arrays \-freorder\-blocks\-algorithm=stc\fR +.Sp +It also enables \fB\-finline\-functions\fR, causes the compiler to tune for +code size rather than execution speed, and performs further optimizations +designed to reduce code size. +.IP "\fB\-Ofast\fR" 4 +.IX Item "-Ofast" +Disregard strict standards compliance. \fB\-Ofast\fR enables all +\&\fB\-O3\fR optimizations. It also enables optimizations that are not +valid for all standard-compliant programs. +It turns on \fB\-ffast\-math\fR and the Fortran-specific +\&\fB\-fstack\-arrays\fR, unless \fB\-fmax\-stack\-var\-size\fR is +specified, and \fB\-fno\-protect\-parens\fR. +.IP "\fB\-Og\fR" 4 +.IX Item "-Og" +Optimize debugging experience. \fB\-Og\fR should be the optimization +level of choice for the standard edit-compile-debug cycle, offering +a reasonable level of optimization while maintaining fast compilation +and a good debugging experience. It is a better choice than \fB\-O0\fR +for producing debuggable code because some compiler passes +that collect debug information are disabled at \fB\-O0\fR. +.Sp +Like \fB\-O0\fR, \fB\-Og\fR completely disables a number of +optimization passes so that individual options controlling them have +no effect. Otherwise \fB\-Og\fR enables all \fB\-O1\fR +optimization flags except for those that may interfere with debugging: +.Sp +\&\fB\-fbranch\-count\-reg \-fdelayed\-branch +\&\-fif\-conversion \-fif\-conversion2 +\&\-finline\-functions\-called\-once +\&\-fmove\-loop\-invariants \-fssa\-phiopt +\&\-ftree\-bit\-ccp \-ftree\-pta \-ftree\-sra\fR +.PP +If you use multiple \fB\-O\fR options, with or without level numbers, +the last such option is the one that is effective. +.PP +Options of the form \fB\-f\fR\fIflag\fR specify machine-independent +flags. Most flags have both positive and negative forms; the negative +form of \fB\-ffoo\fR is \fB\-fno\-foo\fR. In the table +below, only one of the forms is listed\-\-\-the one you typically +use. You can figure out the other form by either removing \fBno\-\fR +or adding it. +.PP +The following options control specific optimizations. They are either +activated by \fB\-O\fR options or are related to ones that are. You +can use the following flags in the rare cases when \*(L"fine-tuning\*(R" of +optimizations to be performed is desired. +.IP "\fB\-fno\-defer\-pop\fR" 4 +.IX Item "-fno-defer-pop" +For machines that must pop arguments after a function call, always pop +the arguments as soon as each function returns. +At levels \fB\-O1\fR and higher, \fB\-fdefer\-pop\fR is the default; +this allows the compiler to let arguments accumulate on the stack for several +function calls and pop them all at once. +.IP "\fB\-fforward\-propagate\fR" 4 +.IX Item "-fforward-propagate" +Perform a forward propagation pass on \s-1RTL.\s0 The pass tries to combine two +instructions and checks if the result can be simplified. If loop unrolling +is active, two passes are performed and the second is scheduled after +loop unrolling. +.Sp +This option is enabled by default at optimization levels \fB\-O\fR, +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-ffp\-contract=\fR\fIstyle\fR" 4 +.IX Item "-ffp-contract=style" +\&\fB\-ffp\-contract=off\fR disables floating-point expression contraction. +\&\fB\-ffp\-contract=fast\fR enables floating-point expression contraction +such as forming of fused multiply-add operations if the target has +native support for them. +\&\fB\-ffp\-contract=on\fR enables floating-point expression contraction +if allowed by the language standard. This is currently not implemented +and treated equal to \fB\-ffp\-contract=off\fR. +.Sp +The default is \fB\-ffp\-contract=fast\fR. +.IP "\fB\-fomit\-frame\-pointer\fR" 4 +.IX Item "-fomit-frame-pointer" +Omit the frame pointer in functions that don't need one. This avoids the +instructions to save, set up and restore the frame pointer; on many targets +it also makes an extra register available. +.Sp +On some targets this flag has no effect because the standard calling sequence +always uses a frame pointer, so it cannot be omitted. +.Sp +Note that \fB\-fno\-omit\-frame\-pointer\fR doesn't guarantee the frame pointer +is used in all functions. Several targets always omit the frame pointer in +leaf functions. +.Sp +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-foptimize\-sibling\-calls\fR" 4 +.IX Item "-foptimize-sibling-calls" +Optimize sibling and tail recursive calls. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-foptimize\-strlen\fR" 4 +.IX Item "-foptimize-strlen" +Optimize various standard C string functions (e.g. \f(CW\*(C`strlen\*(C'\fR, +\&\f(CW\*(C`strchr\*(C'\fR or \f(CW\*(C`strcpy\*(C'\fR) and +their \f(CW\*(C`_FORTIFY_SOURCE\*(C'\fR counterparts into faster alternatives. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fno\-inline\fR" 4 +.IX Item "-fno-inline" +Do not expand any functions inline apart from those marked with +the \f(CW\*(C`always_inline\*(C'\fR attribute. This is the default when not +optimizing. +.Sp +Single functions can be exempted from inlining by marking them +with the \f(CW\*(C`noinline\*(C'\fR attribute. +.IP "\fB\-finline\-small\-functions\fR" 4 +.IX Item "-finline-small-functions" +Integrate functions into their callers when their body is smaller than expected +function call code (so overall size of program gets smaller). The compiler +heuristically decides which functions are simple enough to be worth integrating +in this way. This inlining applies to all functions, even those not declared +inline. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-findirect\-inlining\fR" 4 +.IX Item "-findirect-inlining" +Inline also indirect calls that are discovered to be known at compile +time thanks to previous inlining. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-finline\-functions\fR" 4 +.IX Item "-finline-functions" +Consider all functions for inlining, even if they are not declared inline. +The compiler heuristically decides which functions are worth integrating +in this way. +.Sp +If all calls to a given function are integrated, and the function is +declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as +assembler code in its own right. +.Sp +Enabled at levels \fB\-O3\fR, \fB\-Os\fR. Also enabled +by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-finline\-functions\-called\-once\fR" 4 +.IX Item "-finline-functions-called-once" +Consider all \f(CW\*(C`static\*(C'\fR functions called once for inlining into their +caller even if they are not marked \f(CW\*(C`inline\*(C'\fR. If a call to a given +function is integrated, then the function is not output as assembler code +in its own right. +.Sp +Enabled at levels \fB\-O1\fR, \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR, +but not \fB\-Og\fR. +.IP "\fB\-fearly\-inlining\fR" 4 +.IX Item "-fearly-inlining" +Inline functions marked by \f(CW\*(C`always_inline\*(C'\fR and functions whose body seems +smaller than the function call overhead early before doing +\&\fB\-fprofile\-generate\fR instrumentation and real inlining pass. Doing so +makes profiling significantly cheaper and usually inlining faster on programs +having large chains of nested wrapper functions. +.Sp +Enabled by default. +.IP "\fB\-fipa\-sra\fR" 4 +.IX Item "-fipa-sra" +Perform interprocedural scalar replacement of aggregates, removal of +unused parameters and replacement of parameters passed by reference +by parameters passed by value. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. +.IP "\fB\-finline\-limit=\fR\fIn\fR" 4 +.IX Item "-finline-limit=n" +By default, \s-1GCC\s0 limits the size of functions that can be inlined. This flag +allows coarse control of this limit. \fIn\fR is the size of functions that +can be inlined in number of pseudo instructions. +.Sp +Inlining is actually controlled by a number of parameters, which may be +specified individually by using \fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR. +The \fB\-finline\-limit=\fR\fIn\fR option sets some of these parameters +as follows: +.RS 4 +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +is set to \fIn\fR/2. +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +is set to \fIn\fR/2. +.RE +.RS 4 +.Sp +See below for a documentation of the individual +parameters controlling inlining and for the defaults of these parameters. +.Sp +\&\fINote:\fR there may be no value to \fB\-finline\-limit\fR that results +in default behavior. +.Sp +\&\fINote:\fR pseudo instruction represents, in this particular context, an +abstract measurement of function's size. In no way does it represent a count +of assembly instructions and as such its exact meaning might change from one +release to an another. +.RE +.IP "\fB\-fno\-keep\-inline\-dllexport\fR" 4 +.IX Item "-fno-keep-inline-dllexport" +This is a more fine-grained version of \fB\-fkeep\-inline\-functions\fR, +which applies only to functions that are declared using the \f(CW\*(C`dllexport\*(C'\fR +attribute or declspec. +.IP "\fB\-fkeep\-inline\-functions\fR" 4 +.IX Item "-fkeep-inline-functions" +In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR +into the object file, even if the function has been inlined into all +of its callers. This switch does not affect functions using the +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU C90.\s0 In \*(C+, emit any and all +inline functions into the object file. +.IP "\fB\-fkeep\-static\-functions\fR" 4 +.IX Item "-fkeep-static-functions" +Emit \f(CW\*(C`static\*(C'\fR functions into the object file, even if the function +is never used. +.IP "\fB\-fkeep\-static\-consts\fR" 4 +.IX Item "-fkeep-static-consts" +Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned +on, even if the variables aren't referenced. +.Sp +\&\s-1GCC\s0 enables this option by default. If you want to force the compiler to +check if a variable is referenced, regardless of whether or not +optimization is turned on, use the \fB\-fno\-keep\-static\-consts\fR option. +.IP "\fB\-fmerge\-constants\fR" 4 +.IX Item "-fmerge-constants" +Attempt to merge identical constants (string constants and floating-point +constants) across compilation units. +.Sp +This option is the default for optimized compilation if the assembler and +linker support it. Use \fB\-fno\-merge\-constants\fR to inhibit this +behavior. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fmerge\-all\-constants\fR" 4 +.IX Item "-fmerge-all-constants" +Attempt to merge identical constants and identical variables. +.Sp +This option implies \fB\-fmerge\-constants\fR. In addition to +\&\fB\-fmerge\-constants\fR this considers e.g. even constant initialized +arrays or initialized constant variables with integral or floating-point +types. Languages like C or \*(C+ require each variable, including multiple +instances of the same variable in recursive calls, to have distinct locations, +so using this option results in non-conforming +behavior. +.IP "\fB\-fmodulo\-sched\fR" 4 +.IX Item "-fmodulo-sched" +Perform swing modulo scheduling immediately before the first scheduling +pass. This pass looks at innermost loops and reorders their +instructions by overlapping different iterations. +.IP "\fB\-fmodulo\-sched\-allow\-regmoves\fR" 4 +.IX Item "-fmodulo-sched-allow-regmoves" +Perform more aggressive SMS-based modulo scheduling with register moves +allowed. By setting this flag certain anti-dependences edges are +deleted, which triggers the generation of reg-moves based on the +life-range analysis. This option is effective only with +\&\fB\-fmodulo\-sched\fR enabled. +.IP "\fB\-fno\-branch\-count\-reg\fR" 4 +.IX Item "-fno-branch-count-reg" +Disable the optimization pass that scans for opportunities to use +\&\*(L"decrement and branch\*(R" instructions on a count register instead of +instruction sequences that decrement a register, compare it against zero, and +then branch based upon the result. This option is only meaningful on +architectures that support such instructions, which include x86, PowerPC, +\&\s-1IA\-64\s0 and S/390. Note that the \fB\-fno\-branch\-count\-reg\fR option +doesn't remove the decrement and branch instructions from the generated +instruction stream introduced by other optimization passes. +.Sp +The default is \fB\-fbranch\-count\-reg\fR at \fB\-O1\fR and higher, +except for \fB\-Og\fR. +.IP "\fB\-fno\-function\-cse\fR" 4 +.IX Item "-fno-function-cse" +Do not put function addresses in registers; make each instruction that +calls a constant function contain the function's address explicitly. +.Sp +This option results in less efficient code, but some strange hacks +that alter the assembler output may be confused by the optimizations +performed when this option is not used. +.Sp +The default is \fB\-ffunction\-cse\fR +.IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 +.IX Item "-fno-zero-initialized-in-bss" +If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that +are initialized to zero into \s-1BSS.\s0 This can save space in the resulting +code. +.Sp +This option turns off this behavior because some programs explicitly +rely on variables going to the data section\-\-\-e.g., so that the +resulting executable can find the beginning of that section and/or make +assumptions based on that. +.Sp +The default is \fB\-fzero\-initialized\-in\-bss\fR. +.IP "\fB\-fthread\-jumps\fR" 4 +.IX Item "-fthread-jumps" +Perform optimizations that check to see if a jump branches to a +location where another comparison subsumed by the first is found. If +so, the first branch is redirected to either the destination of the +second branch or a point immediately following it, depending on whether +the condition is known to be true or false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fsplit\-wide\-types\fR" 4 +.IX Item "-fsplit-wide-types" +When using a type that occupies multiple registers, such as \f(CW\*(C`long +long\*(C'\fR on a 32\-bit system, split the registers apart and allocate them +independently. This normally generates better code for those types, +but may make debugging more difficult. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, +\&\fB\-Os\fR. +.IP "\fB\-fcse\-follow\-jumps\fR" 4 +.IX Item "-fcse-follow-jumps" +In common subexpression elimination (\s-1CSE\s0), scan through jump instructions +when the target of the jump is not reached by any other path. For +example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an +\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 follows the jump when the condition +tested is false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcse\-skip\-blocks\fR" 4 +.IX Item "-fcse-skip-blocks" +This is similar to \fB\-fcse\-follow\-jumps\fR, but causes \s-1CSE\s0 to +follow jumps that conditionally skip over blocks. When \s-1CSE\s0 +encounters a simple \f(CW\*(C`if\*(C'\fR statement with no else clause, +\&\fB\-fcse\-skip\-blocks\fR causes \s-1CSE\s0 to follow the jump around the +body of the \f(CW\*(C`if\*(C'\fR. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-frerun\-cse\-after\-loop\fR" 4 +.IX Item "-frerun-cse-after-loop" +Re-run common subexpression elimination after loop optimizations are +performed. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\fR" 4 +.IX Item "-fgcse" +Perform a global common subexpression elimination pass. +This pass also performs global constant and copy propagation. +.Sp +\&\fINote:\fR When compiling a program using computed gotos, a \s-1GCC\s0 +extension, you may get better run-time performance if you disable +the global common subexpression elimination pass by adding +\&\fB\-fno\-gcse\fR to the command line. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\-lm\fR" 4 +.IX Item "-fgcse-lm" +When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination +attempts to move loads that are only killed by stores into themselves. This +allows a loop containing a load/store sequence to be changed to a load outside +the loop, and a copy/store within the loop. +.Sp +Enabled by default when \fB\-fgcse\fR is enabled. +.IP "\fB\-fgcse\-sm\fR" 4 +.IX Item "-fgcse-sm" +When \fB\-fgcse\-sm\fR is enabled, a store motion pass is run after +global common subexpression elimination. This pass attempts to move +stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR, +loops containing a load/store sequence can be changed to a load before +the loop and a store after the loop. +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-las\fR" 4 +.IX Item "-fgcse-las" +When \fB\-fgcse\-las\fR is enabled, the global common subexpression +elimination pass eliminates redundant loads that come after stores to the +same memory location (both partial and full redundancies). +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-after\-reload\fR" 4 +.IX Item "-fgcse-after-reload" +When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination +pass is performed after reload. The purpose of this pass is to clean up +redundant spilling. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-faggressive\-loop\-optimizations\fR" 4 +.IX Item "-faggressive-loop-optimizations" +This option tells the loop optimizer to use language constraints to +derive bounds for the number of iterations of a loop. This assumes that +loop code does not invoke undefined behavior by for example causing signed +integer overflows or out-of-bound array accesses. The bounds for the +number of iterations of a loop are used to guide loop unrolling and peeling +and loop exit test optimizations. +This option is enabled by default. +.IP "\fB\-funconstrained\-commons\fR" 4 +.IX Item "-funconstrained-commons" +This option tells the compiler that variables declared in common blocks +(e.g. Fortran) may later be overridden with longer trailing arrays. This +prevents certain optimizations that depend on knowing the array bounds. +.IP "\fB\-fcrossjumping\fR" 4 +.IX Item "-fcrossjumping" +Perform cross-jumping transformation. +This transformation unifies equivalent code and saves code size. The +resulting code may or may not perform better than without cross-jumping. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fauto\-inc\-dec\fR" 4 +.IX Item "-fauto-inc-dec" +Combine increments or decrements of addresses with memory accesses. +This pass is always skipped on architectures that do not have +instructions to support this. Enabled by default at \fB\-O\fR and +higher on architectures that support this. +.IP "\fB\-fdce\fR" 4 +.IX Item "-fdce" +Perform dead code elimination (\s-1DCE\s0) on \s-1RTL.\s0 +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fdse\fR" 4 +.IX Item "-fdse" +Perform dead store elimination (\s-1DSE\s0) on \s-1RTL.\s0 +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fif\-conversion\fR" 4 +.IX Item "-fif-conversion" +Attempt to transform conditional jumps into branch-less equivalents. This +includes use of conditional moves, min, max, set flags and abs instructions, and +some tricks doable by standard arithmetics. The use of conditional execution +on chips where it is available is controlled by \fB\-fif\-conversion2\fR. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, but +not with \fB\-Og\fR. +.IP "\fB\-fif\-conversion2\fR" 4 +.IX Item "-fif-conversion2" +Use conditional execution (where available) to transform conditional jumps into +branch-less equivalents. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, but +not with \fB\-Og\fR. +.IP "\fB\-fdeclone\-ctor\-dtor\fR" 4 +.IX Item "-fdeclone-ctor-dtor" +The \*(C+ \s-1ABI\s0 requires multiple entry points for constructors and +destructors: one for a base subobject, one for a complete object, and +one for a virtual destructor that calls operator delete afterwards. +For a hierarchy with virtual bases, the base and complete variants are +clones, which means two copies of the function. With this option, the +base and complete variants are changed to be thunks that call a common +implementation. +.Sp +Enabled by \fB\-Os\fR. +.IP "\fB\-fdelete\-null\-pointer\-checks\fR" 4 +.IX Item "-fdelete-null-pointer-checks" +Assume that programs cannot safely dereference null pointers, and that +no code or data element resides at address zero. +This option enables simple constant +folding optimizations at all optimization levels. In addition, other +optimization passes in \s-1GCC\s0 use this flag to control global dataflow +analyses that eliminate useless checks for null pointers; these assume +that a memory access to address zero always results in a trap, so +that if a pointer is checked after it has already been dereferenced, +it cannot be null. +.Sp +Note however that in some environments this assumption is not true. +Use \fB\-fno\-delete\-null\-pointer\-checks\fR to disable this optimization +for programs that depend on that behavior. +.Sp +This option is enabled by default on most targets. On Nios \s-1II ELF,\s0 it +defaults to off. On \s-1AVR, CR16,\s0 and \s-1MSP430,\s0 this option is completely disabled. +.Sp +Passes that use the dataflow information +are enabled independently at different optimization levels. +.IP "\fB\-fdevirtualize\fR" 4 +.IX Item "-fdevirtualize" +Attempt to convert calls to virtual functions to direct calls. This +is done both within a procedure and interprocedurally as part of +indirect inlining (\fB\-findirect\-inlining\fR) and interprocedural constant +propagation (\fB\-fipa\-cp\fR). +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fdevirtualize\-speculatively\fR" 4 +.IX Item "-fdevirtualize-speculatively" +Attempt to convert calls to virtual functions to speculative direct calls. +Based on the analysis of the type inheritance graph, determine for a given call +the set of likely targets. If the set is small, preferably of size 1, change +the call into a conditional deciding between direct and indirect calls. The +speculative calls enable more optimizations, such as inlining. When they seem +useless after further optimization, they are converted back into original form. +.IP "\fB\-fdevirtualize\-at\-ltrans\fR" 4 +.IX Item "-fdevirtualize-at-ltrans" +Stream extra information needed for aggressive devirtualization when running +the link-time optimizer in local transformation mode. +This option enables more devirtualization but +significantly increases the size of streamed data. For this reason it is +disabled by default. +.IP "\fB\-fexpensive\-optimizations\fR" 4 +.IX Item "-fexpensive-optimizations" +Perform a number of minor optimizations that are relatively expensive. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-free\fR" 4 +.IX Item "-free" +Attempt to remove redundant extension instructions. This is especially +helpful for the x86\-64 architecture, which implicitly zero-extends in 64\-bit +registers after writing to their lower 32\-bit half. +.Sp +Enabled for Alpha, AArch64 and x86 at levels \fB\-O2\fR, +\&\fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-lifetime\-dse\fR" 4 +.IX Item "-fno-lifetime-dse" +In \*(C+ the value of an object is only affected by changes within its +lifetime: when the constructor begins, the object has an indeterminate +value, and any changes during the lifetime of the object are dead when +the object is destroyed. Normally dead store elimination will take +advantage of this; if your code relies on the value of the object +storage persisting beyond the lifetime of the object, you can use this +flag to disable this optimization. To preserve stores before the +constructor starts (e.g. because your operator new clears the object +storage) but still treat the object as dead after the destructor you, +can use \fB\-flifetime\-dse=1\fR. The default behavior can be +explicitly selected with \fB\-flifetime\-dse=2\fR. +\&\fB\-flifetime\-dse=0\fR is equivalent to \fB\-fno\-lifetime\-dse\fR. +.IP "\fB\-flive\-range\-shrinkage\fR" 4 +.IX Item "-flive-range-shrinkage" +Attempt to decrease register pressure through register live range +shrinkage. This is helpful for fast processors with small or moderate +size register sets. +.IP "\fB\-fira\-algorithm=\fR\fIalgorithm\fR" 4 +.IX Item "-fira-algorithm=algorithm" +Use the specified coloring algorithm for the integrated register +allocator. The \fIalgorithm\fR argument can be \fBpriority\fR, which +specifies Chow's priority coloring, or \fB\s-1CB\s0\fR, which specifies +Chaitin-Briggs coloring. Chaitin-Briggs coloring is not implemented +for all architectures, but for those targets that do support it, it is +the default because it generates better code. +.IP "\fB\-fira\-region=\fR\fIregion\fR" 4 +.IX Item "-fira-region=region" +Use specified regions for the integrated register allocator. The +\&\fIregion\fR argument should be one of the following: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Use all loops as register allocation regions. +This can give the best results for machines with a small and/or +irregular register set. +.IP "\fBmixed\fR" 4 +.IX Item "mixed" +Use all loops except for loops with small register pressure +as the regions. This value usually gives +the best results in most cases and for most architectures, +and is enabled by default when compiling with optimization for speed +(\fB\-O\fR, \fB\-O2\fR, ...). +.IP "\fBone\fR" 4 +.IX Item "one" +Use all functions as a single region. +This typically results in the smallest code size, and is enabled by default for +\&\fB\-Os\fR or \fB\-O0\fR. +.RE +.RS 4 +.RE +.IP "\fB\-fira\-hoist\-pressure\fR" 4 +.IX Item "-fira-hoist-pressure" +Use \s-1IRA\s0 to evaluate register pressure in the code hoisting pass for +decisions to hoist expressions. This option usually results in smaller +code, but it can slow the compiler down. +.Sp +This option is enabled at level \fB\-Os\fR for all targets. +.IP "\fB\-fira\-loop\-pressure\fR" 4 +.IX Item "-fira-loop-pressure" +Use \s-1IRA\s0 to evaluate register pressure in loops for decisions to move +loop invariants. This option usually results in generation +of faster and smaller code on machines with large register files (>= 32 +registers), but it can slow the compiler down. +.Sp +This option is enabled at level \fB\-O3\fR for some targets. +.IP "\fB\-fno\-ira\-share\-save\-slots\fR" 4 +.IX Item "-fno-ira-share-save-slots" +Disable sharing of stack slots used for saving call-used hard +registers living through a call. Each hard register gets a +separate stack slot, and as a result function stack frames are +larger. +.IP "\fB\-fno\-ira\-share\-spill\-slots\fR" 4 +.IX Item "-fno-ira-share-spill-slots" +Disable sharing of stack slots allocated for pseudo-registers. Each +pseudo-register that does not get a hard register gets a separate +stack slot, and as a result function stack frames are larger. +.IP "\fB\-flra\-remat\fR" 4 +.IX Item "-flra-remat" +Enable CFG-sensitive rematerialization in \s-1LRA.\s0 Instead of loading +values of spilled pseudos, \s-1LRA\s0 tries to rematerialize (recalculate) +values if it is profitable. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fdelayed\-branch\fR" 4 +.IX Item "-fdelayed-branch" +If supported for the target machine, attempt to reorder instructions +to exploit instruction slots available after delayed branch +instructions. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, +but not at \fB\-Og\fR. +.IP "\fB\-fschedule\-insns\fR" 4 +.IX Item "-fschedule-insns" +If supported for the target machine, attempt to reorder instructions to +eliminate execution stalls due to required data being unavailable. This +helps machines that have slow floating point or memory load instructions +by allowing other instructions to be issued until the result of the load +or floating-point instruction is required. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fschedule\-insns2\fR" 4 +.IX Item "-fschedule-insns2" +Similar to \fB\-fschedule\-insns\fR, but requests an additional pass of +instruction scheduling after register allocation has been done. This is +especially useful on machines with a relatively small number of +registers and where memory load instructions take more than one cycle. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-sched\-interblock\fR" 4 +.IX Item "-fno-sched-interblock" +Disable instruction scheduling across basic blocks, which +is normally enabled when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fno\-sched\-spec\fR" 4 +.IX Item "-fno-sched-spec" +Disable speculative motion of non-load instructions, which +is normally enabled when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-pressure\fR" 4 +.IX Item "-fsched-pressure" +Enable register pressure sensitive insn scheduling before register +allocation. This only makes sense when scheduling before register +allocation is enabled, i.e. with \fB\-fschedule\-insns\fR or at +\&\fB\-O2\fR or higher. Usage of this option can improve the +generated code and decrease its size by preventing register pressure +increase above the number of available hard registers and subsequent +spills in register allocation. +.IP "\fB\-fsched\-spec\-load\fR" 4 +.IX Item "-fsched-spec-load" +Allow speculative motion of some load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-load\-dangerous\fR" 4 +.IX Item "-fsched-spec-load-dangerous" +Allow speculative motion of more load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-stalled\-insns\fR" 4 +.IX Item "-fsched-stalled-insns" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns=n" +.PD +Define how many insns (if any) can be moved prematurely from the queue +of stalled insns into the ready list during the second scheduling pass. +\&\fB\-fno\-sched\-stalled\-insns\fR means that no insns are moved +prematurely, \fB\-fsched\-stalled\-insns=0\fR means there is no limit +on how many queued insns can be moved prematurely. +\&\fB\-fsched\-stalled\-insns\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns=1\fR. +.IP "\fB\-fsched\-stalled\-insns\-dep\fR" 4 +.IX Item "-fsched-stalled-insns-dep" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns-dep=n" +.PD +Define how many insn groups (cycles) are examined for a dependency +on a stalled insn that is a candidate for premature removal from the queue +of stalled insns. This has an effect only during the second scheduling pass, +and only if \fB\-fsched\-stalled\-insns\fR is used. +\&\fB\-fno\-sched\-stalled\-insns\-dep\fR is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=0\fR. +\&\fB\-fsched\-stalled\-insns\-dep\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=1\fR. +.IP "\fB\-fsched2\-use\-superblocks\fR" 4 +.IX Item "-fsched2-use-superblocks" +When scheduling after register allocation, use superblock scheduling. +This allows motion across basic block boundaries, +resulting in faster schedules. This option is experimental, as not all machine +descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable +results from the algorithm. +.Sp +This only makes sense when scheduling after register allocation, i.e. with +\&\fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-group\-heuristic\fR" 4 +.IX Item "-fsched-group-heuristic" +Enable the group heuristic in the scheduler. This heuristic favors +the instruction that belongs to a schedule group. This is enabled +by default when scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-critical\-path\-heuristic\fR" 4 +.IX Item "-fsched-critical-path-heuristic" +Enable the critical-path heuristic in the scheduler. This heuristic favors +instructions on the critical path. This is enabled by default when +scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-insn\-heuristic\fR" 4 +.IX Item "-fsched-spec-insn-heuristic" +Enable the speculative instruction heuristic in the scheduler. This +heuristic favors speculative instructions with greater dependency weakness. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR +or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-rank\-heuristic\fR" 4 +.IX Item "-fsched-rank-heuristic" +Enable the rank heuristic in the scheduler. This heuristic favors +the instruction belonging to a basic block with greater size or frequency. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-last\-insn\-heuristic\fR" 4 +.IX Item "-fsched-last-insn-heuristic" +Enable the last-instruction heuristic in the scheduler. This heuristic +favors the instruction that is less dependent on the last instruction +scheduled. This is enabled by default when scheduling is enabled, +i.e. with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-dep\-count\-heuristic\fR" 4 +.IX Item "-fsched-dep-count-heuristic" +Enable the dependent-count heuristic in the scheduler. This heuristic +favors the instruction that has more instructions depending on it. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4 +.IX Item "-freschedule-modulo-scheduled-loops" +Modulo scheduling is performed before traditional scheduling. If a loop +is modulo scheduled, later scheduling passes may change its schedule. +Use this option to control that behavior. +.IP "\fB\-fselective\-scheduling\fR" 4 +.IX Item "-fselective-scheduling" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the first scheduler pass. +.IP "\fB\-fselective\-scheduling2\fR" 4 +.IX Item "-fselective-scheduling2" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the second scheduler pass. +.IP "\fB\-fsel\-sched\-pipelining\fR" 4 +.IX Item "-fsel-sched-pipelining" +Enable software pipelining of innermost loops during selective scheduling. +This option has no effect unless one of \fB\-fselective\-scheduling\fR or +\&\fB\-fselective\-scheduling2\fR is turned on. +.IP "\fB\-fsel\-sched\-pipelining\-outer\-loops\fR" 4 +.IX Item "-fsel-sched-pipelining-outer-loops" +When pipelining loops during selective scheduling, also pipeline outer loops. +This option has no effect unless \fB\-fsel\-sched\-pipelining\fR is turned on. +.IP "\fB\-fsemantic\-interposition\fR" 4 +.IX Item "-fsemantic-interposition" +Some object formats, like \s-1ELF,\s0 allow interposing of symbols by the +dynamic linker. +This means that for symbols exported from the \s-1DSO,\s0 the compiler cannot perform +interprocedural propagation, inlining and other optimizations in anticipation +that the function or variable in question may change. While this feature is +useful, for example, to rewrite memory allocation functions by a debugging +implementation, it is expensive in the terms of code quality. +With \fB\-fno\-semantic\-interposition\fR the compiler assumes that +if interposition happens for functions the overwriting function will have +precisely the same semantics (and side effects). +Similarly if interposition happens +for variables, the constructor of the variable will be the same. The flag +has no effect for functions explicitly declared inline +(where it is never allowed for interposition to change semantics) +and for symbols explicitly declared weak. +.IP "\fB\-fshrink\-wrap\fR" 4 +.IX Item "-fshrink-wrap" +Emit function prologues only before parts of the function that need it, +rather than at the top of the function. This flag is enabled by default at +\&\fB\-O\fR and higher. +.IP "\fB\-fshrink\-wrap\-separate\fR" 4 +.IX Item "-fshrink-wrap-separate" +Shrink-wrap separate parts of the prologue and epilogue separately, so that +those parts are only executed when needed. +This option is on by default, but has no effect unless \fB\-fshrink\-wrap\fR +is also turned on and the target supports this. +.IP "\fB\-fcaller\-saves\fR" 4 +.IX Item "-fcaller-saves" +Enable allocation of values to registers that are clobbered by +function calls, by emitting extra instructions to save and restore the +registers around such calls. Such allocation is done only when it +seems to result in better code. +.Sp +This option is always enabled by default on certain machines, usually +those which have no call-preserved registers to use instead. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcombine\-stack\-adjustments\fR" 4 +.IX Item "-fcombine-stack-adjustments" +Tracks stack adjustments (pushes and pops) and stack memory references +and then tries to find ways to combine them. +.Sp +Enabled by default at \fB\-O1\fR and higher. +.IP "\fB\-fipa\-ra\fR" 4 +.IX Item "-fipa-ra" +Use caller save registers for allocation if those registers are not used by +any called function. In that case it is not necessary to save and restore +them around calls. This is only possible if called functions are part of +same compilation unit as current function and they are compiled before it. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, however the option +is disabled if generated code will be instrumented for profiling +(\fB\-p\fR, or \fB\-pg\fR) or if callee's register usage cannot be known +exactly (this happens on targets that do not expose prologues +and epilogues in \s-1RTL\s0). +.IP "\fB\-fconserve\-stack\fR" 4 +.IX Item "-fconserve-stack" +Attempt to minimize stack usage. The compiler attempts to use less +stack space, even if that makes the program slower. This option +implies setting the \fBlarge-stack-frame\fR parameter to 100 +and the \fBlarge-stack-frame-growth\fR parameter to 400. +.IP "\fB\-ftree\-reassoc\fR" 4 +.IX Item "-ftree-reassoc" +Perform reassociation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-fcode\-hoisting\fR" 4 +.IX Item "-fcode-hoisting" +Perform code hoisting. Code hoisting tries to move the +evaluation of expressions executed on all paths to the function exit +as early as possible. This is especially useful as a code size +optimization, but it often helps for code speed as well. +This flag is enabled by default at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-pre\fR" 4 +.IX Item "-ftree-pre" +Perform partial redundancy elimination (\s-1PRE\s0) on trees. This flag is +enabled by default at \fB\-O2\fR and \fB\-O3\fR. +.IP "\fB\-ftree\-partial\-pre\fR" 4 +.IX Item "-ftree-partial-pre" +Make partial redundancy elimination (\s-1PRE\s0) more aggressive. This flag is +enabled by default at \fB\-O3\fR. +.IP "\fB\-ftree\-forwprop\fR" 4 +.IX Item "-ftree-forwprop" +Perform forward propagation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-fre\fR" 4 +.IX Item "-ftree-fre" +Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference +between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions +that are computed on all paths leading to the redundant computation. +This analysis is faster than \s-1PRE,\s0 though it exposes fewer redundancies. +This flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-phiprop\fR" 4 +.IX Item "-ftree-phiprop" +Perform hoisting of loads from conditional pointers on trees. This +pass is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fhoist\-adjacent\-loads\fR" 4 +.IX Item "-fhoist-adjacent-loads" +Speculatively hoist loads from both branches of an if-then-else if the +loads are from adjacent locations in the same structure and the target +architecture has a conditional move instruction. This flag is enabled +by default at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-copy\-prop\fR" 4 +.IX Item "-ftree-copy-prop" +Perform copy propagation on trees. This pass eliminates unnecessary +copy operations. This flag is enabled by default at \fB\-O\fR and +higher. +.IP "\fB\-fipa\-pure\-const\fR" 4 +.IX Item "-fipa-pure-const" +Discover which functions are pure or constant. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-reference\fR" 4 +.IX Item "-fipa-reference" +Discover which static variables do not escape the +compilation unit. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-reference\-addressable\fR" 4 +.IX Item "-fipa-reference-addressable" +Discover read-only, write-only and non-addressable static variables. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-stack\-alignment\fR" 4 +.IX Item "-fipa-stack-alignment" +Reduce stack alignment on call sites if possible. +Enabled by default. +.IP "\fB\-fipa\-pta\fR" 4 +.IX Item "-fipa-pta" +Perform interprocedural pointer analysis and interprocedural modification +and reference analysis. This option can cause excessive memory and +compile-time usage on large compilation units. It is not enabled by +default at any optimization level. +.IP "\fB\-fipa\-profile\fR" 4 +.IX Item "-fipa-profile" +Perform interprocedural profile propagation. The functions called only from +cold functions are marked as cold. Also functions executed once (such as +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, static constructors or destructors) are identified. Cold +functions and loop less parts of functions executed once are then optimized for +size. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-cp\fR" 4 +.IX Item "-fipa-cp" +Perform interprocedural constant propagation. +This optimization analyzes the program to determine when values passed +to functions are constants and then optimizes accordingly. +This optimization can substantially increase performance +if the application has constants passed to functions. +This flag is enabled by default at \fB\-O2\fR, \fB\-Os\fR and \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fipa\-cp\-clone\fR" 4 +.IX Item "-fipa-cp-clone" +Perform function cloning to make interprocedural constant propagation stronger. +When enabled, interprocedural constant propagation performs function cloning +when externally visible function can be called with constant arguments. +Because this optimization can create multiple copies of functions, +it may significantly increase code size +(see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR). +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fipa\-bit\-cp\fR" 4 +.IX Item "-fipa-bit-cp" +When enabled, perform interprocedural bitwise constant +propagation. This flag is enabled by default at \fB\-O2\fR and +by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +It requires that \fB\-fipa\-cp\fR is enabled. +.IP "\fB\-fipa\-vrp\fR" 4 +.IX Item "-fipa-vrp" +When enabled, perform interprocedural propagation of value +ranges. This flag is enabled by default at \fB\-O2\fR. It requires +that \fB\-fipa\-cp\fR is enabled. +.IP "\fB\-fipa\-icf\fR" 4 +.IX Item "-fipa-icf" +Perform Identical Code Folding for functions and read-only variables. +The optimization reduces code size and may disturb unwind stacks by replacing +a function by equivalent one with a different name. The optimization works +more effectively with link-time optimization enabled. +.Sp +Although the behavior is similar to the Gold Linker's \s-1ICF\s0 optimization, \s-1GCC ICF\s0 +works on different levels and thus the optimizations are not same \- there are +equivalences that are found only by \s-1GCC\s0 and equivalences found only by Gold. +.Sp +This flag is enabled by default at \fB\-O2\fR and \fB\-Os\fR. +.IP "\fB\-flive\-patching=\fR\fIlevel\fR" 4 +.IX Item "-flive-patching=level" +Control \s-1GCC\s0's optimizations to produce output suitable for live-patching. +.Sp +If the compiler's optimization uses a function's body or information extracted +from its body to optimize/change another function, the latter is called an +impacted function of the former. If a function is patched, its impacted +functions should be patched too. +.Sp +The impacted functions are determined by the compiler's interprocedural +optimizations. For example, a caller is impacted when inlining a function +into its caller, +cloning a function and changing its caller to call this new clone, +or extracting a function's pureness/constness information to optimize +its direct or indirect callers, etc. +.Sp +Usually, the more \s-1IPA\s0 optimizations enabled, the larger the number of +impacted functions for each function. In order to control the number of +impacted functions and more easily compute the list of impacted function, +\&\s-1IPA\s0 optimizations can be partially enabled at two different levels. +.Sp +The \fIlevel\fR argument should be one of the following: +.RS 4 +.IP "\fBinline-clone\fR" 4 +.IX Item "inline-clone" +Only enable inlining and cloning optimizations, which includes inlining, +cloning, interprocedural scalar replacement of aggregates and partial inlining. +As a result, when patching a function, all its callers and its clones' +callers are impacted, therefore need to be patched as well. +.Sp +\&\fB\-flive\-patching=inline\-clone\fR disables the following optimization flags: +\&\fB\-fwhole\-program \-fipa\-pta \-fipa\-reference \-fipa\-ra +\&\-fipa\-icf \-fipa\-icf\-functions \-fipa\-icf\-variables +\&\-fipa\-bit\-cp \-fipa\-vrp \-fipa\-pure\-const \-fipa\-reference\-addressable +\&\-fipa\-stack\-alignment\fR +.IP "\fBinline-only-static\fR" 4 +.IX Item "inline-only-static" +Only enable inlining of static functions. +As a result, when patching a static function, all its callers are impacted +and so need to be patched as well. +.Sp +In addition to all the flags that \fB\-flive\-patching=inline\-clone\fR +disables, +\&\fB\-flive\-patching=inline\-only\-static\fR disables the following additional +optimization flags: +\&\fB\-fipa\-cp\-clone \-fipa\-sra \-fpartial\-inlining \-fipa\-cp\fR +.RE +.RS 4 +.Sp +When \fB\-flive\-patching\fR is specified without any value, the default value +is \fIinline-clone\fR. +.Sp +This flag is disabled by default. +.Sp +Note that \fB\-flive\-patching\fR is not supported with link-time optimization +(\fB\-flto\fR). +.RE +.IP "\fB\-fisolate\-erroneous\-paths\-dereference\fR" 4 +.IX Item "-fisolate-erroneous-paths-dereference" +Detect paths that trigger erroneous or undefined behavior due to +dereferencing a null pointer. Isolate those paths from the main control +flow and turn the statement with erroneous or undefined behavior into a trap. +This flag is enabled by default at \fB\-O2\fR and higher and depends on +\&\fB\-fdelete\-null\-pointer\-checks\fR also being enabled. +.IP "\fB\-fisolate\-erroneous\-paths\-attribute\fR" 4 +.IX Item "-fisolate-erroneous-paths-attribute" +Detect paths that trigger erroneous or undefined behavior due to a null value +being used in a way forbidden by a \f(CW\*(C`returns_nonnull\*(C'\fR or \f(CW\*(C`nonnull\*(C'\fR +attribute. Isolate those paths from the main control flow and turn the +statement with erroneous or undefined behavior into a trap. This is not +currently enabled, but may be enabled by \fB\-O2\fR in the future. +.IP "\fB\-ftree\-sink\fR" 4 +.IX Item "-ftree-sink" +Perform forward store motion on trees. This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-bit\-ccp\fR" 4 +.IX Item "-ftree-bit-ccp" +Perform sparse conditional bit constant propagation on trees and propagate +pointer alignment information. +This pass only operates on local scalar variables and is enabled by default +at \fB\-O1\fR and higher, except for \fB\-Og\fR. +It requires that \fB\-ftree\-ccp\fR is enabled. +.IP "\fB\-ftree\-ccp\fR" 4 +.IX Item "-ftree-ccp" +Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This +pass only operates on local scalar variables and is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-fssa\-backprop\fR" 4 +.IX Item "-fssa-backprop" +Propagate information about uses of a value up the definition chain +in order to simplify the definitions. For example, this pass strips +sign operations if the sign of a value never matters. The flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fssa\-phiopt\fR" 4 +.IX Item "-fssa-phiopt" +Perform pattern matching on \s-1SSA PHI\s0 nodes to optimize conditional +code. This pass is enabled by default at \fB\-O1\fR and higher, +except for \fB\-Og\fR. +.IP "\fB\-ftree\-switch\-conversion\fR" 4 +.IX Item "-ftree-switch-conversion" +Perform conversion of simple initializations in a switch to +initializations from a scalar array. This flag is enabled by default +at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-tail\-merge\fR" 4 +.IX Item "-ftree-tail-merge" +Look for identical code sequences. When found, replace one with a jump to the +other. This optimization is known as tail merging or cross jumping. This flag +is enabled by default at \fB\-O2\fR and higher. The compilation time +in this pass can +be limited using \fBmax-tail-merge-comparisons\fR parameter and +\&\fBmax-tail-merge-iterations\fR parameter. +.IP "\fB\-ftree\-dce\fR" 4 +.IX Item "-ftree-dce" +Perform dead code elimination (\s-1DCE\s0) on trees. This flag is enabled by +default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-builtin\-call\-dce\fR" 4 +.IX Item "-ftree-builtin-call-dce" +Perform conditional dead code elimination (\s-1DCE\s0) for calls to built-in functions +that may set \f(CW\*(C`errno\*(C'\fR but are otherwise free of side effects. This flag is +enabled by default at \fB\-O2\fR and higher if \fB\-Os\fR is not also +specified. +.IP "\fB\-ftree\-dominator\-opts\fR" 4 +.IX Item "-ftree-dominator-opts" +Perform a variety of simple scalar cleanups (constant/copy +propagation, redundancy elimination, range propagation and expression +simplification) based on a dominator tree traversal. This also +performs jump threading (to reduce jumps to jumps). This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-dse\fR" 4 +.IX Item "-ftree-dse" +Perform dead store elimination (\s-1DSE\s0) on trees. A dead store is a store into +a memory location that is later overwritten by another store without +any intervening loads. In this case the earlier store can be deleted. This +flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-ch\fR" 4 +.IX Item "-ftree-ch" +Perform loop header copying on trees. This is beneficial since it increases +effectiveness of code motion optimizations. It also saves one jump. This flag +is enabled by default at \fB\-O\fR and higher. It is not enabled +for \fB\-Os\fR, since it usually increases code size. +.IP "\fB\-ftree\-loop\-optimize\fR" 4 +.IX Item "-ftree-loop-optimize" +Perform loop optimizations on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-loop\-linear\fR" 4 +.IX Item "-ftree-loop-linear" +.PD 0 +.IP "\fB\-floop\-strip\-mine\fR" 4 +.IX Item "-floop-strip-mine" +.IP "\fB\-floop\-block\fR" 4 +.IX Item "-floop-block" +.PD +Perform loop nest optimizations. Same as +\&\fB\-floop\-nest\-optimize\fR. To use this code transformation, \s-1GCC\s0 has +to be configured with \fB\-\-with\-isl\fR to enable the Graphite loop +transformation infrastructure. +.IP "\fB\-fgraphite\-identity\fR" 4 +.IX Item "-fgraphite-identity" +Enable the identity transformation for graphite. For every SCoP we generate +the polyhedral representation and transform it back to gimple. Using +\&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the +\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations +are also performed by the code generator isl, like index splitting and +dead code elimination in loops. +.IP "\fB\-floop\-nest\-optimize\fR" 4 +.IX Item "-floop-nest-optimize" +Enable the isl based loop nest optimizer. This is a generic loop nest +optimizer based on the Pluto optimization algorithms. It calculates a loop +structure optimized for data-locality and parallelism. This option +is experimental. +.IP "\fB\-floop\-parallelize\-all\fR" 4 +.IX Item "-floop-parallelize-all" +Use the Graphite data dependence analysis to identify loops that can +be parallelized. Parallelize all the loops that can be analyzed to +not contain loop carried dependences without checking that it is +profitable to parallelize the loops. +.IP "\fB\-ftree\-coalesce\-vars\fR" 4 +.IX Item "-ftree-coalesce-vars" +While transforming the program out of the \s-1SSA\s0 representation, attempt to +reduce copying by coalescing versions of different user-defined +variables, instead of just compiler temporaries. This may severely +limit the ability to debug an optimized program compiled with +\&\fB\-fno\-var\-tracking\-assignments\fR. In the negated form, this flag +prevents \s-1SSA\s0 coalescing of user variables. This option is enabled by +default if optimization is enabled, and it does very little otherwise. +.IP "\fB\-ftree\-loop\-if\-convert\fR" 4 +.IX Item "-ftree-loop-if-convert" +Attempt to transform conditional jumps in the innermost loops to +branch-less equivalents. The intent is to remove control-flow from +the innermost loops in order to improve the ability of the +vectorization pass to handle these loops. This is enabled by default +if vectorization is enabled. +.IP "\fB\-ftree\-loop\-distribution\fR" 4 +.IX Item "-ftree-loop-distribution" +Perform loop distribution. This flag can improve cache performance on +big loop bodies and allow further loop optimizations, like +parallelization or vectorization, to take place. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = B(I) + C +\& D(I) = E(I) * F +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = B(I) + C +\& ENDDO +\& DO I = 1, N +\& D(I) = E(I) * F +\& ENDDO +.Ve +.Sp +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-ftree\-loop\-distribute\-patterns\fR" 4 +.IX Item "-ftree-loop-distribute-patterns" +Perform loop distribution of patterns that can be code generated with +calls to a library. This flag is enabled by default at \fB\-O3\fR, and +by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.Sp +This pass distributes the initialization loops and generates a call to +memset zero. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = 0 +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = 0 +\& ENDDO +\& DO I = 1, N +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +and the initialization loop is transformed into a call to memset zero. +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-floop\-interchange\fR" 4 +.IX Item "-floop-interchange" +Perform loop interchange outside of graphite. This flag can improve cache +performance on loop nest and allow further loop optimizations, like +vectorization, to take place. For example, the loop +.Sp +.Vb 4 +\& for (int i = 0; i < N; i++) +\& for (int j = 0; j < N; j++) +\& for (int k = 0; k < N; k++) +\& c[i][j] = c[i][j] + a[i][k]*b[k][j]; +.Ve +.Sp +is transformed to +.Sp +.Vb 4 +\& for (int i = 0; i < N; i++) +\& for (int k = 0; k < N; k++) +\& for (int j = 0; j < N; j++) +\& c[i][j] = c[i][j] + a[i][k]*b[k][j]; +.Ve +.Sp +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-floop\-unroll\-and\-jam\fR" 4 +.IX Item "-floop-unroll-and-jam" +Apply unroll and jam transformations on feasible loops. In a loop +nest this unrolls the outer loop by some factor and fuses the resulting +multiple inner loops. This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-ftree\-loop\-im\fR" 4 +.IX Item "-ftree-loop-im" +Perform loop invariant motion on trees. This pass moves only invariants that +are hard to handle at \s-1RTL\s0 level (function calls, operations that expand to +nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves +operands of conditions that are invariant out of the loop, so that we can use +just trivial invariantness analysis in loop unswitching. The pass also includes +store motion. +.IP "\fB\-ftree\-loop\-ivcanon\fR" 4 +.IX Item "-ftree-loop-ivcanon" +Create a canonical counter for number of iterations in loops for which +determining number of iterations requires complicated analysis. Later +optimizations then may determine the number easily. Useful especially +in connection with unrolling. +.IP "\fB\-ftree\-scev\-cprop\fR" 4 +.IX Item "-ftree-scev-cprop" +Perform final value replacement. If a variable is modified in a loop +in such a way that its value when exiting the loop can be determined using +only its initial value and the number of loop iterations, replace uses of +the final value by such a computation, provided it is sufficiently cheap. +This reduces data dependencies and may allow further simplifications. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fivopts\fR" 4 +.IX Item "-fivopts" +Perform induction variable optimizations (strength reduction, induction +variable merging and induction variable elimination) on trees. +.IP "\fB\-ftree\-parallelize\-loops=n\fR" 4 +.IX Item "-ftree-parallelize-loops=n" +Parallelize loops, i.e., split their iteration space to run in n threads. +This is only possible for loops whose iterations are independent +and can be arbitrarily reordered. The optimization is only +profitable on multiprocessor machines, for loops that are CPU-intensive, +rather than constrained e.g. by memory bandwidth. This option +implies \fB\-pthread\fR, and thus is only supported on targets +that have support for \fB\-pthread\fR. +.IP "\fB\-ftree\-pta\fR" 4 +.IX Item "-ftree-pta" +Perform function-local points-to analysis on trees. This flag is +enabled by default at \fB\-O1\fR and higher, except for \fB\-Og\fR. +.IP "\fB\-ftree\-sra\fR" 4 +.IX Item "-ftree-sra" +Perform scalar replacement of aggregates. This pass replaces structure +references with scalars to prevent committing structures to memory too +early. This flag is enabled by default at \fB\-O1\fR and higher, +except for \fB\-Og\fR. +.IP "\fB\-fstore\-merging\fR" 4 +.IX Item "-fstore-merging" +Perform merging of narrow stores to consecutive memory addresses. This pass +merges contiguous stores of immediate values narrower than a word into fewer +wider stores to reduce the number of instructions. This is enabled by default +at \fB\-O2\fR and higher as well as \fB\-Os\fR. +.IP "\fB\-ftree\-ter\fR" 4 +.IX Item "-ftree-ter" +Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single +use/single def temporaries are replaced at their use location with their +defining expression. This results in non-GIMPLE code, but gives the expanders +much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-slsr\fR" 4 +.IX Item "-ftree-slsr" +Perform straight-line strength reduction on trees. This recognizes related +expressions involving multiplications and replaces them by less expensive +calculations when possible. This is enabled by default at \fB\-O\fR and +higher. +.IP "\fB\-ftree\-vectorize\fR" 4 +.IX Item "-ftree-vectorize" +Perform vectorization on trees. This flag enables \fB\-ftree\-loop\-vectorize\fR +and \fB\-ftree\-slp\-vectorize\fR if not explicitly specified. +.IP "\fB\-ftree\-loop\-vectorize\fR" 4 +.IX Item "-ftree-loop-vectorize" +Perform loop vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR and by \fB\-ftree\-vectorize\fR, \fB\-fprofile\-use\fR, +and \fB\-fauto\-profile\fR. +.IP "\fB\-ftree\-slp\-vectorize\fR" 4 +.IX Item "-ftree-slp-vectorize" +Perform basic block vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR and by \fB\-ftree\-vectorize\fR, \fB\-fprofile\-use\fR, +and \fB\-fauto\-profile\fR. +.IP "\fB\-fvect\-cost\-model=\fR\fImodel\fR" 4 +.IX Item "-fvect-cost-model=model" +Alter the cost model used for vectorization. The \fImodel\fR argument +should be one of \fBunlimited\fR, \fBdynamic\fR or \fBcheap\fR. +With the \fBunlimited\fR model the vectorized code-path is assumed +to be profitable while with the \fBdynamic\fR model a runtime check +guards the vectorized code-path to enable it only for iteration +counts that will likely execute faster than when executing the original +scalar loop. The \fBcheap\fR model disables vectorization of +loops where doing so would be cost prohibitive for example due to +required runtime checks for data dependence or alignment but otherwise +is equal to the \fBdynamic\fR model. +The default cost model depends on other optimization flags and is +either \fBdynamic\fR or \fBcheap\fR. +.IP "\fB\-fsimd\-cost\-model=\fR\fImodel\fR" 4 +.IX Item "-fsimd-cost-model=model" +Alter the cost model used for vectorization of loops marked with the OpenMP +simd directive. The \fImodel\fR argument should be one of +\&\fBunlimited\fR, \fBdynamic\fR, \fBcheap\fR. All values of \fImodel\fR +have the same meaning as described in \fB\-fvect\-cost\-model\fR and by +default a cost model defined with \fB\-fvect\-cost\-model\fR is used. +.IP "\fB\-ftree\-vrp\fR" 4 +.IX Item "-ftree-vrp" +Perform Value Range Propagation on trees. This is similar to the +constant propagation pass, but instead of values, ranges of values are +propagated. This allows the optimizers to remove unnecessary range +checks like array bound checks and null pointer checks. This is +enabled by default at \fB\-O2\fR and higher. Null pointer check +elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is +enabled. +.IP "\fB\-fsplit\-paths\fR" 4 +.IX Item "-fsplit-paths" +Split paths leading to loop backedges. This can improve dead code +elimination and common subexpression elimination. This is enabled by +default at \fB\-O3\fR and above. +.IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4 +.IX Item "-fsplit-ivs-in-unroller" +Enables expression of values of induction variables in later iterations +of the unrolled loop using the value in the first iteration. This breaks +long dependency chains, thus improving efficiency of the scheduling passes. +.Sp +A combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the +same effect. However, that is not reliable in cases where the loop body +is more complicated than a single basic block. It also does not work at all +on some architectures due to restrictions in the \s-1CSE\s0 pass. +.Sp +This optimization is enabled by default. +.IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4 +.IX Item "-fvariable-expansion-in-unroller" +With this option, the compiler creates multiple copies of some +local variables when unrolling a loop, which can result in superior code. +.IP "\fB\-fpartial\-inlining\fR" 4 +.IX Item "-fpartial-inlining" +Inline parts of functions. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fpredictive\-commoning\fR" 4 +.IX Item "-fpredictive-commoning" +Perform predictive commoning optimization, i.e., reusing computations +(especially memory loads and stores) performed in previous +iterations of loops. +.Sp +This option is enabled at level \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fprefetch\-loop\-arrays\fR" 4 +.IX Item "-fprefetch-loop-arrays" +If supported by the target machine, generate instructions to prefetch +memory to improve the performance of loops that access large arrays. +.Sp +This option may generate better or worse code; results are highly +dependent on the structure of loops within the source code. +.Sp +Disabled at level \fB\-Os\fR. +.IP "\fB\-fno\-printf\-return\-value\fR" 4 +.IX Item "-fno-printf-return-value" +Do not substitute constants for known return value of formatted output +functions such as \f(CW\*(C`sprintf\*(C'\fR, \f(CW\*(C`snprintf\*(C'\fR, \f(CW\*(C`vsprintf\*(C'\fR, and +\&\f(CW\*(C`vsnprintf\*(C'\fR (but not \f(CW\*(C`printf\*(C'\fR of \f(CW\*(C`fprintf\*(C'\fR). This +transformation allows \s-1GCC\s0 to optimize or even eliminate branches based +on the known return value of these functions called with arguments that +are either constant, or whose values are known to be in a range that +makes determining the exact return value possible. For example, when +\&\fB\-fprintf\-return\-value\fR is in effect, both the branch and the +body of the \f(CW\*(C`if\*(C'\fR statement (but not the call to \f(CW\*(C`snprint\*(C'\fR) +can be optimized away when \f(CW\*(C`i\*(C'\fR is a 32\-bit or smaller integer +because the return value is guaranteed to be at most 8. +.Sp +.Vb 3 +\& char buf[9]; +\& if (snprintf (buf, "%08x", i) >= sizeof buf) +\& ... +.Ve +.Sp +The \fB\-fprintf\-return\-value\fR option relies on other optimizations +and yields best results with \fB\-O2\fR and above. It works in tandem +with the \fB\-Wformat\-overflow\fR and \fB\-Wformat\-truncation\fR +options. The \fB\-fprintf\-return\-value\fR option is enabled by default. +.IP "\fB\-fno\-peephole\fR" 4 +.IX Item "-fno-peephole" +.PD 0 +.IP "\fB\-fno\-peephole2\fR" 4 +.IX Item "-fno-peephole2" +.PD +Disable any machine-specific peephole optimizations. The difference +between \fB\-fno\-peephole\fR and \fB\-fno\-peephole2\fR is in how they +are implemented in the compiler; some targets use one, some use the +other, a few use both. +.Sp +\&\fB\-fpeephole\fR is enabled by default. +\&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-guess\-branch\-probability\fR" 4 +.IX Item "-fno-guess-branch-probability" +Do not guess branch probabilities using heuristics. +.Sp +\&\s-1GCC\s0 uses heuristics to guess branch probabilities if they are +not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These +heuristics are based on the control flow graph. If some branch probabilities +are specified by \f(CW\*(C`_\|_builtin_expect\*(C'\fR, then the heuristics are +used to guess branch probabilities for the rest of the control flow graph, +taking the \f(CW\*(C`_\|_builtin_expect\*(C'\fR info into account. The interactions +between the heuristics and \f(CW\*(C`_\|_builtin_expect\*(C'\fR can be complex, and in +some cases, it may be useful to disable the heuristics so that the effects +of \f(CW\*(C`_\|_builtin_expect\*(C'\fR are easier to understand. +.Sp +It is also possible to specify expected probability of the expression +with \f(CW\*(C`_\|_builtin_expect_with_probability\*(C'\fR built-in function. +.Sp +The default is \fB\-fguess\-branch\-probability\fR at levels +\&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-blocks\fR" 4 +.IX Item "-freorder-blocks" +Reorder basic blocks in the compiled function in order to reduce number of +taken branches and improve code locality. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-blocks\-algorithm=\fR\fIalgorithm\fR" 4 +.IX Item "-freorder-blocks-algorithm=algorithm" +Use the specified algorithm for basic block reordering. The +\&\fIalgorithm\fR argument can be \fBsimple\fR, which does not increase +code size (except sometimes due to secondary effects like alignment), +or \fBstc\fR, the \*(L"software trace cache\*(R" algorithm, which tries to +put all often executed code together, minimizing the number of branches +executed by making extra copies of code. +.Sp +The default is \fBsimple\fR at levels \fB\-O\fR, \fB\-Os\fR, and +\&\fBstc\fR at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-freorder\-blocks\-and\-partition\fR" 4 +.IX Item "-freorder-blocks-and-partition" +In addition to reordering basic blocks in the compiled function, in order +to reduce number of taken branches, partitions hot and cold basic blocks +into separate sections of the assembly and \fI.o\fR files, to improve +paging and cache locality performance. +.Sp +This optimization is automatically turned off in the presence of +exception handling or unwind tables (on targets using setjump/longjump or target specific scheme), for linkonce sections, for functions with a user-defined +section attribute and on any architecture that does not support named +sections. When \fB\-fsplit\-stack\fR is used this option is not +enabled by default (to avoid linker errors), but may be enabled +explicitly (if using a working linker). +.Sp +Enabled for x86 at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-functions\fR" 4 +.IX Item "-freorder-functions" +Reorder functions in the object file in order to +improve code locality. This is implemented by using special +subsections \f(CW\*(C`.text.hot\*(C'\fR for most frequently executed functions and +\&\f(CW\*(C`.text.unlikely\*(C'\fR for unlikely executed functions. Reordering is done by +the linker so object file format must support named sections and linker must +place them in a reasonable way. +.Sp +This option isn't effective unless you either provide profile feedback +(see \fB\-fprofile\-arcs\fR for details) or manually annotate functions with +\&\f(CW\*(C`hot\*(C'\fR or \f(CW\*(C`cold\*(C'\fR attributes. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fstrict\-aliasing\fR" 4 +.IX Item "-fstrict-aliasing" +Allow the compiler to assume the strictest aliasing rules applicable to +the language being compiled. For C (and \*(C+), this activates +optimizations based on the type of expressions. In particular, an +object of one type is assumed never to reside at the same address as an +object of a different type, unless the types are almost the same. For +example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a +\&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR. A character type may alias any other +type. +.Sp +Pay special attention to code like this: +.Sp +.Vb 4 +\& union a_union { +\& int i; +\& double d; +\& }; +\& +\& int f() { +\& union a_union t; +\& t.d = 3.0; +\& return t.i; +\& } +.Ve +.Sp +The practice of reading from a different union member than the one most +recently written to (called \*(L"type-punning\*(R") is common. Even with +\&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory +is accessed through the union type. So, the code above works as +expected. However, this code might not: +.Sp +.Vb 7 +\& int f() { +\& union a_union t; +\& int* ip; +\& t.d = 3.0; +\& ip = &t.i; +\& return *ip; +\& } +.Ve +.Sp +Similarly, access by taking the address, casting the resulting pointer +and dereferencing the result has undefined behavior, even if the cast +uses a union type, e.g.: +.Sp +.Vb 4 +\& int f() { +\& double d = 3.0; +\& return ((union a_union *) &d)\->i; +\& } +.Ve +.Sp +The \fB\-fstrict\-aliasing\fR option is enabled at levels +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-falign\-functions\fR" 4 +.IX Item "-falign-functions" +.PD 0 +.IP "\fB\-falign\-functions=\fR\fIn\fR" 4 +.IX Item "-falign-functions=n" +.IP "\fB\-falign\-functions=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-functions=n:m" +.IP "\fB\-falign\-functions=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-functions=n:m:n2" +.IP "\fB\-falign\-functions=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-functions=n:m:n2:m2" +.PD +Align the start of functions to the next power-of-two greater than +\&\fIn\fR, skipping up to \fIm\fR\-1 bytes. This ensures that at least +the first \fIm\fR bytes of the function can be fetched by the \s-1CPU\s0 +without crossing an \fIn\fR\-byte alignment boundary. +.Sp +If \fIm\fR is not specified, it defaults to \fIn\fR. +.Sp +Examples: \fB\-falign\-functions=32\fR aligns functions to the next +32\-byte boundary, \fB\-falign\-functions=24\fR aligns to the next +32\-byte boundary only if this can be done by skipping 23 bytes or less, +\&\fB\-falign\-functions=32:7\fR aligns to the next +32\-byte boundary only if this can be done by skipping 6 bytes or less. +.Sp +The second pair of \fIn2\fR:\fIm2\fR values allows you to specify +a secondary alignment: \fB\-falign\-functions=64:7:32:3\fR aligns to +the next 64\-byte boundary if this can be done by skipping 6 bytes or less, +otherwise aligns to the next 32\-byte boundary if this can be done +by skipping 2 bytes or less. +If \fIm2\fR is not specified, it defaults to \fIn2\fR. +.Sp +Some assemblers only support this flag when \fIn\fR is a power of two; +in that case, it is rounded up. +.Sp +\&\fB\-fno\-align\-functions\fR and \fB\-falign\-functions=1\fR are +equivalent and mean that functions are not aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +The maximum allowed \fIn\fR option value is 65536. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-flimit\-function\-alignment\fR" 4 +.IX Item "-flimit-function-alignment" +If this option is enabled, the compiler tries to avoid unnecessarily +overaligning functions. It attempts to instruct the assembler to align +by the amount specified by \fB\-falign\-functions\fR, but not to +skip more bytes than the size of the function. +.IP "\fB\-falign\-labels\fR" 4 +.IX Item "-falign-labels" +.PD 0 +.IP "\fB\-falign\-labels=\fR\fIn\fR" 4 +.IX Item "-falign-labels=n" +.IP "\fB\-falign\-labels=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-labels=n:m" +.IP "\fB\-falign\-labels=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-labels=n:m:n2" +.IP "\fB\-falign\-labels=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-labels=n:m:n2:m2" +.PD +Align all branch targets to a power-of-two boundary. +.Sp +Parameters of this option are analogous to the \fB\-falign\-functions\fR option. +\&\fB\-fno\-align\-labels\fR and \fB\-falign\-labels=1\fR are +equivalent and mean that labels are not aligned. +.Sp +If \fB\-falign\-loops\fR or \fB\-falign\-jumps\fR are applicable and +are greater than this value, then their values are used instead. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default +which is very likely to be \fB1\fR, meaning no alignment. +The maximum allowed \fIn\fR option value is 65536. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-loops\fR" 4 +.IX Item "-falign-loops" +.PD 0 +.IP "\fB\-falign\-loops=\fR\fIn\fR" 4 +.IX Item "-falign-loops=n" +.IP "\fB\-falign\-loops=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-loops=n:m" +.IP "\fB\-falign\-loops=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-loops=n:m:n2" +.IP "\fB\-falign\-loops=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-loops=n:m:n2:m2" +.PD +Align loops to a power-of-two boundary. If the loops are executed +many times, this makes up for any execution of the dummy padding +instructions. +.Sp +Parameters of this option are analogous to the \fB\-falign\-functions\fR option. +\&\fB\-fno\-align\-loops\fR and \fB\-falign\-loops=1\fR are +equivalent and mean that loops are not aligned. +The maximum allowed \fIn\fR option value is 65536. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-jumps\fR" 4 +.IX Item "-falign-jumps" +.PD 0 +.IP "\fB\-falign\-jumps=\fR\fIn\fR" 4 +.IX Item "-falign-jumps=n" +.IP "\fB\-falign\-jumps=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-jumps=n:m" +.IP "\fB\-falign\-jumps=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-jumps=n:m:n2" +.IP "\fB\-falign\-jumps=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-jumps=n:m:n2:m2" +.PD +Align branch targets to a power-of-two boundary, for branch targets +where the targets can only be reached by jumping. In this case, +no dummy operations need be executed. +.Sp +Parameters of this option are analogous to the \fB\-falign\-functions\fR option. +\&\fB\-fno\-align\-jumps\fR and \fB\-falign\-jumps=1\fR are +equivalent and mean that loops are not aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +The maximum allowed \fIn\fR option value is 65536. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-funit\-at\-a\-time\fR" 4 +.IX Item "-funit-at-a-time" +This option is left for compatibility reasons. \fB\-funit\-at\-a\-time\fR +has no effect, while \fB\-fno\-unit\-at\-a\-time\fR implies +\&\fB\-fno\-toplevel\-reorder\fR and \fB\-fno\-section\-anchors\fR. +.Sp +Enabled by default. +.IP "\fB\-fno\-toplevel\-reorder\fR" 4 +.IX Item "-fno-toplevel-reorder" +Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR +statements. Output them in the same order that they appear in the +input file. When this option is used, unreferenced static variables +are not removed. This option is intended to support existing code +that relies on a particular ordering. For new code, it is better to +use attributes when possible. +.Sp +\&\fB\-ftoplevel\-reorder\fR is the default at \fB\-O1\fR and higher, and +also at \fB\-O0\fR if \fB\-fsection\-anchors\fR is explicitly requested. +Additionally \fB\-fno\-toplevel\-reorder\fR implies +\&\fB\-fno\-section\-anchors\fR. +.IP "\fB\-fweb\fR" 4 +.IX Item "-fweb" +Constructs webs as commonly used for register allocation purposes and assign +each web individual pseudo register. This allows the register allocation pass +to operate on pseudos directly, but also strengthens several other optimization +passes, such as \s-1CSE,\s0 loop optimizer and trivial dead code remover. It can, +however, make debugging impossible, since variables no longer stay in a +\&\*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR. +.IP "\fB\-fwhole\-program\fR" 4 +.IX Item "-fwhole-program" +Assume that the current compilation unit represents the whole program being +compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR +and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions +and in effect are optimized more aggressively by interprocedural optimizers. +.Sp +This option should not be used in combination with \fB\-flto\fR. +Instead relying on a linker plugin should provide safer and more precise +information. +.IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-flto[=n]" +This option runs the standard link-time optimizer. When invoked +with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal +representations) and writes it to special \s-1ELF\s0 sections in the object +file. When the object files are linked together, all the function +bodies are read from these \s-1ELF\s0 sections and instantiated as if they +had been part of the same translation unit. +.Sp +To use the link-time optimizer, \fB\-flto\fR and optimization +options should be specified at compile time and during the final link. +It is recommended that you compile all the files participating in the +same link with the same options and also specify those options at +link time. +For example: +.Sp +.Vb 3 +\& gcc \-c \-O2 \-flto foo.c +\& gcc \-c \-O2 \-flto bar.c +\& gcc \-o myprog \-flto \-O2 foo.o bar.o +.Ve +.Sp +The first two invocations to \s-1GCC\s0 save a bytecode representation +of \s-1GIMPLE\s0 into special \s-1ELF\s0 sections inside \fIfoo.o\fR and +\&\fIbar.o\fR. The final invocation reads the \s-1GIMPLE\s0 bytecode from +\&\fIfoo.o\fR and \fIbar.o\fR, merges the two files into a single +internal image, and compiles the result as usual. Since both +\&\fIfoo.o\fR and \fIbar.o\fR are merged into a single image, this +causes all the interprocedural analyses and optimizations in \s-1GCC\s0 to +work across the two files as if they were a single one. This means, +for example, that the inliner is able to inline functions in +\&\fIbar.o\fR into functions in \fIfoo.o\fR and vice-versa. +.Sp +Another (simpler) way to enable link-time optimization is: +.Sp +.Vb 1 +\& gcc \-o myprog \-flto \-O2 foo.c bar.c +.Ve +.Sp +The above generates bytecode for \fIfoo.c\fR and \fIbar.c\fR, +merges them together into a single \s-1GIMPLE\s0 representation and optimizes +them as usual to produce \fImyprog\fR. +.Sp +The important thing to keep in mind is that to enable link-time +optimizations you need to use the \s-1GCC\s0 driver to perform the link step. +\&\s-1GCC\s0 automatically performs link-time optimization if any of the +objects involved were compiled with the \fB\-flto\fR command-line option. +You can always override +the automatic decision to do link-time optimization +by passing \fB\-fno\-lto\fR to the link command. +.Sp +To make whole program optimization effective, it is necessary to make +certain whole program assumptions. The compiler needs to know +what functions and variables can be accessed by libraries and runtime +outside of the link-time optimized unit. When supported by the linker, +the linker plugin (see \fB\-fuse\-linker\-plugin\fR) passes information +to the compiler about used and externally visible symbols. When +the linker plugin is not available, \fB\-fwhole\-program\fR should be +used to allow the compiler to make these assumptions, which leads +to more aggressive optimization decisions. +.Sp +When a file is compiled with \fB\-flto\fR without +\&\fB\-fuse\-linker\-plugin\fR, the generated object file is larger than +a regular object file because it contains \s-1GIMPLE\s0 bytecodes and the usual +final code (see \fB\-ffat\-lto\-objects\fR. This means that +object files with \s-1LTO\s0 information can be linked as normal object +files; if \fB\-fno\-lto\fR is passed to the linker, no +interprocedural optimizations are applied. Note that when +\&\fB\-fno\-fat\-lto\-objects\fR is enabled the compile stage is faster +but you cannot perform a regular, non-LTO link on them. +.Sp +When producing the final binary, \s-1GCC\s0 only +applies link-time optimizations to those files that contain bytecode. +Therefore, you can mix and match object files and libraries with +\&\s-1GIMPLE\s0 bytecodes and final object code. \s-1GCC\s0 automatically selects +which files to optimize in \s-1LTO\s0 mode and which files to link without +further processing. +.Sp +Generally, options specified at link time override those +specified at compile time, although in some cases \s-1GCC\s0 attempts to infer +link-time options from the settings used to compile the input files. +.Sp +If you do not specify an optimization level option \fB\-O\fR at +link time, then \s-1GCC\s0 uses the highest optimization level +used when compiling the object files. Note that it is generally +ineffective to specify an optimization level option only at link time and +not at compile time, for two reasons. First, compiling without +optimization suppresses compiler passes that gather information +needed for effective optimization at link time. Second, some early +optimization passes can be performed only at compile time and +not at link time. +.Sp +There are some code generation flags preserved by \s-1GCC\s0 when +generating bytecodes, as they need to be used during the final link. +Currently, the following options and their settings are taken from +the first object file that explicitly specifies them: +\&\fB\-fPIC\fR, \fB\-fpic\fR, \fB\-fpie\fR, \fB\-fcommon\fR, +\&\fB\-fexceptions\fR, \fB\-fnon\-call\-exceptions\fR, \fB\-fgnu\-tm\fR +and all the \fB\-m\fR target flags. +.Sp +Certain ABI-changing flags are required to match in all compilation units, +and trying to override this at link time with a conflicting value +is ignored. This includes options such as \fB\-freg\-struct\-return\fR +and \fB\-fpcc\-struct\-return\fR. +.Sp +Other options such as \fB\-ffp\-contract\fR, \fB\-fno\-strict\-overflow\fR, +\&\fB\-fwrapv\fR, \fB\-fno\-trapv\fR or \fB\-fno\-strict\-aliasing\fR +are passed through to the link stage and merged conservatively for +conflicting translation units. Specifically +\&\fB\-fno\-strict\-overflow\fR, \fB\-fwrapv\fR and \fB\-fno\-trapv\fR take +precedence; and for example \fB\-ffp\-contract=off\fR takes precedence +over \fB\-ffp\-contract=fast\fR. You can override them at link time. +.Sp +When you need to pass options to the assembler via \fB\-Wa\fR or +\&\fB\-Xassembler\fR make sure to either compile such translation +units with \fB\-fno\-lto\fR or consistently use the same assembler +options on all translation units. You can alternatively also +specify assembler options at \s-1LTO\s0 link time. +.Sp +If \s-1LTO\s0 encounters objects with C linkage declared with incompatible +types in separate translation units to be linked together (undefined +behavior according to \s-1ISO C99 6.2.7\s0), a non-fatal diagnostic may be +issued. The behavior is still undefined at run time. Similar +diagnostics may be raised for other languages. +.Sp +Another feature of \s-1LTO\s0 is that it is possible to apply interprocedural +optimizations on files written in different languages: +.Sp +.Vb 4 +\& gcc \-c \-flto foo.c +\& g++ \-c \-flto bar.cc +\& gfortran \-c \-flto baz.f90 +\& g++ \-o myprog \-flto \-O3 foo.o bar.o baz.o \-lgfortran +.Ve +.Sp +Notice that the final link is done with \fBg++\fR to get the \*(C+ +runtime libraries and \fB\-lgfortran\fR is added to get the Fortran +runtime libraries. In general, when mixing languages in \s-1LTO\s0 mode, you +should use the same link command options as when mixing languages in a +regular (non-LTO) compilation. +.Sp +If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say +\&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you +are using a linker with plugin support. To create static libraries suitable +for \s-1LTO,\s0 use \fBgcc-ar\fR and \fBgcc-ranlib\fR instead of \fBar\fR +and \fBranlib\fR; +to show the symbols of object files with \s-1GIMPLE\s0 bytecode, use +\&\fBgcc-nm\fR. Those commands require that \fBar\fR, \fBranlib\fR +and \fBnm\fR have been compiled with plugin support. At link time, use the +flag \fB\-fuse\-linker\-plugin\fR to ensure that the library participates in +the \s-1LTO\s0 optimization process: +.Sp +.Vb 1 +\& gcc \-o myprog \-O2 \-flto \-fuse\-linker\-plugin a.o b.o \-lfoo +.Ve +.Sp +With the linker plugin enabled, the linker extracts the needed +\&\s-1GIMPLE\s0 files from \fIlibfoo.a\fR and passes them on to the running \s-1GCC\s0 +to make them part of the aggregated \s-1GIMPLE\s0 image to be optimized. +.Sp +If you are not using a linker with plugin support and/or do not +enable the linker plugin, then the objects inside \fIlibfoo.a\fR +are extracted and linked as usual, but they do not participate +in the \s-1LTO\s0 optimization process. In order to make a static library suitable +for both \s-1LTO\s0 optimization and usual linkage, compile its object files with +\&\fB\-flto\fR \fB\-ffat\-lto\-objects\fR. +.Sp +Link-time optimizations do not require the presence of the whole program to +operate. If the program does not require any symbols to be exported, it is +possible to combine \fB\-flto\fR and \fB\-fwhole\-program\fR to allow +the interprocedural optimizers to use more aggressive assumptions which may +lead to improved optimization opportunities. +Use of \fB\-fwhole\-program\fR is not needed when linker plugin is +active (see \fB\-fuse\-linker\-plugin\fR). +.Sp +The current implementation of \s-1LTO\s0 makes no +attempt to generate bytecode that is portable between different +types of hosts. The bytecode files are versioned and there is a +strict version check, so bytecode files generated in one version of +\&\s-1GCC\s0 do not work with an older or newer version of \s-1GCC.\s0 +.Sp +Link-time optimization does not work well with generation of debugging +information on systems other than those using a combination of \s-1ELF\s0 and +\&\s-1DWARF.\s0 +.Sp +If you specify the optional \fIn\fR, the optimization and code +generation done at link time is executed in parallel using \fIn\fR +parallel jobs by utilizing an installed \fBmake\fR program. The +environment variable \fB\s-1MAKE\s0\fR may be used to override the program +used. The default value for \fIn\fR is 1. +.Sp +You can also specify \fB\-flto=jobserver\fR to use \s-1GNU\s0 make's +job server mode to determine the number of parallel jobs. This +is useful when the Makefile calling \s-1GCC\s0 is already executing in parallel. +You must prepend a \fB+\fR to the command recipe in the parent Makefile +for this to work. This option likely only works if \fB\s-1MAKE\s0\fR is +\&\s-1GNU\s0 make. +.IP "\fB\-flto\-partition=\fR\fIalg\fR" 4 +.IX Item "-flto-partition=alg" +Specify the partitioning algorithm used by the link-time optimizer. +The value is either \fB1to1\fR to specify a partitioning mirroring +the original source files or \fBbalanced\fR to specify partitioning +into equally sized chunks (whenever possible) or \fBmax\fR to create +new partition for every symbol where possible. Specifying \fBnone\fR +as an algorithm disables partitioning and streaming completely. +The default value is \fBbalanced\fR. While \fB1to1\fR can be used +as an workaround for various code ordering issues, the \fBmax\fR +partitioning is intended for internal testing only. +The value \fBone\fR specifies that exactly one partition should be +used while the value \fBnone\fR bypasses partitioning and executes +the link-time optimization step directly from the \s-1WPA\s0 phase. +.IP "\fB\-flto\-odr\-type\-merging\fR" 4 +.IX Item "-flto-odr-type-merging" +Enable streaming of mangled types names of \*(C+ types and their unification +at link time. This increases size of \s-1LTO\s0 object files, but enables +diagnostics about One Definition Rule violations. +.IP "\fB\-flto\-compression\-level=\fR\fIn\fR" 4 +.IX Item "-flto-compression-level=n" +This option specifies the level of compression used for intermediate +language written to \s-1LTO\s0 object files, and is only meaningful in +conjunction with \s-1LTO\s0 mode (\fB\-flto\fR). Valid +values are 0 (no compression) to 9 (maximum compression). Values +outside this range are clamped to either 0 or 9. If the option is not +given, a default balanced compression setting is used. +.IP "\fB\-fuse\-linker\-plugin\fR" 4 +.IX Item "-fuse-linker-plugin" +Enables the use of a linker plugin during link-time optimization. This +option relies on plugin support in the linker, which is available in gold +or in \s-1GNU\s0 ld 2.21 or newer. +.Sp +This option enables the extraction of object files with \s-1GIMPLE\s0 bytecode out +of library archives. This improves the quality of optimization by exposing +more code to the link-time optimizer. This information specifies what +symbols can be accessed externally (by non-LTO object or during dynamic +linking). Resulting code quality improvements on binaries (and shared +libraries that use hidden visibility) are similar to \fB\-fwhole\-program\fR. +See \fB\-flto\fR for a description of the effect of this flag and how to +use it. +.Sp +This option is enabled by default when \s-1LTO\s0 support in \s-1GCC\s0 is enabled +and \s-1GCC\s0 was configured for use with +a linker supporting plugins (\s-1GNU\s0 ld 2.21 or newer or gold). +.IP "\fB\-ffat\-lto\-objects\fR" 4 +.IX Item "-ffat-lto-objects" +Fat \s-1LTO\s0 objects are object files that contain both the intermediate language +and the object code. This makes them usable for both \s-1LTO\s0 linking and normal +linking. This option is effective only when compiling with \fB\-flto\fR +and is ignored at link time. +.Sp +\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO,\s0 but +requires the complete toolchain to be aware of \s-1LTO.\s0 It requires a linker with +linker plugin support for basic functionality. Additionally, +\&\fBnm\fR, \fBar\fR and \fBranlib\fR +need to support linker plugins to allow a full-featured build environment +(capable of building static libraries etc). \s-1GCC\s0 provides the \fBgcc-ar\fR, +\&\fBgcc-nm\fR, \fBgcc-ranlib\fR wrappers to pass the right options +to these tools. With non fat \s-1LTO\s0 makefiles need to be modified to use them. +.Sp +Note that modern binutils provide plugin auto-load mechanism. +Installing the linker plugin into \fI\f(CI$libdir\fI/bfd\-plugins\fR has the same +effect as usage of the command wrappers (\fBgcc-ar\fR, \fBgcc-nm\fR and +\&\fBgcc-ranlib\fR). +.Sp +The default is \fB\-fno\-fat\-lto\-objects\fR on targets with linker plugin +support. +.IP "\fB\-fcompare\-elim\fR" 4 +.IX Item "-fcompare-elim" +After register allocation and post-register allocation instruction splitting, +identify arithmetic instructions that compute processor flags similar to a +comparison operation based on that arithmetic. If possible, eliminate the +explicit comparison operation. +.Sp +This pass only applies to certain targets that cannot explicitly represent +the comparison operation before register allocation is complete. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcprop\-registers\fR" 4 +.IX Item "-fcprop-registers" +After register allocation and post-register allocation instruction splitting, +perform a copy-propagation pass to try to reduce scheduling dependencies +and occasionally eliminate the copy. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fprofile\-correction\fR" 4 +.IX Item "-fprofile-correction" +Profiles collected using an instrumented binary for multi-threaded programs may +be inconsistent due to missed counter updates. When this option is specified, +\&\s-1GCC\s0 uses heuristics to correct or smooth out such inconsistencies. By +default, \s-1GCC\s0 emits an error message when an inconsistent profile is detected. +.Sp +This option is enabled by \fB\-fauto\-profile\fR. +.IP "\fB\-fprofile\-use\fR" 4 +.IX Item "-fprofile-use" +.PD 0 +.IP "\fB\-fprofile\-use=\fR\fIpath\fR" 4 +.IX Item "-fprofile-use=path" +.PD +Enable profile feedback-directed optimizations, +and the following optimizations, many of which +are generally profitable only with profile feedback available: +.Sp +\&\fB\-fbranch\-probabilities \-fprofile\-values +\&\-funroll\-loops \-fpeel\-loops \-ftracer \-fvpt +\&\-finline\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-bit\-cp +\&\-fpredictive\-commoning \-fsplit\-loops \-funswitch\-loops +\&\-fgcse\-after\-reload \-ftree\-loop\-vectorize \-ftree\-slp\-vectorize +\&\-fvect\-cost\-model=dynamic \-ftree\-loop\-distribute\-patterns +\&\-fprofile\-reorder\-functions\fR +.Sp +Before you can use this option, you must first generate profiling information. +.Sp +By default, \s-1GCC\s0 emits an error message if the feedback profiles do not +match the source code. This error can be turned into a warning by using +\&\fB\-Wno\-error=coverage\-mismatch\fR. Note this may result in poorly +optimized code. Additionally, by default, \s-1GCC\s0 also emits a warning message if +the feedback profiles do not exist (see \fB\-Wmissing\-profile\fR). +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 looks at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.IP "\fB\-fauto\-profile\fR" 4 +.IX Item "-fauto-profile" +.PD 0 +.IP "\fB\-fauto\-profile=\fR\fIpath\fR" 4 +.IX Item "-fauto-profile=path" +.PD +Enable sampling-based feedback-directed optimizations, +and the following optimizations, +many of which are generally profitable only with profile feedback available: +.Sp +\&\fB\-fbranch\-probabilities \-fprofile\-values +\&\-funroll\-loops \-fpeel\-loops \-ftracer \-fvpt +\&\-finline\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-bit\-cp +\&\-fpredictive\-commoning \-fsplit\-loops \-funswitch\-loops +\&\-fgcse\-after\-reload \-ftree\-loop\-vectorize \-ftree\-slp\-vectorize +\&\-fvect\-cost\-model=dynamic \-ftree\-loop\-distribute\-patterns +\&\-fprofile\-correction\fR +.Sp +\&\fIpath\fR is the name of a file containing AutoFDO profile information. +If omitted, it defaults to \fIfbdata.afdo\fR in the current directory. +.Sp +Producing an AutoFDO profile data file requires running your program +with the \fBperf\fR utility on a supported GNU/Linux target system. +For more information, see <\fBhttps://perf.wiki.kernel.org/\fR>. +.Sp +E.g. +.Sp +.Vb 2 +\& perf record \-e br_inst_retired:near_taken \-b \-o perf.data \e +\& \-\- your_program +.Ve +.Sp +Then use the \fBcreate_gcov\fR tool to convert the raw profile data +to a format that can be used by \s-1GCC.\s0 You must also supply the +unstripped binary for your program to this tool. +See <\fBhttps://github.com/google/autofdo\fR>. +.Sp +E.g. +.Sp +.Vb 2 +\& create_gcov \-\-binary=your_program.unstripped \-\-profile=perf.data \e +\& \-\-gcov=profile.afdo +.Ve +.PP +The following options control compiler behavior regarding floating-point +arithmetic. These options trade off between speed and +correctness. All must be specifically enabled. +.IP "\fB\-ffloat\-store\fR" 4 +.IX Item "-ffloat-store" +Do not store floating-point variables in registers, and inhibit other +options that might change whether a floating-point value is taken from a +register or memory. +.Sp +This option prevents undesirable excess precision on machines such as +the 68000 where the floating registers (of the 68881) keep more +precision than a \f(CW\*(C`double\*(C'\fR is supposed to have. Similarly for the +x86 architecture. For most programs, the excess precision does only +good, but a few programs rely on the precise definition of \s-1IEEE\s0 floating +point. Use \fB\-ffloat\-store\fR for such programs, after modifying +them to store all pertinent intermediate computations into variables. +.IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 +.IX Item "-fexcess-precision=style" +This option allows further control over excess precision on machines +where floating-point operations occur in a format with more precision or +range than the \s-1IEEE\s0 standard and interchange floating-point types. By +default, \fB\-fexcess\-precision=fast\fR is in effect; this means that +operations may be carried out in a wider precision than the types specified +in the source if that would result in faster code, and it is unpredictable +when rounding to the types specified in the source code takes place. +When compiling C, if \fB\-fexcess\-precision=standard\fR is specified then +excess precision follows the rules specified in \s-1ISO C99\s0; in particular, +both casts and assignments cause values to be rounded to their +semantic types (whereas \fB\-ffloat\-store\fR only affects +assignments). This option is enabled by default for C if a strict +conformance option such as \fB\-std=c99\fR is used. +\&\fB\-ffast\-math\fR enables \fB\-fexcess\-precision=fast\fR by default +regardless of whether a strict conformance option is used. +.Sp +\&\fB\-fexcess\-precision=standard\fR is not implemented for languages +other than C. On the x86, it has no effect if \fB\-mfpmath=sse\fR +or \fB\-mfpmath=sse+387\fR is specified; in the former case, \s-1IEEE\s0 +semantics apply without excess precision, and in the latter, rounding +is unpredictable. +.IP "\fB\-ffast\-math\fR" 4 +.IX Item "-ffast-math" +Sets the options \fB\-fno\-math\-errno\fR, \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-ffinite\-math\-only\fR, \fB\-fno\-rounding\-math\fR, +\&\fB\-fno\-signaling\-nans\fR, \fB\-fcx\-limited\-range\fR and +\&\fB\-fexcess\-precision=fast\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined. +.Sp +This option is not turned on by any \fB\-O\fR option besides +\&\fB\-Ofast\fR since it can result in incorrect output for programs +that depend on an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications +for math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.IP "\fB\-fno\-math\-errno\fR" 4 +.IX Item "-fno-math-errno" +Do not set \f(CW\*(C`errno\*(C'\fR after calling math functions that are executed +with a single instruction, e.g., \f(CW\*(C`sqrt\*(C'\fR. A program that relies on +\&\s-1IEEE\s0 exceptions for math error handling may want to use this flag +for speed while maintaining \s-1IEEE\s0 arithmetic compatibility. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fmath\-errno\fR. +.Sp +On Darwin systems, the math library never sets \f(CW\*(C`errno\*(C'\fR. There is +therefore no reason for the compiler to consider the possibility that +it might, and \fB\-fno\-math\-errno\fR is the default. +.IP "\fB\-funsafe\-math\-optimizations\fR" 4 +.IX Item "-funsafe-math-optimizations" +Allow optimizations for floating-point arithmetic that (a) assume +that arguments and results are valid and (b) may violate \s-1IEEE\s0 or +\&\s-1ANSI\s0 standards. When used at link time, it may include libraries +or startup files that change the default \s-1FPU\s0 control word or other +similar optimizations. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +Enables \fB\-fno\-signed\-zeros\fR, \fB\-fno\-trapping\-math\fR, +\&\fB\-fassociative\-math\fR and \fB\-freciprocal\-math\fR. +.Sp +The default is \fB\-fno\-unsafe\-math\-optimizations\fR. +.IP "\fB\-fassociative\-math\fR" 4 +.IX Item "-fassociative-math" +Allow re-association of operands in series of floating-point operations. +This violates the \s-1ISO C\s0 and \*(C+ language standard by possibly changing +computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as +well as ignore NaNs and inhibit or create underflow or overflow (and +thus cannot be used on code that relies on rounding behavior like +\&\f(CW\*(C`(x + 2**52) \- 2**52\*(C'\fR. May also reorder floating-point comparisons +and thus may not be used when ordered comparisons are required. +This option requires that both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR be in effect. Moreover, it doesn't make +much sense with \fB\-frounding\-math\fR. For Fortran the option +is automatically enabled when both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR are in effect. +.Sp +The default is \fB\-fno\-associative\-math\fR. +.IP "\fB\-freciprocal\-math\fR" 4 +.IX Item "-freciprocal-math" +Allow the reciprocal of a value to be used instead of dividing by +the value if this enables optimizations. For example \f(CW\*(C`x / y\*(C'\fR +can be replaced with \f(CW\*(C`x * (1/y)\*(C'\fR, which is useful if \f(CW\*(C`(1/y)\*(C'\fR +is subject to common subexpression elimination. Note that this loses +precision and increases the number of flops operating on the value. +.Sp +The default is \fB\-fno\-reciprocal\-math\fR. +.IP "\fB\-ffinite\-math\-only\fR" 4 +.IX Item "-ffinite-math-only" +Allow optimizations for floating-point arithmetic that assume +that arguments and results are not NaNs or +\-Infs. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fno\-finite\-math\-only\fR. +.IP "\fB\-fno\-signed\-zeros\fR" 4 +.IX Item "-fno-signed-zeros" +Allow optimizations for floating-point arithmetic that ignore the +signedness of zero. \s-1IEEE\s0 arithmetic specifies the behavior of +distinct +0.0 and \-0.0 values, which then prohibits simplification +of expressions such as x+0.0 or 0.0*x (even with \fB\-ffinite\-math\-only\fR). +This option implies that the sign of a zero result isn't significant. +.Sp +The default is \fB\-fsigned\-zeros\fR. +.IP "\fB\-fno\-trapping\-math\fR" 4 +.IX Item "-fno-trapping-math" +Compile code assuming that floating-point operations cannot generate +user-visible traps. These traps include division by zero, overflow, +underflow, inexact result and invalid operation. This option requires +that \fB\-fno\-signaling\-nans\fR be in effect. Setting this option may +allow faster code if one relies on \*(L"non-stop\*(R" \s-1IEEE\s0 arithmetic, for example. +.Sp +This option should never be turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. +.Sp +The default is \fB\-ftrapping\-math\fR. +.IP "\fB\-frounding\-math\fR" 4 +.IX Item "-frounding-math" +Disable transformations and optimizations that assume default floating-point +rounding behavior. This is round-to-zero for all floating point +to integer conversions, and round-to-nearest for all other arithmetic +truncations. This option should be specified for programs that change +the \s-1FP\s0 rounding mode dynamically, or that may be executed with a +non-default rounding mode. This option disables constant folding of +floating-point expressions at compile time (which may be affected by +rounding mode) and arithmetic transformations that are unsafe in the +presence of sign-dependent rounding modes. +.Sp +The default is \fB\-fno\-rounding\-math\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that are affected by rounding mode. +Future versions of \s-1GCC\s0 may provide finer control of this setting +using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma. This command-line option +will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR. +.IP "\fB\-fsignaling\-nans\fR" 4 +.IX Item "-fsignaling-nans" +Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible +traps during floating-point operations. Setting this option disables +optimizations that may change the number of exceptions visible with +signaling NaNs. This option implies \fB\-ftrapping\-math\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_SUPPORT_SNAN_\|_\*(C'\fR to +be defined. +.Sp +The default is \fB\-fno\-signaling\-nans\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior. +.IP "\fB\-fno\-fp\-int\-builtin\-inexact\fR" 4 +.IX Item "-fno-fp-int-builtin-inexact" +Do not allow the built-in functions \f(CW\*(C`ceil\*(C'\fR, \f(CW\*(C`floor\*(C'\fR, +\&\f(CW\*(C`round\*(C'\fR and \f(CW\*(C`trunc\*(C'\fR, and their \f(CW\*(C`float\*(C'\fR and \f(CW\*(C`long +double\*(C'\fR variants, to generate code that raises the \*(L"inexact\*(R" +floating-point exception for noninteger arguments. \s-1ISO C99\s0 and C11 +allow these functions to raise the \*(L"inexact\*(R" exception, but \s-1ISO/IEC +TS 18661\-1:2014,\s0 the C bindings to \s-1IEEE 754\-2008,\s0 does not allow these +functions to do so. +.Sp +The default is \fB\-ffp\-int\-builtin\-inexact\fR, allowing the +exception to be raised. This option does nothing unless +\&\fB\-ftrapping\-math\fR is in effect. +.Sp +Even if \fB\-fno\-fp\-int\-builtin\-inexact\fR is used, if the functions +generate a call to a library function then the \*(L"inexact\*(R" exception +may be raised if the library implementation does not follow \s-1TS 18661.\s0 +.IP "\fB\-fsingle\-precision\-constant\fR" 4 +.IX Item "-fsingle-precision-constant" +Treat floating-point constants as single precision instead of +implicitly converting them to double-precision constants. +.IP "\fB\-fcx\-limited\-range\fR" 4 +.IX Item "-fcx-limited-range" +When enabled, this option states that a range reduction step is not +needed when performing complex division. Also, there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. The +default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by +\&\fB\-ffast\-math\fR. +.Sp +This option controls the default setting of the \s-1ISO C99\s0 +\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +all languages. +.IP "\fB\-fcx\-fortran\-rules\fR" 4 +.IX Item "-fcx-fortran-rules" +Complex multiplication and division follow Fortran rules. Range +reduction is done as part of complex division, but there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. +.Sp +The default is \fB\-fno\-cx\-fortran\-rules\fR. +.PP +The following options control optimizations that may improve +performance, but are not enabled by any \fB\-O\fR options. This +section includes experimental options that may produce broken code. +.IP "\fB\-fbranch\-probabilities\fR" 4 +.IX Item "-fbranch-probabilities" +After running a program compiled with \fB\-fprofile\-arcs\fR, +you can compile it a second time using +\&\fB\-fbranch\-probabilities\fR, to improve optimizations based on +the number of times each branch was taken. When a program +compiled with \fB\-fprofile\-arcs\fR exits, it saves arc execution +counts to a file called \fI\fIsourcename\fI.gcda\fR for each source +file. The information in this data file is very dependent on the +structure of the generated code, so you must use the same source code +and the same optimization options for both compilations. +.Sp +With \fB\-fbranch\-probabilities\fR, \s-1GCC\s0 puts a +\&\fB\s-1REG_BR_PROB\s0\fR note on each \fB\s-1JUMP_INSN\s0\fR and \fB\s-1CALL_INSN\s0\fR. +These can be used to improve optimization. Currently, they are only +used in one place: in \fIreorg.c\fR, instead of guessing which path a +branch is most likely to take, the \fB\s-1REG_BR_PROB\s0\fR values are used to +exactly determine which path is taken more often. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fprofile\-values\fR" 4 +.IX Item "-fprofile-values" +If combined with \fB\-fprofile\-arcs\fR, it adds code so that some +data about values of expressions in the program is gathered. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +from profiling values of expressions for usage in optimizations. +.Sp +Enabled by \fB\-fprofile\-generate\fR, \fB\-fprofile\-use\fR, and +\&\fB\-fauto\-profile\fR. +.IP "\fB\-fprofile\-reorder\-functions\fR" 4 +.IX Item "-fprofile-reorder-functions" +Function reordering based on profile instrumentation collects +first time of execution of a function and orders these functions +in ascending order. +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-fvpt\fR" 4 +.IX Item "-fvpt" +If combined with \fB\-fprofile\-arcs\fR, this option instructs the compiler +to add code to gather information about values of expressions. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +and actually performs the optimizations based on them. +Currently the optimizations include specialization of division operations +using the knowledge about the value of the denominator. +.Sp +Enabled with \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-frename\-registers\fR" 4 +.IX Item "-frename-registers" +Attempt to avoid false dependencies in scheduled code by making use +of registers left over after register allocation. This optimization +most benefits processors with lots of registers. Depending on the +debug information format adopted by the target, however, it can +make debugging impossible, since variables no longer stay in +a \*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR. +.IP "\fB\-fschedule\-fusion\fR" 4 +.IX Item "-fschedule-fusion" +Performs a target dependent pass over the instruction stream to schedule +instructions of same type together because target machine can execute them +more efficiently if they are adjacent to each other in the instruction flow. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-ftracer\fR" 4 +.IX Item "-ftracer" +Perform tail duplication to enlarge superblock size. This transformation +simplifies the control flow of the function allowing other optimizations to do +a better job. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-funroll\-loops\fR" 4 +.IX Item "-funroll-loops" +Unroll loops whose number of iterations can be determined at compile time or +upon entry to the loop. \fB\-funroll\-loops\fR implies +\&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR. +It also turns on complete loop peeling (i.e. complete removal of loops with +a small constant number of iterations). This option makes code larger, and may +or may not make it run faster. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-funroll\-all\-loops\fR" 4 +.IX Item "-funroll-all-loops" +Unroll all loops, even if their number of iterations is uncertain when +the loop is entered. This usually makes programs run more slowly. +\&\fB\-funroll\-all\-loops\fR implies the same options as +\&\fB\-funroll\-loops\fR. +.IP "\fB\-fpeel\-loops\fR" 4 +.IX Item "-fpeel-loops" +Peels loops for which there is enough information that they do not +roll much (from profile feedback or static analysis). It also turns on +complete loop peeling (i.e. complete removal of loops with small constant +number of iterations). +.Sp +Enabled by \fB\-O3\fR, \fB\-fprofile\-use\fR, and \fB\-fauto\-profile\fR. +.IP "\fB\-fmove\-loop\-invariants\fR" 4 +.IX Item "-fmove-loop-invariants" +Enables the loop invariant motion pass in the \s-1RTL\s0 loop optimizer. Enabled +at level \fB\-O1\fR and higher, except for \fB\-Og\fR. +.IP "\fB\-fsplit\-loops\fR" 4 +.IX Item "-fsplit-loops" +Split a loop into two if it contains a condition that's always true +for one side of the iteration space and false for the other. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-funswitch\-loops\fR" 4 +.IX Item "-funswitch-loops" +Move branches with loop invariant conditions out of the loop, with duplicates +of the loop on both branches (modified according to result of the condition). +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fversion\-loops\-for\-strides\fR" 4 +.IX Item "-fversion-loops-for-strides" +If a loop iterates over an array with a variable stride, create another +version of the loop that assumes the stride is always one. For example: +.Sp +.Vb 2 +\& for (int i = 0; i < n; ++i) +\& x[i * stride] = ...; +.Ve +.Sp +becomes: +.Sp +.Vb 6 +\& if (stride == 1) +\& for (int i = 0; i < n; ++i) +\& x[i] = ...; +\& else +\& for (int i = 0; i < n; ++i) +\& x[i * stride] = ...; +.Ve +.Sp +This is particularly useful for assumed-shape arrays in Fortran where +(for example) it allows better vectorization assuming contiguous accesses. +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-ffunction\-sections\fR" 4 +.IX Item "-ffunction-sections" +.PD 0 +.IP "\fB\-fdata\-sections\fR" 4 +.IX Item "-fdata-sections" +.PD +Place each function or data item into its own section in the output +file if the target supports arbitrary sections. The name of the +function or the name of the data item determines the section's name +in the output file. +.Sp +Use these options on systems where the linker can perform optimizations to +improve locality of reference in the instruction space. Most systems using the +\&\s-1ELF\s0 object format have linkers with such optimizations. On \s-1AIX,\s0 the linker +rearranges sections (CSECTs) based on the call graph. The performance impact +varies. +.Sp +Together with a linker garbage collection (linker \fB\-\-gc\-sections\fR +option) these options may lead to smaller statically-linked executables (after +stripping). +.Sp +On \s-1ELF/DWARF\s0 systems these options do not degenerate the quality of the debug +information. There could be issues with other object files/debug info formats. +.Sp +Only use these options when there are significant benefits from doing so. When +you specify these options, the assembler and linker create larger object and +executable files and are also slower. These options affect code generation. +They prevent optimizations by the compiler and assembler using relative +locations inside a translation unit since the locations are unknown until +link time. An example of such an optimization is relaxing calls to short call +instructions. +.IP "\fB\-fbranch\-target\-load\-optimize\fR" 4 +.IX Item "-fbranch-target-load-optimize" +Perform branch target register load optimization before prologue / epilogue +threading. +The use of target registers can typically be exposed only during reload, +thus hoisting loads out of loops and doing inter-block scheduling needs +a separate optimization pass. +.IP "\fB\-fbranch\-target\-load\-optimize2\fR" 4 +.IX Item "-fbranch-target-load-optimize2" +Perform branch target register load optimization after prologue / epilogue +threading. +.IP "\fB\-fbtr\-bb\-exclusive\fR" 4 +.IX Item "-fbtr-bb-exclusive" +When performing branch target register load optimization, don't reuse +branch target registers within any basic block. +.IP "\fB\-fstdarg\-opt\fR" 4 +.IX Item "-fstdarg-opt" +Optimize the prologue of variadic argument functions with respect to usage of +those arguments. +.IP "\fB\-fsection\-anchors\fR" 4 +.IX Item "-fsection-anchors" +Try to reduce the number of symbolic address calculations by using +shared \*(L"anchor\*(R" symbols to address nearby objects. This transformation +can help to reduce the number of \s-1GOT\s0 entries and \s-1GOT\s0 accesses on some +targets. +.Sp +For example, the implementation of the following function \f(CW\*(C`foo\*(C'\fR: +.Sp +.Vb 2 +\& static int a, b, c; +\& int foo (void) { return a + b + c; } +.Ve +.Sp +usually calculates the addresses of all three variables, but if you +compile it with \fB\-fsection\-anchors\fR, it accesses the variables +from a common anchor point instead. The effect is similar to the +following pseudocode (which isn't valid C): +.Sp +.Vb 5 +\& int foo (void) +\& { +\& register int *xr = &x; +\& return xr[&a \- &x] + xr[&b \- &x] + xr[&c \- &x]; +\& } +.Ve +.Sp +Not all targets support this option. +.IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "--param name=value" +In some places, \s-1GCC\s0 uses various constants to control the amount of +optimization that is done. For example, \s-1GCC\s0 does not inline functions +that contain more than a certain number of instructions. You can +control some of these constants on the command line using the +\&\fB\-\-param\fR option. +.Sp +The names of specific parameters, and the meaning of the values, are +tied to the internals of the compiler, and are subject to change +without notice in future releases. +.Sp +In order to get minimal, maximal and default value of a parameter, +one can use \fB\-\-help=param \-Q\fR options. +.Sp +In each case, the \fIvalue\fR is an integer. The allowable choices for +\&\fIname\fR are: +.RS 4 +.IP "\fBpredictable-branch-outcome\fR" 4 +.IX Item "predictable-branch-outcome" +When branch is predicted to be taken with probability lower than this threshold +(in percent), then it is considered well predictable. +.IP "\fBmax-rtl-if-conversion-insns\fR" 4 +.IX Item "max-rtl-if-conversion-insns" +\&\s-1RTL\s0 if-conversion tries to remove conditional branches around a block and +replace them with conditionally executed instructions. This parameter +gives the maximum number of instructions in a block which should be +considered for if-conversion. The compiler will +also use other heuristics to decide whether if-conversion is likely to be +profitable. +.IP "\fBmax-rtl-if-conversion-predictable-cost\fR" 4 +.IX Item "max-rtl-if-conversion-predictable-cost" +.PD 0 +.IP "\fBmax-rtl-if-conversion-unpredictable-cost\fR" 4 +.IX Item "max-rtl-if-conversion-unpredictable-cost" +.PD +\&\s-1RTL\s0 if-conversion will try to remove conditional branches around a block +and replace them with conditionally executed instructions. These parameters +give the maximum permissible cost for the sequence that would be generated +by if-conversion depending on whether the branch is statically determined +to be predictable or not. The units for this parameter are the same as +those for the \s-1GCC\s0 internal seq_cost metric. The compiler will try to +provide a reasonable default for this parameter using the \s-1BRANCH_COST\s0 +target macro. +.IP "\fBmax-crossjump-edges\fR" 4 +.IX Item "max-crossjump-edges" +The maximum number of incoming edges to consider for cross-jumping. +The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in +the number of edges incoming to each block. Increasing values mean +more aggressive optimization, making the compilation time increase with +probably small improvement in executable size. +.IP "\fBmin-crossjump-insns\fR" 4 +.IX Item "min-crossjump-insns" +The minimum number of instructions that must be matched at the end +of two blocks before cross-jumping is performed on them. This +value is ignored in the case where all instructions in the block being +cross-jumped from are matched. +.IP "\fBmax-grow-copy-bb-insns\fR" 4 +.IX Item "max-grow-copy-bb-insns" +The maximum code size expansion factor when copying basic blocks +instead of jumping. The expansion is relative to a jump instruction. +.IP "\fBmax-goto-duplication-insns\fR" 4 +.IX Item "max-goto-duplication-insns" +The maximum number of instructions to duplicate to a block that jumps +to a computed goto. To avoid O(N^2) behavior in a number of +passes, \s-1GCC\s0 factors computed gotos early in the compilation process, +and unfactors them as late as possible. Only computed jumps at the +end of a basic blocks with no more than max-goto-duplication-insns are +unfactored. +.IP "\fBmax-delay-slot-insn-search\fR" 4 +.IX Item "max-delay-slot-insn-search" +The maximum number of instructions to consider when looking for an +instruction to fill a delay slot. If more than this arbitrary number of +instructions are searched, the time savings from filling the delay slot +are minimal, so stop searching. Increasing values mean more +aggressive optimization, making the compilation time increase with probably +small improvement in execution time. +.IP "\fBmax-delay-slot-live-search\fR" 4 +.IX Item "max-delay-slot-live-search" +When trying to fill delay slots, the maximum number of instructions to +consider when searching for a block with valid live register +information. Increasing this arbitrarily chosen value means more +aggressive optimization, increasing the compilation time. This parameter +should be removed when the delay slot code is rewritten to maintain the +control-flow graph. +.IP "\fBmax-gcse-memory\fR" 4 +.IX Item "max-gcse-memory" +The approximate maximum amount of memory that can be allocated in +order to perform the global common subexpression elimination +optimization. If more memory than specified is required, the +optimization is not done. +.IP "\fBmax-gcse-insertion-ratio\fR" 4 +.IX Item "max-gcse-insertion-ratio" +If the ratio of expression insertions to deletions is larger than this value +for any expression, then \s-1RTL PRE\s0 inserts or removes the expression and thus +leaves partially redundant computations in the instruction stream. +.IP "\fBmax-pending-list-length\fR" 4 +.IX Item "max-pending-list-length" +The maximum number of pending dependencies scheduling allows +before flushing the current state and starting over. Large functions +with few branches or calls can create excessively large lists which +needlessly consume memory and resources. +.IP "\fBmax-modulo-backtrack-attempts\fR" 4 +.IX Item "max-modulo-backtrack-attempts" +The maximum number of backtrack attempts the scheduler should make +when modulo scheduling a loop. Larger values can exponentially increase +compilation time. +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +Several parameters control the tree inliner used in \s-1GCC.\s0 +This number sets the maximum number of instructions (counted in \s-1GCC\s0's +internal representation) in a single function that the tree inliner +considers for inlining. This only affects functions declared +inline and methods implemented in a class declaration (\*(C+). +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR), +a lot of functions that would otherwise not be considered for inlining +by the compiler are investigated. To those functions, a different +(more restrictive) limit compared to functions declared inline can +be applied. +.IP "\fBmax-inline-insns-small\fR" 4 +.IX Item "max-inline-insns-small" +This is bound applied to calls which are considered relevant with +\&\fB\-finline\-small\-functions\fR. +.IP "\fBmax-inline-insns-size\fR" 4 +.IX Item "max-inline-insns-size" +This is bound applied to calls which are optimized for size. Small growth +may be desirable to anticipate optimization oppurtunities exposed by inlining. +.IP "\fBuninlined-function-insns\fR" 4 +.IX Item "uninlined-function-insns" +Number of instructions accounted by inliner for function overhead such as +function prologue and epilogue. +.IP "\fBuninlined-function-time\fR" 4 +.IX Item "uninlined-function-time" +Extra time accounted by inliner for function overhead such as time needed to +execute function prologue and epilogue +.IP "\fBuninlined-thunk-insns\fR" 4 +.IX Item "uninlined-thunk-insns" +.PD 0 +.IP "\fBuninlined-thunk-time\fR" 4 +.IX Item "uninlined-thunk-time" +.PD +Same as \fB\-\-param uninlined-function-insns\fR and +\&\fB\-\-param uninlined-function-time\fR but applied to function thunks +.IP "\fBinline-min-speedup\fR" 4 +.IX Item "inline-min-speedup" +When estimated performance improvement of caller + callee runtime exceeds this +threshold (in percent), the function can be inlined regardless of the limit on +\&\fB\-\-param max-inline-insns-single\fR and \fB\-\-param +max-inline-insns-auto\fR. +.IP "\fBlarge-function-insns\fR" 4 +.IX Item "large-function-insns" +The limit specifying really large functions. For functions larger than this +limit after inlining, inlining is constrained by +\&\fB\-\-param large-function-growth\fR. This parameter is useful primarily +to avoid extreme compilation time caused by non-linear algorithms used by the +back end. +.IP "\fBlarge-function-growth\fR" 4 +.IX Item "large-function-growth" +Specifies maximal growth of large function caused by inlining in percents. +For example, parameter value 100 limits large function growth to 2.0 times +the original size. +.IP "\fBlarge-unit-insns\fR" 4 +.IX Item "large-unit-insns" +The limit specifying large translation unit. Growth caused by inlining of +units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR. +For small units this might be too tight. +For example, consider a unit consisting of function A +that is inline and B that just calls A three times. If B is small relative to +A, the growth of unit is 300\e% and yet such inlining is very sane. For very +large units consisting of small inlineable functions, however, the overall unit +growth limit is needed to avoid exponential explosion of code size. Thus for +smaller units, the size is increased to \fB\-\-param large-unit-insns\fR +before applying \fB\-\-param inline-unit-growth\fR. +.IP "\fBinline-unit-growth\fR" 4 +.IX Item "inline-unit-growth" +Specifies maximal overall growth of the compilation unit caused by inlining. +For example, parameter value 20 limits unit growth to 1.2 times the original +size. Cold functions (either marked cold via an attribute or by profile +feedback) are not accounted into the unit size. +.IP "\fBipcp-unit-growth\fR" 4 +.IX Item "ipcp-unit-growth" +Specifies maximal overall growth of the compilation unit caused by +interprocedural constant propagation. For example, parameter value 10 limits +unit growth to 1.1 times the original size. +.IP "\fBlarge-stack-frame\fR" 4 +.IX Item "large-stack-frame" +The limit specifying large stack frames. While inlining the algorithm is trying +to not grow past this limit too much. +.IP "\fBlarge-stack-frame-growth\fR" 4 +.IX Item "large-stack-frame-growth" +Specifies maximal growth of large stack frames caused by inlining in percents. +For example, parameter value 1000 limits large stack frame growth to 11 times +the original size. +.IP "\fBmax-inline-insns-recursive\fR" 4 +.IX Item "max-inline-insns-recursive" +.PD 0 +.IP "\fBmax-inline-insns-recursive-auto\fR" 4 +.IX Item "max-inline-insns-recursive-auto" +.PD +Specifies the maximum number of instructions an out-of-line copy of a +self-recursive inline +function can grow into by performing recursive inlining. +.Sp +\&\fB\-\-param max-inline-insns-recursive\fR applies to functions +declared inline. +For functions not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled; \fB\-\-param max-inline-insns-recursive-auto\fR applies instead. +.IP "\fBmax-inline-recursive-depth\fR" 4 +.IX Item "max-inline-recursive-depth" +.PD 0 +.IP "\fBmax-inline-recursive-depth-auto\fR" 4 +.IX Item "max-inline-recursive-depth-auto" +.PD +Specifies the maximum recursion depth used for recursive inlining. +.Sp +\&\fB\-\-param max-inline-recursive-depth\fR applies to functions +declared inline. For functions not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled; \fB\-\-param max-inline-recursive-depth-auto\fR applies instead. +.IP "\fBmin-inline-recursive-probability\fR" 4 +.IX Item "min-inline-recursive-probability" +Recursive inlining is profitable only for function having deep recursion +in average and can hurt for function having little recursion depth by +increasing the prologue size or complexity of function body to other +optimizers. +.Sp +When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual +recursion depth can be guessed from the probability that function recurses +via a given call expression. This parameter limits inlining only to call +expressions whose probability exceeds the given threshold (in percents). +.IP "\fBearly-inlining-insns\fR" 4 +.IX Item "early-inlining-insns" +Specify growth that the early inliner can make. In effect it increases +the amount of inlining for code having a large abstraction penalty. +.IP "\fBmax-early-inliner-iterations\fR" 4 +.IX Item "max-early-inliner-iterations" +Limit of iterations of the early inliner. This basically bounds +the number of nested indirect calls the early inliner can resolve. +Deeper chains are still handled by late inlining. +.IP "\fBcomdat-sharing-probability\fR" 4 +.IX Item "comdat-sharing-probability" +Probability (in percent) that \*(C+ inline function with comdat visibility +are shared across multiple compilation units. +.IP "\fBprofile-func-internal-id\fR" 4 +.IX Item "profile-func-internal-id" +A parameter to control whether to use function internal id in profile +database lookup. If the value is 0, the compiler uses an id that +is based on function assembler name and filename, which makes old profile +data more tolerant to source changes such as function reordering etc. +.IP "\fBmin-vect-loop-bound\fR" 4 +.IX Item "min-vect-loop-bound" +The minimum number of iterations under which loops are not vectorized +when \fB\-ftree\-vectorize\fR is used. The number of iterations after +vectorization needs to be greater than the value specified by this option +to allow vectorization. +.IP "\fBgcse-cost-distance-ratio\fR" 4 +.IX Item "gcse-cost-distance-ratio" +Scaling factor in calculation of maximum distance an expression +can be moved by \s-1GCSE\s0 optimizations. This is currently supported only in the +code hoisting pass. The bigger the ratio, the more aggressive code hoisting +is with simple expressions, i.e., the expressions that have cost +less than \fBgcse-unrestricted-cost\fR. Specifying 0 disables +hoisting of simple expressions. +.IP "\fBgcse-unrestricted-cost\fR" 4 +.IX Item "gcse-unrestricted-cost" +Cost, roughly measured as the cost of a single typical machine +instruction, at which \s-1GCSE\s0 optimizations do not constrain +the distance an expression can travel. This is currently +supported only in the code hoisting pass. The lesser the cost, +the more aggressive code hoisting is. Specifying 0 +allows all expressions to travel unrestricted distances. +.IP "\fBmax-hoist-depth\fR" 4 +.IX Item "max-hoist-depth" +The depth of search in the dominator tree for expressions to hoist. +This is used to avoid quadratic behavior in hoisting algorithm. +The value of 0 does not limit on the search, but may slow down compilation +of huge functions. +.IP "\fBmax-tail-merge-comparisons\fR" 4 +.IX Item "max-tail-merge-comparisons" +The maximum amount of similar bbs to compare a bb with. This is used to +avoid quadratic behavior in tree tail merging. +.IP "\fBmax-tail-merge-iterations\fR" 4 +.IX Item "max-tail-merge-iterations" +The maximum amount of iterations of the pass over the function. This is used to +limit compilation time in tree tail merging. +.IP "\fBstore-merging-allow-unaligned\fR" 4 +.IX Item "store-merging-allow-unaligned" +Allow the store merging pass to introduce unaligned stores if it is legal to +do so. +.IP "\fBmax-stores-to-merge\fR" 4 +.IX Item "max-stores-to-merge" +The maximum number of stores to attempt to merge into wider stores in the store +merging pass. +.IP "\fBmax-unrolled-insns\fR" 4 +.IX Item "max-unrolled-insns" +The maximum number of instructions that a loop may have to be unrolled. +If a loop is unrolled, this parameter also determines how many times +the loop code is unrolled. +.IP "\fBmax-average-unrolled-insns\fR" 4 +.IX Item "max-average-unrolled-insns" +The maximum number of instructions biased by probabilities of their execution +that a loop may have to be unrolled. If a loop is unrolled, +this parameter also determines how many times the loop code is unrolled. +.IP "\fBmax-unroll-times\fR" 4 +.IX Item "max-unroll-times" +The maximum number of unrollings of a single loop. +.IP "\fBmax-peeled-insns\fR" 4 +.IX Item "max-peeled-insns" +The maximum number of instructions that a loop may have to be peeled. +If a loop is peeled, this parameter also determines how many times +the loop code is peeled. +.IP "\fBmax-peel-times\fR" 4 +.IX Item "max-peel-times" +The maximum number of peelings of a single loop. +.IP "\fBmax-peel-branches\fR" 4 +.IX Item "max-peel-branches" +The maximum number of branches on the hot path through the peeled sequence. +.IP "\fBmax-completely-peeled-insns\fR" 4 +.IX Item "max-completely-peeled-insns" +The maximum number of insns of a completely peeled loop. +.IP "\fBmax-completely-peel-times\fR" 4 +.IX Item "max-completely-peel-times" +The maximum number of iterations of a loop to be suitable for complete peeling. +.IP "\fBmax-completely-peel-loop-nest-depth\fR" 4 +.IX Item "max-completely-peel-loop-nest-depth" +The maximum depth of a loop nest suitable for complete peeling. +.IP "\fBmax-unswitch-insns\fR" 4 +.IX Item "max-unswitch-insns" +The maximum number of insns of an unswitched loop. +.IP "\fBmax-unswitch-level\fR" 4 +.IX Item "max-unswitch-level" +The maximum number of branches unswitched in a single loop. +.IP "\fBlim-expensive\fR" 4 +.IX Item "lim-expensive" +The minimum cost of an expensive expression in the loop invariant motion. +.IP "\fBiv-consider-all-candidates-bound\fR" 4 +.IX Item "iv-consider-all-candidates-bound" +Bound on number of candidates for induction variables, below which +all candidates are considered for each use in induction variable +optimizations. If there are more candidates than this, +only the most relevant ones are considered to avoid quadratic time complexity. +.IP "\fBiv-max-considered-uses\fR" 4 +.IX Item "iv-max-considered-uses" +The induction variable optimizations give up on loops that contain more +induction variable uses. +.IP "\fBiv-always-prune-cand-set-bound\fR" 4 +.IX Item "iv-always-prune-cand-set-bound" +If the number of candidates in the set is smaller than this value, +always try to remove unnecessary ivs from the set +when adding a new one. +.IP "\fBavg-loop-niter\fR" 4 +.IX Item "avg-loop-niter" +Average number of iterations of a loop. +.IP "\fBdse-max-object-size\fR" 4 +.IX Item "dse-max-object-size" +Maximum size (in bytes) of objects tracked bytewise by dead store elimination. +Larger values may result in larger compilation times. +.IP "\fBdse-max-alias-queries-per-store\fR" 4 +.IX Item "dse-max-alias-queries-per-store" +Maximum number of queries into the alias oracle per store. +Larger values result in larger compilation times and may result in more +removed dead stores. +.IP "\fBscev-max-expr-size\fR" 4 +.IX Item "scev-max-expr-size" +Bound on size of expressions used in the scalar evolutions analyzer. +Large expressions slow the analyzer. +.IP "\fBscev-max-expr-complexity\fR" 4 +.IX Item "scev-max-expr-complexity" +Bound on the complexity of the expressions in the scalar evolutions analyzer. +Complex expressions slow the analyzer. +.IP "\fBmax-tree-if-conversion-phi-args\fR" 4 +.IX Item "max-tree-if-conversion-phi-args" +Maximum number of arguments in a \s-1PHI\s0 supported by \s-1TREE\s0 if conversion +unless the loop is marked with simd pragma. +.IP "\fBvect-max-version-for-alignment-checks\fR" 4 +.IX Item "vect-max-version-for-alignment-checks" +The maximum number of run-time checks that can be performed when +doing loop versioning for alignment in the vectorizer. +.IP "\fBvect-max-version-for-alias-checks\fR" 4 +.IX Item "vect-max-version-for-alias-checks" +The maximum number of run-time checks that can be performed when +doing loop versioning for alias in the vectorizer. +.IP "\fBvect-max-peeling-for-alignment\fR" 4 +.IX Item "vect-max-peeling-for-alignment" +The maximum number of loop peels to enhance access alignment +for vectorizer. Value \-1 means no limit. +.IP "\fBmax-iterations-to-track\fR" 4 +.IX Item "max-iterations-to-track" +The maximum number of iterations of a loop the brute-force algorithm +for analysis of the number of iterations of the loop tries to evaluate. +.IP "\fBhot-bb-count-ws-permille\fR" 4 +.IX Item "hot-bb-count-ws-permille" +A basic block profile count is considered hot if it contributes to +the given permillage (i.e. 0...1000) of the entire profiled execution. +.IP "\fBhot-bb-frequency-fraction\fR" 4 +.IX Item "hot-bb-frequency-fraction" +Select fraction of the entry block frequency of executions of basic block in +function given basic block needs to have to be considered hot. +.IP "\fBmax-predicted-iterations\fR" 4 +.IX Item "max-predicted-iterations" +The maximum number of loop iterations we predict statically. This is useful +in cases where a function contains a single loop with known bound and +another loop with unknown bound. +The known number of iterations is predicted correctly, while +the unknown number of iterations average to roughly 10. This means that the +loop without bounds appears artificially cold relative to the other one. +.IP "\fBbuiltin-expect-probability\fR" 4 +.IX Item "builtin-expect-probability" +Control the probability of the expression having the specified value. This +parameter takes a percentage (i.e. 0 ... 100) as input. +.IP "\fBbuiltin-string-cmp-inline-length\fR" 4 +.IX Item "builtin-string-cmp-inline-length" +The maximum length of a constant string for a builtin string cmp call +eligible for inlining. +.IP "\fBalign-threshold\fR" 4 +.IX Item "align-threshold" +Select fraction of the maximal frequency of executions of a basic block in +a function to align the basic block. +.IP "\fBalign-loop-iterations\fR" 4 +.IX Item "align-loop-iterations" +A loop expected to iterate at least the selected number of iterations is +aligned. +.IP "\fBtracer-dynamic-coverage\fR" 4 +.IX Item "tracer-dynamic-coverage" +.PD 0 +.IP "\fBtracer-dynamic-coverage-feedback\fR" 4 +.IX Item "tracer-dynamic-coverage-feedback" +.PD +This value is used to limit superblock formation once the given percentage of +executed instructions is covered. This limits unnecessary code size +expansion. +.Sp +The \fBtracer-dynamic-coverage-feedback\fR parameter +is used only when profile +feedback is available. The real profiles (as opposed to statically estimated +ones) are much less balanced allowing the threshold to be larger value. +.IP "\fBtracer-max-code-growth\fR" 4 +.IX Item "tracer-max-code-growth" +Stop tail duplication once code growth has reached given percentage. This is +a rather artificial limit, as most of the duplicates are eliminated later in +cross jumping, so it may be set to much higher values than is the desired code +growth. +.IP "\fBtracer-min-branch-ratio\fR" 4 +.IX Item "tracer-min-branch-ratio" +Stop reverse growth when the reverse probability of best edge is less than this +threshold (in percent). +.IP "\fBtracer-min-branch-probability\fR" 4 +.IX Item "tracer-min-branch-probability" +.PD 0 +.IP "\fBtracer-min-branch-probability-feedback\fR" 4 +.IX Item "tracer-min-branch-probability-feedback" +.PD +Stop forward growth if the best edge has probability lower than this +threshold. +.Sp +Similarly to \fBtracer-dynamic-coverage\fR two parameters are +provided. \fBtracer-min-branch-probability-feedback\fR is used for +compilation with profile feedback and \fBtracer-min-branch-probability\fR +compilation without. The value for compilation with profile feedback +needs to be more conservative (higher) in order to make tracer +effective. +.IP "\fBstack-clash-protection-guard-size\fR" 4 +.IX Item "stack-clash-protection-guard-size" +Specify the size of the operating system provided stack guard as +2 raised to \fInum\fR bytes. Higher values may reduce the +number of explicit probes, but a value larger than the operating system +provided guard will leave code vulnerable to stack clash style attacks. +.IP "\fBstack-clash-protection-probe-interval\fR" 4 +.IX Item "stack-clash-protection-probe-interval" +Stack clash protection involves probing stack space as it is allocated. This +param controls the maximum distance between probes into the stack as 2 raised +to \fInum\fR bytes. Higher values may reduce the number of explicit probes, but a value +larger than the operating system provided guard will leave code vulnerable to +stack clash style attacks. +.IP "\fBmax-cse-path-length\fR" 4 +.IX Item "max-cse-path-length" +The maximum number of basic blocks on path that \s-1CSE\s0 considers. +.IP "\fBmax-cse-insns\fR" 4 +.IX Item "max-cse-insns" +The maximum number of instructions \s-1CSE\s0 processes before flushing. +.IP "\fBggc-min-expand\fR" 4 +.IX Item "ggc-min-expand" +\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This +parameter specifies the minimum percentage by which the garbage +collector's heap should be allowed to expand between collections. +Tuning this may improve compilation speed; it has no effect on code +generation. +.Sp +The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when +\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\*(R"\s0 is +the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If +\&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower +bound of 30% is used. Setting this parameter and +\&\fBggc-min-heapsize\fR to zero causes a full collection to occur at +every opportunity. This is extremely slow, but can be useful for +debugging. +.IP "\fBggc-min-heapsize\fR" 4 +.IX Item "ggc-min-heapsize" +Minimum size of the garbage collector's heap before it begins bothering +to collect garbage. The first collection occurs after the heap expands +by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, +tuning this may improve compilation speed, and has no effect on code +generation. +.Sp +The default is the smaller of \s-1RAM/8, RLIMIT_RSS,\s0 or a limit that +tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but +with a lower bound of 4096 (four megabytes) and an upper bound of +131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a +particular platform, the lower bound is used. Setting this parameter +very large effectively disables garbage collection. Setting this +parameter and \fBggc-min-expand\fR to zero causes a full collection +to occur at every opportunity. +.IP "\fBmax-reload-search-insns\fR" 4 +.IX Item "max-reload-search-insns" +The maximum number of instruction reload should look backward for equivalent +register. Increasing values mean more aggressive optimization, making the +compilation time increase with probably slightly better performance. +.IP "\fBmax-cselib-memory-locations\fR" 4 +.IX Item "max-cselib-memory-locations" +The maximum number of memory locations cselib should take into account. +Increasing values mean more aggressive optimization, making the compilation time +increase with probably slightly better performance. +.IP "\fBmax-sched-ready-insns\fR" 4 +.IX Item "max-sched-ready-insns" +The maximum number of instructions ready to be issued the scheduler should +consider at any given time during the first scheduling pass. Increasing +values mean more thorough searches, making the compilation time increase +with probably little benefit. +.IP "\fBmax-sched-region-blocks\fR" 4 +.IX Item "max-sched-region-blocks" +The maximum number of blocks in a region to be considered for +interblock scheduling. +.IP "\fBmax-pipeline-region-blocks\fR" 4 +.IX Item "max-pipeline-region-blocks" +The maximum number of blocks in a region to be considered for +pipelining in the selective scheduler. +.IP "\fBmax-sched-region-insns\fR" 4 +.IX Item "max-sched-region-insns" +The maximum number of insns in a region to be considered for +interblock scheduling. +.IP "\fBmax-pipeline-region-insns\fR" 4 +.IX Item "max-pipeline-region-insns" +The maximum number of insns in a region to be considered for +pipelining in the selective scheduler. +.IP "\fBmin-spec-prob\fR" 4 +.IX Item "min-spec-prob" +The minimum probability (in percents) of reaching a source block +for interblock speculative scheduling. +.IP "\fBmax-sched-extend-regions-iters\fR" 4 +.IX Item "max-sched-extend-regions-iters" +The maximum number of iterations through \s-1CFG\s0 to extend regions. +A value of 0 disables region extensions. +.IP "\fBmax-sched-insn-conflict-delay\fR" 4 +.IX Item "max-sched-insn-conflict-delay" +The maximum conflict delay for an insn to be considered for speculative motion. +.IP "\fBsched-spec-prob-cutoff\fR" 4 +.IX Item "sched-spec-prob-cutoff" +The minimal probability of speculation success (in percents), so that +speculative insns are scheduled. +.IP "\fBsched-state-edge-prob-cutoff\fR" 4 +.IX Item "sched-state-edge-prob-cutoff" +The minimum probability an edge must have for the scheduler to save its +state across it. +.IP "\fBsched-mem-true-dep-cost\fR" 4 +.IX Item "sched-mem-true-dep-cost" +Minimal distance (in \s-1CPU\s0 cycles) between store and load targeting same +memory locations. +.IP "\fBselsched-max-lookahead\fR" 4 +.IX Item "selsched-max-lookahead" +The maximum size of the lookahead window of selective scheduling. It is a +depth of search for available instructions. +.IP "\fBselsched-max-sched-times\fR" 4 +.IX Item "selsched-max-sched-times" +The maximum number of times that an instruction is scheduled during +selective scheduling. This is the limit on the number of iterations +through which the instruction may be pipelined. +.IP "\fBselsched-insns-to-rename\fR" 4 +.IX Item "selsched-insns-to-rename" +The maximum number of best instructions in the ready list that are considered +for renaming in the selective scheduler. +.IP "\fBsms-min-sc\fR" 4 +.IX Item "sms-min-sc" +The minimum value of stage count that swing modulo scheduler +generates. +.IP "\fBmax-last-value-rtl\fR" 4 +.IX Item "max-last-value-rtl" +The maximum size measured as number of RTLs that can be recorded in an expression +in combiner for a pseudo register as last known value of that register. +.IP "\fBmax-combine-insns\fR" 4 +.IX Item "max-combine-insns" +The maximum number of instructions the \s-1RTL\s0 combiner tries to combine. +.IP "\fBinteger-share-limit\fR" 4 +.IX Item "integer-share-limit" +Small integer constants can use a shared data structure, reducing the +compiler's memory usage and increasing its speed. This sets the maximum +value of a shared integer constant. +.IP "\fBssp-buffer-size\fR" 4 +.IX Item "ssp-buffer-size" +The minimum size of buffers (i.e. arrays) that receive stack smashing +protection when \fB\-fstack\-protection\fR is used. +.IP "\fBmin-size-for-stack-sharing\fR" 4 +.IX Item "min-size-for-stack-sharing" +The minimum size of variables taking part in stack slot sharing when not +optimizing. +.IP "\fBmax-jump-thread-duplication-stmts\fR" 4 +.IX Item "max-jump-thread-duplication-stmts" +Maximum number of statements allowed in a block that needs to be +duplicated when threading jumps. +.IP "\fBmax-fields-for-field-sensitive\fR" 4 +.IX Item "max-fields-for-field-sensitive" +Maximum number of fields in a structure treated in +a field sensitive manner during pointer analysis. +.IP "\fBprefetch-latency\fR" 4 +.IX Item "prefetch-latency" +Estimate on average number of instructions that are executed before +prefetch finishes. The distance prefetched ahead is proportional +to this constant. Increasing this number may also lead to less +streams being prefetched (see \fBsimultaneous-prefetches\fR). +.IP "\fBsimultaneous-prefetches\fR" 4 +.IX Item "simultaneous-prefetches" +Maximum number of prefetches that can run at the same time. +.IP "\fBl1\-cache\-line\-size\fR" 4 +.IX Item "l1-cache-line-size" +The size of cache line in L1 data cache, in bytes. +.IP "\fBl1\-cache\-size\fR" 4 +.IX Item "l1-cache-size" +The size of L1 data cache, in kilobytes. +.IP "\fBl2\-cache\-size\fR" 4 +.IX Item "l2-cache-size" +The size of L2 data cache, in kilobytes. +.IP "\fBprefetch-dynamic-strides\fR" 4 +.IX Item "prefetch-dynamic-strides" +Whether the loop array prefetch pass should issue software prefetch hints +for strides that are non-constant. In some cases this may be +beneficial, though the fact the stride is non-constant may make it +hard to predict when there is clear benefit to issuing these hints. +.Sp +Set to 1 if the prefetch hints should be issued for non-constant +strides. Set to 0 if prefetch hints should be issued only for strides that +are known to be constant and below \fBprefetch-minimum-stride\fR. +.IP "\fBprefetch-minimum-stride\fR" 4 +.IX Item "prefetch-minimum-stride" +Minimum constant stride, in bytes, to start using prefetch hints for. If +the stride is less than this threshold, prefetch hints will not be issued. +.Sp +This setting is useful for processors that have hardware prefetchers, in +which case there may be conflicts between the hardware prefetchers and +the software prefetchers. If the hardware prefetchers have a maximum +stride they can handle, it should be used here to improve the use of +software prefetchers. +.Sp +A value of \-1 means we don't have a threshold and therefore +prefetch hints can be issued for any constant stride. +.Sp +This setting is only useful for strides that are known and constant. +.IP "\fBloop-interchange-max-num-stmts\fR" 4 +.IX Item "loop-interchange-max-num-stmts" +The maximum number of stmts in a loop to be interchanged. +.IP "\fBloop-interchange-stride-ratio\fR" 4 +.IX Item "loop-interchange-stride-ratio" +The minimum ratio between stride of two loops for interchange to be profitable. +.IP "\fBmin-insn-to-prefetch-ratio\fR" 4 +.IX Item "min-insn-to-prefetch-ratio" +The minimum ratio between the number of instructions and the +number of prefetches to enable prefetching in a loop. +.IP "\fBprefetch-min-insn-to-mem-ratio\fR" 4 +.IX Item "prefetch-min-insn-to-mem-ratio" +The minimum ratio between the number of instructions and the +number of memory references to enable prefetching in a loop. +.IP "\fBuse-canonical-types\fR" 4 +.IX Item "use-canonical-types" +Whether the compiler should use the \*(L"canonical\*(R" type system. +Should always be 1, which uses a more efficient internal +mechanism for comparing types in \*(C+ and Objective\-\*(C+. However, if +bugs in the canonical type system are causing compilation failures, +set this value to 0 to disable canonical types. +.IP "\fBswitch-conversion-max-branch-ratio\fR" 4 +.IX Item "switch-conversion-max-branch-ratio" +Switch initialization conversion refuses to create arrays that are +bigger than \fBswitch-conversion-max-branch-ratio\fR times the number of +branches in the switch. +.IP "\fBmax-partial-antic-length\fR" 4 +.IX Item "max-partial-antic-length" +Maximum length of the partial antic set computed during the tree +partial redundancy elimination optimization (\fB\-ftree\-pre\fR) when +optimizing at \fB\-O3\fR and above. For some sorts of source code +the enhanced partial redundancy elimination optimization can run away, +consuming all of the memory available on the host machine. This +parameter sets a limit on the length of the sets that are computed, +which prevents the runaway behavior. Setting a value of 0 for +this parameter allows an unlimited set length. +.IP "\fBrpo-vn-max-loop-depth\fR" 4 +.IX Item "rpo-vn-max-loop-depth" +Maximum loop depth that is value-numbered optimistically. +When the limit hits the innermost +\&\fIrpo-vn-max-loop-depth\fR loops and the outermost loop in the +loop nest are value-numbered optimistically and the remaining ones not. +.IP "\fBsccvn-max-alias-queries-per-access\fR" 4 +.IX Item "sccvn-max-alias-queries-per-access" +Maximum number of alias-oracle queries we perform when looking for +redundancies for loads and stores. If this limit is hit the search +is aborted and the load or store is not considered redundant. The +number of queries is algorithmically limited to the number of +stores on all paths from the load to the function entry. +.IP "\fBira-max-loops-num\fR" 4 +.IX Item "ira-max-loops-num" +\&\s-1IRA\s0 uses regional register allocation by default. If a function +contains more loops than the number given by this parameter, only at most +the given number of the most frequently-executed loops form regions +for regional register allocation. +.IP "\fBira-max-conflict-table-size\fR" 4 +.IX Item "ira-max-conflict-table-size" +Although \s-1IRA\s0 uses a sophisticated algorithm to compress the conflict +table, the table can still require excessive amounts of memory for +huge functions. If the conflict table for a function could be more +than the size in \s-1MB\s0 given by this parameter, the register allocator +instead uses a faster, simpler, and lower-quality +algorithm that does not require building a pseudo-register conflict table. +.IP "\fBira-loop-reserved-regs\fR" 4 +.IX Item "ira-loop-reserved-regs" +\&\s-1IRA\s0 can be used to evaluate more accurate register pressure in loops +for decisions to move loop invariants (see \fB\-O3\fR). The number +of available registers reserved for some other purposes is given +by this parameter. Default of the parameter +is the best found from numerous experiments. +.IP "\fBlra-inheritance-ebb-probability-cutoff\fR" 4 +.IX Item "lra-inheritance-ebb-probability-cutoff" +\&\s-1LRA\s0 tries to reuse values reloaded in registers in subsequent insns. +This optimization is called inheritance. \s-1EBB\s0 is used as a region to +do this optimization. The parameter defines a minimal fall-through +edge probability in percentage used to add \s-1BB\s0 to inheritance \s-1EBB\s0 in +\&\s-1LRA.\s0 The default value was chosen +from numerous runs of \s-1SPEC2000\s0 on x86\-64. +.IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 +.IX Item "loop-invariant-max-bbs-in-loop" +Loop invariant motion can be very expensive, both in compilation time and +in amount of needed compile-time memory, with very large loops. Loops +with more basic blocks than this parameter won't have loop invariant +motion optimization performed on them. +.IP "\fBloop-max-datarefs-for-datadeps\fR" 4 +.IX Item "loop-max-datarefs-for-datadeps" +Building data dependencies is expensive for very large loops. This +parameter limits the number of data references in loops that are +considered for data dependence analysis. These large loops are no +handled by the optimizations using loop data dependencies. +.IP "\fBmax-vartrack-size\fR" 4 +.IX Item "max-vartrack-size" +Sets a maximum number of hash table slots to use during variable +tracking dataflow analysis of any function. If this limit is exceeded +with variable tracking at assignments enabled, analysis for that +function is retried without it, after removing all debug insns from +the function. If the limit is exceeded even without debug insns, var +tracking analysis is completely disabled for the function. Setting +the parameter to zero makes it unlimited. +.IP "\fBmax-vartrack-expr-depth\fR" 4 +.IX Item "max-vartrack-expr-depth" +Sets a maximum number of recursion levels when attempting to map +variable names or debug temporaries to value expressions. This trades +compilation time for more complete debug information. If this is set too +low, value expressions that are available and could be represented in +debug information may end up not being used; setting this higher may +enable the compiler to find more complex debug expressions, but compile +time and memory use may grow. +.IP "\fBmax-debug-marker-count\fR" 4 +.IX Item "max-debug-marker-count" +Sets a threshold on the number of debug markers (e.g. begin stmt +markers) to avoid complexity explosion at inlining or expanding to \s-1RTL.\s0 +If a function has more such gimple stmts than the set limit, such stmts +will be dropped from the inlined copy of a function, and from its \s-1RTL\s0 +expansion. +.IP "\fBmin-nondebug-insn-uid\fR" 4 +.IX Item "min-nondebug-insn-uid" +Use uids starting at this parameter for nondebug insns. The range below +the parameter is reserved exclusively for debug insns created by +\&\fB\-fvar\-tracking\-assignments\fR, but debug insns may get +(non-overlapping) uids above it if the reserved range is exhausted. +.IP "\fBipa-sra-ptr-growth-factor\fR" 4 +.IX Item "ipa-sra-ptr-growth-factor" +IPA-SRA replaces a pointer to an aggregate with one or more new +parameters only when their cumulative size is less or equal to +\&\fBipa-sra-ptr-growth-factor\fR times the size of the original +pointer parameter. +.IP "\fBsra-max-scalarization-size-Ospeed\fR" 4 +.IX Item "sra-max-scalarization-size-Ospeed" +.PD 0 +.IP "\fBsra-max-scalarization-size-Osize\fR" 4 +.IX Item "sra-max-scalarization-size-Osize" +.PD +The two Scalar Reduction of Aggregates passes (\s-1SRA\s0 and IPA-SRA) aim to +replace scalar parts of aggregates with uses of independent scalar +variables. These parameters control the maximum size, in storage units, +of aggregate which is considered for replacement when compiling for +speed +(\fBsra-max-scalarization-size-Ospeed\fR) or size +(\fBsra-max-scalarization-size-Osize\fR) respectively. +.IP "\fBsra-max-propagations\fR" 4 +.IX Item "sra-max-propagations" +The maximum number of artificial accesses that Scalar Replacement of +Aggregates (\s-1SRA\s0) will track, per one local variable, in order to +facilitate copy propagation. +.IP "\fBtm-max-aggregate-size\fR" 4 +.IX Item "tm-max-aggregate-size" +When making copies of thread-local variables in a transaction, this +parameter specifies the size in bytes after which variables are +saved with the logging functions as opposed to save/restore code +sequence pairs. This option only applies when using +\&\fB\-fgnu\-tm\fR. +.IP "\fBgraphite-max-nb-scop-params\fR" 4 +.IX Item "graphite-max-nb-scop-params" +To avoid exponential effects in the Graphite loop transforms, the +number of parameters in a Static Control Part (SCoP) is bounded. +A value of zero can be used to lift +the bound. A variable whose value is unknown at compilation time and +defined outside a SCoP is a parameter of the SCoP. +.IP "\fBloop-block-tile-size\fR" 4 +.IX Item "loop-block-tile-size" +Loop blocking or strip mining transforms, enabled with +\&\fB\-floop\-block\fR or \fB\-floop\-strip\-mine\fR, strip mine each +loop in the loop nest by a given number of iterations. The strip +length can be changed using the \fBloop-block-tile-size\fR +parameter. +.IP "\fBipa-cp-value-list-size\fR" 4 +.IX Item "ipa-cp-value-list-size" +IPA-CP attempts to track all possible values and types passed to a function's +parameter in order to propagate them and perform devirtualization. +\&\fBipa-cp-value-list-size\fR is the maximum number of values and types it +stores per one formal parameter of a function. +.IP "\fBipa-cp-eval-threshold\fR" 4 +.IX Item "ipa-cp-eval-threshold" +IPA-CP calculates its own score of cloning profitability heuristics +and performs those cloning opportunities with scores that exceed +\&\fBipa-cp-eval-threshold\fR. +.IP "\fBipa-cp-recursion-penalty\fR" 4 +.IX Item "ipa-cp-recursion-penalty" +Percentage penalty the recursive functions will receive when they +are evaluated for cloning. +.IP "\fBipa-cp-single-call-penalty\fR" 4 +.IX Item "ipa-cp-single-call-penalty" +Percentage penalty functions containing a single call to another +function will receive when they are evaluated for cloning. +.IP "\fBipa-max-agg-items\fR" 4 +.IX Item "ipa-max-agg-items" +IPA-CP is also capable to propagate a number of scalar values passed +in an aggregate. \fBipa-max-agg-items\fR controls the maximum +number of such values per one parameter. +.IP "\fBipa-cp-loop-hint-bonus\fR" 4 +.IX Item "ipa-cp-loop-hint-bonus" +When IPA-CP determines that a cloning candidate would make the number +of iterations of a loop known, it adds a bonus of +\&\fBipa-cp-loop-hint-bonus\fR to the profitability score of +the candidate. +.IP "\fBipa-cp-array-index-hint-bonus\fR" 4 +.IX Item "ipa-cp-array-index-hint-bonus" +When IPA-CP determines that a cloning candidate would make the index of +an array access known, it adds a bonus of +\&\fBipa-cp-array-index-hint-bonus\fR to the profitability +score of the candidate. +.IP "\fBipa-max-aa-steps\fR" 4 +.IX Item "ipa-max-aa-steps" +During its analysis of function bodies, IPA-CP employs alias analysis +in order to track values pointed to by function parameters. In order +not spend too much time analyzing huge functions, it gives up and +consider all memory clobbered after examining +\&\fBipa-max-aa-steps\fR statements modifying memory. +.IP "\fBlto-partitions\fR" 4 +.IX Item "lto-partitions" +Specify desired number of partitions produced during \s-1WHOPR\s0 compilation. +The number of partitions should exceed the number of CPUs used for compilation. +.IP "\fBlto-min-partition\fR" 4 +.IX Item "lto-min-partition" +Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). +This prevents expenses of splitting very small programs into too many +partitions. +.IP "\fBlto-max-partition\fR" 4 +.IX Item "lto-max-partition" +Size of max partition for \s-1WHOPR\s0 (in estimated instructions). +to provide an upper bound for individual size of partition. +Meant to be used only with balanced partitioning. +.IP "\fBlto-max-streaming-parallelism\fR" 4 +.IX Item "lto-max-streaming-parallelism" +Maximal number of parallel processes used for \s-1LTO\s0 streaming. +.IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 +.IX Item "cxx-max-namespaces-for-diagnostic-help" +The maximum number of namespaces to consult for suggestions when \*(C+ +name lookup fails for an identifier. +.IP "\fBsink-frequency-threshold\fR" 4 +.IX Item "sink-frequency-threshold" +The maximum relative execution frequency (in percents) of the target block +relative to a statement's original block to allow statement sinking of a +statement. Larger numbers result in more aggressive statement sinking. +A small positive adjustment is applied for +statements with memory operands as those are even more profitable so sink. +.IP "\fBmax-stores-to-sink\fR" 4 +.IX Item "max-stores-to-sink" +The maximum number of conditional store pairs that can be sunk. Set to 0 +if either vectorization (\fB\-ftree\-vectorize\fR) or if-conversion +(\fB\-ftree\-loop\-if\-convert\fR) is disabled. +.IP "\fBallow-store-data-races\fR" 4 +.IX Item "allow-store-data-races" +Allow optimizers to introduce new data races on stores. +Set to 1 to allow, otherwise to 0. +.IP "\fBcase-values-threshold\fR" 4 +.IX Item "case-values-threshold" +The smallest number of different values for which it is best to use a +jump-table instead of a tree of conditional branches. If the value is +0, use the default for the machine. +.IP "\fBtree-reassoc-width\fR" 4 +.IX Item "tree-reassoc-width" +Set the maximum number of instructions executed in parallel in +reassociated tree. This parameter overrides target dependent +heuristics used by default if has non zero value. +.IP "\fBsched-pressure-algorithm\fR" 4 +.IX Item "sched-pressure-algorithm" +Choose between the two available implementations of +\&\fB\-fsched\-pressure\fR. Algorithm 1 is the original implementation +and is the more likely to prevent instructions from being reordered. +Algorithm 2 was designed to be a compromise between the relatively +conservative approach taken by algorithm 1 and the rather aggressive +approach taken by the default scheduler. It relies more heavily on +having a regular register file and accurate register pressure classes. +See \fIhaifa\-sched.c\fR in the \s-1GCC\s0 sources for more details. +.Sp +The default choice depends on the target. +.IP "\fBmax-slsr-cand-scan\fR" 4 +.IX Item "max-slsr-cand-scan" +Set the maximum number of existing candidates that are considered when +seeking a basis for a new straight-line strength reduction candidate. +.IP "\fBasan-globals\fR" 4 +.IX Item "asan-globals" +Enable buffer overflow detection for global objects. This kind +of protection is enabled by default if you are using +\&\fB\-fsanitize=address\fR option. +To disable global objects protection use \fB\-\-param asan\-globals=0\fR. +.IP "\fBasan-stack\fR" 4 +.IX Item "asan-stack" +Enable buffer overflow detection for stack objects. This kind of +protection is enabled by default when using \fB\-fsanitize=address\fR. +To disable stack protection use \fB\-\-param asan\-stack=0\fR option. +.IP "\fBasan-instrument-reads\fR" 4 +.IX Item "asan-instrument-reads" +Enable buffer overflow detection for memory reads. This kind of +protection is enabled by default when using \fB\-fsanitize=address\fR. +To disable memory reads protection use +\&\fB\-\-param asan\-instrument\-reads=0\fR. +.IP "\fBasan-instrument-writes\fR" 4 +.IX Item "asan-instrument-writes" +Enable buffer overflow detection for memory writes. This kind of +protection is enabled by default when using \fB\-fsanitize=address\fR. +To disable memory writes protection use +\&\fB\-\-param asan\-instrument\-writes=0\fR option. +.IP "\fBasan-memintrin\fR" 4 +.IX Item "asan-memintrin" +Enable detection for built-in functions. This kind of protection +is enabled by default when using \fB\-fsanitize=address\fR. +To disable built-in functions protection use +\&\fB\-\-param asan\-memintrin=0\fR. +.IP "\fBasan-use-after-return\fR" 4 +.IX Item "asan-use-after-return" +Enable detection of use-after-return. This kind of protection +is enabled by default when using the \fB\-fsanitize=address\fR option. +To disable it use \fB\-\-param asan\-use\-after\-return=0\fR. +.Sp +Note: By default the check is disabled at run time. To enable it, +add \f(CW\*(C`detect_stack_use_after_return=1\*(C'\fR to the environment variable +\&\fB\s-1ASAN_OPTIONS\s0\fR. +.IP "\fBasan-instrumentation-with-call-threshold\fR" 4 +.IX Item "asan-instrumentation-with-call-threshold" +If number of memory accesses in function being instrumented +is greater or equal to this number, use callbacks instead of inline checks. +E.g. to disable inline code use +\&\fB\-\-param asan\-instrumentation\-with\-call\-threshold=0\fR. +.IP "\fBuse-after-scope-direct-emission-threshold\fR" 4 +.IX Item "use-after-scope-direct-emission-threshold" +If the size of a local variable in bytes is smaller or equal to this +number, directly poison (or unpoison) shadow memory instead of using +run-time callbacks. +.IP "\fBmax-fsm-thread-path-insns\fR" 4 +.IX Item "max-fsm-thread-path-insns" +Maximum number of instructions to copy when duplicating blocks on a +finite state automaton jump thread path. +.IP "\fBmax-fsm-thread-length\fR" 4 +.IX Item "max-fsm-thread-length" +Maximum number of basic blocks on a finite state automaton jump thread +path. +.IP "\fBmax-fsm-thread-paths\fR" 4 +.IX Item "max-fsm-thread-paths" +Maximum number of new jump thread paths to create for a finite state +automaton. +.IP "\fBparloops-chunk-size\fR" 4 +.IX Item "parloops-chunk-size" +Chunk size of omp schedule for loops parallelized by parloops. +.IP "\fBparloops-schedule\fR" 4 +.IX Item "parloops-schedule" +Schedule type of omp schedule for loops parallelized by parloops (static, +dynamic, guided, auto, runtime). +.IP "\fBparloops-min-per-thread\fR" 4 +.IX Item "parloops-min-per-thread" +The minimum number of iterations per thread of an innermost parallelized +loop for which the parallelized variant is preferred over the single threaded +one. Note that for a parallelized loop nest the +minimum number of iterations of the outermost loop per thread is two. +.IP "\fBmax-ssa-name-query-depth\fR" 4 +.IX Item "max-ssa-name-query-depth" +Maximum depth of recursion when querying properties of \s-1SSA\s0 names in things +like fold routines. One level of recursion corresponds to following a +use-def chain. +.IP "\fBhsa-gen-debug-stores\fR" 4 +.IX Item "hsa-gen-debug-stores" +Enable emission of special debug stores within \s-1HSA\s0 kernels which are +then read and reported by libgomp plugin. Generation of these stores +is disabled by default, use \fB\-\-param hsa\-gen\-debug\-stores=1\fR to +enable it. +.IP "\fBmax-speculative-devirt-maydefs\fR" 4 +.IX Item "max-speculative-devirt-maydefs" +The maximum number of may-defs we analyze when looking for a must-def +specifying the dynamic type of an object that invokes a virtual call +we may be able to devirtualize speculatively. +.IP "\fBmax-vrp-switch-assertions\fR" 4 +.IX Item "max-vrp-switch-assertions" +The maximum number of assertions to add along the default edge of a switch +statement during \s-1VRP.\s0 +.IP "\fBunroll-jam-min-percent\fR" 4 +.IX Item "unroll-jam-min-percent" +The minimum percentage of memory references that must be optimized +away for the unroll-and-jam transformation to be considered profitable. +.IP "\fBunroll-jam-max-unroll\fR" 4 +.IX Item "unroll-jam-max-unroll" +The maximum number of times the outer loop should be unrolled by +the unroll-and-jam transformation. +.IP "\fBmax-rtl-if-conversion-unpredictable-cost\fR" 4 +.IX Item "max-rtl-if-conversion-unpredictable-cost" +Maximum permissible cost for the sequence that would be generated +by the \s-1RTL\s0 if-conversion pass for a branch that is considered unpredictable. +.IP "\fBmax-variable-expansions-in-unroller\fR" 4 +.IX Item "max-variable-expansions-in-unroller" +If \fB\-fvariable\-expansion\-in\-unroller\fR is used, the maximum number +of times that an individual variable will be expanded during loop unrolling. +.IP "\fBtracer-min-branch-probability-feedback\fR" 4 +.IX Item "tracer-min-branch-probability-feedback" +Stop forward growth if the probability of best edge is less than +this threshold (in percent). Used when profile feedback is available. +.IP "\fBpartial-inlining-entry-probability\fR" 4 +.IX Item "partial-inlining-entry-probability" +Maximum probability of the entry \s-1BB\s0 of split region +(in percent relative to entry \s-1BB\s0 of the function) +to make partial inlining happen. +.IP "\fBmax-tracked-strlens\fR" 4 +.IX Item "max-tracked-strlens" +Maximum number of strings for which strlen optimization pass will +track string lengths. +.IP "\fBgcse-after-reload-partial-fraction\fR" 4 +.IX Item "gcse-after-reload-partial-fraction" +The threshold ratio for performing partial redundancy +elimination after reload. +.IP "\fBgcse-after-reload-critical-fraction\fR" 4 +.IX Item "gcse-after-reload-critical-fraction" +The threshold ratio of critical edges execution count that +permit performing redundancy elimination after reload. +.IP "\fBmax-loop-header-insns\fR" 4 +.IX Item "max-loop-header-insns" +The maximum number of insns in loop header duplicated +by the copy loop headers pass. +.IP "\fBvect-epilogues-nomask\fR" 4 +.IX Item "vect-epilogues-nomask" +Enable loop epilogue vectorization using smaller vector size. +.IP "\fBslp-max-insns-in-bb\fR" 4 +.IX Item "slp-max-insns-in-bb" +Maximum number of instructions in basic block to be +considered for \s-1SLP\s0 vectorization. +.IP "\fBavoid-fma-max-bits\fR" 4 +.IX Item "avoid-fma-max-bits" +Maximum number of bits for which we avoid creating FMAs. +.IP "\fBsms-loop-average-count-threshold\fR" 4 +.IX Item "sms-loop-average-count-threshold" +A threshold on the average loop count considered by the swing modulo scheduler. +.IP "\fBsms-dfa-history\fR" 4 +.IX Item "sms-dfa-history" +The number of cycles the swing modulo scheduler considers when checking +conflicts using \s-1DFA.\s0 +.IP "\fBhot-bb-count-fraction\fR" 4 +.IX Item "hot-bb-count-fraction" +Select fraction of the maximal count of repetitions of basic block +in program given basic block needs +to have to be considered hot (used in non-LTO mode) +.IP "\fBmax-inline-insns-recursive-auto\fR" 4 +.IX Item "max-inline-insns-recursive-auto" +The maximum number of instructions non-inline function +can grow to via recursive inlining. +.IP "\fBgraphite-allow-codegen-errors\fR" 4 +.IX Item "graphite-allow-codegen-errors" +Whether codegen errors should be ICEs when \fB\-fchecking\fR. +.IP "\fBsms-max-ii-factor\fR" 4 +.IX Item "sms-max-ii-factor" +A factor for tuning the upper bound that swing modulo scheduler +uses for scheduling a loop. +.IP "\fBlra-max-considered-reload-pseudos\fR" 4 +.IX Item "lra-max-considered-reload-pseudos" +The max number of reload pseudos which are considered during +spilling a non-reload pseudo. +.IP "\fBmax-pow-sqrt-depth\fR" 4 +.IX Item "max-pow-sqrt-depth" +Maximum depth of sqrt chains to use when synthesizing exponentiation +by a real constant. +.IP "\fBmax-dse-active-local-stores\fR" 4 +.IX Item "max-dse-active-local-stores" +Maximum number of active local stores in \s-1RTL\s0 dead store elimination. +.IP "\fBasan-instrument-allocas\fR" 4 +.IX Item "asan-instrument-allocas" +Enable asan allocas/VLAs protection. +.IP "\fBmax-iterations-computation-cost\fR" 4 +.IX Item "max-iterations-computation-cost" +Bound on the cost of an expression to compute the number of iterations. +.IP "\fBmax-isl-operations\fR" 4 +.IX Item "max-isl-operations" +Maximum number of isl operations, 0 means unlimited. +.IP "\fBgraphite-max-arrays-per-scop\fR" 4 +.IX Item "graphite-max-arrays-per-scop" +Maximum number of arrays per scop. +.IP "\fBmax-vartrack-reverse-op-size\fR" 4 +.IX Item "max-vartrack-reverse-op-size" +Max. size of loc list for which reverse ops should be added. +.IP "\fBunlikely-bb-count-fraction\fR" 4 +.IX Item "unlikely-bb-count-fraction" +The minimum fraction of profile runs a given basic block execution count +must be not to be considered unlikely. +.IP "\fBtracer-dynamic-coverage-feedback\fR" 4 +.IX Item "tracer-dynamic-coverage-feedback" +The percentage of function, weighted by execution frequency, +that must be covered by trace formation. +Used when profile feedback is available. +.IP "\fBmax-inline-recursive-depth-auto\fR" 4 +.IX Item "max-inline-recursive-depth-auto" +The maximum depth of recursive inlining for non-inline functions. +.IP "\fBfsm-scale-path-stmts\fR" 4 +.IX Item "fsm-scale-path-stmts" +Scale factor to apply to the number of statements in a threading path +when comparing to the number of (scaled) blocks. +.IP "\fBfsm-maximum-phi-arguments\fR" 4 +.IX Item "fsm-maximum-phi-arguments" +Maximum number of arguments a \s-1PHI\s0 may have before the \s-1FSM\s0 threader +will not try to thread through its block. +.IP "\fBuninit-control-dep-attempts\fR" 4 +.IX Item "uninit-control-dep-attempts" +Maximum number of nested calls to search for control dependencies +during uninitialized variable analysis. +.IP "\fBindir-call-topn-profile\fR" 4 +.IX Item "indir-call-topn-profile" +Track top N target addresses in indirect-call profile. +.IP "\fBmax-once-peeled-insns\fR" 4 +.IX Item "max-once-peeled-insns" +The maximum number of insns of a peeled loop that rolls only once. +.IP "\fBsra-max-scalarization-size-Osize\fR" 4 +.IX Item "sra-max-scalarization-size-Osize" +Maximum size, in storage units, of an aggregate +which should be considered for scalarization when compiling for size. +.IP "\fBfsm-scale-path-blocks\fR" 4 +.IX Item "fsm-scale-path-blocks" +Scale factor to apply to the number of blocks in a threading path +when comparing to the number of (scaled) statements. +.IP "\fBsched-autopref-queue-depth\fR" 4 +.IX Item "sched-autopref-queue-depth" +Hardware autoprefetcher scheduler model control flag. +Number of lookahead cycles the model looks into; at ' +\&' only enable instruction sorting heuristic. +.IP "\fBloop-versioning-max-inner-insns\fR" 4 +.IX Item "loop-versioning-max-inner-insns" +The maximum number of instructions that an inner loop can have +before the loop versioning pass considers it too big to copy. +.IP "\fBloop-versioning-max-outer-insns\fR" 4 +.IX Item "loop-versioning-max-outer-insns" +The maximum number of instructions that an outer loop can have +before the loop versioning pass considers it too big to copy, +discounting any instructions in inner loops that directly benefit +from versioning. +.IP "\fBssa-name-def-chain-limit\fR" 4 +.IX Item "ssa-name-def-chain-limit" +The maximum number of \s-1SSA_NAME\s0 assignments to follow in determining +a property of a variable such as its value. This limits the number +of iterations or recursive calls \s-1GCC\s0 performs when optimizing certain +statements or when determining their validity prior to issuing +diagnostics. +.RE +.RS 4 +.RE +.SS "Program Instrumentation Options" +.IX Subsection "Program Instrumentation Options" +\&\s-1GCC\s0 supports a number of command-line options that control adding +run-time instrumentation to the code it normally generates. +For example, one purpose of instrumentation is collect profiling +statistics for use in finding program hot spots, code coverage +analysis, or profile-guided optimizations. +Another class of program instrumentation is adding run-time checking +to detect programming errors like invalid pointer +dereferences or out-of-bounds array accesses, as well as deliberately +hostile attacks such as stack smashing or \*(C+ vtable hijacking. +There is also a general hook which can be used to implement other +forms of tracing or function-level instrumentation for debug or +program analysis purposes. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-pg\fR" 4 +.IX Item "-pg" +.PD +Generate extra code to write profile information suitable for the +analysis program \fBprof\fR (for \fB\-p\fR) or \fBgprof\fR +(for \fB\-pg\fR). You must use this option when compiling +the source files you want data about, and you must also use it when +linking. +.Sp +You can use the function attribute \f(CW\*(C`no_instrument_function\*(C'\fR to +suppress profiling of individual functions when compiling with these options. +.IP "\fB\-fprofile\-arcs\fR" 4 +.IX Item "-fprofile-arcs" +Add code so that program flow \fIarcs\fR are instrumented. During +execution the program records how many times each branch and call is +executed and how many times it is taken or returns. On targets that support +constructors with priority support, profiling properly handles constructors, +destructors and \*(C+ constructors (and destructors) of classes which are used +as a type of a global variable. +.Sp +When the compiled +program exits it saves this data to a file called +\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for +profile-directed optimizations (\fB\-fbranch\-probabilities\fR), or for +test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's +\&\fIauxname\fR is generated from the name of the output file, if +explicitly specified and it is not the final executable, otherwise it is +the basename of the source file. In both cases any suffix is removed +(e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or +\&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR). +.IP "\fB\-\-coverage\fR" 4 +.IX Item "--coverage" +This option is used to compile and link code instrumented for coverage +analysis. The option is a synonym for \fB\-fprofile\-arcs\fR +\&\fB\-ftest\-coverage\fR (when compiling) and \fB\-lgcov\fR (when +linking). See the documentation for those options for more details. +.RS 4 +.IP "*" 4 +Compile the source files with \fB\-fprofile\-arcs\fR plus optimization +and code generation options. For test coverage analysis, use the +additional \fB\-ftest\-coverage\fR option. You do not need to profile +every source file in a program. +.IP "*" 4 +Compile the source files additionally with \fB\-fprofile\-abs\-path\fR +to create absolute path names in the \fI.gcno\fR files. This allows +\&\fBgcov\fR to find the correct sources in projects where compilations +occur with different working directories. +.IP "*" 4 +Link your object files with \fB\-lgcov\fR or \fB\-fprofile\-arcs\fR +(the latter implies the former). +.IP "*" 4 +Run the program on a representative workload to generate the arc profile +information. This may be repeated any number of times. You can run +concurrent instances of your program, and provided that the file system +supports locking, the data files will be correctly updated. Unless +a strict \s-1ISO C\s0 dialect option is in effect, \f(CW\*(C`fork\*(C'\fR calls are +detected and correctly handled without double counting. +.IP "*" 4 +For profile-directed optimizations, compile the source files again with +the same optimization and code generation options plus +\&\fB\-fbranch\-probabilities\fR. +.IP "*" 4 +For test coverage analysis, use \fBgcov\fR to produce human readable +information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the +\&\fBgcov\fR documentation for further information. +.RE +.RS 4 +.Sp +With \fB\-fprofile\-arcs\fR, for each function of your program \s-1GCC\s0 +creates a program flow graph, then finds a spanning tree for the graph. +Only arcs that are not on the spanning tree have to be instrumented: the +compiler adds code to count the number of times that these arcs are +executed. When an arc is the only exit or only entrance to a block, the +instrumentation code can be added to the block; otherwise, a new basic +block must be created to hold the instrumentation code. +.RE +.IP "\fB\-ftest\-coverage\fR" 4 +.IX Item "-ftest-coverage" +Produce a notes file that the \fBgcov\fR code-coverage utility can use to +show program coverage. Each source file's note file is called +\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option +above for a description of \fIauxname\fR and instructions on how to +generate test coverage data. Coverage data matches the source files +more closely if you do not optimize. +.IP "\fB\-fprofile\-abs\-path\fR" 4 +.IX Item "-fprofile-abs-path" +Automatically convert relative source file names to absolute path names +in the \fI.gcno\fR files. This allows \fBgcov\fR to find the correct +sources in projects where compilations occur with different working +directories. +.IP "\fB\-fprofile\-dir=\fR\fIpath\fR" 4 +.IX Item "-fprofile-dir=path" +Set the directory to search for the profile data files in to \fIpath\fR. +This option affects only the profile data generated by +\&\fB\-fprofile\-generate\fR, \fB\-ftest\-coverage\fR, \fB\-fprofile\-arcs\fR +and used by \fB\-fprofile\-use\fR and \fB\-fbranch\-probabilities\fR +and its related options. Both absolute and relative paths can be used. +By default, \s-1GCC\s0 uses the current directory as \fIpath\fR, thus the +profile data file appears in the same directory as the object file. +In order to prevent the file name clashing, if the object file name is +not an absolute path, we mangle the absolute path of the +\&\fI\fIsourcename\fI.gcda\fR file and use it as the file name of a +\&\fI.gcda\fR file. +.Sp +When an executable is run in a massive parallel environment, it is recommended +to save profile to different folders. That can be done with variables +in \fIpath\fR that are exported during run-time: +.RS 4 +.IP "\fB\f(CB%p\fB\fR" 4 +.IX Item "%p" +process \s-1ID.\s0 +.IP "\fB\f(CB%q\fB{\s-1VAR\s0}\fR" 4 +.IX Item "%q{VAR}" +value of environment variable \fI\s-1VAR\s0\fR +.RE +.RS 4 +.RE +.IP "\fB\-fprofile\-generate\fR" 4 +.IX Item "-fprofile-generate" +.PD 0 +.IP "\fB\-fprofile\-generate=\fR\fIpath\fR" 4 +.IX Item "-fprofile-generate=path" +.PD +Enable options usually used for instrumenting application to produce +profile useful for later recompilation with profile feedback based +optimization. You must use \fB\-fprofile\-generate\fR both when +compiling and when linking your program. +.Sp +The following options are enabled: +\&\fB\-fprofile\-arcs\fR, \fB\-fprofile\-values\fR, +\&\fB\-finline\-functions\fR, and \fB\-fipa\-bit\-cp\fR. +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 looks at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.Sp +To optimize the program based on the collected profile information, use +\&\fB\-fprofile\-use\fR. +.IP "\fB\-fprofile\-update=\fR\fImethod\fR" 4 +.IX Item "-fprofile-update=method" +Alter the update method for an application instrumented for profile +feedback based optimization. The \fImethod\fR argument should be one of +\&\fBsingle\fR, \fBatomic\fR or \fBprefer-atomic\fR. +The first one is useful for single-threaded applications, +while the second one prevents profile corruption by emitting thread-safe code. +.Sp +\&\fBWarning:\fR When an application does not properly join all threads +(or creates an detached thread), a profile file can be still corrupted. +.Sp +Using \fBprefer-atomic\fR would be transformed either to \fBatomic\fR, +when supported by a target, or to \fBsingle\fR otherwise. The \s-1GCC\s0 driver +automatically selects \fBprefer-atomic\fR when \fB\-pthread\fR +is present in the command line. +.IP "\fB\-fprofile\-filter\-files=\fR\fIregex\fR" 4 +.IX Item "-fprofile-filter-files=regex" +Instrument only functions from files where names match +any regular expression (separated by a semi-colon). +.Sp +For example, \fB\-fprofile\-filter\-files=main.c;module.*.c\fR will instrument +only \fImain.c\fR and all C files starting with 'module'. +.IP "\fB\-fprofile\-exclude\-files=\fR\fIregex\fR" 4 +.IX Item "-fprofile-exclude-files=regex" +Instrument only functions from files where names do not match +all the regular expressions (separated by a semi-colon). +.Sp +For example, \fB\-fprofile\-exclude\-files=/usr/*\fR will prevent instrumentation +of all files that are located in \fI/usr/\fR folder. +.IP "\fB\-fsanitize=address\fR" 4 +.IX Item "-fsanitize=address" +Enable AddressSanitizer, a fast memory error detector. +Memory access instructions are instrumented to detect +out-of-bounds and use-after-free bugs. +The option enables \fB\-fsanitize\-address\-use\-after\-scope\fR. +See <\fBhttps://github.com/google/sanitizers/wiki/AddressSanitizer\fR> for +more details. The run-time behavior can be influenced using the +\&\fB\s-1ASAN_OPTIONS\s0\fR environment variable. When set to \f(CW\*(C`help=1\*(C'\fR, +the available options are shown at startup of the instrumented program. See +<\fBhttps://github.com/google/sanitizers/wiki/AddressSanitizerFlags#run\-time\-flags\fR> +for a list of supported options. +The option cannot be combined with \fB\-fsanitize=thread\fR. +.IP "\fB\-fsanitize=kernel\-address\fR" 4 +.IX Item "-fsanitize=kernel-address" +Enable AddressSanitizer for Linux kernel. +See <\fBhttps://github.com/google/kasan/wiki\fR> for more details. +.IP "\fB\-fsanitize=pointer\-compare\fR" 4 +.IX Item "-fsanitize=pointer-compare" +Instrument comparison operation (<, <=, >, >=) with pointer operands. +The option must be combined with either \fB\-fsanitize=kernel\-address\fR or +\&\fB\-fsanitize=address\fR +The option cannot be combined with \fB\-fsanitize=thread\fR. +Note: By default the check is disabled at run time. To enable it, +add \f(CW\*(C`detect_invalid_pointer_pairs=2\*(C'\fR to the environment variable +\&\fB\s-1ASAN_OPTIONS\s0\fR. Using \f(CW\*(C`detect_invalid_pointer_pairs=1\*(C'\fR detects +invalid operation only when both pointers are non-null. +.IP "\fB\-fsanitize=pointer\-subtract\fR" 4 +.IX Item "-fsanitize=pointer-subtract" +Instrument subtraction with pointer operands. +The option must be combined with either \fB\-fsanitize=kernel\-address\fR or +\&\fB\-fsanitize=address\fR +The option cannot be combined with \fB\-fsanitize=thread\fR. +Note: By default the check is disabled at run time. To enable it, +add \f(CW\*(C`detect_invalid_pointer_pairs=2\*(C'\fR to the environment variable +\&\fB\s-1ASAN_OPTIONS\s0\fR. Using \f(CW\*(C`detect_invalid_pointer_pairs=1\*(C'\fR detects +invalid operation only when both pointers are non-null. +.IP "\fB\-fsanitize=thread\fR" 4 +.IX Item "-fsanitize=thread" +Enable ThreadSanitizer, a fast data race detector. +Memory access instructions are instrumented to detect +data race bugs. See <\fBhttps://github.com/google/sanitizers/wiki#threadsanitizer\fR> for more +details. The run-time behavior can be influenced using the \fB\s-1TSAN_OPTIONS\s0\fR +environment variable; see +<\fBhttps://github.com/google/sanitizers/wiki/ThreadSanitizerFlags\fR> for a list of +supported options. +The option cannot be combined with \fB\-fsanitize=address\fR, +\&\fB\-fsanitize=leak\fR. +.Sp +Note that sanitized atomic builtins cannot throw exceptions when +operating on invalid memory addresses with non-call exceptions +(\fB\-fnon\-call\-exceptions\fR). +.IP "\fB\-fsanitize=leak\fR" 4 +.IX Item "-fsanitize=leak" +Enable LeakSanitizer, a memory leak detector. +This option only matters for linking of executables and +the executable is linked against a library that overrides \f(CW\*(C`malloc\*(C'\fR +and other allocator functions. See +<\fBhttps://github.com/google/sanitizers/wiki/AddressSanitizerLeakSanitizer\fR> for more +details. The run-time behavior can be influenced using the +\&\fB\s-1LSAN_OPTIONS\s0\fR environment variable. +The option cannot be combined with \fB\-fsanitize=thread\fR. +.IP "\fB\-fsanitize=undefined\fR" 4 +.IX Item "-fsanitize=undefined" +Enable UndefinedBehaviorSanitizer, a fast undefined behavior detector. +Various computations are instrumented to detect undefined behavior +at runtime. See <\fBhttps://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html\fR> for more details. The run-time behavior can be influenced using the +\&\fB\s-1UBSAN_OPTIONS\s0\fR environment variable. Current suboptions are: +.RS 4 +.IP "\fB\-fsanitize=shift\fR" 4 +.IX Item "-fsanitize=shift" +This option enables checking that the result of a shift operation is +not undefined. Note that what exactly is considered undefined differs +slightly between C and \*(C+, as well as between \s-1ISO C90\s0 and C99, etc. +This option has two suboptions, \fB\-fsanitize=shift\-base\fR and +\&\fB\-fsanitize=shift\-exponent\fR. +.IP "\fB\-fsanitize=shift\-exponent\fR" 4 +.IX Item "-fsanitize=shift-exponent" +This option enables checking that the second argument of a shift operation +is not negative and is smaller than the precision of the promoted first +argument. +.IP "\fB\-fsanitize=shift\-base\fR" 4 +.IX Item "-fsanitize=shift-base" +If the second argument of a shift operation is within range, check that the +result of a shift operation is not undefined. Note that what exactly is +considered undefined differs slightly between C and \*(C+, as well as between +\&\s-1ISO C90\s0 and C99, etc. +.IP "\fB\-fsanitize=integer\-divide\-by\-zero\fR" 4 +.IX Item "-fsanitize=integer-divide-by-zero" +Detect integer division by zero as well as \f(CW\*(C`INT_MIN / \-1\*(C'\fR division. +.IP "\fB\-fsanitize=unreachable\fR" 4 +.IX Item "-fsanitize=unreachable" +With this option, the compiler turns the \f(CW\*(C`_\|_builtin_unreachable\*(C'\fR +call into a diagnostics message call instead. When reaching the +\&\f(CW\*(C`_\|_builtin_unreachable\*(C'\fR call, the behavior is undefined. +.IP "\fB\-fsanitize=vla\-bound\fR" 4 +.IX Item "-fsanitize=vla-bound" +This option instructs the compiler to check that the size of a variable +length array is positive. +.IP "\fB\-fsanitize=null\fR" 4 +.IX Item "-fsanitize=null" +This option enables pointer checking. Particularly, the application +built with this option turned on will issue an error message when it +tries to dereference a \s-1NULL\s0 pointer, or if a reference (possibly an +rvalue reference) is bound to a \s-1NULL\s0 pointer, or if a method is invoked +on an object pointed by a \s-1NULL\s0 pointer. +.IP "\fB\-fsanitize=return\fR" 4 +.IX Item "-fsanitize=return" +This option enables return statement checking. Programs +built with this option turned on will issue an error message +when the end of a non-void function is reached without actually +returning a value. This option works in \*(C+ only. +.IP "\fB\-fsanitize=signed\-integer\-overflow\fR" 4 +.IX Item "-fsanitize=signed-integer-overflow" +This option enables signed integer overflow checking. We check that +the result of \f(CW\*(C`+\*(C'\fR, \f(CW\*(C`*\*(C'\fR, and both unary and binary \f(CW\*(C`\-\*(C'\fR +does not overflow in the signed arithmetics. Note, integer promotion +rules must be taken into account. That is, the following is not an +overflow: +.Sp +.Vb 2 +\& signed char a = SCHAR_MAX; +\& a++; +.Ve +.IP "\fB\-fsanitize=bounds\fR" 4 +.IX Item "-fsanitize=bounds" +This option enables instrumentation of array bounds. Various out of bounds +accesses are detected. Flexible array members, flexible array member-like +arrays, and initializers of variables with static storage are not instrumented. +.IP "\fB\-fsanitize=bounds\-strict\fR" 4 +.IX Item "-fsanitize=bounds-strict" +This option enables strict instrumentation of array bounds. Most out of bounds +accesses are detected, including flexible array members and flexible array +member-like arrays. Initializers of variables with static storage are not +instrumented. +.IP "\fB\-fsanitize=alignment\fR" 4 +.IX Item "-fsanitize=alignment" +This option enables checking of alignment of pointers when they are +dereferenced, or when a reference is bound to insufficiently aligned target, +or when a method or constructor is invoked on insufficiently aligned object. +.IP "\fB\-fsanitize=object\-size\fR" 4 +.IX Item "-fsanitize=object-size" +This option enables instrumentation of memory references using the +\&\f(CW\*(C`_\|_builtin_object_size\*(C'\fR function. Various out of bounds pointer +accesses are detected. +.IP "\fB\-fsanitize=float\-divide\-by\-zero\fR" 4 +.IX Item "-fsanitize=float-divide-by-zero" +Detect floating-point division by zero. Unlike other similar options, +\&\fB\-fsanitize=float\-divide\-by\-zero\fR is not enabled by +\&\fB\-fsanitize=undefined\fR, since floating-point division by zero can +be a legitimate way of obtaining infinities and NaNs. +.IP "\fB\-fsanitize=float\-cast\-overflow\fR" 4 +.IX Item "-fsanitize=float-cast-overflow" +This option enables floating-point type to integer conversion checking. +We check that the result of the conversion does not overflow. +Unlike other similar options, \fB\-fsanitize=float\-cast\-overflow\fR is +not enabled by \fB\-fsanitize=undefined\fR. +This option does not work well with \f(CW\*(C`FE_INVALID\*(C'\fR exceptions enabled. +.IP "\fB\-fsanitize=nonnull\-attribute\fR" 4 +.IX Item "-fsanitize=nonnull-attribute" +This option enables instrumentation of calls, checking whether null values +are not passed to arguments marked as requiring a non-null value by the +\&\f(CW\*(C`nonnull\*(C'\fR function attribute. +.IP "\fB\-fsanitize=returns\-nonnull\-attribute\fR" 4 +.IX Item "-fsanitize=returns-nonnull-attribute" +This option enables instrumentation of return statements in functions +marked with \f(CW\*(C`returns_nonnull\*(C'\fR function attribute, to detect returning +of null values from such functions. +.IP "\fB\-fsanitize=bool\fR" 4 +.IX Item "-fsanitize=bool" +This option enables instrumentation of loads from bool. If a value other +than 0/1 is loaded, a run-time error is issued. +.IP "\fB\-fsanitize=enum\fR" 4 +.IX Item "-fsanitize=enum" +This option enables instrumentation of loads from an enum type. If +a value outside the range of values for the enum type is loaded, +a run-time error is issued. +.IP "\fB\-fsanitize=vptr\fR" 4 +.IX Item "-fsanitize=vptr" +This option enables instrumentation of \*(C+ member function calls, member +accesses and some conversions between pointers to base and derived classes, +to verify the referenced object has the correct dynamic type. +.IP "\fB\-fsanitize=pointer\-overflow\fR" 4 +.IX Item "-fsanitize=pointer-overflow" +This option enables instrumentation of pointer arithmetics. If the pointer +arithmetics overflows, a run-time error is issued. +.IP "\fB\-fsanitize=builtin\fR" 4 +.IX Item "-fsanitize=builtin" +This option enables instrumentation of arguments to selected builtin +functions. If an invalid value is passed to such arguments, a run-time +error is issued. E.g. passing 0 as the argument to \f(CW\*(C`_\|_builtin_ctz\*(C'\fR +or \f(CW\*(C`_\|_builtin_clz\*(C'\fR invokes undefined behavior and is diagnosed +by this option. +.RE +.RS 4 +.Sp +While \fB\-ftrapv\fR causes traps for signed overflows to be emitted, +\&\fB\-fsanitize=undefined\fR gives a diagnostic message. +This currently works only for the C family of languages. +.RE +.IP "\fB\-fno\-sanitize=all\fR" 4 +.IX Item "-fno-sanitize=all" +This option disables all previously enabled sanitizers. +\&\fB\-fsanitize=all\fR is not allowed, as some sanitizers cannot be used +together. +.IP "\fB\-fasan\-shadow\-offset=\fR\fInumber\fR" 4 +.IX Item "-fasan-shadow-offset=number" +This option forces \s-1GCC\s0 to use custom shadow offset in AddressSanitizer checks. +It is useful for experimenting with different shadow memory layouts in +Kernel AddressSanitizer. +.IP "\fB\-fsanitize\-sections=\fR\fIs1\fR\fB,\fR\fIs2\fR\fB,...\fR" 4 +.IX Item "-fsanitize-sections=s1,s2,..." +Sanitize global variables in selected user-defined sections. \fIsi\fR may +contain wildcards. +.IP "\fB\-fsanitize\-recover\fR[\fB=\fR\fIopts\fR]" 4 +.IX Item "-fsanitize-recover[=opts]" +\&\fB\-fsanitize\-recover=\fR controls error recovery mode for sanitizers +mentioned in comma-separated list of \fIopts\fR. Enabling this option +for a sanitizer component causes it to attempt to continue +running the program as if no error happened. This means multiple +runtime errors can be reported in a single program run, and the exit +code of the program may indicate success even when errors +have been reported. The \fB\-fno\-sanitize\-recover=\fR option +can be used to alter +this behavior: only the first detected error is reported +and program then exits with a non-zero exit code. +.Sp +Currently this feature only works for \fB\-fsanitize=undefined\fR (and its suboptions +except for \fB\-fsanitize=unreachable\fR and \fB\-fsanitize=return\fR), +\&\fB\-fsanitize=float\-cast\-overflow\fR, \fB\-fsanitize=float\-divide\-by\-zero\fR, +\&\fB\-fsanitize=bounds\-strict\fR, +\&\fB\-fsanitize=kernel\-address\fR and \fB\-fsanitize=address\fR. +For these sanitizers error recovery is turned on by default, +except \fB\-fsanitize=address\fR, for which this feature is experimental. +\&\fB\-fsanitize\-recover=all\fR and \fB\-fno\-sanitize\-recover=all\fR is also +accepted, the former enables recovery for all sanitizers that support it, +the latter disables recovery for all sanitizers that support it. +.Sp +Even if a recovery mode is turned on the compiler side, it needs to be also +enabled on the runtime library side, otherwise the failures are still fatal. +The runtime library defaults to \f(CW\*(C`halt_on_error=0\*(C'\fR for +ThreadSanitizer and UndefinedBehaviorSanitizer, while default value for +AddressSanitizer is \f(CW\*(C`halt_on_error=1\*(C'\fR. This can be overridden through +setting the \f(CW\*(C`halt_on_error\*(C'\fR flag in the corresponding environment variable. +.Sp +Syntax without an explicit \fIopts\fR parameter is deprecated. It is +equivalent to specifying an \fIopts\fR list of: +.Sp +.Vb 1 +\& undefined,float\-cast\-overflow,float\-divide\-by\-zero,bounds\-strict +.Ve +.IP "\fB\-fsanitize\-address\-use\-after\-scope\fR" 4 +.IX Item "-fsanitize-address-use-after-scope" +Enable sanitization of local variables to detect use-after-scope bugs. +The option sets \fB\-fstack\-reuse\fR to \fBnone\fR. +.IP "\fB\-fsanitize\-undefined\-trap\-on\-error\fR" 4 +.IX Item "-fsanitize-undefined-trap-on-error" +The \fB\-fsanitize\-undefined\-trap\-on\-error\fR option instructs the compiler to +report undefined behavior using \f(CW\*(C`_\|_builtin_trap\*(C'\fR rather than +a \f(CW\*(C`libubsan\*(C'\fR library routine. The advantage of this is that the +\&\f(CW\*(C`libubsan\*(C'\fR library is not needed and is not linked in, so this +is usable even in freestanding environments. +.IP "\fB\-fsanitize\-coverage=trace\-pc\fR" 4 +.IX Item "-fsanitize-coverage=trace-pc" +Enable coverage-guided fuzzing code instrumentation. +Inserts a call to \f(CW\*(C`_\|_sanitizer_cov_trace_pc\*(C'\fR into every basic block. +.IP "\fB\-fsanitize\-coverage=trace\-cmp\fR" 4 +.IX Item "-fsanitize-coverage=trace-cmp" +Enable dataflow guided fuzzing code instrumentation. +Inserts a call to \f(CW\*(C`_\|_sanitizer_cov_trace_cmp1\*(C'\fR, +\&\f(CW\*(C`_\|_sanitizer_cov_trace_cmp2\*(C'\fR, \f(CW\*(C`_\|_sanitizer_cov_trace_cmp4\*(C'\fR or +\&\f(CW\*(C`_\|_sanitizer_cov_trace_cmp8\*(C'\fR for integral comparison with both operands +variable or \f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp1\*(C'\fR, +\&\f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp2\*(C'\fR, +\&\f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp4\*(C'\fR or +\&\f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp8\*(C'\fR for integral comparison with one +operand constant, \f(CW\*(C`_\|_sanitizer_cov_trace_cmpf\*(C'\fR or +\&\f(CW\*(C`_\|_sanitizer_cov_trace_cmpd\*(C'\fR for float or double comparisons and +\&\f(CW\*(C`_\|_sanitizer_cov_trace_switch\*(C'\fR for switch statements. +.IP "\fB\-fcf\-protection=\fR[\fBfull\fR|\fBbranch\fR|\fBreturn\fR|\fBnone\fR]" 4 +.IX Item "-fcf-protection=[full|branch|return|none]" +Enable code instrumentation of control-flow transfers to increase +program security by checking that target addresses of control-flow +transfer instructions (such as indirect function call, function return, +indirect jump) are valid. This prevents diverting the flow of control +to an unexpected target. This is intended to protect against such +threats as Return-oriented Programming (\s-1ROP\s0), and similarly +call/jmp\-oriented programming (\s-1COP/JOP\s0). +.Sp +The value \f(CW\*(C`branch\*(C'\fR tells the compiler to implement checking of +validity of control-flow transfer at the point of indirect branch +instructions, i.e. call/jmp instructions. The value \f(CW\*(C`return\*(C'\fR +implements checking of validity at the point of returning from a +function. The value \f(CW\*(C`full\*(C'\fR is an alias for specifying both +\&\f(CW\*(C`branch\*(C'\fR and \f(CW\*(C`return\*(C'\fR. The value \f(CW\*(C`none\*(C'\fR turns off +instrumentation. +.Sp +The macro \f(CW\*(C`_\|_CET_\|_\*(C'\fR is defined when \fB\-fcf\-protection\fR is +used. The first bit of \f(CW\*(C`_\|_CET_\|_\*(C'\fR is set to 1 for the value +\&\f(CW\*(C`branch\*(C'\fR and the second bit of \f(CW\*(C`_\|_CET_\|_\*(C'\fR is set to 1 for +the \f(CW\*(C`return\*(C'\fR. +.Sp +You can also use the \f(CW\*(C`nocf_check\*(C'\fR attribute to identify +which functions and calls should be skipped from instrumentation. +.Sp +Currently the x86 GNU/Linux target provides an implementation based +on Intel Control-flow Enforcement Technology (\s-1CET\s0) which works for +i686 processor or newer. +.IP "\fB\-fstack\-protector\fR" 4 +.IX Item "-fstack-protector" +Emit extra code to check for buffer overflows, such as stack smashing +attacks. This is done by adding a guard variable to functions with +vulnerable objects. This includes functions that call \f(CW\*(C`alloca\*(C'\fR, and +functions with buffers larger than 8 bytes. The guards are initialized +when a function is entered and then checked when the function exits. +If a guard check fails, an error message is printed and the program exits. +.IP "\fB\-fstack\-protector\-all\fR" 4 +.IX Item "-fstack-protector-all" +Like \fB\-fstack\-protector\fR except that all functions are protected. +.IP "\fB\-fstack\-protector\-strong\fR" 4 +.IX Item "-fstack-protector-strong" +Like \fB\-fstack\-protector\fR but includes additional functions to +be protected \-\-\- those that have local array definitions, or have +references to local frame addresses. +.IP "\fB\-fstack\-protector\-explicit\fR" 4 +.IX Item "-fstack-protector-explicit" +Like \fB\-fstack\-protector\fR but only protects those functions which +have the \f(CW\*(C`stack_protect\*(C'\fR attribute. +.IP "\fB\-fstack\-check\fR" 4 +.IX Item "-fstack-check" +Generate code to verify that you do not go beyond the boundary of the +stack. You should specify this flag if you are running in an +environment with multiple threads, but you only rarely need to specify it in +a single-threaded environment since stack overflow is automatically +detected on nearly all systems if there is only one stack. +.Sp +Note that this switch does not actually cause checking to be done; the +operating system or the language runtime must do that. The switch causes +generation of code to ensure that they see the stack being extended. +.Sp +You can additionally specify a string parameter: \fBno\fR means no +checking, \fBgeneric\fR means force the use of old-style checking, +\&\fBspecific\fR means use the best checking method and is equivalent +to bare \fB\-fstack\-check\fR. +.Sp +Old-style checking is a generic mechanism that requires no specific +target support in the compiler but comes with the following drawbacks: +.RS 4 +.IP "1." 4 +.IX Item "1." +Modified allocation strategy for large objects: they are always +allocated dynamically if their size exceeds a fixed threshold. Note this +may change the semantics of some code. +.IP "2." 4 +.IX Item "2." +Fixed limit on the size of the static frame of functions: when it is +topped by a particular function, stack checking is not reliable and +a warning is issued by the compiler. +.IP "3." 4 +.IX Item "3." +Inefficiency: because of both the modified allocation strategy and the +generic implementation, code performance is hampered. +.RE +.RS 4 +.Sp +Note that old-style stack checking is also the fallback method for +\&\fBspecific\fR if no target support has been added in the compiler. +.Sp +\&\fB\-fstack\-check=\fR is designed for Ada's needs to detect infinite recursion +and stack overflows. \fBspecific\fR is an excellent choice when compiling +Ada code. It is not generally sufficient to protect against stack-clash +attacks. To protect against those you want \fB\-fstack\-clash\-protection\fR. +.RE +.IP "\fB\-fstack\-clash\-protection\fR" 4 +.IX Item "-fstack-clash-protection" +Generate code to prevent stack clash style attacks. When this option is +enabled, the compiler will only allocate one page of stack space at a time +and each page is accessed immediately after allocation. Thus, it prevents +allocations from jumping over any stack guard page provided by the +operating system. +.Sp +Most targets do not fully support stack clash protection. However, on +those targets \fB\-fstack\-clash\-protection\fR will protect dynamic stack +allocations. \fB\-fstack\-clash\-protection\fR may also provide limited +protection for static stack allocations if the target supports +\&\fB\-fstack\-check=specific\fR. +.IP "\fB\-fstack\-limit\-register=\fR\fIreg\fR" 4 +.IX Item "-fstack-limit-register=reg" +.PD 0 +.IP "\fB\-fstack\-limit\-symbol=\fR\fIsym\fR" 4 +.IX Item "-fstack-limit-symbol=sym" +.IP "\fB\-fno\-stack\-limit\fR" 4 +.IX Item "-fno-stack-limit" +.PD +Generate code to ensure that the stack does not grow beyond a certain value, +either the value of a register or the address of a symbol. If a larger +stack is required, a signal is raised at run time. For most targets, +the signal is raised before the stack overruns the boundary, so +it is possible to catch the signal without taking special precautions. +.Sp +For instance, if the stack starts at absolute address \fB0x80000000\fR +and grows downwards, you can use the flags +\&\fB\-fstack\-limit\-symbol=_\|_stack_limit\fR and +\&\fB\-Wl,\-\-defsym,_\|_stack_limit=0x7ffe0000\fR to enforce a stack limit +of 128KB. Note that this may only work with the \s-1GNU\s0 linker. +.Sp +You can locally override stack limit checking by using the +\&\f(CW\*(C`no_stack_limit\*(C'\fR function attribute. +.IP "\fB\-fsplit\-stack\fR" 4 +.IX Item "-fsplit-stack" +Generate code to automatically split the stack before it overflows. +The resulting program has a discontiguous stack which can only +overflow if the program is unable to allocate any more memory. This +is most useful when running threaded programs, as it is no longer +necessary to calculate a good stack size to use for each thread. This +is currently only implemented for the x86 targets running +GNU/Linux. +.Sp +When code compiled with \fB\-fsplit\-stack\fR calls code compiled +without \fB\-fsplit\-stack\fR, there may not be much stack space +available for the latter code to run. If compiling all code, +including library code, with \fB\-fsplit\-stack\fR is not an option, +then the linker can fix up these calls so that the code compiled +without \fB\-fsplit\-stack\fR always has a large stack. Support for +this is implemented in the gold linker in \s-1GNU\s0 binutils release 2.21 +and later. +.IP "\fB\-fvtable\-verify=\fR[\fBstd\fR|\fBpreinit\fR|\fBnone\fR]" 4 +.IX Item "-fvtable-verify=[std|preinit|none]" +This option is only available when compiling \*(C+ code. +It turns on (or off, if using \fB\-fvtable\-verify=none\fR) the security +feature that verifies at run time, for every virtual call, that +the vtable pointer through which the call is made is valid for the type of +the object, and has not been corrupted or overwritten. If an invalid vtable +pointer is detected at run time, an error is reported and execution of the +program is immediately halted. +.Sp +This option causes run-time data structures to be built at program startup, +which are used for verifying the vtable pointers. +The options \fBstd\fR and \fBpreinit\fR +control the timing of when these data structures are built. In both cases the +data structures are built before execution reaches \f(CW\*(C`main\*(C'\fR. Using +\&\fB\-fvtable\-verify=std\fR causes the data structures to be built after +shared libraries have been loaded and initialized. +\&\fB\-fvtable\-verify=preinit\fR causes them to be built before shared +libraries have been loaded and initialized. +.Sp +If this option appears multiple times in the command line with different +values specified, \fBnone\fR takes highest priority over both \fBstd\fR and +\&\fBpreinit\fR; \fBpreinit\fR takes priority over \fBstd\fR. +.IP "\fB\-fvtv\-debug\fR" 4 +.IX Item "-fvtv-debug" +When used in conjunction with \fB\-fvtable\-verify=std\fR or +\&\fB\-fvtable\-verify=preinit\fR, causes debug versions of the +runtime functions for the vtable verification feature to be called. +This flag also causes the compiler to log information about which +vtable pointers it finds for each class. +This information is written to a file named \fIvtv_set_ptr_data.log\fR +in the directory named by the environment variable \fB\s-1VTV_LOGS_DIR\s0\fR +if that is defined or the current working directory otherwise. +.Sp +Note: This feature \fIappends\fR data to the log file. If you want a fresh log +file, be sure to delete any existing one. +.IP "\fB\-fvtv\-counts\fR" 4 +.IX Item "-fvtv-counts" +This is a debugging flag. When used in conjunction with +\&\fB\-fvtable\-verify=std\fR or \fB\-fvtable\-verify=preinit\fR, this +causes the compiler to keep track of the total number of virtual calls +it encounters and the number of verifications it inserts. It also +counts the number of calls to certain run-time library functions +that it inserts and logs this information for each compilation unit. +The compiler writes this information to a file named +\&\fIvtv_count_data.log\fR in the directory named by the environment +variable \fB\s-1VTV_LOGS_DIR\s0\fR if that is defined or the current working +directory otherwise. It also counts the size of the vtable pointer sets +for each class, and writes this information to \fIvtv_class_set_sizes.log\fR +in the same directory. +.Sp +Note: This feature \fIappends\fR data to the log files. To get fresh log +files, be sure to delete any existing ones. +.IP "\fB\-finstrument\-functions\fR" 4 +.IX Item "-finstrument-functions" +Generate instrumentation calls for entry and exit to functions. Just +after function entry and just before function exit, the following +profiling functions are called with the address of the current +function and its call site. (On some platforms, +\&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current +function, so the call site information may not be available to the +profiling functions otherwise.) +.Sp +.Vb 4 +\& void _\|_cyg_profile_func_enter (void *this_fn, +\& void *call_site); +\& void _\|_cyg_profile_func_exit (void *this_fn, +\& void *call_site); +.Ve +.Sp +The first argument is the address of the start of the current function, +which may be looked up exactly in the symbol table. +.Sp +This instrumentation is also done for functions expanded inline in other +functions. The profiling calls indicate where, conceptually, the +inline function is entered and exited. This means that addressable +versions of such functions must be available. If all your uses of a +function are expanded inline, this may mean an additional expansion of +code size. If you use \f(CW\*(C`extern inline\*(C'\fR in your C code, an +addressable version of such functions must be provided. (This is +normally the case anyway, but if you get lucky and the optimizer always +expands the functions inline, you might have gotten away without +providing static copies.) +.Sp +A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in +which case this instrumentation is not done. This can be used, for +example, for the profiling functions listed above, high-priority +interrupt routines, and any functions from which the profiling functions +cannot safely be called (perhaps signal handlers, if the profiling +routines generate output or allocate memory). +.IP "\fB\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-file-list=file,file,..." +Set the list of functions that are excluded from instrumentation (see +the description of \fB\-finstrument\-functions\fR). If the file that +contains a function definition matches with one of \fIfile\fR, then +that function is not instrumented. The match is done on substrings: +if the \fIfile\fR parameter is a substring of the file name, it is +considered to be a match. +.Sp +For example: +.Sp +.Vb 1 +\& \-finstrument\-functions\-exclude\-file\-list=/bits/stl,include/sys +.Ve +.Sp +excludes any inline function defined in files whose pathnames +contain \fI/bits/stl\fR or \fIinclude/sys\fR. +.Sp +If, for some reason, you want to include letter \fB,\fR in one of +\&\fIsym\fR, write \fB,\fR. For example, +\&\fB\-finstrument\-functions\-exclude\-file\-list=',,tmp'\fR +(note the single quote surrounding the option). +.IP "\fB\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-function-list=sym,sym,..." +This is similar to \fB\-finstrument\-functions\-exclude\-file\-list\fR, +but this option sets the list of function names to be excluded from +instrumentation. The function name to be matched is its user-visible +name, such as \f(CW\*(C`vector blah(const vector &)\*(C'\fR, not the +internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The +match is done on substrings: if the \fIsym\fR parameter is a substring +of the function name, it is considered to be a match. For C99 and \*(C+ +extended identifiers, the function name must be given in \s-1UTF\-8,\s0 not +using universal character names. +.IP "\fB\-fpatchable\-function\-entry=\fR\fIN\fR\fB[,\fR\fIM\fR\fB]\fR" 4 +.IX Item "-fpatchable-function-entry=N[,M]" +Generate \fIN\fR NOPs right at the beginning +of each function, with the function entry point before the \fIM\fRth \s-1NOP.\s0 +If \fIM\fR is omitted, it defaults to \f(CW0\fR so the +function entry points to the address just at the first \s-1NOP.\s0 +The \s-1NOP\s0 instructions reserve extra space which can be used to patch in +any desired instrumentation at run time, provided that the code segment +is writable. The amount of space is controllable indirectly via +the number of NOPs; the \s-1NOP\s0 instruction used corresponds to the instruction +emitted by the internal \s-1GCC\s0 back-end interface \f(CW\*(C`gen_nop\*(C'\fR. This behavior +is target-specific and may also depend on the architecture variant and/or +other compilation options. +.Sp +For run-time identification, the starting addresses of these areas, +which correspond to their respective function entries minus \fIM\fR, +are additionally collected in the \f(CW\*(C`_\|_patchable_function_entries\*(C'\fR +section of the resulting binary. +.Sp +Note that the value of \f(CW\*(C`_\|_attribute_\|_ ((patchable_function_entry +(N,M)))\*(C'\fR takes precedence over command-line option +\&\fB\-fpatchable\-function\-entry=N,M\fR. This can be used to increase +the area size or to remove it completely on a single function. +If \f(CW\*(C`N=0\*(C'\fR, no pad location is recorded. +.Sp +The \s-1NOP\s0 instructions are inserted at\-\-\-and maybe before, depending on +\&\fIM\fR\-\-\-the function entry address, even before the prologue. +.SS "Options Controlling the Preprocessor" +.IX Subsection "Options Controlling the Preprocessor" +These options control the C preprocessor, which is run on each C source +file before actual compilation. +.PP +If you use the \fB\-E\fR option, nothing is done except preprocessing. +Some of these options make sense only together with \fB\-E\fR because +they cause the preprocessor output to be unsuitable for actual +compilation. +.PP +In addition to the options listed here, there are a number of options +to control search paths for include files documented in +\&\fBDirectory Options\fR. +Options to control preprocessor diagnostics are listed in +\&\fBWarning Options\fR. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +Predefine \fIname\fR as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-D name=definition" +The contents of \fIdefinition\fR are tokenized and processed as if +they appeared during translation phase three in a \fB#define\fR +directive. In particular, the definition is truncated by +embedded newline characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like +program you may need to use the shell's quoting syntax to protect +characters such as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you should +quote the option. With \fBsh\fR and \fBcsh\fR, +\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they +are given on the command line. All \fB\-imacros\fR \fIfile\fR and +\&\fB\-include\fR \fIfile\fR options are processed after all +\&\fB\-D\fR and \fB\-U\fR options. +.IP "\fB\-U\fR \fIname\fR" 4 +.IX Item "-U name" +Cancel any previous definition of \fIname\fR, either built in or +provided with a \fB\-D\fR option. +.IP "\fB\-include\fR \fIfile\fR" 4 +.IX Item "-include file" +Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first +line of the primary source file. However, the first directory searched +for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR +the directory containing the main source file. If not found there, it +is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search +chain as normal. +.Sp +If multiple \fB\-include\fR options are given, the files are included +in the order they appear on the command line. +.IP "\fB\-imacros\fR \fIfile\fR" 4 +.IX Item "-imacros file" +Exactly like \fB\-include\fR, except that any output produced by +scanning \fIfile\fR is thrown away. Macros it defines remain defined. +This allows you to acquire all the macros from a header without also +processing its declarations. +.Sp +All files specified by \fB\-imacros\fR are processed before all files +specified by \fB\-include\fR. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. The +standard predefined macros remain defined. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Define additional macros required for using the \s-1POSIX\s0 threads library. +You should use this option consistently for both compilation and linking. +This option is supported on GNU/Linux targets, most other Unix derivatives, +and also on x86 Cygwin and MinGW targets. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +Instead of outputting the result of preprocessing, output a rule +suitable for \fBmake\fR describing the dependencies of the main +source file. The preprocessor outputs one \fBmake\fR rule containing +the object file name for that source file, a colon, and the names of all +the included files, including those coming from \fB\-include\fR or +\&\fB\-imacros\fR command-line options. +.Sp +Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the +object file name consists of the name of the source file with any +suffix replaced with object file suffix and with any leading directory +parts removed. If there are many included files then the rule is +split into several lines using \fB\e\fR\-newline. The rule has no +commands. +.Sp +This option does not suppress the preprocessor's debug output, such as +\&\fB\-dM\fR. To avoid mixing such debug output with the dependency +rules you should explicitly specify the dependency output file with +\&\fB\-MF\fR, or use an environment variable like +\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output +is still sent to the regular output stream as normal. +.Sp +Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses +warnings with an implicit \fB\-w\fR. +.IP "\fB\-MM\fR" 4 +.IX Item "-MM" +Like \fB\-M\fR but do not mention header files that are found in +system header directories, nor header files that are included, +directly or indirectly, from such a header. +.Sp +This implies that the choice of angle brackets or double quotes in an +\&\fB#include\fR directive does not in itself determine whether that +header appears in \fB\-MM\fR dependency output. +.IP "\fB\-MF\fR \fIfile\fR" 4 +.IX Item "-MF file" +When used with \fB\-M\fR or \fB\-MM\fR, specifies a +file to write the dependencies to. If no \fB\-MF\fR switch is given +the preprocessor sends the rules to the same place it would send +preprocessed output. +.Sp +When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, +\&\fB\-MF\fR overrides the default dependency output file. +.Sp +If \fIfile\fR is \fI\-\fR, then the dependencies are written to \fIstdout\fR. +.IP "\fB\-MG\fR" 4 +.IX Item "-MG" +In conjunction with an option such as \fB\-M\fR requesting +dependency generation, \fB\-MG\fR assumes missing header files are +generated files and adds them to the dependency list without raising +an error. The dependency filename is taken directly from the +\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR +also suppresses preprocessed output, as a missing header file renders +this useless. +.Sp +This feature is used in automatic updating of makefiles. +.IP "\fB\-MP\fR" 4 +.IX Item "-MP" +This option instructs \s-1CPP\s0 to add a phony target for each dependency +other than the main file, causing each to depend on nothing. These +dummy rules work around errors \fBmake\fR gives if you remove header +files without updating the \fIMakefile\fR to match. +.Sp +This is typical output: +.Sp +.Vb 1 +\& test.o: test.c test.h +\& +\& test.h: +.Ve +.IP "\fB\-MT\fR \fItarget\fR" 4 +.IX Item "-MT target" +Change the target of the rule emitted by dependency generation. By +default \s-1CPP\s0 takes the name of the main input file, deletes any +directory components and any file suffix such as \fB.c\fR, and +appends the platform's usual object suffix. The result is the target. +.Sp +An \fB\-MT\fR option sets the target to be exactly the string you +specify. If you want multiple targets, you can specify them as a single +argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. +.Sp +For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give +.Sp +.Vb 1 +\& $(objpfx)foo.o: foo.c +.Ve +.IP "\fB\-MQ\fR \fItarget\fR" 4 +.IX Item "-MQ target" +Same as \fB\-MT\fR, but it quotes any characters which are special to +Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives +.Sp +.Vb 1 +\& $$(objpfx)foo.o: foo.c +.Ve +.Sp +The default target is automatically quoted, as if it were given with +\&\fB\-MQ\fR. +.IP "\fB\-MD\fR" 4 +.IX Item "-MD" +\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that +\&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on +whether an \fB\-o\fR option is given. If it is, the driver uses its +argument but with a suffix of \fI.d\fR, otherwise it takes the name +of the input file, removes any directory components and suffix, and +applies a \fI.d\fR suffix. +.Sp +If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any +\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR +is understood to specify a target object file. +.Sp +Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate +a dependency output file as a side effect of the compilation process. +.IP "\fB\-MMD\fR" 4 +.IX Item "-MMD" +Like \fB\-MD\fR except mention only user header files, not system +header files. +.IP "\fB\-fpreprocessed\fR" 4 +.IX Item "-fpreprocessed" +Indicate to the preprocessor that the input file has already been +preprocessed. This suppresses things like macro expansion, trigraph +conversion, escaped newline splicing, and processing of most directives. +The preprocessor still recognizes and removes comments, so that you can +pass a file preprocessed with \fB\-C\fR to the compiler without +problems. In this mode the integrated preprocessor is little more than +a tokenizer for the front ends. +.Sp +\&\fB\-fpreprocessed\fR is implicit if the input file has one of the +extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the +extensions that \s-1GCC\s0 uses for preprocessed files created by +\&\fB\-save\-temps\fR. +.IP "\fB\-fdirectives\-only\fR" 4 +.IX Item "-fdirectives-only" +When preprocessing, handle directives, but do not expand macros. +.Sp +The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR +options. +.Sp +With \fB\-E\fR, preprocessing is limited to the handling of directives +such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other +preprocessor operations, such as macro expansion and trigraph +conversion are not performed. In addition, the \fB\-dD\fR option is +implicitly enabled. +.Sp +With \fB\-fpreprocessed\fR, predefinition of command line and most +builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are +contextually dependent, are handled normally. This enables compilation of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.Sp +With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for +\&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.IP "\fB\-fdollars\-in\-identifiers\fR" 4 +.IX Item "-fdollars-in-identifiers" +Accept \fB$\fR in identifiers. +.IP "\fB\-fextended\-identifiers\fR" 4 +.IX Item "-fextended-identifiers" +Accept universal character names in identifiers. This option is +enabled by default for C99 (and later C standard versions) and \*(C+. +.IP "\fB\-fno\-canonical\-system\-headers\fR" 4 +.IX Item "-fno-canonical-system-headers" +When preprocessing, do not shorten system header paths with canonicalization. +.IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 +.IX Item "-ftabstop=width" +Set the distance between tab stops. This helps the preprocessor report +correct column numbers in warnings or errors, even if tabs appear on the +line. If the value is less than 1 or greater than 100, the option is +ignored. The default is 8. +.IP "\fB\-ftrack\-macro\-expansion\fR[\fB=\fR\fIlevel\fR]" 4 +.IX Item "-ftrack-macro-expansion[=level]" +Track locations of tokens across macro expansions. This allows the +compiler to emit diagnostic about the current macro expansion stack +when a compilation error occurs in a macro expansion. Using this +option makes the preprocessor and the compiler consume more +memory. The \fIlevel\fR parameter can be used to choose the level of +precision of token location tracking thus decreasing the memory +consumption if necessary. Value \fB0\fR of \fIlevel\fR de-activates +this option. Value \fB1\fR tracks tokens locations in a +degraded mode for the sake of minimal memory overhead. In this mode +all tokens resulting from the expansion of an argument of a +function-like macro have the same location. Value \fB2\fR tracks +tokens locations completely. This value is the most memory hungry. +When this option is given no argument, the default parameter value is +\&\fB2\fR. +.Sp +Note that \f(CW\*(C`\-ftrack\-macro\-expansion=2\*(C'\fR is activated by default. +.IP "\fB\-fmacro\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fmacro-prefix-map=old=new" +When preprocessing files residing in directory \fI\fIold\fI\fR, +expand the \f(CW\*(C`_\|_FILE_\|_\*(C'\fR and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR macros as if the +files resided in directory \fI\fInew\fI\fR instead. This can be used +to change an absolute path to a relative path by using \fI.\fR for +\&\fInew\fR which can result in more reproducible builds that are +location independent. This option also affects +\&\f(CW\*(C`_\|_builtin_FILE()\*(C'\fR during compilation. See also +\&\fB\-ffile\-prefix\-map\fR. +.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fexec-charset=charset" +Set the execution character set, used for string and character +constants. The default is \s-1UTF\-8.\s0 \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fwide-exec-charset=charset" +Set the wide execution character set, used for wide string and +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16,\s0 whichever +corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with +\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported +by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have +problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. +.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 +.IX Item "-finput-charset=charset" +Set the input character set, used for translation from the character +set of the input file to the source character set used by \s-1GCC.\s0 If the +locale does not specify, or \s-1GCC\s0 cannot get this information from the +locale, the default is \s-1UTF\-8.\s0 This can be overridden by either the locale +or this command-line option. Currently the command-line option takes +precedence if there's a conflict. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fpch\-deps\fR" 4 +.IX Item "-fpch-deps" +When using precompiled headers, this flag +causes the dependency-output flags to also list the files from the +precompiled header's dependencies. If not specified, only the +precompiled header are listed and not the files that were used to +create it, because those files are not consulted when a precompiled +header is used. +.IP "\fB\-fpch\-preprocess\fR" 4 +.IX Item "-fpch-preprocess" +This option allows use of a precompiled header together with \fB\-E\fR. It inserts a special \f(CW\*(C`#pragma\*(C'\fR, +\&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark +the place where the precompiled header was found, and its \fIfilename\fR. +When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR +and loads the \s-1PCH.\s0 +.Sp +This option is off by default, because the resulting preprocessed output +is only really suitable as input to \s-1GCC.\s0 It is switched on by +\&\fB\-save\-temps\fR. +.Sp +You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is +safe to edit the filename if the \s-1PCH\s0 file is available in a different +location. The filename may be absolute or it may be relative to \s-1GCC\s0's +current directory. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor +emits, after the initial linemarker, a second linemarker with the +current working directory followed by two slashes. \s-1GCC\s0 uses this +directory, when it's present in the preprocessed input, as the +directory emitted as the current working directory in some debugging +information formats. This option is implicitly enabled if debugging +information is enabled, but this can be inhibited with the negated +form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is +present in the command line, this option has no effect, since no +\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. +.IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A predicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR +\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because +it does not use shell special characters. +.IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A -predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it +causes the preprocessor to treat comments as tokens in their own right. +For example, comments appearing at the start of what would be a +directive line have the effect of turning that line into an ordinary +source line, since the first token on the line is no longer a \fB#\fR. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is +like \fB\-C\fR, except that comments contained within macros are +also passed through to the output file where the macro is expanded. +.Sp +In addition to the side effects of the \fB\-C\fR option, the +\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro +to be converted to C\-style comments. This is to prevent later use +of that macro from inadvertently commenting out the remainder of +the source line. +.Sp +The \fB\-CC\fR option is generally used to support lint comments. +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that is +not C code, and will be sent to a program which might be confused by the +linemarkers. +.IP "\fB\-traditional\fR" 4 +.IX Item "-traditional" +.PD 0 +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +.PD +Try to imitate the behavior of pre-standard C preprocessors, as +opposed to \s-1ISO C\s0 preprocessors. +See the \s-1GNU CPP\s0 manual for details. +.Sp +Note that \s-1GCC\s0 does not otherwise attempt to emulate a pre-standard +C compiler, and these options are only supported with the \fB\-E\fR +switch, or when invoking \s-1CPP\s0 explicitly. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Support \s-1ISO C\s0 trigraphs. +These are three-character sequences, all starting with \fB??\fR, that +are defined by \s-1ISO C\s0 to stand for single characters. For example, +\&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character +constant for a newline. +.Sp +The nine trigraphs and their replacements are +.Sp +.Vb 2 +\& Trigraph: ??( ??) ??< ??> ??= ??/ ??\*(Aq ??! ??\- +\& Replacement: [ ] { } # \e ^ | ~ +.Ve +.Sp +By default, \s-1GCC\s0 ignores trigraphs, but in +standard-conforming modes it converts them. See the \fB\-std\fR and +\&\fB\-ansi\fR options. +.IP "\fB\-remap\fR" 4 +.IX Item "-remap" +Enable special code to work around file systems which only permit very +short file names, such as MS-DOS. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the +\&\fB#include\fR stack it is. Precompiled header files are also +printed, even if they are found to be invalid; an invalid precompiled +header file is printed with \fB...x\fR and a valid one with \fB...!\fR . +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +Says to make debugging dumps during compilation as specified by +\&\fIletters\fR. The flags documented here are those relevant to the +preprocessor. Other \fIletters\fR are interpreted +by the compiler proper, or reserved for future versions of \s-1GCC,\s0 and so +are silently ignored. If you specify \fIletters\fR whose behavior +conflicts, the result is undefined. +.RS 4 +.IP "\fB\-dM\fR" 4 +.IX Item "-dM" +Instead of the normal output, generate a list of \fB#define\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way of +finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.h\fR, the command +.Sp +.Vb 1 +\& touch foo.h; cpp \-dM foo.h +.Ve +.Sp +shows all the predefined macros. +.Sp +If you use \fB\-dM\fR without the \fB\-E\fR option, \fB\-dM\fR is +interpreted as a synonym for \fB\-fdump\-rtl\-mach\fR. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Like \fB\-dM\fR except in two respects: it does \fInot\fR include the +predefined macros, and it outputs \fIboth\fR the \fB#define\fR +directives and the result of preprocessing. Both kinds of output go to +the standard output file. +.IP "\fB\-dN\fR" 4 +.IX Item "-dN" +Like \fB\-dD\fR, but emit only the macro names, not their expansions. +.IP "\fB\-dI\fR" 4 +.IX Item "-dI" +Output \fB#include\fR directives in addition to the result of +preprocessing. +.IP "\fB\-dU\fR" 4 +.IX Item "-dU" +Like \fB\-dD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and +\&\fB#undef\fR directives are also output for macros tested but +undefined at the time. +.RE +.RS 4 +.RE +.IP "\fB\-fdebug\-cpp\fR" 4 +.IX Item "-fdebug-cpp" +This option is only useful for debugging \s-1GCC.\s0 When used from \s-1CPP\s0 or with +\&\fB\-E\fR, it dumps debugging information about location maps. Every +token in the output is preceded by the dump of the map its location +belongs to. +.Sp +When used from \s-1GCC\s0 without \fB\-E\fR, this option has no effect. +.IP "\fB\-Wp,\fR\fIoption\fR" 4 +.IX Item "-Wp,option" +You can use \fB\-Wp,\fR\fIoption\fR to bypass the compiler driver +and pass \fIoption\fR directly through to the preprocessor. If +\&\fIoption\fR contains commas, it is split into multiple options at the +commas. However, many options are modified, translated or interpreted +by the compiler driver before being passed to the preprocessor, and +\&\fB\-Wp\fR forcibly bypasses this phase. The preprocessor's direct +interface is undocumented and subject to change, so whenever possible +you should avoid using \fB\-Wp\fR and let the driver handle the +options instead. +.IP "\fB\-Xpreprocessor\fR \fIoption\fR" 4 +.IX Item "-Xpreprocessor option" +Pass \fIoption\fR as an option to the preprocessor. You can use this to +supply system-specific preprocessor options that \s-1GCC\s0 does not +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument. +.IP "\fB\-no\-integrated\-cpp\fR" 4 +.IX Item "-no-integrated-cpp" +Perform preprocessing as a separate pass before compilation. +By default, \s-1GCC\s0 performs preprocessing as an integrated part of +input tokenization and parsing. +If this option is provided, the appropriate language front end +(\fBcc1\fR, \fBcc1plus\fR, or \fBcc1obj\fR for C, \*(C+, +and Objective-C, respectively) is instead invoked twice, +once for preprocessing only and once for actual compilation +of the preprocessed input. +This option may be useful in conjunction with the \fB\-B\fR or +\&\fB\-wrapper\fR options to specify an alternate preprocessor or +perform additional processing of the program source between +normal preprocessing and compilation. +.SS "Passing Options to the Assembler" +.IX Subsection "Passing Options to the Assembler" +You can pass options to the assembler. +.IP "\fB\-Wa,\fR\fIoption\fR" 4 +.IX Item "-Wa,option" +Pass \fIoption\fR as an option to the assembler. If \fIoption\fR +contains commas, it is split into multiple options at the commas. +.IP "\fB\-Xassembler\fR \fIoption\fR" 4 +.IX Item "-Xassembler option" +Pass \fIoption\fR as an option to the assembler. You can use this to +supply system-specific assembler options that \s-1GCC\s0 does not +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xassembler\fR twice, once for the option and once for the argument. +.SS "Options for Linking" +.IX Subsection "Options for Linking" +These options come into play when the compiler links object files into +an executable output file. They are meaningless if the compiler is +not doing a link step. +.IP "\fIobject-file-name\fR" 4 +.IX Item "object-file-name" +A file name that does not end in a special recognized suffix is +considered to name an object file or library. (Object files are +distinguished from libraries by the linker according to the file +contents.) If linking is done, these object files are used as input +to the linker. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.IP "\fB\-E\fR" 4 +.IX Item "-E" +.PD +If any of these options is used, then the linker is not run, and +object file names should not be used as arguments. +.IP "\fB\-flinker\-output=\fR\fItype\fR" 4 +.IX Item "-flinker-output=type" +This option controls the code generation of the link time optimizer. By +default the linker output is determined by the linker plugin automatically. For +debugging the compiler and in the case of incremental linking to non-lto object +file is desired, it may be useful to control the type manually. +.Sp +If \fItype\fR is \fBexec\fR the code generation is configured to produce static +binary. In this case \fB\-fpic\fR and \fB\-fpie\fR are both disabled. +.Sp +If \fItype\fR is \fBdyn\fR the code generation is configured to produce shared +library. In this case \fB\-fpic\fR or \fB\-fPIC\fR is preserved, but not +enabled automatically. This makes it possible to build shared libraries without +position independent code on architectures this is possible, i.e. on x86. +.Sp +If \fItype\fR is \fBpie\fR the code generation is configured to produce +\&\fB\-fpie\fR executable. This result in similar optimizations as \fBexec\fR +except that \fB\-fpie\fR is not disabled if specified at compilation time. +.Sp +If \fItype\fR is \fBrel\fR the compiler assumes that incremental linking is +done. The sections containing intermediate code for link-time optimization are +merged, pre-optimized, and output to the resulting object file. In addition, if +\&\fB\-ffat\-lto\-objects\fR is specified the binary code is produced for future +non-lto linking. The object file produced by incremental linking will be smaller +than a static library produced from the same object files. At link-time the +result of incremental linking will also load faster to compiler than a static +library assuming that majority of objects in the library are used. +.Sp +Finally \fBnolto-rel\fR configure compiler to for incremental linking where +code generation is forced, final binary is produced and the intermediate code +for later link-time optimization is stripped. When multiple object files are +linked together the resulting code will be optimized better than with link time +optimizations disabled (for example, the cross-module inlining will happen), +most of benefits of whole program optimizations are however lost. +.Sp +During the incremental link (by \fB\-r\fR) the linker plugin will default to +\&\fBrel\fR. With current interfaces to \s-1GNU\s0 Binutils it is however not +possible to link incrementally \s-1LTO\s0 objects and non-LTO objects into a single +mixed object file. In the case any of object files in incremental link cannot +be used for link-time optimization the linker plugin will output warning and +use \fBnolto-rel\fR. To maintain the whole program optimization it is +recommended to link such objects into static library instead. Alternatively it +is possible to use H.J. Lu's binutils with support for mixed objects. +.IP "\fB\-fuse\-ld=bfd\fR" 4 +.IX Item "-fuse-ld=bfd" +Use the \fBbfd\fR linker instead of the default linker. +.IP "\fB\-fuse\-ld=gold\fR" 4 +.IX Item "-fuse-ld=gold" +Use the \fBgold\fR linker instead of the default linker. +.IP "\fB\-fuse\-ld=lld\fR" 4 +.IX Item "-fuse-ld=lld" +Use the \s-1LLVM\s0 \fBlld\fR linker instead of the default linker. +.IP "\fB\-l\fR\fIlibrary\fR" 4 +.IX Item "-llibrary" +.PD 0 +.IP "\fB\-l\fR \fIlibrary\fR" 4 +.IX Item "-l library" +.PD +Search the library named \fIlibrary\fR when linking. (The second +alternative with the library as a separate argument is only for +\&\s-1POSIX\s0 compliance and is not recommended.) +.Sp +The \fB\-l\fR option is passed directly to the linker by \s-1GCC.\s0 Refer +to your linker documentation for exact details. The general +description below applies to the \s-1GNU\s0 linker. +.Sp +The linker searches a standard list of directories for the library. +The directories searched include several standard system directories +plus any that you specify with \fB\-L\fR. +.Sp +Static libraries are archives of object files, and have file names +like \fIlib\fIlibrary\fI.a\fR. Some targets also support shared +libraries, which typically have names like \fIlib\fIlibrary\fI.so\fR. +If both static and shared libraries are found, the linker gives +preference to linking with the shared library unless the +\&\fB\-static\fR option is used. +.Sp +It makes a difference where in the command you write this option; the +linker searches and processes libraries and object files in the order they +are specified. Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR +after file \fIfoo.o\fR but before \fIbar.o\fR. If \fIbar.o\fR refers +to functions in \fBz\fR, those functions may not be loaded. +.IP "\fB\-lobjc\fR" 4 +.IX Item "-lobjc" +You need this special case of the \fB\-l\fR option in order to +link an Objective-C or Objective\-\*(C+ program. +.IP "\fB\-nostartfiles\fR" 4 +.IX Item "-nostartfiles" +Do not use the standard system startup files when linking. +The standard system libraries are used normally, unless \fB\-nostdlib\fR, +\&\fB\-nolibc\fR, or \fB\-nodefaultlibs\fR is used. +.IP "\fB\-nodefaultlibs\fR" 4 +.IX Item "-nodefaultlibs" +Do not use the standard system libraries when linking. +Only the libraries you specify are passed to the linker, and options +specifying linkage of the system libraries, such as \fB\-static\-libgcc\fR +or \fB\-shared\-libgcc\fR, are ignored. +The standard startup files are used normally, unless \fB\-nostartfiles\fR +is used. +.Sp +The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, +\&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.IP "\fB\-nolibc\fR" 4 +.IX Item "-nolibc" +Do not use the C library or system libraries tightly coupled with it when +linking. Still link with the startup files, \fIlibgcc\fR or toolchain +provided language support libraries such as \fIlibgnat\fR, \fIlibgfortran\fR +or \fIlibstdc++\fR unless options preventing their inclusion are used as +well. This typically removes \fB\-lc\fR from the link command line, as well +as system libraries that normally go with it and become meaningless when +absence of a C library is assumed, for example \fB\-lpthread\fR or +\&\fB\-lm\fR in some configurations. This is intended for bare-board +targets when there is indeed no C library available. +.IP "\fB\-nostdlib\fR" 4 +.IX Item "-nostdlib" +Do not use the standard system startup files or libraries when linking. +No startup files and only the libraries you specify are passed to +the linker, and options specifying linkage of the system libraries, such as +\&\fB\-static\-libgcc\fR or \fB\-shared\-libgcc\fR, are ignored. +.Sp +The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR, +\&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.Sp +One of the standard libraries bypassed by \fB\-nostdlib\fR and +\&\fB\-nodefaultlibs\fR is \fIlibgcc.a\fR, a library of internal subroutines +which \s-1GCC\s0 uses to overcome shortcomings of particular machines, or special +needs for some languages. +.Sp +In most cases, you need \fIlibgcc.a\fR even when you want to avoid +other standard libraries. In other words, when you specify \fB\-nostdlib\fR +or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well. +This ensures that you have no unresolved references to internal \s-1GCC\s0 +library subroutines. +(An example of such an internal subroutine is \f(CW\*(C`_\|_main\*(C'\fR, used to ensure \*(C+ +constructors are called.) +.IP "\fB\-e\fR \fIentry\fR" 4 +.IX Item "-e entry" +.PD 0 +.IP "\fB\-\-entry=\fR\fIentry\fR" 4 +.IX Item "--entry=entry" +.PD +Specify that the program entry point is \fIentry\fR. The argument is +interpreted by the linker; the \s-1GNU\s0 linker accepts either a symbol name +or an address. +.IP "\fB\-pie\fR" 4 +.IX Item "-pie" +Produce a dynamically linked position independent executable on targets +that support it. For predictable results, you must also specify the same +set of options used for compilation (\fB\-fpie\fR, \fB\-fPIE\fR, +or model suboptions) when you specify this linker option. +.IP "\fB\-no\-pie\fR" 4 +.IX Item "-no-pie" +Don't produce a dynamically linked position independent executable. +.IP "\fB\-static\-pie\fR" 4 +.IX Item "-static-pie" +Produce a static position independent executable on targets that support +it. A static position independent executable is similar to a static +executable, but can be loaded at any address without a dynamic linker. +For predictable results, you must also specify the same set of options +used for compilation (\fB\-fpie\fR, \fB\-fPIE\fR, or model +suboptions) when you specify this linker option. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Link with the \s-1POSIX\s0 threads library. This option is supported on +GNU/Linux targets, most other Unix derivatives, and also on +x86 Cygwin and MinGW targets. On some targets this option also sets +flags for the preprocessor, so it should be used consistently for both +compilation and linking. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +Produce a relocatable object as output. This is also known as partial +linking. +.IP "\fB\-rdynamic\fR" 4 +.IX Item "-rdynamic" +Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets +that support it. This instructs the linker to add all symbols, not +only used ones, to the dynamic symbol table. This option is needed +for some uses of \f(CW\*(C`dlopen\*(C'\fR or to allow obtaining backtraces +from within a program. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +Remove all symbol table and relocation information from the executable. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +On systems that support dynamic linking, this overrides \fB\-pie\fR +and prevents linking with the shared libraries. On other systems, this +option has no effect. +.IP "\fB\-shared\fR" 4 +.IX Item "-shared" +Produce a shared object which can then be linked with other objects to +form an executable. Not all systems support this option. For predictable +results, you must also specify the same set of options used for compilation +(\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions) when +you specify this linker option.[1] +.IP "\fB\-shared\-libgcc\fR" 4 +.IX Item "-shared-libgcc" +.PD 0 +.IP "\fB\-static\-libgcc\fR" 4 +.IX Item "-static-libgcc" +.PD +On systems that provide \fIlibgcc\fR as a shared library, these options +force the use of either the shared or static version, respectively. +If no shared version of \fIlibgcc\fR was built when the compiler was +configured, these options have no effect. +.Sp +There are several situations in which an application should use the +shared \fIlibgcc\fR instead of the static version. The most common +of these is when the application wishes to throw and catch exceptions +across different shared libraries. In that case, each of the libraries +as well as the application itself should use the shared \fIlibgcc\fR. +.Sp +Therefore, the G++ driver automatically adds \fB\-shared\-libgcc\fR +whenever you build a shared library or a main executable, because \*(C+ +programs typically use exceptions, so this is the right thing to do. +.Sp +If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may +find that they are not always linked with the shared \fIlibgcc\fR. +If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker +or a \s-1GNU\s0 linker that does not support option \fB\-\-eh\-frame\-hdr\fR, +it links the shared version of \fIlibgcc\fR into shared libraries +by default. Otherwise, it takes advantage of the linker and optimizes +away the linking with the shared version of \fIlibgcc\fR, linking with +the static version of libgcc by default. This allows exceptions to +propagate through such shared libraries, without incurring relocation +costs at library load time. +.Sp +However, if a library or main executable is supposed to throw or catch +exceptions, you must link it using the G++ driver, or using the option +\&\fB\-shared\-libgcc\fR, such that it is linked with the shared +\&\fIlibgcc\fR. +.IP "\fB\-static\-libasan\fR" 4 +.IX Item "-static-libasan" +When the \fB\-fsanitize=address\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBlibasan\fR. If +\&\fIlibasan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIlibasan\fR. The \fB\-static\-libasan\fR option directs the \s-1GCC\s0 +driver to link \fIlibasan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-libtsan\fR" 4 +.IX Item "-static-libtsan" +When the \fB\-fsanitize=thread\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBlibtsan\fR. If +\&\fIlibtsan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIlibtsan\fR. The \fB\-static\-libtsan\fR option directs the \s-1GCC\s0 +driver to link \fIlibtsan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-liblsan\fR" 4 +.IX Item "-static-liblsan" +When the \fB\-fsanitize=leak\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBliblsan\fR. If +\&\fIliblsan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIliblsan\fR. The \fB\-static\-liblsan\fR option directs the \s-1GCC\s0 +driver to link \fIliblsan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-libubsan\fR" 4 +.IX Item "-static-libubsan" +When the \fB\-fsanitize=undefined\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBlibubsan\fR. If +\&\fIlibubsan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIlibubsan\fR. The \fB\-static\-libubsan\fR option directs the \s-1GCC\s0 +driver to link \fIlibubsan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-libstdc++\fR" 4 +.IX Item "-static-libstdc++" +When the \fBg++\fR program is used to link a \*(C+ program, it +normally automatically links against \fBlibstdc++\fR. If +\&\fIlibstdc++\fR is available as a shared library, and the +\&\fB\-static\fR option is not used, then this links against the +shared version of \fIlibstdc++\fR. That is normally fine. However, it +is sometimes useful to freeze the version of \fIlibstdc++\fR used by +the program without going all the way to a fully static link. The +\&\fB\-static\-libstdc++\fR option directs the \fBg++\fR driver to +link \fIlibstdc++\fR statically, without necessarily linking other +libraries statically. +.IP "\fB\-symbolic\fR" 4 +.IX Item "-symbolic" +Bind references to global symbols when building a shared object. Warn +about any unresolved references (unless overridden by the link editor +option \fB\-Xlinker \-z \-Xlinker defs\fR). Only a few systems support +this option. +.IP "\fB\-T\fR \fIscript\fR" 4 +.IX Item "-T script" +Use \fIscript\fR as the linker script. This option is supported by most +systems using the \s-1GNU\s0 linker. On some targets, such as bare-board +targets without an operating system, the \fB\-T\fR option may be required +when linking to avoid references to undefined symbols. +.IP "\fB\-Xlinker\fR \fIoption\fR" 4 +.IX Item "-Xlinker option" +Pass \fIoption\fR as an option to the linker. You can use this to +supply system-specific linker options that \s-1GCC\s0 does not recognize. +.Sp +If you want to pass an option that takes a separate argument, you must use +\&\fB\-Xlinker\fR twice, once for the option and once for the argument. +For example, to pass \fB\-assert definitions\fR, you must write +\&\fB\-Xlinker \-assert \-Xlinker definitions\fR. It does not work to write +\&\fB\-Xlinker \*(L"\-assert definitions\*(R"\fR, because this passes the entire +string as a single argument, which is not what the linker expects. +.Sp +When using the \s-1GNU\s0 linker, it is usually more convenient to pass +arguments to linker options using the \fIoption\fR\fB=\fR\fIvalue\fR +syntax than as separate arguments. For example, you can specify +\&\fB\-Xlinker \-Map=output.map\fR rather than +\&\fB\-Xlinker \-Map \-Xlinker output.map\fR. Other linkers may not support +this syntax for command-line options. +.IP "\fB\-Wl,\fR\fIoption\fR" 4 +.IX Item "-Wl,option" +Pass \fIoption\fR as an option to the linker. If \fIoption\fR contains +commas, it is split into multiple options at the commas. You can use this +syntax to pass an argument to the option. +For example, \fB\-Wl,\-Map,output.map\fR passes \fB\-Map output.map\fR to the +linker. When using the \s-1GNU\s0 linker, you can also get the same effect with +\&\fB\-Wl,\-Map=output.map\fR. +.IP "\fB\-u\fR \fIsymbol\fR" 4 +.IX Item "-u symbol" +Pretend the symbol \fIsymbol\fR is undefined, to force linking of +library modules to define it. You can use \fB\-u\fR multiple times with +different symbols to force loading of additional library modules. +.IP "\fB\-z\fR \fIkeyword\fR" 4 +.IX Item "-z keyword" +\&\fB\-z\fR is passed directly on to the linker along with the keyword +\&\fIkeyword\fR. See the section in the documentation of your linker for +permitted values and their meanings. +.SS "Options for Directory Search" +.IX Subsection "Options for Directory Search" +These options specify directories to search for header files, for +libraries and for parts of the compiler: +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +.PD 0 +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +.PD +Add the directory \fIdir\fR to the list of directories to be searched +for header files during preprocessing. +If \fIdir\fR begins with \fB=\fR or \f(CW$SYSROOT\fR, then the \fB=\fR +or \f(CW$SYSROOT\fR is replaced by the sysroot prefix; see +\&\fB\-\-sysroot\fR and \fB\-isysroot\fR. +.Sp +Directories specified with \fB\-iquote\fR apply only to the quote +form of the directive, \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. +Directories specified with \fB\-I\fR, \fB\-isystem\fR, +or \fB\-idirafter\fR apply to lookup for both the +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR and +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR directives. +.Sp +You can specify any number or combination of these options on the +command line to search for header files in several directories. +The lookup order is as follows: +.RS 4 +.IP "1." 4 +.IX Item "1." +For the quote form of the include directive, the directory of the current +file is searched first. +.IP "2." 4 +.IX Item "2." +For the quote form of the include directive, the directories specified +by \fB\-iquote\fR options are searched in left-to-right order, +as they appear on the command line. +.IP "3." 4 +.IX Item "3." +Directories specified with \fB\-I\fR options are scanned in +left-to-right order. +.IP "4." 4 +.IX Item "4." +Directories specified with \fB\-isystem\fR options are scanned in +left-to-right order. +.IP "5." 4 +.IX Item "5." +Standard system directories are scanned. +.IP "6." 4 +.IX Item "6." +Directories specified with \fB\-idirafter\fR options are scanned in +left-to-right order. +.RE +.RS 4 +.Sp +You can use \fB\-I\fR to override a system header +file, substituting your own version, since these directories are +searched before the standard system header file directories. +However, you should +not use this option to add directories that contain vendor-supplied +system header files; use \fB\-isystem\fR for that. +.Sp +The \fB\-isystem\fR and \fB\-idirafter\fR options also mark the directory +as a system directory, so that it gets the same special treatment that +is applied to the standard system directories. +.Sp +If a standard system include directory, or a directory specified with +\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR +option is ignored. The directory is still searched but as a +system directory at its normal position in the system include chain. +This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and +the ordering for the \f(CW\*(C`#include_next\*(C'\fR directive are not inadvertently +changed. +If you really need to change the search order for system directories, +use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options. +.RE +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +Split the include path. +This option has been deprecated. Please use \fB\-iquote\fR instead for +\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR +option. +.Sp +Any directories specified with \fB\-I\fR +options before \fB\-I\-\fR are searched only for headers requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are +specified with \fB\-I\fR options after the \fB\-I\-\fR, those +directories are searched for all \fB#include\fR directives. +.Sp +In addition, \fB\-I\-\fR inhibits the use of the directory of the current +file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. There is no way to override this effect of \fB\-I\-\fR. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the prefix represents a directory, you should include the +final \fB/\fR. +.IP "\fB\-iwithprefix\fR \fIdir\fR" 4 +.IX Item "-iwithprefix dir" +.PD 0 +.IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 +.IX Item "-iwithprefixbefore dir" +.PD +Append \fIdir\fR to the prefix specified previously with +\&\fB\-iprefix\fR, and add the resulting directory to the include search +path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR +would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files (except for Darwin targets, where it applies to both header +files and libraries). See the \fB\-\-sysroot\fR option for more +information. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing +target-specific \*(C+ headers. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. +Only the directories explicitly specified with \fB\-I\fR, +\&\fB\-iquote\fR, \fB\-isystem\fR, and/or \fB\-idirafter\fR +options (and the directory of the current file, if appropriate) +are searched. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the \*(C+\-specific standard directories, +but do still search the other standard directories. (This option is +used when building the \*(C+ library.) +.IP "\fB\-iplugindir=\fR\fIdir\fR" 4 +.IX Item "-iplugindir=dir" +Set the directory to search for plugins that are passed +by \fB\-fplugin=\fR\fIname\fR instead of +\&\fB\-fplugin=\fR\fIpath\fR\fB/\fR\fIname\fR\fB.so\fR. This option is not meant +to be used by the user, but only passed by the driver. +.IP "\fB\-L\fR\fIdir\fR" 4 +.IX Item "-Ldir" +Add directory \fIdir\fR to the list of directories to be searched +for \fB\-l\fR. +.IP "\fB\-B\fR\fIprefix\fR" 4 +.IX Item "-Bprefix" +This option specifies where to find the executables, libraries, +include files, and data files of the compiler itself. +.Sp +The compiler driver program runs one or more of the subprograms +\&\fBcpp\fR, \fBcc1\fR, \fBas\fR and \fBld\fR. It tries +\&\fIprefix\fR as a prefix for each program it tries to run, both with and +without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR for the corresponding target +machine and compiler version. +.Sp +For each subprogram to be run, the compiler driver first tries the +\&\fB\-B\fR prefix, if any. If that name is not found, or if \fB\-B\fR +is not specified, the driver tries two standard prefixes, +\&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR. If neither of +those results in a file name that is found, the unmodified program +name is searched for using the directories specified in your +\&\fB\s-1PATH\s0\fR environment variable. +.Sp +The compiler checks to see if the path provided by \fB\-B\fR +refers to a directory, and if necessary it adds a directory +separator character at the end of the path. +.Sp +\&\fB\-B\fR prefixes that effectively specify directory names also apply +to libraries in the linker, because the compiler translates these +options into \fB\-L\fR options for the linker. They also apply to +include files in the preprocessor, because the compiler translates these +options into \fB\-isystem\fR options for the preprocessor. In this case, +the compiler appends \fBinclude\fR to the prefix. +.Sp +The runtime support file \fIlibgcc.a\fR can also be searched for using +the \fB\-B\fR prefix, if needed. If it is not found there, the two +standard prefixes above are tried, and that is all. The file is left +out of the link if it is not found by those means. +.Sp +Another way to specify a prefix much like the \fB\-B\fR prefix is to use +the environment variable \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.Sp +As a special kludge, if the path provided by \fB\-B\fR is +\&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to +9, then it is replaced by \fI[dir/]include\fR. This is to help +with boot-strapping the compiler. +.IP "\fB\-no\-canonical\-prefixes\fR" 4 +.IX Item "-no-canonical-prefixes" +Do not expand any symbolic links, resolve references to \fB/../\fR +or \fB/./\fR, or make the path absolute when generating a relative +prefix. +.IP "\fB\-\-sysroot=\fR\fIdir\fR" 4 +.IX Item "--sysroot=dir" +Use \fIdir\fR as the logical root directory for headers and libraries. +For example, if the compiler normally searches for headers in +\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it instead +searches \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR. +.Sp +If you use both this option and the \fB\-isysroot\fR option, then +the \fB\-\-sysroot\fR option applies to libraries, but the +\&\fB\-isysroot\fR option applies to header files. +.Sp +The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support +for this option. If your linker does not support this option, the +header file aspect of \fB\-\-sysroot\fR still works, but the +library aspect does not. +.IP "\fB\-\-no\-sysroot\-suffix\fR" 4 +.IX Item "--no-sysroot-suffix" +For some targets, a suffix is added to the root directory specified +with \fB\-\-sysroot\fR, depending on the other options used, so that +headers may for example be found in +\&\fI\fIdir\fI/\fIsuffix\fI/usr/include\fR instead of +\&\fI\fIdir\fI/usr/include\fR. This option disables the addition of +such a suffix. +.SS "Options for Code Generation Conventions" +.IX Subsection "Options for Code Generation Conventions" +These machine-independent options control the interface conventions +used in code generation. +.PP +Most of them have both positive and negative forms; the negative form +of \fB\-ffoo\fR is \fB\-fno\-foo\fR. In the table below, only +one of the forms is listed\-\-\-the one that is not the default. You +can figure out the other form by either removing \fBno\-\fR or adding +it. +.IP "\fB\-fstack\-reuse=\fR\fIreuse-level\fR" 4 +.IX Item "-fstack-reuse=reuse-level" +This option controls stack space reuse for user declared local/auto variables +and compiler generated temporaries. \fIreuse_level\fR can be \fBall\fR, +\&\fBnamed_vars\fR, or \fBnone\fR. \fBall\fR enables stack reuse for all +local variables and temporaries, \fBnamed_vars\fR enables the reuse only for +user defined local variables with names, and \fBnone\fR disables stack reuse +completely. The default value is \fBall\fR. The option is needed when the +program extends the lifetime of a scoped local variable or a compiler generated +temporary beyond the end point defined by the language. When a lifetime of +a variable ends, and if the variable lives in memory, the optimizing compiler +has the freedom to reuse its stack space with other temporaries or scoped +local variables whose live range does not overlap with it. Legacy code extending +local lifetime is likely to break with the stack reuse optimization. +.Sp +For example, +.Sp +.Vb 3 +\& int *p; +\& { +\& int local1; +\& +\& p = &local1; +\& local1 = 10; +\& .... +\& } +\& { +\& int local2; +\& local2 = 20; +\& ... +\& } +\& +\& if (*p == 10) // out of scope use of local1 +\& { +\& +\& } +.Ve +.Sp +Another example: +.Sp +.Vb 6 +\& struct A +\& { +\& A(int k) : i(k), j(k) { } +\& int i; +\& int j; +\& }; +\& +\& A *ap; +\& +\& void foo(const A& ar) +\& { +\& ap = &ar; +\& } +\& +\& void bar() +\& { +\& foo(A(10)); // temp object\*(Aqs lifetime ends when foo returns +\& +\& { +\& A a(20); +\& .... +\& } +\& ap\->i+= 10; // ap references out of scope temp whose space +\& // is reused with a. What is the value of ap\->i? +\& } +.Ve +.Sp +The lifetime of a compiler generated temporary is well defined by the \*(C+ +standard. When a lifetime of a temporary ends, and if the temporary lives +in memory, the optimizing compiler has the freedom to reuse its stack +space with other temporaries or scoped local variables whose live range +does not overlap with it. However some of the legacy code relies on +the behavior of older compilers in which temporaries' stack space is +not reused, the aggressive stack reuse can lead to runtime errors. This +option is used to control the temporary stack reuse optimization. +.IP "\fB\-ftrapv\fR" 4 +.IX Item "-ftrapv" +This option generates traps for signed overflow on addition, subtraction, +multiplication operations. +The options \fB\-ftrapv\fR and \fB\-fwrapv\fR override each other, so using +\&\fB\-ftrapv\fR \fB\-fwrapv\fR on the command-line results in +\&\fB\-fwrapv\fR being effective. Note that only active options override, so +using \fB\-ftrapv\fR \fB\-fwrapv\fR \fB\-fno\-wrapv\fR on the command-line +results in \fB\-ftrapv\fR being effective. +.IP "\fB\-fwrapv\fR" 4 +.IX Item "-fwrapv" +This option instructs the compiler to assume that signed arithmetic +overflow of addition, subtraction and multiplication wraps around +using twos-complement representation. This flag enables some optimizations +and disables others. +The options \fB\-ftrapv\fR and \fB\-fwrapv\fR override each other, so using +\&\fB\-ftrapv\fR \fB\-fwrapv\fR on the command-line results in +\&\fB\-fwrapv\fR being effective. Note that only active options override, so +using \fB\-ftrapv\fR \fB\-fwrapv\fR \fB\-fno\-wrapv\fR on the command-line +results in \fB\-ftrapv\fR being effective. +.IP "\fB\-fwrapv\-pointer\fR" 4 +.IX Item "-fwrapv-pointer" +This option instructs the compiler to assume that pointer arithmetic +overflow on addition and subtraction wraps around using twos-complement +representation. This flag disables some optimizations which assume +pointer overflow is invalid. +.IP "\fB\-fstrict\-overflow\fR" 4 +.IX Item "-fstrict-overflow" +This option implies \fB\-fno\-wrapv\fR \fB\-fno\-wrapv\-pointer\fR and when +negated implies \fB\-fwrapv\fR \fB\-fwrapv\-pointer\fR. +.IP "\fB\-fexceptions\fR" 4 +.IX Item "-fexceptions" +Enable exception handling. Generates extra code needed to propagate +exceptions. For some targets, this implies \s-1GCC\s0 generates frame +unwind information for all functions, which can produce significant data +size overhead, although it does not affect execution. If you do not +specify this option, \s-1GCC\s0 enables it by default for languages like +\&\*(C+ that normally require exception handling, and disables it for +languages like C that do not normally require it. However, you may need +to enable this option when compiling C code that needs to interoperate +properly with exception handlers written in \*(C+. You may also wish to +disable this option if you are compiling older \*(C+ programs that don't +use exception handling. +.IP "\fB\-fnon\-call\-exceptions\fR" 4 +.IX Item "-fnon-call-exceptions" +Generate code that allows trapping instructions to throw exceptions. +Note that this requires platform-specific runtime support that does +not exist everywhere. Moreover, it only allows \fItrapping\fR +instructions to throw exceptions, i.e. memory references or floating-point +instructions. It does not allow exceptions to be thrown from +arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR. +.IP "\fB\-fdelete\-dead\-exceptions\fR" 4 +.IX Item "-fdelete-dead-exceptions" +Consider that instructions that may throw exceptions but don't otherwise +contribute to the execution of the program can be optimized away. +This option is enabled by default for the Ada front end, as permitted by +the Ada language specification. +Optimization passes that cause dead exceptions to be removed are enabled independently at different optimization levels. +.IP "\fB\-funwind\-tables\fR" 4 +.IX Item "-funwind-tables" +Similar to \fB\-fexceptions\fR, except that it just generates any needed +static data, but does not affect the generated code in any other way. +You normally do not need to enable this option; instead, a language processor +that needs this handling enables it on your behalf. +.IP "\fB\-fasynchronous\-unwind\-tables\fR" 4 +.IX Item "-fasynchronous-unwind-tables" +Generate unwind table in \s-1DWARF\s0 format, if supported by target machine. The +table is exact at each instruction boundary, so it can be used for stack +unwinding from asynchronous events (such as debugger or garbage collector). +.IP "\fB\-fno\-gnu\-unique\fR" 4 +.IX Item "-fno-gnu-unique" +On systems with recent \s-1GNU\s0 assembler and C library, the \*(C+ compiler +uses the \f(CW\*(C`STB_GNU_UNIQUE\*(C'\fR binding to make sure that definitions +of template static data members and static local variables in inline +functions are unique even in the presence of \f(CW\*(C`RTLD_LOCAL\*(C'\fR; this +is necessary to avoid problems with a library used by two different +\&\f(CW\*(C`RTLD_LOCAL\*(C'\fR plugins depending on a definition in one of them and +therefore disagreeing with the other one about the binding of the +symbol. But this causes \f(CW\*(C`dlclose\*(C'\fR to be ignored for affected +DSOs; if your program relies on reinitialization of a \s-1DSO\s0 via +\&\f(CW\*(C`dlclose\*(C'\fR and \f(CW\*(C`dlopen\*(C'\fR, you can use +\&\fB\-fno\-gnu\-unique\fR. +.IP "\fB\-fpcc\-struct\-return\fR" 4 +.IX Item "-fpcc-struct-return" +Return \*(L"short\*(R" \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like +longer ones, rather than in registers. This convention is less +efficient, but it has the advantage of allowing intercallability between +GCC-compiled files and files compiled with other compilers, particularly +the Portable C Compiler (pcc). +.Sp +The precise convention for returning structures in memory depends +on the target configuration macros. +.Sp +Short structures and unions are those whose size and alignment match +that of some integer type. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-fpcc\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-freg\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-freg\-struct\-return\fR" 4 +.IX Item "-freg-struct-return" +Return \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in registers when possible. +This is more efficient for small structures than +\&\fB\-fpcc\-struct\-return\fR. +.Sp +If you specify neither \fB\-fpcc\-struct\-return\fR nor +\&\fB\-freg\-struct\-return\fR, \s-1GCC\s0 defaults to whichever convention is +standard for the target. If there is no standard convention, \s-1GCC\s0 +defaults to \fB\-fpcc\-struct\-return\fR, except on targets where \s-1GCC\s0 is +the principal compiler. In those cases, we can choose the standard, and +we chose the more efficient register return alternative. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-freg\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-fpcc\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-enums\fR" 4 +.IX Item "-fshort-enums" +Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the +declared range of possible values. Specifically, the \f(CW\*(C`enum\*(C'\fR type +is equivalent to the smallest integer type that has enough room. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-enums\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-wchar\fR" 4 +.IX Item "-fshort-wchar" +Override the underlying type for \f(CW\*(C`wchar_t\*(C'\fR to be \f(CW\*(C`short +unsigned int\*(C'\fR instead of the default for the target. This option is +useful for building programs to run under \s-1WINE.\s0 +.Sp +\&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fno\-common\fR" 4 +.IX Item "-fno-common" +In C code, this option controls the placement of global variables +defined without an initializer, known as \fItentative definitions\fR +in the C standard. Tentative definitions are distinct from declarations +of a variable with the \f(CW\*(C`extern\*(C'\fR keyword, which do not allocate storage. +.Sp +Unix C compilers have traditionally allocated storage for +uninitialized global variables in a common block. This allows the +linker to resolve all tentative definitions of the same variable +in different compilation units to the same object, or to a non-tentative +definition. +This is the behavior specified by \fB\-fcommon\fR, and is the default for +\&\s-1GCC\s0 on most targets. +On the other hand, this behavior is not required by \s-1ISO +C,\s0 and on some targets may carry a speed or code size penalty on +variable references. +.Sp +The \fB\-fno\-common\fR option specifies that the compiler should instead +place uninitialized global variables in the \s-1BSS\s0 section of the object file. +This inhibits the merging of tentative definitions by the linker so +you get a multiple-definition error if the same +variable is defined in more than one compilation unit. +Compiling with \fB\-fno\-common\fR is useful on targets for which +it provides better performance, or if you wish to verify that the +program will work on other systems that always treat uninitialized +variable definitions this way. +.IP "\fB\-fno\-ident\fR" 4 +.IX Item "-fno-ident" +Ignore the \f(CW\*(C`#ident\*(C'\fR directive. +.IP "\fB\-finhibit\-size\-directive\fR" 4 +.IX Item "-finhibit-size-directive" +Don't output a \f(CW\*(C`.size\*(C'\fR assembler directive, or anything else that +would cause trouble if the function is split in the middle, and the +two halves are placed at locations far apart in memory. This option is +used when compiling \fIcrtstuff.c\fR; you should not need to use it +for anything else. +.IP "\fB\-fverbose\-asm\fR" 4 +.IX Item "-fverbose-asm" +Put extra commentary information in the generated assembly code to +make it more readable. This option is generally only of use to those +who actually need to read the generated assembly code (perhaps while +debugging the compiler itself). +.Sp +\&\fB\-fno\-verbose\-asm\fR, the default, causes the +extra information to be omitted and is useful when comparing two assembler +files. +.Sp +The added comments include: +.RS 4 +.IP "*" 4 +information on the compiler version and command-line options, +.IP "*" 4 +the source code lines associated with the assembly instructions, +in the form \s-1FILENAME:LINENUMBER:CONTENT OF LINE,\s0 +.IP "*" 4 +hints on which high-level expressions correspond to +the various assembly instruction operands. +.RE +.RS 4 +.Sp +For example, given this C source file: +.Sp +.Vb 4 +\& int test (int n) +\& { +\& int i; +\& int total = 0; +\& +\& for (i = 0; i < n; i++) +\& total += i * i; +\& +\& return total; +\& } +.Ve +.Sp +compiling to (x86_64) assembly via \fB\-S\fR and emitting the result +direct to stdout via \fB\-o\fR \fB\-\fR +.Sp +.Vb 1 +\& gcc \-S test.c \-fverbose\-asm \-Os \-o \- +.Ve +.Sp +gives output similar to this: +.Sp +.Vb 5 +\& .file "test.c" +\& # GNU C11 (GCC) version 7.0.0 20160809 (experimental) (x86_64\-pc\-linux\-gnu) +\& [...snip...] +\& # options passed: +\& [...snip...] +\& +\& .text +\& .globl test +\& .type test, @function +\& test: +\& .LFB0: +\& .cfi_startproc +\& # test.c:4: int total = 0; +\& xorl %eax, %eax # +\& # test.c:6: for (i = 0; i < n; i++) +\& xorl %edx, %edx # i +\& .L2: +\& # test.c:6: for (i = 0; i < n; i++) +\& cmpl %edi, %edx # n, i +\& jge .L5 #, +\& # test.c:7: total += i * i; +\& movl %edx, %ecx # i, tmp92 +\& imull %edx, %ecx # i, tmp92 +\& # test.c:6: for (i = 0; i < n; i++) +\& incl %edx # i +\& # test.c:7: total += i * i; +\& addl %ecx, %eax # tmp92, +\& jmp .L2 # +\& .L5: +\& # test.c:10: } +\& ret +\& .cfi_endproc +\& .LFE0: +\& .size test, .\-test +\& .ident "GCC: (GNU) 7.0.0 20160809 (experimental)" +\& .section .note.GNU\-stack,"",@progbits +.Ve +.Sp +The comments are intended for humans rather than machines and hence the +precise format of the comments is subject to change. +.RE +.IP "\fB\-frecord\-gcc\-switches\fR" 4 +.IX Item "-frecord-gcc-switches" +This switch causes the command line used to invoke the +compiler to be recorded into the object file that is being created. +This switch is only implemented on some targets and the exact format +of the recording is target and binary file format dependent, but it +usually takes the form of a section containing \s-1ASCII\s0 text. This +switch is related to the \fB\-fverbose\-asm\fR switch, but that +switch only records information in the assembler output file as +comments, so it never reaches the object file. +See also \fB\-grecord\-gcc\-switches\fR for another +way of storing compiler options into the object file. +.IP "\fB\-fpic\fR" 4 +.IX Item "-fpic" +Generate position-independent code (\s-1PIC\s0) suitable for use in a shared +library, if supported for the target machine. Such code accesses all +constant addresses through a global offset table (\s-1GOT\s0). The dynamic +loader resolves the \s-1GOT\s0 entries when the program starts (the dynamic +loader is not part of \s-1GCC\s0; it is part of the operating system). If +the \s-1GOT\s0 size for the linked executable exceeds a machine-specific +maximum size, you get an error message from the linker indicating that +\&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR +instead. (These maximums are 8k on the \s-1SPARC,\s0 28k on AArch64 and 32k +on the m68k and \s-1RS/6000.\s0 The x86 has no such limit.) +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. For the x86, \s-1GCC\s0 supports \s-1PIC\s0 for System V +but not for the Sun 386i. Code generated for the \s-1IBM RS/6000\s0 is always +position-independent. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 1. +.IP "\fB\-fPIC\fR" 4 +.IX Item "-fPIC" +If supported for the target machine, emit position-independent code, +suitable for dynamic linking and avoiding any limit on the size of the +global offset table. This option makes a difference on AArch64, m68k, +PowerPC and \s-1SPARC.\s0 +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 2. +.IP "\fB\-fpie\fR" 4 +.IX Item "-fpie" +.PD 0 +.IP "\fB\-fPIE\fR" 4 +.IX Item "-fPIE" +.PD +These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but the +generated position-independent code can be only linked into executables. +Usually these options are used to compile code that will be linked using +the \fB\-pie\fR \s-1GCC\s0 option. +.Sp +\&\fB\-fpie\fR and \fB\-fPIE\fR both define the macros +\&\f(CW\*(C`_\|_pie_\|_\*(C'\fR and \f(CW\*(C`_\|_PIE_\|_\*(C'\fR. The macros have the value 1 +for \fB\-fpie\fR and 2 for \fB\-fPIE\fR. +.IP "\fB\-fno\-plt\fR" 4 +.IX Item "-fno-plt" +Do not use the \s-1PLT\s0 for external function calls in position-independent code. +Instead, load the callee address at call sites from the \s-1GOT\s0 and branch to it. +This leads to more efficient code by eliminating \s-1PLT\s0 stubs and exposing +\&\s-1GOT\s0 loads to optimizations. On architectures such as 32\-bit x86 where +\&\s-1PLT\s0 stubs expect the \s-1GOT\s0 pointer in a specific register, this gives more +register allocation freedom to the compiler. +Lazy binding requires use of the \s-1PLT\s0; +with \fB\-fno\-plt\fR all external symbols are resolved at load time. +.Sp +Alternatively, the function attribute \f(CW\*(C`noplt\*(C'\fR can be used to avoid calls +through the \s-1PLT\s0 for specific external functions. +.Sp +In position-dependent code, a few targets also convert calls to +functions that are marked to not use the \s-1PLT\s0 to use the \s-1GOT\s0 instead. +.IP "\fB\-fno\-jump\-tables\fR" 4 +.IX Item "-fno-jump-tables" +Do not use jump tables for switch statements even where it would be +more efficient than other code generation strategies. This option is +of use in conjunction with \fB\-fpic\fR or \fB\-fPIC\fR for +building code that forms part of a dynamic linker and cannot +reference the address of a jump table. On some targets, jump tables +do not require a \s-1GOT\s0 and this option is not needed. +.IP "\fB\-ffixed\-\fR\fIreg\fR" 4 +.IX Item "-ffixed-reg" +Treat the register named \fIreg\fR as a fixed register; generated code +should never refer to it (except perhaps as a stack pointer, frame +pointer or in some other fixed role). +.Sp +\&\fIreg\fR must be the name of a register. The register names accepted +are machine-specific and are defined in the \f(CW\*(C`REGISTER_NAMES\*(C'\fR +macro in the machine description macro file. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-used\-\fR\fIreg\fR" 4 +.IX Item "-fcall-used-reg" +Treat the register named \fIreg\fR as an allocable register that is +clobbered by function calls. It may be allocated for temporaries or +variables that do not live across a call. Functions compiled this way +do not save and restore the register \fIreg\fR. +.Sp +It is an error to use this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model produces disastrous results. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-saved\-\fR\fIreg\fR" 4 +.IX Item "-fcall-saved-reg" +Treat the register named \fIreg\fR as an allocable register saved by +functions. It may be allocated even for temporaries or variables that +live across a call. Functions compiled this way save and restore +the register \fIreg\fR if they use it. +.Sp +It is an error to use this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model produces disastrous results. +.Sp +A different sort of disaster results from the use of this flag for +a register in which function values may be returned. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fpack\-struct[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-fpack-struct[=n]" +Without a value specified, pack all structure members together without +holes. When a value is specified (which must be a small power of two), pack +structure members according to this value, representing the maximum +alignment (that is, objects with default alignment requirements larger than +this are output potentially unaligned at the next fitting location. +.Sp +\&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Additionally, it makes the code suboptimal. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fleading\-underscore\fR" 4 +.IX Item "-fleading-underscore" +This option and its counterpart, \fB\-fno\-leading\-underscore\fR, forcibly +change the way C symbols are represented in the object file. One use +is to help link with legacy assembly code. +.Sp +\&\fBWarning:\fR the \fB\-fleading\-underscore\fR switch causes \s-1GCC\s0 to +generate code that is not binary compatible with code generated without that +switch. Use it to conform to a non-default application binary interface. +Not all targets provide complete support for this switch. +.IP "\fB\-ftls\-model=\fR\fImodel\fR" 4 +.IX Item "-ftls-model=model" +Alter the thread-local storage model to be used. +The \fImodel\fR argument should be one of \fBglobal-dynamic\fR, +\&\fBlocal-dynamic\fR, \fBinitial-exec\fR or \fBlocal-exec\fR. +Note that the choice is subject to optimization: the compiler may use +a more efficient model for symbols not visible outside of the translation +unit, or if \fB\-fpic\fR is not given on the command line. +.Sp +The default without \fB\-fpic\fR is \fBinitial-exec\fR; with +\&\fB\-fpic\fR the default is \fBglobal-dynamic\fR. +.IP "\fB\-ftrampolines\fR" 4 +.IX Item "-ftrampolines" +For targets that normally need trampolines for nested functions, always +generate them instead of using descriptors. Otherwise, for targets that +do not need them, like for example HP-PA or \s-1IA\-64,\s0 do nothing. +.Sp +A trampoline is a small piece of code that is created at run time on the +stack when the address of a nested function is taken, and is used to call +the nested function indirectly. Therefore, it requires the stack to be +made executable in order for the program to work properly. +.Sp +\&\fB\-fno\-trampolines\fR is enabled by default on a language by language +basis to let the compiler avoid generating them, if it computes that this +is safe, and replace them with descriptors. Descriptors are made up of data +only, but the generated code must be prepared to deal with them. As of this +writing, \fB\-fno\-trampolines\fR is enabled by default only for Ada. +.Sp +Moreover, code compiled with \fB\-ftrampolines\fR and code compiled with +\&\fB\-fno\-trampolines\fR are not binary compatible if nested functions are +present. This option must therefore be used on a program-wide basis and be +manipulated with extreme care. +.IP "\fB\-fvisibility=\fR[\fBdefault\fR|\fBinternal\fR|\fBhidden\fR|\fBprotected\fR]" 4 +.IX Item "-fvisibility=[default|internal|hidden|protected]" +Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all +symbols are marked with this unless overridden within the code. +Using this feature can very substantially improve linking and +load times of shared object libraries, produce more optimized +code, provide near-perfect \s-1API\s0 export and prevent symbol clashes. +It is \fBstrongly\fR recommended that you use this in any shared objects +you distribute. +.Sp +Despite the nomenclature, \fBdefault\fR always means public; i.e., +available to be linked against from outside the shared object. +\&\fBprotected\fR and \fBinternal\fR are pretty useless in real-world +usage so the only other commonly used option is \fBhidden\fR. +The default if \fB\-fvisibility\fR isn't specified is +\&\fBdefault\fR, i.e., make every symbol public. +.Sp +A good explanation of the benefits offered by ensuring \s-1ELF\s0 +symbols have the correct visibility is given by \*(L"How To Write +Shared Libraries\*(R" by Ulrich Drepper (which can be found at +<\fBhttps://www.akkadia.org/drepper/\fR>)\-\-\-however a superior +solution made possible by this option to marking things hidden when +the default is public is to make the default hidden and mark things +public. This is the norm with DLLs on Windows and with \fB\-fvisibility=hidden\fR +and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of +\&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with +identical syntax. This is a great boon to those working with +cross-platform projects. +.Sp +For those adding visibility support to existing code, you may find +\&\f(CW\*(C`#pragma GCC visibility\*(C'\fR of use. This works by you enclosing +the declarations you wish to set visibility for with (for example) +\&\f(CW\*(C`#pragma GCC visibility push(hidden)\*(C'\fR and +\&\f(CW\*(C`#pragma GCC visibility pop\*(C'\fR. +Bear in mind that symbol visibility should be viewed \fBas +part of the \s-1API\s0 interface contract\fR and thus all new code should +always specify visibility when it is not the default; i.e., declarations +only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly +as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this +abundantly clear also aids readability and self-documentation of the code. +Note that due to \s-1ISO \*(C+\s0 specification requirements, \f(CW\*(C`operator new\*(C'\fR and +\&\f(CW\*(C`operator delete\*(C'\fR must always be of default visibility. +.Sp +Be aware that headers from outside your project, in particular system +headers and headers from any other library you use, may not be +expecting to be compiled with visibility other than the default. You +may need to explicitly say \f(CW\*(C`#pragma GCC visibility push(default)\*(C'\fR +before including any such headers. +.Sp +\&\f(CW\*(C`extern\*(C'\fR declarations are not affected by \fB\-fvisibility\fR, so +a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with +no modifications. However, this means that calls to \f(CW\*(C`extern\*(C'\fR +functions with no explicit visibility use the \s-1PLT,\s0 so it is more +effective to use \f(CW\*(C`_\|_attribute ((visibility))\*(C'\fR and/or +\&\f(CW\*(C`#pragma GCC visibility\*(C'\fR to tell the compiler which \f(CW\*(C`extern\*(C'\fR +declarations should be treated as hidden. +.Sp +Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage +entities. This means that, for instance, an exception class that is +be thrown between DSOs must be explicitly marked with default +visibility so that the \fBtype_info\fR nodes are unified between +the DSOs. +.Sp +An overview of these techniques, their benefits and how to use them +is at <\fBhttp://gcc.gnu.org/wiki/Visibility\fR>. +.IP "\fB\-fstrict\-volatile\-bitfields\fR" 4 +.IX Item "-fstrict-volatile-bitfields" +This option should be used if accesses to volatile bit-fields (or other +structure fields, although the compiler usually honors those types +anyway) should use a single access of the width of the +field's type, aligned to a natural alignment if possible. For +example, targets with memory-mapped peripheral registers might require +all such accesses to be 16 bits wide; with this flag you can +declare all peripheral bit-fields as \f(CW\*(C`unsigned short\*(C'\fR (assuming short +is 16 bits on these targets) to force \s-1GCC\s0 to use 16\-bit accesses +instead of, perhaps, a more efficient 32\-bit access. +.Sp +If this option is disabled, the compiler uses the most efficient +instruction. In the previous example, that might be a 32\-bit load +instruction, even though that accesses bytes that do not contain +any portion of the bit-field, or memory-mapped registers unrelated to +the one being updated. +.Sp +In some cases, such as when the \f(CW\*(C`packed\*(C'\fR attribute is applied to a +structure field, it may not be possible to access the field with a single +read or write that is correctly aligned for the target machine. In this +case \s-1GCC\s0 falls back to generating multiple accesses rather than code that +will fault or truncate the result at run time. +.Sp +Note: Due to restrictions of the C/\*(C+11 memory model, write accesses are +not allowed to touch non bit-field members. It is therefore recommended +to define all bits of the field's type as bit-field members. +.Sp +The default value of this option is determined by the application binary +interface for the target processor. +.IP "\fB\-fsync\-libcalls\fR" 4 +.IX Item "-fsync-libcalls" +This option controls whether any out-of-line instance of the \f(CW\*(C`_\|_sync\*(C'\fR +family of functions may be used to implement the \*(C+11 \f(CW\*(C`_\|_atomic\*(C'\fR +family of functions. +.Sp +The default value of this option is enabled, thus the only useful form +of the option is \fB\-fno\-sync\-libcalls\fR. This option is used in +the implementation of the \fIlibatomic\fR runtime library. +.SS "\s-1GCC\s0 Developer Options" +.IX Subsection "GCC Developer Options" +This section describes command-line options that are primarily of +interest to \s-1GCC\s0 developers, including options to support compiler +testing and investigation of compiler bugs and compile-time +performance problems. This includes options that produce debug dumps +at various points in the compilation; that print statistics such as +memory use and execution time; and that print information about \s-1GCC\s0's +configuration, such as where it searches for libraries. You should +rarely need to use any of these options for ordinary compilation and +linking tasks. +.PP +Many developer options that cause \s-1GCC\s0 to dump output to a file take an +optional \fB=\fR\fIfilename\fR suffix. You can specify \fBstdout\fR +or \fB\-\fR to dump to standard output, and \fBstderr\fR for standard +error. +.PP +If \fB=\fR\fIfilename\fR is omitted, a default dump file name is +constructed by concatenating the base dump file name, a pass number, +phase letter, and pass name. The base dump file name is the name of +output file produced by the compiler if explicitly specified and not +an executable; otherwise it is the source file name. +The pass number is determined by the order passes are registered with +the compiler's pass manager. +This is generally the same as the order of execution, but passes +registered by plugins, target-specific passes, or passes that are +otherwise registered late are numbered higher than the pass named +\&\fBfinal\fR, even if they are executed earlier. The phase letter is +one of \fBi\fR (inter-procedural analysis), \fBl\fR +(language-specific), \fBr\fR (\s-1RTL\s0), or \fBt\fR (tree). +The files are created in the directory of the output file. +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +.PD 0 +.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fdump-rtl-pass" +.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fdump-rtl-pass=filename" +.PD +Says to make debugging dumps during compilation at times specified by +\&\fIletters\fR. This is used for debugging the RTL-based passes of the +compiler. +.Sp +Some \fB\-d\fR\fIletters\fR switches have different meaning when +\&\fB\-E\fR is used for preprocessing. +.Sp +Debug dumps can be enabled with a \fB\-fdump\-rtl\fR switch or some +\&\fB\-d\fR option \fIletters\fR. Here are the possible +letters for use in \fIpass\fR and \fIletters\fR, and their meanings: +.RS 4 +.IP "\fB\-fdump\-rtl\-alignments\fR" 4 +.IX Item "-fdump-rtl-alignments" +Dump after branch alignments have been computed. +.IP "\fB\-fdump\-rtl\-asmcons\fR" 4 +.IX Item "-fdump-rtl-asmcons" +Dump after fixing rtl statements that have unsatisfied in/out constraints. +.IP "\fB\-fdump\-rtl\-auto_inc_dec\fR" 4 +.IX Item "-fdump-rtl-auto_inc_dec" +Dump after auto-inc-dec discovery. This pass is only run on +architectures that have auto inc or auto dec instructions. +.IP "\fB\-fdump\-rtl\-barriers\fR" 4 +.IX Item "-fdump-rtl-barriers" +Dump after cleaning up the barrier instructions. +.IP "\fB\-fdump\-rtl\-bbpart\fR" 4 +.IX Item "-fdump-rtl-bbpart" +Dump after partitioning hot and cold basic blocks. +.IP "\fB\-fdump\-rtl\-bbro\fR" 4 +.IX Item "-fdump-rtl-bbro" +Dump after block reordering. +.IP "\fB\-fdump\-rtl\-btl1\fR" 4 +.IX Item "-fdump-rtl-btl1" +.PD 0 +.IP "\fB\-fdump\-rtl\-btl2\fR" 4 +.IX Item "-fdump-rtl-btl2" +.PD +\&\fB\-fdump\-rtl\-btl1\fR and \fB\-fdump\-rtl\-btl2\fR enable dumping +after the two branch +target load optimization passes. +.IP "\fB\-fdump\-rtl\-bypass\fR" 4 +.IX Item "-fdump-rtl-bypass" +Dump after jump bypassing and control flow optimizations. +.IP "\fB\-fdump\-rtl\-combine\fR" 4 +.IX Item "-fdump-rtl-combine" +Dump after the \s-1RTL\s0 instruction combination pass. +.IP "\fB\-fdump\-rtl\-compgotos\fR" 4 +.IX Item "-fdump-rtl-compgotos" +Dump after duplicating the computed gotos. +.IP "\fB\-fdump\-rtl\-ce1\fR" 4 +.IX Item "-fdump-rtl-ce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-ce2\fR" 4 +.IX Item "-fdump-rtl-ce2" +.IP "\fB\-fdump\-rtl\-ce3\fR" 4 +.IX Item "-fdump-rtl-ce3" +.PD +\&\fB\-fdump\-rtl\-ce1\fR, \fB\-fdump\-rtl\-ce2\fR, and +\&\fB\-fdump\-rtl\-ce3\fR enable dumping after the three +if conversion passes. +.IP "\fB\-fdump\-rtl\-cprop_hardreg\fR" 4 +.IX Item "-fdump-rtl-cprop_hardreg" +Dump after hard register copy propagation. +.IP "\fB\-fdump\-rtl\-csa\fR" 4 +.IX Item "-fdump-rtl-csa" +Dump after combining stack adjustments. +.IP "\fB\-fdump\-rtl\-cse1\fR" 4 +.IX Item "-fdump-rtl-cse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-cse2\fR" 4 +.IX Item "-fdump-rtl-cse2" +.PD +\&\fB\-fdump\-rtl\-cse1\fR and \fB\-fdump\-rtl\-cse2\fR enable dumping after +the two common subexpression elimination passes. +.IP "\fB\-fdump\-rtl\-dce\fR" 4 +.IX Item "-fdump-rtl-dce" +Dump after the standalone dead code elimination passes. +.IP "\fB\-fdump\-rtl\-dbr\fR" 4 +.IX Item "-fdump-rtl-dbr" +Dump after delayed branch scheduling. +.IP "\fB\-fdump\-rtl\-dce1\fR" 4 +.IX Item "-fdump-rtl-dce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-dce2\fR" 4 +.IX Item "-fdump-rtl-dce2" +.PD +\&\fB\-fdump\-rtl\-dce1\fR and \fB\-fdump\-rtl\-dce2\fR enable dumping after +the two dead store elimination passes. +.IP "\fB\-fdump\-rtl\-eh\fR" 4 +.IX Item "-fdump-rtl-eh" +Dump after finalization of \s-1EH\s0 handling code. +.IP "\fB\-fdump\-rtl\-eh_ranges\fR" 4 +.IX Item "-fdump-rtl-eh_ranges" +Dump after conversion of \s-1EH\s0 handling range regions. +.IP "\fB\-fdump\-rtl\-expand\fR" 4 +.IX Item "-fdump-rtl-expand" +Dump after \s-1RTL\s0 generation. +.IP "\fB\-fdump\-rtl\-fwprop1\fR" 4 +.IX Item "-fdump-rtl-fwprop1" +.PD 0 +.IP "\fB\-fdump\-rtl\-fwprop2\fR" 4 +.IX Item "-fdump-rtl-fwprop2" +.PD +\&\fB\-fdump\-rtl\-fwprop1\fR and \fB\-fdump\-rtl\-fwprop2\fR enable +dumping after the two forward propagation passes. +.IP "\fB\-fdump\-rtl\-gcse1\fR" 4 +.IX Item "-fdump-rtl-gcse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-gcse2\fR" 4 +.IX Item "-fdump-rtl-gcse2" +.PD +\&\fB\-fdump\-rtl\-gcse1\fR and \fB\-fdump\-rtl\-gcse2\fR enable dumping +after global common subexpression elimination. +.IP "\fB\-fdump\-rtl\-init\-regs\fR" 4 +.IX Item "-fdump-rtl-init-regs" +Dump after the initialization of the registers. +.IP "\fB\-fdump\-rtl\-initvals\fR" 4 +.IX Item "-fdump-rtl-initvals" +Dump after the computation of the initial value sets. +.IP "\fB\-fdump\-rtl\-into_cfglayout\fR" 4 +.IX Item "-fdump-rtl-into_cfglayout" +Dump after converting to cfglayout mode. +.IP "\fB\-fdump\-rtl\-ira\fR" 4 +.IX Item "-fdump-rtl-ira" +Dump after iterated register allocation. +.IP "\fB\-fdump\-rtl\-jump\fR" 4 +.IX Item "-fdump-rtl-jump" +Dump after the second jump optimization. +.IP "\fB\-fdump\-rtl\-loop2\fR" 4 +.IX Item "-fdump-rtl-loop2" +\&\fB\-fdump\-rtl\-loop2\fR enables dumping after the rtl +loop optimization passes. +.IP "\fB\-fdump\-rtl\-mach\fR" 4 +.IX Item "-fdump-rtl-mach" +Dump after performing the machine dependent reorganization pass, if that +pass exists. +.IP "\fB\-fdump\-rtl\-mode_sw\fR" 4 +.IX Item "-fdump-rtl-mode_sw" +Dump after removing redundant mode switches. +.IP "\fB\-fdump\-rtl\-rnreg\fR" 4 +.IX Item "-fdump-rtl-rnreg" +Dump after register renumbering. +.IP "\fB\-fdump\-rtl\-outof_cfglayout\fR" 4 +.IX Item "-fdump-rtl-outof_cfglayout" +Dump after converting from cfglayout mode. +.IP "\fB\-fdump\-rtl\-peephole2\fR" 4 +.IX Item "-fdump-rtl-peephole2" +Dump after the peephole pass. +.IP "\fB\-fdump\-rtl\-postreload\fR" 4 +.IX Item "-fdump-rtl-postreload" +Dump after post-reload optimizations. +.IP "\fB\-fdump\-rtl\-pro_and_epilogue\fR" 4 +.IX Item "-fdump-rtl-pro_and_epilogue" +Dump after generating the function prologues and epilogues. +.IP "\fB\-fdump\-rtl\-sched1\fR" 4 +.IX Item "-fdump-rtl-sched1" +.PD 0 +.IP "\fB\-fdump\-rtl\-sched2\fR" 4 +.IX Item "-fdump-rtl-sched2" +.PD +\&\fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR enable dumping +after the basic block scheduling passes. +.IP "\fB\-fdump\-rtl\-ree\fR" 4 +.IX Item "-fdump-rtl-ree" +Dump after sign/zero extension elimination. +.IP "\fB\-fdump\-rtl\-seqabstr\fR" 4 +.IX Item "-fdump-rtl-seqabstr" +Dump after common sequence discovery. +.IP "\fB\-fdump\-rtl\-shorten\fR" 4 +.IX Item "-fdump-rtl-shorten" +Dump after shortening branches. +.IP "\fB\-fdump\-rtl\-sibling\fR" 4 +.IX Item "-fdump-rtl-sibling" +Dump after sibling call optimizations. +.IP "\fB\-fdump\-rtl\-split1\fR" 4 +.IX Item "-fdump-rtl-split1" +.PD 0 +.IP "\fB\-fdump\-rtl\-split2\fR" 4 +.IX Item "-fdump-rtl-split2" +.IP "\fB\-fdump\-rtl\-split3\fR" 4 +.IX Item "-fdump-rtl-split3" +.IP "\fB\-fdump\-rtl\-split4\fR" 4 +.IX Item "-fdump-rtl-split4" +.IP "\fB\-fdump\-rtl\-split5\fR" 4 +.IX Item "-fdump-rtl-split5" +.PD +These options enable dumping after five rounds of +instruction splitting. +.IP "\fB\-fdump\-rtl\-sms\fR" 4 +.IX Item "-fdump-rtl-sms" +Dump after modulo scheduling. This pass is only run on some +architectures. +.IP "\fB\-fdump\-rtl\-stack\fR" 4 +.IX Item "-fdump-rtl-stack" +Dump after conversion from \s-1GCC\s0's \*(L"flat register file\*(R" registers to the +x87's stack-like registers. This pass is only run on x86 variants. +.IP "\fB\-fdump\-rtl\-subreg1\fR" 4 +.IX Item "-fdump-rtl-subreg1" +.PD 0 +.IP "\fB\-fdump\-rtl\-subreg2\fR" 4 +.IX Item "-fdump-rtl-subreg2" +.PD +\&\fB\-fdump\-rtl\-subreg1\fR and \fB\-fdump\-rtl\-subreg2\fR enable dumping after +the two subreg expansion passes. +.IP "\fB\-fdump\-rtl\-unshare\fR" 4 +.IX Item "-fdump-rtl-unshare" +Dump after all rtl has been unshared. +.IP "\fB\-fdump\-rtl\-vartrack\fR" 4 +.IX Item "-fdump-rtl-vartrack" +Dump after variable tracking. +.IP "\fB\-fdump\-rtl\-vregs\fR" 4 +.IX Item "-fdump-rtl-vregs" +Dump after converting virtual registers to hard registers. +.IP "\fB\-fdump\-rtl\-web\fR" 4 +.IX Item "-fdump-rtl-web" +Dump after live range splitting. +.IP "\fB\-fdump\-rtl\-regclass\fR" 4 +.IX Item "-fdump-rtl-regclass" +.PD 0 +.IP "\fB\-fdump\-rtl\-subregs_of_mode_init\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_init" +.IP "\fB\-fdump\-rtl\-subregs_of_mode_finish\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_finish" +.IP "\fB\-fdump\-rtl\-dfinit\fR" 4 +.IX Item "-fdump-rtl-dfinit" +.IP "\fB\-fdump\-rtl\-dfinish\fR" 4 +.IX Item "-fdump-rtl-dfinish" +.PD +These dumps are defined but always produce empty files. +.IP "\fB\-da\fR" 4 +.IX Item "-da" +.PD 0 +.IP "\fB\-fdump\-rtl\-all\fR" 4 +.IX Item "-fdump-rtl-all" +.PD +Produce all the dumps listed above. +.IP "\fB\-dA\fR" 4 +.IX Item "-dA" +Annotate the assembler output with miscellaneous debugging information. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Dump all macro definitions, at the end of preprocessing, in addition to +normal output. +.IP "\fB\-dH\fR" 4 +.IX Item "-dH" +Produce a core dump whenever an error occurs. +.IP "\fB\-dp\fR" 4 +.IX Item "-dp" +Annotate the assembler output with a comment indicating which +pattern and alternative is used. The length and cost of each instruction are +also printed. +.IP "\fB\-dP\fR" 4 +.IX Item "-dP" +Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction. +Also turns on \fB\-dp\fR annotation. +.IP "\fB\-dx\fR" 4 +.IX Item "-dx" +Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used +with \fB\-fdump\-rtl\-expand\fR. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-debug\fR" 4 +.IX Item "-fdump-debug" +Dump debugging information generated during the debug +generation phase. +.IP "\fB\-fdump\-earlydebug\fR" 4 +.IX Item "-fdump-earlydebug" +Dump debugging information generated during the early debug +generation phase. +.IP "\fB\-fdump\-noaddr\fR" 4 +.IX Item "-fdump-noaddr" +When doing debugging dumps, suppress address output. This makes it more +feasible to use diff on debugging dumps for compiler invocations with +different compiler binaries and/or different +text / bss / data / heap / stack / dso start locations. +.IP "\fB\-freport\-bug\fR" 4 +.IX Item "-freport-bug" +Collect and dump debug information into a temporary file if an +internal compiler error (\s-1ICE\s0) occurs. +.IP "\fB\-fdump\-unnumbered\fR" 4 +.IX Item "-fdump-unnumbered" +When doing debugging dumps, suppress instruction numbers and address output. +This makes it more feasible to use diff on debugging dumps for compiler +invocations with different options, in particular with and without +\&\fB\-g\fR. +.IP "\fB\-fdump\-unnumbered\-links\fR" 4 +.IX Item "-fdump-unnumbered-links" +When doing debugging dumps (see \fB\-d\fR option above), suppress +instruction numbers for the links to the previous and next instructions +in a sequence. +.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-ipa-switch" +.PD 0 +.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-ipa-switch-options" +.PD +Control the dumping at various stages of inter-procedural analysis +language tree to a file. The file name is generated by appending a +switch specific suffix to the source file name, and the file is created +in the same directory as the output file. The following dumps are +possible: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enables all inter-procedural analysis dumps. +.IP "\fBcgraph\fR" 4 +.IX Item "cgraph" +Dumps information about call-graph optimization, unused function removal, +and inlining decisions. +.IP "\fBinline\fR" 4 +.IX Item "inline" +Dump after function inlining. +.RE +.RS 4 +.Sp +Additionally, the options \fB\-optimized\fR, \fB\-missed\fR, +\&\fB\-note\fR, and \fB\-all\fR can be provided, with the same meaning +as for \fB\-fopt\-info\fR, defaulting to \fB\-optimized\fR. +.Sp +For example, \fB\-fdump\-ipa\-inline\-optimized\-missed\fR will emit +information on callsites that were inlined, along with callsites +that were not inlined. +.Sp +By default, the dump will contain messages about successful +optimizations (equivalent to \fB\-optimized\fR) together with +low-level details about the analysis. +.RE +.IP "\fB\-fdump\-lang\-all\fR" 4 +.IX Item "-fdump-lang-all" +.PD 0 +.IP "\fB\-fdump\-lang\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-lang-switch" +.IP "\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-lang-switch-options" +.IP "\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fdump-lang-switch-options=filename" +.PD +Control the dumping of language-specific information. The \fIoptions\fR +and \fIfilename\fR portions behave as described in the +\&\fB\-fdump\-tree\fR option. The following \fIswitch\fR values are +accepted: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all language-specific dumps. +.IP "\fBclass\fR" 4 +.IX Item "class" +Dump class hierarchy information. Virtual table information is emitted +unless '\fBslim\fR' is specified. This option is applicable to \*(C+ only. +.IP "\fBraw\fR" 4 +.IX Item "raw" +Dump the raw internal tree data. This option is applicable to \*(C+ only. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-passes\fR" 4 +.IX Item "-fdump-passes" +Print on \fIstderr\fR the list of optimization passes that are turned +on and off by the current command-line options. +.IP "\fB\-fdump\-statistics\-\fR\fIoption\fR" 4 +.IX Item "-fdump-statistics-option" +Enable and control dumping of pass statistics in a separate file. The +file name is generated by appending a suffix ending in +\&\fB.statistics\fR to the source file name, and the file is created in +the same directory as the output file. If the \fB\-\fR\fIoption\fR +form is used, \fB\-stats\fR causes counters to be summed over the +whole compilation unit while \fB\-details\fR dumps every event as +the passes generate them. The default with no option is to sum +counters for each function compiled. +.IP "\fB\-fdump\-tree\-all\fR" 4 +.IX Item "-fdump-tree-all" +.PD 0 +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-tree-switch" +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-tree-switch-options" +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fdump-tree-switch-options=filename" +.PD +Control the dumping at various stages of processing the intermediate +language tree to a file. If the \fB\-\fR\fIoptions\fR +form is used, \fIoptions\fR is a list of \fB\-\fR separated options +which control the details of the dump. Not all options are applicable +to all dumps; those that are not meaningful are ignored. The +following options are available +.RS 4 +.IP "\fBaddress\fR" 4 +.IX Item "address" +Print the address of each node. Usually this is not meaningful as it +changes according to the environment and source file. Its primary use +is for tying up a dump file with a debug environment. +.IP "\fBasmname\fR" 4 +.IX Item "asmname" +If \f(CW\*(C`DECL_ASSEMBLER_NAME\*(C'\fR has been set for a given decl, use that +in the dump instead of \f(CW\*(C`DECL_NAME\*(C'\fR. Its primary use is ease of +use working backward from mangled names in the assembly file. +.IP "\fBslim\fR" 4 +.IX Item "slim" +When dumping front-end intermediate representations, inhibit dumping +of members of a scope or body of a function merely because that scope +has been reached. Only dump such items when they are directly reachable +by some other path. +.Sp +When dumping pretty-printed trees, this option inhibits dumping the +bodies of control structures. +.Sp +When dumping \s-1RTL,\s0 print the \s-1RTL\s0 in slim (condensed) form instead of +the default LISP-like representation. +.IP "\fBraw\fR" 4 +.IX Item "raw" +Print a raw representation of the tree. By default, trees are +pretty-printed into a C\-like representation. +.IP "\fBdetails\fR" 4 +.IX Item "details" +Enable more detailed dumps (not honored by every dump option). Also +include information from the optimization passes. +.IP "\fBstats\fR" 4 +.IX Item "stats" +Enable dumping various statistics about the pass (not honored by every dump +option). +.IP "\fBblocks\fR" 4 +.IX Item "blocks" +Enable showing basic block boundaries (disabled in raw dumps). +.IP "\fBgraph\fR" 4 +.IX Item "graph" +For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR), +dump a representation of the control flow graph suitable for viewing with +GraphViz to \fI\fIfile\fI.\fIpassid\fI.\fIpass\fI.dot\fR. Each function in +the file is pretty-printed as a subgraph, so that GraphViz can render them +all in a single plot. +.Sp +This option currently only works for \s-1RTL\s0 dumps, and the \s-1RTL\s0 is always +dumped in slim form. +.IP "\fBvops\fR" 4 +.IX Item "vops" +Enable showing virtual operands for every statement. +.IP "\fBlineno\fR" 4 +.IX Item "lineno" +Enable showing line numbers for statements. +.IP "\fBuid\fR" 4 +.IX Item "uid" +Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +.IP "\fBverbose\fR" 4 +.IX Item "verbose" +Enable showing the tree dump for each statement. +.IP "\fBeh\fR" 4 +.IX Item "eh" +Enable showing the \s-1EH\s0 region number holding each statement. +.IP "\fBscev\fR" 4 +.IX Item "scev" +Enable showing scalar evolution analysis details. +.IP "\fBoptimized\fR" 4 +.IX Item "optimized" +Enable showing optimization information (only available in certain +passes). +.IP "\fBmissed\fR" 4 +.IX Item "missed" +Enable showing missed optimization information (only available in certain +passes). +.IP "\fBnote\fR" 4 +.IX Item "note" +Enable other detailed optimization information (only available in +certain passes). +.IP "\fBall\fR" 4 +.IX Item "all" +Turn on all options, except \fBraw\fR, \fBslim\fR, \fBverbose\fR +and \fBlineno\fR. +.IP "\fBoptall\fR" 4 +.IX Item "optall" +Turn on all optimization options, i.e., \fBoptimized\fR, +\&\fBmissed\fR, and \fBnote\fR. +.RE +.RS 4 +.Sp +To determine what tree dumps are available or find the dump for a pass +of interest follow the steps below. +.IP "1." 4 +.IX Item "1." +Invoke \s-1GCC\s0 with \fB\-fdump\-passes\fR and in the \fIstderr\fR output +look for a code that corresponds to the pass you are interested in. +For example, the codes \f(CW\*(C`tree\-evrp\*(C'\fR, \f(CW\*(C`tree\-vrp1\*(C'\fR, and +\&\f(CW\*(C`tree\-vrp2\*(C'\fR correspond to the three Value Range Propagation passes. +The number at the end distinguishes distinct invocations of the same pass. +.IP "2." 4 +.IX Item "2." +To enable the creation of the dump file, append the pass code to +the \fB\-fdump\-\fR option prefix and invoke \s-1GCC\s0 with it. For example, +to enable the dump from the Early Value Range Propagation pass, invoke +\&\s-1GCC\s0 with the \fB\-fdump\-tree\-evrp\fR option. Optionally, you may +specify the name of the dump file. If you don't specify one, \s-1GCC\s0 +creates as described below. +.IP "3." 4 +.IX Item "3." +Find the pass dump in a file whose name is composed of three components +separated by a period: the name of the source file \s-1GCC\s0 was invoked to +compile, a numeric suffix indicating the pass number followed by the +letter \fBt\fR for tree passes (and the letter \fBr\fR for \s-1RTL\s0 passes), +and finally the pass code. For example, the Early \s-1VRP\s0 pass dump might +be in a file named \fImyfile.c.038t.evrp\fR in the current working +directory. Note that the numeric codes are not stable and may change +from one version of \s-1GCC\s0 to another. +.RE +.RS 4 +.RE +.IP "\fB\-fopt\-info\fR" 4 +.IX Item "-fopt-info" +.PD 0 +.IP "\fB\-fopt\-info\-\fR\fIoptions\fR" 4 +.IX Item "-fopt-info-options" +.IP "\fB\-fopt\-info\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fopt-info-options=filename" +.PD +Controls optimization dumps from various optimization passes. If the +\&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of +\&\fB\-\fR separated option keywords to select the dump details and +optimizations. +.Sp +The \fIoptions\fR can be divided into three groups: +.RS 4 +.IP "1." 4 +.IX Item "1." +options describing what kinds of messages should be emitted, +.IP "2." 4 +.IX Item "2." +options describing the verbosity of the dump, and +.IP "3." 4 +.IX Item "3." +options describing which optimizations should be included. +.RE +.RS 4 +.Sp +The options from each group can be freely mixed as they are +non-overlapping. However, in case of any conflicts, +the later options override the earlier options on the command +line. +.Sp +The following options control which kinds of messages should be emitted: +.IP "\fBoptimized\fR" 4 +.IX Item "optimized" +Print information when an optimization is successfully applied. It is +up to a pass to decide which information is relevant. For example, the +vectorizer passes print the source location of loops which are +successfully vectorized. +.IP "\fBmissed\fR" 4 +.IX Item "missed" +Print information about missed optimizations. Individual passes +control which information to include in the output. +.IP "\fBnote\fR" 4 +.IX Item "note" +Print verbose information about optimizations, such as certain +transformations, more detailed messages about decisions etc. +.IP "\fBall\fR" 4 +.IX Item "all" +Print detailed optimization information. This includes +\&\fBoptimized\fR, \fBmissed\fR, and \fBnote\fR. +.RE +.RS 4 +.Sp +The following option controls the dump verbosity: +.IP "\fBinternals\fR" 4 +.IX Item "internals" +By default, only \*(L"high-level\*(R" messages are emitted. This option enables +additional, more detailed, messages, which are likely to only be of interest +to \s-1GCC\s0 developers. +.RE +.RS 4 +.Sp +One or more of the following option keywords can be used to describe a +group of optimizations: +.IP "\fBipa\fR" 4 +.IX Item "ipa" +Enable dumps from all interprocedural optimizations. +.IP "\fBloop\fR" 4 +.IX Item "loop" +Enable dumps from all loop optimizations. +.IP "\fBinline\fR" 4 +.IX Item "inline" +Enable dumps from all inlining optimizations. +.IP "\fBomp\fR" 4 +.IX Item "omp" +Enable dumps from all \s-1OMP\s0 (Offloading and Multi Processing) optimizations. +.IP "\fBvec\fR" 4 +.IX Item "vec" +Enable dumps from all vectorization optimizations. +.IP "\fBoptall\fR" 4 +.IX Item "optall" +Enable dumps from all optimizations. This is a superset of +the optimization groups listed above. +.RE +.RS 4 +.Sp +If \fIoptions\fR is +omitted, it defaults to \fBoptimized-optall\fR, which means to dump messages +about successful optimizations from all the passes, omitting messages +that are treated as \*(L"internals\*(R". +.Sp +If the \fIfilename\fR is provided, then the dumps from all the +applicable optimizations are concatenated into the \fIfilename\fR. +Otherwise the dump is output onto \fIstderr\fR. Though multiple +\&\fB\-fopt\-info\fR options are accepted, only one of them can include +a \fIfilename\fR. If other filenames are provided then all but the +first such option are ignored. +.Sp +Note that the output \fIfilename\fR is overwritten +in case of multiple translation units. If a combined output from +multiple translation units is desired, \fIstderr\fR should be used +instead. +.Sp +In the following example, the optimization info is output to +\&\fIstderr\fR: +.Sp +.Vb 1 +\& gcc \-O3 \-fopt\-info +.Ve +.Sp +This example: +.Sp +.Vb 1 +\& gcc \-O3 \-fopt\-info\-missed=missed.all +.Ve +.Sp +outputs missed optimization report from all the passes into +\&\fImissed.all\fR, and this one: +.Sp +.Vb 1 +\& gcc \-O2 \-ftree\-vectorize \-fopt\-info\-vec\-missed +.Ve +.Sp +prints information about missed optimization opportunities from +vectorization passes on \fIstderr\fR. +Note that \fB\-fopt\-info\-vec\-missed\fR is equivalent to +\&\fB\-fopt\-info\-missed\-vec\fR. The order of the optimization group +names and message types listed after \fB\-fopt\-info\fR does not matter. +.Sp +As another example, +.Sp +.Vb 1 +\& gcc \-O3 \-fopt\-info\-inline\-optimized\-missed=inline.txt +.Ve +.Sp +outputs information about missed optimizations as well as +optimized locations from all the inlining passes into +\&\fIinline.txt\fR. +.Sp +Finally, consider: +.Sp +.Vb 1 +\& gcc \-fopt\-info\-vec\-missed=vec.miss \-fopt\-info\-loop\-optimized=loop.opt +.Ve +.Sp +Here the two output filenames \fIvec.miss\fR and \fIloop.opt\fR are +in conflict since only one output file is allowed. In this case, only +the first option takes effect and the subsequent options are +ignored. Thus only \fIvec.miss\fR is produced which contains +dumps from the vectorizer about missed opportunities. +.RE +.IP "\fB\-fsave\-optimization\-record\fR" 4 +.IX Item "-fsave-optimization-record" +Write a \s-1SRCFILE\s0.opt\-record.json.gz file detailing what optimizations +were performed, for those optimizations that support \fB\-fopt\-info\fR. +.Sp +This option is experimental and the format of the data within the +compressed \s-1JSON\s0 file is subject to change. +.Sp +It is roughly equivalent to a machine-readable version of +\&\fB\-fopt\-info\-all\fR, as a collection of messages with source file, +line number and column number, with the following additional data for +each message: +.RS 4 +.IP "*" 4 +the execution count of the code being optimized, along with metadata about +whether this was from actual profile data, or just an estimate, allowing +consumers to prioritize messages by code hotness, +.IP "*" 4 +the function name of the code being optimized, where applicable, +.IP "*" 4 +the \*(L"inlining chain\*(R" for the code being optimized, so that when +a function is inlined into several different places (which might +themselves be inlined), the reader can distinguish between the copies, +.IP "*" 4 +objects identifying those parts of the message that refer to expressions, +statements or symbol-table nodes, which of these categories they are, and, +when available, their source code location, +.IP "*" 4 +the \s-1GCC\s0 pass that emitted the message, and +.IP "*" 4 +the location in \s-1GCC\s0's own code from which the message was emitted +.RE +.RS 4 +.Sp +Additionally, some messages are logically nested within other +messages, reflecting implementation details of the optimization +passes. +.RE +.IP "\fB\-fsched\-verbose=\fR\fIn\fR" 4 +.IX Item "-fsched-verbose=n" +On targets that use instruction scheduling, this option controls the +amount of debugging output the scheduler prints to the dump files. +.Sp +For \fIn\fR greater than zero, \fB\-fsched\-verbose\fR outputs the +same information as \fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR. +For \fIn\fR greater than one, it also output basic block probabilities, +detailed ready list information and unit/insn info. For \fIn\fR greater +than two, it includes \s-1RTL\s0 at abort point, control-flow and regions info. +And for \fIn\fR over four, \fB\-fsched\-verbose\fR also includes +dependence info. +.IP "\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR" 4 +.IX Item "-fenable-kind-pass" +.PD 0 +.IP "\fB\-fdisable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-kind-pass=range-list" +.PD +This is a set of options that are used to explicitly disable/enable +optimization passes. These options are intended for use for debugging \s-1GCC.\s0 +Compiler users should use regular options for enabling/disabling +passes instead. +.RS 4 +.IP "\fB\-fdisable\-ipa\-\fR\fIpass\fR" 4 +.IX Item "-fdisable-ipa-pass" +Disable \s-1IPA\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "\fB\-fdisable\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fdisable-rtl-pass" +.PD 0 +.IP "\fB\-fdisable\-rtl\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-rtl-pass=range-list" +.PD +Disable \s-1RTL\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. \fIrange-list\fR is a +comma-separated list of function ranges or assembler names. Each range is a number +pair separated by a colon. The range is inclusive in both ends. If the range +is trivial, the number pair can be simplified as a single number. If the +function's call graph node's \fIuid\fR falls within one of the specified ranges, +the \fIpass\fR is disabled for that function. The \fIuid\fR is shown in the +function header of a dump file, and the pass names can be dumped by using +option \fB\-fdump\-passes\fR. +.IP "\fB\-fdisable\-tree\-\fR\fIpass\fR" 4 +.IX Item "-fdisable-tree-pass" +.PD 0 +.IP "\fB\-fdisable\-tree\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-tree-pass=range-list" +.PD +Disable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description of +option arguments. +.IP "\fB\-fenable\-ipa\-\fR\fIpass\fR" 4 +.IX Item "-fenable-ipa-pass" +Enable \s-1IPA\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "\fB\-fenable\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fenable-rtl-pass" +.PD 0 +.IP "\fB\-fenable\-rtl\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fenable-rtl-pass=range-list" +.PD +Enable \s-1RTL\s0 pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument +description and examples. +.IP "\fB\-fenable\-tree\-\fR\fIpass\fR" 4 +.IX Item "-fenable-tree-pass" +.PD 0 +.IP "\fB\-fenable\-tree\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fenable-tree-pass=range-list" +.PD +Enable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description +of option arguments. +.RE +.RS 4 +.Sp +Here are some examples showing uses of these options. +.Sp +.Vb 10 +\& # disable ccp1 for all functions +\& \-fdisable\-tree\-ccp1 +\& # disable complete unroll for function whose cgraph node uid is 1 +\& \-fenable\-tree\-cunroll=1 +\& # disable gcse2 for functions at the following ranges [1,1], +\& # [300,400], and [400,1000] +\& # disable gcse2 for functions foo and foo2 +\& \-fdisable\-rtl\-gcse2=foo,foo2 +\& # disable early inlining +\& \-fdisable\-tree\-einline +\& # disable ipa inlining +\& \-fdisable\-ipa\-inline +\& # enable tree full unroll +\& \-fenable\-tree\-unroll +.Ve +.RE +.IP "\fB\-fchecking\fR" 4 +.IX Item "-fchecking" +.PD 0 +.IP "\fB\-fchecking=\fR\fIn\fR" 4 +.IX Item "-fchecking=n" +.PD +Enable internal consistency checking. The default depends on +the compiler configuration. \fB\-fchecking=2\fR enables further +internal consistency checking that might affect code generation. +.IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4 +.IX Item "-frandom-seed=string" +This option provides a seed that \s-1GCC\s0 uses in place of +random numbers in generating certain symbol names +that have to be different in every compiled file. It is also used to +place unique stamps in coverage data files and the object files that +produce them. You can use the \fB\-frandom\-seed\fR option to produce +reproducibly identical object files. +.Sp +The \fIstring\fR can either be a number (decimal, octal or hex) or an +arbitrary string (in which case it's converted to a number by +computing \s-1CRC32\s0). +.Sp +The \fIstring\fR should be different for every file you compile. +.IP "\fB\-save\-temps\fR" 4 +.IX Item "-save-temps" +.PD 0 +.IP "\fB\-save\-temps=cwd\fR" 4 +.IX Item "-save-temps=cwd" +.PD +Store the usual \*(L"temporary\*(R" intermediate files permanently; place them +in the current directory and name them based on the source file. Thus, +compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR produces files +\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a +preprocessed \fIfoo.i\fR output file even though the compiler now +normally uses an integrated preprocessor. +.Sp +When used in combination with the \fB\-x\fR command-line option, +\&\fB\-save\-temps\fR is sensible enough to avoid over writing an +input source file with the same extension as an intermediate file. +The corresponding intermediate file may be obtained by renaming the +source file before using \fB\-save\-temps\fR. +.Sp +If you invoke \s-1GCC\s0 in parallel, compiling several different source +files that share a common base name in different subdirectories or the +same source file compiled for multiple output destinations, it is +likely that the different parallel compilers will interfere with each +other, and overwrite the temporary files. For instance: +.Sp +.Vb 2 +\& gcc \-save\-temps \-o outdir1/foo.o indir1/foo.c& +\& gcc \-save\-temps \-o outdir2/foo.o indir2/foo.c& +.Ve +.Sp +may result in \fIfoo.i\fR and \fIfoo.o\fR being written to +simultaneously by both compilers. +.IP "\fB\-save\-temps=obj\fR" 4 +.IX Item "-save-temps=obj" +Store the usual \*(L"temporary\*(R" intermediate files permanently. If the +\&\fB\-o\fR option is used, the temporary files are based on the +object file. If the \fB\-o\fR option is not used, the +\&\fB\-save\-temps=obj\fR switch behaves like \fB\-save\-temps\fR. +.Sp +For example: +.Sp +.Vb 3 +\& gcc \-save\-temps=obj \-c foo.c +\& gcc \-save\-temps=obj \-c bar.c \-o dir/xbar.o +\& gcc \-save\-temps=obj foobar.c \-o dir2/yfoobar +.Ve +.Sp +creates \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR, +\&\fIdir/xbar.s\fR, \fIdir2/yfoobar.i\fR, \fIdir2/yfoobar.s\fR, and +\&\fIdir2/yfoobar.o\fR. +.IP "\fB\-time\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-time[=file]" +Report the \s-1CPU\s0 time taken by each subprocess in the compilation +sequence. For C source files, this is the compiler proper and assembler +(plus the linker if linking is done). +.Sp +Without the specification of an output file, the output looks like this: +.Sp +.Vb 2 +\& # cc1 0.12 0.01 +\& # as 0.00 0.01 +.Ve +.Sp +The first number on each line is the \*(L"user time\*(R", that is time spent +executing the program itself. The second number is \*(L"system time\*(R", +time spent executing operating system routines on behalf of the program. +Both numbers are in seconds. +.Sp +With the specification of an output file, the output is appended to the +named file, and it looks like this: +.Sp +.Vb 2 +\& 0.12 0.01 cc1 +\& 0.00 0.01 as +.Ve +.Sp +The \*(L"user time\*(R" and the \*(L"system time\*(R" are moved before the program +name, and the options passed to the program are displayed, so that one +can later tell what file was being compiled, and with which options. +.IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-fdump-final-insns[=file]" +Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the +optional argument is omitted (or if \fIfile\fR is \f(CW\*(C`.\*(C'\fR), the name +of the dump file is determined by appending \f(CW\*(C`.gkd\*(C'\fR to the +compilation output file name. +.IP "\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR]" 4 +.IX Item "-fcompare-debug[=opts]" +If no error occurs during compilation, run the compiler a second time, +adding \fIopts\fR and \fB\-fcompare\-debug\-second\fR to the arguments +passed to the second compilation. Dump the final internal +representation in both compilations, and print an error if they differ. +.Sp +If the equal sign is omitted, the default \fB\-gtoggle\fR is used. +.Sp +The environment variable \fB\s-1GCC_COMPARE_DEBUG\s0\fR, if defined, non-empty +and nonzero, implicitly enables \fB\-fcompare\-debug\fR. If +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR is defined to a string starting with a dash, +then it is used for \fIopts\fR, otherwise the default \fB\-gtoggle\fR +is used. +.Sp +\&\fB\-fcompare\-debug=\fR, with the equal sign but without \fIopts\fR, +is equivalent to \fB\-fno\-compare\-debug\fR, which disables the dumping +of the final representation and the second compilation, preventing even +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR from taking effect. +.Sp +To verify full coverage during \fB\-fcompare\-debug\fR testing, set +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR to say \fB\-fcompare\-debug\-not\-overridden\fR, +which \s-1GCC\s0 rejects as an invalid option in any actual compilation +(rather than preprocessing, assembly or linking). To get just a +warning, setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR to \fB\-w%n\-fcompare\-debug +not overridden\fR will do. +.IP "\fB\-fcompare\-debug\-second\fR" 4 +.IX Item "-fcompare-debug-second" +This option is implicitly passed to the compiler for the second +compilation requested by \fB\-fcompare\-debug\fR, along with options to +silence warnings, and omitting other options that would cause the compiler +to produce output to files or to standard output as a side effect. Dump +files and preserved temporary files are renamed so as to contain the +\&\f(CW\*(C`.gk\*(C'\fR additional extension during the second compilation, to avoid +overwriting those generated by the first. +.Sp +When this option is passed to the compiler driver, it causes the +\&\fIfirst\fR compilation to be skipped, which makes it useful for little +other than debugging the compiler proper. +.IP "\fB\-gtoggle\fR" 4 +.IX Item "-gtoggle" +Turn off generation of debug info, if leaving out this option +generates it, or turn it on at level 2 otherwise. The position of this +argument in the command line does not matter; it takes effect after all +other options are processed, and it does so only once, no matter how +many times it is given. This is mainly intended to be used with +\&\fB\-fcompare\-debug\fR. +.IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4 +.IX Item "-fvar-tracking-assignments-toggle" +Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that +\&\fB\-gtoggle\fR toggles \fB\-g\fR. +.IP "\fB\-Q\fR" 4 +.IX Item "-Q" +Makes the compiler print out each function name as it is compiled, and +print some statistics about each pass when it finishes. +.IP "\fB\-ftime\-report\fR" 4 +.IX Item "-ftime-report" +Makes the compiler print some statistics about the time consumed by each +pass when it finishes. +.IP "\fB\-ftime\-report\-details\fR" 4 +.IX Item "-ftime-report-details" +Record the time consumed by infrastructure parts separately for each pass. +.IP "\fB\-fira\-verbose=\fR\fIn\fR" 4 +.IX Item "-fira-verbose=n" +Control the verbosity of the dump file for the integrated register allocator. +The default value is 5. If the value \fIn\fR is greater or equal to 10, +the dump output is sent to stderr using the same format as \fIn\fR minus 10. +.IP "\fB\-flto\-report\fR" 4 +.IX Item "-flto-report" +Prints a report with internal details on the workings of the link-time +optimizer. The contents of this report vary from version to version. +It is meant to be useful to \s-1GCC\s0 developers when processing object +files in \s-1LTO\s0 mode (via \fB\-flto\fR). +.Sp +Disabled by default. +.IP "\fB\-flto\-report\-wpa\fR" 4 +.IX Item "-flto-report-wpa" +Like \fB\-flto\-report\fR, but only print for the \s-1WPA\s0 phase of Link +Time Optimization. +.IP "\fB\-fmem\-report\fR" 4 +.IX Item "-fmem-report" +Makes the compiler print some statistics about permanent memory +allocation when it finishes. +.IP "\fB\-fmem\-report\-wpa\fR" 4 +.IX Item "-fmem-report-wpa" +Makes the compiler print some statistics about permanent memory +allocation for the \s-1WPA\s0 phase only. +.IP "\fB\-fpre\-ipa\-mem\-report\fR" 4 +.IX Item "-fpre-ipa-mem-report" +.PD 0 +.IP "\fB\-fpost\-ipa\-mem\-report\fR" 4 +.IX Item "-fpost-ipa-mem-report" +.PD +Makes the compiler print some statistics about permanent memory +allocation before or after interprocedural optimization. +.IP "\fB\-fprofile\-report\fR" 4 +.IX Item "-fprofile-report" +Makes the compiler print some statistics about consistency of the +(estimated) profile and effect of individual passes. +.IP "\fB\-fstack\-usage\fR" 4 +.IX Item "-fstack-usage" +Makes the compiler output stack usage information for the program, on a +per-function basis. The filename for the dump is made by appending +\&\fI.su\fR to the \fIauxname\fR. \fIauxname\fR is generated from the name of +the output file, if explicitly specified and it is not an executable, +otherwise it is the basename of the source file. An entry is made up +of three fields: +.RS 4 +.IP "*" 4 +The name of the function. +.IP "*" 4 +A number of bytes. +.IP "*" 4 +One or more qualifiers: \f(CW\*(C`static\*(C'\fR, \f(CW\*(C`dynamic\*(C'\fR, \f(CW\*(C`bounded\*(C'\fR. +.RE +.RS 4 +.Sp +The qualifier \f(CW\*(C`static\*(C'\fR means that the function manipulates the stack +statically: a fixed number of bytes are allocated for the frame on function +entry and released on function exit; no stack adjustments are otherwise made +in the function. The second field is this fixed number of bytes. +.Sp +The qualifier \f(CW\*(C`dynamic\*(C'\fR means that the function manipulates the stack +dynamically: in addition to the static allocation described above, stack +adjustments are made in the body of the function, for example to push/pop +arguments around function calls. If the qualifier \f(CW\*(C`bounded\*(C'\fR is also +present, the amount of these adjustments is bounded at compile time and +the second field is an upper bound of the total amount of stack used by +the function. If it is not present, the amount of these adjustments is +not bounded at compile time and the second field only represents the +bounded part. +.RE +.IP "\fB\-fstats\fR" 4 +.IX Item "-fstats" +Emit statistics about front-end processing at the end of the compilation. +This option is supported only by the \*(C+ front end, and +the information is generally only useful to the G++ development team. +.IP "\fB\-fdbg\-cnt\-list\fR" 4 +.IX Item "-fdbg-cnt-list" +Print the name and the counter upper bound for all debug counters. +.IP "\fB\-fdbg\-cnt=\fR\fIcounter-value-list\fR" 4 +.IX Item "-fdbg-cnt=counter-value-list" +Set the internal debug counter lower and upper bound. \fIcounter-value-list\fR +is a comma-separated list of \fIname\fR:\fIlower_bound\fR:\fIupper_bound\fR +tuples which sets the lower and the upper bound of each debug +counter \fIname\fR. The \fIlower_bound\fR is optional and is zero +initialized if not set. +All debug counters have the initial upper bound of \f(CW\*(C`UINT_MAX\*(C'\fR; +thus \f(CW\*(C`dbg_cnt\*(C'\fR returns true always unless the upper bound +is set by this option. +For example, with \fB\-fdbg\-cnt=dce:2:4,tail_call:10\fR, +\&\f(CW\*(C`dbg_cnt(dce)\*(C'\fR returns true only for third and fourth invocation. +For \f(CW\*(C`dbg_cnt(tail_call)\*(C'\fR true is returned for first 10 invocations. +.IP "\fB\-print\-file\-name=\fR\fIlibrary\fR" 4 +.IX Item "-print-file-name=library" +Print the full absolute name of the library file \fIlibrary\fR that +would be used when linking\-\-\-and don't do anything else. With this +option, \s-1GCC\s0 does not compile or link anything; it just prints the +file name. +.IP "\fB\-print\-multi\-directory\fR" 4 +.IX Item "-print-multi-directory" +Print the directory name corresponding to the multilib selected by any +other switches present in the command line. This directory is supposed +to exist in \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\-print\-multi\-lib\fR" 4 +.IX Item "-print-multi-lib" +Print the mapping from multilib directory names to compiler switches +that enable them. The directory name is separated from the switches by +\&\fB;\fR, and each switch starts with an \fB@\fR instead of the +\&\fB\-\fR, without spaces between multiple switches. This is supposed to +ease shell processing. +.IP "\fB\-print\-multi\-os\-directory\fR" 4 +.IX Item "-print-multi-os-directory" +Print the path to \s-1OS\s0 libraries for the selected +multilib, relative to some \fIlib\fR subdirectory. If \s-1OS\s0 libraries are +present in the \fIlib\fR subdirectory and no multilibs are used, this is +usually just \fI.\fR, if \s-1OS\s0 libraries are present in \fIlib\fIsuffix\fI\fR +sibling directories this prints e.g. \fI../lib64\fR, \fI../lib\fR or +\&\fI../lib32\fR, or if \s-1OS\s0 libraries are present in \fIlib/\fIsubdir\fI\fR +subdirectories it prints e.g. \fIamd64\fR, \fIsparcv9\fR or \fIev6\fR. +.IP "\fB\-print\-multiarch\fR" 4 +.IX Item "-print-multiarch" +Print the path to \s-1OS\s0 libraries for the selected multiarch, +relative to some \fIlib\fR subdirectory. +.IP "\fB\-print\-prog\-name=\fR\fIprogram\fR" 4 +.IX Item "-print-prog-name=program" +Like \fB\-print\-file\-name\fR, but searches for a program such as \fBcpp\fR. +.IP "\fB\-print\-libgcc\-file\-name\fR" 4 +.IX Item "-print-libgcc-file-name" +Same as \fB\-print\-file\-name=libgcc.a\fR. +.Sp +This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR +but you do want to link with \fIlibgcc.a\fR. You can do: +.Sp +.Vb 1 +\& gcc \-nostdlib ... \`gcc \-print\-libgcc\-file\-name\` +.Ve +.IP "\fB\-print\-search\-dirs\fR" 4 +.IX Item "-print-search-dirs" +Print the name of the configured installation directory and a list of +program and library directories \fBgcc\fR searches\-\-\-and don't do anything else. +.Sp +This is useful when \fBgcc\fR prints the error message +\&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR. +To resolve this you either need to put \fIcpp0\fR and the other compiler +components where \fBgcc\fR expects to find them, or you can set the environment +variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them. +Don't forget the trailing \fB/\fR. +.IP "\fB\-print\-sysroot\fR" 4 +.IX Item "-print-sysroot" +Print the target sysroot directory that is used during +compilation. This is the target sysroot specified either at configure +time or using the \fB\-\-sysroot\fR option, possibly with an extra +suffix that depends on compilation options. If no target sysroot is +specified, the option prints nothing. +.IP "\fB\-print\-sysroot\-headers\-suffix\fR" 4 +.IX Item "-print-sysroot-headers-suffix" +Print the suffix added to the target sysroot when searching for +headers, or give an error if the compiler is not configured with such +a suffix\-\-\-and don't do anything else. +.IP "\fB\-dumpmachine\fR" 4 +.IX Item "-dumpmachine" +Print the compiler's target machine (for example, +\&\fBi686\-pc\-linux\-gnu\fR)\-\-\-and don't do anything else. +.IP "\fB\-dumpversion\fR" 4 +.IX Item "-dumpversion" +Print the compiler version (for example, \f(CW3.0\fR, \f(CW6.3.0\fR or \f(CW7\fR)\-\-\-and don't do +anything else. This is the compiler version used in filesystem paths and +specs. Depending on how the compiler has been configured it can be just +a single number (major version), two numbers separated by a dot (major and +minor version) or three numbers separated by dots (major, minor and patchlevel +version). +.IP "\fB\-dumpfullversion\fR" 4 +.IX Item "-dumpfullversion" +Print the full compiler version\-\-\-and don't do anything else. The output is +always three numbers separated by dots, major, minor and patchlevel version. +.IP "\fB\-dumpspecs\fR" 4 +.IX Item "-dumpspecs" +Print the compiler's built-in specs\-\-\-and don't do anything else. (This +is used when \s-1GCC\s0 itself is being built.) +.SS "Machine-Dependent Options" +.IX Subsection "Machine-Dependent Options" +Each target machine supported by \s-1GCC\s0 can have its own options\-\-\-for +example, to allow you to compile for a particular processor variant or +\&\s-1ABI,\s0 or to control optimizations specific to that machine. By +convention, the names of machine-specific options start with +\&\fB\-m\fR. +.PP +Some configurations of the compiler also support additional target-specific +options, usually for compatibility with other compilers on the same +platform. +.PP +\fIAArch64 Options\fR +.IX Subsection "AArch64 Options" +.PP +These options are defined for AArch64 implementations: +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified data model. Permissible values +are \fBilp32\fR for SysV-like data model where int, long int and pointers +are 32 bits, and \fBlp64\fR for SysV-like data model where int is 32 bits, +but long int and pointers are 64 bits. +.Sp +The default depends on the specific target configuration. Note that +the \s-1LP64\s0 and \s-1ILP32\s0 ABIs are not link-compatible; you must compile your +entire program with the same \s-1ABI,\s0 and link with a compatible set of libraries. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate big-endian code. This is the default when \s-1GCC\s0 is configured for an +\&\fBaarch64_be\-*\-*\fR target. +.IP "\fB\-mgeneral\-regs\-only\fR" 4 +.IX Item "-mgeneral-regs-only" +Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced \s-1SIMD\s0 registers but will not +impose any restrictions on the assembler. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate little-endian code. This is the default when \s-1GCC\s0 is configured for an +\&\fBaarch64\-*\-*\fR but not an \fBaarch64_be\-*\-*\fR target. +.IP "\fB\-mcmodel=tiny\fR" 4 +.IX Item "-mcmodel=tiny" +Generate code for the tiny code model. The program and its statically defined +symbols must be within 1MB of each other. Programs can be statically or +dynamically linked. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model. The program and its statically defined +symbols must be within 4GB of each other. Programs can be statically or +dynamically linked. This is the default code model. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large code model. This makes no assumptions about +addresses and sizes of sections. Programs can be statically linked only. +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD 0 +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD +Avoid or allow generating memory accesses that may not be aligned on a natural +object boundary as described in the architecture specification. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +.PD 0 +.IP "\fB\-mno\-omit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-mno-omit-leaf-frame-pointer" +.PD +Omit or keep the frame pointer in leaf functions. The former behavior is the +default. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for a global canary or \fBsysreg\fR for a +canary in an appropriate system register. +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which system register to use as base register for reading the canary, +and from what offset from that base register. There is no default +register or offset as this is entirely for use within the Linux +kernel. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for a global canary or \fBsysreg\fR for a +canary in an appropriate system register. +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which system register to use as base register for reading the canary, +and from what offset from that base register. There is no default +register or offset as this is entirely for use within the Linux +kernel. +.IP "\fB\-mtls\-dialect=desc\fR" 4 +.IX Item "-mtls-dialect=desc" +Use \s-1TLS\s0 descriptors as the thread-local storage mechanism for dynamic accesses +of \s-1TLS\s0 variables. This is the default. +.IP "\fB\-mtls\-dialect=traditional\fR" 4 +.IX Item "-mtls-dialect=traditional" +Use traditional \s-1TLS\s0 as the thread-local storage mechanism for dynamic accesses +of \s-1TLS\s0 variables. +.IP "\fB\-mtls\-size=\fR\fIsize\fR" 4 +.IX Item "-mtls-size=size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 12, 24, 32, 48. +This option requires binutils 2.26 or newer. +.IP "\fB\-mfix\-cortex\-a53\-835769\fR" 4 +.IX Item "-mfix-cortex-a53-835769" +.PD 0 +.IP "\fB\-mno\-fix\-cortex\-a53\-835769\fR" 4 +.IX Item "-mno-fix-cortex-a53-835769" +.PD +Enable or disable the workaround for the \s-1ARM\s0 Cortex\-A53 erratum number 835769. +This involves inserting a \s-1NOP\s0 instruction between memory instructions and +64\-bit integer multiply-accumulate instructions. +.IP "\fB\-mfix\-cortex\-a53\-843419\fR" 4 +.IX Item "-mfix-cortex-a53-843419" +.PD 0 +.IP "\fB\-mno\-fix\-cortex\-a53\-843419\fR" 4 +.IX Item "-mno-fix-cortex-a53-843419" +.PD +Enable or disable the workaround for the \s-1ARM\s0 Cortex\-A53 erratum number 843419. +This erratum workaround is made at link time and this will only pass the +corresponding flag to the linker. +.IP "\fB\-mlow\-precision\-recip\-sqrt\fR" 4 +.IX Item "-mlow-precision-recip-sqrt" +.PD 0 +.IP "\fB\-mno\-low\-precision\-recip\-sqrt\fR" 4 +.IX Item "-mno-low-precision-recip-sqrt" +.PD +Enable or disable the reciprocal square root approximation. +This option only has an effect if \fB\-ffast\-math\fR or +\&\fB\-funsafe\-math\-optimizations\fR is used as well. Enabling this reduces +precision of reciprocal square root results to about 16 bits for +single precision and to 32 bits for double precision. +.IP "\fB\-mlow\-precision\-sqrt\fR" 4 +.IX Item "-mlow-precision-sqrt" +.PD 0 +.IP "\fB\-mno\-low\-precision\-sqrt\fR" 4 +.IX Item "-mno-low-precision-sqrt" +.PD +Enable or disable the square root approximation. +This option only has an effect if \fB\-ffast\-math\fR or +\&\fB\-funsafe\-math\-optimizations\fR is used as well. Enabling this reduces +precision of square root results to about 16 bits for +single precision and to 32 bits for double precision. +If enabled, it implies \fB\-mlow\-precision\-recip\-sqrt\fR. +.IP "\fB\-mlow\-precision\-div\fR" 4 +.IX Item "-mlow-precision-div" +.PD 0 +.IP "\fB\-mno\-low\-precision\-div\fR" 4 +.IX Item "-mno-low-precision-div" +.PD +Enable or disable the division approximation. +This option only has an effect if \fB\-ffast\-math\fR or +\&\fB\-funsafe\-math\-optimizations\fR is used as well. Enabling this reduces +precision of division results to about 16 bits for +single precision and to 32 bits for double precision. +.IP "\fB\-mtrack\-speculation\fR" 4 +.IX Item "-mtrack-speculation" +.PD 0 +.IP "\fB\-mno\-track\-speculation\fR" 4 +.IX Item "-mno-track-speculation" +.PD +Enable or disable generation of additional code to track speculative +execution through conditional branches. The tracking state can then +be used by the compiler when expanding calls to +\&\f(CW\*(C`_\|_builtin_speculation_safe_copy\*(C'\fR to permit a more efficient code +sequence to be generated. +.IP "\fB\-moutline\-atomics\fR" 4 +.IX Item "-moutline-atomics" +.PD 0 +.IP "\fB\-mno\-outline\-atomics\fR" 4 +.IX Item "-mno-outline-atomics" +.PD +Enable or disable calls to out-of-line helpers to implement atomic operations. +These helpers will, at runtime, determine if the \s-1LSE\s0 instructions from +ARMv8.1\-A can be used; if not, they will use the load/store\-exclusive +instructions that are present in the base ARMv8.0 \s-1ISA.\s0 +.Sp +This option is only applicable when compiling for the base ARMv8.0 +instruction set. If using a later revision, e.g. \fB\-march=armv8.1\-a\fR +or \fB\-march=armv8\-a+lse\fR, the ARMv8.1\-Atomics instructions will be +used directly. The same applies when using \fB\-mcpu=\fR when the +selected cpu supports the \fBlse\fR feature. +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +Specify the name of the target architecture and, optionally, one or +more feature modifiers. This option has the form +\&\fB\-march=\fR\fIarch\fR{\fB+\fR[\fBno\fR]\fIfeature\fR}*. +.Sp +The permissible values for \fIarch\fR are \fBarmv8\-a\fR, +\&\fBarmv8.1\-a\fR, \fBarmv8.2\-a\fR, \fBarmv8.3\-a\fR, \fBarmv8.4\-a\fR, +\&\fBarmv8.5\-a\fR or \fInative\fR. +.Sp +The value \fBarmv8.5\-a\fR implies \fBarmv8.4\-a\fR and enables compiler +support for the ARMv8.5\-A architecture extensions. +.Sp +The value \fBarmv8.4\-a\fR implies \fBarmv8.3\-a\fR and enables compiler +support for the ARMv8.4\-A architecture extensions. +.Sp +The value \fBarmv8.3\-a\fR implies \fBarmv8.2\-a\fR and enables compiler +support for the ARMv8.3\-A architecture extensions. +.Sp +The value \fBarmv8.2\-a\fR implies \fBarmv8.1\-a\fR and enables compiler +support for the ARMv8.2\-A architecture extensions. +.Sp +The value \fBarmv8.1\-a\fR implies \fBarmv8\-a\fR and enables compiler +support for the ARMv8.1\-A architecture extension. In particular, it +enables the \fB+crc\fR, \fB+lse\fR, and \fB+rdma\fR features. +.Sp +The value \fBnative\fR is available on native AArch64 GNU/Linux and +causes the compiler to pick the architecture of the host system. This +option has no effect if the compiler is unable to recognize the +architecture of the host system, +.Sp +The permissible values for \fIfeature\fR are listed in the sub-section +on \fBaarch64\-feature\-modifiers,,\fR\fB\-march\fR \fBand\fR \fB\-mcpu\fR +\&\fBFeature Modifiers\fR. Where conflicting feature modifiers are +specified, the right-most feature is used. +.Sp +\&\s-1GCC\s0 uses \fIname\fR to determine what kind of instructions it can emit +when generating assembly code. If \fB\-march\fR is specified +without either of \fB\-mtune\fR or \fB\-mcpu\fR also being +specified, the code is tuned to perform well across a range of target +processors implementing the target architecture. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +Specify the name of the target processor for which \s-1GCC\s0 should tune the +performance of the code. Permissible values for this option are: +\&\fBgeneric\fR, \fBcortex\-a35\fR, \fBcortex\-a53\fR, \fBcortex\-a55\fR, +\&\fBcortex\-a57\fR, \fBcortex\-a72\fR, \fBcortex\-a73\fR, \fBcortex\-a75\fR, +\&\fBcortex\-a76\fR, \fBares\fR, \fBexynos\-m1\fR, \fBemag\fR, \fBfalkor\fR, +\&\fBneoverse\-e1\fR, \fBneoverse\-n1\fR, \fBneoverse\-n2\fR, \fBneoverse\-v1\fR, +\&\fBneoverse\-512tvb\fR, +\&\fBqdf24xx\fR, \fBsaphira\fR, \fBphecda\fR, \fBxgene1\fR, \fBvulcan\fR, +\&\fBocteontx\fR, \fBocteontx81\fR, \fBocteontx83\fR, +\&\fBa64fx\fR, +\&\fBthunderx\fR, \fBthunderxt88\fR, +\&\fBthunderxt88p1\fR, \fBthunderxt81\fR, \fBtsv110\fR, +\&\fBthunderxt83\fR, \fBthunderx2t99\fR, \fBzeus\fR, +\&\fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a73.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR, +\&\fBcortex\-a75.cortex\-a55\fR, \fBcortex\-a76.cortex\-a55\fR +\&\fBnative\fR. +.Sp +The values \fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a73.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR, +\&\fBcortex\-a75.cortex\-a55\fR, \fBcortex\-a76.cortex\-a55\fR specify that \s-1GCC\s0 +should tune for a big.LITTLE system. +.Sp +The value \fBneoverse\-512tvb\fR specifies that \s-1GCC\s0 should tune +for Neoverse cores that (a) implement \s-1SVE\s0 and (b) have a total vector +bandwidth of 512 bits per cycle. In other words, the option tells \s-1GCC\s0 to +tune for Neoverse cores that can execute 4 128\-bit Advanced \s-1SIMD\s0 arithmetic +instructions a cycle and that can execute an equivalent number of \s-1SVE\s0 +arithmetic instructions per cycle (2 for 256\-bit \s-1SVE, 4\s0 for 128\-bit \s-1SVE\s0). +This is more general than tuning for a specific core like Neoverse V1 +but is more specific than the default tuning described below. +.Sp +Additionally on native AArch64 GNU/Linux systems the value +\&\fBnative\fR tunes performance to the host system. This option has no effect +if the compiler is unable to recognize the processor of the host system. +.Sp +Where none of \fB\-mtune=\fR, \fB\-mcpu=\fR or \fB\-march=\fR +are specified, the code is tuned to perform well across a range +of target processors. +.Sp +This option cannot be suffixed by feature modifiers. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Specify the name of the target processor, optionally suffixed by one +or more feature modifiers. This option has the form +\&\fB\-mcpu=\fR\fIcpu\fR{\fB+\fR[\fBno\fR]\fIfeature\fR}*, where +the permissible values for \fIcpu\fR are the same as those available +for \fB\-mtune\fR. The permissible values for \fIfeature\fR are +documented in the sub-section on +\&\fBaarch64\-feature\-modifiers,,\fR\fB\-march\fR \fBand\fR \fB\-mcpu\fR +\&\fBFeature Modifiers\fR. Where conflicting feature modifiers are +specified, the right-most feature is used. +.Sp +\&\s-1GCC\s0 uses \fIname\fR to determine what kind of instructions it can emit when +generating assembly code (as if by \fB\-march\fR) and to determine +the target processor for which to tune for performance (as if +by \fB\-mtune\fR). Where this option is used in conjunction +with \fB\-march\fR or \fB\-mtune\fR, those options take precedence +over the appropriate part of this option. +.Sp +\&\fB\-mcpu=neoverse\-512tvb\fR is special in that it does not refer +to a specific core, but instead refers to all Neoverse cores that +(a) implement \s-1SVE\s0 and (b) have a total vector bandwidth of 512 bits +a cycle. Unless overridden by \fB\-march\fR, +\&\fB\-mcpu=neoverse\-512tvb\fR generates code that can run on a +Neoverse V1 core, since Neoverse V1 is the first Neoverse core with +these properties. Unless overridden by \fB\-mtune\fR, +\&\fB\-mcpu=neoverse\-512tvb\fR tunes code in the same way as for +\&\fB\-mtune=neoverse\-512tvb\fR. +.IP "\fB\-moverride=\fR\fIstring\fR" 4 +.IX Item "-moverride=string" +Override tuning decisions made by the back-end in response to a +\&\fB\-mtune=\fR switch. The syntax, semantics, and accepted values +for \fIstring\fR in this option are not guaranteed to be consistent +across releases. +.Sp +This option is only intended to be useful when developing \s-1GCC.\s0 +.IP "\fB\-mverbose\-cost\-dump\fR" 4 +.IX Item "-mverbose-cost-dump" +Enable verbose cost model dumping in the debug dump files. This option is +provided for use in debugging the compiler. +.IP "\fB\-mpc\-relative\-literal\-loads\fR" 4 +.IX Item "-mpc-relative-literal-loads" +.PD 0 +.IP "\fB\-mno\-pc\-relative\-literal\-loads\fR" 4 +.IX Item "-mno-pc-relative-literal-loads" +.PD +Enable or disable PC-relative literal loads. With this option literal pools are +accessed using a single instruction and emitted after each function. This +limits the maximum size of functions to 1MB. This is enabled by default for +\&\fB\-mcmodel=tiny\fR. +.IP "\fB\-msign\-return\-address=\fR\fIscope\fR" 4 +.IX Item "-msign-return-address=scope" +Select the function scope on which return address signing will be applied. +Permissible values are \fBnone\fR, which disables return address signing, +\&\fBnon-leaf\fR, which enables pointer signing for functions which are not leaf +functions, and \fBall\fR, which enables pointer signing for all functions. The +default value is \fBnone\fR. This option has been deprecated by +\&\-mbranch\-protection. +.IP "\fB\-mbranch\-protection=\fR\fInone\fR\fB|\fR\fIstandard\fR\fB|\fR\fIpac-ret\fR\fB[+\fR\fIleaf\fR\fB]|\fR\fIbti\fR" 4 +.IX Item "-mbranch-protection=none|standard|pac-ret[+leaf]|bti" +Select the branch protection features to use. +\&\fBnone\fR is the default and turns off all types of branch protection. +\&\fBstandard\fR turns on all types of branch protection features. If a feature +has additional tuning options, then \fBstandard\fR sets it to its standard +level. +\&\fBpac\-ret[+\fR\fIleaf\fR\fB]\fR turns on return address signing to its standard +level: signing functions that save the return address to memory (non-leaf +functions will practically always do this) using the a\-key. The optional +argument \fBleaf\fR can be used to extend the signing to include leaf +functions. +\&\fBbti\fR turns on branch target identification mechanism. +.IP "\fB\-mharden\-sls=\fR\fIopts\fR" 4 +.IX Item "-mharden-sls=opts" +Enable compiler hardening against straight line speculation (\s-1SLS\s0). +\&\fIopts\fR is a comma-separated list of the following options: +.RS 4 +.IP "\fBretbr\fR" 4 +.IX Item "retbr" +.PD 0 +.IP "\fBblr\fR" 4 +.IX Item "blr" +.RE +.RS 4 +.PD +.Sp +In addition, \fB\-mharden\-sls=all\fR enables all \s-1SLS\s0 hardening while +\&\fB\-mharden\-sls=none\fR disables all \s-1SLS\s0 hardening. +.RE +.IP "\fB\-msve\-vector\-bits=\fR\fIbits\fR" 4 +.IX Item "-msve-vector-bits=bits" +Specify the number of bits in an \s-1SVE\s0 vector register. This option only has +an effect when \s-1SVE\s0 is enabled. +.Sp +\&\s-1GCC\s0 supports two forms of \s-1SVE\s0 code generation: \*(L"vector-length +agnostic\*(R" output that works with any size of vector register and +\&\*(L"vector-length specific\*(R" output that allows \s-1GCC\s0 to make assumptions +about the vector length when it is useful for optimization reasons. +The possible values of \fBbits\fR are: \fBscalable\fR, \fB128\fR, +\&\fB256\fR, \fB512\fR, \fB1024\fR and \fB2048\fR. +Specifying \fBscalable\fR selects vector-length agnostic +output. At present \fB\-msve\-vector\-bits=128\fR also generates vector-length +agnostic output. All other values generate vector-length specific code. +The behavior of these values may change in future releases and no value except +\&\fBscalable\fR should be relied on for producing code that is portable across +different hardware \s-1SVE\s0 vector lengths. +.Sp +The default is \fB\-msve\-vector\-bits=scalable\fR, which produces +vector-length agnostic code. +.PP +\fB\-march\fR and \fB\-mcpu\fR Feature Modifiers +.IX Subsection "-march and -mcpu Feature Modifiers" +.PP +Feature modifiers used with \fB\-march\fR and \fB\-mcpu\fR can be any of +the following and their inverses \fBno\fR\fIfeature\fR: +.IP "\fBcrc\fR" 4 +.IX Item "crc" +Enable \s-1CRC\s0 extension. This is on by default for +\&\fB\-march=armv8.1\-a\fR. +.IP "\fBcrypto\fR" 4 +.IX Item "crypto" +Enable Crypto extension. This also enables Advanced \s-1SIMD\s0 and floating-point +instructions. +.IP "\fBfp\fR" 4 +.IX Item "fp" +Enable floating-point instructions. This is on by default for all possible +values for options \fB\-march\fR and \fB\-mcpu\fR. +.IP "\fBsimd\fR" 4 +.IX Item "simd" +Enable Advanced \s-1SIMD\s0 instructions. This also enables floating-point +instructions. This is on by default for all possible values for options +\&\fB\-march\fR and \fB\-mcpu\fR. +.IP "\fBsve\fR" 4 +.IX Item "sve" +Enable Scalable Vector Extension instructions. This also enables Advanced +\&\s-1SIMD\s0 and floating-point instructions. +.IP "\fBlse\fR" 4 +.IX Item "lse" +Enable Large System Extension instructions. This is on by default for +\&\fB\-march=armv8.1\-a\fR. +.IP "\fBrdma\fR" 4 +.IX Item "rdma" +Enable Round Double Multiply Accumulate instructions. This is on by default +for \fB\-march=armv8.1\-a\fR. +.IP "\fBfp16\fR" 4 +.IX Item "fp16" +Enable \s-1FP16\s0 extension. This also enables floating-point instructions. +.IP "\fBfp16fml\fR" 4 +.IX Item "fp16fml" +Enable \s-1FP16\s0 fmla extension. This also enables \s-1FP16\s0 extensions and +floating-point instructions. This option is enabled by default for \fB\-march=armv8.4\-a\fR. Use of this option with architectures prior to Armv8.2\-A is not supported. +.IP "\fBrcpc\fR" 4 +.IX Item "rcpc" +Enable the RcPc extension. This does not change code generation from \s-1GCC,\s0 +but is passed on to the assembler, enabling inline asm statements to use +instructions from the RcPc extension. +.IP "\fBdotprod\fR" 4 +.IX Item "dotprod" +Enable the Dot Product extension. This also enables Advanced \s-1SIMD\s0 instructions. +.IP "\fBaes\fR" 4 +.IX Item "aes" +Enable the Armv8\-a aes and pmull crypto extension. This also enables Advanced +\&\s-1SIMD\s0 instructions. +.IP "\fBsha2\fR" 4 +.IX Item "sha2" +Enable the Armv8\-a sha2 crypto extension. This also enables Advanced \s-1SIMD\s0 instructions. +.IP "\fBsha3\fR" 4 +.IX Item "sha3" +Enable the sha512 and sha3 crypto extension. This also enables Advanced \s-1SIMD\s0 +instructions. Use of this option with architectures prior to Armv8.2\-A is not supported. +.IP "\fBsm4\fR" 4 +.IX Item "sm4" +Enable the sm3 and sm4 crypto extension. This also enables Advanced \s-1SIMD\s0 instructions. +Use of this option with architectures prior to Armv8.2\-A is not supported. +.IP "\fBprofile\fR" 4 +.IX Item "profile" +Enable the Statistical Profiling extension. This option is only to enable the +extension at the assembler level and does not affect code generation. +.IP "\fBrng\fR" 4 +.IX Item "rng" +Enable the Armv8.5\-a Random Number instructions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +.IP "\fBmemtag\fR" 4 +.IX Item "memtag" +Enable the Armv8.5\-a Memory Tagging Extensions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +.IP "\fBsb\fR" 4 +.IX Item "sb" +Enable the Armv8\-a Speculation Barrier instruction. This option is only to +enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for \fB\-march=armv8.5\-a\fR. +.IP "\fBssbs\fR" 4 +.IX Item "ssbs" +Enable the Armv8\-a Speculative Store Bypass Safe instruction. This option +is only to enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for \fB\-march=armv8.5\-a\fR. +.IP "\fBpredres\fR" 4 +.IX Item "predres" +Enable the Armv8\-a Execution and Data Prediction Restriction instructions. +This option is only to enable the extension at the assembler level and does +not affect code generation. This option is enabled by default for +\&\fB\-march=armv8.5\-a\fR. +.PP +Feature \fBcrypto\fR implies \fBaes\fR, \fBsha2\fR, and \fBsimd\fR, +which implies \fBfp\fR. +Conversely, \fBnofp\fR implies \fBnosimd\fR, which implies +\&\fBnocrypto\fR, \fBnoaes\fR and \fBnosha2\fR. +.PP +\fIAdapteva Epiphany Options\fR +.IX Subsection "Adapteva Epiphany Options" +.PP +These \fB\-m\fR options are defined for Adapteva Epiphany: +.IP "\fB\-mhalf\-reg\-file\fR" 4 +.IX Item "-mhalf-reg-file" +Don't allocate any register in the range \f(CW\*(C`r32\*(C'\fR...\f(CW\*(C`r63\*(C'\fR. +That allows code to run on hardware variants that lack these registers. +.IP "\fB\-mprefer\-short\-insn\-regs\fR" 4 +.IX Item "-mprefer-short-insn-regs" +Preferentially allocate registers that allow short instruction generation. +This can result in increased instruction count, so this may either reduce or +increase overall code size. +.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 +.IX Item "-mbranch-cost=num" +Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. +.IP "\fB\-mcmove\fR" 4 +.IX Item "-mcmove" +Enable the generation of conditional moves. +.IP "\fB\-mnops=\fR\fInum\fR" 4 +.IX Item "-mnops=num" +Emit \fInum\fR NOPs before every other generated instruction. +.IP "\fB\-mno\-soft\-cmpsf\fR" 4 +.IX Item "-mno-soft-cmpsf" +For single-precision floating-point comparisons, emit an \f(CW\*(C`fsub\*(C'\fR instruction +and test the flags. This is faster than a software comparison, but can +get incorrect results in the presence of NaNs, or when two different small +numbers are compared such that their difference is calculated as zero. +The default is \fB\-msoft\-cmpsf\fR, which uses slower, but IEEE-compliant, +software comparisons. +.IP "\fB\-mstack\-offset=\fR\fInum\fR" 4 +.IX Item "-mstack-offset=num" +Set the offset between the top of the stack and the stack pointer. +E.g., a value of 8 means that the eight bytes in the range \f(CW\*(C`sp+0...sp+7\*(C'\fR +can be used by leaf functions without stack allocation. +Values other than \fB8\fR or \fB16\fR are untested and unlikely to work. +Note also that this option changes the \s-1ABI\s0; compiling a program with a +different stack offset than the libraries have been compiled with +generally does not work. +This option can be useful if you want to evaluate if a different stack +offset would give you better code, but to actually use a different stack +offset to build working programs, it is recommended to configure the +toolchain with the appropriate \fB\-\-with\-stack\-offset=\fR\fInum\fR option. +.IP "\fB\-mno\-round\-nearest\fR" 4 +.IX Item "-mno-round-nearest" +Make the scheduler assume that the rounding mode has been set to +truncating. The default is \fB\-mround\-nearest\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +If not otherwise specified by an attribute, assume all calls might be beyond +the offset range of the \f(CW\*(C`b\*(C'\fR / \f(CW\*(C`bl\*(C'\fR instructions, and therefore load the +function address into a register before performing a (otherwise direct) call. +This is the default. +.IP "\fB\-mshort\-calls\fR" 4 +.IX Item "-mshort-calls" +If not otherwise specified by an attribute, assume all direct calls are +in the range of the \f(CW\*(C`b\*(C'\fR / \f(CW\*(C`bl\*(C'\fR instructions, so use these instructions +for direct calls. The default is \fB\-mlong\-calls\fR. +.IP "\fB\-msmall16\fR" 4 +.IX Item "-msmall16" +Assume addresses can be loaded as 16\-bit unsigned values. This does not +apply to function addresses for which \fB\-mlong\-calls\fR semantics +are in effect. +.IP "\fB\-mfp\-mode=\fR\fImode\fR" 4 +.IX Item "-mfp-mode=mode" +Set the prevailing mode of the floating-point unit. +This determines the floating-point mode that is provided and expected +at function call and return time. Making this mode match the mode you +predominantly need at function start can make your programs smaller and +faster by avoiding unnecessary mode switches. +.Sp +\&\fImode\fR can be set to one the following values: +.RS 4 +.IP "\fBcaller\fR" 4 +.IX Item "caller" +Any mode at function entry is valid, and retained or restored when +the function returns, and when it calls other functions. +This mode is useful for compiling libraries or other compilation units +you might want to incorporate into different programs with different +prevailing \s-1FPU\s0 modes, and the convenience of being able to use a single +object file outweighs the size and speed overhead for any extra +mode switching that might be needed, compared with what would be needed +with a more specific choice of prevailing \s-1FPU\s0 mode. +.IP "\fBtruncate\fR" 4 +.IX Item "truncate" +This is the mode used for floating-point calculations with +truncating (i.e. round towards zero) rounding mode. That includes +conversion from floating point to integer. +.IP "\fBround-nearest\fR" 4 +.IX Item "round-nearest" +This is the mode used for floating-point calculations with +round-to-nearest-or-even rounding mode. +.IP "\fBint\fR" 4 +.IX Item "int" +This is the mode used to perform integer calculations in the \s-1FPU,\s0 e.g. +integer multiply, or integer multiply-and-accumulate. +.RE +.RS 4 +.Sp +The default is \fB\-mfp\-mode=caller\fR +.RE +.IP "\fB\-mno\-split\-lohi\fR" 4 +.IX Item "-mno-split-lohi" +.PD 0 +.IP "\fB\-mno\-postinc\fR" 4 +.IX Item "-mno-postinc" +.IP "\fB\-mno\-postmodify\fR" 4 +.IX Item "-mno-postmodify" +.PD +Code generation tweaks that disable, respectively, splitting of 32\-bit +loads, generation of post-increment addresses, and generation of +post-modify addresses. The defaults are \fBmsplit-lohi\fR, +\&\fB\-mpost\-inc\fR, and \fB\-mpost\-modify\fR. +.IP "\fB\-mnovect\-double\fR" 4 +.IX Item "-mnovect-double" +Change the preferred \s-1SIMD\s0 mode to SImode. The default is +\&\fB\-mvect\-double\fR, which uses DImode as preferred \s-1SIMD\s0 mode. +.IP "\fB\-max\-vect\-align=\fR\fInum\fR" 4 +.IX Item "-max-vect-align=num" +The maximum alignment for \s-1SIMD\s0 vector mode types. +\&\fInum\fR may be 4 or 8. The default is 8. +Note that this is an \s-1ABI\s0 change, even though many library function +interfaces are unaffected if they don't use \s-1SIMD\s0 vector modes +in places that affect size and/or alignment of relevant types. +.IP "\fB\-msplit\-vecmove\-early\fR" 4 +.IX Item "-msplit-vecmove-early" +Split vector moves into single word moves before reload. In theory this +can give better register allocation, but so far the reverse seems to be +generally the case. +.IP "\fB\-m1reg\-\fR\fIreg\fR" 4 +.IX Item "-m1reg-reg" +Specify a register to hold the constant \-1, which makes loading small negative +constants and certain bitmasks faster. +Allowable values for \fIreg\fR are \fBr43\fR and \fBr63\fR, +which specify use of that register as a fixed register, +and \fBnone\fR, which means that no register is used for this +purpose. The default is \fB\-m1reg\-none\fR. +.PP +\fI\s-1AMD GCN\s0 Options\fR +.IX Subsection "AMD GCN Options" +.PP +These options are defined specifically for the \s-1AMD GCN\s0 port. +.IP "\fB\-march=\fR\fIgpu\fR" 4 +.IX Item "-march=gpu" +.PD 0 +.IP "\fB\-mtune=\fR\fIgpu\fR" 4 +.IX Item "-mtune=gpu" +.PD +Set architecture type or tuning for \fIgpu\fR. Supported values for \fIgpu\fR +are +.RS 4 +.IP "\fBfiji\fR" 4 +.IX Item "fiji" +Compile for \s-1GCN3\s0 Fiji devices (gfx803). +.IP "\fBgfx900\fR" 4 +.IX Item "gfx900" +Compile for \s-1GCN5\s0 Vega 10 devices (gfx900). +.RE +.RS 4 +.RE +.IP "\fB\-mstack\-size=\fR\fIbytes\fR" 4 +.IX Item "-mstack-size=bytes" +Specify how many \fIbytes\fR of stack space will be requested for each \s-1GPU\s0 +thread (wave-front). Beware that there may be many threads and limited memory +available. The size of the stack allocation may also have an impact on +run-time performance. The default is 32KB when using OpenACC or OpenMP, and +1MB otherwise. +.PP +\fI\s-1ARC\s0 Options\fR +.IX Subsection "ARC Options" +.PP +The following options control the architecture variant for which code +is being compiled: +.IP "\fB\-mbarrel\-shifter\fR" 4 +.IX Item "-mbarrel-shifter" +Generate instructions supported by barrel shifter. This is the default +unless \fB\-mcpu=ARC601\fR or \fB\-mcpu=ARCEM\fR is in effect. +.IP "\fB\-mjli\-always\fR" 4 +.IX Item "-mjli-always" +Force to call a function using jli_s instruction. This option is +valid only for ARCv2 architecture. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Set architecture type, register usage, and instruction scheduling +parameters for \fIcpu\fR. There are also shortcut alias options +available for backward compatibility and convenience. Supported +values for \fIcpu\fR are +.RS 4 +.IP "\fBarc600\fR" 4 +.IX Item "arc600" +Compile for \s-1ARC600.\s0 Aliases: \fB\-mA6\fR, \fB\-mARC600\fR. +.IP "\fBarc601\fR" 4 +.IX Item "arc601" +Compile for \s-1ARC601.\s0 Alias: \fB\-mARC601\fR. +.IP "\fBarc700\fR" 4 +.IX Item "arc700" +Compile for \s-1ARC700.\s0 Aliases: \fB\-mA7\fR, \fB\-mARC700\fR. +This is the default when configured with \fB\-\-with\-cpu=arc700\fR. +.IP "\fBarcem\fR" 4 +.IX Item "arcem" +Compile for \s-1ARC EM.\s0 +.IP "\fBarchs\fR" 4 +.IX Item "archs" +Compile for \s-1ARC HS.\s0 +.IP "\fBem\fR" 4 +.IX Item "em" +Compile for \s-1ARC EM CPU\s0 with no hardware extensions. +.IP "\fBem4\fR" 4 +.IX Item "em4" +Compile for \s-1ARC EM4 CPU.\s0 +.IP "\fBem4_dmips\fR" 4 +.IX Item "em4_dmips" +Compile for \s-1ARC EM4 DMIPS CPU.\s0 +.IP "\fBem4_fpus\fR" 4 +.IX Item "em4_fpus" +Compile for \s-1ARC EM4 DMIPS CPU\s0 with the single-precision floating-point +extension. +.IP "\fBem4_fpuda\fR" 4 +.IX Item "em4_fpuda" +Compile for \s-1ARC EM4 DMIPS CPU\s0 with single-precision floating-point and +double assist instructions. +.IP "\fBhs\fR" 4 +.IX Item "hs" +Compile for \s-1ARC HS CPU\s0 with no hardware extensions except the atomic +instructions. +.IP "\fBhs34\fR" 4 +.IX Item "hs34" +Compile for \s-1ARC HS34 CPU.\s0 +.IP "\fBhs38\fR" 4 +.IX Item "hs38" +Compile for \s-1ARC HS38 CPU.\s0 +.IP "\fBhs38_linux\fR" 4 +.IX Item "hs38_linux" +Compile for \s-1ARC HS38 CPU\s0 with all hardware extensions on. +.IP "\fBarc600_norm\fR" 4 +.IX Item "arc600_norm" +Compile for \s-1ARC 600 CPU\s0 with \f(CW\*(C`norm\*(C'\fR instructions enabled. +.IP "\fBarc600_mul32x16\fR" 4 +.IX Item "arc600_mul32x16" +Compile for \s-1ARC 600 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and 32x16\-bit multiply +instructions enabled. +.IP "\fBarc600_mul64\fR" 4 +.IX Item "arc600_mul64" +Compile for \s-1ARC 600 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and \f(CW\*(C`mul64\*(C'\fR\-family +instructions enabled. +.IP "\fBarc601_norm\fR" 4 +.IX Item "arc601_norm" +Compile for \s-1ARC 601 CPU\s0 with \f(CW\*(C`norm\*(C'\fR instructions enabled. +.IP "\fBarc601_mul32x16\fR" 4 +.IX Item "arc601_mul32x16" +Compile for \s-1ARC 601 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and 32x16\-bit multiply +instructions enabled. +.IP "\fBarc601_mul64\fR" 4 +.IX Item "arc601_mul64" +Compile for \s-1ARC 601 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and \f(CW\*(C`mul64\*(C'\fR\-family +instructions enabled. +.IP "\fBnps400\fR" 4 +.IX Item "nps400" +Compile for \s-1ARC 700\s0 on \s-1NPS400\s0 chip. +.IP "\fBem_mini\fR" 4 +.IX Item "em_mini" +Compile for \s-1ARC EM\s0 minimalist configuration featuring reduced register +set. +.RE +.RS 4 +.RE +.IP "\fB\-mdpfp\fR" 4 +.IX Item "-mdpfp" +.PD 0 +.IP "\fB\-mdpfp\-compact\fR" 4 +.IX Item "-mdpfp-compact" +.PD +Generate double-precision \s-1FPX\s0 instructions, tuned for the compact +implementation. +.IP "\fB\-mdpfp\-fast\fR" 4 +.IX Item "-mdpfp-fast" +Generate double-precision \s-1FPX\s0 instructions, tuned for the fast +implementation. +.IP "\fB\-mno\-dpfp\-lrsr\fR" 4 +.IX Item "-mno-dpfp-lrsr" +Disable \f(CW\*(C`lr\*(C'\fR and \f(CW\*(C`sr\*(C'\fR instructions from using \s-1FPX\s0 extension +aux registers. +.IP "\fB\-mea\fR" 4 +.IX Item "-mea" +Generate extended arithmetic instructions. Currently only +\&\f(CW\*(C`divaw\*(C'\fR, \f(CW\*(C`adds\*(C'\fR, \f(CW\*(C`subs\*(C'\fR, and \f(CW\*(C`sat16\*(C'\fR are +supported. This is always enabled for \fB\-mcpu=ARC700\fR. +.IP "\fB\-mno\-mpy\fR" 4 +.IX Item "-mno-mpy" +Do not generate \f(CW\*(C`mpy\*(C'\fR\-family instructions for \s-1ARC700.\s0 This option is +deprecated. +.IP "\fB\-mmul32x16\fR" 4 +.IX Item "-mmul32x16" +Generate 32x16\-bit multiply and multiply-accumulate instructions. +.IP "\fB\-mmul64\fR" 4 +.IX Item "-mmul64" +Generate \f(CW\*(C`mul64\*(C'\fR and \f(CW\*(C`mulu64\*(C'\fR instructions. +Only valid for \fB\-mcpu=ARC600\fR. +.IP "\fB\-mnorm\fR" 4 +.IX Item "-mnorm" +Generate \f(CW\*(C`norm\*(C'\fR instructions. This is the default if \fB\-mcpu=ARC700\fR +is in effect. +.IP "\fB\-mspfp\fR" 4 +.IX Item "-mspfp" +.PD 0 +.IP "\fB\-mspfp\-compact\fR" 4 +.IX Item "-mspfp-compact" +.PD +Generate single-precision \s-1FPX\s0 instructions, tuned for the compact +implementation. +.IP "\fB\-mspfp\-fast\fR" 4 +.IX Item "-mspfp-fast" +Generate single-precision \s-1FPX\s0 instructions, tuned for the fast +implementation. +.IP "\fB\-msimd\fR" 4 +.IX Item "-msimd" +Enable generation of \s-1ARC SIMD\s0 instructions via target-specific +builtins. Only valid for \fB\-mcpu=ARC700\fR. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +This option ignored; it is provided for compatibility purposes only. +Software floating-point code is emitted by default, and this default +can overridden by \s-1FPX\s0 options; \fB\-mspfp\fR, \fB\-mspfp\-compact\fR, or +\&\fB\-mspfp\-fast\fR for single precision, and \fB\-mdpfp\fR, +\&\fB\-mdpfp\-compact\fR, or \fB\-mdpfp\-fast\fR for double precision. +.IP "\fB\-mswap\fR" 4 +.IX Item "-mswap" +Generate \f(CW\*(C`swap\*(C'\fR instructions. +.IP "\fB\-matomic\fR" 4 +.IX Item "-matomic" +This enables use of the locked load/store conditional extension to implement +atomic memory built-in functions. Not available for \s-1ARC\s0 6xx or \s-1ARC +EM\s0 cores. +.IP "\fB\-mdiv\-rem\fR" 4 +.IX Item "-mdiv-rem" +Enable \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`rem\*(C'\fR instructions for ARCv2 cores. +.IP "\fB\-mcode\-density\fR" 4 +.IX Item "-mcode-density" +Enable code density instructions for \s-1ARC EM.\s0 +This option is on by default for \s-1ARC HS.\s0 +.IP "\fB\-mll64\fR" 4 +.IX Item "-mll64" +Enable double load/store operations for \s-1ARC HS\s0 cores. +.IP "\fB\-mtp\-regno=\fR\fIregno\fR" 4 +.IX Item "-mtp-regno=regno" +Specify thread pointer register number. +.IP "\fB\-mmpy\-option=\fR\fImulto\fR" 4 +.IX Item "-mmpy-option=multo" +Compile ARCv2 code with a multiplier design option. You can specify +the option using either a string or numeric value for \fImulto\fR. +\&\fBwlh1\fR is the default value. The recognized values are: +.RS 4 +.IP "\fB0\fR" 4 +.IX Item "0" +.PD 0 +.IP "\fBnone\fR" 4 +.IX Item "none" +.PD +No multiplier available. +.IP "\fB1\fR" 4 +.IX Item "1" +.PD 0 +.IP "\fBw\fR" 4 +.IX Item "w" +.PD +16x16 multiplier, fully pipelined. +The following instructions are enabled: \f(CW\*(C`mpyw\*(C'\fR and \f(CW\*(C`mpyuw\*(C'\fR. +.IP "\fB2\fR" 4 +.IX Item "2" +.PD 0 +.IP "\fBwlh1\fR" 4 +.IX Item "wlh1" +.PD +32x32 multiplier, fully +pipelined (1 stage). The following instructions are additionally +enabled: \f(CW\*(C`mpy\*(C'\fR, \f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB3\fR" 4 +.IX Item "3" +.PD 0 +.IP "\fBwlh2\fR" 4 +.IX Item "wlh2" +.PD +32x32 multiplier, fully pipelined +(2 stages). The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB4\fR" 4 +.IX Item "4" +.PD 0 +.IP "\fBwlh3\fR" 4 +.IX Item "wlh3" +.PD +Two 16x16 multipliers, blocking, +sequential. The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB5\fR" 4 +.IX Item "5" +.PD 0 +.IP "\fBwlh4\fR" 4 +.IX Item "wlh4" +.PD +One 16x16 multiplier, blocking, +sequential. The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB6\fR" 4 +.IX Item "6" +.PD 0 +.IP "\fBwlh5\fR" 4 +.IX Item "wlh5" +.PD +One 32x4 multiplier, blocking, +sequential. The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB7\fR" 4 +.IX Item "7" +.PD 0 +.IP "\fBplus_dmpy\fR" 4 +.IX Item "plus_dmpy" +.PD +\&\s-1ARC HS SIMD\s0 support. +.IP "\fB8\fR" 4 +.IX Item "8" +.PD 0 +.IP "\fBplus_macd\fR" 4 +.IX Item "plus_macd" +.PD +\&\s-1ARC HS SIMD\s0 support. +.IP "\fB9\fR" 4 +.IX Item "9" +.PD 0 +.IP "\fBplus_qmacw\fR" 4 +.IX Item "plus_qmacw" +.PD +\&\s-1ARC HS SIMD\s0 support. +.RE +.RS 4 +.Sp +This option is only available for ARCv2 cores. +.RE +.IP "\fB\-mfpu=\fR\fIfpu\fR" 4 +.IX Item "-mfpu=fpu" +Enables support for specific floating-point hardware extensions for ARCv2 +cores. Supported values for \fIfpu\fR are: +.RS 4 +.IP "\fBfpus\fR" 4 +.IX Item "fpus" +Enables support for single-precision floating-point hardware +extensions. +.IP "\fBfpud\fR" 4 +.IX Item "fpud" +Enables support for double-precision floating-point hardware +extensions. The single-precision floating-point extension is also +enabled. Not available for \s-1ARC EM.\s0 +.IP "\fBfpuda\fR" 4 +.IX Item "fpuda" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. The single-precision +floating-point extension is also enabled. This option is +only available for \s-1ARC EM.\s0 +.IP "\fBfpuda_div\fR" 4 +.IX Item "fpuda_div" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. +The single-precision floating-point, square-root, and divide +extensions are also enabled. This option is +only available for \s-1ARC EM.\s0 +.IP "\fBfpuda_fma\fR" 4 +.IX Item "fpuda_fma" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. +The single-precision floating-point and fused multiply and add +hardware extensions are also enabled. This option is +only available for \s-1ARC EM.\s0 +.IP "\fBfpuda_all\fR" 4 +.IX Item "fpuda_all" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. +All single-precision floating-point hardware extensions are also +enabled. This option is only available for \s-1ARC EM.\s0 +.IP "\fBfpus_div\fR" 4 +.IX Item "fpus_div" +Enables support for single-precision floating-point, square-root and divide +hardware extensions. +.IP "\fBfpud_div\fR" 4 +.IX Item "fpud_div" +Enables support for double-precision floating-point, square-root and divide +hardware extensions. This option +includes option \fBfpus_div\fR. Not available for \s-1ARC EM.\s0 +.IP "\fBfpus_fma\fR" 4 +.IX Item "fpus_fma" +Enables support for single-precision floating-point and +fused multiply and add hardware extensions. +.IP "\fBfpud_fma\fR" 4 +.IX Item "fpud_fma" +Enables support for double-precision floating-point and +fused multiply and add hardware extensions. This option +includes option \fBfpus_fma\fR. Not available for \s-1ARC EM.\s0 +.IP "\fBfpus_all\fR" 4 +.IX Item "fpus_all" +Enables support for all single-precision floating-point hardware +extensions. +.IP "\fBfpud_all\fR" 4 +.IX Item "fpud_all" +Enables support for all single\- and double-precision floating-point +hardware extensions. Not available for \s-1ARC EM.\s0 +.RE +.RS 4 +.RE +.IP "\fB\-mirq\-ctrl\-saved=\fR\fIregister-range\fR\fB,\fR \fIblink\fR\fB,\fR \fIlp_count\fR" 4 +.IX Item "-mirq-ctrl-saved=register-range, blink, lp_count" +Specifies general-purposes registers that the processor automatically +saves/restores on interrupt entry and exit. \fIregister-range\fR is +specified as two registers separated by a dash. The register range +always starts with \f(CW\*(C`r0\*(C'\fR, the upper limit is \f(CW\*(C`fp\*(C'\fR register. +\&\fIblink\fR and \fIlp_count\fR are optional. This option is only +valid for \s-1ARC EM\s0 and \s-1ARC HS\s0 cores. +.IP "\fB\-mrgf\-banked\-regs=\fR\fInumber\fR" 4 +.IX Item "-mrgf-banked-regs=number" +Specifies the number of registers replicated in second register bank +on entry to fast interrupt. Fast interrupts are interrupts with the +highest priority level P0. These interrupts save only \s-1PC\s0 and \s-1STATUS32\s0 +registers to avoid memory transactions during interrupt entry and exit +sequences. Use this option when you are using fast interrupts in an +\&\s-1ARC V2\s0 family processor. Permitted values are 4, 8, 16, and 32. +.IP "\fB\-mlpc\-width=\fR\fIwidth\fR" 4 +.IX Item "-mlpc-width=width" +Specify the width of the \f(CW\*(C`lp_count\*(C'\fR register. Valid values for +\&\fIwidth\fR are 8, 16, 20, 24, 28 and 32 bits. The default width is +fixed to 32 bits. If the width is less than 32, the compiler does not +attempt to transform loops in your program to use the zero-delay loop +mechanism unless it is known that the \f(CW\*(C`lp_count\*(C'\fR register can +hold the required loop-counter value. Depending on the width +specified, the compiler and run-time library might continue to use the +loop mechanism for various needs. This option defines macro +\&\f(CW\*(C`_\|_ARC_LPC_WIDTH_\|_\*(C'\fR with the value of \fIwidth\fR. +.IP "\fB\-mrf16\fR" 4 +.IX Item "-mrf16" +This option instructs the compiler to generate code for a 16\-entry +register file. This option defines the \f(CW\*(C`_\|_ARC_RF16_\|_\*(C'\fR +preprocessor macro. +.IP "\fB\-mbranch\-index\fR" 4 +.IX Item "-mbranch-index" +Enable use of \f(CW\*(C`bi\*(C'\fR or \f(CW\*(C`bih\*(C'\fR instructions to implement jump +tables. +.PP +The following options are passed through to the assembler, and also +define preprocessor macro symbols. +.IP "\fB\-mdsp\-packa\fR" 4 +.IX Item "-mdsp-packa" +Passed down to the assembler to enable the \s-1DSP\s0 Pack A extensions. +Also sets the preprocessor symbol \f(CW\*(C`_\|_Xdsp_packa\*(C'\fR. This option is +deprecated. +.IP "\fB\-mdvbf\fR" 4 +.IX Item "-mdvbf" +Passed down to the assembler to enable the dual Viterbi butterfly +extension. Also sets the preprocessor symbol \f(CW\*(C`_\|_Xdvbf\*(C'\fR. This +option is deprecated. +.IP "\fB\-mlock\fR" 4 +.IX Item "-mlock" +Passed down to the assembler to enable the locked load/store +conditional extension. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xlock\*(C'\fR. +.IP "\fB\-mmac\-d16\fR" 4 +.IX Item "-mmac-d16" +Passed down to the assembler. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xxmac_d16\*(C'\fR. This option is deprecated. +.IP "\fB\-mmac\-24\fR" 4 +.IX Item "-mmac-24" +Passed down to the assembler. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xxmac_24\*(C'\fR. This option is deprecated. +.IP "\fB\-mrtsc\fR" 4 +.IX Item "-mrtsc" +Passed down to the assembler to enable the 64\-bit time-stamp counter +extension instruction. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xrtsc\*(C'\fR. This option is deprecated. +.IP "\fB\-mswape\fR" 4 +.IX Item "-mswape" +Passed down to the assembler to enable the swap byte ordering +extension instruction. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xswape\*(C'\fR. +.IP "\fB\-mtelephony\fR" 4 +.IX Item "-mtelephony" +Passed down to the assembler to enable dual\- and single-operand +instructions for telephony. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xtelephony\*(C'\fR. This option is deprecated. +.IP "\fB\-mxy\fR" 4 +.IX Item "-mxy" +Passed down to the assembler to enable the \s-1XY\s0 memory extension. Also +sets the preprocessor symbol \f(CW\*(C`_\|_Xxy\*(C'\fR. +.PP +The following options control how the assembly code is annotated: +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Annotate assembler instructions with estimated addresses. +.IP "\fB\-mannotate\-align\fR" 4 +.IX Item "-mannotate-align" +Explain what alignment considerations lead to the decision to make an +instruction short or long. +.PP +The following options are passed through to the linker: +.IP "\fB\-marclinux\fR" 4 +.IX Item "-marclinux" +Passed through to the linker, to specify use of the \f(CW\*(C`arclinux\*(C'\fR emulation. +This option is enabled by default in tool chains built for +\&\f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets +when profiling is not requested. +.IP "\fB\-marclinux_prof\fR" 4 +.IX Item "-marclinux_prof" +Passed through to the linker, to specify use of the +\&\f(CW\*(C`arclinux_prof\*(C'\fR emulation. This option is enabled by default in +tool chains built for \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and +\&\f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets when profiling is requested. +.PP +The following options control the semantics of generated code: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Generate calls as register indirect calls, thus providing access +to the full 32\-bit address range. +.IP "\fB\-mmedium\-calls\fR" 4 +.IX Item "-mmedium-calls" +Don't use less than 25\-bit addressing range for calls, which is the +offset available for an unconditional branch-and-link +instruction. Conditional execution of function calls is suppressed, to +allow use of the 25\-bit range, rather than the 21\-bit range with +conditional branch-and-link. This is the default for tool chains built +for \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put definitions of externally-visible data in a small data section if +that data is no bigger than \fInum\fR bytes. The default value of +\&\fInum\fR is 4 for any \s-1ARC\s0 configuration, or 8 when we have double +load/store operations. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +Do not generate sdata references. This is the default for tool chains +built for \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR +targets. +.IP "\fB\-mvolatile\-cache\fR" 4 +.IX Item "-mvolatile-cache" +Use ordinarily cached memory accesses for volatile references. This is the +default. +.IP "\fB\-mno\-volatile\-cache\fR" 4 +.IX Item "-mno-volatile-cache" +Enable cache bypass for volatile references. +.PP +The following options fine tune code generation: +.IP "\fB\-malign\-call\fR" 4 +.IX Item "-malign-call" +Do alignment optimizations for call instructions. +.IP "\fB\-mauto\-modify\-reg\fR" 4 +.IX Item "-mauto-modify-reg" +Enable the use of pre/post modify with register displacement. +.IP "\fB\-mbbit\-peephole\fR" 4 +.IX Item "-mbbit-peephole" +Enable bbit peephole2. +.IP "\fB\-mno\-brcc\fR" 4 +.IX Item "-mno-brcc" +This option disables a target-specific pass in \fIarc_reorg\fR to +generate compare-and-branch (\f(CW\*(C`br\f(CIcc\f(CW\*(C'\fR) instructions. +It has no effect on +generation of these instructions driven by the combiner pass. +.IP "\fB\-mcase\-vector\-pcrel\fR" 4 +.IX Item "-mcase-vector-pcrel" +Use PC-relative switch case tables to enable case table shortening. +This is the default for \fB\-Os\fR. +.IP "\fB\-mcompact\-casesi\fR" 4 +.IX Item "-mcompact-casesi" +Enable compact \f(CW\*(C`casesi\*(C'\fR pattern. This is the default for \fB\-Os\fR, +and only available for ARCv1 cores. This option is deprecated. +.IP "\fB\-mno\-cond\-exec\fR" 4 +.IX Item "-mno-cond-exec" +Disable the ARCompact-specific pass to generate conditional +execution instructions. +.Sp +Due to delay slot scheduling and interactions between operand numbers, +literal sizes, instruction lengths, and the support for conditional execution, +the target-independent pass to generate conditional execution is often lacking, +so the \s-1ARC\s0 port has kept a special pass around that tries to find more +conditional execution generation opportunities after register allocation, +branch shortening, and delay slot scheduling have been done. This pass +generally, but not always, improves performance and code size, at the cost of +extra compilation time, which is why there is an option to switch it off. +If you have a problem with call instructions exceeding their allowable +offset range because they are conditionalized, you should consider using +\&\fB\-mmedium\-calls\fR instead. +.IP "\fB\-mearly\-cbranchsi\fR" 4 +.IX Item "-mearly-cbranchsi" +Enable pre-reload use of the \f(CW\*(C`cbranchsi\*(C'\fR pattern. +.IP "\fB\-mexpand\-adddi\fR" 4 +.IX Item "-mexpand-adddi" +Expand \f(CW\*(C`adddi3\*(C'\fR and \f(CW\*(C`subdi3\*(C'\fR at \s-1RTL\s0 generation time into +\&\f(CW\*(C`add.f\*(C'\fR, \f(CW\*(C`adc\*(C'\fR etc. This option is deprecated. +.IP "\fB\-mindexed\-loads\fR" 4 +.IX Item "-mindexed-loads" +Enable the use of indexed loads. This can be problematic because some +optimizers then assume that indexed stores exist, which is not +the case. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Enable Local Register Allocation. This is still experimental for \s-1ARC,\s0 +so by default the compiler uses standard reload +(i.e. \fB\-mno\-lra\fR). +.IP "\fB\-mlra\-priority\-none\fR" 4 +.IX Item "-mlra-priority-none" +Don't indicate any priority for target registers. +.IP "\fB\-mlra\-priority\-compact\fR" 4 +.IX Item "-mlra-priority-compact" +Indicate target register priority for r0..r3 / r12..r15. +.IP "\fB\-mlra\-priority\-noncompact\fR" 4 +.IX Item "-mlra-priority-noncompact" +Reduce target register priority for r0..r3 / r12..r15. +.IP "\fB\-mmillicode\fR" 4 +.IX Item "-mmillicode" +When optimizing for size (using \fB\-Os\fR), prologues and epilogues +that have to save or restore a large number of registers are often +shortened by using call to a special function in libgcc; this is +referred to as a \fImillicode\fR call. As these calls can pose +performance issues, and/or cause linking issues when linking in a +nonstandard way, this option is provided to turn on or off millicode +call generation. +.IP "\fB\-mcode\-density\-frame\fR" 4 +.IX Item "-mcode-density-frame" +This option enable the compiler to emit \f(CW\*(C`enter\*(C'\fR and \f(CW\*(C`leave\*(C'\fR +instructions. These instructions are only valid for CPUs with +code-density feature. +.IP "\fB\-mmixed\-code\fR" 4 +.IX Item "-mmixed-code" +Tweak register allocation to help 16\-bit instruction generation. +This generally has the effect of decreasing the average instruction size +while increasing the instruction count. +.IP "\fB\-mq\-class\fR" 4 +.IX Item "-mq-class" +Enable \fBq\fR instruction alternatives. +This is the default for \fB\-Os\fR. +.IP "\fB\-mRcq\fR" 4 +.IX Item "-mRcq" +Enable \fBRcq\fR constraint handling. +Most short code generation depends on this. +This is the default. +.IP "\fB\-mRcw\fR" 4 +.IX Item "-mRcw" +Enable \fBRcw\fR constraint handling. +Most ccfsm condexec mostly depends on this. +This is the default. +.IP "\fB\-msize\-level=\fR\fIlevel\fR" 4 +.IX Item "-msize-level=level" +Fine-tune size optimization with regards to instruction lengths and alignment. +The recognized values for \fIlevel\fR are: +.RS 4 +.IP "\fB0\fR" 4 +.IX Item "0" +No size optimization. This level is deprecated and treated like \fB1\fR. +.IP "\fB1\fR" 4 +.IX Item "1" +Short instructions are used opportunistically. +.IP "\fB2\fR" 4 +.IX Item "2" +In addition, alignment of loops and of code after barriers are dropped. +.IP "\fB3\fR" 4 +.IX Item "3" +In addition, optional data alignment is dropped, and the option \fBOs\fR is enabled. +.RE +.RS 4 +.Sp +This defaults to \fB3\fR when \fB\-Os\fR is in effect. Otherwise, +the behavior when this is not set is equivalent to level \fB1\fR. +.RE +.IP "\fB\-mtune=\fR\fIcpu\fR" 4 +.IX Item "-mtune=cpu" +Set instruction scheduling parameters for \fIcpu\fR, overriding any implied +by \fB\-mcpu=\fR. +.Sp +Supported values for \fIcpu\fR are +.RS 4 +.IP "\fB\s-1ARC600\s0\fR" 4 +.IX Item "ARC600" +Tune for \s-1ARC600 CPU.\s0 +.IP "\fB\s-1ARC601\s0\fR" 4 +.IX Item "ARC601" +Tune for \s-1ARC601 CPU.\s0 +.IP "\fB\s-1ARC700\s0\fR" 4 +.IX Item "ARC700" +Tune for \s-1ARC700 CPU\s0 with standard multiplier block. +.IP "\fBARC700\-xmac\fR" 4 +.IX Item "ARC700-xmac" +Tune for \s-1ARC700 CPU\s0 with \s-1XMAC\s0 block. +.IP "\fB\s-1ARC725D\s0\fR" 4 +.IX Item "ARC725D" +Tune for \s-1ARC725D CPU.\s0 +.IP "\fB\s-1ARC750D\s0\fR" 4 +.IX Item "ARC750D" +Tune for \s-1ARC750D CPU.\s0 +.RE +.RS 4 +.RE +.IP "\fB\-mmultcost=\fR\fInum\fR" 4 +.IX Item "-mmultcost=num" +Cost to assume for a multiply instruction, with \fB4\fR being equal to a +normal instruction. +.IP "\fB\-munalign\-prob\-threshold=\fR\fIprobability\fR" 4 +.IX Item "-munalign-prob-threshold=probability" +Set probability threshold for unaligning branches. +When tuning for \fB\s-1ARC700\s0\fR and optimizing for speed, branches without +filled delay slot are preferably emitted unaligned and long, unless +profiling indicates that the probability for the branch to be taken +is below \fIprobability\fR. +The default is (\s-1REG_BR_PROB_BASE/2\s0), i.e. 5000. +.PP +The following options are maintained for backward compatibility, but +are now deprecated and will be removed in a future release: +.IP "\fB\-margonaut\fR" 4 +.IX Item "-margonaut" +Obsolete \s-1FPX.\s0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +.PD +Compile code for big-endian targets. Use of these options is now +deprecated. Big-endian code is supported by configuring \s-1GCC\s0 to build +\&\f(CW\*(C`arceb\-elf32\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets, +for which big endian is the default. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD 0 +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +.PD +Compile code for little-endian targets. Use of these options is now +deprecated. Little-endian code is supported by configuring \s-1GCC\s0 to build +\&\f(CW\*(C`arc\-elf32\*(C'\fR and \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR targets, +for which little endian is the default. +.IP "\fB\-mbarrel_shifter\fR" 4 +.IX Item "-mbarrel_shifter" +Replaced by \fB\-mbarrel\-shifter\fR. +.IP "\fB\-mdpfp_compact\fR" 4 +.IX Item "-mdpfp_compact" +Replaced by \fB\-mdpfp\-compact\fR. +.IP "\fB\-mdpfp_fast\fR" 4 +.IX Item "-mdpfp_fast" +Replaced by \fB\-mdpfp\-fast\fR. +.IP "\fB\-mdsp_packa\fR" 4 +.IX Item "-mdsp_packa" +Replaced by \fB\-mdsp\-packa\fR. +.IP "\fB\-mEA\fR" 4 +.IX Item "-mEA" +Replaced by \fB\-mea\fR. +.IP "\fB\-mmac_24\fR" 4 +.IX Item "-mmac_24" +Replaced by \fB\-mmac\-24\fR. +.IP "\fB\-mmac_d16\fR" 4 +.IX Item "-mmac_d16" +Replaced by \fB\-mmac\-d16\fR. +.IP "\fB\-mspfp_compact\fR" 4 +.IX Item "-mspfp_compact" +Replaced by \fB\-mspfp\-compact\fR. +.IP "\fB\-mspfp_fast\fR" 4 +.IX Item "-mspfp_fast" +Replaced by \fB\-mspfp\-fast\fR. +.IP "\fB\-mtune=\fR\fIcpu\fR" 4 +.IX Item "-mtune=cpu" +Values \fBarc600\fR, \fBarc601\fR, \fBarc700\fR and +\&\fBarc700\-xmac\fR for \fIcpu\fR are replaced by \fB\s-1ARC600\s0\fR, +\&\fB\s-1ARC601\s0\fR, \fB\s-1ARC700\s0\fR and \fBARC700\-xmac\fR respectively. +.IP "\fB\-multcost=\fR\fInum\fR" 4 +.IX Item "-multcost=num" +Replaced by \fB\-mmultcost\fR. +.PP +\fI\s-1ARM\s0 Options\fR +.IX Subsection "ARM Options" +.PP +These \fB\-m\fR options are defined for the \s-1ARM\s0 port: +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified \s-1ABI.\s0 Permissible values are: \fBapcs-gnu\fR, +\&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. +.IP "\fB\-mapcs\-frame\fR" 4 +.IX Item "-mapcs-frame" +Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call +Standard for all functions, even if this is not strictly necessary for +correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR +with this option causes the stack frames not to be generated for +leaf functions. The default is \fB\-mno\-apcs\-frame\fR. +This option is deprecated. +.IP "\fB\-mapcs\fR" 4 +.IX Item "-mapcs" +This is a synonym for \fB\-mapcs\-frame\fR and is deprecated. +.IP "\fB\-mthumb\-interwork\fR" 4 +.IX Item "-mthumb-interwork" +Generate code that supports calling between the \s-1ARM\s0 and Thumb +instruction sets. Without this option, on pre\-v5 architectures, the +two instruction sets cannot be reliably used inside one program. The +default is \fB\-mno\-thumb\-interwork\fR, since slightly larger code +is generated when \fB\-mthumb\-interwork\fR is specified. In \s-1AAPCS\s0 +configurations this option is meaningless. +.IP "\fB\-mno\-sched\-prolog\fR" 4 +.IX Item "-mno-sched-prolog" +Prevent the reordering of instructions in the function prologue, or the +merging of those instruction with the instructions in the function's +body. This means that all functions start with a recognizable set +of instructions (or in fact one of a choice from a small set of +different function prologues), and this information can be used to +locate the start of functions inside an executable piece of code. The +default is \fB\-msched\-prolog\fR. +.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4 +.IX Item "-mfloat-abi=name" +Specifies which floating-point \s-1ABI\s0 to use. Permissible values +are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR. +.Sp +Specifying \fBsoft\fR causes \s-1GCC\s0 to generate output containing +library calls for floating-point operations. +\&\fBsoftfp\fR allows the generation of code using hardware floating-point +instructions, but still uses the soft-float calling conventions. +\&\fBhard\fR allows generation of floating-point instructions +and uses FPU-specific calling conventions. +.Sp +The default depends on the specific target configuration. Note that +the hard-float and soft-float ABIs are not link-compatible; you must +compile your entire program with the same \s-1ABI,\s0 and link with a +compatible set of libraries. +.IP "\fB\-mgeneral\-regs\-only\fR" 4 +.IX Item "-mgeneral-regs-only" +Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced \s-1SIMD\s0 registers but will not +impose any restrictions on the assembler. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a processor running in little-endian mode. This is +the default for all standard configurations. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a processor running in big-endian mode; the default is +to compile code for a little-endian processor. +.IP "\fB\-mbe8\fR" 4 +.IX Item "-mbe8" +.PD 0 +.IP "\fB\-mbe32\fR" 4 +.IX Item "-mbe32" +.PD +When linking a big-endian image select between \s-1BE8\s0 and \s-1BE32\s0 formats. +The option has no effect for little-endian images and is ignored. The +default is dependent on the selected target architecture. For ARMv6 +and later architectures the default is \s-1BE8,\s0 for older architectures +the default is \s-1BE32.\s0 \s-1BE32\s0 format has been deprecated by \s-1ARM.\s0 +.IP "\fB\-march=\fR\fIname\fR[\fB+extension...\fR]" 4 +.IX Item "-march=name[+extension...]" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. +.Sp +Permissible names are: +\&\fBarmv4t\fR, +\&\fBarmv5t\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, \fBarmv6k\fR, \fBarmv6kz\fR, \fBarmv6t2\fR, +\&\fBarmv6z\fR, \fBarmv6zk\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7ve\fR, +\&\fBarmv8\-a\fR, \fBarmv8.1\-a\fR, \fBarmv8.2\-a\fR, \fBarmv8.3\-a\fR, +\&\fBarmv8.4\-a\fR, +\&\fBarmv8.5\-a\fR, +\&\fBarmv7\-r\fR, +\&\fBarmv8\-r\fR, +\&\fBarmv6\-m\fR, \fBarmv6s\-m\fR, +\&\fBarmv7\-m\fR, \fBarmv7e\-m\fR, +\&\fBarmv8\-m.base\fR, \fBarmv8\-m.main\fR, +\&\fBiwmmxt\fR and \fBiwmmxt2\fR. +.Sp +Additionally, the following architectures, which lack support for the +Thumb execution state, are recognized but support is deprecated: \fBarmv4\fR. +.Sp +Many of the architectures support extensions. These can be added by +appending \fB+\fR\fIextension\fR to the architecture name. Extension +options are processed in order and capabilities accumulate. An extension +will also enable any necessary base extensions +upon which it depends. For example, the \fB+crypto\fR extension +will always enable the \fB+simd\fR extension. The exception to the +additive construction is for extensions that are prefixed with +\&\fB+no...\fR: these extensions disable the specified option and +any other extensions that may depend on the presence of that +extension. +.Sp +For example, \fB\-march=armv7\-a+simd+nofp+vfpv4\fR is equivalent to +writing \fB\-march=armv7\-a+vfpv4\fR since the \fB+simd\fR option is +entirely disabled by the \fB+nofp\fR option that follows it. +.Sp +Most extension names are generically named, but have an effect that is +dependent upon the architecture to which it is applied. For example, +the \fB+simd\fR option can be applied to both \fBarmv7\-a\fR and +\&\fBarmv8\-a\fR architectures, but will enable the original ARMv7\-A +Advanced \s-1SIMD\s0 (Neon) extensions for \fBarmv7\-a\fR and the ARMv8\-A +variant for \fBarmv8\-a\fR. +.Sp +The table below lists the supported extensions for each architecture. +Architectures not mentioned do not support any extensions. +.RS 4 +.IP "\fBarmv5te\fR" 4 +.IX Item "armv5te" +.PD 0 +.IP "\fBarmv6\fR" 4 +.IX Item "armv6" +.IP "\fBarmv6j\fR" 4 +.IX Item "armv6j" +.IP "\fBarmv6k\fR" 4 +.IX Item "armv6k" +.IP "\fBarmv6kz\fR" 4 +.IX Item "armv6kz" +.IP "\fBarmv6t2\fR" 4 +.IX Item "armv6t2" +.IP "\fBarmv6z\fR" 4 +.IX Item "armv6z" +.IP "\fBarmv6zk\fR" 4 +.IX Item "armv6zk" +.RS 4 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +.PD +The VFPv2 floating-point instructions. The extension \fB+vfpv2\fR can be +used as an alias for this extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7\fR" 4 +.IX Item "armv7" +The common subset of the ARMv7\-A, ARMv7\-R and ARMv7\-M architectures. +.RS 4 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension \fB+vfpv3\-d16\fR can be used as an alias +for this extension. Note that floating-point is not supported by the +base ARMv7\-M architecture, but is compatible with both the ARMv7\-A and +ARMv7\-R architectures. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7\-a\fR" 4 +.IX Item "armv7-a" +.RS 4 +.PD 0 +.IP "\fB+mp\fR" 4 +.IX Item "+mp" +.PD +The multiprocessing extension. +.IP "\fB+sec\fR" 4 +.IX Item "+sec" +The security extension. +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension \fB+vfpv3\-d16\fR can be used as an alias +for this extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions. +The extensions \fB+neon\fR and \fB+neon\-vfpv3\fR can be used as aliases +for this extension. +.IP "\fB+vfpv3\fR" 4 +.IX Item "+vfpv3" +The VFPv3 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+vfpv3\-d16\-fp16\fR" 4 +.IX Item "+vfpv3-d16-fp16" +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv3\-fp16\fR" 4 +.IX Item "+vfpv3-fp16" +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv4\-d16\fR" 4 +.IX Item "+vfpv4-d16" +The VFPv4 floating-point instructions, with 16 double-precision +registers. +.IP "\fB+vfpv4\fR" 4 +.IX Item "+vfpv4" +The VFPv4 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+neon\-fp16\fR" 4 +.IX Item "+neon-fp16" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. +.IP "\fB+neon\-vfpv4\fR" 4 +.IX Item "+neon-vfpv4" +The Advanced \s-1SIMD\s0 (Neon) v2 and the VFPv4 floating-point instructions. +.IP "\fB+nosimd\fR" 4 +.IX Item "+nosimd" +Disable the Advanced \s-1SIMD\s0 instructions (does not disable floating point). +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point and Advanced \s-1SIMD\s0 instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7ve\fR" 4 +.IX Item "armv7ve" +The extended version of the ARMv7\-A architecture with support for +virtualization. +.RS 4 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv4 floating-point instructions, with 16 double-precision registers. +The extension \fB+vfpv4\-d16\fR can be used as an alias for this extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The Advanced \s-1SIMD\s0 (Neon) v2 and the VFPv4 floating-point instructions. The +extension \fB+neon\-vfpv4\fR can be used as an alias for this extension. +.IP "\fB+vfpv3\-d16\fR" 4 +.IX Item "+vfpv3-d16" +The VFPv3 floating-point instructions, with 16 double-precision +registers. +.IP "\fB+vfpv3\fR" 4 +.IX Item "+vfpv3" +The VFPv3 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+vfpv3\-d16\-fp16\fR" 4 +.IX Item "+vfpv3-d16-fp16" +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv3\-fp16\fR" 4 +.IX Item "+vfpv3-fp16" +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv4\-d16\fR" 4 +.IX Item "+vfpv4-d16" +The VFPv4 floating-point instructions, with 16 double-precision +registers. +.IP "\fB+vfpv4\fR" 4 +.IX Item "+vfpv4" +The VFPv4 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+neon\fR" 4 +.IX Item "+neon" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions. +The extension \fB+neon\-vfpv3\fR can be used as an alias for this extension. +.IP "\fB+neon\-fp16\fR" 4 +.IX Item "+neon-fp16" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. +.IP "\fB+nosimd\fR" 4 +.IX Item "+nosimd" +Disable the Advanced \s-1SIMD\s0 instructions (does not disable floating point). +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point and Advanced \s-1SIMD\s0 instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8\-a\fR" 4 +.IX Item "armv8-a" +.RS 4 +.PD 0 +.IP "\fB+crc\fR" 4 +.IX Item "+crc" +.PD +The Cyclic Redundancy Check (\s-1CRC\s0) instructions. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.1\-a\fR" 4 +.IX Item "armv8.1-a" +.RS 4 +.PD 0 +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +.PD +The ARMv8.1\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.2\-a\fR" 4 +.IX Item "armv8.2-a" +.PD 0 +.IP "\fBarmv8.3\-a\fR" 4 +.IX Item "armv8.3-a" +.RS 4 +.IP "\fB+fp16\fR" 4 +.IX Item "+fp16" +.PD +The half-precision floating-point data processing instructions. +This also enables the Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+fp16fml\fR" 4 +.IX Item "+fp16fml" +The half-precision floating-point fmla extension. This also enables +the half-precision floating-point extension and Advanced \s-1SIMD\s0 and +floating-point instructions. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8.1\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions. +.IP "\fB+dotprod\fR" 4 +.IX Item "+dotprod" +Enable the Dot Product extension. This also enables Advanced \s-1SIMD\s0 instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.4\-a\fR" 4 +.IX Item "armv8.4-a" +.RS 4 +.PD 0 +.IP "\fB+fp16\fR" 4 +.IX Item "+fp16" +.PD +The half-precision floating-point data processing instructions. +This also enables the Advanced \s-1SIMD\s0 and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8.3\-A Advanced \s-1SIMD\s0 and floating-point instructions as well as the +Dot Product extension. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions as well as the Dot Product extension. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.5\-a\fR" 4 +.IX Item "armv8.5-a" +.RS 4 +.PD 0 +.IP "\fB+fp16\fR" 4 +.IX Item "+fp16" +.PD +The half-precision floating-point data processing instructions. +This also enables the Advanced \s-1SIMD\s0 and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8.3\-A Advanced \s-1SIMD\s0 and floating-point instructions as well as the +Dot Product extension. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions as well as the Dot Product extension. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7\-r\fR" 4 +.IX Item "armv7-r" +.RS 4 +.PD 0 +.IP "\fB+fp.sp\fR" 4 +.IX Item "+fp.sp" +.PD +The single-precision VFPv3 floating-point instructions. The extension +\&\fB+vfpv3xd\fR can be used as an alias for this extension. +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv3 floating-point instructions with 16 double-precision registers. +The extension +vfpv3\-d16 can be used as an alias for this extension. +.IP "\fB+vfpv3xd\-d16\-fp16\fR" 4 +.IX Item "+vfpv3xd-d16-fp16" +The single-precision VFPv3 floating-point instructions with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv3\-d16\-fp16\fR" 4 +.IX Item "+vfpv3-d16-fp16" +The VFPv3 floating-point instructions with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point extension. +.IP "\fB+idiv\fR" 4 +.IX Item "+idiv" +The ARM-state integer division instructions. +.IP "\fB+noidiv\fR" 4 +.IX Item "+noidiv" +Disable the ARM-state integer division extension. +.RE +.RS 4 +.RE +.IP "\fBarmv7e\-m\fR" 4 +.IX Item "armv7e-m" +.RS 4 +.PD 0 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +.PD +The single-precision VFPv4 floating-point instructions. +.IP "\fB+fpv5\fR" 4 +.IX Item "+fpv5" +The single-precision FPv5 floating-point instructions. +.IP "\fB+fp.dp\fR" 4 +.IX Item "+fp.dp" +The single\- and double-precision FPv5 floating-point instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point extensions. +.RE +.RS 4 +.RE +.IP "\fBarmv8\-m.main\fR" 4 +.IX Item "armv8-m.main" +.RS 4 +.PD 0 +.IP "\fB+dsp\fR" 4 +.IX Item "+dsp" +.PD +The \s-1DSP\s0 instructions. +.IP "\fB+nodsp\fR" 4 +.IX Item "+nodsp" +Disable the \s-1DSP\s0 extension. +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The single-precision floating-point instructions. +.IP "\fB+fp.dp\fR" 4 +.IX Item "+fp.dp" +The single\- and double-precision floating-point instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point extension. +.RE +.RS 4 +.RE +.IP "\fBarmv8\-r\fR" 4 +.IX Item "armv8-r" +.RS 4 +.PD 0 +.IP "\fB+crc\fR" 4 +.IX Item "+crc" +.PD +The Cyclic Redundancy Check (\s-1CRC\s0) instructions. +.IP "\fB+fp.sp\fR" 4 +.IX Item "+fp.sp" +The single-precision FPv5 floating-point instructions. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.RE +.RS 4 +.RE +.RE +.RS 4 +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. +.RE +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR, \fBarm710t\fR, +\&\fBarm720t\fR, \fBarm740t\fR, \fBstrongarm\fR, \fBstrongarm110\fR, +\&\fBstrongarm1100\fR, 0\fBstrongarm1110\fR, \fBarm8\fR, \fBarm810\fR, +\&\fBarm9\fR, \fBarm9e\fR, \fBarm920\fR, \fBarm920t\fR, \fBarm922t\fR, +\&\fBarm946e\-s\fR, \fBarm966e\-s\fR, \fBarm968e\-s\fR, \fBarm926ej\-s\fR, +\&\fBarm940t\fR, \fBarm9tdmi\fR, \fBarm10tdmi\fR, \fBarm1020t\fR, +\&\fBarm1026ej\-s\fR, \fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR, +\&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR, +\&\fBarm1156t2\-s\fR, \fBarm1156t2f\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, +\&\fBgeneric\-armv7\-a\fR, \fBcortex\-a5\fR, \fBcortex\-a7\fR, \fBcortex\-a8\fR, +\&\fBcortex\-a9\fR, \fBcortex\-a12\fR, \fBcortex\-a15\fR, \fBcortex\-a17\fR, +\&\fBcortex\-a32\fR, \fBcortex\-a35\fR, \fBcortex\-a53\fR, \fBcortex\-a55\fR, +\&\fBcortex\-a57\fR, \fBcortex\-a72\fR, \fBcortex\-a73\fR, \fBcortex\-a75\fR, +\&\fBcortex\-a76\fR, \fBares\fR, \fBcortex\-r4\fR, \fBcortex\-r4f\fR, +\&\fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-r8\fR, \fBcortex\-r52\fR, +\&\fBcortex\-m0\fR, \fBcortex\-m0plus\fR, \fBcortex\-m1\fR, \fBcortex\-m3\fR, +\&\fBcortex\-m4\fR, \fBcortex\-m7\fR, \fBcortex\-m23\fR, \fBcortex\-m33\fR, +\&\fBcortex\-m1.small\-multiply\fR, \fBcortex\-m0.small\-multiply\fR, +\&\fBcortex\-m0plus.small\-multiply\fR, \fBexynos\-m1\fR, \fBmarvell\-pj4\fR, +\&\fBneoverse\-n1\fR, \fBneoverse\-n2\fR, \fBneoverse\-v1\fR, \fBxscale\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR, \fBfa526\fR, \fBfa626\fR, +\&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR, \fBxgene1\fR. +.Sp +Additionally, this option can specify that \s-1GCC\s0 should tune the performance +of the code for a big.LITTLE system. Permissible names are: +\&\fBcortex\-a15.cortex\-a7\fR, \fBcortex\-a17.cortex\-a7\fR, +\&\fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a72.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR, +\&\fBcortex\-a75.cortex\-a55\fR, \fBcortex\-a76.cortex\-a55\fR. +.Sp +\&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the +performance for a blend of processors within architecture \fIarch\fR. +The aim is to generate code that run well on the current most popular +processors, balancing between optimizations that benefit some CPUs in the +range, and avoiding performance pitfalls of other CPUs. The effects of +this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come and go. +.Sp +\&\fB\-mtune\fR permits the same extension options as \fB\-mcpu\fR, but +the extension options do not affect the tuning of the generated code. +.Sp +\&\fB\-mtune=native\fR causes the compiler to auto-detect the \s-1CPU\s0 +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mcpu=\fR\fIname\fR[\fB+extension...\fR]" 4 +.IX Item "-mcpu=name[+extension...]" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. +.Sp +Many of the supported CPUs implement optional architectural +extensions. Where this is so the architectural extensions are +normally enabled by default. If implementations that lack the +extension exist, then the extension syntax can be used to disable +those extensions that have been omitted. For floating-point and +Advanced \s-1SIMD\s0 (Neon) instructions, the settings of the options +\&\fB\-mfloat\-abi\fR and \fB\-mfpu\fR must also be considered: +floating-point and Advanced \s-1SIMD\s0 instructions will only be used if +\&\fB\-mfloat\-abi\fR is not set to \fBsoft\fR; and any setting of +\&\fB\-mfpu\fR other than \fBauto\fR will override the available +floating-point and \s-1SIMD\s0 extension instructions. +.Sp +For example, \fBcortex\-a9\fR can be found in three major +configurations: integer only, with just a floating-point unit or with +floating-point and Advanced \s-1SIMD.\s0 The default is to enable all the +instructions, but the extensions \fB+nosimd\fR and \fB+nofp\fR can +be used to disable just the \s-1SIMD\s0 or both the \s-1SIMD\s0 and floating-point +instructions respectively. +.Sp +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +The following extension options are common to the listed CPUs: +.RS 4 +.IP "\fB+nodsp\fR" 4 +.IX Item "+nodsp" +Disable the \s-1DSP\s0 instructions on \fBcortex\-m33\fR. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disables the floating-point instructions on \fBarm9e\fR, +\&\fBarm946e\-s\fR, \fBarm966e\-s\fR, \fBarm968e\-s\fR, \fBarm10e\fR, +\&\fBarm1020e\fR, \fBarm1022e\fR, \fBarm926ej\-s\fR, +\&\fBarm1026ej\-s\fR, \fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-r8\fR, +\&\fBcortex\-m4\fR, \fBcortex\-m7\fR and \fBcortex\-m33\fR. +Disables the floating-point and \s-1SIMD\s0 instructions on +\&\fBgeneric\-armv7\-a\fR, \fBcortex\-a5\fR, \fBcortex\-a7\fR, +\&\fBcortex\-a8\fR, \fBcortex\-a9\fR, \fBcortex\-a12\fR, +\&\fBcortex\-a15\fR, \fBcortex\-a17\fR, \fBcortex\-a15.cortex\-a7\fR, +\&\fBcortex\-a17.cortex\-a7\fR, \fBcortex\-a32\fR, \fBcortex\-a35\fR, +\&\fBcortex\-a53\fR and \fBcortex\-a55\fR. +.IP "\fB+nofp.dp\fR" 4 +.IX Item "+nofp.dp" +Disables the double-precision component of the floating-point instructions +on \fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-r8\fR, \fBcortex\-r52\fR and +\&\fBcortex\-m7\fR. +.IP "\fB+nosimd\fR" 4 +.IX Item "+nosimd" +Disables the \s-1SIMD\s0 (but not floating-point) instructions on +\&\fBgeneric\-armv7\-a\fR, \fBcortex\-a5\fR, \fBcortex\-a7\fR +and \fBcortex\-a9\fR. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +Enables the cryptographic instructions on \fBcortex\-a32\fR, +\&\fBcortex\-a35\fR, \fBcortex\-a53\fR, \fBcortex\-a55\fR, \fBcortex\-a57\fR, +\&\fBcortex\-a72\fR, \fBcortex\-a73\fR, \fBcortex\-a75\fR, \fBexynos\-m1\fR, +\&\fBxgene1\fR, \fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a73.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR and +\&\fBcortex\-a75.cortex\-a55\fR. +.RE +.RS 4 +.Sp +Additionally the \fBgeneric\-armv7\-a\fR pseudo target defaults to +VFPv3 with 16 double-precision registers. It supports the following +extension options: \fBmp\fR, \fBsec\fR, \fBvfpv3\-d16\fR, +\&\fBvfpv3\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3\-fp16\fR, +\&\fBvfpv4\-d16\fR, \fBvfpv4\fR, \fBneon\fR, \fBneon\-vfpv3\fR, +\&\fBneon\-fp16\fR, \fBneon\-vfpv4\fR. The meanings are the same as for +the extensions to \fB\-march=armv7\-a\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. +.RE +.IP "\fB\-mfpu=\fR\fIname\fR" 4 +.IX Item "-mfpu=name" +This specifies what floating-point hardware (or hardware emulation) is +available on the target. Permissible names are: \fBauto\fR, \fBvfpv2\fR, +\&\fBvfpv3\fR, +\&\fBvfpv3\-fp16\fR, \fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR, +\&\fBvfpv3xd\-fp16\fR, \fBneon\-vfpv3\fR, \fBneon\-fp16\fR, \fBvfpv4\fR, +\&\fBvfpv4\-d16\fR, \fBfpv4\-sp\-d16\fR, \fBneon\-vfpv4\fR, +\&\fBfpv5\-d16\fR, \fBfpv5\-sp\-d16\fR, +\&\fBfp\-armv8\fR, \fBneon\-fp\-armv8\fR and \fBcrypto\-neon\-fp\-armv8\fR. +Note that \fBneon\fR is an alias for \fBneon\-vfpv3\fR and \fBvfp\fR +is an alias for \fBvfpv2\fR. +.Sp +The setting \fBauto\fR is the default and is special. It causes the +compiler to select the floating-point and Advanced \s-1SIMD\s0 instructions +based on the settings of \fB\-mcpu\fR and \fB\-march\fR. +.Sp +If the selected floating-point hardware includes the \s-1NEON\s0 extension +(e.g. \fB\-mfpu=neon\fR), note that floating-point +operations are not generated by \s-1GCC\s0's auto-vectorization pass unless +\&\fB\-funsafe\-math\-optimizations\fR is also specified. This is +because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE 754\s0 standard for +floating-point arithmetic (in particular denormal values are treated as +zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. +.Sp +You can also set the fpu name at function level by using the \f(CW\*(C`target("fpu=")\*(C'\fR function attributes or pragmas. +.IP "\fB\-mfp16\-format=\fR\fIname\fR" 4 +.IX Item "-mfp16-format=name" +Specify the format of the \f(CW\*(C`_\|_fp16\*(C'\fR half-precision floating-point type. +Permissible names are \fBnone\fR, \fBieee\fR, and \fBalternative\fR; +the default is \fBnone\fR, in which case the \f(CW\*(C`_\|_fp16\*(C'\fR type is not +defined. +.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4 +.IX Item "-mstructure-size-boundary=n" +The sizes of all structures and unions are rounded up to a multiple +of the number of bits set by this option. Permissible values are 8, 32 +and 64. The default value varies for different toolchains. For the \s-1COFF\s0 +targeted toolchain the default value is 8. A value of 64 is only allowed +if the underlying \s-1ABI\s0 supports it. +.Sp +Specifying a larger number can produce faster, more efficient code, but +can also increase the size of the program. Different values are potentially +incompatible. Code compiled with one value cannot necessarily expect to +work with code or libraries compiled with another value, if they exchange +information using structures or unions. +.Sp +This option is deprecated. +.IP "\fB\-mabort\-on\-noreturn\fR" 4 +.IX Item "-mabort-on-noreturn" +Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a +\&\f(CW\*(C`noreturn\*(C'\fR function. It is executed if the function tries to +return. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +lies outside of the 64\-megabyte addressing range of the offset-based +version of subroutine call instruction. +.Sp +Even if this switch is enabled, not all function calls are turned +into long calls. The heuristic is that static functions, functions +that have the \f(CW\*(C`short_call\*(C'\fR attribute, functions that are inside +the scope of a \f(CW\*(C`#pragma no_long_calls\*(C'\fR directive, and functions whose +definitions have already been compiled within the current compilation +unit are not turned into long calls. The exceptions to this rule are +that weak function definitions, functions with the \f(CW\*(C`long_call\*(C'\fR +attribute or the \f(CW\*(C`section\*(C'\fR attribute, and functions that are within +the scope of a \f(CW\*(C`#pragma long_calls\*(C'\fR directive are always +turned into long calls. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR restores the default behavior, as does +placing the function calls within the scope of a \f(CW\*(C`#pragma +long_calls_off\*(C'\fR directive. Note these switches have no effect on how +the compiler generates code to handle function calls via function +pointers. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The runtime system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 +.IX Item "-mpic-register=reg" +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default is any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. +.IP "\fB\-mpic\-data\-is\-text\-relative\fR" 4 +.IX Item "-mpic-data-is-text-relative" +Assume that the displacement between the text and data segments is fixed +at static link time. This permits using PC-relative addressing +operations to access data known to be in the data segment. For +non-VxWorks \s-1RTP\s0 targets, this option is enabled by default. When +disabled on such targets, it will enable \fB\-msingle\-pic\-base\fR by +default. +.IP "\fB\-mpoke\-function\-name\fR" 4 +.IX Item "-mpoke-function-name" +Write the name of each function into the text section, directly +preceding the function prologue. The generated code is similar to this: +.Sp +.Vb 9 +\& t0 +\& .ascii "arm_poke_function_name", 0 +\& .align +\& t1 +\& .word 0xff000000 + (t1 \- t0) +\& arm_poke_function_name +\& mov ip, sp +\& stmfd sp!, {fp, ip, lr, pc} +\& sub fp, ip, #4 +.Ve +.Sp +When performing a stack backtrace, code can inspect the value of +\&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR. If the trace function then looks at +location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that +there is a function name embedded immediately preceding this location +and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR. +.IP "\fB\-mthumb\fR" 4 +.IX Item "-mthumb" +.PD 0 +.IP "\fB\-marm\fR" 4 +.IX Item "-marm" +.PD +Select between generating code that executes in \s-1ARM\s0 and Thumb +states. The default for most configurations is to generate code +that executes in \s-1ARM\s0 state, but the default can be changed by +configuring \s-1GCC\s0 with the \fB\-\-with\-mode=\fR\fIstate\fR +configure option. +.Sp +You can also override the \s-1ARM\s0 and Thumb mode for each function +by using the \f(CW\*(C`target("thumb")\*(C'\fR and \f(CW\*(C`target("arm")\*(C'\fR function attributes or pragmas. +.IP "\fB\-mflip\-thumb\fR" 4 +.IX Item "-mflip-thumb" +Switch ARM/Thumb modes on alternating functions. +This option is provided for regression testing of mixed Thumb/ARM code +generation, and is not intended for ordinary use in compiling code. +.IP "\fB\-mtpcs\-frame\fR" 4 +.IX Item "-mtpcs-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all non-leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-tpcs\-frame\fR. +.IP "\fB\-mtpcs\-leaf\-frame\fR" 4 +.IX Item "-mtpcs-leaf-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-apcs\-leaf\-frame\fR. +.IP "\fB\-mcallee\-super\-interworking\fR" 4 +.IX Item "-mcallee-super-interworking" +Gives all externally visible functions in the file being compiled an \s-1ARM\s0 +instruction set header which switches to Thumb mode before executing the +rest of the function. This allows these functions to be called from +non-interworking code. This option is not valid in \s-1AAPCS\s0 configurations +because interworking is enabled by default. +.IP "\fB\-mcaller\-super\-interworking\fR" 4 +.IX Item "-mcaller-super-interworking" +Allows calls via function pointers (including virtual functions) to +execute correctly regardless of whether the target code has been +compiled for interworking or not. There is a small overhead in the cost +of executing a function pointer if this option is enabled. This option +is not valid in \s-1AAPCS\s0 configurations because interworking is enabled +by default. +.IP "\fB\-mtp=\fR\fIname\fR" 4 +.IX Item "-mtp=name" +Specify the access model for the thread local storage pointer. The valid +models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR, +\&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly +(supported in the arm6k architecture), and \fBauto\fR, which uses the +best available method for the selected processor. The default setting is +\&\fBauto\fR. +.IP "\fB\-mtls\-dialect=\fR\fIdialect\fR" 4 +.IX Item "-mtls-dialect=dialect" +Specify the dialect to use for accessing thread local storage. Two +\&\fIdialect\fRs are supported\-\-\-\fBgnu\fR and \fBgnu2\fR. The +\&\fBgnu\fR dialect selects the original \s-1GNU\s0 scheme for supporting +local and global dynamic \s-1TLS\s0 models. The \fBgnu2\fR dialect +selects the \s-1GNU\s0 descriptor scheme, which provides better performance +for shared libraries. The \s-1GNU\s0 descriptor scheme is compatible with +the original scheme, but does require new assembler, linker and +library support. Initial and local exec \s-1TLS\s0 models are unaffected by +this option and always use the original scheme. +.IP "\fB\-mword\-relocations\fR" 4 +.IX Item "-mword-relocations" +Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). +This is enabled by default on targets (uClinux, SymbianOS) where the runtime +loader imposes this restriction, and when \fB\-fpic\fR or \fB\-fPIC\fR +is specified. This option conflicts with \fB\-mslow\-flash\-data\fR. +.IP "\fB\-mfix\-cortex\-m3\-ldrd\fR" 4 +.IX Item "-mfix-cortex-m3-ldrd" +Some Cortex\-M3 cores can cause data corruption when \f(CW\*(C`ldrd\*(C'\fR instructions +with overlapping destination and base registers are used. This option avoids +generating these instructions. This option is enabled by default when +\&\fB\-mcpu=cortex\-m3\fR is specified. +.IP "\fB\-munaligned\-access\fR" 4 +.IX Item "-munaligned-access" +.PD 0 +.IP "\fB\-mno\-unaligned\-access\fR" 4 +.IX Item "-mno-unaligned-access" +.PD +Enables (or disables) reading and writing of 16\- and 32\- bit values +from addresses that are not 16\- or 32\- bit aligned. By default +unaligned access is disabled for all pre\-ARMv6, all ARMv6\-M and for +ARMv8\-M Baseline architectures, and enabled for all other +architectures. If unaligned access is not enabled then words in packed +data structures are accessed a byte at a time. +.Sp +The \s-1ARM\s0 attribute \f(CW\*(C`Tag_CPU_unaligned_access\*(C'\fR is set in the +generated object file to either true or false, depending upon the +setting of this option. If unaligned access is enabled then the +preprocessor symbol \f(CW\*(C`_\|_ARM_FEATURE_UNALIGNED\*(C'\fR is also +defined. +.IP "\fB\-mneon\-for\-64bits\fR" 4 +.IX Item "-mneon-for-64bits" +Enables using Neon to handle scalar 64\-bits operations. This is +disabled by default since the cost of moving data from core registers +to Neon is high. +.IP "\fB\-mslow\-flash\-data\fR" 4 +.IX Item "-mslow-flash-data" +Assume loading data from flash is slower than fetching instruction. +Therefore literal load is minimized for better performance. +This option is only supported when compiling for ARMv7 M\-profile and +off by default. It conflicts with \fB\-mword\-relocations\fR. +.IP "\fB\-masm\-syntax\-unified\fR" 4 +.IX Item "-masm-syntax-unified" +Assume inline assembler is using unified asm syntax. The default is +currently off which implies divided syntax. This option has no impact +on Thumb2. However, this may change in future releases of \s-1GCC.\s0 +Divided syntax should be considered deprecated. +.IP "\fB\-mrestrict\-it\fR" 4 +.IX Item "-mrestrict-it" +Restricts generation of \s-1IT\s0 blocks to conform to the rules of ARMv8\-A. +\&\s-1IT\s0 blocks can only contain a single 16\-bit instruction from a select +set of instructions. This option is on by default for ARMv8\-A Thumb mode. +.IP "\fB\-mprint\-tune\-info\fR" 4 +.IX Item "-mprint-tune-info" +Print \s-1CPU\s0 tuning information as comment in assembler file. This is +an option used only for regression testing of the compiler and not +intended for ordinary use in compiling code. This option is disabled +by default. +.IP "\fB\-mverbose\-cost\-dump\fR" 4 +.IX Item "-mverbose-cost-dump" +Enable verbose cost model dumping in the debug dump files. This option is +provided for use in debugging the compiler. +.IP "\fB\-mpure\-code\fR" 4 +.IX Item "-mpure-code" +Do not allow constant data to be placed in code sections. +Additionally, when compiling for \s-1ELF\s0 object format give all text sections the +\&\s-1ELF\s0 processor-specific section attribute \f(CW\*(C`SHF_ARM_PURECODE\*(C'\fR. This option +is only available when generating non-pic code for M\-profile targets. +.IP "\fB\-mcmse\fR" 4 +.IX Item "-mcmse" +Generate secure code as per the \*(L"ARMv8\-M Security Extensions: Requirements on +Development Tools Engineering Specification\*(R", which can be found on +<\fBhttps://developer.arm.com/documentation/ecm0359818/latest/\fR>. +.PP +\fI\s-1AVR\s0 Options\fR +.IX Subsection "AVR Options" +.PP +These options are defined for \s-1AVR\s0 implementations: +.IP "\fB\-mmcu=\fR\fImcu\fR" 4 +.IX Item "-mmcu=mcu" +Specify Atmel \s-1AVR\s0 instruction set architectures (\s-1ISA\s0) or \s-1MCU\s0 type. +.Sp +The default for this option is \fBavr2\fR. +.Sp +\&\s-1GCC\s0 supports the following \s-1AVR\s0 devices and ISAs: +.RS 4 +.ie n .IP """avr2""" 4 +.el .IP "\f(CWavr2\fR" 4 +.IX Item "avr2" +\&\*(L"Classic\*(R" devices with up to 8 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`attiny22\*(C'\fR, \f(CW\*(C`attiny26\*(C'\fR, \f(CW\*(C`at90s2313\*(C'\fR, \f(CW\*(C`at90s2323\*(C'\fR, \f(CW\*(C`at90s2333\*(C'\fR, \f(CW\*(C`at90s2343\*(C'\fR, \f(CW\*(C`at90s4414\*(C'\fR, \f(CW\*(C`at90s4433\*(C'\fR, \f(CW\*(C`at90s4434\*(C'\fR, \f(CW\*(C`at90c8534\*(C'\fR, \f(CW\*(C`at90s8515\*(C'\fR, \f(CW\*(C`at90s8535\*(C'\fR. +.ie n .IP """avr25""" 4 +.el .IP "\f(CWavr25\fR" 4 +.IX Item "avr25" +\&\*(L"Classic\*(R" devices with up to 8 KiB of program memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction. +\&\fImcu\fR = \f(CW\*(C`attiny13\*(C'\fR, \f(CW\*(C`attiny13a\*(C'\fR, \f(CW\*(C`attiny24\*(C'\fR, \f(CW\*(C`attiny24a\*(C'\fR, \f(CW\*(C`attiny25\*(C'\fR, \f(CW\*(C`attiny261\*(C'\fR, \f(CW\*(C`attiny261a\*(C'\fR, \f(CW\*(C`attiny2313\*(C'\fR, \f(CW\*(C`attiny2313a\*(C'\fR, \f(CW\*(C`attiny43u\*(C'\fR, \f(CW\*(C`attiny44\*(C'\fR, \f(CW\*(C`attiny44a\*(C'\fR, \f(CW\*(C`attiny45\*(C'\fR, \f(CW\*(C`attiny48\*(C'\fR, \f(CW\*(C`attiny441\*(C'\fR, \f(CW\*(C`attiny461\*(C'\fR, \f(CW\*(C`attiny461a\*(C'\fR, \f(CW\*(C`attiny4313\*(C'\fR, \f(CW\*(C`attiny84\*(C'\fR, \f(CW\*(C`attiny84a\*(C'\fR, \f(CW\*(C`attiny85\*(C'\fR, \f(CW\*(C`attiny87\*(C'\fR, \f(CW\*(C`attiny88\*(C'\fR, \f(CW\*(C`attiny828\*(C'\fR, \f(CW\*(C`attiny841\*(C'\fR, \f(CW\*(C`attiny861\*(C'\fR, \f(CW\*(C`attiny861a\*(C'\fR, \f(CW\*(C`ata5272\*(C'\fR, \f(CW\*(C`ata6616c\*(C'\fR, \f(CW\*(C`at86rf401\*(C'\fR. +.ie n .IP """avr3""" 4 +.el .IP "\f(CWavr3\fR" 4 +.IX Item "avr3" +\&\*(L"Classic\*(R" devices with 16 KiB up to 64 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`at76c711\*(C'\fR, \f(CW\*(C`at43usb355\*(C'\fR. +.ie n .IP """avr31""" 4 +.el .IP "\f(CWavr31\fR" 4 +.IX Item "avr31" +\&\*(L"Classic\*(R" devices with 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega103\*(C'\fR, \f(CW\*(C`at43usb320\*(C'\fR. +.ie n .IP """avr35""" 4 +.el .IP "\f(CWavr35\fR" 4 +.IX Item "avr35" +\&\*(L"Classic\*(R" devices with 16 KiB up to 64 KiB of program memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction. +\&\fImcu\fR = \f(CW\*(C`attiny167\*(C'\fR, \f(CW\*(C`attiny1634\*(C'\fR, \f(CW\*(C`atmega8u2\*(C'\fR, \f(CW\*(C`atmega16u2\*(C'\fR, \f(CW\*(C`atmega32u2\*(C'\fR, \f(CW\*(C`ata5505\*(C'\fR, \f(CW\*(C`ata6617c\*(C'\fR, \f(CW\*(C`ata664251\*(C'\fR, \f(CW\*(C`at90usb82\*(C'\fR, \f(CW\*(C`at90usb162\*(C'\fR. +.ie n .IP """avr4""" 4 +.el .IP "\f(CWavr4\fR" 4 +.IX Item "avr4" +\&\*(L"Enhanced\*(R" devices with up to 8 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega48\*(C'\fR, \f(CW\*(C`atmega48a\*(C'\fR, \f(CW\*(C`atmega48p\*(C'\fR, \f(CW\*(C`atmega48pa\*(C'\fR, \f(CW\*(C`atmega48pb\*(C'\fR, \f(CW\*(C`atmega8\*(C'\fR, \f(CW\*(C`atmega8a\*(C'\fR, \f(CW\*(C`atmega8hva\*(C'\fR, \f(CW\*(C`atmega88\*(C'\fR, \f(CW\*(C`atmega88a\*(C'\fR, \f(CW\*(C`atmega88p\*(C'\fR, \f(CW\*(C`atmega88pa\*(C'\fR, \f(CW\*(C`atmega88pb\*(C'\fR, \f(CW\*(C`atmega8515\*(C'\fR, \f(CW\*(C`atmega8535\*(C'\fR, \f(CW\*(C`ata6285\*(C'\fR, \f(CW\*(C`ata6286\*(C'\fR, \f(CW\*(C`ata6289\*(C'\fR, \f(CW\*(C`ata6612c\*(C'\fR, \f(CW\*(C`at90pwm1\*(C'\fR, \f(CW\*(C`at90pwm2\*(C'\fR, \f(CW\*(C`at90pwm2b\*(C'\fR, \f(CW\*(C`at90pwm3\*(C'\fR, \f(CW\*(C`at90pwm3b\*(C'\fR, \f(CW\*(C`at90pwm81\*(C'\fR. +.ie n .IP """avr5""" 4 +.el .IP "\f(CWavr5\fR" 4 +.IX Item "avr5" +\&\*(L"Enhanced\*(R" devices with 16 KiB up to 64 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega168pb\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega325pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega328pb\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64hve2\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega644rfr2\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5791\*(C'\fR, \f(CW\*(C`ata6613c\*(C'\fR, \f(CW\*(C`ata6614q\*(C'\fR, \f(CW\*(C`ata5782\*(C'\fR, \f(CW\*(C`ata5831\*(C'\fR, \f(CW\*(C`ata8210\*(C'\fR, \f(CW\*(C`ata8510\*(C'\fR, \f(CW\*(C`ata5702m322\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +.ie n .IP """avr51""" 4 +.el .IP "\f(CWavr51\fR" 4 +.IX Item "avr51" +\&\*(L"Enhanced\*(R" devices with 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega128\*(C'\fR, \f(CW\*(C`atmega128a\*(C'\fR, \f(CW\*(C`atmega128rfa1\*(C'\fR, \f(CW\*(C`atmega128rfr2\*(C'\fR, \f(CW\*(C`atmega1280\*(C'\fR, \f(CW\*(C`atmega1281\*(C'\fR, \f(CW\*(C`atmega1284\*(C'\fR, \f(CW\*(C`atmega1284p\*(C'\fR, \f(CW\*(C`atmega1284rfr2\*(C'\fR, \f(CW\*(C`at90can128\*(C'\fR, \f(CW\*(C`at90usb1286\*(C'\fR, \f(CW\*(C`at90usb1287\*(C'\fR. +.ie n .IP """avr6""" 4 +.el .IP "\f(CWavr6\fR" 4 +.IX Item "avr6" +\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC,\s0 i.e. with more than 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega256rfr2\*(C'\fR, \f(CW\*(C`atmega2560\*(C'\fR, \f(CW\*(C`atmega2561\*(C'\fR, \f(CW\*(C`atmega2564rfr2\*(C'\fR. +.ie n .IP """avrxmega2""" 4 +.el .IP "\f(CWavrxmega2\fR" 4 +.IX Item "avrxmega2" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 8 KiB and up to 64 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atxmega8e5\*(C'\fR, \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16a4u\*(C'\fR, \f(CW\*(C`atxmega16c4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR, \f(CW\*(C`atxmega16e5\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32a4u\*(C'\fR, \f(CW\*(C`atxmega32c3\*(C'\fR, \f(CW\*(C`atxmega32c4\*(C'\fR, \f(CW\*(C`atxmega32d3\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR, \f(CW\*(C`atxmega32e5\*(C'\fR. +.ie n .IP """avrxmega3""" 4 +.el .IP "\f(CWavrxmega3\fR" 4 +.IX Item "avrxmega3" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with up to 64 KiB of combined program memory and \s-1RAM,\s0 and with program memory visible in the \s-1RAM\s0 address space. +\&\fImcu\fR = \f(CW\*(C`attiny202\*(C'\fR, \f(CW\*(C`attiny204\*(C'\fR, \f(CW\*(C`attiny212\*(C'\fR, \f(CW\*(C`attiny214\*(C'\fR, \f(CW\*(C`attiny402\*(C'\fR, \f(CW\*(C`attiny404\*(C'\fR, \f(CW\*(C`attiny406\*(C'\fR, \f(CW\*(C`attiny412\*(C'\fR, \f(CW\*(C`attiny414\*(C'\fR, \f(CW\*(C`attiny416\*(C'\fR, \f(CW\*(C`attiny417\*(C'\fR, \f(CW\*(C`attiny804\*(C'\fR, \f(CW\*(C`attiny806\*(C'\fR, \f(CW\*(C`attiny807\*(C'\fR, \f(CW\*(C`attiny814\*(C'\fR, \f(CW\*(C`attiny816\*(C'\fR, \f(CW\*(C`attiny817\*(C'\fR, \f(CW\*(C`attiny1604\*(C'\fR, \f(CW\*(C`attiny1606\*(C'\fR, \f(CW\*(C`attiny1607\*(C'\fR, \f(CW\*(C`attiny1614\*(C'\fR, \f(CW\*(C`attiny1616\*(C'\fR, \f(CW\*(C`attiny1617\*(C'\fR, \f(CW\*(C`attiny3214\*(C'\fR, \f(CW\*(C`attiny3216\*(C'\fR, \f(CW\*(C`attiny3217\*(C'\fR, \f(CW\*(C`atmega808\*(C'\fR, \f(CW\*(C`atmega809\*(C'\fR, \f(CW\*(C`atmega1608\*(C'\fR, \f(CW\*(C`atmega1609\*(C'\fR, \f(CW\*(C`atmega3208\*(C'\fR, \f(CW\*(C`atmega3209\*(C'\fR, \f(CW\*(C`atmega4808\*(C'\fR, \f(CW\*(C`atmega4809\*(C'\fR. +.ie n .IP """avrxmega4""" 4 +.el .IP "\f(CWavrxmega4\fR" 4 +.IX Item "avrxmega4" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64 KiB and up to 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64a3u\*(C'\fR, \f(CW\*(C`atxmega64a4u\*(C'\fR, \f(CW\*(C`atxmega64b1\*(C'\fR, \f(CW\*(C`atxmega64b3\*(C'\fR, \f(CW\*(C`atxmega64c3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR, \f(CW\*(C`atxmega64d4\*(C'\fR. +.ie n .IP """avrxmega5""" 4 +.el .IP "\f(CWavrxmega5\fR" 4 +.IX Item "avrxmega5" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of \s-1RAM.\s0 +\&\fImcu\fR = \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. +.ie n .IP """avrxmega6""" 4 +.el .IP "\f(CWavrxmega6\fR" 4 +.IX Item "avrxmega6" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128a3u\*(C'\fR, \f(CW\*(C`atxmega128b1\*(C'\fR, \f(CW\*(C`atxmega128b3\*(C'\fR, \f(CW\*(C`atxmega128c3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR, \f(CW\*(C`atxmega128d4\*(C'\fR, \f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192a3u\*(C'\fR, \f(CW\*(C`atxmega192c3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR, \f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256a3u\*(C'\fR, \f(CW\*(C`atxmega256c3\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR, \f(CW\*(C`atxmega384c3\*(C'\fR, \f(CW\*(C`atxmega384d3\*(C'\fR. +.ie n .IP """avrxmega7""" 4 +.el .IP "\f(CWavrxmega7\fR" 4 +.IX Item "avrxmega7" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128 KiB of program memory and more than 64 KiB of \s-1RAM.\s0 +\&\fImcu\fR = \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. +.ie n .IP """avrtiny""" 4 +.el .IP "\f(CWavrtiny\fR" 4 +.IX Item "avrtiny" +\&\*(L"\s-1TINY\*(R"\s0 Tiny core devices with 512 B up to 4 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`attiny4\*(C'\fR, \f(CW\*(C`attiny5\*(C'\fR, \f(CW\*(C`attiny9\*(C'\fR, \f(CW\*(C`attiny10\*(C'\fR, \f(CW\*(C`attiny20\*(C'\fR, \f(CW\*(C`attiny40\*(C'\fR. +.ie n .IP """avr1""" 4 +.el .IP "\f(CWavr1\fR" 4 +.IX Item "avr1" +This \s-1ISA\s0 is implemented by the minimal \s-1AVR\s0 core and supported for assembler only. +\&\fImcu\fR = \f(CW\*(C`attiny11\*(C'\fR, \f(CW\*(C`attiny12\*(C'\fR, \f(CW\*(C`attiny15\*(C'\fR, \f(CW\*(C`attiny28\*(C'\fR, \f(CW\*(C`at90s1200\*(C'\fR. +.RE +.RS 4 +.RE +.IP "\fB\-mabsdata\fR" 4 +.IX Item "-mabsdata" +Assume that all data in static storage can be accessed by \s-1LDS / STS\s0 +instructions. This option has only an effect on reduced Tiny devices like +ATtiny40. See also the \f(CW\*(C`absdata\*(C'\fR +\&\fB\s-1AVR\s0 Variable Attributes,variable attribute\fR. +.IP "\fB\-maccumulate\-args\fR" 4 +.IX Item "-maccumulate-args" +Accumulate outgoing function arguments and acquire/release the needed +stack space for outgoing function arguments once in function +prologue/epilogue. Without this option, outgoing arguments are pushed +before calling a function and popped afterwards. +.Sp +Popping the arguments after the function call can be expensive on +\&\s-1AVR\s0 so that accumulating the stack space might lead to smaller +executables because arguments need not be removed from the +stack after such a function call. +.Sp +This option can lead to reduced code size for functions that perform +several calls to functions that get their arguments on the stack like +calls to printf-like functions. +.IP "\fB\-mbranch\-cost=\fR\fIcost\fR" 4 +.IX Item "-mbranch-cost=cost" +Set the branch costs for conditional branch instructions to +\&\fIcost\fR. Reasonable values for \fIcost\fR are small, non-negative +integers. The default branch cost is 0. +.IP "\fB\-mcall\-prologues\fR" 4 +.IX Item "-mcall-prologues" +Functions prologues/epilogues are expanded as calls to appropriate +subroutines. Code size is smaller. +.IP "\fB\-mgas\-isr\-prologues\fR" 4 +.IX Item "-mgas-isr-prologues" +Interrupt service routines (ISRs) may use the \f(CW\*(C`_\|_gcc_isr\*(C'\fR pseudo +instruction supported by \s-1GNU\s0 Binutils. +If this option is on, the feature can still be disabled for individual +ISRs by means of the \fB\s-1AVR\s0 Function Attributes,,\f(CB\*(C`no_gccisr\*(C'\fB\fR +function attribute. This feature is activated per default +if optimization is on (but not with \fB\-Og\fR, \f(CW@pxref\fR{Optimize Options}), +and if \s-1GNU\s0 Binutils support \s-1PR21683\s0 (\f(CW\*(C`https://sourceware.org/PR21683\*(C'\fR). +.IP "\fB\-mint8\fR" 4 +.IX Item "-mint8" +Assume \f(CW\*(C`int\*(C'\fR to be 8\-bit integer. This affects the sizes of all types: a +\&\f(CW\*(C`char\*(C'\fR is 1 byte, an \f(CW\*(C`int\*(C'\fR is 1 byte, a \f(CW\*(C`long\*(C'\fR is 2 bytes, +and \f(CW\*(C`long long\*(C'\fR is 4 bytes. Please note that this option does not +conform to the C standards, but it results in smaller code +size. +.IP "\fB\-mmain\-is\-OS_task\fR" 4 +.IX Item "-mmain-is-OS_task" +Do not save registers in \f(CW\*(C`main\*(C'\fR. The effect is the same like +attaching attribute \fB\s-1AVR\s0 Function Attributes,,\f(CB\*(C`OS_task\*(C'\fB\fR +to \f(CW\*(C`main\*(C'\fR. It is activated per default if optimization is on. +.IP "\fB\-mn\-flash=\fR\fInum\fR" 4 +.IX Item "-mn-flash=num" +Assume that the flash memory has a size of +\&\fInum\fR times 64 KiB. +.IP "\fB\-mno\-interrupts\fR" 4 +.IX Item "-mno-interrupts" +Generated code is not compatible with hardware interrupts. +Code size is smaller. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Try to replace \f(CW\*(C`CALL\*(C'\fR resp. \f(CW\*(C`JMP\*(C'\fR instruction by the shorter +\&\f(CW\*(C`RCALL\*(C'\fR resp. \f(CW\*(C`RJMP\*(C'\fR instruction if applicable. +Setting \fB\-mrelax\fR just adds the \fB\-\-mlink\-relax\fR option to +the assembler's command line and the \fB\-\-relax\fR option to the +linker's command line. +.Sp +Jump relaxing is performed by the linker because jump offsets are not +known before code is located. Therefore, the assembler code generated by the +compiler is the same, but the instructions in the executable may +differ from instructions in the assembler code. +.Sp +Relaxing must be turned on if linker stubs are needed, see the +section on \f(CW\*(C`EIND\*(C'\fR and linker stubs below. +.IP "\fB\-mrmw\fR" 4 +.IX Item "-mrmw" +Assume that the device supports the Read-Modify-Write +instructions \f(CW\*(C`XCH\*(C'\fR, \f(CW\*(C`LAC\*(C'\fR, \f(CW\*(C`LAS\*(C'\fR and \f(CW\*(C`LAT\*(C'\fR. +.IP "\fB\-mshort\-calls\fR" 4 +.IX Item "-mshort-calls" +Assume that \f(CW\*(C`RJMP\*(C'\fR and \f(CW\*(C`RCALL\*(C'\fR can target the whole +program memory. +.Sp +This option is used internally for multilib selection. It is +not an optimization option, and you don't need to set it by hand. +.IP "\fB\-msp8\fR" 4 +.IX Item "-msp8" +Treat the stack pointer register as an 8\-bit register, +i.e. assume the high byte of the stack pointer is zero. +In general, you don't need to set this option by hand. +.Sp +This option is used internally by the compiler to select and +build multilibs for architectures \f(CW\*(C`avr2\*(C'\fR and \f(CW\*(C`avr25\*(C'\fR. +These architectures mix devices with and without \f(CW\*(C`SPH\*(C'\fR. +For any setting other than \fB\-mmcu=avr2\fR or \fB\-mmcu=avr25\fR +the compiler driver adds or removes this option from the compiler +proper's command line, because the compiler then knows if the device +or architecture has an 8\-bit stack pointer and thus no \f(CW\*(C`SPH\*(C'\fR +register or not. +.IP "\fB\-mstrict\-X\fR" 4 +.IX Item "-mstrict-X" +Use address register \f(CW\*(C`X\*(C'\fR in a way proposed by the hardware. This means +that \f(CW\*(C`X\*(C'\fR is only used in indirect, post-increment or +pre-decrement addressing. +.Sp +Without this option, the \f(CW\*(C`X\*(C'\fR register may be used in the same way +as \f(CW\*(C`Y\*(C'\fR or \f(CW\*(C`Z\*(C'\fR which then is emulated by additional +instructions. +For example, loading a value with \f(CW\*(C`X+const\*(C'\fR addressing with a +small non-negative \f(CW\*(C`const < 64\*(C'\fR to a register \fIRn\fR is +performed as +.Sp +.Vb 3 +\& adiw r26, const ; X += const +\& ld , X ; = *X +\& sbiw r26, const ; X \-= const +.Ve +.IP "\fB\-mtiny\-stack\fR" 4 +.IX Item "-mtiny-stack" +Only change the lower 8 bits of the stack pointer. +.IP "\fB\-mfract\-convert\-truncate\fR" 4 +.IX Item "-mfract-convert-truncate" +Allow to use truncation instead of rounding towards zero for fractional fixed-point types. +.IP "\fB\-nodevicelib\fR" 4 +.IX Item "-nodevicelib" +Don't link against AVR-LibC's device specific library \f(CW\*(C`lib.a\*(C'\fR. +.IP "\fB\-nodevicespecs\fR" 4 +.IX Item "-nodevicespecs" +Don't add \fB\-specs=device\-specs/specs\-\fR to the compiler driver's +command line. The user takes responsibility for supplying the sub-processes +like compiler proper, assembler and linker with appropriate command line +options. +.IP "\fB\-Waddr\-space\-convert\fR" 4 +.IX Item "-Waddr-space-convert" +Warn about conversions between address spaces in the case where the +resulting address space is not contained in the incoming address space. +.IP "\fB\-Wmisspelled\-isr\fR" 4 +.IX Item "-Wmisspelled-isr" +Warn if the \s-1ISR\s0 is misspelled, i.e. without _\|_vector prefix. +Enabled by default. +.PP +\f(CW\*(C`EIND\*(C'\fR and Devices with More Than 128 Ki Bytes of Flash +.IX Subsection "EIND and Devices with More Than 128 Ki Bytes of Flash" +.PP +Pointers in the implementation are 16 bits wide. +The address of a function or label is represented as word address so +that indirect jumps and calls can target any code address in the +range of 64 Ki words. +.PP +In order to facilitate indirect jump on devices with more than 128 Ki +bytes of program memory space, there is a special function register called +\&\f(CW\*(C`EIND\*(C'\fR that serves as most significant part of the target address +when \f(CW\*(C`EICALL\*(C'\fR or \f(CW\*(C`EIJMP\*(C'\fR instructions are used. +.PP +Indirect jumps and calls on these devices are handled as follows by +the compiler and are subject to some limitations: +.IP "*" 4 +The compiler never sets \f(CW\*(C`EIND\*(C'\fR. +.IP "*" 4 +The compiler uses \f(CW\*(C`EIND\*(C'\fR implicitly in \f(CW\*(C`EICALL\*(C'\fR/\f(CW\*(C`EIJMP\*(C'\fR +instructions or might read \f(CW\*(C`EIND\*(C'\fR directly in order to emulate an +indirect call/jump by means of a \f(CW\*(C`RET\*(C'\fR instruction. +.IP "*" 4 +The compiler assumes that \f(CW\*(C`EIND\*(C'\fR never changes during the startup +code or during the application. In particular, \f(CW\*(C`EIND\*(C'\fR is not +saved/restored in function or interrupt service routine +prologue/epilogue. +.IP "*" 4 +For indirect calls to functions and computed goto, the linker +generates \fIstubs\fR. Stubs are jump pads sometimes also called +\&\fItrampolines\fR. Thus, the indirect call/jump jumps to such a stub. +The stub contains a direct jump to the desired address. +.IP "*" 4 +Linker relaxation must be turned on so that the linker generates +the stubs correctly in all situations. See the compiler option +\&\fB\-mrelax\fR and the linker option \fB\-\-relax\fR. +There are corner cases where the linker is supposed to generate stubs +but aborts without relaxation and without a helpful error message. +.IP "*" 4 +The default linker script is arranged for code with \f(CW\*(C`EIND = 0\*(C'\fR. +If code is supposed to work for a setup with \f(CW\*(C`EIND != 0\*(C'\fR, a custom +linker script has to be used in order to place the sections whose +name start with \f(CW\*(C`.trampolines\*(C'\fR into the segment where \f(CW\*(C`EIND\*(C'\fR +points to. +.IP "*" 4 +The startup code from libgcc never sets \f(CW\*(C`EIND\*(C'\fR. +Notice that startup code is a blend of code from libgcc and AVR-LibC. +For the impact of AVR-LibC on \f(CW\*(C`EIND\*(C'\fR, see the +AVR-LibC\ user\ manual (\f(CW\*(C`http://nongnu.org/avr\-libc/user\-manual/\*(C'\fR). +.IP "*" 4 +It is legitimate for user-specific startup code to set up \f(CW\*(C`EIND\*(C'\fR +early, for example by means of initialization code located in +section \f(CW\*(C`.init3\*(C'\fR. Such code runs prior to general startup code +that initializes \s-1RAM\s0 and calls constructors, but after the bit +of startup code from AVR-LibC that sets \f(CW\*(C`EIND\*(C'\fR to the segment +where the vector table is located. +.Sp +.Vb 1 +\& #include +\& +\& static void +\& _\|_attribute_\|_((section(".init3"),naked,used,no_instrument_function)) +\& init3_set_eind (void) +\& { +\& _\|_asm volatile ("ldi r24,pm_hh8(_\|_trampolines_start)\en\et" +\& "out %i0,r24" :: "n" (&EIND) : "r24","memory"); +\& } +.Ve +.Sp +The \f(CW\*(C`_\|_trampolines_start\*(C'\fR symbol is defined in the linker script. +.IP "*" 4 +Stubs are generated automatically by the linker if +the following two conditions are met: +.RS 4 +.ie n .IP "\-" 4 +.el .IP "\-" 4 +.IX Item "-" +(short for \fIgenerate stubs\fR) like so: +.Sp +.Vb 2 +\& LDI r24, lo8(gs()) +\& LDI r25, hi8(gs()) +.Ve +.IP "\-" 4 +.IX Item "-" +\&\fIoutside\fR the segment where the stubs are located. +.RE +.RS 4 +.RE +.IP "*" 4 +The compiler emits such \f(CW\*(C`gs\*(C'\fR modifiers for code labels in the +following situations: +.RS 4 +.IP "\-" 4 +.IX Item "-" +.PD 0 +.IP "\-" 4 +.IX Item "-" +.IP "\-" 4 +.IX Item "-" +.PD +command-line option. +.IP "\-" 4 +.IX Item "-" +tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. +.IP "\-" 4 +.IX Item "-" +.PD 0 +.ie n .IP "\-" 4 +.el .IP "\-" 4 +.IX Item "-" +.RE +.RS 4 +.RE +.IP "*" 4 +.PD +Jumping to non-symbolic addresses like so is \fInot\fR supported: +.Sp +.Vb 5 +\& int main (void) +\& { +\& /* Call function at word address 0x2 */ +\& return ((int(*)(void)) 0x2)(); +\& } +.Ve +.Sp +Instead, a stub has to be set up, i.e. the function has to be called +through a symbol (\f(CW\*(C`func_4\*(C'\fR in the example): +.Sp +.Vb 3 +\& int main (void) +\& { +\& extern int func_4 (void); +\& +\& /* Call function at byte address 0x4 */ +\& return func_4(); +\& } +.Ve +.Sp +and the application be linked with \fB\-Wl,\-\-defsym,func_4=0x4\fR. +Alternatively, \f(CW\*(C`func_4\*(C'\fR can be defined in the linker script. +.PP +Handling of the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR and \f(CW\*(C`RAMPZ\*(C'\fR Special Function Registers +.IX Subsection "Handling of the RAMPD, RAMPX, RAMPY and RAMPZ Special Function Registers" +.PP +Some \s-1AVR\s0 devices support memories larger than the 64 KiB range +that can be accessed with 16\-bit pointers. To access memory locations +outside this 64 KiB range, the content of a \f(CW\*(C`RAMP\*(C'\fR +register is used as high part of the address: +The \f(CW\*(C`X\*(C'\fR, \f(CW\*(C`Y\*(C'\fR, \f(CW\*(C`Z\*(C'\fR address register is concatenated +with the \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR, \f(CW\*(C`RAMPZ\*(C'\fR special function +register, respectively, to get a wide address. Similarly, +\&\f(CW\*(C`RAMPD\*(C'\fR is used together with direct addressing. +.IP "*" 4 +The startup code initializes the \f(CW\*(C`RAMP\*(C'\fR special function +registers with zero. +.IP "*" 4 +If a \fB\s-1AVR\s0 Named Address Spaces,named address space\fR other than +generic or \f(CW\*(C`_\|_flash\*(C'\fR is used, then \f(CW\*(C`RAMPZ\*(C'\fR is set +as needed before the operation. +.IP "*" 4 +If the device supports \s-1RAM\s0 larger than 64 KiB and the compiler +needs to change \f(CW\*(C`RAMPZ\*(C'\fR to accomplish an operation, \f(CW\*(C`RAMPZ\*(C'\fR +is reset to zero after the operation. +.IP "*" 4 +If the device comes with a specific \f(CW\*(C`RAMP\*(C'\fR register, the \s-1ISR\s0 +prologue/epilogue saves/restores that \s-1SFR\s0 and initializes it with +zero in case the \s-1ISR\s0 code might (implicitly) use it. +.IP "*" 4 +\&\s-1RAM\s0 larger than 64 KiB is not supported by \s-1GCC\s0 for \s-1AVR\s0 targets. +If you use inline assembler to read from locations outside the +16\-bit address range and change one of the \f(CW\*(C`RAMP\*(C'\fR registers, +you must reset it to zero after the access. +.PP +\s-1AVR\s0 Built-in Macros +.IX Subsection "AVR Built-in Macros" +.PP +\&\s-1GCC\s0 defines several built-in macros so that the user code can test +for the presence or absence of features. Almost any of the following +built-in macros are deduced from device capabilities and thus +triggered by the \fB\-mmcu=\fR command-line option. +.PP +For even more AVR-specific built-in macros see +\&\fB\s-1AVR\s0 Named Address Spaces\fR and \fB\s-1AVR\s0 Built-in Functions\fR. +.ie n .IP """_\|_AVR_ARCH_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ARCH_\|_\fR" 4 +.IX Item "__AVR_ARCH__" +Build-in macro that resolves to a decimal number that identifies the +architecture and depends on the \fB\-mmcu=\fR\fImcu\fR option. +Possible values are: +.Sp +\&\f(CW2\fR, \f(CW25\fR, \f(CW3\fR, \f(CW31\fR, \f(CW35\fR, +\&\f(CW4\fR, \f(CW5\fR, \f(CW51\fR, \f(CW6\fR +.Sp +for \fImcu\fR=\f(CW\*(C`avr2\*(C'\fR, \f(CW\*(C`avr25\*(C'\fR, \f(CW\*(C`avr3\*(C'\fR, \f(CW\*(C`avr31\*(C'\fR, +\&\f(CW\*(C`avr35\*(C'\fR, \f(CW\*(C`avr4\*(C'\fR, \f(CW\*(C`avr5\*(C'\fR, \f(CW\*(C`avr51\*(C'\fR, \f(CW\*(C`avr6\*(C'\fR, +.Sp +respectively and +.Sp +\&\f(CW100\fR, +\&\f(CW102\fR, \f(CW103\fR, \f(CW104\fR, +\&\f(CW105\fR, \f(CW106\fR, \f(CW107\fR +.Sp +for \fImcu\fR=\f(CW\*(C`avrtiny\*(C'\fR, +\&\f(CW\*(C`avrxmega2\*(C'\fR, \f(CW\*(C`avrxmega3\*(C'\fR, \f(CW\*(C`avrxmega4\*(C'\fR, +\&\f(CW\*(C`avrxmega5\*(C'\fR, \f(CW\*(C`avrxmega6\*(C'\fR, \f(CW\*(C`avrxmega7\*(C'\fR, respectively. +If \fImcu\fR specifies a device, this built-in macro is set +accordingly. For example, with \fB\-mmcu=atmega8\fR the macro is +defined to \f(CW4\fR. +.ie n .IP """_\|_AVR_\fIDevice\fP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_\f(CIDevice\f(CW_\|_\fR" 4 +.IX Item "__AVR_Device__" +Setting \fB\-mmcu=\fR\fIdevice\fR defines this built-in macro which reflects +the device's name. For example, \fB\-mmcu=atmega8\fR defines the +built-in macro \f(CW\*(C`_\|_AVR_ATmega8_\|_\*(C'\fR, \fB\-mmcu=attiny261a\fR defines +\&\f(CW\*(C`_\|_AVR_ATtiny261A_\|_\*(C'\fR, etc. +.Sp +The built-in macros' names follow +the scheme \f(CW\*(C`_\|_AVR_\f(CIDevice\f(CW_\|_\*(C'\fR where \fIDevice\fR is +the device name as from the \s-1AVR\s0 user manual. The difference between +\&\fIDevice\fR in the built-in macro and \fIdevice\fR in +\&\fB\-mmcu=\fR\fIdevice\fR is that the latter is always lowercase. +.Sp +If \fIdevice\fR is not a device but only a core architecture like +\&\fBavr51\fR, this macro is not defined. +.ie n .IP """_\|_AVR_DEVICE_NAME_\|_""" 4 +.el .IP "\f(CW_\|_AVR_DEVICE_NAME_\|_\fR" 4 +.IX Item "__AVR_DEVICE_NAME__" +Setting \fB\-mmcu=\fR\fIdevice\fR defines this built-in macro to +the device's name. For example, with \fB\-mmcu=atmega8\fR the macro +is defined to \f(CW\*(C`atmega8\*(C'\fR. +.Sp +If \fIdevice\fR is not a device but only a core architecture like +\&\fBavr51\fR, this macro is not defined. +.ie n .IP """_\|_AVR_XMEGA_\|_""" 4 +.el .IP "\f(CW_\|_AVR_XMEGA_\|_\fR" 4 +.IX Item "__AVR_XMEGA__" +The device / architecture belongs to the \s-1XMEGA\s0 family of devices. +.ie n .IP """_\|_AVR_HAVE_ELPM_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_ELPM_\|_\fR" 4 +.IX Item "__AVR_HAVE_ELPM__" +The device has the \f(CW\*(C`ELPM\*(C'\fR instruction. +.ie n .IP """_\|_AVR_HAVE_ELPMX_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_ELPMX_\|_\fR" 4 +.IX Item "__AVR_HAVE_ELPMX__" +The device has the \f(CW\*(C`ELPM R\f(CIn\f(CW,Z\*(C'\fR and \f(CW\*(C`ELPM +R\f(CIn\f(CW,Z+\*(C'\fR instructions. +.ie n .IP """_\|_AVR_HAVE_MOVW_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_MOVW_\|_\fR" 4 +.IX Item "__AVR_HAVE_MOVW__" +The device has the \f(CW\*(C`MOVW\*(C'\fR instruction to perform 16\-bit +register-register moves. +.ie n .IP """_\|_AVR_HAVE_LPMX_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_LPMX_\|_\fR" 4 +.IX Item "__AVR_HAVE_LPMX__" +The device has the \f(CW\*(C`LPM R\f(CIn\f(CW,Z\*(C'\fR and +\&\f(CW\*(C`LPM R\f(CIn\f(CW,Z+\*(C'\fR instructions. +.ie n .IP """_\|_AVR_HAVE_MUL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_MUL_\|_\fR" 4 +.IX Item "__AVR_HAVE_MUL__" +The device has a hardware multiplier. +.ie n .IP """_\|_AVR_HAVE_JMP_CALL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_JMP_CALL_\|_\fR" 4 +.IX Item "__AVR_HAVE_JMP_CALL__" +The device has the \f(CW\*(C`JMP\*(C'\fR and \f(CW\*(C`CALL\*(C'\fR instructions. +This is the case for devices with more than 8 KiB of program +memory. +.ie n .IP """_\|_AVR_HAVE_EIJMP_EICALL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_EIJMP_EICALL_\|_\fR" 4 +.IX Item "__AVR_HAVE_EIJMP_EICALL__" +.PD 0 +.ie n .IP """_\|_AVR_3_BYTE_PC_\|_""" 4 +.el .IP "\f(CW_\|_AVR_3_BYTE_PC_\|_\fR" 4 +.IX Item "__AVR_3_BYTE_PC__" +.PD +The device has the \f(CW\*(C`EIJMP\*(C'\fR and \f(CW\*(C`EICALL\*(C'\fR instructions. +This is the case for devices with more than 128 KiB of program memory. +This also means that the program counter +(\s-1PC\s0) is 3 bytes wide. +.ie n .IP """_\|_AVR_2_BYTE_PC_\|_""" 4 +.el .IP "\f(CW_\|_AVR_2_BYTE_PC_\|_\fR" 4 +.IX Item "__AVR_2_BYTE_PC__" +The program counter (\s-1PC\s0) is 2 bytes wide. This is the case for devices +with up to 128 KiB of program memory. +.ie n .IP """_\|_AVR_HAVE_8BIT_SP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_8BIT_SP_\|_\fR" 4 +.IX Item "__AVR_HAVE_8BIT_SP__" +.PD 0 +.ie n .IP """_\|_AVR_HAVE_16BIT_SP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_16BIT_SP_\|_\fR" 4 +.IX Item "__AVR_HAVE_16BIT_SP__" +.PD +The stack pointer (\s-1SP\s0) register is treated as 8\-bit respectively +16\-bit register by the compiler. +The definition of these macros is affected by \fB\-mtiny\-stack\fR. +.ie n .IP """_\|_AVR_HAVE_SPH_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_SPH_\|_\fR" 4 +.IX Item "__AVR_HAVE_SPH__" +.PD 0 +.ie n .IP """_\|_AVR_SP8_\|_""" 4 +.el .IP "\f(CW_\|_AVR_SP8_\|_\fR" 4 +.IX Item "__AVR_SP8__" +.PD +The device has the \s-1SPH\s0 (high part of stack pointer) special function +register or has an 8\-bit stack pointer, respectively. +The definition of these macros is affected by \fB\-mmcu=\fR and +in the cases of \fB\-mmcu=avr2\fR and \fB\-mmcu=avr25\fR also +by \fB\-msp8\fR. +.ie n .IP """_\|_AVR_HAVE_RAMPD_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPD_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPD__" +.PD 0 +.ie n .IP """_\|_AVR_HAVE_RAMPX_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPX_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPX__" +.ie n .IP """_\|_AVR_HAVE_RAMPY_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPY_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPY__" +.ie n .IP """_\|_AVR_HAVE_RAMPZ_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPZ_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPZ__" +.PD +The device has the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR, +\&\f(CW\*(C`RAMPZ\*(C'\fR special function register, respectively. +.ie n .IP """_\|_NO_INTERRUPTS_\|_""" 4 +.el .IP "\f(CW_\|_NO_INTERRUPTS_\|_\fR" 4 +.IX Item "__NO_INTERRUPTS__" +This macro reflects the \fB\-mno\-interrupts\fR command-line option. +.ie n .IP """_\|_AVR_ERRATA_SKIP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ERRATA_SKIP_\|_\fR" 4 +.IX Item "__AVR_ERRATA_SKIP__" +.PD 0 +.ie n .IP """_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_\fR" 4 +.IX Item "__AVR_ERRATA_SKIP_JMP_CALL__" +.PD +Some \s-1AVR\s0 devices (\s-1AT90S8515,\s0 ATmega103) must not skip 32\-bit +instructions because of a hardware erratum. Skip instructions are +\&\f(CW\*(C`SBRS\*(C'\fR, \f(CW\*(C`SBRC\*(C'\fR, \f(CW\*(C`SBIS\*(C'\fR, \f(CW\*(C`SBIC\*(C'\fR and \f(CW\*(C`CPSE\*(C'\fR. +The second macro is only defined if \f(CW\*(C`_\|_AVR_HAVE_JMP_CALL_\|_\*(C'\fR is also +set. +.ie n .IP """_\|_AVR_ISA_RMW_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ISA_RMW_\|_\fR" 4 +.IX Item "__AVR_ISA_RMW__" +The device has Read-Modify-Write instructions (\s-1XCH, LAC, LAS\s0 and \s-1LAT\s0). +.ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\fIoffset\fP""" 4 +.el .IP "\f(CW_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW\fR" 4 +.IX Item "__AVR_SFR_OFFSET__=offset" +Instructions that can address I/O special function registers directly +like \f(CW\*(C`IN\*(C'\fR, \f(CW\*(C`OUT\*(C'\fR, \f(CW\*(C`SBI\*(C'\fR, etc. may use a different +address as if addressed by an instruction to access \s-1RAM\s0 like \f(CW\*(C`LD\*(C'\fR +or \f(CW\*(C`STS\*(C'\fR. This offset depends on the device architecture and has +to be subtracted from the \s-1RAM\s0 address in order to get the +respective I/O address. +.ie n .IP """_\|_AVR_SHORT_CALLS_\|_""" 4 +.el .IP "\f(CW_\|_AVR_SHORT_CALLS_\|_\fR" 4 +.IX Item "__AVR_SHORT_CALLS__" +The \fB\-mshort\-calls\fR command line option is set. +.ie n .IP """_\|_AVR_PM_BASE_ADDRESS_\|_=\fIaddr\fP""" 4 +.el .IP "\f(CW_\|_AVR_PM_BASE_ADDRESS_\|_=\f(CIaddr\f(CW\fR" 4 +.IX Item "__AVR_PM_BASE_ADDRESS__=addr" +Some devices support reading from flash memory by means of \f(CW\*(C`LD*\*(C'\fR +instructions. The flash memory is seen in the data address space +at an offset of \f(CW\*(C`_\|_AVR_PM_BASE_ADDRESS_\|_\*(C'\fR. If this macro +is not defined, this feature is not available. If defined, +the address space is linear and there is no need to put +\&\f(CW\*(C`.rodata\*(C'\fR into \s-1RAM.\s0 This is handled by the default linker +description file, and is currently available for +\&\f(CW\*(C`avrtiny\*(C'\fR and \f(CW\*(C`avrxmega3\*(C'\fR. Even more convenient, +there is no need to use address spaces like \f(CW\*(C`_\|_flash\*(C'\fR or +features like attribute \f(CW\*(C`progmem\*(C'\fR and \f(CW\*(C`pgm_read_*\*(C'\fR. +.ie n .IP """_\|_WITH_AVRLIBC_\|_""" 4 +.el .IP "\f(CW_\|_WITH_AVRLIBC_\|_\fR" 4 +.IX Item "__WITH_AVRLIBC__" +The compiler is configured to be used together with AVR-Libc. +See the \fB\-\-with\-avrlibc\fR configure option. +.PP +\fIBlackfin Options\fR +.IX Subsection "Blackfin Options" +.IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4 +.IX Item "-mcpu=cpu[-sirevision]" +Specifies the name of the target Blackfin processor. Currently, \fIcpu\fR +can be one of \fBbf512\fR, \fBbf514\fR, \fBbf516\fR, \fBbf518\fR, +\&\fBbf522\fR, \fBbf523\fR, \fBbf524\fR, \fBbf525\fR, \fBbf526\fR, +\&\fBbf527\fR, \fBbf531\fR, \fBbf532\fR, \fBbf533\fR, +\&\fBbf534\fR, \fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR, +\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR, +\&\fBbf542m\fR, \fBbf544m\fR, \fBbf547m\fR, \fBbf548m\fR, \fBbf549m\fR, +\&\fBbf561\fR, \fBbf592\fR. +.Sp +The optional \fIsirevision\fR specifies the silicon revision of the target +Blackfin processor. Any workarounds available for the targeted silicon revision +are enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled. +If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor +are enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two +hexadecimal digits representing the major and minor numbers in the silicon +revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR +is not defined. If \fIsirevision\fR is \fBany\fR, the +\&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR. +If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known +silicon revision of the targeted Blackfin processor. +.Sp +\&\s-1GCC\s0 defines a preprocessor macro for the specified \fIcpu\fR. +For the \fBbfin-elf\fR toolchain, this option causes the hardware \s-1BSP\s0 +provided by libgloss to be linked in if \fB\-msim\fR is not given. +.Sp +Without this option, \fBbf532\fR is used as the processor by default. +.Sp +Note that support for \fBbf561\fR is incomplete. For \fBbf561\fR, +only the preprocessor macro is defined. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +the simulator \s-1BSP\s0 provided by libgloss to be linked in. This option +has effect only for \fBbfin-elf\fR toolchain. +Certain other options, such as \fB\-mid\-shared\-library\fR and +\&\fB\-mfdpic\fR, imply \fB\-msim\fR. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up and restore frame pointers and +makes an extra register available in leaf functions. +.IP "\fB\-mspecld\-anomaly\fR" 4 +.IX Item "-mspecld-anomaly" +When enabled, the compiler ensures that the generated code does not +contain speculative loads after jump instructions. If this option is used, +\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined. +.IP "\fB\-mno\-specld\-anomaly\fR" 4 +.IX Item "-mno-specld-anomaly" +Don't generate extra code to prevent speculative loads from occurring. +.IP "\fB\-mcsync\-anomaly\fR" 4 +.IX Item "-mcsync-anomaly" +When enabled, the compiler ensures that the generated code does not +contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches. +If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined. +.IP "\fB\-mno\-csync\-anomaly\fR" 4 +.IX Item "-mno-csync-anomaly" +Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from +occurring too soon after a conditional branch. +.IP "\fB\-mlow64k\fR" 4 +.IX Item "-mlow64k" +When enabled, the compiler is free to take advantage of the knowledge that +the entire program fits into the low 64k of memory. +.IP "\fB\-mno\-low64k\fR" 4 +.IX Item "-mno-low64k" +Assume that the program is arbitrarily large. This is the default. +.IP "\fB\-mstack\-check\-l1\fR" 4 +.IX Item "-mstack-check-l1" +Do stack checking using information placed into L1 scratchpad memory by the +uClinux kernel. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute in place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume ID-based shared libraries are being used. +This is the default. +.IP "\fB\-mleaf\-id\-shared\-library\fR" 4 +.IX Item "-mleaf-id-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method, +but assumes that this library or executable won't link against any other +\&\s-1ID\s0 shared libraries. That allows the compiler to use faster code for jumps +and calls. +.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4 +.IX Item "-mno-leaf-id-shared-library" +Do not assume that the code being compiled won't link against any \s-1ID\s0 shared +libraries. Slower code is generated for jump and call insns. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specifies the identification number of the ID-based shared library being +compiled. Specifying a value of 0 generates more compact code; specifying +other values forces the allocation of that number to the current +library but is no more space\- or time-efficient than omitting this option. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute in place in +an environment without virtual memory management by eliminating relocations +against the text section. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +lies outside of the 24\-bit addressing range of the offset-based +version of subroutine call instruction. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR restores the default behavior. Note these +switches have no effect on how the compiler generates code to handle +function calls via function pointers. +.IP "\fB\-mfast\-fp\fR" 4 +.IX Item "-mfast-fp" +Link with the fast floating-point library. This library relaxes some of +the \s-1IEEE\s0 floating-point standard's rules for checking inputs against +Not-a-Number (\s-1NAN\s0), in the interest of performance. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +.IP "\fB\-mmulticore\fR" 4 +.IX Item "-mmulticore" +Build a standalone application for multicore Blackfin processors. +This option causes proper start files and link scripts supporting +multicore to be used, and defines the macro \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. +It can only be used with \fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. +.Sp +This option can be used with \fB\-mcorea\fR or \fB\-mcoreb\fR, which +selects the one-application-per-core programming model. Without +\&\fB\-mcorea\fR or \fB\-mcoreb\fR, the single\-application/dual\-core +programming model is used. In this model, the main function of Core B +should be named as \f(CW\*(C`coreb_main\*(C'\fR. +.Sp +If this option is not used, the single-core application programming +model is used. +.IP "\fB\-mcorea\fR" 4 +.IX Item "-mcorea" +Build a standalone application for Core A of \s-1BF561\s0 when using +the one-application-per-core programming model. Proper start files +and link scripts are used to support Core A, and the macro +\&\f(CW\*(C`_\|_BFIN_COREA\*(C'\fR is defined. +This option can only be used in conjunction with \fB\-mmulticore\fR. +.IP "\fB\-mcoreb\fR" 4 +.IX Item "-mcoreb" +Build a standalone application for Core B of \s-1BF561\s0 when using +the one-application-per-core programming model. Proper start files +and link scripts are used to support Core B, and the macro +\&\f(CW\*(C`_\|_BFIN_COREB\*(C'\fR is defined. When this option is used, \f(CW\*(C`coreb_main\*(C'\fR +should be used instead of \f(CW\*(C`main\*(C'\fR. +This option can only be used in conjunction with \fB\-mmulticore\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Build a standalone application for \s-1SDRAM.\s0 Proper start files and +link scripts are used to put the application into \s-1SDRAM,\s0 and the macro +\&\f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR is defined. +The loader should initialize \s-1SDRAM\s0 before loading the application. +.IP "\fB\-micplb\fR" 4 +.IX Item "-micplb" +Assume that ICPLBs are enabled at run time. This has an effect on certain +anomaly workarounds. For Linux targets, the default is to assume ICPLBs +are enabled; for standalone applications the default is off. +.PP +\fIC6X Options\fR +.IX Subsection "C6X Options" +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. Permissible names are: \fBc62x\fR, +\&\fBc64x\fR, \fBc64x+\fR, \fBc67x\fR, \fBc67x+\fR, \fBc674x\fR. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. This is the default. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Choose startup files and linker script suitable for the simulator. +.IP "\fB\-msdata=default\fR" 4 +.IX Item "-msdata=default" +Put small global and static data in the \f(CW\*(C`.neardata\*(C'\fR section, +which is pointed to by register \f(CW\*(C`B14\*(C'\fR. Put small uninitialized +global and static data in the \f(CW\*(C`.bss\*(C'\fR section, which is adjacent +to the \f(CW\*(C`.neardata\*(C'\fR section. Put small read-only data into the +\&\f(CW\*(C`.rodata\*(C'\fR section. The corresponding sections used for large +pieces of data are \f(CW\*(C`.fardata\*(C'\fR, \f(CW\*(C`.far\*(C'\fR and \f(CW\*(C`.const\*(C'\fR. +.IP "\fB\-msdata=all\fR" 4 +.IX Item "-msdata=all" +Put all data, not just small objects, into the sections reserved for +small data, and use addressing relative to the \f(CW\*(C`B14\*(C'\fR register to +access them. +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +Make no use of the sections reserved for small data, and use absolute +addresses to access all data. Put all initialized global and static +data in the \f(CW\*(C`.fardata\*(C'\fR section, and all uninitialized data in the +\&\f(CW\*(C`.far\*(C'\fR section. Put all constant data into the \f(CW\*(C`.const\*(C'\fR +section. +.PP +\fI\s-1CRIS\s0 Options\fR +.IX Subsection "CRIS Options" +.PP +These options are defined specifically for the \s-1CRIS\s0 ports. +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +.PD 0 +.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mcpu=architecture-type" +.PD +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for +respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX.\s0 +Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is +\&\fBv10\fR. +.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mtune=architecture-type" +Tune to \fIarchitecture-type\fR everything applicable about the generated +code, except for the \s-1ABI\s0 and the set of available instructions. The +choices for \fIarchitecture-type\fR are the same as for +\&\fB\-march=\fR\fIarchitecture-type\fR. +.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4 +.IX Item "-mmax-stack-frame=n" +Warn when the stack frame of a function exceeds \fIn\fR bytes. +.IP "\fB\-metrax4\fR" 4 +.IX Item "-metrax4" +.PD 0 +.IP "\fB\-metrax100\fR" 4 +.IX Item "-metrax100" +.PD +The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for +\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively. +.IP "\fB\-mmul\-bug\-workaround\fR" 4 +.IX Item "-mmul-bug-workaround" +.PD 0 +.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4 +.IX Item "-mno-mul-bug-workaround" +.PD +Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0 +models where it applies. This option is active by default. +.IP "\fB\-mpdebug\fR" 4 +.IX Item "-mpdebug" +Enable CRIS-specific verbose debug-related information in the assembly +code. This option also has the effect of turning off the \fB#NO_APP\fR +formatted-code indicator to the assembler at the beginning of the +assembly file. +.IP "\fB\-mcc\-init\fR" 4 +.IX Item "-mcc-init" +Do not use condition-code results from previous instruction; always emit +compare and test instructions before use of condition codes. +.IP "\fB\-mno\-side\-effects\fR" 4 +.IX Item "-mno-side-effects" +Do not emit instructions with side effects in addressing modes other than +post-increment. +.IP "\fB\-mstack\-align\fR" 4 +.IX Item "-mstack-align" +.PD 0 +.IP "\fB\-mno\-stack\-align\fR" 4 +.IX Item "-mno-stack-align" +.IP "\fB\-mdata\-align\fR" 4 +.IX Item "-mdata-align" +.IP "\fB\-mno\-data\-align\fR" 4 +.IX Item "-mno-data-align" +.IP "\fB\-mconst\-align\fR" 4 +.IX Item "-mconst-align" +.IP "\fB\-mno\-const\-align\fR" 4 +.IX Item "-mno-const-align" +.PD +These options (\fBno\-\fR options) arrange (eliminate arrangements) for the +stack frame, individual data and constants to be aligned for the maximum +single data access size for the chosen \s-1CPU\s0 model. The default is to +arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are +not affected by these options. +.IP "\fB\-m32\-bit\fR" 4 +.IX Item "-m32-bit" +.PD 0 +.IP "\fB\-m16\-bit\fR" 4 +.IX Item "-m16-bit" +.IP "\fB\-m8\-bit\fR" 4 +.IX Item "-m8-bit" +.PD +Similar to the stack\- data\- and const-align options above, these options +arrange for stack frame, writable data and constants to all be 32\-bit, +16\-bit or 8\-bit aligned. The default is 32\-bit alignment. +.IP "\fB\-mno\-prologue\-epilogue\fR" 4 +.IX Item "-mno-prologue-epilogue" +.PD 0 +.IP "\fB\-mprologue\-epilogue\fR" 4 +.IX Item "-mprologue-epilogue" +.PD +With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and +epilogue which set up the stack frame are omitted and no return +instructions or return sequences are generated in the code. Use this +option only together with visual inspection of the compiled code: no +warnings or errors are generated when call-saved registers must be saved, +or storage for local variables needs to be allocated. +.IP "\fB\-mno\-gotplt\fR" 4 +.IX Item "-mno-gotplt" +.PD 0 +.IP "\fB\-mgotplt\fR" 4 +.IX Item "-mgotplt" +.PD +With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) +instruction sequences that load addresses for functions from the \s-1PLT\s0 part +of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the +\&\s-1PLT.\s0 The default is \fB\-mgotplt\fR. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Legacy no-op option only recognized with the cris-axis-elf and +cris-axis-linux-gnu targets. +.IP "\fB\-mlinux\fR" 4 +.IX Item "-mlinux" +Legacy no-op option only recognized with the cris-axis-linux-gnu target. +.IP "\fB\-sim\fR" 4 +.IX Item "-sim" +This option, recognized for the cris-axis-elf, arranges +to link with input-output functions from a simulator library. Code, +initialized data and zero-initialized data are allocated consecutively. +.IP "\fB\-sim2\fR" 4 +.IX Item "-sim2" +Like \fB\-sim\fR, but pass linker options to locate initialized data at +0x40000000 and zero-initialized data at 0x80000000. +.PP +\fI\s-1CR16\s0 Options\fR +.IX Subsection "CR16 Options" +.PP +These options are defined specifically for the \s-1CR16\s0 ports. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mcr16cplus\fR" 4 +.IX Item "-mcr16cplus" +.PD 0 +.IP "\fB\-mcr16c\fR" 4 +.IX Item "-mcr16c" +.PD +Generate code for \s-1CR16C\s0 or \s-1CR16C+\s0 architecture. \s-1CR16C+\s0 architecture +is default. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Links the library libsim.a which is in compatible with simulator. Applicable +to \s-1ELF\s0 compiler only. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +Choose integer type as 32\-bit wide. +.IP "\fB\-mbit\-ops\fR" 4 +.IX Item "-mbit-ops" +Generates \f(CW\*(C`sbit\*(C'\fR/\f(CW\*(C`cbit\*(C'\fR instructions for bit manipulations. +.IP "\fB\-mdata\-model=\fR\fImodel\fR" 4 +.IX Item "-mdata-model=model" +Choose a data model. The choices for \fImodel\fR are \fBnear\fR, +\&\fBfar\fR or \fBmedium\fR. \fBmedium\fR is default. +However, \fBfar\fR is not valid with \fB\-mcr16c\fR, as the +\&\s-1CR16C\s0 architecture does not support the far data model. +.PP +\fIC\-SKY Options\fR +.IX Subsection "C-SKY Options" +.PP +\&\s-1GCC\s0 supports these options when compiling for C\-SKY V2 processors. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Specify the C\-SKY target architecture. Valid values for \fIarch\fR are: +\&\fBck801\fR, \fBck802\fR, \fBck803\fR, \fBck807\fR, and \fBck810\fR. +The default is \fBck810\fR. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Specify the C\-SKY target processor. Valid values for \fIcpu\fR are: +\&\fBck801\fR, \fBck801t\fR, +\&\fBck802\fR, \fBck802t\fR, \fBck802j\fR, +\&\fBck803\fR, \fBck803h\fR, \fBck803t\fR, \fBck803ht\fR, +\&\fBck803f\fR, \fBck803fh\fR, \fBck803e\fR, \fBck803eh\fR, +\&\fBck803et\fR, \fBck803eht\fR, \fBck803ef\fR, \fBck803efh\fR, +\&\fBck803ft\fR, \fBck803eft\fR, \fBck803efht\fR, \fBck803r1\fR, +\&\fBck803hr1\fR, \fBck803tr1\fR, \fBck803htr1\fR, \fBck803fr1\fR, +\&\fBck803fhr1\fR, \fBck803er1\fR, \fBck803ehr1\fR, \fBck803etr1\fR, +\&\fBck803ehtr1\fR, \fBck803efr1\fR, \fBck803efhr1\fR, \fBck803ftr1\fR, +\&\fBck803eftr1\fR, \fBck803efhtr1\fR, +\&\fBck803s\fR, \fBck803st\fR, \fBck803se\fR, \fBck803sf\fR, +\&\fBck803sef\fR, \fBck803seft\fR, +\&\fBck807e\fR, \fBck807ef\fR, \fBck807\fR, \fBck807f\fR, +\&\fBck810e\fR, \fBck810et\fR, \fBck810ef\fR, \fBck810eft\fR, +\&\fBck810\fR, \fBck810v\fR, \fBck810f\fR, \fBck810t\fR, \fBck810fv\fR, +\&\fBck810tv\fR, \fBck810ft\fR, and \fBck810ftv\fR. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +.PD +Select big\- or little-endian code. The default is little-endian. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Select hardware or software floating-point implementations. +The default is soft float. +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +.PD 0 +.IP "\fB\-mno\-double\-float\fR" 4 +.IX Item "-mno-double-float" +.PD +When \fB\-mhard\-float\fR is in effect, enable generation of +double-precision float instructions. This is the default except +when compiling for \s-1CK803.\s0 +.IP "\fB\-mfdivdu\fR" 4 +.IX Item "-mfdivdu" +.PD 0 +.IP "\fB\-mno\-fdivdu\fR" 4 +.IX Item "-mno-fdivdu" +.PD +When \fB\-mhard\-float\fR is in effect, enable generation of +\&\f(CW\*(C`frecipd\*(C'\fR, \f(CW\*(C`fsqrtd\*(C'\fR, and \f(CW\*(C`fdivd\*(C'\fR instructions. +This is the default except when compiling for \s-1CK803.\s0 +.IP "\fB\-mfpu=\fR\fIfpu\fR" 4 +.IX Item "-mfpu=fpu" +Select the floating-point processor. This option can only be used with +\&\fB\-mhard\-float\fR. +Values for \fIfpu\fR are +\&\fBfpv2_sf\fR (equivalent to \fB\-mno\-double\-float \-mno\-fdivdu\fR), +\&\fBfpv2\fR (\fB\-mdouble\-float \-mno\-divdu\fR), and +\&\fBfpv2_divd\fR (\fB\-mdouble\-float \-mdivdu\fR). +.IP "\fB\-melrw\fR" 4 +.IX Item "-melrw" +.PD 0 +.IP "\fB\-mno\-elrw\fR" 4 +.IX Item "-mno-elrw" +.PD +Enable the extended \f(CW\*(C`lrw\*(C'\fR instruction. This option defaults to on +for \s-1CK801\s0 and off otherwise. +.IP "\fB\-mistack\fR" 4 +.IX Item "-mistack" +.PD 0 +.IP "\fB\-mno\-istack\fR" 4 +.IX Item "-mno-istack" +.PD +Enable interrupt stack instructions; the default is off. +.Sp +The \fB\-mistack\fR option is required to handle the +\&\f(CW\*(C`interrupt\*(C'\fR and \f(CW\*(C`isr\*(C'\fR function attributes. +.IP "\fB\-mmp\fR" 4 +.IX Item "-mmp" +Enable multiprocessor instructions; the default is off. +.IP "\fB\-mcp\fR" 4 +.IX Item "-mcp" +Enable coprocessor instructions; the default is off. +.IP "\fB\-mcache\fR" 4 +.IX Item "-mcache" +Enable coprocessor instructions; the default is off. +.IP "\fB\-msecurity\fR" 4 +.IX Item "-msecurity" +Enable C\-SKY security instructions; the default is off. +.IP "\fB\-mtrust\fR" 4 +.IX Item "-mtrust" +Enable C\-SKY trust instructions; the default is off. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-medsp\fR" 4 +.IX Item "-medsp" +.IP "\fB\-mvdsp\fR" 4 +.IX Item "-mvdsp" +.PD +Enable C\-SKY \s-1DSP,\s0 Enhanced \s-1DSP,\s0 or Vector \s-1DSP\s0 instructions, respectively. +All of these options default to off. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Generate divide instructions. Default is off. +.IP "\fB\-msmart\fR" 4 +.IX Item "-msmart" +.PD 0 +.IP "\fB\-mno\-smart\fR" 4 +.IX Item "-mno-smart" +.PD +Generate code for Smart Mode, using only registers numbered 0\-7 to allow +use of 16\-bit instructions. This option is ignored for \s-1CK801\s0 where this +is the required behavior, and it defaults to on for \s-1CK802.\s0 +For other targets, the default is off. +.IP "\fB\-mhigh\-registers\fR" 4 +.IX Item "-mhigh-registers" +.PD 0 +.IP "\fB\-mno\-high\-registers\fR" 4 +.IX Item "-mno-high-registers" +.PD +Generate code using the high registers numbered 16\-31. This option +is not supported on \s-1CK801, CK802,\s0 or \s-1CK803,\s0 and is enabled by default +for other processors. +.IP "\fB\-manchor\fR" 4 +.IX Item "-manchor" +.PD 0 +.IP "\fB\-mno\-anchor\fR" 4 +.IX Item "-mno-anchor" +.PD +Generate code using global anchor symbol addresses. +.IP "\fB\-mpushpop\fR" 4 +.IX Item "-mpushpop" +.PD 0 +.IP "\fB\-mno\-pushpop\fR" 4 +.IX Item "-mno-pushpop" +.PD +Generate code using \f(CW\*(C`push\*(C'\fR and \f(CW\*(C`pop\*(C'\fR instructions. This option +defaults to on. +.IP "\fB\-mmultiple\-stld\fR" 4 +.IX Item "-mmultiple-stld" +.PD 0 +.IP "\fB\-mstm\fR" 4 +.IX Item "-mstm" +.IP "\fB\-mno\-multiple\-stld\fR" 4 +.IX Item "-mno-multiple-stld" +.IP "\fB\-mno\-stm\fR" 4 +.IX Item "-mno-stm" +.PD +Generate code using \f(CW\*(C`stm\*(C'\fR and \f(CW\*(C`ldm\*(C'\fR instructions. This option +isn't supported on \s-1CK801\s0 but is enabled by default on other processors. +.IP "\fB\-mconstpool\fR" 4 +.IX Item "-mconstpool" +.PD 0 +.IP "\fB\-mno\-constpool\fR" 4 +.IX Item "-mno-constpool" +.PD +Create constant pools in the compiler instead of deferring it to the +assembler. This option is the default and required for correct code +generation on \s-1CK801\s0 and \s-1CK802,\s0 and is optional on other processors. +.IP "\fB\-mstack\-size\fR" 4 +.IX Item "-mstack-size" +.PD 0 +.IP "\fB\-mno\-stack\-size\fR" 4 +.IX Item "-mno-stack-size" +.PD +Emit \f(CW\*(C`.stack_size\*(C'\fR directives for each function in the assembly +output. This option defaults to off. +.IP "\fB\-mccrt\fR" 4 +.IX Item "-mccrt" +.PD 0 +.IP "\fB\-mno\-ccrt\fR" 4 +.IX Item "-mno-ccrt" +.PD +Generate code for the C\-SKY compiler runtime instead of libgcc. This +option defaults to off. +.IP "\fB\-mbranch\-cost=\fR\fIn\fR" 4 +.IX Item "-mbranch-cost=n" +Set the branch costs to roughly \f(CW\*(C`n\*(C'\fR instructions. The default is 1. +.IP "\fB\-msched\-prolog\fR" 4 +.IX Item "-msched-prolog" +.PD 0 +.IP "\fB\-mno\-sched\-prolog\fR" 4 +.IX Item "-mno-sched-prolog" +.PD +Permit scheduling of function prologue and epilogue sequences. Using +this option can result in code that is not compliant with the C\-SKY V2 \s-1ABI\s0 +prologue requirements and that cannot be debugged or backtraced. +It is disabled by default. +.PP +\fIDarwin Options\fR +.IX Subsection "Darwin Options" +.PP +These options are defined for all architectures running the Darwin operating +system. +.PP +\&\s-1FSF GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates +an object file for the single architecture that \s-1GCC\s0 was built to +target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple +\&\fB\-arch\fR options are used; it does so by running the compiler or +linker multiple times and joining the results together with +\&\fIlipo\fR. +.PP +The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or +\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0 +that \s-1GCC\s0 is targeting, like \fB\-mcpu\fR or \fB\-march\fR. The +\&\fB\-force_cpusubtype_ALL\fR option can be used to override this. +.PP +The Darwin tools vary in their behavior when presented with an \s-1ISA\s0 +mismatch. The assembler, \fIas\fR, only permits instructions to +be used that are valid for the subtype of the file it is generating, +so you cannot put 64\-bit instructions in a \fBppc750\fR object file. +The linker for shared libraries, \fI/usr/bin/libtool\fR, fails +and prints an error if asked to create a shared library with a less +restrictive subtype than its input files (for instance, trying to put +a \fBppc970\fR object file in a \fBppc7400\fR library). The linker +for executables, \fBld\fR, quietly gives the executable the most +restrictive subtype of any of its input files. +.IP "\fB\-F\fR\fIdir\fR" 4 +.IX Item "-Fdir" +Add the framework directory \fIdir\fR to the head of the list of +directories to be searched for header files. These directories are +interleaved with those specified by \fB\-I\fR options and are +scanned in a left-to-right order. +.Sp +A framework directory is a directory with frameworks in it. A +framework is a directory with a \fIHeaders\fR and/or +\&\fIPrivateHeaders\fR directory contained directly in it that ends +in \fI.framework\fR. The name of a framework is the name of this +directory excluding the \fI.framework\fR. Headers associated with +the framework are found in one of those two directories, with +\&\fIHeaders\fR being searched first. A subframework is a framework +directory that is in a framework's \fIFrameworks\fR directory. +Includes of subframework headers can only appear in a header of a +framework that contains the subframework, or in a sibling subframework +header. Two subframeworks are siblings if they occur in the same +framework. A subframework should not have the same name as a +framework; a warning is issued if this is violated. Currently a +subframework cannot have subframeworks; in the future, the mechanism +may be extended to support this. The standard frameworks can be found +in \fI/System/Library/Frameworks\fR and +\&\fI/Library/Frameworks\fR. An example include looks like +\&\f(CW\*(C`#include \*(C'\fR, where \fIFramework\fR denotes +the name of the framework and \fIheader.h\fR is found in the +\&\fIPrivateHeaders\fR or \fIHeaders\fR directory. +.IP "\fB\-iframework\fR\fIdir\fR" 4 +.IX Item "-iframeworkdir" +Like \fB\-F\fR except the directory is a treated as a system +directory. The main difference between this \fB\-iframework\fR and +\&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not +warn about constructs contained within header files found via +\&\fIdir\fR. This option is valid only for the C family of languages. +.IP "\fB\-gused\fR" 4 +.IX Item "-gused" +Emit debugging information for symbols that are used. For stabs +debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. +This is by default \s-1ON.\s0 +.IP "\fB\-gfull\fR" 4 +.IX Item "-gfull" +Emit debugging information for all symbols and types. +.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4 +.IX Item "-mmacosx-version-min=version" +The earliest version of MacOS X that this executable will run on +is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR, +\&\f(CW10.2\fR, and \f(CW10.3.9\fR. +.Sp +If the compiler was built to use the system's headers by default, +then the default for this option is the system version on which the +compiler is running, otherwise the default is to make choices that +are compatible with as many systems and code bases as possible. +.IP "\fB\-mkernel\fR" 4 +.IX Item "-mkernel" +Enable kernel development mode. The \fB\-mkernel\fR option sets +\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-use\-cxa\-atexit\fR, +\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR, +\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where +applicable. This mode also sets \fB\-mno\-altivec\fR, +\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and +\&\fB\-mlong\-branch\fR for PowerPC targets. +.IP "\fB\-mone\-byte\-bool\fR" 4 +.IX Item "-mone-byte-bool" +Override the defaults for \f(CW\*(C`bool\*(C'\fR so that \f(CW\*(C`sizeof(bool)==1\*(C'\fR. +By default \f(CW\*(C`sizeof(bool)\*(C'\fR is \f(CW4\fR when compiling for +Darwin/PowerPC and \f(CW1\fR when compiling for Darwin/x86, so this +option has no effect on x86. +.Sp +\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0 +to generate code that is not binary compatible with code generated +without that switch. Using this switch may require recompiling all +other modules in a program, including system libraries. Use this +switch to conform to a non-default data model. +.IP "\fB\-mfix\-and\-continue\fR" 4 +.IX Item "-mfix-and-continue" +.PD 0 +.IP "\fB\-ffix\-and\-continue\fR" 4 +.IX Item "-ffix-and-continue" +.IP "\fB\-findirect\-data\fR" 4 +.IX Item "-findirect-data" +.PD +Generate code suitable for fast turnaround development, such as to +allow \s-1GDB\s0 to dynamically load \fI.o\fR files into already-running +programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR +are provided for backwards compatibility. +.IP "\fB\-all_load\fR" 4 +.IX Item "-all_load" +Loads all members of static archive libraries. +See man \fBld\fR\|(1) for more information. +.IP "\fB\-arch_errors_fatal\fR" 4 +.IX Item "-arch_errors_fatal" +Cause the errors having to do with files that have the wrong architecture +to be fatal. +.IP "\fB\-bind_at_load\fR" 4 +.IX Item "-bind_at_load" +Causes the output file to be marked such that the dynamic linker will +bind all undefined references when the file is loaded or launched. +.IP "\fB\-bundle\fR" 4 +.IX Item "-bundle" +Produce a Mach-o bundle format file. +See man \fBld\fR\|(1) for more information. +.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4 +.IX Item "-bundle_loader executable" +This option specifies the \fIexecutable\fR that will load the build +output file being linked. See man \fBld\fR\|(1) for more information. +.IP "\fB\-dynamiclib\fR" 4 +.IX Item "-dynamiclib" +When passed this option, \s-1GCC\s0 produces a dynamic library instead of +an executable when linking, using the Darwin \fIlibtool\fR command. +.IP "\fB\-force_cpusubtype_ALL\fR" 4 +.IX Item "-force_cpusubtype_ALL" +This causes \s-1GCC\s0's output file to have the \fB\s-1ALL\s0\fR subtype, instead of +one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. +.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 +.IX Item "-allowable_client client_name" +.PD 0 +.IP "\fB\-client_name\fR" 4 +.IX Item "-client_name" +.IP "\fB\-compatibility_version\fR" 4 +.IX Item "-compatibility_version" +.IP "\fB\-current_version\fR" 4 +.IX Item "-current_version" +.IP "\fB\-dead_strip\fR" 4 +.IX Item "-dead_strip" +.IP "\fB\-dependency\-file\fR" 4 +.IX Item "-dependency-file" +.IP "\fB\-dylib_file\fR" 4 +.IX Item "-dylib_file" +.IP "\fB\-dylinker_install_name\fR" 4 +.IX Item "-dylinker_install_name" +.IP "\fB\-dynamic\fR" 4 +.IX Item "-dynamic" +.IP "\fB\-exported_symbols_list\fR" 4 +.IX Item "-exported_symbols_list" +.IP "\fB\-filelist\fR" 4 +.IX Item "-filelist" +.IP "\fB\-flat_namespace\fR" 4 +.IX Item "-flat_namespace" +.IP "\fB\-force_flat_namespace\fR" 4 +.IX Item "-force_flat_namespace" +.IP "\fB\-headerpad_max_install_names\fR" 4 +.IX Item "-headerpad_max_install_names" +.IP "\fB\-image_base\fR" 4 +.IX Item "-image_base" +.IP "\fB\-init\fR" 4 +.IX Item "-init" +.IP "\fB\-install_name\fR" 4 +.IX Item "-install_name" +.IP "\fB\-keep_private_externs\fR" 4 +.IX Item "-keep_private_externs" +.IP "\fB\-multi_module\fR" 4 +.IX Item "-multi_module" +.IP "\fB\-multiply_defined\fR" 4 +.IX Item "-multiply_defined" +.IP "\fB\-multiply_defined_unused\fR" 4 +.IX Item "-multiply_defined_unused" +.IP "\fB\-noall_load\fR" 4 +.IX Item "-noall_load" +.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4 +.IX Item "-no_dead_strip_inits_and_terms" +.IP "\fB\-nofixprebinding\fR" 4 +.IX Item "-nofixprebinding" +.IP "\fB\-nomultidefs\fR" 4 +.IX Item "-nomultidefs" +.IP "\fB\-noprebind\fR" 4 +.IX Item "-noprebind" +.IP "\fB\-noseglinkedit\fR" 4 +.IX Item "-noseglinkedit" +.IP "\fB\-pagezero_size\fR" 4 +.IX Item "-pagezero_size" +.IP "\fB\-prebind\fR" 4 +.IX Item "-prebind" +.IP "\fB\-prebind_all_twolevel_modules\fR" 4 +.IX Item "-prebind_all_twolevel_modules" +.IP "\fB\-private_bundle\fR" 4 +.IX Item "-private_bundle" +.IP "\fB\-read_only_relocs\fR" 4 +.IX Item "-read_only_relocs" +.IP "\fB\-sectalign\fR" 4 +.IX Item "-sectalign" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-whyload\fR" 4 +.IX Item "-whyload" +.IP "\fB\-seg1addr\fR" 4 +.IX Item "-seg1addr" +.IP "\fB\-sectcreate\fR" 4 +.IX Item "-sectcreate" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-sectorder\fR" 4 +.IX Item "-sectorder" +.IP "\fB\-segaddr\fR" 4 +.IX Item "-segaddr" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-seg_addr_table\fR" 4 +.IX Item "-seg_addr_table" +.IP "\fB\-seg_addr_table_filename\fR" 4 +.IX Item "-seg_addr_table_filename" +.IP "\fB\-seglinkedit\fR" 4 +.IX Item "-seglinkedit" +.IP "\fB\-segprot\fR" 4 +.IX Item "-segprot" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-single_module\fR" 4 +.IX Item "-single_module" +.IP "\fB\-static\fR" 4 +.IX Item "-static" +.IP "\fB\-sub_library\fR" 4 +.IX Item "-sub_library" +.IP "\fB\-sub_umbrella\fR" 4 +.IX Item "-sub_umbrella" +.IP "\fB\-twolevel_namespace\fR" 4 +.IX Item "-twolevel_namespace" +.IP "\fB\-umbrella\fR" 4 +.IX Item "-umbrella" +.IP "\fB\-undefined\fR" 4 +.IX Item "-undefined" +.IP "\fB\-unexported_symbols_list\fR" 4 +.IX Item "-unexported_symbols_list" +.IP "\fB\-weak_reference_mismatches\fR" 4 +.IX Item "-weak_reference_mismatches" +.IP "\fB\-whatsloaded\fR" 4 +.IX Item "-whatsloaded" +.PD +These options are passed to the Darwin linker. The Darwin linker man page +describes them in detail. +.PP +\fI\s-1DEC\s0 Alpha Options\fR +.IX Subsection "DEC Alpha Options" +.PP +These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations: +.IP "\fB\-mno\-soft\-float\fR" 4 +.IX Item "-mno-soft-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions for +floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR are used to perform floating-point +operations. Unless they are replaced by routines that emulate the +floating-point operations, or compiled in such a way as to call such +emulations routines, these routines issue floating-point +operations. If you are compiling for an Alpha without floating-point +operations, you must ensure that the library is built so as not to call +them. +.Sp +Note that Alpha implementations without floating-point operations are +required to have floating-point registers. +.IP "\fB\-mfp\-reg\fR" 4 +.IX Item "-mfp-reg" +.PD 0 +.IP "\fB\-mno\-fp\-regs\fR" 4 +.IX Item "-mno-fp-regs" +.PD +Generate code that uses (does not use) the floating-point register set. +\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point +register set is not used, floating-point operands are passed in integer +registers as if they were integers and floating-point results are passed +in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence, +so any function with a floating-point argument or return value called by code +compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that +option. +.Sp +A typical use of this option is building a kernel that does not use, +and hence need not save and restore, any floating-point registers. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +The Alpha architecture implements floating-point hardware optimized for +maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating-point +standard. However, for full compliance, software assistance is +required. This option generates code fully IEEE-compliant code +\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below). +If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is +defined during compilation. The resulting code is less efficient but is +able to correctly support denormalized numbers and exceptional \s-1IEEE\s0 +values such as not-a-number and plus/minus infinity. Other Alpha +compilers call this option \fB\-ieee_with_no_inexact\fR. +.IP "\fB\-mieee\-with\-inexact\fR" 4 +.IX Item "-mieee-with-inexact" +This is like \fB\-mieee\fR except the generated code also maintains +the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the +generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to +\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor +macro. On some Alpha implementations the resulting code may execute +significantly slower than the code generated by default. Since there is +very little code that depends on the \fIinexact-flag\fR, you should +normally not specify this option. Other Alpha compilers call this +option \fB\-ieee_with_inexact\fR. +.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4 +.IX Item "-mfp-trap-mode=trap-mode" +This option controls what floating-point related traps are enabled. +Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR. +The trap mode can be set to one of four values: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +This is the default (normal) setting. The only traps that are enabled +are the ones that cannot be disabled in software (e.g., division by zero +trap). +.IP "\fBu\fR" 4 +.IX Item "u" +In addition to the traps enabled by \fBn\fR, underflow traps are enabled +as well. +.IP "\fBsu\fR" 4 +.IX Item "su" +Like \fBu\fR, but the instructions are marked to be safe for software +completion (see Alpha architecture manual for details). +.IP "\fBsui\fR" 4 +.IX Item "sui" +Like \fBsu\fR, but inexact traps are enabled as well. +.RE +.RS 4 +.RE +.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4 +.IX Item "-mfp-rounding-mode=rounding-mode" +Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option +\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one +of: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +Normal \s-1IEEE\s0 rounding mode. Floating-point numbers are rounded towards +the nearest machine number or towards the even machine number in case +of a tie. +.IP "\fBm\fR" 4 +.IX Item "m" +Round towards minus infinity. +.IP "\fBc\fR" 4 +.IX Item "c" +Chopped rounding mode. Floating-point numbers are rounded towards zero. +.IP "\fBd\fR" 4 +.IX Item "d" +Dynamic rounding mode. A field in the floating-point control register +(\fIfpcr\fR, see Alpha architecture reference manual) controls the +rounding mode in effect. The C library initializes this register for +rounding towards plus infinity. Thus, unless your program modifies the +\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity. +.RE +.RS 4 +.RE +.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4 +.IX Item "-mtrap-precision=trap-precision" +In the Alpha architecture, floating-point traps are imprecise. This +means without software assistance it is impossible to recover from a +floating trap and program execution normally needs to be terminated. +\&\s-1GCC\s0 can generate code that can assist operating system trap handlers +in determining the exact location that caused a floating-point trap. +Depending on the requirements of an application, different levels of +precisions can be selected: +.RS 4 +.IP "\fBp\fR" 4 +.IX Item "p" +Program precision. This option is the default and means a trap handler +can only identify which program caused a floating-point exception. +.IP "\fBf\fR" 4 +.IX Item "f" +Function precision. The trap handler can determine the function that +caused a floating-point exception. +.IP "\fBi\fR" 4 +.IX Item "i" +Instruction precision. The trap handler can determine the exact +instruction that caused a floating-point exception. +.RE +.RS 4 +.Sp +Other Alpha compilers provide the equivalent options called +\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR. +.RE +.IP "\fB\-mieee\-conformant\fR" 4 +.IX Item "-mieee-conformant" +This option marks the generated code as \s-1IEEE\s0 conformant. You must not +use this option unless you also specify \fB\-mtrap\-precision=i\fR and either +\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect +is to emit the line \fB.eflag 48\fR in the function prologue of the +generated assembly file. +.IP "\fB\-mbuild\-constants\fR" 4 +.IX Item "-mbuild-constants" +Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to +see if it can construct it from smaller constants in two or three +instructions. If it cannot, it outputs the constant as a literal and +generates code to load it from the data segment at run time. +.Sp +Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants +using code, even if it takes more instructions (the maximum is six). +.Sp +You typically use this option to build a shared library dynamic +loader. Itself a shared library, it must relocate itself in memory +before it can find the variables and constants in its own data segment. +.IP "\fB\-mbwx\fR" 4 +.IX Item "-mbwx" +.PD 0 +.IP "\fB\-mno\-bwx\fR" 4 +.IX Item "-mno-bwx" +.IP "\fB\-mcix\fR" 4 +.IX Item "-mcix" +.IP "\fB\-mno\-cix\fR" 4 +.IX Item "-mno-cix" +.IP "\fB\-mfix\fR" 4 +.IX Item "-mfix" +.IP "\fB\-mno\-fix\fR" 4 +.IX Item "-mno-fix" +.IP "\fB\-mmax\fR" 4 +.IX Item "-mmax" +.IP "\fB\-mno\-max\fR" 4 +.IX Item "-mno-max" +.PD +Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX, +CIX, FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction +sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that +of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified. +.IP "\fB\-mfloat\-vax\fR" 4 +.IX Item "-mfloat-vax" +.PD 0 +.IP "\fB\-mfloat\-ieee\fR" 4 +.IX Item "-mfloat-ieee" +.PD +Generate code that uses (does not use) \s-1VAX F\s0 and G floating-point +arithmetic instead of \s-1IEEE\s0 single and double precision. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Older Alpha assemblers provided no way to generate symbol relocations +except via assembler macros. Use of these macros does not allow +optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12 +supports a new syntax that allows the compiler to explicitly mark +which relocations should apply to which instructions. This option +is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of +the assembler when it is built and sets the default accordingly. +.IP "\fB\-msmall\-data\fR" 4 +.IX Item "-msmall-data" +.PD 0 +.IP "\fB\-mlarge\-data\fR" 4 +.IX Item "-mlarge-data" +.PD +When \fB\-mexplicit\-relocs\fR is in effect, static data is +accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR +is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR +(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via +16\-bit relocations off of the \f(CW$gp\fR register. This limits the +size of the small data area to 64KB, but allows the variables to be +directly accessed via a single instruction. +.Sp +The default is \fB\-mlarge\-data\fR. With this option the data area +is limited to just below 2GB. Programs that require more than 2GB of +data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the +heap instead of in the program's data segment. +.Sp +When generating code for shared libraries, \fB\-fpic\fR implies +\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR. +.IP "\fB\-msmall\-text\fR" 4 +.IX Item "-msmall-text" +.PD 0 +.IP "\fB\-mlarge\-text\fR" 4 +.IX Item "-mlarge-text" +.PD +When \fB\-msmall\-text\fR is used, the compiler assumes that the +code of the entire program (or shared library) fits in 4MB, and is +thus reachable with a branch instruction. When \fB\-msmall\-data\fR +is used, the compiler can assume that all local symbols share the +same \f(CW$gp\fR value, and thus reduce the number of instructions +required for a function call from 4 to 1. +.Sp +The default is \fB\-mlarge\-text\fR. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set and instruction scheduling parameters for +machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR +style name or the corresponding chip number. \s-1GCC\s0 supports scheduling +parameters for the \s-1EV4, EV5\s0 and \s-1EV6\s0 family of processors and +chooses the default values for the instruction set from the processor +you specify. If you do not specify a processor type, \s-1GCC\s0 defaults +to the processor on which the compiler was built. +.Sp +Supported values for \fIcpu_type\fR are +.RS 4 +.IP "\fBev4\fR" 4 +.IX Item "ev4" +.PD 0 +.IP "\fBev45\fR" 4 +.IX Item "ev45" +.IP "\fB21064\fR" 4 +.IX Item "21064" +.PD +Schedules as an \s-1EV4\s0 and has no instruction set extensions. +.IP "\fBev5\fR" 4 +.IX Item "ev5" +.PD 0 +.IP "\fB21164\fR" 4 +.IX Item "21164" +.PD +Schedules as an \s-1EV5\s0 and has no instruction set extensions. +.IP "\fBev56\fR" 4 +.IX Item "ev56" +.PD 0 +.IP "\fB21164a\fR" 4 +.IX Item "21164a" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension. +.IP "\fBpca56\fR" 4 +.IX Item "pca56" +.PD 0 +.IP "\fB21164pc\fR" 4 +.IX Item "21164pc" +.IP "\fB21164PC\fR" 4 +.IX Item "21164PC" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions. +.IP "\fBev6\fR" 4 +.IX Item "ev6" +.PD 0 +.IP "\fB21264\fR" 4 +.IX Item "21264" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX, FIX,\s0 and \s-1MAX\s0 extensions. +.IP "\fBev67\fR" 4 +.IX Item "ev67" +.PD 0 +.IP "\fB21264a\fR" 4 +.IX Item "21264a" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX, CIX, FIX,\s0 and \s-1MAX\s0 extensions. +.RE +.RS 4 +.Sp +Native toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.RE +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set only the instruction scheduling parameters for machine type +\&\fIcpu_type\fR. The instruction set is not changed. +.Sp +Native toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mtune=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4 +.IX Item "-mmemory-latency=time" +Sets the latency the scheduler should assume for typical memory +references as seen by the application. This number is highly +dependent on the memory access patterns used by the application +and the size of the external cache on the machine. +.Sp +Valid options for \fItime\fR are +.RS 4 +.IP "\fInumber\fR" 4 +.IX Item "number" +A decimal number representing clock cycles. +.IP "\fBL1\fR" 4 +.IX Item "L1" +.PD 0 +.IP "\fBL2\fR" 4 +.IX Item "L2" +.IP "\fBL3\fR" 4 +.IX Item "L3" +.IP "\fBmain\fR" 4 +.IX Item "main" +.PD +The compiler contains estimates of the number of clock cycles for +\&\*(L"typical\*(R" \s-1EV4 & EV5\s0 hardware for the Level 1, 2 & 3 caches +(also called Dcache, Scache, and Bcache), as well as to main memory. +Note that L3 is only valid for \s-1EV5.\s0 +.RE +.RS 4 +.RE +.PP +\fI\s-1FR30\s0 Options\fR +.IX Subsection "FR30 Options" +.PP +These options are defined specifically for the \s-1FR30\s0 port. +.IP "\fB\-msmall\-model\fR" 4 +.IX Item "-msmall-model" +Use the small address space model. This can produce smaller code, but +it does assume that all symbolic values and addresses fit into a +20\-bit range. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that runtime support has been provided and so there is no need +to include the simulator library (\fIlibsim.a\fR) on the linker +command line. +.PP +\fI\s-1FT32\s0 Options\fR +.IX Subsection "FT32 Options" +.PP +These options are defined specifically for the \s-1FT32\s0 port. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +an alternate runtime startup and library to be linked. +You must not use this option when generating programs that will run on +real hardware; you must provide your own runtime library for whatever +I/O functions are needed. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Enable Local Register Allocation. This is still experimental for \s-1FT32,\s0 +so by default the compiler uses standard reload. +.IP "\fB\-mnodiv\fR" 4 +.IX Item "-mnodiv" +Do not use div and mod instructions. +.IP "\fB\-mft32b\fR" 4 +.IX Item "-mft32b" +Enable use of the extended instructions of the \s-1FT32B\s0 processor. +.IP "\fB\-mcompress\fR" 4 +.IX Item "-mcompress" +Compress all code using the Ft32B code compression scheme. +.IP "\fB\-mnopm\fR" 4 +.IX Item "-mnopm" +Do not generate code that reads program memory. +.PP +\fI\s-1FRV\s0 Options\fR +.IX Subsection "FRV Options" +.IP "\fB\-mgpr\-32\fR" 4 +.IX Item "-mgpr-32" +Only use the first 32 general-purpose registers. +.IP "\fB\-mgpr\-64\fR" 4 +.IX Item "-mgpr-64" +Use all 64 general-purpose registers. +.IP "\fB\-mfpr\-32\fR" 4 +.IX Item "-mfpr-32" +Use only the first 32 floating-point registers. +.IP "\fB\-mfpr\-64\fR" 4 +.IX Item "-mfpr-64" +Use all 64 floating-point registers. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware instructions for floating-point operations. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use library routines for floating-point operations. +.IP "\fB\-malloc\-cc\fR" 4 +.IX Item "-malloc-cc" +Dynamically allocate condition code registers. +.IP "\fB\-mfixed\-cc\fR" 4 +.IX Item "-mfixed-cc" +Do not try to dynamically allocate condition code registers, only +use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR. +.IP "\fB\-mdword\fR" 4 +.IX Item "-mdword" +Change \s-1ABI\s0 to use double word insns. +.IP "\fB\-mno\-dword\fR" 4 +.IX Item "-mno-dword" +Do not use double word instructions. +.IP "\fB\-mdouble\fR" 4 +.IX Item "-mdouble" +Use floating-point double instructions. +.IP "\fB\-mno\-double\fR" 4 +.IX Item "-mno-double" +Do not use floating-point double instructions. +.IP "\fB\-mmedia\fR" 4 +.IX Item "-mmedia" +Use media instructions. +.IP "\fB\-mno\-media\fR" 4 +.IX Item "-mno-media" +Do not use media instructions. +.IP "\fB\-mmuladd\fR" 4 +.IX Item "-mmuladd" +Use multiply and add/subtract instructions. +.IP "\fB\-mno\-muladd\fR" 4 +.IX Item "-mno-muladd" +Do not use multiply and add/subtract instructions. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Select the \s-1FDPIC ABI,\s0 which uses function descriptors to represent +pointers to functions. Without any PIC/PIE\-related options, it +implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it +assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the +\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets +are computed with 32 bits. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +It's enabled by default if optimizing for speed and compiling for +shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an +optimization option such as \fB\-O3\fR or above is present in the +command line. +.IP "\fB\-mTLS\fR" 4 +.IX Item "-mTLS" +Assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mtls\fR" 4 +.IX Item "-mtls" +Do not assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mgprel\-ro\fR" 4 +.IX Item "-mgprel-ro" +Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC ABI\s0 for data +that is known to be in read-only sections. It's enabled by default, +except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help +make the global offset table smaller, it trades 1 instruction for 4. +With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4, +one of which may be shared by multiple symbols, and it avoids the need +for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a +win. If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it. +.IP "\fB\-multilib\-library\-pic\fR" 4 +.IX Item "-multilib-library-pic" +Link with the (library, not \s-1FD\s0) pic libraries. It's implied by +\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and +\&\fB\-fpic\fR without \fB\-mfdpic\fR. You should never have to use +it explicitly. +.IP "\fB\-mlinked\-fp\fR" 4 +.IX Item "-mlinked-fp" +Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever +a stack frame is allocated. This option is enabled by default and can +be disabled with \fB\-mno\-linked\-fp\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Use indirect addressing to call functions outside the current +compilation unit. This allows the functions to be placed anywhere +within the 32\-bit address space. +.IP "\fB\-malign\-labels\fR" 4 +.IX Item "-malign-labels" +Try to align labels to an 8\-byte boundary by inserting NOPs into the +previous packet. This option only has an effect when \s-1VLIW\s0 packing +is enabled. It doesn't create new packets; it merely adds NOPs to +existing ones. +.IP "\fB\-mlibrary\-pic\fR" 4 +.IX Item "-mlibrary-pic" +Generate position-independent \s-1EABI\s0 code. +.IP "\fB\-macc\-4\fR" 4 +.IX Item "-macc-4" +Use only the first four media accumulator registers. +.IP "\fB\-macc\-8\fR" 4 +.IX Item "-macc-8" +Use all eight media accumulator registers. +.IP "\fB\-mpack\fR" 4 +.IX Item "-mpack" +Pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-pack\fR" 4 +.IX Item "-mno-pack" +Do not pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-eflags\fR" 4 +.IX Item "-mno-eflags" +Do not mark \s-1ABI\s0 switches in e_flags. +.IP "\fB\-mcond\-move\fR" 4 +.IX Item "-mcond-move" +Enable the use of conditional-move instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-move\fR" 4 +.IX Item "-mno-cond-move" +Disable the use of conditional-move instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mscc\fR" 4 +.IX Item "-mscc" +Enable the use of conditional set instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-scc\fR" 4 +.IX Item "-mno-scc" +Disable the use of conditional set instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mcond\-exec\fR" 4 +.IX Item "-mcond-exec" +Enable the use of conditional execution (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-exec\fR" 4 +.IX Item "-mno-cond-exec" +Disable the use of conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mvliw\-branch\fR" 4 +.IX Item "-mvliw-branch" +Run a pass to pack branches into \s-1VLIW\s0 instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-vliw\-branch\fR" 4 +.IX Item "-mno-vliw-branch" +Do not run a pass to pack branches into \s-1VLIW\s0 instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mmulti\-cond\-exec\fR" 4 +.IX Item "-mmulti-cond-exec" +Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution +(default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-multi\-cond\-exec\fR" 4 +.IX Item "-mno-multi-cond-exec" +Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mnested\-cond\-exec\fR" 4 +.IX Item "-mnested-cond-exec" +Enable nested conditional execution optimizations (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-nested\-cond\-exec\fR" 4 +.IX Item "-mno-nested-cond-exec" +Disable nested conditional execution optimizations. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-moptimize\-membar\fR" 4 +.IX Item "-moptimize-membar" +This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the +compiler-generated code. It is enabled by default. +.IP "\fB\-mno\-optimize\-membar\fR" 4 +.IX Item "-mno-optimize-membar" +This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR +instructions from the generated code. +.IP "\fB\-mtomcat\-stats\fR" 4 +.IX Item "-mtomcat-stats" +Cause gas to print out tomcat statistics. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Select the processor type for which to generate code. Possible values are +\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR, +\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR. +.PP +\fIGNU/Linux Options\fR +.IX Subsection "GNU/Linux Options" +.PP +These \fB\-m\fR options are defined for GNU/Linux targets: +.IP "\fB\-mglibc\fR" 4 +.IX Item "-mglibc" +Use the \s-1GNU C\s0 library. This is the default except +on \fB*\-*\-linux\-*uclibc*\fR, \fB*\-*\-linux\-*musl*\fR and +\&\fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-muclibc\fR" 4 +.IX Item "-muclibc" +Use uClibc C library. This is the default on +\&\fB*\-*\-linux\-*uclibc*\fR targets. +.IP "\fB\-mmusl\fR" 4 +.IX Item "-mmusl" +Use the musl C library. This is the default on +\&\fB*\-*\-linux\-*musl*\fR targets. +.IP "\fB\-mbionic\fR" 4 +.IX Item "-mbionic" +Use Bionic C library. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-mandroid\fR" 4 +.IX Item "-mandroid" +Compile code compatible with Android platform. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.Sp +When compiling, this option enables \fB\-mbionic\fR, \fB\-fPIC\fR, +\&\fB\-fno\-exceptions\fR and \fB\-fno\-rtti\fR by default. When linking, +this option makes the \s-1GCC\s0 driver pass Android-specific options to the linker. +Finally, this option causes the preprocessor macro \f(CW\*(C`_\|_ANDROID_\|_\*(C'\fR +to be defined. +.IP "\fB\-tno\-android\-cc\fR" 4 +.IX Item "-tno-android-cc" +Disable compilation effects of \fB\-mandroid\fR, i.e., do not enable +\&\fB\-mbionic\fR, \fB\-fPIC\fR, \fB\-fno\-exceptions\fR and +\&\fB\-fno\-rtti\fR by default. +.IP "\fB\-tno\-android\-ld\fR" 4 +.IX Item "-tno-android-ld" +Disable linking effects of \fB\-mandroid\fR, i.e., pass standard Linux +linking options to the linker. +.PP +\fIH8/300 Options\fR +.IX Subsection "H8/300 Options" +.PP +These \fB\-m\fR options are defined for the H8/300 implementations: +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mh\fR" 4 +.IX Item "-mh" +Generate code for the H8/300H. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Generate code for the H8S. +.IP "\fB\-mn\fR" 4 +.IX Item "-mn" +Generate code for the H8S and H8/300H in the normal mode. This switch +must be used either with \fB\-mh\fR or \fB\-ms\fR. +.IP "\fB\-ms2600\fR" 4 +.IX Item "-ms2600" +Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR. +.IP "\fB\-mexr\fR" 4 +.IX Item "-mexr" +Extended registers are stored on stack before execution of function +with monitor attribute. Default option is \fB\-mexr\fR. +This option is valid only for H8S targets. +.IP "\fB\-mno\-exr\fR" 4 +.IX Item "-mno-exr" +Extended registers are not stored on stack before execution of function +with monitor attribute. Default option is \fB\-mno\-exr\fR. +This option is valid only for H8S targets. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +Make \f(CW\*(C`int\*(C'\fR data 32 bits by default. +.IP "\fB\-malign\-300\fR" 4 +.IX Item "-malign-300" +On the H8/300H and H8S, use the same alignment rules as for the H8/300. +The default for the H8/300H and H8S is to align longs and floats on +4\-byte boundaries. +\&\fB\-malign\-300\fR causes them to be aligned on 2\-byte boundaries. +This option has no effect on the H8/300. +.PP +\fI\s-1HPPA\s0 Options\fR +.IX Subsection "HPPA Options" +.PP +These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA 1.0,\s0 \fB1.1\fR for \s-1PA +1.1,\s0 and \fB2.0\fR for \s-1PA 2.0\s0 processors. Refer to +\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper +architecture option for your machine. Code compiled for lower numbered +architectures runs on higher numbered architectures, but not the +other way around. +.IP "\fB\-mpa\-risc\-1\-0\fR" 4 +.IX Item "-mpa-risc-1-0" +.PD 0 +.IP "\fB\-mpa\-risc\-1\-1\fR" 4 +.IX Item "-mpa-risc-1-1" +.IP "\fB\-mpa\-risc\-2\-0\fR" 4 +.IX Item "-mpa-risc-2-0" +.PD +Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively. +.IP "\fB\-mcaller\-copies\fR" 4 +.IX Item "-mcaller-copies" +The caller copies function arguments passed by hidden reference. This +option should be used with care as it is not compatible with the default +32\-bit runtime. However, only aggregates larger than eight bytes are +passed by hidden reference and the option provides better compatibility +with OpenMP. +.IP "\fB\-mjump\-in\-delay\fR" 4 +.IX Item "-mjump-in-delay" +This option is ignored and provided for compatibility purposes only. +.IP "\fB\-mdisable\-fpregs\fR" 4 +.IX Item "-mdisable-fpregs" +Prevent floating-point registers from being used in any manner. This is +necessary for compiling kernels that perform lazy context switching of +floating-point registers. If you use this option and attempt to perform +floating-point operations, the compiler aborts. +.IP "\fB\-mdisable\-indexing\fR" 4 +.IX Item "-mdisable-indexing" +Prevent the compiler from using indexing address modes. This avoids some +rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH.\s0 +.IP "\fB\-mno\-space\-regs\fR" 4 +.IX Item "-mno-space-regs" +Generate code that assumes the target has no space registers. This allows +\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes. +.Sp +Such code is suitable for level 0 \s-1PA\s0 systems and kernels. +.IP "\fB\-mfast\-indirect\-calls\fR" 4 +.IX Item "-mfast-indirect-calls" +Generate code that assumes calls never cross space boundaries. This +allows \s-1GCC\s0 to emit code that performs faster indirect calls. +.Sp +This option does not work in the presence of shared libraries or nested +functions. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mlong\-load\-store\fR" 4 +.IX Item "-mlong-load-store" +Generate 3\-instruction load and store sequences as sometimes required by +the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to +the \s-1HP\s0 compilers. +.IP "\fB\-mportable\-runtime\fR" 4 +.IX Item "-mportable-runtime" +Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems. +.IP "\fB\-mgas\fR" 4 +.IX Item "-mgas" +Enable the use of assembler directives only \s-1GAS\s0 understands. +.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4 +.IX Item "-mschedule=cpu-type" +Schedule code according to the constraints for the machine type +\&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR +\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer +to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the +proper scheduling option for your machine. The default scheduling is +\&\fB8000\fR. +.IP "\fB\-mlinker\-opt\fR" 4 +.IX Item "-mlinker-opt" +Enable the optimization pass in the HP-UX linker. Note this makes symbolic +debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 +linkers in which they give bogus error messages when linking some programs. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-msio\fR" 4 +.IX Item "-msio" +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO.\s0 The default is +\&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO.\s0 These +options are available under HP-UX and HI-UX. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +Use options specific to \s-1GNU\s0 \fBld\fR. +This passes \fB\-shared\fR to \fBld\fR when +building a shared library. It is the default when \s-1GCC\s0 is configured, +explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not +affect which \fBld\fR is called; it only changes what parameters +are passed to that \fBld\fR. +The \fBld\fR that is called is determined by the +\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and +finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed +using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available +on the 64\-bit HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mhp\-ld\fR" 4 +.IX Item "-mhp-ld" +Use options specific to \s-1HP\s0 \fBld\fR. +This passes \fB\-b\fR to \fBld\fR when building +a shared library and passes \fB+Accept TypeMismatch\fR to \fBld\fR on all +links. It is the default when \s-1GCC\s0 is configured, explicitly or +implicitly, with the \s-1HP\s0 linker. This option does not affect +which \fBld\fR is called; it only changes what parameters are passed to that +\&\fBld\fR. +The \fBld\fR that is called is determined by the \fB\-\-with\-ld\fR +configure option, \s-1GCC\s0's program search path, and finally by the user's +\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich +`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit +HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Generate code that uses long call sequences. This ensures that a call +is always able to reach linker generated stubs. The default is to generate +long calls only when the distance from the call site to the beginning +of the function or translation unit, as the case may be, exceeds a +predefined limit set by the branch type being used. The limits for +normal calls are 7,600,000 and 240,000 bytes, respectively for the +\&\s-1PA 2.0\s0 and \s-1PA 1.X\s0 architectures. Sibcalls are always limited at +240,000 bytes. +.Sp +Distances are measured from the beginning of functions when using the +\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR +and \fB\-mno\-portable\-runtime\fR options together under HP-UX with +the \s-1SOM\s0 linker. +.Sp +It is normally not desirable to use this option as it degrades +performance. However, it may be useful in large applications, +particularly when partial linking is used to build the application. +.Sp +The types of long calls used depends on the capabilities of the +assembler and linker, and the type of code being generated. The +impact on systems that support long absolute calls, and long pic +symbol-difference or pc-relative calls should be relatively small. +However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code +and it is quite long. +.IP "\fB\-munix=\fR\fIunix-std\fR" 4 +.IX Item "-munix=unix-std" +Generate compiler predefines and select a startfile for the specified +\&\s-1UNIX\s0 standard. The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR +and \fB98\fR. \fB93\fR is supported on all HP-UX versions. \fB95\fR +is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX +11.11 and later. The default values are \fB93\fR for HP-UX 10.00, +\&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 +and later. +.Sp +\&\fB\-munix=93\fR provides the same predefines as \s-1GCC 3.3\s0 and 3.4. +\&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR +and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. +\&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, +\&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and +\&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR. +.Sp +It is \fIimportant\fR to note that this option changes the interfaces +for various library routines. It also affects the operational behavior +of the C library. Thus, \fIextreme\fR care is needed in using this +option. +.Sp +Library code that is intended to operate with more than one \s-1UNIX\s0 +standard must test, set and restore the variable \f(CW\*(C`_\|_xpg4_extended_mask\*(C'\fR +as appropriate. Most \s-1GNU\s0 software doesn't provide this capability. +.IP "\fB\-nolibdld\fR" 4 +.IX Item "-nolibdld" +Suppress the generation of link options to search libdld.sl when the +\&\fB\-static\fR option is specified on HP-UX 10 and later. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +The HP-UX implementation of setlocale in libc has a dependency on +libdld.sl. There isn't an archive version of libdld.sl. Thus, +when the \fB\-static\fR option is specified, special link options +are needed to resolve this dependency. +.Sp +On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to +link with libdld.sl when the \fB\-static\fR option is specified. +This causes the resulting binary to be dynamic. On the 64\-bit port, +the linkers generate dynamic binaries by default in any case. The +\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from +adding these link options. +.IP "\fB\-threads\fR" 4 +.IX Item "-threads" +Add support for multithreading with the \fIdce thread\fR library +under HP-UX. This option sets flags for both the preprocessor and +linker. +.PP +\fI\s-1IA\-64\s0 Options\fR +.IX Subsection "IA-64 Options" +.PP +These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. This is the default for HP-UX. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. This is the default for \s-1AIX5\s0 +and GNU/Linux. +.IP "\fB\-mgnu\-as\fR" 4 +.IX Item "-mgnu-as" +.PD 0 +.IP "\fB\-mno\-gnu\-as\fR" 4 +.IX Item "-mno-gnu-as" +.PD +Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +.PD 0 +.IP "\fB\-mno\-gnu\-ld\fR" 4 +.IX Item "-mno-gnu-ld" +.PD +Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. +.IP "\fB\-mno\-pic\fR" 4 +.IX Item "-mno-pic" +Generate code that does not use a global pointer register. The result +is not position independent code, and violates the \s-1IA\-64 ABI.\s0 +.IP "\fB\-mvolatile\-asm\-stop\fR" 4 +.IX Item "-mvolatile-asm-stop" +.PD 0 +.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 +.IX Item "-mno-volatile-asm-stop" +.PD +Generate (or don't) a stop bit immediately before and after volatile asm +statements. +.IP "\fB\-mregister\-names\fR" 4 +.IX Item "-mregister-names" +.PD 0 +.IP "\fB\-mno\-register\-names\fR" 4 +.IX Item "-mno-register-names" +.PD +Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for +the stacked registers. This may make assembler output more readable. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +Disable (or enable) optimizations that use the small data section. This may +be useful for working around optimizer bugs. +.IP "\fB\-mconstant\-gp\fR" 4 +.IX Item "-mconstant-gp" +Generate code that uses a single constant global pointer value. This is +useful when compiling kernel code. +.IP "\fB\-mauto\-pic\fR" 4 +.IX Item "-mauto-pic" +Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. +This is useful when compiling firmware code. +.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 +.IX Item "-minline-float-divide-min-latency" +Generate code for inline divides of floating-point values +using the minimum latency algorithm. +.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-float-divide-max-throughput" +Generate code for inline divides of floating-point values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-float\-divide\fR" 4 +.IX Item "-mno-inline-float-divide" +Do not generate inline code for divides of floating-point values. +.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 +.IX Item "-minline-int-divide-min-latency" +Generate code for inline divides of integer values +using the minimum latency algorithm. +.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-int-divide-max-throughput" +Generate code for inline divides of integer values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-int\-divide\fR" 4 +.IX Item "-mno-inline-int-divide" +Do not generate inline code for divides of integer values. +.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 +.IX Item "-minline-sqrt-min-latency" +Generate code for inline square roots +using the minimum latency algorithm. +.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 +.IX Item "-minline-sqrt-max-throughput" +Generate code for inline square roots +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-sqrt\fR" 4 +.IX Item "-mno-inline-sqrt" +Do not generate inline code for \f(CW\*(C`sqrt\*(C'\fR. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mno\-dwarf2\-asm\fR" 4 +.IX Item "-mno-dwarf2-asm" +.PD 0 +.IP "\fB\-mdwarf2\-asm\fR" 4 +.IX Item "-mdwarf2-asm" +.PD +Don't (or do) generate assembler code for the \s-1DWARF\s0 line number debugging +info. This may be useful when not using the \s-1GNU\s0 assembler. +.IP "\fB\-mearly\-stop\-bits\fR" 4 +.IX Item "-mearly-stop-bits" +.PD 0 +.IP "\fB\-mno\-early\-stop\-bits\fR" 4 +.IX Item "-mno-early-stop-bits" +.PD +Allow stop bits to be placed earlier than immediately preceding the +instruction that triggered the stop bit. This can improve instruction +scheduling, but does not always do so. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 +.IX Item "-mtls-size=tls-size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and +64. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune the instruction scheduling for a particular \s-1CPU,\s0 Valid values are +\&\fBitanium\fR, \fBitanium1\fR, \fBmerced\fR, \fBitanium2\fR, +and \fBmckinley\fR. +.IP "\fB\-milp32\fR" 4 +.IX Item "-milp32" +.PD 0 +.IP "\fB\-mlp64\fR" 4 +.IX Item "-mlp64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. These are HP-UX specific flags. +.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-data-spec" +.PD 0 +.IP "\fB\-msched\-br\-data\-spec\fR" 4 +.IX Item "-msched-br-data-spec" +.PD +(Dis/En)able data speculative scheduling before reload. +This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and +the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). +The default setting is disabled. +.IP "\fB\-msched\-ar\-data\-spec\fR" 4 +.IX Item "-msched-ar-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-data-spec" +.PD +(En/Dis)able data speculative scheduling after reload. +This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and +the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). +The default setting is enabled. +.IP "\fB\-mno\-sched\-control\-spec\fR" 4 +.IX Item "-mno-sched-control-spec" +.PD 0 +.IP "\fB\-msched\-control\-spec\fR" 4 +.IX Item "-msched-control-spec" +.PD +(Dis/En)able control speculative scheduling. This feature is +available only during region scheduling (i.e. before reload). +This results in generation of the \f(CW\*(C`ld.s\*(C'\fR instructions and +the corresponding check instructions \f(CW\*(C`chk.s\*(C'\fR. +The default setting is disabled. +.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 +.IX Item "-msched-br-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads before reload. +This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. +The default setting is enabled. +.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-msched-ar-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads after reload. +This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled. +The default setting is enabled. +.IP "\fB\-msched\-in\-control\-spec\fR" 4 +.IX Item "-msched-in-control-spec" +.PD 0 +.IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4 +.IX Item "-mno-sched-in-control-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the control speculative loads. +This is effective only with \fB\-msched\-control\-spec\fR enabled. +The default setting is enabled. +.IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-data-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-data-spec-insns" +.PD +If enabled, data-speculative instructions are chosen for schedule +only if there are no other choices at the moment. This makes +the use of the data speculation much more conservative. +The default setting is disabled. +.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-control-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-control-spec-insns" +.PD +If enabled, control-speculative instructions are chosen for schedule +only if there are no other choices at the moment. This makes +the use of the control speculation much more conservative. +The default setting is disabled. +.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-mno-sched-count-spec-in-critical-path" +.PD 0 +.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-msched-count-spec-in-critical-path" +.PD +If enabled, speculative dependencies are considered during +computation of the instructions priorities. This makes the use of the +speculation a bit more conservative. +The default setting is disabled. +.IP "\fB\-msched\-spec\-ldc\fR" 4 +.IX Item "-msched-spec-ldc" +Use a simple data speculation check. This option is on by default. +.IP "\fB\-msched\-control\-spec\-ldc\fR" 4 +.IX Item "-msched-control-spec-ldc" +Use a simple check for control speculation. This option is on by default. +.IP "\fB\-msched\-stop\-bits\-after\-every\-cycle\fR" 4 +.IX Item "-msched-stop-bits-after-every-cycle" +Place a stop bit after every cycle when scheduling. This option is on +by default. +.IP "\fB\-msched\-fp\-mem\-deps\-zero\-cost\fR" 4 +.IX Item "-msched-fp-mem-deps-zero-cost" +Assume that floating-point stores and loads are not likely to cause a conflict +when placed into the same instruction group. This option is disabled by +default. +.IP "\fB\-msel\-sched\-dont\-check\-control\-spec\fR" 4 +.IX Item "-msel-sched-dont-check-control-spec" +Generate checks for control speculation in selective scheduling. +This flag is disabled by default. +.IP "\fB\-msched\-max\-memory\-insns=\fR\fImax-insns\fR" 4 +.IX Item "-msched-max-memory-insns=max-insns" +Limit on the number of memory insns per instruction group, giving lower +priority to subsequent memory insns attempting to schedule in the same +instruction group. Frequently useful to prevent cache bank conflicts. +The default value is 1. +.IP "\fB\-msched\-max\-memory\-insns\-hard\-limit\fR" 4 +.IX Item "-msched-max-memory-insns-hard-limit" +Makes the limit specified by \fBmsched-max-memory-insns\fR a hard limit, +disallowing more than that number in an instruction group. +Otherwise, the limit is \*(L"soft\*(R", meaning that non-memory operations +are preferred when the limit is reached, but memory operations may still +be scheduled. +.PP +\fI\s-1LM32\s0 Options\fR +.IX Subsection "LM32 Options" +.PP +These \fB\-m\fR options are defined for the LatticeMico32 architecture: +.IP "\fB\-mbarrel\-shift\-enabled\fR" 4 +.IX Item "-mbarrel-shift-enabled" +Enable barrel-shift instructions. +.IP "\fB\-mdivide\-enabled\fR" 4 +.IX Item "-mdivide-enabled" +Enable divide and modulus instructions. +.IP "\fB\-mmultiply\-enabled\fR" 4 +.IX Item "-mmultiply-enabled" +Enable multiply instructions. +.IP "\fB\-msign\-extend\-enabled\fR" 4 +.IX Item "-msign-extend-enabled" +Enable sign extend instructions. +.IP "\fB\-muser\-enabled\fR" 4 +.IX Item "-muser-enabled" +Enable user-defined instructions. +.PP +\fIM32C Options\fR +.IX Subsection "M32C Options" +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Select the \s-1CPU\s0 for which code is generated. \fIname\fR may be one of +\&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to +/60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for +the M32C/80 series. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +an alternate runtime library to be linked in which supports, for +example, file I/O. You must not use this option when generating +programs that will run on real hardware; you must provide your own +runtime library for whatever I/O functions are needed. +.IP "\fB\-memregs=\fR\fInumber\fR" 4 +.IX Item "-memregs=number" +Specifies the number of memory-based pseudo-registers \s-1GCC\s0 uses +during code generation. These pseudo-registers are used like real +registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the +code into available registers, and the performance penalty of using +memory instead of registers. Note that all modules in a program must +be compiled with the same value for this option. Because of that, you +must not use this option with \s-1GCC\s0's default runtime libraries. +.PP +\fIM32R/D Options\fR +.IX Subsection "M32R/D Options" +.PP +These \fB\-m\fR options are defined for Renesas M32R/D architectures: +.IP "\fB\-m32r2\fR" 4 +.IX Item "-m32r2" +Generate code for the M32R/2. +.IP "\fB\-m32rx\fR" 4 +.IX Item "-m32rx" +Generate code for the M32R/X. +.IP "\fB\-m32r\fR" 4 +.IX Item "-m32r" +Generate code for the M32R. This is the default. +.IP "\fB\-mmodel=small\fR" 4 +.IX Item "-mmodel=small" +Assume all objects live in the lower 16MB of memory (so that their addresses +can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines +are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +This is the default. +.Sp +The addressability of a particular object can be set with the +\&\f(CW\*(C`model\*(C'\fR attribute. +.IP "\fB\-mmodel=medium\fR" 4 +.IX Item "-mmodel=medium" +Assume objects may be anywhere in the 32\-bit address space (the compiler +generates \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +.IP "\fB\-mmodel=large\fR" 4 +.IX Item "-mmodel=large" +Assume objects may be anywhere in the 32\-bit address space (the compiler +generates \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction +(the compiler generates the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR +instruction sequence). +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +Disable use of the small data area. Variables are put into +one of \f(CW\*(C`.data\*(C'\fR, \f(CW\*(C`.bss\*(C'\fR, or \f(CW\*(C`.rodata\*(C'\fR (unless the +\&\f(CW\*(C`section\*(C'\fR attribute has been specified). +This is the default. +.Sp +The small data area consists of sections \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR. +Objects may be explicitly put in the small data area with the +\&\f(CW\*(C`section\*(C'\fR attribute using one of these sections. +.IP "\fB\-msdata=sdata\fR" 4 +.IX Item "-msdata=sdata" +Put small global and static data in the small data area, but do not +generate special code to reference them. +.IP "\fB\-msdata=use\fR" 4 +.IX Item "-msdata=use" +Put small global and static data in the small data area, and generate +special instructions to reference them. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put global and static objects less than or equal to \fInum\fR bytes +into the small data or \s-1BSS\s0 sections instead of the normal data or \s-1BSS\s0 +sections. The default value of \fInum\fR is 8. +The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR +for this option to have any effect. +.Sp +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +Compiling with different values of \fInum\fR may or may not work; if it +doesn't the linker gives an error message\-\-\-incorrect code is not +generated. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +Makes the M32R\-specific code in the compiler display some statistics +that might help in debugging programs. +.IP "\fB\-malign\-loops\fR" 4 +.IX Item "-malign-loops" +Align all loops to a 32\-byte boundary. +.IP "\fB\-mno\-align\-loops\fR" 4 +.IX Item "-mno-align-loops" +Do not enforce a 32\-byte alignment for loops. This is the default. +.IP "\fB\-missue\-rate=\fR\fInumber\fR" 4 +.IX Item "-missue-rate=number" +Issue \fInumber\fR instructions per cycle. \fInumber\fR can only be 1 +or 2. +.IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4 +.IX Item "-mbranch-cost=number" +\&\fInumber\fR can only be 1 or 2. If it is 1 then branches are +preferred over conditional code, if it is 2, then the opposite applies. +.IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4 +.IX Item "-mflush-trap=number" +Specifies the trap number to use to flush the cache. The default is +12. Valid numbers are between 0 and 15 inclusive. +.IP "\fB\-mno\-flush\-trap\fR" 4 +.IX Item "-mno-flush-trap" +Specifies that the cache cannot be flushed by using a trap. +.IP "\fB\-mflush\-func=\fR\fIname\fR" 4 +.IX Item "-mflush-func=name" +Specifies the name of the operating system function to call to flush +the cache. The default is \fB_flush_cache\fR, but a function call +is only used if a trap is not available. +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +Indicates that there is no \s-1OS\s0 function for flushing the cache. +.PP +\fIM680x0 Options\fR +.IX Subsection "M680x0 Options" +.PP +These are the \fB\-m\fR options defined for M680x0 and ColdFire processors. +The default settings depend on which architecture was selected when +the compiler was configured; the defaults for the most common choices +are given below. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code for a specific M680x0 or ColdFire instruction set +architecture. Permissible values of \fIarch\fR for M680x0 +architectures are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR and \fBcpu32\fR. ColdFire +architectures are selected according to Freescale's \s-1ISA\s0 classification +and the permissible values are: \fBisaa\fR, \fBisaaplus\fR, +\&\fBisab\fR and \fBisac\fR. +.Sp +\&\s-1GCC\s0 defines a macro \f(CW\*(C`_\|_mcf\f(CIarch\f(CW_\|_\*(C'\fR whenever it is generating +code for a ColdFire target. The \fIarch\fR in this macro is one of the +\&\fB\-march\fR arguments given above. +.Sp +When used together, \fB\-march\fR and \fB\-mtune\fR select code +that runs on a family of similar processors but that is optimized +for a particular microarchitecture. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Generate code for a specific M680x0 or ColdFire processor. +The M680x0 \fIcpu\fRs are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR, \fB68302\fR, \fB68332\fR +and \fBcpu32\fR. The ColdFire \fIcpu\fRs are given by the table +below, which also classifies the CPUs into families: +.RS 4 +.IP "Family : \fB\-mcpu\fR arguments" 4 +.IX Item "Family : -mcpu arguments" +.PD 0 +.IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51ag\fR \fB51cn\fR \fB51em\fR \fB51je\fR \fB51jf\fR \fB51jg\fR \fB51jm\fR \fB51mm\fR \fB51qe\fR \fB51qm\fR" 4 +.IX Item "51 : 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm" +.IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4 +.IX Item "5206 : 5202 5204 5206" +.IP "\fB5206e\fR : \fB5206e\fR" 4 +.IX Item "5206e : 5206e" +.IP "\fB5208\fR : \fB5207\fR \fB5208\fR" 4 +.IX Item "5208 : 5207 5208" +.IP "\fB5211a\fR : \fB5210a\fR \fB5211a\fR" 4 +.IX Item "5211a : 5210a 5211a" +.IP "\fB5213\fR : \fB5211\fR \fB5212\fR \fB5213\fR" 4 +.IX Item "5213 : 5211 5212 5213" +.IP "\fB5216\fR : \fB5214\fR \fB5216\fR" 4 +.IX Item "5216 : 5214 5216" +.IP "\fB52235\fR : \fB52230\fR \fB52231\fR \fB52232\fR \fB52233\fR \fB52234\fR \fB52235\fR" 4 +.IX Item "52235 : 52230 52231 52232 52233 52234 52235" +.IP "\fB5225\fR : \fB5224\fR \fB5225\fR" 4 +.IX Item "5225 : 5224 5225" +.IP "\fB52259\fR : \fB52252\fR \fB52254\fR \fB52255\fR \fB52256\fR \fB52258\fR \fB52259\fR" 4 +.IX Item "52259 : 52252 52254 52255 52256 52258 52259" +.IP "\fB5235\fR : \fB5232\fR \fB5233\fR \fB5234\fR \fB5235\fR \fB523x\fR" 4 +.IX Item "5235 : 5232 5233 5234 5235 523x" +.IP "\fB5249\fR : \fB5249\fR" 4 +.IX Item "5249 : 5249" +.IP "\fB5250\fR : \fB5250\fR" 4 +.IX Item "5250 : 5250" +.IP "\fB5271\fR : \fB5270\fR \fB5271\fR" 4 +.IX Item "5271 : 5270 5271" +.IP "\fB5272\fR : \fB5272\fR" 4 +.IX Item "5272 : 5272" +.IP "\fB5275\fR : \fB5274\fR \fB5275\fR" 4 +.IX Item "5275 : 5274 5275" +.IP "\fB5282\fR : \fB5280\fR \fB5281\fR \fB5282\fR \fB528x\fR" 4 +.IX Item "5282 : 5280 5281 5282 528x" +.IP "\fB53017\fR : \fB53011\fR \fB53012\fR \fB53013\fR \fB53014\fR \fB53015\fR \fB53016\fR \fB53017\fR" 4 +.IX Item "53017 : 53011 53012 53013 53014 53015 53016 53017" +.IP "\fB5307\fR : \fB5307\fR" 4 +.IX Item "5307 : 5307" +.IP "\fB5329\fR : \fB5327\fR \fB5328\fR \fB5329\fR \fB532x\fR" 4 +.IX Item "5329 : 5327 5328 5329 532x" +.IP "\fB5373\fR : \fB5372\fR \fB5373\fR \fB537x\fR" 4 +.IX Item "5373 : 5372 5373 537x" +.IP "\fB5407\fR : \fB5407\fR" 4 +.IX Item "5407 : 5407" +.IP "\fB5475\fR : \fB5470\fR \fB5471\fR \fB5472\fR \fB5473\fR \fB5474\fR \fB5475\fR \fB547x\fR \fB5480\fR \fB5481\fR \fB5482\fR \fB5483\fR \fB5484\fR \fB5485\fR" 4 +.IX Item "5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485" +.RE +.RS 4 +.PD +.Sp +\&\fB\-mcpu=\fR\fIcpu\fR overrides \fB\-march=\fR\fIarch\fR if +\&\fIarch\fR is compatible with \fIcpu\fR. Other combinations of +\&\fB\-mcpu\fR and \fB\-march\fR are rejected. +.Sp +\&\s-1GCC\s0 defines the macro \f(CW\*(C`_\|_mcf_cpu_\f(CIcpu\f(CW\*(C'\fR when ColdFire target +\&\fIcpu\fR is selected. It also defines \f(CW\*(C`_\|_mcf_family_\f(CIfamily\f(CW\*(C'\fR, +where the value of \fIfamily\fR is given by the table above. +.RE +.IP "\fB\-mtune=\fR\fItune\fR" 4 +.IX Item "-mtune=tune" +Tune the code for a particular microarchitecture within the +constraints set by \fB\-march\fR and \fB\-mcpu\fR. +The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR, +\&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR +and \fBcpu32\fR. The ColdFire microarchitectures +are: \fBcfv1\fR, \fBcfv2\fR, \fBcfv3\fR, \fBcfv4\fR and \fBcfv4e\fR. +.Sp +You can also use \fB\-mtune=68020\-40\fR for code that needs +to run relatively well on 68020, 68030 and 68040 targets. +\&\fB\-mtune=68020\-60\fR is similar but includes 68060 targets +as well. These two options select the same tuning decisions as +\&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively. +.Sp +\&\s-1GCC\s0 defines the macros \f(CW\*(C`_\|_mc\f(CIarch\f(CW\*(C'\fR and \f(CW\*(C`_\|_mc\f(CIarch\f(CW_\|_\*(C'\fR +when tuning for 680x0 architecture \fIarch\fR. It also defines +\&\f(CW\*(C`mc\f(CIarch\f(CW\*(C'\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR +option is used. If \s-1GCC\s0 is tuning for a range of architectures, +as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR, +it defines the macros for every architecture in the range. +.Sp +\&\s-1GCC\s0 also defines the macro \f(CW\*(C`_\|_m\f(CIuarch\f(CW_\|_\*(C'\fR when tuning for +ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one +of the arguments given above. +.IP "\fB\-m68000\fR" 4 +.IX Item "-m68000" +.PD 0 +.IP "\fB\-mc68000\fR" 4 +.IX Item "-mc68000" +.PD +Generate output for a 68000. This is the default +when the compiler is configured for 68000\-based systems. +It is equivalent to \fB\-march=68000\fR. +.Sp +Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core, +including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. +.IP "\fB\-m68010\fR" 4 +.IX Item "-m68010" +Generate output for a 68010. This is the default +when the compiler is configured for 68010\-based systems. +It is equivalent to \fB\-march=68010\fR. +.IP "\fB\-m68020\fR" 4 +.IX Item "-m68020" +.PD 0 +.IP "\fB\-mc68020\fR" 4 +.IX Item "-mc68020" +.PD +Generate output for a 68020. This is the default +when the compiler is configured for 68020\-based systems. +It is equivalent to \fB\-march=68020\fR. +.IP "\fB\-m68030\fR" 4 +.IX Item "-m68030" +Generate output for a 68030. This is the default when the compiler is +configured for 68030\-based systems. It is equivalent to +\&\fB\-march=68030\fR. +.IP "\fB\-m68040\fR" 4 +.IX Item "-m68040" +Generate output for a 68040. This is the default when the compiler is +configured for 68040\-based systems. It is equivalent to +\&\fB\-march=68040\fR. +.Sp +This option inhibits the use of 68881/68882 instructions that have to be +emulated by software on the 68040. Use this option if your 68040 does not +have code to emulate those instructions. +.IP "\fB\-m68060\fR" 4 +.IX Item "-m68060" +Generate output for a 68060. This is the default when the compiler is +configured for 68060\-based systems. It is equivalent to +\&\fB\-march=68060\fR. +.Sp +This option inhibits the use of 68020 and 68881/68882 instructions that +have to be emulated by software on the 68060. Use this option if your 68060 +does not have code to emulate those instructions. +.IP "\fB\-mcpu32\fR" 4 +.IX Item "-mcpu32" +Generate output for a \s-1CPU32.\s0 This is the default +when the compiler is configured for CPU32\-based systems. +It is equivalent to \fB\-march=cpu32\fR. +.Sp +Use this option for microcontrollers with a +\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334, +68336, 68340, 68341, 68349 and 68360. +.IP "\fB\-m5200\fR" 4 +.IX Item "-m5200" +Generate output for a 520X ColdFire \s-1CPU.\s0 This is the default +when the compiler is configured for 520X\-based systems. +It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated +in favor of that option. +.Sp +Use this option for microcontroller with a 5200 core, including +the \s-1MCF5202, MCF5203, MCF5204\s0 and \s-1MCF5206.\s0 +.IP "\fB\-m5206e\fR" 4 +.IX Item "-m5206e" +Generate output for a 5206e ColdFire \s-1CPU.\s0 The option is now +deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. +.IP "\fB\-m528x\fR" 4 +.IX Item "-m528x" +Generate output for a member of the ColdFire 528X family. +The option is now deprecated in favor of the equivalent +\&\fB\-mcpu=528x\fR. +.IP "\fB\-m5307\fR" 4 +.IX Item "-m5307" +Generate output for a ColdFire 5307 \s-1CPU.\s0 The option is now deprecated +in favor of the equivalent \fB\-mcpu=5307\fR. +.IP "\fB\-m5407\fR" 4 +.IX Item "-m5407" +Generate output for a ColdFire 5407 \s-1CPU.\s0 The option is now deprecated +in favor of the equivalent \fB\-mcpu=5407\fR. +.IP "\fB\-mcfv4e\fR" 4 +.IX Item "-mcfv4e" +Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). +This includes use of hardware floating-point instructions. +The option is equivalent to \fB\-mcpu=547x\fR, and is now +deprecated in favor of that option. +.IP "\fB\-m68020\-40\fR" 4 +.IX Item "-m68020-40" +Generate output for a 68040, without using any of the new instructions. +This results in code that can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68040. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-40\fR. +.IP "\fB\-m68020\-60\fR" 4 +.IX Item "-m68020-60" +Generate output for a 68060, without using any of the new instructions. +This results in code that can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68060. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-m68881\fR" 4 +.IX Item "-m68881" +.PD +Generate floating-point instructions. This is the default for 68020 +and above, and for ColdFire devices that have an \s-1FPU.\s0 It defines the +macro \f(CW\*(C`_\|_HAVE_68881_\|_\*(C'\fR on M680x0 targets and \f(CW\*(C`_\|_mcffpu_\|_\*(C'\fR +on ColdFire targets. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not generate floating-point instructions; use library calls instead. +This is the default for 68000, 68010, and 68832 targets. It is also +the default for ColdFire devices that have no \s-1FPU.\s0 +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Generate (do not generate) ColdFire hardware divide and remainder +instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, +the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 +architectures. Otherwise, the default is taken from the target \s-1CPU\s0 +(either the default \s-1CPU,\s0 or the one specified by \fB\-mcpu\fR). For +example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for +\&\fB\-mcpu=5206e\fR. +.Sp +\&\s-1GCC\s0 defines the macro \f(CW\*(C`_\|_mcfhwdiv_\|_\*(C'\fR when this option is enabled. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. +Additionally, parameters passed on the stack are also aligned to a +16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit. +.IP "\fB\-mno\-short\fR" 4 +.IX Item "-mno-short" +Do not consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide. This is the default. +.IP "\fB\-mnobitfield\fR" 4 +.IX Item "-mnobitfield" +.PD 0 +.IP "\fB\-mno\-bitfield\fR" 4 +.IX Item "-mno-bitfield" +.PD +Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR +and \fB\-m5200\fR options imply \fB\-mnobitfield\fR. +.IP "\fB\-mbitfield\fR" 4 +.IX Item "-mbitfield" +Do use the bit-field instructions. The \fB\-m68020\fR option implies +\&\fB\-mbitfield\fR. This is the default if you use a configuration +designed for a 68020. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions +that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR +instruction, which pops their arguments while returning. This +saves one instruction in the caller since there is no need to pop +the arguments there. +.Sp +This calling convention is incompatible with the one normally +used on Unix, so you cannot use it if you need to call libraries +compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code is generated for calls to those +functions. +.Sp +In addition, seriously incorrect code results if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.Sp +The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030, +68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200. +.Sp +The default is \fB\-mno\-rtd\fR. +.IP "\fB\-malign\-int\fR" 4 +.IX Item "-malign-int" +.PD 0 +.IP "\fB\-mno\-align\-int\fR" 4 +.IX Item "-mno-align-int" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR, +\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit +boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR). +Aligning variables on 32\-bit boundaries produces code that runs somewhat +faster on processors with 32\-bit busses at the expense of more memory. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 +aligns structures containing the above types differently than +most published application binary interface specifications for the m68k. +.IP "\fB\-mpcrel\fR" 4 +.IX Item "-mpcrel" +Use the pc-relative addressing mode of the 68000 directly, instead of +using a global offset table. At present, this option implies \fB\-fpic\fR, +allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is +not presently supported with \fB\-mpcrel\fR, though this could be supported for +68020 and higher processors. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +Do not (do) assume that unaligned memory references are handled by +the system. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute-in-place in +an environment without virtual memory management. This option implies +\&\fB\-fPIC\fR. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute-in-place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume ID-based shared libraries are being used. +This is the default. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specifies the identification number of the ID-based shared library being +compiled. Specifying a value of 0 generates more compact code; specifying +other values forces the allocation of that number to the current +library, but is no more space\- or time-efficient than omitting this option. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +When generating position-independent code for ColdFire, generate code +that works if the \s-1GOT\s0 has more than 8192 entries. This code is +larger and slower than code generated without this option. On M680x0 +processors, this option is not needed; \fB\-fPIC\fR suffices. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 +While this is relatively efficient, it only works if the \s-1GOT\s0 +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_68K_GOT16O foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +It should then work with very large GOTs. However, code generated with +\&\fB\-mxgot\fR is less efficient, since it takes 4 instructions to fetch +the value of a global symbol. +.Sp +Note that some linkers, including newer versions of the \s-1GNU\s0 linker, +can create multiple GOTs and sort \s-1GOT\s0 entries. If you have such a linker, +you should only need to use \fB\-mxgot\fR when compiling a single +object file that accesses more than 8192 \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating +position-independent code. +.IP "\fB\-mlong\-jump\-table\-offsets\fR" 4 +.IX Item "-mlong-jump-table-offsets" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.PP +\fIMCore Options\fR +.IX Subsection "MCore Options" +.PP +These are the \fB\-m\fR options defined for the Motorola M*Core +processors. +.IP "\fB\-mhardlit\fR" 4 +.IX Item "-mhardlit" +.PD 0 +.IP "\fB\-mno\-hardlit\fR" 4 +.IX Item "-mno-hardlit" +.PD +Inline constants into the code stream if it can be done in two +instructions or less. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Use the divide instruction. (Enabled by default). +.IP "\fB\-mrelax\-immediate\fR" 4 +.IX Item "-mrelax-immediate" +.PD 0 +.IP "\fB\-mno\-relax\-immediate\fR" 4 +.IX Item "-mno-relax-immediate" +.PD +Allow arbitrary-sized immediates in bit operations. +.IP "\fB\-mwide\-bitfields\fR" 4 +.IX Item "-mwide-bitfields" +.PD 0 +.IP "\fB\-mno\-wide\-bitfields\fR" 4 +.IX Item "-mno-wide-bitfields" +.PD +Always treat bit-fields as \f(CW\*(C`int\*(C'\fR\-sized. +.IP "\fB\-m4byte\-functions\fR" 4 +.IX Item "-m4byte-functions" +.PD 0 +.IP "\fB\-mno\-4byte\-functions\fR" 4 +.IX Item "-mno-4byte-functions" +.PD +Force all functions to be aligned to a 4\-byte boundary. +.IP "\fB\-mcallgraph\-data\fR" 4 +.IX Item "-mcallgraph-data" +.PD 0 +.IP "\fB\-mno\-callgraph\-data\fR" 4 +.IX Item "-mno-callgraph-data" +.PD +Emit callgraph information. +.IP "\fB\-mslow\-bytes\fR" 4 +.IX Item "-mslow-bytes" +.PD 0 +.IP "\fB\-mno\-slow\-bytes\fR" 4 +.IX Item "-mno-slow-bytes" +.PD +Prefer word access when reading byte quantities. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +Generate code for a little-endian target. +.IP "\fB\-m210\fR" 4 +.IX Item "-m210" +.PD 0 +.IP "\fB\-m340\fR" 4 +.IX Item "-m340" +.PD +Generate code for the 210 processor. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that runtime support has been provided and so omit the +simulator library (\fIlibsim.a)\fR from the linker command line. +.IP "\fB\-mstack\-increment=\fR\fIsize\fR" 4 +.IX Item "-mstack-increment=size" +Set the maximum amount for a single stack increment operation. Large +values can increase the speed of programs that contain functions +that need a large amount of stack space, but they can also trigger a +segmentation fault if the stack is extended too much. The default +value is 0x1000. +.PP +\fIMeP Options\fR +.IX Subsection "MeP Options" +.IP "\fB\-mabsdiff\fR" 4 +.IX Item "-mabsdiff" +Enables the \f(CW\*(C`abs\*(C'\fR instruction, which is the absolute difference +between two registers. +.IP "\fB\-mall\-opts\fR" 4 +.IX Item "-mall-opts" +Enables all the optional instructions\-\-\-average, multiply, divide, bit +operations, leading zero, absolute difference, min/max, clip, and +saturation. +.IP "\fB\-maverage\fR" 4 +.IX Item "-maverage" +Enables the \f(CW\*(C`ave\*(C'\fR instruction, which computes the average of two +registers. +.IP "\fB\-mbased=\fR\fIn\fR" 4 +.IX Item "-mbased=n" +Variables of size \fIn\fR bytes or smaller are placed in the +\&\f(CW\*(C`.based\*(C'\fR section by default. Based variables use the \f(CW$tp\fR +register as a base register, and there is a 128\-byte limit to the +\&\f(CW\*(C`.based\*(C'\fR section. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enables the bit operation instructions\-\-\-bit test (\f(CW\*(C`btstm\*(C'\fR), set +(\f(CW\*(C`bsetm\*(C'\fR), clear (\f(CW\*(C`bclrm\*(C'\fR), invert (\f(CW\*(C`bnotm\*(C'\fR), and +test-and-set (\f(CW\*(C`tas\*(C'\fR). +.IP "\fB\-mc=\fR\fIname\fR" 4 +.IX Item "-mc=name" +Selects which section constant data is placed in. \fIname\fR may +be \fBtiny\fR, \fBnear\fR, or \fBfar\fR. +.IP "\fB\-mclip\fR" 4 +.IX Item "-mclip" +Enables the \f(CW\*(C`clip\*(C'\fR instruction. Note that \fB\-mclip\fR is not +useful unless you also provide \fB\-mminmax\fR. +.IP "\fB\-mconfig=\fR\fIname\fR" 4 +.IX Item "-mconfig=name" +Selects one of the built-in core configurations. Each MeP chip has +one or more modules in it; each module has a core \s-1CPU\s0 and a variety of +coprocessors, optional instructions, and peripherals. The +\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC,\s0 provides these +configurations through this option; using this option is the same as +using all the corresponding command-line options. The default +configuration is \fBdefault\fR. +.IP "\fB\-mcop\fR" 4 +.IX Item "-mcop" +Enables the coprocessor instructions. By default, this is a 32\-bit +coprocessor. Note that the coprocessor is normally enabled via the +\&\fB\-mconfig=\fR option. +.IP "\fB\-mcop32\fR" 4 +.IX Item "-mcop32" +Enables the 32\-bit coprocessor's instructions. +.IP "\fB\-mcop64\fR" 4 +.IX Item "-mcop64" +Enables the 64\-bit coprocessor's instructions. +.IP "\fB\-mivc2\fR" 4 +.IX Item "-mivc2" +Enables \s-1IVC2\s0 scheduling. \s-1IVC2\s0 is a 64\-bit \s-1VLIW\s0 coprocessor. +.IP "\fB\-mdc\fR" 4 +.IX Item "-mdc" +Causes constant variables to be placed in the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +Enables the \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions. +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Generate big-endian code. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Generate little-endian code. +.IP "\fB\-mio\-volatile\fR" 4 +.IX Item "-mio-volatile" +Tells the compiler that any variable marked with the \f(CW\*(C`io\*(C'\fR +attribute is to be considered volatile. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Causes variables to be assigned to the \f(CW\*(C`.far\*(C'\fR section by default. +.IP "\fB\-mleadz\fR" 4 +.IX Item "-mleadz" +Enables the \f(CW\*(C`leadz\*(C'\fR (leading zero) instruction. +.IP "\fB\-mm\fR" 4 +.IX Item "-mm" +Causes variables to be assigned to the \f(CW\*(C`.near\*(C'\fR section by default. +.IP "\fB\-mminmax\fR" 4 +.IX Item "-mminmax" +Enables the \f(CW\*(C`min\*(C'\fR and \f(CW\*(C`max\*(C'\fR instructions. +.IP "\fB\-mmult\fR" 4 +.IX Item "-mmult" +Enables the multiplication and multiply-accumulate instructions. +.IP "\fB\-mno\-opts\fR" 4 +.IX Item "-mno-opts" +Disables all the optional instructions enabled by \fB\-mall\-opts\fR. +.IP "\fB\-mrepeat\fR" 4 +.IX Item "-mrepeat" +Enables the \f(CW\*(C`repeat\*(C'\fR and \f(CW\*(C`erepeat\*(C'\fR instructions, used for +low-overhead looping. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Causes all variables to default to the \f(CW\*(C`.tiny\*(C'\fR section. Note +that there is a 65536\-byte limit to this section. Accesses to these +variables use the \f(CW%gp\fR base register. +.IP "\fB\-msatur\fR" 4 +.IX Item "-msatur" +Enables the saturation instructions. Note that the compiler does not +currently generate these itself, but this option is included for +compatibility with other tools, like \f(CW\*(C`as\*(C'\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Link the SDRAM-based runtime instead of the default ROM-based runtime. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Link the simulator run-time libraries. +.IP "\fB\-msimnovec\fR" 4 +.IX Item "-msimnovec" +Link the simulator runtime libraries, excluding built-in support +for reset and exception vectors and tables. +.IP "\fB\-mtf\fR" 4 +.IX Item "-mtf" +Causes all functions to default to the \f(CW\*(C`.far\*(C'\fR section. Without +this option, functions default to the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mtiny=\fR\fIn\fR" 4 +.IX Item "-mtiny=n" +Variables that are \fIn\fR bytes or smaller are allocated to the +\&\f(CW\*(C`.tiny\*(C'\fR section. These variables use the \f(CW$gp\fR base +register. The default for this option is 4, but note that there's a +65536\-byte limit to the \f(CW\*(C`.tiny\*(C'\fR section. +.PP +\fIMicroBlaze Options\fR +.IX Subsection "MicroBlaze Options" +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use software emulation for floating point (default). +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware floating-point instructions. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. +.IP "\fB\-mno\-clearbss\fR" 4 +.IX Item "-mno-clearbss" +This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +Use features of, and schedule code for, the given \s-1CPU.\s0 +Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, +where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and +\&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, +\&\fBv4.00.b\fR, \fBv5.00.a\fR, \fBv5.00.b\fR, \fBv6.00.a\fR. +.IP "\fB\-mxl\-soft\-mul\fR" 4 +.IX Item "-mxl-soft-mul" +Use software multiply emulation (default). +.IP "\fB\-mxl\-soft\-div\fR" 4 +.IX Item "-mxl-soft-div" +Use software emulation for divides (default). +.IP "\fB\-mxl\-barrel\-shift\fR" 4 +.IX Item "-mxl-barrel-shift" +Use the hardware barrel shifter. +.IP "\fB\-mxl\-pattern\-compare\fR" 4 +.IX Item "-mxl-pattern-compare" +Use pattern compare instructions. +.IP "\fB\-msmall\-divides\fR" 4 +.IX Item "-msmall-divides" +Use table lookup optimization for small signed integer divisions. +.IP "\fB\-mxl\-stack\-check\fR" 4 +.IX Item "-mxl-stack-check" +This option is deprecated. Use \fB\-fstack\-check\fR instead. +.IP "\fB\-mxl\-gp\-opt\fR" 4 +.IX Item "-mxl-gp-opt" +Use GP-relative \f(CW\*(C`.sdata\*(C'\fR/\f(CW\*(C`.sbss\*(C'\fR sections. +.IP "\fB\-mxl\-multiply\-high\fR" 4 +.IX Item "-mxl-multiply-high" +Use multiply high instructions for high part of 32x32 multiply. +.IP "\fB\-mxl\-float\-convert\fR" 4 +.IX Item "-mxl-float-convert" +Use hardware floating-point conversion instructions. +.IP "\fB\-mxl\-float\-sqrt\fR" 4 +.IX Item "-mxl-float-sqrt" +Use hardware floating-point square root instruction. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. +.IP "\fB\-mxl\-reorder\fR" 4 +.IX Item "-mxl-reorder" +Use reorder instructions (swap and byte reversed load/store). +.IP "\fB\-mxl\-mode\-\fR\fIapp-model\fR" 4 +.IX Item "-mxl-mode-app-model" +Select application model \fIapp-model\fR. Valid models are +.RS 4 +.IP "\fBexecutable\fR" 4 +.IX Item "executable" +normal executable (default), uses startup code \fIcrt0.o\fR. +.IP "\fB\-mpic\-data\-is\-text\-relative\fR" 4 +.IX Item "-mpic-data-is-text-relative" +Assume that the displacement between the text and data segments is fixed +at static link time. This allows data to be referenced by offset from start of +text address instead of \s-1GOT\s0 since PC-relative addressing is not supported. +.IP "\fBxmdstub\fR" 4 +.IX Item "xmdstub" +for use with Xilinx Microprocessor Debugger (\s-1XMD\s0) based +software intrusive debug agent called xmdstub. This uses startup file +\&\fIcrt1.o\fR and sets the start address of the program to 0x800. +.IP "\fBbootstrap\fR" 4 +.IX Item "bootstrap" +for applications that are loaded using a bootloader. +This model uses startup file \fIcrt2.o\fR which does not contain a processor +reset vector handler. This is suitable for transferring control on a +processor reset to the bootloader rather than the application. +.IP "\fBnovectors\fR" 4 +.IX Item "novectors" +for applications that do not require any of the +MicroBlaze vectors. This option may be useful for applications running +within a monitoring application. This model uses \fIcrt3.o\fR as a startup file. +.RE +.RS 4 +.Sp +Option \fB\-xl\-mode\-\fR\fIapp-model\fR is a deprecated alias for +\&\fB\-mxl\-mode\-\fR\fIapp-model\fR. +.RE +.PP +\fI\s-1MIPS\s0 Options\fR +.IX Subsection "MIPS Options" +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Generate big-endian code. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR +configurations. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code that runs on \fIarch\fR, which can be the name of a +generic \s-1MIPS ISA,\s0 or the name of a particular processor. +The \s-1ISA\s0 names are: +\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, +\&\fBmips32\fR, \fBmips32r2\fR, \fBmips32r3\fR, \fBmips32r5\fR, +\&\fBmips32r6\fR, \fBmips64\fR, \fBmips64r2\fR, \fBmips64r3\fR, +\&\fBmips64r5\fR and \fBmips64r6\fR. +The processor names are: +\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR, +\&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR, +\&\fB5kc\fR, \fB5kf\fR, +\&\fB20kc\fR, +\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR, +\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR, +\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR, \fB34kn\fR, +\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR, +\&\fB1004kc\fR, \fB1004kf2_1\fR, \fB1004kf1_1\fR, +\&\fBi6400\fR, \fBi6500\fR, +\&\fBinteraptiv\fR, +\&\fBloongson2e\fR, \fBloongson2f\fR, \fBloongson3a\fR, \fBgs464\fR, +\&\fBgs464e\fR, \fBgs264e\fR, +\&\fBm4k\fR, +\&\fBm14k\fR, \fBm14kc\fR, \fBm14ke\fR, \fBm14kec\fR, +\&\fBm5100\fR, \fBm5101\fR, +\&\fBocteon\fR, \fBocteon+\fR, \fBocteon2\fR, \fBocteon3\fR, +\&\fBorion\fR, +\&\fBp5600\fR, \fBp6600\fR, +\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR, +\&\fBr4600\fR, \fBr4650\fR, \fBr4700\fR, \fBr5900\fR, +\&\fBr6000\fR, \fBr8000\fR, +\&\fBrm7000\fR, \fBrm9000\fR, +\&\fBr10000\fR, \fBr12000\fR, \fBr14000\fR, \fBr16000\fR, +\&\fBsb1\fR, +\&\fBsr71000\fR, +\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR, +\&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR, +\&\fBxlr\fR and \fBxlp\fR. +The special value \fBfrom-abi\fR selects the +most compatible architecture for the selected \s-1ABI\s0 (that is, +\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). +.Sp +The native Linux/GNU toolchain also supports the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +In processor names, a final \fB000\fR can be abbreviated as \fBk\fR +(for example, \fB\-march=r2k\fR). Prefixes are optional, and +\&\fBvr\fR may be written \fBr\fR. +.Sp +Names of the form \fIn\fR\fBf2_1\fR refer to processors with +FPUs clocked at half the rate of the core, names of the form +\&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same +rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to +processors with FPUs clocked a ratio of 3:2 with respect to the core. +For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym +for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are +accepted as synonyms for \fIn\fR\fBf1_1\fR. +.Sp +\&\s-1GCC\s0 defines two macros based on the value of this option. The first +is \f(CW\*(C`_MIPS_ARCH\*(C'\fR, which gives the name of target architecture, as +a string. The second has the form \f(CW\*(C`_MIPS_ARCH_\f(CIfoo\f(CW\*(C'\fR, +where \fIfoo\fR is the capitalized value of \f(CW\*(C`_MIPS_ARCH\*(C'\fR. +For example, \fB\-march=r2000\fR sets \f(CW\*(C`_MIPS_ARCH\*(C'\fR +to \f(CW"r2000"\fR and defines the macro \f(CW\*(C`_MIPS_ARCH_R2000\*(C'\fR. +.Sp +Note that the \f(CW\*(C`_MIPS_ARCH\*(C'\fR macro uses the processor names given +above. In other words, it has the full prefix and does not +abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR, +the macro names the resolved architecture (either \f(CW"mips1"\fR or +\&\f(CW"mips3"\fR). It names the default architecture when no +\&\fB\-march\fR option is given. +.IP "\fB\-mtune=\fR\fIarch\fR" 4 +.IX Item "-mtune=arch" +Optimize for \fIarch\fR. Among other things, this option controls +the way instructions are scheduled, and the perceived cost of arithmetic +operations. The list of \fIarch\fR values is the same as for +\&\fB\-march\fR. +.Sp +When this option is not used, \s-1GCC\s0 optimizes for the processor +specified by \fB\-march\fR. By using \fB\-march\fR and +\&\fB\-mtune\fR together, it is possible to generate code that +runs on a family of processors, but optimize the code for one +particular member of that family. +.Sp +\&\fB\-mtune\fR defines the macros \f(CW\*(C`_MIPS_TUNE\*(C'\fR and +\&\f(CW\*(C`_MIPS_TUNE_\f(CIfoo\f(CW\*(C'\fR, which work in the same way as the +\&\fB\-march\fR ones described above. +.IP "\fB\-mips1\fR" 4 +.IX Item "-mips1" +Equivalent to \fB\-march=mips1\fR. +.IP "\fB\-mips2\fR" 4 +.IX Item "-mips2" +Equivalent to \fB\-march=mips2\fR. +.IP "\fB\-mips3\fR" 4 +.IX Item "-mips3" +Equivalent to \fB\-march=mips3\fR. +.IP "\fB\-mips4\fR" 4 +.IX Item "-mips4" +Equivalent to \fB\-march=mips4\fR. +.IP "\fB\-mips32\fR" 4 +.IX Item "-mips32" +Equivalent to \fB\-march=mips32\fR. +.IP "\fB\-mips32r3\fR" 4 +.IX Item "-mips32r3" +Equivalent to \fB\-march=mips32r3\fR. +.IP "\fB\-mips32r5\fR" 4 +.IX Item "-mips32r5" +Equivalent to \fB\-march=mips32r5\fR. +.IP "\fB\-mips32r6\fR" 4 +.IX Item "-mips32r6" +Equivalent to \fB\-march=mips32r6\fR. +.IP "\fB\-mips64\fR" 4 +.IX Item "-mips64" +Equivalent to \fB\-march=mips64\fR. +.IP "\fB\-mips64r2\fR" 4 +.IX Item "-mips64r2" +Equivalent to \fB\-march=mips64r2\fR. +.IP "\fB\-mips64r3\fR" 4 +.IX Item "-mips64r3" +Equivalent to \fB\-march=mips64r3\fR. +.IP "\fB\-mips64r5\fR" 4 +.IX Item "-mips64r5" +Equivalent to \fB\-march=mips64r5\fR. +.IP "\fB\-mips64r6\fR" 4 +.IX Item "-mips64r6" +Equivalent to \fB\-march=mips64r6\fR. +.IP "\fB\-mips16\fR" 4 +.IX Item "-mips16" +.PD 0 +.IP "\fB\-mno\-mips16\fR" 4 +.IX Item "-mno-mips16" +.PD +Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targeting a +\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE.\s0 +.Sp +\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis +by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. +.IP "\fB\-mflip\-mips16\fR" 4 +.IX Item "-mflip-mips16" +Generate \s-1MIPS16\s0 code on alternating functions. This option is provided +for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is +not intended for ordinary use in compiling user code. +.IP "\fB\-minterlink\-compressed\fR" 4 +.IX Item "-minterlink-compressed" +.PD 0 +.IP "\fB\-mno\-interlink\-compressed\fR" 4 +.IX Item "-mno-interlink-compressed" +.PD +Require (do not require) that code using the standard (uncompressed) \s-1MIPS ISA\s0 +be link-compatible with \s-1MIPS16\s0 and microMIPS code, and vice versa. +.Sp +For example, code using the standard \s-1ISA\s0 encoding cannot jump directly +to \s-1MIPS16\s0 or microMIPS code; it must either use a call or an indirect jump. +\&\fB\-minterlink\-compressed\fR therefore disables direct jumps unless \s-1GCC\s0 +knows that the target of the jump is not compressed. +.IP "\fB\-minterlink\-mips16\fR" 4 +.IX Item "-minterlink-mips16" +.PD 0 +.IP "\fB\-mno\-interlink\-mips16\fR" 4 +.IX Item "-mno-interlink-mips16" +.PD +Aliases of \fB\-minterlink\-compressed\fR and +\&\fB\-mno\-interlink\-compressed\fR. These options predate the microMIPS \s-1ASE\s0 +and are retained for backwards compatibility. +.IP "\fB\-mabi=32\fR" 4 +.IX Item "-mabi=32" +.PD 0 +.IP "\fB\-mabi=o64\fR" 4 +.IX Item "-mabi=o64" +.IP "\fB\-mabi=n32\fR" 4 +.IX Item "-mabi=n32" +.IP "\fB\-mabi=64\fR" 4 +.IX Item "-mabi=64" +.IP "\fB\-mabi=eabi\fR" 4 +.IX Item "-mabi=eabi" +.PD +Generate code for the given \s-1ABI.\s0 +.Sp +Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally +generates 64\-bit code when you select a 64\-bit architecture, but you +can use \fB\-mgp32\fR to get 32\-bit code instead. +.Sp +For information about the O64 \s-1ABI,\s0 see +<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. +.Sp +\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers +are 64 rather than 32 bits wide. You can select this combination with +\&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \f(CW\*(C`mthc1\*(C'\fR +and \f(CW\*(C`mfhc1\*(C'\fR instructions and is therefore only supported for +\&\s-1MIPS32R2, MIPS32R3\s0 and \s-1MIPS32R5\s0 processors. +.Sp +The register assignments for arguments and return values remain the +same, but each scalar value is passed in a single 64\-bit register +rather than a pair of 32\-bit registers. For example, scalar +floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a +\&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair. The set of call-saved registers also +remains the same in that the even-numbered double-precision registers +are saved. +.Sp +Two additional variants of the o32 \s-1ABI\s0 are supported to enable +a transition from 32\-bit to 64\-bit registers. These are \s-1FPXX\s0 +(\fB\-mfpxx\fR) and \s-1FP64A\s0 (\fB\-mfp64\fR \fB\-mno\-odd\-spreg\fR). +The \s-1FPXX\s0 extension mandates that all code must execute correctly +when run using 32\-bit or 64\-bit registers. The code can be interlinked +with either \s-1FP32\s0 or \s-1FP64,\s0 but not both. +The \s-1FP64A\s0 extension is similar to the \s-1FP64\s0 extension but forbids the +use of odd-numbered single-precision registers. This can be used +in conjunction with the \f(CW\*(C`FRE\*(C'\fR mode of FPUs in \s-1MIPS32R5\s0 +processors and allows both \s-1FP32\s0 and \s-1FP64A\s0 code to interlink and +run in the same process without changing \s-1FPU\s0 modes. +.IP "\fB\-mabicalls\fR" 4 +.IX Item "-mabicalls" +.PD 0 +.IP "\fB\-mno\-abicalls\fR" 4 +.IX Item "-mno-abicalls" +.PD +Generate (do not generate) code that is suitable for SVR4\-style +dynamic objects. \fB\-mabicalls\fR is the default for SVR4\-based +systems. +.IP "\fB\-mshared\fR" 4 +.IX Item "-mshared" +.PD 0 +.IP "\fB\-mno\-shared\fR" 4 +.IX Item "-mno-shared" +.PD +Generate (do not generate) code that is fully position-independent, +and that can therefore be linked into shared libraries. This option +only affects \fB\-mabicalls\fR. +.Sp +All \fB\-mabicalls\fR code has traditionally been position-independent, +regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR. However, +as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute +accesses for locally-binding symbols. It can also use shorter \s-1GP\s0 +initialization sequences and generate direct calls to locally-defined +functions. This mode is selected by \fB\-mno\-shared\fR. +.Sp +\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates +objects that can only be linked by the \s-1GNU\s0 linker. However, the option +does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0 +of relocatable objects. Using \fB\-mno\-shared\fR generally makes +executables both smaller and quicker. +.Sp +\&\fB\-mshared\fR is the default. +.IP "\fB\-mplt\fR" 4 +.IX Item "-mplt" +.PD 0 +.IP "\fB\-mno\-plt\fR" 4 +.IX Item "-mno-plt" +.PD +Assume (do not assume) that the static and dynamic linkers +support PLTs and copy relocations. This option only affects +\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI,\s0 this option +has no effect without \fB\-msym32\fR. +.Sp +You can make \fB\-mplt\fR the default by configuring +\&\s-1GCC\s0 with \fB\-\-with\-mips\-plt\fR. The default is +\&\fB\-mno\-plt\fR otherwise. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +Lift (do not lift) the usual restrictions on the size of the global +offset table. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 +While this is relatively efficient, it only works if the \s-1GOT\s0 +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_MIPS_GOT16 foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +This works with very large GOTs, although the code is also +less efficient, since it takes three instructions to fetch the +value of a global symbol. +.Sp +Note that some linkers can create multiple GOTs. If you have such a +linker, you should only need to use \fB\-mxgot\fR when a single object +file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating position +independent code. +.IP "\fB\-mgp32\fR" 4 +.IX Item "-mgp32" +Assume that general-purpose registers are 32 bits wide. +.IP "\fB\-mgp64\fR" 4 +.IX Item "-mgp64" +Assume that general-purpose registers are 64 bits wide. +.IP "\fB\-mfp32\fR" 4 +.IX Item "-mfp32" +Assume that floating-point registers are 32 bits wide. +.IP "\fB\-mfp64\fR" 4 +.IX Item "-mfp64" +Assume that floating-point registers are 64 bits wide. +.IP "\fB\-mfpxx\fR" 4 +.IX Item "-mfpxx" +Do not assume the width of floating-point registers. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use floating-point coprocessor instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use floating-point coprocessor instructions. Implement +floating-point calculations using library calls instead. +.IP "\fB\-mno\-float\fR" 4 +.IX Item "-mno-float" +Equivalent to \fB\-msoft\-float\fR, but additionally asserts that the +program being compiled does not perform any floating-point operations. +This option is presently supported only by some bare-metal \s-1MIPS\s0 +configurations, where it may select a special set of libraries +that lack all floating-point support (including, for example, the +floating-point \f(CW\*(C`printf\*(C'\fR formats). +If code compiled with \fB\-mno\-float\fR accidentally contains +floating-point operations, it is likely to suffer a link-time +or run-time failure. +.IP "\fB\-msingle\-float\fR" 4 +.IX Item "-msingle-float" +Assume that the floating-point coprocessor only supports single-precision +operations. +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +Assume that the floating-point coprocessor supports double-precision +operations. This is the default. +.IP "\fB\-modd\-spreg\fR" 4 +.IX Item "-modd-spreg" +.PD 0 +.IP "\fB\-mno\-odd\-spreg\fR" 4 +.IX Item "-mno-odd-spreg" +.PD +Enable the use of odd-numbered single-precision floating-point registers +for the o32 \s-1ABI.\s0 This is the default for processors that are known to +support these registers. When using the o32 \s-1FPXX ABI,\s0 \fB\-mno\-odd\-spreg\fR +is set by default. +.IP "\fB\-mabs=2008\fR" 4 +.IX Item "-mabs=2008" +.PD 0 +.IP "\fB\-mabs=legacy\fR" 4 +.IX Item "-mabs=legacy" +.PD +These options control the treatment of the special not-a-number (NaN) +\&\s-1IEEE 754\s0 floating-point data with the \f(CW\*(C`abs.\f(CIfmt\f(CW\*(C'\fR and +\&\f(CW\*(C`neg.\f(CIfmt\f(CW\*(C'\fR machine instructions. +.Sp +By default or when \fB\-mabs=legacy\fR is used the legacy +treatment is selected. In this case these instructions are considered +arithmetic and avoided where correct operation is required and the +input operand might be a NaN. A longer sequence of instructions that +manipulate the sign bit of floating-point datum manually is used +instead unless the \fB\-ffinite\-math\-only\fR option has also been +specified. +.Sp +The \fB\-mabs=2008\fR option selects the \s-1IEEE 754\-2008\s0 treatment. In +this case these instructions are considered non-arithmetic and therefore +operating correctly in all cases, including in particular where the +input operand is a NaN. These instructions are therefore always used +for the respective operations. +.IP "\fB\-mnan=2008\fR" 4 +.IX Item "-mnan=2008" +.PD 0 +.IP "\fB\-mnan=legacy\fR" 4 +.IX Item "-mnan=legacy" +.PD +These options control the encoding of the special not-a-number (NaN) +\&\s-1IEEE 754\s0 floating-point data. +.Sp +The \fB\-mnan=legacy\fR option selects the legacy encoding. In this +case quiet NaNs (qNaNs) are denoted by the first bit of their trailing +significand field being 0, whereas signaling NaNs (sNaNs) are denoted +by the first bit of their trailing significand field being 1. +.Sp +The \fB\-mnan=2008\fR option selects the \s-1IEEE 754\-2008\s0 encoding. In +this case qNaNs are denoted by the first bit of their trailing +significand field being 1, whereas sNaNs are denoted by the first bit of +their trailing significand field being 0. +.Sp +The default is \fB\-mnan=legacy\fR unless \s-1GCC\s0 has been configured with +\&\fB\-\-with\-nan=2008\fR. +.IP "\fB\-mllsc\fR" 4 +.IX Item "-mllsc" +.PD 0 +.IP "\fB\-mno\-llsc\fR" 4 +.IX Item "-mno-llsc" +.PD +Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to +implement atomic memory built-in functions. When neither option is +specified, \s-1GCC\s0 uses the instructions if the target architecture +supports them. +.Sp +\&\fB\-mllsc\fR is useful if the runtime environment can emulate the +instructions and \fB\-mno\-llsc\fR can be useful when compiling for +nonstandard ISAs. You can make either option the default by +configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR +respectively. \fB\-\-with\-llsc\fR is the default for some +configurations; see the installation documentation for details. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-mno\-dsp\fR" 4 +.IX Item "-mno-dsp" +.PD +Use (do not use) revision 1 of the \s-1MIPS DSP ASE.\s0 + This option defines the +preprocessor macro \f(CW\*(C`_\|_mips_dsp\*(C'\fR. It also defines +\&\f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 1. +.IP "\fB\-mdspr2\fR" 4 +.IX Item "-mdspr2" +.PD 0 +.IP "\fB\-mno\-dspr2\fR" 4 +.IX Item "-mno-dspr2" +.PD +Use (do not use) revision 2 of the \s-1MIPS DSP ASE.\s0 + This option defines the +preprocessor macros \f(CW\*(C`_\|_mips_dsp\*(C'\fR and \f(CW\*(C`_\|_mips_dspr2\*(C'\fR. +It also defines \f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 2. +.IP "\fB\-msmartmips\fR" 4 +.IX Item "-msmartmips" +.PD 0 +.IP "\fB\-mno\-smartmips\fR" 4 +.IX Item "-mno-smartmips" +.PD +Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE.\s0 +.IP "\fB\-mpaired\-single\fR" 4 +.IX Item "-mpaired-single" +.PD 0 +.IP "\fB\-mno\-paired\-single\fR" 4 +.IX Item "-mno-paired-single" +.PD +Use (do not use) paired-single floating-point instructions. + This option requires +hardware floating-point support to be enabled. +.IP "\fB\-mdmx\fR" 4 +.IX Item "-mdmx" +.PD 0 +.IP "\fB\-mno\-mdmx\fR" 4 +.IX Item "-mno-mdmx" +.PD +Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions. +This option can only be used when generating 64\-bit code and requires +hardware floating-point support to be enabled. +.IP "\fB\-mips3d\fR" 4 +.IX Item "-mips3d" +.PD 0 +.IP "\fB\-mno\-mips3d\fR" 4 +.IX Item "-mno-mips3d" +.PD +Use (do not use) the \s-1MIPS\-3D ASE.\s0 +The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. +.IP "\fB\-mmicromips\fR" 4 +.IX Item "-mmicromips" +.PD 0 +.IP "\fB\-mno\-micromips\fR" 4 +.IX Item "-mno-micromips" +.PD +Generate (do not generate) microMIPS code. +.Sp +MicroMIPS code generation can also be controlled on a per-function basis +by means of \f(CW\*(C`micromips\*(C'\fR and \f(CW\*(C`nomicromips\*(C'\fR attributes. +.IP "\fB\-mmt\fR" 4 +.IX Item "-mmt" +.PD 0 +.IP "\fB\-mno\-mt\fR" 4 +.IX Item "-mno-mt" +.PD +Use (do not use) \s-1MT\s0 Multithreading instructions. +.IP "\fB\-mmcu\fR" 4 +.IX Item "-mmcu" +.PD 0 +.IP "\fB\-mno\-mcu\fR" 4 +.IX Item "-mno-mcu" +.PD +Use (do not use) the \s-1MIPS MCU ASE\s0 instructions. +.IP "\fB\-meva\fR" 4 +.IX Item "-meva" +.PD 0 +.IP "\fB\-mno\-eva\fR" 4 +.IX Item "-mno-eva" +.PD +Use (do not use) the \s-1MIPS\s0 Enhanced Virtual Addressing instructions. +.IP "\fB\-mvirt\fR" 4 +.IX Item "-mvirt" +.PD 0 +.IP "\fB\-mno\-virt\fR" 4 +.IX Item "-mno-virt" +.PD +Use (do not use) the \s-1MIPS\s0 Virtualization (\s-1VZ\s0) instructions. +.IP "\fB\-mxpa\fR" 4 +.IX Item "-mxpa" +.PD 0 +.IP "\fB\-mno\-xpa\fR" 4 +.IX Item "-mno-xpa" +.PD +Use (do not use) the \s-1MIPS\s0 eXtended Physical Address (\s-1XPA\s0) instructions. +.IP "\fB\-mcrc\fR" 4 +.IX Item "-mcrc" +.PD 0 +.IP "\fB\-mno\-crc\fR" 4 +.IX Item "-mno-crc" +.PD +Use (do not use) the \s-1MIPS\s0 Cyclic Redundancy Check (\s-1CRC\s0) instructions. +.IP "\fB\-mginv\fR" 4 +.IX Item "-mginv" +.PD 0 +.IP "\fB\-mno\-ginv\fR" 4 +.IX Item "-mno-ginv" +.PD +Use (do not use) the \s-1MIPS\s0 Global INValidate (\s-1GINV\s0) instructions. +.IP "\fB\-mloongson\-mmi\fR" 4 +.IX Item "-mloongson-mmi" +.PD 0 +.IP "\fB\-mno\-loongson\-mmi\fR" 4 +.IX Item "-mno-loongson-mmi" +.PD +Use (do not use) the \s-1MIPS\s0 Loongson MultiMedia extensions Instructions (\s-1MMI\s0). +.IP "\fB\-mloongson\-ext\fR" 4 +.IX Item "-mloongson-ext" +.PD 0 +.IP "\fB\-mno\-loongson\-ext\fR" 4 +.IX Item "-mno-loongson-ext" +.PD +Use (do not use) the \s-1MIPS\s0 Loongson EXTensions (\s-1EXT\s0) instructions. +.IP "\fB\-mloongson\-ext2\fR" 4 +.IX Item "-mloongson-ext2" +.PD 0 +.IP "\fB\-mno\-loongson\-ext2\fR" 4 +.IX Item "-mno-loongson-ext2" +.PD +Use (do not use) the \s-1MIPS\s0 Loongson EXTensions r2 (\s-1EXT2\s0) instructions. +.IP "\fB\-mlong64\fR" 4 +.IX Item "-mlong64" +Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for +an explanation of the default and the way that the pointer size is +determined. +.IP "\fB\-mlong32\fR" 4 +.IX Item "-mlong32" +Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. +.Sp +The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on +the \s-1ABI.\s0 All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use +32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, +or the same size as integer registers, whichever is smaller. +.IP "\fB\-msym32\fR" 4 +.IX Item "-msym32" +.PD 0 +.IP "\fB\-mno\-sym32\fR" 4 +.IX Item "-mno-sym32" +.PD +Assume (do not assume) that all symbols have 32\-bit values, regardless +of the selected \s-1ABI.\s0 This option is useful in combination with +\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 +to generate shorter and faster references to symbolic addresses. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put definitions of externally-visible data in a small data section +if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then generate +more efficient accesses to the data; see \fB\-mgpopt\fR for details. +.Sp +The default \fB\-G\fR option depends on the configuration. +.IP "\fB\-mlocal\-sdata\fR" 4 +.IX Item "-mlocal-sdata" +.PD 0 +.IP "\fB\-mno\-local\-sdata\fR" 4 +.IX Item "-mno-local-sdata" +.PD +Extend (do not extend) the \fB\-G\fR behavior to local data too, +such as to static variables in C. \fB\-mlocal\-sdata\fR is the +default for all configurations. +.Sp +If the linker complains that an application is using too much small data, +you might want to try rebuilding the less performance-critical parts with +\&\fB\-mno\-local\-sdata\fR. You might also want to build large +libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave +more room for the main program. +.IP "\fB\-mextern\-sdata\fR" 4 +.IX Item "-mextern-sdata" +.PD 0 +.IP "\fB\-mno\-extern\-sdata\fR" 4 +.IX Item "-mno-extern-sdata" +.PD +Assume (do not assume) that externally-defined data is in +a small data section if the size of that data is within the \fB\-G\fR limit. +\&\fB\-mextern\-sdata\fR is the default for all configurations. +.Sp +If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR +\&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR +that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR +is placed in a small data section. If \fIVar\fR is defined by another +module, you must either compile that module with a high-enough +\&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's +definition. If \fIVar\fR is common, you must link the application +with a high-enough \fB\-G\fR setting. +.Sp +The easiest way of satisfying these restrictions is to compile +and link every module with the same \fB\-G\fR option. However, +you may wish to build a library that supports several different +small data limits. You can do this by compiling the library with +the highest supported \fB\-G\fR setting and additionally using +\&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions +about externally-defined data. +.IP "\fB\-mgpopt\fR" 4 +.IX Item "-mgpopt" +.PD 0 +.IP "\fB\-mno\-gpopt\fR" 4 +.IX Item "-mno-gpopt" +.PD +Use (do not use) GP-relative accesses for symbols that are known to be +in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and +\&\fB\-mextern\-sdata\fR. \fB\-mgpopt\fR is the default for all +configurations. +.Sp +\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register +might not hold the value of \f(CW\*(C`_gp\*(C'\fR. For example, if the code is +part of a library that might be used in a boot monitor, programs that +call boot monitor routines pass an unknown value in \f(CW$gp\fR. +(In such situations, the boot monitor itself is usually compiled +with \fB\-G0\fR.) +.Sp +\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and +\&\fB\-mno\-extern\-sdata\fR. +.IP "\fB\-membedded\-data\fR" 4 +.IX Item "-membedded-data" +.PD 0 +.IP "\fB\-mno\-embedded\-data\fR" 4 +.IX Item "-mno-embedded-data" +.PD +Allocate variables to the read-only data section first if possible, then +next in the small data section if possible, otherwise in data. This gives +slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required +when executing, and thus may be preferred for some embedded systems. +.IP "\fB\-muninit\-const\-in\-rodata\fR" 4 +.IX Item "-muninit-const-in-rodata" +.PD 0 +.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4 +.IX Item "-mno-uninit-const-in-rodata" +.PD +Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section. +This option is only meaningful in conjunction with \fB\-membedded\-data\fR. +.IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4 +.IX Item "-mcode-readable=setting" +Specify whether \s-1GCC\s0 may generate code that reads from executable sections. +There are three possible settings: +.RS 4 +.IP "\fB\-mcode\-readable=yes\fR" 4 +.IX Item "-mcode-readable=yes" +Instructions may freely access executable sections. This is the +default setting. +.IP "\fB\-mcode\-readable=pcrel\fR" 4 +.IX Item "-mcode-readable=pcrel" +\&\s-1MIPS16\s0 PC-relative load instructions can access executable sections, +but other instructions must not do so. This option is useful on 4KSc +and 4KSd processors when the code TLBs have the Read Inhibit bit set. +It is also useful on processors that can be configured to have a dual +instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically +redirect PC-relative loads to the instruction \s-1RAM.\s0 +.IP "\fB\-mcode\-readable=no\fR" 4 +.IX Item "-mcode-readable=no" +Instructions must not access executable sections. This option can be +useful on targets that are configured to have a dual instruction/data +\&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect +PC-relative loads to the instruction \s-1RAM.\s0 +.RE +.RS 4 +.RE +.IP "\fB\-msplit\-addresses\fR" 4 +.IX Item "-msplit-addresses" +.PD 0 +.IP "\fB\-mno\-split\-addresses\fR" 4 +.IX Item "-mno-split-addresses" +.PD +Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler +relocation operators. This option has been superseded by +\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Use (do not use) assembler relocation operators when dealing with symbolic +addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR, +is to use assembler macros instead. +.Sp +\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured +to use an assembler that supports relocation operators. +.IP "\fB\-mcheck\-zero\-division\fR" 4 +.IX Item "-mcheck-zero-division" +.PD 0 +.IP "\fB\-mno\-check\-zero\-division\fR" 4 +.IX Item "-mno-check-zero-division" +.PD +Trap (do not trap) on integer division by zero. +.Sp +The default is \fB\-mcheck\-zero\-division\fR. +.IP "\fB\-mdivide\-traps\fR" 4 +.IX Item "-mdivide-traps" +.PD 0 +.IP "\fB\-mdivide\-breaks\fR" 4 +.IX Item "-mdivide-breaks" +.PD +\&\s-1MIPS\s0 systems check for division by zero by generating either a +conditional trap or a break instruction. Using traps results in +smaller code, but is only supported on \s-1MIPS II\s0 and later. Also, some +versions of the Linux kernel have a bug that prevents trap from +generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to +allow conditional traps on architectures that support them and +\&\fB\-mdivide\-breaks\fR to force the use of breaks. +.Sp +The default is usually \fB\-mdivide\-traps\fR, but this can be +overridden at configure time using \fB\-\-with\-divide=breaks\fR. +Divide-by-zero checks can be completely disabled using +\&\fB\-mno\-check\-zero\-division\fR. +.IP "\fB\-mload\-store\-pairs\fR" 4 +.IX Item "-mload-store-pairs" +.PD 0 +.IP "\fB\-mno\-load\-store\-pairs\fR" 4 +.IX Item "-mno-load-store-pairs" +.PD +Enable (disable) an optimization that pairs consecutive load or store +instructions to enable load/store bonding. This option is enabled by +default but only takes effect when the selected architecture is known +to support bonding. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +.PD 0 +.IP "\fB\-mno\-memcpy\fR" 4 +.IX Item "-mno-memcpy" +.PD +Force (do not force) the use of \f(CW\*(C`memcpy\*(C'\fR for non-trivial block +moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline +most constant-sized copies. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling +functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller +and callee to be in the same 256 megabyte segment. +.Sp +This option has no effect on abicalls code. The default is +\&\fB\-mno\-long\-calls\fR. +.IP "\fB\-mmad\fR" 4 +.IX Item "-mmad" +.PD 0 +.IP "\fB\-mno\-mad\fR" 4 +.IX Item "-mno-mad" +.PD +Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR +instructions, as provided by the R4650 \s-1ISA.\s0 +.IP "\fB\-mimadd\fR" 4 +.IX Item "-mimadd" +.PD 0 +.IP "\fB\-mno\-imadd\fR" 4 +.IX Item "-mno-imadd" +.PD +Enable (disable) use of the \f(CW\*(C`madd\*(C'\fR and \f(CW\*(C`msub\*(C'\fR integer +instructions. The default is \fB\-mimadd\fR on architectures +that support \f(CW\*(C`madd\*(C'\fR and \f(CW\*(C`msub\*(C'\fR except for the 74k +architecture where it was found to generate slower code. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable (disable) use of the floating-point multiply-accumulate +instructions, when they are available. The default is +\&\fB\-mfused\-madd\fR. +.Sp +On the R8000 \s-1CPU\s0 when multiply-accumulate instructions are used, +the intermediate product is calculated to infinite precision +and is not subject to the \s-1FCSR\s0 Flush to Zero bit. This may be +undesirable in some circumstances. On other processors the result +is numerically identical to the equivalent computation using +separate multiply, add, subtract and negate instructions. +.IP "\fB\-nocpp\fR" 4 +.IX Item "-nocpp" +Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user +assembler files (with a \fB.s\fR suffix) when assembling them. +.IP "\fB\-mfix\-24k\fR" 4 +.IX Item "-mfix-24k" +.PD 0 +.IP "\fB\-mno\-fix\-24k\fR" 4 +.IX Item "-mno-fix-24k" +.PD +Work around the 24K E48 (lost data on stores during refill) errata. +The workarounds are implemented by the assembler rather than by \s-1GCC.\s0 +.IP "\fB\-mfix\-r4000\fR" 4 +.IX Item "-mfix-r4000" +.PD 0 +.IP "\fB\-mno\-fix\-r4000\fR" 4 +.IX Item "-mno-fix-r4000" +.PD +Work around certain R4000 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +while an integer multiplication is in progress. +.IP "\-" 4 +An integer division may give an incorrect result if started in a delay slot +of a taken branch or a jump. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r4400\fR" 4 +.IX Item "-mfix-r4400" +.PD 0 +.IP "\fB\-mno\-fix\-r4400\fR" 4 +.IX Item "-mno-fix-r4400" +.PD +Work around certain R4400 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r10000\fR" 4 +.IX Item "-mfix-r10000" +.PD 0 +.IP "\fB\-mno\-fix\-r10000\fR" 4 +.IX Item "-mno-fix-r10000" +.PD +Work around certain R10000 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`ll\*(C'\fR/\f(CW\*(C`sc\*(C'\fR sequences may not behave atomically on revisions +prior to 3.0. They may deadlock on revisions 2.6 and earlier. +.RE +.RS 4 +.Sp +This option can only be used if the target architecture supports +branch-likely instructions. \fB\-mfix\-r10000\fR is the default when +\&\fB\-march=r10000\fR is used; \fB\-mno\-fix\-r10000\fR is the default +otherwise. +.RE +.IP "\fB\-mfix\-r5900\fR" 4 +.IX Item "-mfix-r5900" +.PD 0 +.IP "\fB\-mno\-fix\-r5900\fR" 4 +.IX Item "-mno-fix-r5900" +.PD +Do not attempt to schedule the preceding instruction into the delay slot +of a branch instruction placed at the end of a short loop of six +instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction there +instead. The short loop bug under certain conditions causes loops to +execute only once or twice, due to a hardware bug in the R5900 chip. The +workaround is implemented by the assembler rather than by \s-1GCC.\s0 +.IP "\fB\-mfix\-rm7000\fR" 4 +.IX Item "-mfix-rm7000" +.PD 0 +.IP "\fB\-mno\-fix\-rm7000\fR" 4 +.IX Item "-mno-fix-rm7000" +.PD +Work around the \s-1RM7000\s0 \f(CW\*(C`dmult\*(C'\fR/\f(CW\*(C`dmultu\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC.\s0 +.IP "\fB\-mfix\-vr4120\fR" 4 +.IX Item "-mfix-vr4120" +.PD 0 +.IP "\fB\-mno\-fix\-vr4120\fR" 4 +.IX Item "-mno-fix-vr4120" +.PD +Work around certain \s-1VR4120\s0 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result. +.IP "\-" 4 +\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one +of the operands is negative. +.RE +.RS 4 +.Sp +The workarounds for the division errata rely on special functions in +\&\fIlibgcc.a\fR. At present, these functions are only provided by +the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations. +.Sp +Other \s-1VR4120\s0 errata require a \s-1NOP\s0 to be inserted between certain pairs of +instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself. +.RE +.IP "\fB\-mfix\-vr4130\fR" 4 +.IX Item "-mfix-vr4130" +Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC,\s0 +although \s-1GCC\s0 avoids using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the +\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +instructions are available instead. +.IP "\fB\-mfix\-sb1\fR" 4 +.IX Item "-mfix-sb1" +.PD 0 +.IP "\fB\-mno\-fix\-sb1\fR" 4 +.IX Item "-mno-fix-sb1" +.PD +Work around certain \s-1SB\-1 CPU\s0 core errata. +(This flag currently works around the \s-1SB\-1\s0 revision 2 +\&\*(L"F1\*(R" and \*(L"F2\*(R" floating-point errata.) +.IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 +.IX Item "-mr10k-cache-barrier=setting" +Specify whether \s-1GCC\s0 should insert cache barriers to avoid the +side effects of speculation on R10K processors. +.Sp +In common with many processors, the R10K tries to predict the outcome +of a conditional branch and speculatively executes instructions from +the \*(L"taken\*(R" branch. It later aborts these instructions if the +predicted outcome is wrong. However, on the R10K, even aborted +instructions can have side effects. +.Sp +This problem only affects kernel stores and, depending on the system, +kernel loads. As an example, a speculatively-executed store may load +the target memory into cache and mark the cache line as dirty, even if +the store itself is later aborted. If a \s-1DMA\s0 operation writes to the +same area of memory before the \*(L"dirty\*(R" line is flushed, the cached +data overwrites the DMA-ed data. See the R10K processor manual +for a full description, including other potential problems. +.Sp +One workaround is to insert cache barrier instructions before every memory +access that might be speculatively executed and that might have side +effects even if aborted. \fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR +controls \s-1GCC\s0's implementation of this workaround. It assumes that +aborted accesses to any byte in the following regions does not have +side effects: +.RS 4 +.IP "1." 4 +.IX Item "1." +the memory occupied by the current function's stack frame; +.IP "2." 4 +.IX Item "2." +the memory occupied by an incoming stack argument; +.IP "3." 4 +.IX Item "3." +the memory occupied by an object with a link-time-constant address. +.RE +.RS 4 +.Sp +It is the kernel's responsibility to ensure that speculative +accesses to these regions are indeed safe. +.Sp +If the input program contains a function declaration such as: +.Sp +.Vb 1 +\& void foo (void); +.Ve +.Sp +then the implementation of \f(CW\*(C`foo\*(C'\fR must allow \f(CW\*(C`j foo\*(C'\fR and +\&\f(CW\*(C`jal foo\*(C'\fR to be executed speculatively. \s-1GCC\s0 honors this +restriction for functions it compiles itself. It expects non-GCC +functions (such as hand-written assembly code) to do the same. +.Sp +The option has three forms: +.IP "\fB\-mr10k\-cache\-barrier=load\-store\fR" 4 +.IX Item "-mr10k-cache-barrier=load-store" +Insert a cache barrier before a load or store that might be +speculatively executed and that might have side effects even +if aborted. +.IP "\fB\-mr10k\-cache\-barrier=store\fR" 4 +.IX Item "-mr10k-cache-barrier=store" +Insert a cache barrier before a store that might be speculatively +executed and that might have side effects even if aborted. +.IP "\fB\-mr10k\-cache\-barrier=none\fR" 4 +.IX Item "-mr10k-cache-barrier=none" +Disable the insertion of cache barriers. This is the default setting. +.RE +.RS 4 +.RE +.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4 +.IX Item "-mflush-func=func" +.PD 0 +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +.PD +Specifies the function to call to flush the I and D caches, or to not +call any such function. If called, the function must take the same +arguments as the common \f(CW\*(C`_flush_func\*(C'\fR, that is, the address of the +memory range for which the cache is being flushed, the size of the +memory range, and the number 3 (to flush both caches). The default +depends on the target \s-1GCC\s0 was configured for, but commonly is either +\&\f(CW\*(C`_flush_func\*(C'\fR or \f(CW\*(C`_\|_cpu_flush\*(C'\fR. +.IP "\fBmbranch\-cost=\fR\fInum\fR" 4 +.IX Item "mbranch-cost=num" +Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. A zero cost redundantly selects +the default, which is based on the \fB\-mtune\fR setting. +.IP "\fB\-mbranch\-likely\fR" 4 +.IX Item "-mbranch-likely" +.PD 0 +.IP "\fB\-mno\-branch\-likely\fR" 4 +.IX Item "-mno-branch-likely" +.PD +Enable or disable use of Branch Likely instructions, regardless of the +default for the selected architecture. By default, Branch Likely +instructions may be generated if they are supported by the selected +architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures +and processors that implement those architectures; for those, Branch +Likely instructions are not be generated by default because the \s-1MIPS32\s0 +and \s-1MIPS64\s0 architectures specifically deprecate their use. +.IP "\fB\-mcompact\-branches=never\fR" 4 +.IX Item "-mcompact-branches=never" +.PD 0 +.IP "\fB\-mcompact\-branches=optimal\fR" 4 +.IX Item "-mcompact-branches=optimal" +.IP "\fB\-mcompact\-branches=always\fR" 4 +.IX Item "-mcompact-branches=always" +.PD +These options control which form of branches will be generated. The +default is \fB\-mcompact\-branches=optimal\fR. +.Sp +The \fB\-mcompact\-branches=never\fR option ensures that compact branch +instructions will never be generated. +.Sp +The \fB\-mcompact\-branches=always\fR option ensures that a compact +branch instruction will be generated if available. If a compact branch +instruction is not available, a delay slot form of the branch will be +used instead. +.Sp +This option is supported from \s-1MIPS\s0 Release 6 onwards. +.Sp +The \fB\-mcompact\-branches=optimal\fR option will cause a delay slot +branch to be used if one is available in the current \s-1ISA\s0 and the delay +slot is successfully filled. If the delay slot is not filled, a compact +branch will be chosen if one is available. +.IP "\fB\-mfp\-exceptions\fR" 4 +.IX Item "-mfp-exceptions" +.PD 0 +.IP "\fB\-mno\-fp\-exceptions\fR" 4 +.IX Item "-mno-fp-exceptions" +.PD +Specifies whether \s-1FP\s0 exceptions are enabled. This affects how +\&\s-1FP\s0 instructions are scheduled for some processors. +The default is that \s-1FP\s0 exceptions are +enabled. +.Sp +For instance, on the \s-1SB\-1,\s0 if \s-1FP\s0 exceptions are disabled, and we are emitting +64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one +\&\s-1FP\s0 pipe. +.IP "\fB\-mvr4130\-align\fR" 4 +.IX Item "-mvr4130-align" +.PD 0 +.IP "\fB\-mno\-vr4130\-align\fR" 4 +.IX Item "-mno-vr4130-align" +.PD +The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two +instructions together if the first one is 8\-byte aligned. When this +option is enabled, \s-1GCC\s0 aligns pairs of instructions that it +thinks should execute in parallel. +.Sp +This option only has an effect when optimizing for the \s-1VR4130.\s0 +It normally makes code faster, but at the expense of making it bigger. +It is enabled by default at optimization level \fB\-O3\fR. +.IP "\fB\-msynci\fR" 4 +.IX Item "-msynci" +.PD 0 +.IP "\fB\-mno\-synci\fR" 4 +.IX Item "-mno-synci" +.PD +Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on +architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if +enabled) are generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache\*(C'\fR is +compiled. +.Sp +This option defaults to \fB\-mno\-synci\fR, but the default can be +overridden by configuring \s-1GCC\s0 with \fB\-\-with\-synci\fR. +.Sp +When compiling code for single processor systems, it is generally safe +to use \f(CW\*(C`synci\*(C'\fR. However, on many multi-core (\s-1SMP\s0) systems, it +does not invalidate the instruction caches on all cores and may lead +to undefined behavior. +.IP "\fB\-mrelax\-pic\-calls\fR" 4 +.IX Item "-mrelax-pic-calls" +.PD 0 +.IP "\fB\-mno\-relax\-pic\-calls\fR" 4 +.IX Item "-mno-relax-pic-calls" +.PD +Try to turn \s-1PIC\s0 calls that are normally dispatched via register +\&\f(CW$25\fR into direct calls. This is only possible if the linker can +resolve the destination at link time and if the destination is within +range for a direct call. +.Sp +\&\fB\-mrelax\-pic\-calls\fR is the default if \s-1GCC\s0 was configured to use +an assembler and a linker that support the \f(CW\*(C`.reloc\*(C'\fR assembly +directive and \fB\-mexplicit\-relocs\fR is in effect. With +\&\fB\-mno\-explicit\-relocs\fR, this optimization can be performed by the +assembler and the linker alone without help from the compiler. +.IP "\fB\-mmcount\-ra\-address\fR" 4 +.IX Item "-mmcount-ra-address" +.PD 0 +.IP "\fB\-mno\-mcount\-ra\-address\fR" 4 +.IX Item "-mno-mcount-ra-address" +.PD +Emit (do not emit) code that allows \f(CW\*(C`_mcount\*(C'\fR to modify the +calling function's return address. When enabled, this option extends +the usual \f(CW\*(C`_mcount\*(C'\fR interface with a new \fIra-address\fR +parameter, which has type \f(CW\*(C`intptr_t *\*(C'\fR and is passed in register +\&\f(CW$12\fR. \f(CW\*(C`_mcount\*(C'\fR can then modify the return address by +doing both of the following: +.RS 4 +.IP "*" 4 +Returning the new address in register \f(CW$31\fR. +.IP "*" 4 +Storing the new address in \f(CW\*(C`*\f(CIra\-address\f(CW\*(C'\fR, +if \fIra-address\fR is nonnull. +.RE +.RS 4 +.Sp +The default is \fB\-mno\-mcount\-ra\-address\fR. +.RE +.IP "\fB\-mframe\-header\-opt\fR" 4 +.IX Item "-mframe-header-opt" +.PD 0 +.IP "\fB\-mno\-frame\-header\-opt\fR" 4 +.IX Item "-mno-frame-header-opt" +.PD +Enable (disable) frame header optimization in the o32 \s-1ABI.\s0 When using the +o32 \s-1ABI,\s0 calling functions will allocate 16 bytes on the stack for the called +function to write out register arguments. When enabled, this optimization +will suppress the allocation of the frame header if it can be determined that +it is unused. +.Sp +This optimization is off by default at all optimization levels. +.IP "\fB\-mlxc1\-sxc1\fR" 4 +.IX Item "-mlxc1-sxc1" +.PD 0 +.IP "\fB\-mno\-lxc1\-sxc1\fR" 4 +.IX Item "-mno-lxc1-sxc1" +.PD +When applicable, enable (disable) the generation of \f(CW\*(C`lwxc1\*(C'\fR, +\&\f(CW\*(C`swxc1\*(C'\fR, \f(CW\*(C`ldxc1\*(C'\fR, \f(CW\*(C`sdxc1\*(C'\fR instructions. Enabled by default. +.IP "\fB\-mmadd4\fR" 4 +.IX Item "-mmadd4" +.PD 0 +.IP "\fB\-mno\-madd4\fR" 4 +.IX Item "-mno-madd4" +.PD +When applicable, enable (disable) the generation of 4\-operand \f(CW\*(C`madd.s\*(C'\fR, +\&\f(CW\*(C`madd.d\*(C'\fR and related instructions. Enabled by default. +.PP +\fI\s-1MMIX\s0 Options\fR +.IX Subsection "MMIX Options" +.PP +These options are defined for the \s-1MMIX:\s0 +.IP "\fB\-mlibfuncs\fR" 4 +.IX Item "-mlibfuncs" +.PD 0 +.IP "\fB\-mno\-libfuncs\fR" 4 +.IX Item "-mno-libfuncs" +.PD +Specify that intrinsic library functions are being compiled, passing all +values in registers, no matter the size. +.IP "\fB\-mepsilon\fR" 4 +.IX Item "-mepsilon" +.PD 0 +.IP "\fB\-mno\-epsilon\fR" 4 +.IX Item "-mno-epsilon" +.PD +Generate floating-point comparison instructions that compare with respect +to the \f(CW\*(C`rE\*(C'\fR epsilon register. +.IP "\fB\-mabi=mmixware\fR" 4 +.IX Item "-mabi=mmixware" +.PD 0 +.IP "\fB\-mabi=gnu\fR" 4 +.IX Item "-mabi=gnu" +.PD +Generate code that passes function parameters and return values that (in +the called function) are seen as registers \f(CW$0\fR and up, as opposed to +the \s-1GNU ABI\s0 which uses global registers \f(CW$231\fR and up. +.IP "\fB\-mzero\-extend\fR" 4 +.IX Item "-mzero-extend" +.PD 0 +.IP "\fB\-mno\-zero\-extend\fR" 4 +.IX Item "-mno-zero-extend" +.PD +When reading data from memory in sizes shorter than 64 bits, use (do not +use) zero-extending load instructions by default, rather than +sign-extending ones. +.IP "\fB\-mknuthdiv\fR" 4 +.IX Item "-mknuthdiv" +.PD 0 +.IP "\fB\-mno\-knuthdiv\fR" 4 +.IX Item "-mno-knuthdiv" +.PD +Make the result of a division yielding a remainder have the same sign as +the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the +remainder follows the sign of the dividend. Both methods are +arithmetically valid, the latter being almost exclusively used. +.IP "\fB\-mtoplevel\-symbols\fR" 4 +.IX Item "-mtoplevel-symbols" +.PD 0 +.IP "\fB\-mno\-toplevel\-symbols\fR" 4 +.IX Item "-mno-toplevel-symbols" +.PD +Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly +code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Generate an executable in the \s-1ELF\s0 format, rather than the default +\&\fBmmo\fR format used by the \fBmmix\fR simulator. +.IP "\fB\-mbranch\-predict\fR" 4 +.IX Item "-mbranch-predict" +.PD 0 +.IP "\fB\-mno\-branch\-predict\fR" 4 +.IX Item "-mno-branch-predict" +.PD +Use (do not use) the probable-branch instructions, when static branch +prediction indicates a probable branch. +.IP "\fB\-mbase\-addresses\fR" 4 +.IX Item "-mbase-addresses" +.PD 0 +.IP "\fB\-mno\-base\-addresses\fR" 4 +.IX Item "-mno-base-addresses" +.PD +Generate (do not generate) code that uses \fIbase addresses\fR. Using a +base address automatically generates a request (handled by the assembler +and the linker) for a constant to be set up in a global register. The +register is used for one or more base address requests within the range 0 +to 255 from the value held in the register. The generally leads to short +and fast code, but the number of different data items that can be +addressed is limited. This means that a program that uses lots of static +data may require \fB\-mno\-base\-addresses\fR. +.IP "\fB\-msingle\-exit\fR" 4 +.IX Item "-msingle-exit" +.PD 0 +.IP "\fB\-mno\-single\-exit\fR" 4 +.IX Item "-mno-single-exit" +.PD +Force (do not force) generated code to have a single exit point in each +function. +.PP +\fI\s-1MN10300\s0 Options\fR +.IX Subsection "MN10300 Options" +.PP +These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures: +.IP "\fB\-mmult\-bug\fR" 4 +.IX Item "-mmult-bug" +Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0 +processors. This is the default. +.IP "\fB\-mno\-mult\-bug\fR" 4 +.IX Item "-mno-mult-bug" +Do not generate code to avoid bugs in the multiply instructions for the +\&\s-1MN10300\s0 processors. +.IP "\fB\-mam33\fR" 4 +.IX Item "-mam33" +Generate code using features specific to the \s-1AM33\s0 processor. +.IP "\fB\-mno\-am33\fR" 4 +.IX Item "-mno-am33" +Do not generate code using features specific to the \s-1AM33\s0 processor. This +is the default. +.IP "\fB\-mam33\-2\fR" 4 +.IX Item "-mam33-2" +Generate code using features specific to the \s-1AM33/2.0\s0 processor. +.IP "\fB\-mam34\fR" 4 +.IX Item "-mam34" +Generate code using features specific to the \s-1AM34\s0 processor. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Use the timing characteristics of the indicated \s-1CPU\s0 type when +scheduling instructions. This does not change the targeted processor +type. The \s-1CPU\s0 type must be one of \fBmn10300\fR, \fBam33\fR, +\&\fBam33\-2\fR or \fBam34\fR. +.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4 +.IX Item "-mreturn-pointer-on-d0" +When generating a function that returns a pointer, return the pointer +in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned +only in \f(CW\*(C`a0\*(C'\fR, and attempts to call such functions without a prototype +result in errors. Note that this option is on by default; use +\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it. +.IP "\fB\-mno\-crt0\fR" 4 +.IX Item "-mno-crt0" +Do not link in the C run-time initialization object file. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Indicate to the linker that it should perform a relaxation optimization pass +to shorten branches, calls and absolute memory addresses. This option only +has an effect when used on the command line for the final link step. +.Sp +This option makes symbolic debugging impossible. +.IP "\fB\-mliw\fR" 4 +.IX Item "-mliw" +Allow the compiler to generate \fILong Instruction Word\fR +instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the +default. This option defines the preprocessor macro \f(CW\*(C`_\|_LIW_\|_\*(C'\fR. +.IP "\fB\-mno\-liw\fR" 4 +.IX Item "-mno-liw" +Do not allow the compiler to generate \fILong Instruction Word\fR +instructions. This option defines the preprocessor macro +\&\f(CW\*(C`_\|_NO_LIW_\|_\*(C'\fR. +.IP "\fB\-msetlb\fR" 4 +.IX Item "-msetlb" +Allow the compiler to generate the \fI\s-1SETLB\s0\fR and \fILcc\fR +instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the +default. This option defines the preprocessor macro \f(CW\*(C`_\|_SETLB_\|_\*(C'\fR. +.IP "\fB\-mno\-setlb\fR" 4 +.IX Item "-mno-setlb" +Do not allow the compiler to generate \fI\s-1SETLB\s0\fR or \fILcc\fR +instructions. This option defines the preprocessor macro +\&\f(CW\*(C`_\|_NO_SETLB_\|_\*(C'\fR. +.PP +\fIMoxie Options\fR +.IX Subsection "Moxie Options" +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Generate big-endian code. This is the default for \fBmoxie\-*\-*\fR +configurations. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Generate little-endian code. +.IP "\fB\-mmul.x\fR" 4 +.IX Item "-mmul.x" +Generate mul.x and umul.x instructions. This is the default for +\&\fBmoxiebox\-*\-*\fR configurations. +.IP "\fB\-mno\-crt0\fR" 4 +.IX Item "-mno-crt0" +Do not link in the C run-time initialization object file. +.PP +\fI\s-1MSP430\s0 Options\fR +.IX Subsection "MSP430 Options" +.PP +These options are defined for the \s-1MSP430:\s0 +.IP "\fB\-masm\-hex\fR" 4 +.IX Item "-masm-hex" +Force assembly output to always use hex constants. Normally such +constants are signed decimals, but this option is available for +testsuite and/or aesthetic purposes. +.IP "\fB\-mmcu=\fR" 4 +.IX Item "-mmcu=" +Select the \s-1MCU\s0 to target. This is used to create a C preprocessor +symbol based upon the \s-1MCU\s0 name, converted to upper case and pre\- and +post-fixed with \fB_\|_\fR. This in turn is used by the +\&\fImsp430.h\fR header file to select an MCU-specific supplementary +header file. +.Sp +The option also sets the \s-1ISA\s0 to use. If the \s-1MCU\s0 name is one that is +known to only support the 430 \s-1ISA\s0 then that is selected, otherwise the +430X \s-1ISA\s0 is selected. A generic \s-1MCU\s0 name of \fBmsp430\fR can also be +used to select the 430 \s-1ISA.\s0 Similarly the generic \fBmsp430x\fR \s-1MCU\s0 +name selects the 430X \s-1ISA.\s0 +.Sp +In addition an MCU-specific linker script is added to the linker +command line. The script's name is the name of the \s-1MCU\s0 with +\&\fI.ld\fR appended. Thus specifying \fB\-mmcu=xxx\fR on the \fBgcc\fR +command line defines the C preprocessor symbol \f(CW\*(C`_\|_XXX_\|_\*(C'\fR and +cause the linker to search for a script called \fIxxx.ld\fR. +.Sp +This option is also passed on to the assembler. +.IP "\fB\-mwarn\-mcu\fR" 4 +.IX Item "-mwarn-mcu" +.PD 0 +.IP "\fB\-mno\-warn\-mcu\fR" 4 +.IX Item "-mno-warn-mcu" +.PD +This option enables or disables warnings about conflicts between the +\&\s-1MCU\s0 name specified by the \fB\-mmcu\fR option and the \s-1ISA\s0 set by the +\&\fB\-mcpu\fR option and/or the hardware multiply support set by the +\&\fB\-mhwmult\fR option. It also toggles warnings about unrecognized +\&\s-1MCU\s0 names. This option is on by default. +.IP "\fB\-mcpu=\fR" 4 +.IX Item "-mcpu=" +Specifies the \s-1ISA\s0 to use. Accepted values are \fBmsp430\fR, +\&\fBmsp430x\fR and \fBmsp430xv2\fR. This option is deprecated. The +\&\fB\-mmcu=\fR option should be used to select the \s-1ISA.\s0 +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Link to the simulator runtime libraries and linker script. Overrides +any scripts that would be selected by the \fB\-mmcu=\fR option. +.IP "\fB\-mlarge\fR" 4 +.IX Item "-mlarge" +Use large-model addressing (20\-bit pointers, 32\-bit \f(CW\*(C`size_t\*(C'\fR). +.IP "\fB\-msmall\fR" 4 +.IX Item "-msmall" +Use small-model addressing (16\-bit pointers, 16\-bit \f(CW\*(C`size_t\*(C'\fR). +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +This option is passed to the assembler and linker, and allows the +linker to perform certain optimizations that cannot be done until +the final link. +.IP "\fBmhwmult=\fR" 4 +.IX Item "mhwmult=" +Describes the type of hardware multiply supported by the target. +Accepted values are \fBnone\fR for no hardware multiply, \fB16bit\fR +for the original 16\-bit\-only multiply supported by early MCUs. +\&\fB32bit\fR for the 16/32\-bit multiply supported by later MCUs and +\&\fBf5series\fR for the 16/32\-bit multiply supported by F5\-series MCUs. +A value of \fBauto\fR can also be given. This tells \s-1GCC\s0 to deduce +the hardware multiply support based upon the \s-1MCU\s0 name provided by the +\&\fB\-mmcu\fR option. If no \fB\-mmcu\fR option is specified or if +the \s-1MCU\s0 name is not recognized then no hardware multiply support is +assumed. \f(CW\*(C`auto\*(C'\fR is the default setting. +.Sp +Hardware multiplies are normally performed by calling a library +routine. This saves space in the generated code. When compiling at +\&\fB\-O3\fR or higher however the hardware multiplier is invoked +inline. This makes for bigger, but faster code. +.Sp +The hardware multiply routines disable interrupts whilst running and +restore the previous interrupt state when they finish. This makes +them safe to use inside interrupt handlers as well as in normal code. +.IP "\fB\-minrt\fR" 4 +.IX Item "-minrt" +Enable the use of a minimum runtime environment \- no static +initializers or constructors. This is intended for memory-constrained +devices. The compiler includes special symbols in some objects +that tell the linker and runtime which code fragments are required. +.IP "\fB\-mcode\-region=\fR" 4 +.IX Item "-mcode-region=" +.PD 0 +.IP "\fB\-mdata\-region=\fR" 4 +.IX Item "-mdata-region=" +.PD +These options tell the compiler where to place functions and data that +do not have one of the \f(CW\*(C`lower\*(C'\fR, \f(CW\*(C`upper\*(C'\fR, \f(CW\*(C`either\*(C'\fR or +\&\f(CW\*(C`section\*(C'\fR attributes. Possible values are \f(CW\*(C`lower\*(C'\fR, +\&\f(CW\*(C`upper\*(C'\fR, \f(CW\*(C`either\*(C'\fR or \f(CW\*(C`any\*(C'\fR. The first three behave +like the corresponding attribute. The fourth possible value \- +\&\f(CW\*(C`any\*(C'\fR \- is the default. It leaves placement entirely up to the +linker script and how it assigns the standard sections +(\f(CW\*(C`.text\*(C'\fR, \f(CW\*(C`.data\*(C'\fR, etc) to the memory regions. +.IP "\fB\-msilicon\-errata=\fR" 4 +.IX Item "-msilicon-errata=" +This option passes on a request to assembler to enable the fixes for +the named silicon errata. +.IP "\fB\-msilicon\-errata\-warn=\fR" 4 +.IX Item "-msilicon-errata-warn=" +This option passes on a request to the assembler to enable warning +messages when a silicon errata might need to be applied. +.PP +\fI\s-1NDS32\s0 Options\fR +.IX Subsection "NDS32 Options" +.PP +These options are defined for \s-1NDS32\s0 implementations: +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code in big-endian mode. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code in little-endian mode. +.IP "\fB\-mreduced\-regs\fR" 4 +.IX Item "-mreduced-regs" +Use reduced-set registers for register allocation. +.IP "\fB\-mfull\-regs\fR" 4 +.IX Item "-mfull-regs" +Use full-set registers for register allocation. +.IP "\fB\-mcmov\fR" 4 +.IX Item "-mcmov" +Generate conditional move instructions. +.IP "\fB\-mno\-cmov\fR" 4 +.IX Item "-mno-cmov" +Do not generate conditional move instructions. +.IP "\fB\-mext\-perf\fR" 4 +.IX Item "-mext-perf" +Generate performance extension instructions. +.IP "\fB\-mno\-ext\-perf\fR" 4 +.IX Item "-mno-ext-perf" +Do not generate performance extension instructions. +.IP "\fB\-mext\-perf2\fR" 4 +.IX Item "-mext-perf2" +Generate performance extension 2 instructions. +.IP "\fB\-mno\-ext\-perf2\fR" 4 +.IX Item "-mno-ext-perf2" +Do not generate performance extension 2 instructions. +.IP "\fB\-mext\-string\fR" 4 +.IX Item "-mext-string" +Generate string extension instructions. +.IP "\fB\-mno\-ext\-string\fR" 4 +.IX Item "-mno-ext-string" +Do not generate string extension instructions. +.IP "\fB\-mv3push\fR" 4 +.IX Item "-mv3push" +Generate v3 push25/pop25 instructions. +.IP "\fB\-mno\-v3push\fR" 4 +.IX Item "-mno-v3push" +Do not generate v3 push25/pop25 instructions. +.IP "\fB\-m16\-bit\fR" 4 +.IX Item "-m16-bit" +Generate 16\-bit instructions. +.IP "\fB\-mno\-16\-bit\fR" 4 +.IX Item "-mno-16-bit" +Do not generate 16\-bit instructions. +.IP "\fB\-misr\-vector\-size=\fR\fInum\fR" 4 +.IX Item "-misr-vector-size=num" +Specify the size of each interrupt vector, which must be 4 or 16. +.IP "\fB\-mcache\-block\-size=\fR\fInum\fR" 4 +.IX Item "-mcache-block-size=num" +Specify the size of each cache block, +which must be a power of 2 between 4 and 512. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Specify the name of the target architecture. +.IP "\fB\-mcmodel=\fR\fIcode-model\fR" 4 +.IX Item "-mcmodel=code-model" +Set the code model to one of +.RS 4 +.IP "\fBsmall\fR" 4 +.IX Item "small" +All the data and read-only data segments must be within 512KB addressing space. +The text segment must be within 16MB addressing space. +.IP "\fBmedium\fR" 4 +.IX Item "medium" +The data segment must be within 512KB while the read-only data segment can be +within 4GB addressing space. The text segment should be still within 16MB +addressing space. +.IP "\fBlarge\fR" 4 +.IX Item "large" +All the text and data segments can be within 4GB addressing space. +.RE +.RS 4 +.RE +.IP "\fB\-mctor\-dtor\fR" 4 +.IX Item "-mctor-dtor" +Enable constructor/destructor feature. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Guide linker to relax instructions. +.PP +\fINios \s-1II\s0 Options\fR +.IX Subsection "Nios II Options" +.PP +These are the options defined for the Altera Nios \s-1II\s0 processor. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put global and static objects less than or equal to \fInum\fR bytes +into the small data or \s-1BSS\s0 sections instead of the normal data or \s-1BSS\s0 +sections. The default value of \fInum\fR is 8. +.IP "\fB\-mgpopt=\fR\fIoption\fR" 4 +.IX Item "-mgpopt=option" +.PD 0 +.IP "\fB\-mgpopt\fR" 4 +.IX Item "-mgpopt" +.IP "\fB\-mno\-gpopt\fR" 4 +.IX Item "-mno-gpopt" +.PD +Generate (do not generate) GP-relative accesses. The following +\&\fIoption\fR names are recognized: +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +Do not generate GP-relative accesses. +.IP "\fBlocal\fR" 4 +.IX Item "local" +Generate GP-relative accesses for small data objects that are not +external, weak, or uninitialized common symbols. +Also use GP-relative addressing for objects that +have been explicitly placed in a small data section via a \f(CW\*(C`section\*(C'\fR +attribute. +.IP "\fBglobal\fR" 4 +.IX Item "global" +As for \fBlocal\fR, but also generate GP-relative accesses for +small data objects that are external, weak, or common. If you use this option, +you must ensure that all parts of your program (including libraries) are +compiled with the same \fB\-G\fR setting. +.IP "\fBdata\fR" 4 +.IX Item "data" +Generate GP-relative accesses for all data objects in the program. If you +use this option, the entire data and \s-1BSS\s0 segments +of your program must fit in 64K of memory and you must use an appropriate +linker script to allocate them within the addressable range of the +global pointer. +.IP "\fBall\fR" 4 +.IX Item "all" +Generate GP-relative addresses for function pointers as well as data +pointers. If you use this option, the entire text, data, and \s-1BSS\s0 segments +of your program must fit in 64K of memory and you must use an appropriate +linker script to allocate them within the addressable range of the +global pointer. +.RE +.RS 4 +.Sp +\&\fB\-mgpopt\fR is equivalent to \fB\-mgpopt=local\fR, and +\&\fB\-mno\-gpopt\fR is equivalent to \fB\-mgpopt=none\fR. +.Sp +The default is \fB\-mgpopt\fR except when \fB\-fpic\fR or +\&\fB\-fPIC\fR is specified to generate position-independent code. +Note that the Nios \s-1II ABI\s0 does not permit GP-relative accesses from +shared libraries. +.Sp +You may need to specify \fB\-mno\-gpopt\fR explicitly when building +programs that include large amounts of small data, including large +\&\s-1GOT\s0 data sections. In this case, the 16\-bit offset for GP-relative +addressing may not be large enough to allow access to the entire +small data section. +.RE +.IP "\fB\-mgprel\-sec=\fR\fIregexp\fR" 4 +.IX Item "-mgprel-sec=regexp" +This option specifies additional section names that can be accessed via +GP-relative addressing. It is most useful in conjunction with +\&\f(CW\*(C`section\*(C'\fR attributes on variable declarations and a custom linker script. +The \fIregexp\fR is a \s-1POSIX\s0 Extended Regular Expression. +.Sp +This option does not affect the behavior of the \fB\-G\fR option, and +the specified sections are in addition to the standard \f(CW\*(C`.sdata\*(C'\fR +and \f(CW\*(C`.sbss\*(C'\fR small-data sections that are recognized by \fB\-mgpopt\fR. +.IP "\fB\-mr0rel\-sec=\fR\fIregexp\fR" 4 +.IX Item "-mr0rel-sec=regexp" +This option specifies names of sections that can be accessed via a +16\-bit offset from \f(CW\*(C`r0\*(C'\fR; that is, in the low 32K or high 32K +of the 32\-bit address space. It is most useful in conjunction with +\&\f(CW\*(C`section\*(C'\fR attributes on variable declarations and a custom linker script. +The \fIregexp\fR is a \s-1POSIX\s0 Extended Regular Expression. +.Sp +In contrast to the use of GP-relative addressing for small data, +zero-based addressing is never generated by default and there are no +conventional section names used in standard linker scripts for sections +in the low or high areas of memory. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +.PD 0 +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +.PD +Generate little-endian (default) or big-endian (experimental) code, +respectively. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +This specifies the name of the target Nios \s-1II\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. Permissible names are: \fBr1\fR, \fBr2\fR. +.Sp +The preprocessor macro \f(CW\*(C`_\|_nios2_arch_\|_\*(C'\fR is available to programs, +with value 1 or 2, indicating the targeted \s-1ISA\s0 level. +.IP "\fB\-mbypass\-cache\fR" 4 +.IX Item "-mbypass-cache" +.PD 0 +.IP "\fB\-mno\-bypass\-cache\fR" 4 +.IX Item "-mno-bypass-cache" +.PD +Force all load and store instructions to always bypass cache by +using I/O variants of the instructions. The default is not to +bypass the cache. +.IP "\fB\-mno\-cache\-volatile\fR" 4 +.IX Item "-mno-cache-volatile" +.PD 0 +.IP "\fB\-mcache\-volatile\fR" 4 +.IX Item "-mcache-volatile" +.PD +Volatile memory access bypass the cache using the I/O variants of +the load and store instructions. The default is not to bypass the cache. +.IP "\fB\-mno\-fast\-sw\-div\fR" 4 +.IX Item "-mno-fast-sw-div" +.PD 0 +.IP "\fB\-mfast\-sw\-div\fR" 4 +.IX Item "-mfast-sw-div" +.PD +Do not use table-based fast divide for small numbers. The default +is to use the fast divide at \fB\-O3\fR and above. +.IP "\fB\-mno\-hw\-mul\fR" 4 +.IX Item "-mno-hw-mul" +.PD 0 +.IP "\fB\-mhw\-mul\fR" 4 +.IX Item "-mhw-mul" +.IP "\fB\-mno\-hw\-mulx\fR" 4 +.IX Item "-mno-hw-mulx" +.IP "\fB\-mhw\-mulx\fR" 4 +.IX Item "-mhw-mulx" +.IP "\fB\-mno\-hw\-div\fR" 4 +.IX Item "-mno-hw-div" +.IP "\fB\-mhw\-div\fR" 4 +.IX Item "-mhw-div" +.PD +Enable or disable emitting \f(CW\*(C`mul\*(C'\fR, \f(CW\*(C`mulx\*(C'\fR and \f(CW\*(C`div\*(C'\fR family of +instructions by the compiler. The default is to emit \f(CW\*(C`mul\*(C'\fR +and not emit \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`mulx\*(C'\fR. +.IP "\fB\-mbmx\fR" 4 +.IX Item "-mbmx" +.PD 0 +.IP "\fB\-mno\-bmx\fR" 4 +.IX Item "-mno-bmx" +.IP "\fB\-mcdx\fR" 4 +.IX Item "-mcdx" +.IP "\fB\-mno\-cdx\fR" 4 +.IX Item "-mno-cdx" +.PD +Enable or disable generation of Nios \s-1II R2 BMX\s0 (bit manipulation) and +\&\s-1CDX\s0 (code density) instructions. Enabling these instructions also +requires \fB\-march=r2\fR. Since these instructions are optional +extensions to the R2 architecture, the default is not to emit them. +.IP "\fB\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR" 4 +.IX Item "-mcustom-insn=N" +.PD 0 +.IP "\fB\-mno\-custom\-\fR\fIinsn\fR" 4 +.IX Item "-mno-custom-insn" +.PD +Each \fB\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR option enables use of a +custom instruction with encoding \fIN\fR when generating code that uses +\&\fIinsn\fR. For example, \fB\-mcustom\-fadds=253\fR generates custom +instruction 253 for single-precision floating-point add operations instead +of the default behavior of using a library call. +.Sp +The following values of \fIinsn\fR are supported. Except as otherwise +noted, floating-point operations are expected to be implemented with +normal \s-1IEEE 754\s0 semantics and correspond directly to the C operators or the +equivalent \s-1GCC\s0 built-in functions. +.Sp +Single-precision floating point: +.RS 4 +.IP "\fBfadds\fR, \fBfsubs\fR, \fBfdivs\fR, \fBfmuls\fR" 4 +.IX Item "fadds, fsubs, fdivs, fmuls" +Binary arithmetic operations. +.IP "\fBfnegs\fR" 4 +.IX Item "fnegs" +Unary negation. +.IP "\fBfabss\fR" 4 +.IX Item "fabss" +Unary absolute value. +.IP "\fBfcmpeqs\fR, \fBfcmpges\fR, \fBfcmpgts\fR, \fBfcmples\fR, \fBfcmplts\fR, \fBfcmpnes\fR" 4 +.IX Item "fcmpeqs, fcmpges, fcmpgts, fcmples, fcmplts, fcmpnes" +Comparison operations. +.IP "\fBfmins\fR, \fBfmaxs\fR" 4 +.IX Item "fmins, fmaxs" +Floating-point minimum and maximum. These instructions are only +generated if \fB\-ffinite\-math\-only\fR is specified. +.IP "\fBfsqrts\fR" 4 +.IX Item "fsqrts" +Unary square root operation. +.IP "\fBfcoss\fR, \fBfsins\fR, \fBftans\fR, \fBfatans\fR, \fBfexps\fR, \fBflogs\fR" 4 +.IX Item "fcoss, fsins, ftans, fatans, fexps, flogs" +Floating-point trigonometric and exponential functions. These instructions +are only generated if \fB\-funsafe\-math\-optimizations\fR is also specified. +.RE +.RS 4 +.Sp +Double-precision floating point: +.IP "\fBfaddd\fR, \fBfsubd\fR, \fBfdivd\fR, \fBfmuld\fR" 4 +.IX Item "faddd, fsubd, fdivd, fmuld" +Binary arithmetic operations. +.IP "\fBfnegd\fR" 4 +.IX Item "fnegd" +Unary negation. +.IP "\fBfabsd\fR" 4 +.IX Item "fabsd" +Unary absolute value. +.IP "\fBfcmpeqd\fR, \fBfcmpged\fR, \fBfcmpgtd\fR, \fBfcmpled\fR, \fBfcmpltd\fR, \fBfcmpned\fR" 4 +.IX Item "fcmpeqd, fcmpged, fcmpgtd, fcmpled, fcmpltd, fcmpned" +Comparison operations. +.IP "\fBfmind\fR, \fBfmaxd\fR" 4 +.IX Item "fmind, fmaxd" +Double-precision minimum and maximum. These instructions are only +generated if \fB\-ffinite\-math\-only\fR is specified. +.IP "\fBfsqrtd\fR" 4 +.IX Item "fsqrtd" +Unary square root operation. +.IP "\fBfcosd\fR, \fBfsind\fR, \fBftand\fR, \fBfatand\fR, \fBfexpd\fR, \fBflogd\fR" 4 +.IX Item "fcosd, fsind, ftand, fatand, fexpd, flogd" +Double-precision trigonometric and exponential functions. These instructions +are only generated if \fB\-funsafe\-math\-optimizations\fR is also specified. +.RE +.RS 4 +.Sp +Conversions: +.IP "\fBfextsd\fR" 4 +.IX Item "fextsd" +Conversion from single precision to double precision. +.IP "\fBftruncds\fR" 4 +.IX Item "ftruncds" +Conversion from double precision to single precision. +.IP "\fBfixsi\fR, \fBfixsu\fR, \fBfixdi\fR, \fBfixdu\fR" 4 +.IX Item "fixsi, fixsu, fixdi, fixdu" +Conversion from floating point to signed or unsigned integer types, with +truncation towards zero. +.IP "\fBround\fR" 4 +.IX Item "round" +Conversion from single-precision floating point to signed integer, +rounding to the nearest integer and ties away from zero. +This corresponds to the \f(CW\*(C`_\|_builtin_lroundf\*(C'\fR function when +\&\fB\-fno\-math\-errno\fR is used. +.IP "\fBfloatis\fR, \fBfloatus\fR, \fBfloatid\fR, \fBfloatud\fR" 4 +.IX Item "floatis, floatus, floatid, floatud" +Conversion from signed or unsigned integer types to floating-point types. +.RE +.RS 4 +.Sp +In addition, all of the following transfer instructions for internal +registers X and Y must be provided to use any of the double-precision +floating-point instructions. Custom instructions taking two +double-precision source operands expect the first operand in the +64\-bit register X. The other operand (or only operand of a unary +operation) is given to the custom arithmetic instruction with the +least significant half in source register \fIsrc1\fR and the most +significant half in \fIsrc2\fR. A custom instruction that returns a +double-precision result returns the most significant 32 bits in the +destination register and the other half in 32\-bit register Y. +\&\s-1GCC\s0 automatically generates the necessary code sequences to write +register X and/or read register Y when double-precision floating-point +instructions are used. +.IP "\fBfwrx\fR" 4 +.IX Item "fwrx" +Write \fIsrc1\fR into the least significant half of X and \fIsrc2\fR into +the most significant half of X. +.IP "\fBfwry\fR" 4 +.IX Item "fwry" +Write \fIsrc1\fR into Y. +.IP "\fBfrdxhi\fR, \fBfrdxlo\fR" 4 +.IX Item "frdxhi, frdxlo" +Read the most or least (respectively) significant half of X and store it in +\&\fIdest\fR. +.IP "\fBfrdy\fR" 4 +.IX Item "frdy" +Read the value of Y and store it into \fIdest\fR. +.RE +.RS 4 +.Sp +Note that you can gain more local control over generation of Nios \s-1II\s0 custom +instructions by using the \f(CW\*(C`target("custom\-\f(CIinsn\f(CW=\f(CIN\f(CW")\*(C'\fR +and \f(CW\*(C`target("no\-custom\-\f(CIinsn\f(CW")\*(C'\fR function attributes +or pragmas. +.RE +.IP "\fB\-mcustom\-fpu\-cfg=\fR\fIname\fR" 4 +.IX Item "-mcustom-fpu-cfg=name" +This option enables a predefined, named set of custom instruction encodings +(see \fB\-mcustom\-\fR\fIinsn\fR above). +Currently, the following sets are defined: +.Sp +\&\fB\-mcustom\-fpu\-cfg=60\-1\fR is equivalent to: +\&\fB\-mcustom\-fmuls=252 +\&\-mcustom\-fadds=253 +\&\-mcustom\-fsubs=254 +\&\-fsingle\-precision\-constant\fR +.Sp +\&\fB\-mcustom\-fpu\-cfg=60\-2\fR is equivalent to: +\&\fB\-mcustom\-fmuls=252 +\&\-mcustom\-fadds=253 +\&\-mcustom\-fsubs=254 +\&\-mcustom\-fdivs=255 +\&\-fsingle\-precision\-constant\fR +.Sp +\&\fB\-mcustom\-fpu\-cfg=72\-3\fR is equivalent to: +\&\fB\-mcustom\-floatus=243 +\&\-mcustom\-fixsi=244 +\&\-mcustom\-floatis=245 +\&\-mcustom\-fcmpgts=246 +\&\-mcustom\-fcmples=249 +\&\-mcustom\-fcmpeqs=250 +\&\-mcustom\-fcmpnes=251 +\&\-mcustom\-fmuls=252 +\&\-mcustom\-fadds=253 +\&\-mcustom\-fsubs=254 +\&\-mcustom\-fdivs=255 +\&\-fsingle\-precision\-constant\fR +.Sp +Custom instruction assignments given by individual +\&\fB\-mcustom\-\fR\fIinsn\fR\fB=\fR options override those given by +\&\fB\-mcustom\-fpu\-cfg=\fR, regardless of the +order of the options on the command line. +.Sp +Note that you can gain more local control over selection of a \s-1FPU\s0 +configuration by using the \f(CW\*(C`target("custom\-fpu\-cfg=\f(CIname\f(CW")\*(C'\fR +function attribute +or pragma. +.PP +These additional \fB\-m\fR options are available for the Altera Nios \s-1II +ELF\s0 (bare-metal) target: +.IP "\fB\-mhal\fR" 4 +.IX Item "-mhal" +Link with \s-1HAL BSP.\s0 This suppresses linking with the GCC-provided C runtime +startup and termination code, and is typically used in conjunction with +\&\fB\-msys\-crt0=\fR to specify the location of the alternate startup code +provided by the \s-1HAL BSP.\s0 +.IP "\fB\-msmallc\fR" 4 +.IX Item "-msmallc" +Link with a limited version of the C library, \fB\-lsmallc\fR, rather than +Newlib. +.IP "\fB\-msys\-crt0=\fR\fIstartfile\fR" 4 +.IX Item "-msys-crt0=startfile" +\&\fIstartfile\fR is the file name of the startfile (crt0) to use +when linking. This option is only useful in conjunction with \fB\-mhal\fR. +.IP "\fB\-msys\-lib=\fR\fIsystemlib\fR" 4 +.IX Item "-msys-lib=systemlib" +\&\fIsystemlib\fR is the library name of the library that provides +low-level system calls required by the C library, +e.g. \f(CW\*(C`read\*(C'\fR and \f(CW\*(C`write\*(C'\fR. +This option is typically used to link with a library provided by a \s-1HAL BSP.\s0 +.PP +\fINvidia \s-1PTX\s0 Options\fR +.IX Subsection "Nvidia PTX Options" +.PP +These options are defined for Nvidia \s-1PTX:\s0 +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit \s-1ABI.\s0 +.IP "\fB\-misa=\fR\fIISA-string\fR" 4 +.IX Item "-misa=ISA-string" +Generate code for given the specified \s-1PTX ISA\s0 (e.g. \fBsm_35\fR). \s-1ISA\s0 +strings must be lower-case. Valid \s-1ISA\s0 strings include \fBsm_30\fR and +\&\fBsm_35\fR. The default \s-1ISA\s0 is sm_30. +.IP "\fB\-mmainkernel\fR" 4 +.IX Item "-mmainkernel" +Link in code for a _\|_main kernel. This is for stand-alone instead of +offloading execution. +.IP "\fB\-moptimize\fR" 4 +.IX Item "-moptimize" +Apply partitioned execution optimizations. This is the default when any +level of optimization is selected. +.IP "\fB\-msoft\-stack\fR" 4 +.IX Item "-msoft-stack" +Generate code that does not use \f(CW\*(C`.local\*(C'\fR memory +directly for stack storage. Instead, a per-warp stack pointer is +maintained explicitly. This enables variable-length stack allocation (with +variable-length arrays or \f(CW\*(C`alloca\*(C'\fR), and when global memory is used for +underlying storage, makes it possible to access automatic variables from other +threads, or with atomic instructions. This code generation variant is used +for OpenMP offloading, but the option is exposed on its own for the purpose +of testing the compiler; to generate code suitable for linking into programs +using OpenMP offloading, use option \fB\-mgomp\fR. +.IP "\fB\-muniform\-simt\fR" 4 +.IX Item "-muniform-simt" +Switch to code generation variant that allows to execute all threads in each +warp, while maintaining memory state and side effects as if only one thread +in each warp was active outside of OpenMP \s-1SIMD\s0 regions. All atomic operations +and calls to runtime (malloc, free, vprintf) are conditionally executed (iff +current lane index equals the master lane index), and the register being +assigned is copied via a shuffle instruction from the master lane. Outside of +\&\s-1SIMD\s0 regions lane 0 is the master; inside, each thread sees itself as the +master. Shared memory array \f(CW\*(C`int _\|_nvptx_uni[]\*(C'\fR stores all-zeros or +all-ones bitmasks for each warp, indicating current mode (0 outside of \s-1SIMD\s0 +regions). Each thread can bitwise-and the bitmask at position \f(CW\*(C`tid.y\*(C'\fR +with current lane index to compute the master lane index. +.IP "\fB\-mgomp\fR" 4 +.IX Item "-mgomp" +Generate code for use in OpenMP offloading: enables \fB\-msoft\-stack\fR and +\&\fB\-muniform\-simt\fR options, and selects corresponding multilib variant. +.PP +\fIOpenRISC Options\fR +.IX Subsection "OpenRISC Options" +.PP +These options are defined for OpenRISC: +.IP "\fB\-mboard=\fR\fIname\fR" 4 +.IX Item "-mboard=name" +Configure a board specific runtime. This will be passed to the linker for +newlib board library linking. The default is \f(CW\*(C`or1ksim\*(C'\fR. +.IP "\fB\-mnewlib\fR" 4 +.IX Item "-mnewlib" +For compatibility, it's always newlib for elf now. +.IP "\fB\-mhard\-div\fR" 4 +.IX Item "-mhard-div" +Generate code for hardware which supports divide instructions. This is the +default. +.IP "\fB\-mhard\-mul\fR" 4 +.IX Item "-mhard-mul" +Generate code for hardware which supports multiply instructions. This is the +default. +.IP "\fB\-mcmov\fR" 4 +.IX Item "-mcmov" +Generate code for hardware which supports the conditional move (\f(CW\*(C`l.cmov\*(C'\fR) +instruction. +.IP "\fB\-mror\fR" 4 +.IX Item "-mror" +Generate code for hardware which supports rotate right instructions. +.IP "\fB\-msext\fR" 4 +.IX Item "-msext" +Generate code for hardware which supports sign-extension instructions. +.IP "\fB\-msfimm\fR" 4 +.IX Item "-msfimm" +Generate code for hardware which supports set flag immediate (\f(CW\*(C`l.sf*i\*(C'\fR) +instructions. +.IP "\fB\-mshftimm\fR" 4 +.IX Item "-mshftimm" +Generate code for hardware which supports shift immediate related instructions +(i.e. \f(CW\*(C`l.srai\*(C'\fR, \f(CW\*(C`l.srli\*(C'\fR, \f(CW\*(C`l.slli\*(C'\fR, \f(CW\*(C`1.rori\*(C'\fR). Note, to +enable generation of the \f(CW\*(C`l.rori\*(C'\fR instruction the \fB\-mror\fR flag must +also be specified. +.IP "\fB\-msoft\-div\fR" 4 +.IX Item "-msoft-div" +Generate code for hardware which requires divide instruction emulation. +.IP "\fB\-msoft\-mul\fR" 4 +.IX Item "-msoft-mul" +Generate code for hardware which requires multiply instruction emulation. +.PP +\fI\s-1PDP\-11\s0 Options\fR +.IX Subsection "PDP-11 Options" +.PP +These options are defined for the \s-1PDP\-11:\s0 +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating +point on the \s-1PDP\-11/40\s0 is not supported.) Implies \-m45. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use hardware floating point. +.IP "\fB\-mac0\fR" 4 +.IX Item "-mac0" +Return floating-point results in ac0 (fr0 in Unix assembler syntax). +.IP "\fB\-mno\-ac0\fR" 4 +.IX Item "-mno-ac0" +Return floating-point results in memory. This is the default. +.IP "\fB\-m40\fR" 4 +.IX Item "-m40" +Generate code for a \s-1PDP\-11/40.\s0 Implies \-msoft\-float \-mno\-split. +.IP "\fB\-m45\fR" 4 +.IX Item "-m45" +Generate code for a \s-1PDP\-11/45.\s0 This is the default. +.IP "\fB\-m10\fR" 4 +.IX Item "-m10" +Generate code for a \s-1PDP\-11/10.\s0 Implies \-msoft\-float \-mno\-split. +.IP "\fB\-mint16\fR" 4 +.IX Item "-mint16" +.PD 0 +.IP "\fB\-mno\-int32\fR" 4 +.IX Item "-mno-int32" +.PD +Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +.PD 0 +.IP "\fB\-mno\-int16\fR" 4 +.IX Item "-mno-int16" +.PD +Use 32\-bit \f(CW\*(C`int\*(C'\fR. +.IP "\fB\-msplit\fR" 4 +.IX Item "-msplit" +Target has split instruction and data space. Implies \-m45. +.IP "\fB\-munix\-asm\fR" 4 +.IX Item "-munix-asm" +Use Unix assembler syntax. +.IP "\fB\-mdec\-asm\fR" 4 +.IX Item "-mdec-asm" +Use \s-1DEC\s0 assembler syntax. +.IP "\fB\-mgnu\-asm\fR" 4 +.IX Item "-mgnu-asm" +Use \s-1GNU\s0 assembler syntax. This is the default. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Use the new \s-1LRA\s0 register allocator. By default, the old \*(L"reload\*(R" +allocator is used. +.PP +\fIpicoChip Options\fR +.IX Subsection "picoChip Options" +.PP +These \fB\-m\fR options are defined for picoChip implementations: +.IP "\fB\-mae=\fR\fIae_type\fR" 4 +.IX Item "-mae=ae_type" +Set the instruction set, register set, and instruction scheduling +parameters for array element type \fIae_type\fR. Supported values +for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. +.Sp +\&\fB\-mae=ANY\fR selects a completely generic \s-1AE\s0 type. Code +generated with this option runs on any of the other \s-1AE\s0 types. The +code is not as efficient as it would be if compiled for a specific +\&\s-1AE\s0 type, and some types of operation (e.g., multiplication) do not +work properly on all types of \s-1AE.\s0 +.Sp +\&\fB\-mae=MUL\fR selects a \s-1MUL AE\s0 type. This is the most useful \s-1AE\s0 type +for compiled code, and is the default. +.Sp +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC AE.\s0 Code compiled with this +option may suffer from poor performance of byte (char) manipulation, +since the \s-1DSP AE\s0 does not provide hardware support for byte load/stores. +.IP "\fB\-msymbol\-as\-address\fR" 4 +.IX Item "-msymbol-as-address" +Enable the compiler to directly use a symbol name as an address in a +load/store instruction, without first loading it into a +register. Typically, the use of this option generates larger +programs, which run faster than when the option isn't used. However, the +results vary from program to program, so it is left as a user option, +rather than being permanently enabled. +.IP "\fB\-mno\-inefficient\-warnings\fR" 4 +.IX Item "-mno-inefficient-warnings" +Disables warnings about the generation of inefficient code. These +warnings can be generated, for example, when compiling code that +performs byte-level memory operations on the \s-1MAC AE\s0 type. The \s-1MAC AE\s0 has +no hardware support for byte-level memory operations, so all byte +load/stores must be synthesized from word load/store operations. This is +inefficient and a warning is generated to indicate +that you should rewrite the code to avoid byte operations, or to target +an \s-1AE\s0 type that has the necessary hardware support. This option disables +these warnings. +.PP +\fIPowerPC Options\fR +.IX Subsection "PowerPC Options" +.PP +These are listed under +.PP +\fIRISC-V Options\fR +.IX Subsection "RISC-V Options" +.PP +These command-line options are defined for RISC-V targets: +.IP "\fB\-mbranch\-cost=\fR\fIn\fR" 4 +.IX Item "-mbranch-cost=n" +Set the cost of branches to roughly \fIn\fR instructions. +.IP "\fB\-mplt\fR" 4 +.IX Item "-mplt" +.PD 0 +.IP "\fB\-mno\-plt\fR" 4 +.IX Item "-mno-plt" +.PD +When generating \s-1PIC\s0 code, do or don't allow the use of PLTs. Ignored for +non-PIC. The default is \fB\-mplt\fR. +.IP "\fB\-mabi=\fR\fIABI-string\fR" 4 +.IX Item "-mabi=ABI-string" +Specify integer and floating-point calling convention. \fIABI-string\fR +contains two parts: the size of integer types and the registers used for +floating-point types. For example \fB\-march=rv64ifd \-mabi=lp64d\fR means that +\&\fBlong\fR and pointers are 64\-bit (implicitly defining \fBint\fR to be +32\-bit), and that floating-point values up to 64 bits wide are passed in F +registers. Contrast this with \fB\-march=rv64ifd \-mabi=lp64f\fR, which still +allows the compiler to generate code that uses the F and D extensions but only +allows floating-point values up to 32 bits long to be passed in registers; or +\&\fB\-march=rv64ifd \-mabi=lp64\fR, in which no floating-point arguments will be +passed in registers. +.Sp +The default for this argument is system dependent, users who want a specific +calling convention should specify one explicitly. The valid calling +conventions are: \fBilp32\fR, \fBilp32f\fR, \fBilp32d\fR, \fBlp64\fR, +\&\fBlp64f\fR, and \fBlp64d\fR. Some calling conventions are impossible to +implement on some ISAs: for example, \fB\-march=rv32if \-mabi=ilp32d\fR is +invalid because the \s-1ABI\s0 requires 64\-bit values be passed in F registers, but F +registers are only 32 bits wide. There is also the \fBilp32e\fR \s-1ABI\s0 that can +only be used with the \fBrv32e\fR architecture. This \s-1ABI\s0 is not well +specified at present, and is subject to change. +.IP "\fB\-mfdiv\fR" 4 +.IX Item "-mfdiv" +.PD 0 +.IP "\fB\-mno\-fdiv\fR" 4 +.IX Item "-mno-fdiv" +.PD +Do or don't use hardware floating-point divide and square root instructions. +This requires the F or D extensions for floating-point registers. The default +is to use them if the specified architecture has these instructions. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Do or don't use hardware instructions for integer division. This requires the +M extension. The default is to use them if the specified architecture has +these instructions. +.IP "\fB\-march=\fR\fIISA-string\fR" 4 +.IX Item "-march=ISA-string" +Generate code for given RISC-V \s-1ISA\s0 (e.g. \fBrv64im\fR). \s-1ISA\s0 strings must be +lower-case. Examples include \fBrv64i\fR, \fBrv32g\fR, \fBrv32e\fR, and +\&\fBrv32imaf\fR. +.IP "\fB\-mtune=\fR\fIprocessor-string\fR" 4 +.IX Item "-mtune=processor-string" +Optimize the output for the given processor, specified by microarchitecture +name. Permissible values for this option are: \fBrocket\fR, +\&\fBsifive\-3\-series\fR, \fBsifive\-5\-series\fR, \fBsifive\-7\-series\fR, +and \fBsize\fR. +.Sp +When \fB\-mtune=\fR is not specified, the default is \fBrocket\fR. +.Sp +The \fBsize\fR choice is not intended for use by end-users. This is used +when \fB\-Os\fR is specified. It overrides the instruction cost info +provided by \fB\-mtune=\fR, but does not override the pipeline info. This +helps reduce code size while still giving good performance. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128\-bits). +.Sp +\&\fBWarning:\fR If you use this switch, then you must build all modules with +the same value, including any libraries. This includes the system libraries +and startup modules. +.IP "\fB\-msmall\-data\-limit=\fR\fIn\fR" 4 +.IX Item "-msmall-data-limit=n" +Put global and static data smaller than \fIn\fR bytes into a special section +(on some targets). +.IP "\fB\-msave\-restore\fR" 4 +.IX Item "-msave-restore" +.PD 0 +.IP "\fB\-mno\-save\-restore\fR" 4 +.IX Item "-mno-save-restore" +.PD +Do or don't use smaller but slower prologue and epilogue code that uses +library function calls. The default is to use fast inline prologues and +epilogues. +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD 0 +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD +Do not or do generate unaligned memory accesses. The default is set depending +on whether the processor we are optimizing for supports fast unaligned access +or not. +.IP "\fB\-mcmodel=medlow\fR" 4 +.IX Item "-mcmodel=medlow" +Generate code for the medium-low code model. The program and its statically +defined symbols must lie within a single 2 GiB address range and must lie +between absolute addresses \-2 GiB and +2 GiB. Programs can be +statically or dynamically linked. This is the default code model. +.IP "\fB\-mcmodel=medany\fR" 4 +.IX Item "-mcmodel=medany" +Generate code for the medium-any code model. The program and its statically +defined symbols must be within any single 2 GiB address range. Programs can be +statically or dynamically linked. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-exlicit\-relocs\fR" 4 +.IX Item "-mno-exlicit-relocs" +.PD +Use or do not use assembler relocation operators when dealing with symbolic +addresses. The alternative is to use assembler macros instead, which may +limit optimization. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +.PD 0 +.IP "\fB\-mno\-relax\fR" 4 +.IX Item "-mno-relax" +.PD +Take advantage of linker relaxations to reduce the number of instructions +required to materialize symbol addresses. The default is to take advantage of +linker relaxations. +.IP "\fB\-memit\-attribute\fR" 4 +.IX Item "-memit-attribute" +.PD 0 +.IP "\fB\-mno\-emit\-attribute\fR" 4 +.IX Item "-mno-emit-attribute" +.PD +Emit (do not emit) RISC-V attribute to record extra information into \s-1ELF\s0 +objects. This feature requires at least binutils 2.32. +.PP +\fI\s-1RL78\s0 Options\fR +.IX Subsection "RL78 Options" +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Links in additional target libraries to support operation within a +simulator. +.IP "\fB\-mmul=none\fR" 4 +.IX Item "-mmul=none" +.PD 0 +.IP "\fB\-mmul=g10\fR" 4 +.IX Item "-mmul=g10" +.IP "\fB\-mmul=g13\fR" 4 +.IX Item "-mmul=g13" +.IP "\fB\-mmul=g14\fR" 4 +.IX Item "-mmul=g14" +.IP "\fB\-mmul=rl78\fR" 4 +.IX Item "-mmul=rl78" +.PD +Specifies the type of hardware multiplication and division support to +be used. The simplest is \f(CW\*(C`none\*(C'\fR, which uses software for both +multiplication and division. This is the default. The \f(CW\*(C`g13\*(C'\fR +value is for the hardware multiply/divide peripheral found on the +\&\s-1RL78/G13\s0 (S2 core) targets. The \f(CW\*(C`g14\*(C'\fR value selects the use of +the multiplication and division instructions supported by the \s-1RL78/G14\s0 +(S3 core) parts. The value \f(CW\*(C`rl78\*(C'\fR is an alias for \f(CW\*(C`g14\*(C'\fR and +the value \f(CW\*(C`mg10\*(C'\fR is an alias for \f(CW\*(C`none\*(C'\fR. +.Sp +In addition a C preprocessor macro is defined, based upon the setting +of this option. Possible values are: \f(CW\*(C`_\|_RL78_MUL_NONE_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_RL78_MUL_G13_\|_\*(C'\fR or \f(CW\*(C`_\|_RL78_MUL_G14_\|_\*(C'\fR. +.IP "\fB\-mcpu=g10\fR" 4 +.IX Item "-mcpu=g10" +.PD 0 +.IP "\fB\-mcpu=g13\fR" 4 +.IX Item "-mcpu=g13" +.IP "\fB\-mcpu=g14\fR" 4 +.IX Item "-mcpu=g14" +.IP "\fB\-mcpu=rl78\fR" 4 +.IX Item "-mcpu=rl78" +.PD +Specifies the \s-1RL78\s0 core to target. The default is the G14 core, also +known as an S3 core or just \s-1RL78.\s0 The G13 or S2 core does not have +multiply or divide instructions, instead it uses a hardware peripheral +for these operations. The G10 or S1 core does not have register +banks, so it uses a different calling convention. +.Sp +If this option is set it also selects the type of hardware multiply +support to use, unless this is overridden by an explicit +\&\fB\-mmul=none\fR option on the command line. Thus specifying +\&\fB\-mcpu=g13\fR enables the use of the G13 hardware multiply +peripheral and specifying \fB\-mcpu=g10\fR disables the use of +hardware multiplications altogether. +.Sp +Note, although the \s-1RL78/G14\s0 core is the default target, specifying +\&\fB\-mcpu=g14\fR or \fB\-mcpu=rl78\fR on the command line does +change the behavior of the toolchain since it also enables G14 +hardware multiply support. If these options are not specified on the +command line then software multiplication routines will be used even +though the code targets the \s-1RL78\s0 core. This is for backwards +compatibility with older toolchains which did not have hardware +multiply and divide support. +.Sp +In addition a C preprocessor macro is defined, based upon the setting +of this option. Possible values are: \f(CW\*(C`_\|_RL78_G10_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_RL78_G13_\|_\*(C'\fR or \f(CW\*(C`_\|_RL78_G14_\|_\*(C'\fR. +.IP "\fB\-mg10\fR" 4 +.IX Item "-mg10" +.PD 0 +.IP "\fB\-mg13\fR" 4 +.IX Item "-mg13" +.IP "\fB\-mg14\fR" 4 +.IX Item "-mg14" +.IP "\fB\-mrl78\fR" 4 +.IX Item "-mrl78" +.PD +These are aliases for the corresponding \fB\-mcpu=\fR option. They +are provided for backwards compatibility. +.IP "\fB\-mallregs\fR" 4 +.IX Item "-mallregs" +Allow the compiler to use all of the available registers. By default +registers \f(CW\*(C`r24..r31\*(C'\fR are reserved for use in interrupt handlers. +With this option enabled these registers can be used in ordinary +functions as well. +.IP "\fB\-m64bit\-doubles\fR" 4 +.IX Item "-m64bit-doubles" +.PD 0 +.IP "\fB\-m32bit\-doubles\fR" 4 +.IX Item "-m32bit-doubles" +.PD +Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) +or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is +\&\fB\-m32bit\-doubles\fR. +.IP "\fB\-msave\-mduc\-in\-interrupts\fR" 4 +.IX Item "-msave-mduc-in-interrupts" +.PD 0 +.IP "\fB\-mno\-save\-mduc\-in\-interrupts\fR" 4 +.IX Item "-mno-save-mduc-in-interrupts" +.PD +Specifies that interrupt handler functions should preserve the +\&\s-1MDUC\s0 registers. This is only necessary if normal code might use +the \s-1MDUC\s0 registers, for example because it performs multiplication +and division operations. The default is to ignore the \s-1MDUC\s0 registers +as this makes the interrupt handlers faster. The target option \-mg13 +needs to be passed for this to work as this feature is only available +on the G13 target (S2 core). The \s-1MDUC\s0 registers will only be saved +if the interrupt handler performs a multiplication or division +operation or it calls another function. +.PP +\fI\s-1IBM RS/6000\s0 and PowerPC Options\fR +.IX Subsection "IBM RS/6000 and PowerPC Options" +.PP +These \fB\-m\fR options are defined for the \s-1IBM RS/6000\s0 and PowerPC: +.IP "\fB\-mpowerpc\-gpopt\fR" 4 +.IX Item "-mpowerpc-gpopt" +.PD 0 +.IP "\fB\-mno\-powerpc\-gpopt\fR" 4 +.IX Item "-mno-powerpc-gpopt" +.IP "\fB\-mpowerpc\-gfxopt\fR" 4 +.IX Item "-mpowerpc-gfxopt" +.IP "\fB\-mno\-powerpc\-gfxopt\fR" 4 +.IX Item "-mno-powerpc-gfxopt" +.IP "\fB\-mpowerpc64\fR" 4 +.IX Item "-mpowerpc64" +.IP "\fB\-mno\-powerpc64\fR" 4 +.IX Item "-mno-powerpc64" +.IP "\fB\-mmfcrf\fR" 4 +.IX Item "-mmfcrf" +.IP "\fB\-mno\-mfcrf\fR" 4 +.IX Item "-mno-mfcrf" +.IP "\fB\-mpopcntb\fR" 4 +.IX Item "-mpopcntb" +.IP "\fB\-mno\-popcntb\fR" 4 +.IX Item "-mno-popcntb" +.IP "\fB\-mpopcntd\fR" 4 +.IX Item "-mpopcntd" +.IP "\fB\-mno\-popcntd\fR" 4 +.IX Item "-mno-popcntd" +.IP "\fB\-mfprnd\fR" 4 +.IX Item "-mfprnd" +.IP "\fB\-mno\-fprnd\fR" 4 +.IX Item "-mno-fprnd" +.IP "\fB\-mcmpb\fR" 4 +.IX Item "-mcmpb" +.IP "\fB\-mno\-cmpb\fR" 4 +.IX Item "-mno-cmpb" +.IP "\fB\-mmfpgpr\fR" 4 +.IX Item "-mmfpgpr" +.IP "\fB\-mno\-mfpgpr\fR" 4 +.IX Item "-mno-mfpgpr" +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +You use these options to specify which instructions are available on the +processor you are using. The default value of these options is +determined when configuring \s-1GCC.\s0 Specifying the +\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these +options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option +rather than the options listed above. +.Sp +Specifying \fB\-mpowerpc\-gpopt\fR allows +\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the +General Purpose group, including floating-point square root. Specifying +\&\fB\-mpowerpc\-gfxopt\fR allows \s-1GCC\s0 to +use the optional PowerPC architecture instructions in the Graphics +group, including floating-point select. +.Sp +The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from +condition register field instruction implemented on the \s-1POWER4\s0 +processor and other processors that support the PowerPC V2.01 +architecture. +The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and +double-precision \s-1FP\s0 reciprocal estimate instruction implemented on the +\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02 +architecture. +The \fB\-mpopcntd\fR option allows \s-1GCC\s0 to generate the popcount +instruction implemented on the \s-1POWER7\s0 processor and other processors +that support the PowerPC V2.06 architecture. +The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to +integer instructions implemented on the \s-1POWER5+\s0 processor and other +processors that support the PowerPC V2.03 architecture. +The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes +instruction implemented on the \s-1POWER6\s0 processor and other processors +that support the PowerPC V2.05 architecture. +The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from +general-purpose register instructions implemented on the \s-1POWER6X\s0 +processor and other processors that support the extended PowerPC V2.05 +architecture. +The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal +floating-point instructions implemented on some \s-1POWER\s0 processors. +.Sp +The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional +64\-bit instructions that are found in the full PowerPC64 architecture +and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to +\&\fB\-mno\-powerpc64\fR. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set architecture type, register usage, and +instruction scheduling parameters for machine type \fIcpu_type\fR. +Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR, +\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB464\fR, \fB464fp\fR, +\&\fB476\fR, \fB476fp\fR, \fB505\fR, \fB601\fR, \fB602\fR, \fB603\fR, +\&\fB603e\fR, \fB604\fR, \fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, +\&\fB7400\fR, \fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR, +\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBa2\fR, \fBe300c2\fR, +\&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBe5500\fR, +\&\fBe6500\fR, \fBec603e\fR, \fBG3\fR, \fBG4\fR, \fBG5\fR, +\&\fBtitan\fR, \fBpower3\fR, \fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, +\&\fBpower6\fR, \fBpower6x\fR, \fBpower7\fR, \fBpower8\fR, +\&\fBpower9\fR, \fBpowerpc\fR, \fBpowerpc64\fR, \fBpowerpc64le\fR, +\&\fBrs64\fR, and \fBnative\fR. +.Sp +\&\fB\-mcpu=powerpc\fR, \fB\-mcpu=powerpc64\fR, and +\&\fB\-mcpu=powerpc64le\fR specify pure 32\-bit PowerPC (either +endian), 64\-bit big endian PowerPC and 64\-bit little endian PowerPC +architecture machine types, with an appropriate, generic processor +model assumed for scheduling purposes. +.Sp +Specifying \fBnative\fR as cpu type detects and selects the +architecture option that corresponds to the host processor of the +system performing the compilation. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize the +processor. +.Sp +The other options specify a specific processor. Code generated under +those options runs best on that processor, and may not run at all on +others. +.Sp +The \fB\-mcpu\fR options automatically enable or disable the +following options: +.Sp +\&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple +\&\-mpopcntb \-mpopcntd \-mpowerpc64 +\&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt +\&\-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mhtm \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic \-mfloat128 \-mfloat128\-hardware\fR +.Sp +The particular options set for any particular \s-1CPU\s0 varies between +compiler versions, depending on what setting seems to produce optimal +code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's +capabilities. If you wish to set an individual option to a particular +value, you may specify it after the \fB\-mcpu\fR option, like +\&\fB\-mcpu=970 \-mno\-altivec\fR. +.Sp +On \s-1AIX,\s0 the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are +not enabled or disabled by the \fB\-mcpu\fR option at present because +\&\s-1AIX\s0 does not have full support for these options. You may still +enable or disable them individually if you're sure it'll work in your +environment. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the architecture type or register usage, +as \fB\-mcpu=\fR\fIcpu_type\fR does. The same +values for \fIcpu_type\fR are used for \fB\-mtune\fR as for +\&\fB\-mcpu\fR. If both are specified, the code generated uses the +architecture and registers set by \fB\-mcpu\fR, but the +scheduling parameters set by \fB\-mtune\fR. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate PowerPC64 code for the small model: The \s-1TOC\s0 is limited to +64k. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate PowerPC64 code for the medium model: The \s-1TOC\s0 and other static +data may be up to a total of 4G in size. This is the default for 64\-bit +Linux. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate PowerPC64 code for the large model: The \s-1TOC\s0 may be up to 4G +in size. Other data and code is only limited by the 64\-bit address +space. +.IP "\fB\-maltivec\fR" 4 +.IX Item "-maltivec" +.PD 0 +.IP "\fB\-mno\-altivec\fR" 4 +.IX Item "-mno-altivec" +.PD +Generate code that uses (does not use) AltiVec instructions, and also +enable the use of built-in functions that allow more direct access to +the AltiVec instruction set. You may also need to set +\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 +enhancements. +.Sp +When \fB\-maltivec\fR is used, the element order for AltiVec intrinsics +such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-mvrsave\fR" 4 +.IX Item "-mvrsave" +.PD 0 +.IP "\fB\-mno\-vrsave\fR" 4 +.IX Item "-mno-vrsave" +.PD +Generate \s-1VRSAVE\s0 instructions when generating AltiVec code. +.IP "\fB\-msecure\-plt\fR" 4 +.IX Item "-msecure-plt" +Generate code that allows \fBld\fR and \fBld.so\fR +to build executables and shared +libraries with non-executable \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections. +This is a PowerPC +32\-bit \s-1SYSV ABI\s0 option. +.IP "\fB\-mbss\-plt\fR" 4 +.IX Item "-mbss-plt" +Generate code that uses a \s-1BSS\s0 \f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR +fills in, and +requires \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR +sections that are both writable and executable. +This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. +.IP "\fB\-misel\fR" 4 +.IX Item "-misel" +.PD 0 +.IP "\fB\-mno\-isel\fR" 4 +.IX Item "-mno-isel" +.PD +This switch enables or disables the generation of \s-1ISEL\s0 instructions. +.IP "\fB\-mvsx\fR" 4 +.IX Item "-mvsx" +.PD 0 +.IP "\fB\-mno\-vsx\fR" 4 +.IX Item "-mno-vsx" +.PD +Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) +instructions, and also enable the use of built-in functions that allow +more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA.\s0 +.IP "\fB\-mhtm\fR" 4 +.IX Item "-mhtm" +.PD 0 +.IP "\fB\-mno\-htm\fR" 4 +.IX Item "-mno-htm" +.PD +Enable (disable) the use of the built-in functions that allow direct +access to the Hardware Transactional Memory (\s-1HTM\s0) instructions that +were added in version 2.07 of the PowerPC \s-1ISA.\s0 +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA.\s0 Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. +.IP "\fB\-mfloat128\fR" 4 +.IX Item "-mfloat128" +.PD 0 +.IP "\fB\-mno\-float128\fR" 4 +.IX Item "-mno-float128" +.PD +Enable/disable the \fI_\|_float128\fR keyword for \s-1IEEE\s0 128\-bit floating point +and use either software emulation for \s-1IEEE\s0 128\-bit floating point or +hardware instructions. +.Sp +The \s-1VSX\s0 instruction set (\fB\-mvsx\fR, \fB\-mcpu=power7\fR, +\&\fB\-mcpu=power8\fR), or \fB\-mcpu=power9\fR must be enabled to +use the \s-1IEEE\s0 128\-bit floating point support. The \s-1IEEE\s0 128\-bit +floating point support only works on PowerPC Linux systems. +.Sp +The default for \fB\-mfloat128\fR is enabled on PowerPC Linux +systems using the \s-1VSX\s0 instruction set, and disabled on other systems. +.Sp +If you use the \s-1ISA 3.0\s0 instruction set (\fB\-mpower9\-vector\fR or +\&\fB\-mcpu=power9\fR) on a 64\-bit system, the \s-1IEEE\s0 128\-bit floating +point support will also enable the generation of \s-1ISA 3.0 IEEE\s0 128\-bit +floating point instructions. Otherwise, if you do not specify to +generate \s-1ISA 3.0\s0 instructions or you are targeting a 32\-bit big endian +system, \s-1IEEE\s0 128\-bit floating point will be done with software +emulation. +.IP "\fB\-mfloat128\-hardware\fR" 4 +.IX Item "-mfloat128-hardware" +.PD 0 +.IP "\fB\-mno\-float128\-hardware\fR" 4 +.IX Item "-mno-float128-hardware" +.PD +Enable/disable using \s-1ISA 3.0\s0 hardware instructions to support the +\&\fI_\|_float128\fR data type. +.Sp +The default for \fB\-mfloat128\-hardware\fR is enabled on PowerPC +Linux systems using the \s-1ISA 3.0\s0 instruction set, and disabled on other +systems. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0 +targets (including GNU/Linux). The 32\-bit environment sets int, long +and pointer to 32 bits and generates code that runs on any PowerPC +variant. The 64\-bit environment sets int to 32 bits and long and +pointer to 64 bits, and generates code for PowerPC64, as for +\&\fB\-mpowerpc64\fR. +.IP "\fB\-mfull\-toc\fR" 4 +.IX Item "-mfull-toc" +.PD 0 +.IP "\fB\-mno\-fp\-in\-toc\fR" 4 +.IX Item "-mno-fp-in-toc" +.IP "\fB\-mno\-sum\-in\-toc\fR" 4 +.IX Item "-mno-sum-in-toc" +.IP "\fB\-mminimal\-toc\fR" 4 +.IX Item "-mminimal-toc" +.PD +Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for +every executable file. The \fB\-mfull\-toc\fR option is selected by +default. In that case, \s-1GCC\s0 allocates at least one \s-1TOC\s0 entry for +each unique non-automatic variable reference in your program. \s-1GCC\s0 +also places floating-point constants in the \s-1TOC.\s0 However, only +16,384 entries are available in the \s-1TOC.\s0 +.Sp +If you receive a linker error message that saying you have overflowed +the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used +with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. +\&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point +constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to +generate code to calculate the sum of an address and a constant at +run time instead of putting that sum into the \s-1TOC.\s0 You may specify one +or both of these options. Each causes \s-1GCC\s0 to produce very slightly +slower and larger code at the expense of conserving \s-1TOC\s0 space. +.Sp +If you still run out of space in the \s-1TOC\s0 even when you specify both of +these options, specify \fB\-mminimal\-toc\fR instead. This option causes +\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file. When you specify this +option, \s-1GCC\s0 produces code that is slower and larger but which +uses extremely little \s-1TOC\s0 space. You may wish to use this option +only on files that contain less frequently-executed code. +.IP "\fB\-maix64\fR" 4 +.IX Item "-maix64" +.PD 0 +.IP "\fB\-maix32\fR" 4 +.IX Item "-maix32" +.PD +Enable 64\-bit \s-1AIX ABI\s0 and calling convention: 64\-bit pointers, 64\-bit +\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. +Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR, +while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and +implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. +.IP "\fB\-mxl\-compat\fR" 4 +.IX Item "-mxl-compat" +.PD 0 +.IP "\fB\-mno\-xl\-compat\fR" 4 +.IX Item "-mno-xl-compat" +.PD +Produce code that conforms more closely to \s-1IBM XL\s0 compiler semantics +when using AIX-compatible \s-1ABI.\s0 Pass floating-point arguments to +prototyped functions beyond the register save area (\s-1RSA\s0) on the stack +in addition to argument FPRs. Do not assume that most significant +double in 128\-bit long double value is properly rounded when comparing +values and converting to double. Use \s-1XL\s0 symbol names for long double +support routines. +.Sp +The \s-1AIX\s0 calling convention was extended but not initially documented to +handle an obscure K&R C case of calling a function that takes the +address of its arguments with fewer arguments than declared. \s-1IBM XL\s0 +compilers access floating-point arguments that do not fit in the +\&\s-1RSA\s0 from the stack when a subroutine is compiled without +optimization. Because always storing floating-point arguments on the +stack is inefficient and rarely needed, this option is not enabled by +default and only is necessary when calling subroutines compiled by \s-1IBM +XL\s0 compilers without optimization. +.IP "\fB\-mpe\fR" 4 +.IX Item "-mpe" +Support \fI\s-1IBM RS/6000 SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an +application written to use message passing with special startup code to +enable the application to run. The system must have \s-1PE\s0 installed in the +standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file +must be overridden with the \fB\-specs=\fR option to specify the +appropriate directory location. The Parallel Environment does not +support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR +option are incompatible. +.IP "\fB\-malign\-natural\fR" 4 +.IX Item "-malign-natural" +.PD 0 +.IP "\fB\-malign\-power\fR" 4 +.IX Item "-malign-power" +.PD +On \s-1AIX,\s0 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option +\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger +types, such as floating-point doubles, on their natural size-based boundary. +The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified +alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI.\s0 +.Sp +On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR +is not supported. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code that does not use (uses) the floating-point register set. +Software floating-point emulation is provided if you use the +\&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking. +.IP "\fB\-mmultiple\fR" 4 +.IX Item "-mmultiple" +.PD 0 +.IP "\fB\-mno\-multiple\fR" 4 +.IX Item "-mno-multiple" +.PD +Generate code that uses (does not use) the load multiple word +instructions and the store multiple word instructions. These +instructions are generated by default on \s-1POWER\s0 systems, and not +generated on PowerPC systems. Do not use \fB\-mmultiple\fR on little-endian +PowerPC systems, since those instructions do not work when the +processor is in little-endian mode. The exceptions are \s-1PPC740\s0 and +\&\s-1PPC750\s0 which permit these instructions in little-endian mode. +.IP "\fB\-mupdate\fR" 4 +.IX Item "-mupdate" +.PD 0 +.IP "\fB\-mno\-update\fR" 4 +.IX Item "-mno-update" +.PD +Generate code that uses (does not use) the load or store instructions +that update the base register to the address of the calculated memory +location. These instructions are generated by default. If you use +\&\fB\-mno\-update\fR, there is a small window between the time that the +stack pointer is updated and the address of the previous frame is +stored, which means code that walks the stack frame across interrupts or +signals may get corrupted data. +.IP "\fB\-mavoid\-indexed\-addresses\fR" 4 +.IX Item "-mavoid-indexed-addresses" +.PD 0 +.IP "\fB\-mno\-avoid\-indexed\-addresses\fR" 4 +.IX Item "-mno-avoid-indexed-addresses" +.PD +Generate code that tries to avoid (not avoid) the use of indexed load +or store instructions. These instructions can incur a performance +penalty on Power6 processors in certain situations, such as when +stepping through large arrays that cross a 16M boundary. This option +is enabled by default when targeting Power6 and disabled otherwise. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine-dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mmulhw\fR" 4 +.IX Item "-mmulhw" +.PD 0 +.IP "\fB\-mno\-mulhw\fR" 4 +.IX Item "-mno-mulhw" +.PD +Generate code that uses (does not use) the half-word multiply and +multiply-accumulate instructions on the \s-1IBM 405, 440, 464\s0 and 476 processors. +These instructions are generated by default when targeting those +processors. +.IP "\fB\-mdlmzb\fR" 4 +.IX Item "-mdlmzb" +.PD 0 +.IP "\fB\-mno\-dlmzb\fR" 4 +.IX Item "-mno-dlmzb" +.PD +Generate code that uses (does not use) the string-search \fBdlmzb\fR +instruction on the \s-1IBM 405, 440, 464\s0 and 476 processors. This instruction is +generated by default when targeting those processors. +.IP "\fB\-mno\-bit\-align\fR" 4 +.IX Item "-mno-bit-align" +.PD 0 +.IP "\fB\-mbit\-align\fR" 4 +.IX Item "-mbit-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) force structures +and unions that contain bit-fields to be aligned to the base type of the +bit-field. +.Sp +For example, by default a structure containing nothing but 8 +\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 is aligned to a 4\-byte +boundary and has a size of 4 bytes. By using \fB\-mno\-bit\-align\fR, +the structure is aligned to a 1\-byte boundary and is 1 byte in +size. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +unaligned memory references are handled by the system. +.IP "\fB\-mrelocatable\fR" 4 +.IX Item "-mrelocatable" +.PD 0 +.IP "\fB\-mno\-relocatable\fR" 4 +.IX Item "-mno-relocatable" +.PD +Generate code that allows (does not allow) a static executable to be +relocated to a different address at run time. A simple embedded +PowerPC system loader should relocate the entire contents of +\&\f(CW\*(C`.got2\*(C'\fR and 4\-byte locations listed in the \f(CW\*(C`.fixup\*(C'\fR section, +a table of 32\-bit addresses generated by this option. For this to +work, all objects linked together must be compiled with +\&\fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR. +\&\fB\-mrelocatable\fR code aligns the stack to an 8\-byte boundary. +.IP "\fB\-mrelocatable\-lib\fR" 4 +.IX Item "-mrelocatable-lib" +.PD 0 +.IP "\fB\-mno\-relocatable\-lib\fR" 4 +.IX Item "-mno-relocatable-lib" +.PD +Like \fB\-mrelocatable\fR, \fB\-mrelocatable\-lib\fR generates a +\&\f(CW\*(C`.fixup\*(C'\fR section to allow static executables to be relocated at +run time, but \fB\-mrelocatable\-lib\fR does not use the smaller stack +alignment of \fB\-mrelocatable\fR. Objects compiled with +\&\fB\-mrelocatable\-lib\fR may be linked with objects compiled with +any combination of the \fB\-mrelocatable\fR options. +.IP "\fB\-mno\-toc\fR" 4 +.IX Item "-mno-toc" +.PD 0 +.IP "\fB\-mtoc\fR" 4 +.IX Item "-mtoc" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +register 2 contains a pointer to a global area pointing to the addresses +used in the program. +.IP "\fB\-mlittle\fR" 4 +.IX Item "-mlittle" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in little-endian mode. The \fB\-mlittle\-endian\fR option is +the same as \fB\-mlittle\fR. +.IP "\fB\-mbig\fR" 4 +.IX Item "-mbig" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in big-endian mode. The \fB\-mbig\-endian\fR option is +the same as \fB\-mbig\fR. +.IP "\fB\-mdynamic\-no\-pic\fR" 4 +.IX Item "-mdynamic-no-pic" +On Darwin and Mac \s-1OS X\s0 systems, compile code so that it is not +relocatable, but that its external references are relocatable. The +resulting code is suitable for applications, but not shared +libraries. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The runtime system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mprioritize\-restricted\-insns=\fR\fIpriority\fR" 4 +.IX Item "-mprioritize-restricted-insns=priority" +This option controls the priority that is assigned to +dispatch-slot restricted instructions during the second scheduling +pass. The argument \fIpriority\fR takes the value \fB0\fR, \fB1\fR, +or \fB2\fR to assign no, highest, or second-highest (respectively) +priority to dispatch-slot restricted +instructions. +.IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4 +.IX Item "-msched-costly-dep=dependence_type" +This option controls which dependences are considered costly +by the target during instruction scheduling. The argument +\&\fIdependence_type\fR takes one of the following values: +.RS 4 +.IP "\fBno\fR" 4 +.IX Item "no" +No dependence is costly. +.IP "\fBall\fR" 4 +.IX Item "all" +All dependences are costly. +.IP "\fBtrue_store_to_load\fR" 4 +.IX Item "true_store_to_load" +A true dependence from store to load is costly. +.IP "\fBstore_to_load\fR" 4 +.IX Item "store_to_load" +Any dependence from store to load is costly. +.IP "\fInumber\fR" 4 +.IX Item "number" +Any dependence for which the latency is greater than or equal to +\&\fInumber\fR is costly. +.RE +.RS 4 +.RE +.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4 +.IX Item "-minsert-sched-nops=scheme" +This option controls which \s-1NOP\s0 insertion scheme is used during +the second scheduling pass. The argument \fIscheme\fR takes one of the +following values: +.RS 4 +.IP "\fBno\fR" 4 +.IX Item "no" +Don't insert NOPs. +.IP "\fBpad\fR" 4 +.IX Item "pad" +Pad with NOPs any dispatch group that has vacant issue slots, +according to the scheduler's grouping. +.IP "\fBregroup_exact\fR" 4 +.IX Item "regroup_exact" +Insert NOPs to force costly dependent insns into +separate groups. Insert exactly as many NOPs as needed to force an insn +to a new group, according to the estimated processor grouping. +.IP "\fInumber\fR" 4 +.IX Item "number" +Insert NOPs to force costly dependent insns into +separate groups. Insert \fInumber\fR NOPs to force an insn to a new group. +.RE +.RS 4 +.RE +.IP "\fB\-mcall\-sysv\fR" 4 +.IX Item "-mcall-sysv" +On System V.4 and embedded PowerPC systems compile code using calling +conventions that adhere to the March 1995 draft of the System V +Application Binary Interface, PowerPC processor supplement. This is the +default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR. +.IP "\fB\-mcall\-sysv\-eabi\fR" 4 +.IX Item "-mcall-sysv-eabi" +.PD 0 +.IP "\fB\-mcall\-eabi\fR" 4 +.IX Item "-mcall-eabi" +.PD +Specify both \fB\-mcall\-sysv\fR and \fB\-meabi\fR options. +.IP "\fB\-mcall\-sysv\-noeabi\fR" 4 +.IX Item "-mcall-sysv-noeabi" +Specify both \fB\-mcall\-sysv\fR and \fB\-mno\-eabi\fR options. +.IP "\fB\-mcall\-aixdesc\fR" 4 +.IX Item "-mcall-aixdesc" +On System V.4 and embedded PowerPC systems compile code for the \s-1AIX\s0 +operating system. +.IP "\fB\-mcall\-linux\fR" 4 +.IX Item "-mcall-linux" +On System V.4 and embedded PowerPC systems compile code for the +Linux-based \s-1GNU\s0 system. +.IP "\fB\-mcall\-freebsd\fR" 4 +.IX Item "-mcall-freebsd" +On System V.4 and embedded PowerPC systems compile code for the +FreeBSD operating system. +.IP "\fB\-mcall\-netbsd\fR" 4 +.IX Item "-mcall-netbsd" +On System V.4 and embedded PowerPC systems compile code for the +NetBSD operating system. +.IP "\fB\-mcall\-openbsd\fR" 4 +.IX Item "-mcall-openbsd" +On System V.4 and embedded PowerPC systems compile code for the +OpenBSD operating system. +.IP "\fB\-mtraceback=\fR\fItraceback_type\fR" 4 +.IX Item "-mtraceback=traceback_type" +Select the type of traceback table. Valid values for \fItraceback_type\fR +are \fBfull\fR, \fBpart\fR, and \fBno\fR. +.IP "\fB\-maix\-struct\-return\fR" 4 +.IX Item "-maix-struct-return" +Return all structures in memory (as specified by the \s-1AIX ABI\s0). +.IP "\fB\-msvr4\-struct\-return\fR" 4 +.IX Item "-msvr4-struct-return" +Return structures smaller than 8 bytes in registers (as specified by the +\&\s-1SVR4 ABI\s0). +.IP "\fB\-mabi=\fR\fIabi-type\fR" 4 +.IX Item "-mabi=abi-type" +Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. +Valid values are \fBaltivec\fR, \fBno-altivec\fR, +\&\fBibmlongdouble\fR, \fBieeelongdouble\fR, +\&\fBelfv1\fR, \fBelfv2\fR. +.IP "\fB\-mabi=ibmlongdouble\fR" 4 +.IX Item "-mabi=ibmlongdouble" +Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended-precision long double. +This is not likely to work if your system defaults to using \s-1IEEE\s0 +extended-precision long double. If you change the long double type +from \s-1IEEE\s0 extended-precision, the compiler will issue a warning unless +you use the \fB\-Wno\-psabi\fR option. Requires \fB\-mlong\-double\-128\fR +to be enabled. +.IP "\fB\-mabi=ieeelongdouble\fR" 4 +.IX Item "-mabi=ieeelongdouble" +Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. +This is not likely to work if your system defaults to using \s-1IBM\s0 +extended-precision long double. If you change the long double type +from \s-1IBM\s0 extended-precision, the compiler will issue a warning unless +you use the \fB\-Wno\-psabi\fR option. Requires \fB\-mlong\-double\-128\fR +to be enabled. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI.\s0 +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI.\s0 +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mgnu\-attribute\fR" 4 +.IX Item "-mgnu-attribute" +.PD 0 +.IP "\fB\-mno\-gnu\-attribute\fR" 4 +.IX Item "-mno-gnu-attribute" +.PD +Emit .gnu_attribute assembly directives to set tag/value pairs in a +\&.gnu.attributes section that specify \s-1ABI\s0 variations in function +parameters or return values. +.IP "\fB\-mprototype\fR" 4 +.IX Item "-mprototype" +.PD 0 +.IP "\fB\-mno\-prototype\fR" 4 +.IX Item "-mno-prototype" +.PD +On System V.4 and embedded PowerPC systems assume that all calls to +variable argument functions are properly prototyped. Otherwise, the +compiler must insert an instruction before every non-prototyped call to +set or clear bit 6 of the condition code register (\f(CW\*(C`CR\*(C'\fR) to +indicate whether floating-point values are passed in the floating-point +registers in case the function takes variable arguments. With +\&\fB\-mprototype\fR, only calls to prototyped variable argument functions +set or clear the bit. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +On embedded PowerPC systems, assume that the startup module is called +\&\fIsim\-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and +\&\fIlibc.a\fR. This is the default for \fBpowerpc\-*\-eabisim\fR +configurations. +.IP "\fB\-mmvme\fR" 4 +.IX Item "-mmvme" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mads\fR" 4 +.IX Item "-mads" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-myellowknife\fR" 4 +.IX Item "-myellowknife" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mvxworks\fR" 4 +.IX Item "-mvxworks" +On System V.4 and embedded PowerPC systems, specify that you are +compiling for a VxWorks system. +.IP "\fB\-memb\fR" 4 +.IX Item "-memb" +On embedded PowerPC systems, set the \f(CW\*(C`PPC_EMB\*(C'\fR bit in the \s-1ELF\s0 flags +header to indicate that \fBeabi\fR extended relocations are used. +.IP "\fB\-meabi\fR" 4 +.IX Item "-meabi" +.PD 0 +.IP "\fB\-mno\-eabi\fR" 4 +.IX Item "-mno-eabi" +.PD +On System V.4 and embedded PowerPC systems do (do not) adhere to the +Embedded Applications Binary Interface (\s-1EABI\s0), which is a set of +modifications to the System V.4 specifications. Selecting \fB\-meabi\fR +means that the stack is aligned to an 8\-byte boundary, a function +\&\f(CW\*(C`_\|_eabi\*(C'\fR is called from \f(CW\*(C`main\*(C'\fR to set up the \s-1EABI\s0 +environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and +\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas. Selecting +\&\fB\-mno\-eabi\fR means that the stack is aligned to a 16\-byte boundary, +no \s-1EABI\s0 initialization function is called from \f(CW\*(C`main\*(C'\fR, and the +\&\fB\-msdata\fR option only uses \f(CW\*(C`r13\*(C'\fR to point to a single +small data area. The \fB\-meabi\fR option is on by default if you +configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options. +.IP "\fB\-msdata=eabi\fR" 4 +.IX Item "-msdata=eabi" +On System V.4 and embedded PowerPC systems, put small initialized +\&\f(CW\*(C`const\*(C'\fR global and static data in the \f(CW\*(C`.sdata2\*(C'\fR section, which +is pointed to by register \f(CW\*(C`r2\*(C'\fR. Put small initialized +non\-\f(CW\*(C`const\*(C'\fR global and static data in the \f(CW\*(C`.sdata\*(C'\fR section, +which is pointed to by register \f(CW\*(C`r13\*(C'\fR. Put small uninitialized +global and static data in the \f(CW\*(C`.sbss\*(C'\fR section, which is adjacent to +the \f(CW\*(C`.sdata\*(C'\fR section. The \fB\-msdata=eabi\fR option is +incompatible with the \fB\-mrelocatable\fR option. The +\&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option. +.IP "\fB\-msdata=sysv\fR" 4 +.IX Item "-msdata=sysv" +On System V.4 and embedded PowerPC systems, put small global and static +data in the \f(CW\*(C`.sdata\*(C'\fR section, which is pointed to by register +\&\f(CW\*(C`r13\*(C'\fR. Put small uninitialized global and static data in the +\&\f(CW\*(C`.sbss\*(C'\fR section, which is adjacent to the \f(CW\*(C`.sdata\*(C'\fR section. +The \fB\-msdata=sysv\fR option is incompatible with the +\&\fB\-mrelocatable\fR option. +.IP "\fB\-msdata=default\fR" 4 +.IX Item "-msdata=default" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used, +compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the +same as \fB\-msdata=sysv\fR. +.IP "\fB\-msdata=data\fR" 4 +.IX Item "-msdata=data" +On System V.4 and embedded PowerPC systems, put small global +data in the \f(CW\*(C`.sdata\*(C'\fR section. Put small uninitialized global +data in the \f(CW\*(C`.sbss\*(C'\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR +to address small data however. This is the default behavior unless +other \fB\-msdata\fR options are used. +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +.PD 0 +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD +On embedded PowerPC systems, put all initialized global and static data +in the \f(CW\*(C`.data\*(C'\fR section, and all uninitialized data in the +\&\f(CW\*(C`.bss\*(C'\fR section. +.IP "\fB\-mreadonly\-in\-sdata\fR" 4 +.IX Item "-mreadonly-in-sdata" +Put read-only objects in the \f(CW\*(C`.sdata\*(C'\fR section as well. This is the +default. +.IP "\fB\-mblock\-move\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-move-inline-limit=num" +Inline all block moves (such as calls to \f(CW\*(C`memcpy\*(C'\fR or structure +copies) less than or equal to \fInum\fR bytes. The minimum value for +\&\fInum\fR is 32 bytes on 32\-bit targets and 64 bytes on 64\-bit +targets. The default value is target-specific. +.IP "\fB\-mblock\-compare\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-compare-inline-limit=num" +Generate non-looping inline code for all block compares (such as calls +to \f(CW\*(C`memcmp\*(C'\fR or structure compares) less than or equal to \fInum\fR +bytes. If \fInum\fR is 0, all inline expansion (non-loop and loop) of +block compare is disabled. The default value is target-specific. +.IP "\fB\-mblock\-compare\-inline\-loop\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-compare-inline-loop-limit=num" +Generate an inline expansion using loop code for all block compares that +are less than or equal to \fInum\fR bytes, but greater than the limit +for non-loop inline block compare expansion. If the block length is not +constant, at most \fInum\fR bytes will be compared before \f(CW\*(C`memcmp\*(C'\fR +is called to compare the remainder of the block. The default value is +target-specific. +.IP "\fB\-mstring\-compare\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mstring-compare-inline-limit=num" +Compare at most \fInum\fR string bytes with inline code. +If the difference or end of string is not found at the +end of the inline compare a call to \f(CW\*(C`strcmp\*(C'\fR or \f(CW\*(C`strncmp\*(C'\fR will +take care of the rest of the comparison. The default is 64 bytes. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +On embedded PowerPC systems, put global and static items less than or +equal to \fInum\fR bytes into the small data or \s-1BSS\s0 sections instead of +the normal data or \s-1BSS\s0 section. By default, \fInum\fR is 8. The +\&\fB\-G\fR \fInum\fR switch is also passed to the linker. +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +.IP "\fB\-mregnames\fR" 4 +.IX Item "-mregnames" +.PD 0 +.IP "\fB\-mno\-regnames\fR" 4 +.IX Item "-mno-regnames" +.PD +On System V.4 and embedded PowerPC systems do (do not) emit register +names in the assembly language output using symbolic forms. +.IP "\fB\-mlongcall\fR" 4 +.IX Item "-mlongcall" +.PD 0 +.IP "\fB\-mno\-longcall\fR" 4 +.IX Item "-mno-longcall" +.PD +By default assume that all calls are far away so that a longer and more +expensive calling sequence is required. This is required for calls +farther than 32 megabytes (33,554,432 bytes) from the current location. +A short call is generated if the compiler knows +the call cannot be that far away. This setting can be overridden by +the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma +longcall(0)\*(C'\fR. +.Sp +Some linkers are capable of detecting out-of-range calls and generating +glue code on the fly. On these systems, long calls are unnecessary and +generate slower code. As of this writing, the \s-1AIX\s0 linker can do this, +as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature +to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well. +.Sp +On PowerPC64 ELFv2 and 32\-bit PowerPC systems with newer \s-1GNU\s0 linkers, +\&\s-1GCC\s0 can generate long calls using an inline \s-1PLT\s0 call sequence (see +\&\fB\-mpltseq\fR). PowerPC with \fB\-mbss\-plt\fR and PowerPC64 +ELFv1 (big-endian) do not support inline \s-1PLT\s0 calls. +.Sp +On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR generates \f(CW\*(C`jbsr +callee, L42\*(C'\fR, plus a \fIbranch island\fR (glue code). The two target +addresses represent the callee and the branch island. The +Darwin/PPC linker prefers the first address and generates a \f(CW\*(C`bl +callee\*(C'\fR if the \s-1PPC\s0 \f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; +otherwise, the linker generates \f(CW\*(C`bl L42\*(C'\fR to call the branch +island. The branch island is appended to the body of the +calling function; it computes the full 32\-bit address of the callee +and jumps to it. +.Sp +On Mach-O (Darwin) systems, this option directs the compiler emit to +the glue for every direct call, and the Darwin linker decides whether +to use or discard it. +.Sp +In the future, \s-1GCC\s0 may ignore all longcall specifications +when the linker is known to generate glue. +.IP "\fB\-mpltseq\fR" 4 +.IX Item "-mpltseq" +.PD 0 +.IP "\fB\-mno\-pltseq\fR" 4 +.IX Item "-mno-pltseq" +.PD +Implement (do not implement) \-fno\-plt and long calls using an inline +\&\s-1PLT\s0 call sequence that supports lazy linking and long calls to +functions in dlopen'd shared libraries. Inline \s-1PLT\s0 calls are only +supported on PowerPC64 ELFv2 and 32\-bit PowerPC systems with newer \s-1GNU\s0 +linkers, and are enabled by default if the support is detected when +configuring \s-1GCC,\s0 and, in the case of 32\-bit PowerPC, if \s-1GCC\s0 is +configured with \fB\-\-enable\-secureplt\fR. \fB\-mpltseq\fR code +and \fB\-mbss\-plt\fR 32\-bit PowerPC relocatable objects may not be +linked together. +.IP "\fB\-mtls\-markers\fR" 4 +.IX Item "-mtls-markers" +.PD 0 +.IP "\fB\-mno\-tls\-markers\fR" 4 +.IX Item "-mno-tls-markers" +.PD +Mark (do not mark) calls to \f(CW\*(C`_\|_tls_get_addr\*(C'\fR with a relocation +specifying the function argument. The relocation allows the linker to +reliably associate function call with argument setup instructions for +\&\s-1TLS\s0 optimization, which in turn allows \s-1GCC\s0 to better schedule the +sequence. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +.PD 0 +.IP "\fB\-mno\-recip\fR" 4 +.IX Item "-mno-recip" +.PD +This option enables use of the reciprocal estimate and +reciprocal square root estimate instructions with additional +Newton-Raphson steps to increase precision instead of doing a divide or +square root and divide for floating-point arguments. You should use +the \fB\-ffast\-math\fR option when using \fB\-mrecip\fR (or at +least \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-ffinite\-math\-only\fR, \fB\-freciprocal\-math\fR and +\&\fB\-fno\-trapping\-math\fR). Note that while the throughput of the +sequence is generally higher than the throughput of the non-reciprocal +instruction, the precision of the sequence can be decreased by up to 2 +ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square +roots. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option controls which reciprocal estimate instructions +may be used. \fIopt\fR is a comma-separated list of options, which may +be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all estimate instructions. +.IP "\fBdefault\fR" 4 +.IX Item "default" +Enable the default instructions, equivalent to \fB\-mrecip\fR. +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR. +.IP "\fBdiv\fR" 4 +.IX Item "div" +Enable the reciprocal approximation instructions for both +single and double precision. +.IP "\fBdivf\fR" 4 +.IX Item "divf" +Enable the single-precision reciprocal approximation instructions. +.IP "\fBdivd\fR" 4 +.IX Item "divd" +Enable the double-precision reciprocal approximation instructions. +.IP "\fBrsqrt\fR" 4 +.IX Item "rsqrt" +Enable the reciprocal square root approximation instructions for both +single and double precision. +.IP "\fBrsqrtf\fR" 4 +.IX Item "rsqrtf" +Enable the single-precision reciprocal square root approximation instructions. +.IP "\fBrsqrtd\fR" 4 +.IX Item "rsqrtd" +Enable the double-precision reciprocal square root approximation instructions. +.RE +.RS 4 +.Sp +So, for example, \fB\-mrecip=all,!rsqrtd\fR enables +all of the reciprocal estimate instructions, except for the +\&\f(CW\*(C`FRSQRTE\*(C'\fR, \f(CW\*(C`XSRSQRTEDP\*(C'\fR, and \f(CW\*(C`XVRSQRTEDP\*(C'\fR instructions +which handle the double-precision reciprocal square root calculations. +.RE +.IP "\fB\-mrecip\-precision\fR" 4 +.IX Item "-mrecip-precision" +.PD 0 +.IP "\fB\-mno\-recip\-precision\fR" 4 +.IX Item "-mno-recip-precision" +.PD +Assume (do not assume) that the reciprocal estimate instructions +provide higher-precision estimates than is mandated by the PowerPC +\&\s-1ABI.\s0 Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or +\&\fB\-mcpu=power8\fR automatically selects \fB\-mrecip\-precision\fR. +The double-precision square root estimate instructions are not generated by +default on low-precision machines, since they do not provide an +estimate that converges after three steps. +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. The only type supported at present is \fBmass\fR, +which specifies to use \s-1IBM\s0's Mathematical Acceleration Subsystem +(\s-1MASS\s0) libraries for vectorizing intrinsics using external libraries. +\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR, +\&\f(CW\*(C`acoshd2\*(C'\fR, \f(CW\*(C`acoshf4\*(C'\fR, \f(CW\*(C`asind2\*(C'\fR, \f(CW\*(C`asinf4\*(C'\fR, +\&\f(CW\*(C`asinhd2\*(C'\fR, \f(CW\*(C`asinhf4\*(C'\fR, \f(CW\*(C`atan2d2\*(C'\fR, \f(CW\*(C`atan2f4\*(C'\fR, +\&\f(CW\*(C`atand2\*(C'\fR, \f(CW\*(C`atanf4\*(C'\fR, \f(CW\*(C`atanhd2\*(C'\fR, \f(CW\*(C`atanhf4\*(C'\fR, +\&\f(CW\*(C`cbrtd2\*(C'\fR, \f(CW\*(C`cbrtf4\*(C'\fR, \f(CW\*(C`cosd2\*(C'\fR, \f(CW\*(C`cosf4\*(C'\fR, +\&\f(CW\*(C`coshd2\*(C'\fR, \f(CW\*(C`coshf4\*(C'\fR, \f(CW\*(C`erfcd2\*(C'\fR, \f(CW\*(C`erfcf4\*(C'\fR, +\&\f(CW\*(C`erfd2\*(C'\fR, \f(CW\*(C`erff4\*(C'\fR, \f(CW\*(C`exp2d2\*(C'\fR, \f(CW\*(C`exp2f4\*(C'\fR, +\&\f(CW\*(C`expd2\*(C'\fR, \f(CW\*(C`expf4\*(C'\fR, \f(CW\*(C`expm1d2\*(C'\fR, \f(CW\*(C`expm1f4\*(C'\fR, +\&\f(CW\*(C`hypotd2\*(C'\fR, \f(CW\*(C`hypotf4\*(C'\fR, \f(CW\*(C`lgammad2\*(C'\fR, \f(CW\*(C`lgammaf4\*(C'\fR, +\&\f(CW\*(C`log10d2\*(C'\fR, \f(CW\*(C`log10f4\*(C'\fR, \f(CW\*(C`log1pd2\*(C'\fR, \f(CW\*(C`log1pf4\*(C'\fR, +\&\f(CW\*(C`log2d2\*(C'\fR, \f(CW\*(C`log2f4\*(C'\fR, \f(CW\*(C`logd2\*(C'\fR, \f(CW\*(C`logf4\*(C'\fR, +\&\f(CW\*(C`powd2\*(C'\fR, \f(CW\*(C`powf4\*(C'\fR, \f(CW\*(C`sind2\*(C'\fR, \f(CW\*(C`sinf4\*(C'\fR, \f(CW\*(C`sinhd2\*(C'\fR, +\&\f(CW\*(C`sinhf4\*(C'\fR, \f(CW\*(C`sqrtd2\*(C'\fR, \f(CW\*(C`sqrtf4\*(C'\fR, \f(CW\*(C`tand2\*(C'\fR, +\&\f(CW\*(C`tanf4\*(C'\fR, \f(CW\*(C`tanhd2\*(C'\fR, and \f(CW\*(C`tanhf4\*(C'\fR when generating code +for power7. Both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR must also be enabled. The \s-1MASS\s0 +libraries must be specified at link time. +.IP "\fB\-mfriz\fR" 4 +.IX Item "-mfriz" +.PD 0 +.IP "\fB\-mno\-friz\fR" 4 +.IX Item "-mno-friz" +.PD +Generate (do not generate) the \f(CW\*(C`friz\*(C'\fR instruction when the +\&\fB\-funsafe\-math\-optimizations\fR option is used to optimize +rounding of floating-point values to 64\-bit integer and back to floating +point. The \f(CW\*(C`friz\*(C'\fR instruction does not return the same value if +the floating-point number is too large to fit in an integer. +.IP "\fB\-mpointers\-to\-nested\-functions\fR" 4 +.IX Item "-mpointers-to-nested-functions" +.PD 0 +.IP "\fB\-mno\-pointers\-to\-nested\-functions\fR" 4 +.IX Item "-mno-pointers-to-nested-functions" +.PD +Generate (do not generate) code to load up the static chain register +(\f(CW\*(C`r11\*(C'\fR) when calling through a pointer on \s-1AIX\s0 and 64\-bit Linux +systems where a function pointer points to a 3\-word descriptor giving +the function address, \s-1TOC\s0 value to be loaded in register \f(CW\*(C`r2\*(C'\fR, and +static chain value to be loaded in register \f(CW\*(C`r11\*(C'\fR. The +\&\fB\-mpointers\-to\-nested\-functions\fR is on by default. You cannot +call through pointers to nested functions or pointers +to functions compiled in other languages that use the static chain if +you use \fB\-mno\-pointers\-to\-nested\-functions\fR. +.IP "\fB\-msave\-toc\-indirect\fR" 4 +.IX Item "-msave-toc-indirect" +.PD 0 +.IP "\fB\-mno\-save\-toc\-indirect\fR" 4 +.IX Item "-mno-save-toc-indirect" +.PD +Generate (do not generate) code to save the \s-1TOC\s0 value in the reserved +stack location in the function prologue if the function calls through +a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not +saved in the prologue, it is saved just before the call through the +pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC.\s0 +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC.\s0 This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC.\s0 +.Sp +The \fB\-mno\-compat\-align\-parm\fR option is the default. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.IP "\fB\-mstack\-protector\-guard\-symbol=\fR\fIsymbol\fR" 4 +.IX Item "-mstack-protector-guard-symbol=symbol" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for global canary or \fBtls\fR for per-thread +canary in the \s-1TLS\s0 block (the default with \s-1GNU\s0 libc version 2.4 or later). +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which register to use as base register for reading the canary, and from what +offset from that base register. The default for those is as specified in the +relevant \s-1ABI.\s0 \fB\-mstack\-protector\-guard\-symbol=\fR\fIsymbol\fR overrides +the offset with a symbol reference to a canary in the \s-1TLS\s0 block. +.PP +\fI\s-1RX\s0 Options\fR +.IX Subsection "RX Options" +.PP +These command-line options are defined for \s-1RX\s0 targets: +.IP "\fB\-m64bit\-doubles\fR" 4 +.IX Item "-m64bit-doubles" +.PD 0 +.IP "\fB\-m32bit\-doubles\fR" 4 +.IX Item "-m32bit-doubles" +.PD +Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) +or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is +\&\fB\-m32bit\-doubles\fR. \fINote\fR \s-1RX\s0 floating-point hardware only +works on 32\-bit values, which is why the default is +\&\fB\-m32bit\-doubles\fR. +.IP "\fB\-fpu\fR" 4 +.IX Item "-fpu" +.PD 0 +.IP "\fB\-nofpu\fR" 4 +.IX Item "-nofpu" +.PD +Enables (\fB\-fpu\fR) or disables (\fB\-nofpu\fR) the use of \s-1RX\s0 +floating-point hardware. The default is enabled for the \s-1RX600\s0 +series and disabled for the \s-1RX200\s0 series. +.Sp +Floating-point instructions are only generated for 32\-bit floating-point +values, however, so the \s-1FPU\s0 hardware is not used for doubles if the +\&\fB\-m64bit\-doubles\fR option is used. +.Sp +\&\fINote\fR If the \fB\-fpu\fR option is enabled then +\&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. +This is because the \s-1RX FPU\s0 instructions are themselves unsafe. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1RX CPU\s0 to be targeted. Currently three types are +supported, the generic \fB\s-1RX600\s0\fR and \fB\s-1RX200\s0\fR series hardware and +the specific \fB\s-1RX610\s0\fR \s-1CPU.\s0 The default is \fB\s-1RX600\s0\fR. +.Sp +The only difference between \fB\s-1RX600\s0\fR and \fB\s-1RX610\s0\fR is that the +\&\fB\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. +.Sp +The \fB\s-1RX200\s0\fR series does not have a hardware floating-point unit +and so \fB\-nofpu\fR is enabled by default when this type is +selected. +.IP "\fB\-mbig\-endian\-data\fR" 4 +.IX Item "-mbig-endian-data" +.PD 0 +.IP "\fB\-mlittle\-endian\-data\fR" 4 +.IX Item "-mlittle-endian-data" +.PD +Store data (but not code) in the big-endian format. The default is +\&\fB\-mlittle\-endian\-data\fR, i.e. to store data in the little-endian +format. +.IP "\fB\-msmall\-data\-limit=\fR\fIN\fR" 4 +.IX Item "-msmall-data-limit=N" +Specifies the maximum size in bytes of global and static variables +which can be placed into the small data area. Using the small data +area can lead to smaller and faster code, but the size of area is +limited and it is up to the programmer to ensure that the area does +not overflow. Also when the small data area is used one of the \s-1RX\s0's +registers (usually \f(CW\*(C`r13\*(C'\fR) is reserved for use pointing to this +area, so it is no longer available for use by the compiler. This +could result in slower and/or larger code if variables are pushed onto +the stack instead of being held in this register. +.Sp +Note, common variables (variables that have not been initialized) and +constants are not placed into the small data area as they are assigned +to other sections in the output executable. +.Sp +The default value is zero, which disables this feature. Note, this +feature is not enabled by default with higher optimization levels +(\fB\-O2\fR etc) because of the potentially detrimental effects of +reserving a register. It is up to the programmer to experiment and +discover whether this feature is of benefit to their program. See the +description of the \fB\-mpid\fR option for a description of how the +actual register to hold the small data area pointer is chosen. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +.PD 0 +.IP "\fB\-mno\-sim\fR" 4 +.IX Item "-mno-sim" +.PD +Use the simulator runtime. The default is to use the libgloss +board-specific runtime. +.IP "\fB\-mas100\-syntax\fR" 4 +.IX Item "-mas100-syntax" +.PD 0 +.IP "\fB\-mno\-as100\-syntax\fR" 4 +.IX Item "-mno-as100-syntax" +.PD +When generating assembler output use a syntax that is compatible with +Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 +assembler, but it has some restrictions so it is not generated by default. +.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 +.IX Item "-mmax-constant-size=N" +Specifies the maximum size, in bytes, of a constant that can be used as +an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does +allow constants of up to 4 bytes in length to be used in instructions, +a longer value equates to a longer instruction. Thus in some +circumstances it can be beneficial to restrict the size of constants +that are used in instructions. Constants that are too big are instead +placed into a constant pool and referenced via register indirection. +.Sp +The value \fIN\fR can be between 0 and 4. A value of 0 (the default) +or 4 means that constants of any size are allowed. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Enable linker relaxation. Linker relaxation is a process whereby the +linker attempts to reduce the size of a program by finding shorter +versions of various instructions. Disabled by default. +.IP "\fB\-mint\-register=\fR\fIN\fR" 4 +.IX Item "-mint-register=N" +Specify the number of registers to reserve for fast interrupt handler +functions. The value \fIN\fR can be between 0 and 4. A value of 1 +means that register \f(CW\*(C`r13\*(C'\fR is reserved for the exclusive use +of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and +\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and +\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. +A value of 0, the default, does not reserve any registers. +.IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 +.IX Item "-msave-acc-in-interrupts" +Specifies that interrupt handler functions should preserve the +accumulator register. This is only necessary if normal code might use +the accumulator register, for example because it performs 64\-bit +multiplications. The default is to ignore the accumulator as this +makes the interrupt handlers faster. +.IP "\fB\-mpid\fR" 4 +.IX Item "-mpid" +.PD 0 +.IP "\fB\-mno\-pid\fR" 4 +.IX Item "-mno-pid" +.PD +Enables the generation of position independent data. When enabled any +access to constant data is done via an offset from a base address +held in a register. This allows the location of constant data to be +determined at run time without requiring the executable to be +relocated, which is a benefit to embedded applications with tight +memory constraints. Data that can be modified is not affected by this +option. +.Sp +Note, using this feature reserves a register, usually \f(CW\*(C`r13\*(C'\fR, for +the constant data base address. This can result in slower and/or +larger code, especially in complicated functions. +.Sp +The actual register chosen to hold the constant data base address +depends upon whether the \fB\-msmall\-data\-limit\fR and/or the +\&\fB\-mint\-register\fR command-line options are enabled. Starting +with register \f(CW\*(C`r13\*(C'\fR and proceeding downwards, registers are +allocated first to satisfy the requirements of \fB\-mint\-register\fR, +then \fB\-mpid\fR and finally \fB\-msmall\-data\-limit\fR. Thus it +is possible for the small data area register to be \f(CW\*(C`r8\*(C'\fR if both +\&\fB\-mint\-register=4\fR and \fB\-mpid\fR are specified on the +command line. +.Sp +By default this feature is not enabled. The default can be restored +via the \fB\-mno\-pid\fR command-line option. +.IP "\fB\-mno\-warn\-multiple\-fast\-interrupts\fR" 4 +.IX Item "-mno-warn-multiple-fast-interrupts" +.PD 0 +.IP "\fB\-mwarn\-multiple\-fast\-interrupts\fR" 4 +.IX Item "-mwarn-multiple-fast-interrupts" +.PD +Prevents \s-1GCC\s0 from issuing a warning message if it finds more than one +fast interrupt handler when it is compiling a file. The default is to +issue a warning for each extra fast interrupt handler found, as the \s-1RX\s0 +only supports one such interrupt. +.IP "\fB\-mallow\-string\-insns\fR" 4 +.IX Item "-mallow-string-insns" +.PD 0 +.IP "\fB\-mno\-allow\-string\-insns\fR" 4 +.IX Item "-mno-allow-string-insns" +.PD +Enables or disables the use of the string manipulation instructions +\&\f(CW\*(C`SMOVF\*(C'\fR, \f(CW\*(C`SCMPU\*(C'\fR, \f(CW\*(C`SMOVB\*(C'\fR, \f(CW\*(C`SMOVU\*(C'\fR, \f(CW\*(C`SUNTIL\*(C'\fR +\&\f(CW\*(C`SWHILE\*(C'\fR and also the \f(CW\*(C`RMPA\*(C'\fR instruction. These +instructions may prefetch data, which is not safe to do if accessing +an I/O register. (See section 12.2.7 of the \s-1RX62N\s0 Group User's Manual +for more information). +.Sp +The default is to allow these instructions, but it is not possible for +\&\s-1GCC\s0 to reliably detect all circumstances where a string instruction +might be used to access an I/O register, so their use cannot be +disabled automatically. Instead it is reliant upon the programmer to +use the \fB\-mno\-allow\-string\-insns\fR option if their program +accesses I/O space. +.Sp +When the instructions are enabled \s-1GCC\s0 defines the C preprocessor +symbol \f(CW\*(C`_\|_RX_ALLOW_STRING_INSNS_\|_\*(C'\fR, otherwise it defines the +symbol \f(CW\*(C`_\|_RX_DISALLOW_STRING_INSNS_\|_\*(C'\fR. +.IP "\fB\-mjsr\fR" 4 +.IX Item "-mjsr" +.PD 0 +.IP "\fB\-mno\-jsr\fR" 4 +.IX Item "-mno-jsr" +.PD +Use only (or not only) \f(CW\*(C`JSR\*(C'\fR instructions to access functions. +This option can be used when code size exceeds the range of \f(CW\*(C`BSR\*(C'\fR +instructions. Note that \fB\-mno\-jsr\fR does not mean to not use +\&\f(CW\*(C`JSR\*(C'\fR but instead means that any type of branch may be used. +.PP +\&\fINote:\fR The generic \s-1GCC\s0 command-line option \fB\-ffixed\-\fR\fIreg\fR +has special significance to the \s-1RX\s0 port when used with the +\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a +function intended to process fast interrupts. \s-1GCC\s0 ensures +that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR +and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the +corresponding registers have been restricted via the +\&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command-line +options. +.PP +\fIS/390 and zSeries Options\fR +.IX Subsection "S/390 and zSeries Options" +.PP +These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions and registers +for floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR are used to perform floating-point +operations. When \fB\-mhard\-float\fR is specified, the compiler +generates \s-1IEEE\s0 floating-point instructions. This is the default. +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.PD 0 +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +Use (do not use) the hardware decimal-floating-point instructions for +decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is +specified, functions in \fIlibgcc.a\fR are used to perform +decimal-floating-point operations. When \fB\-mhard\-dfp\fR is +specified, the compiler generates decimal-floating-point hardware +instructions. This is the default for \fB\-march=z9\-ec\fR or higher. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default. +.IP "\fB\-mbackchain\fR" 4 +.IX Item "-mbackchain" +.PD 0 +.IP "\fB\-mno\-backchain\fR" 4 +.IX Item "-mno-backchain" +.PD +Store (do not store) the address of the caller's frame as backchain pointer +into the callee's stack frame. +A backchain may be needed to allow debugging using tools that do not understand +\&\s-1DWARF\s0 call frame information. +When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored +at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, +the backchain is placed into the topmost word of the 96/160 byte register +save area. +.Sp +In general, code compiled with \fB\-mbackchain\fR is call-compatible with +code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain +for debugging purposes usually requires that the whole binary is built with +\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not maintain the backchain. +.IP "\fB\-mpacked\-stack\fR" 4 +.IX Item "-mpacked-stack" +.PD 0 +.IP "\fB\-mno\-packed\-stack\fR" 4 +.IX Item "-mno-packed-stack" +.PD +Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is +specified, the compiler uses the all fields of the 96/160 byte register save +area only for their default purpose; unused fields still take up stack space. +When \fB\-mpacked\-stack\fR is specified, register save slots are densely +packed at the top of the register save area; unused space is reused for other +purposes, allowing for more efficient use of the available stack space. +However, when \fB\-mbackchain\fR is also in effect, the topmost word of +the save area is always used to store the backchain, and the return address +register is always saved two words below the backchain. +.Sp +As long as the stack frame backchain is not used, code generated with +\&\fB\-mpacked\-stack\fR is call-compatible with code generated with +\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC 2.95\s0 for +S/390 or zSeries generated code that uses the stack frame backchain at run +time, not just for debugging purposes. Such code is not call-compatible +with code compiled with \fB\-mpacked\-stack\fR. Also, note that the +combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not use the packed stack layout. +.IP "\fB\-msmall\-exec\fR" 4 +.IX Item "-msmall-exec" +.PD 0 +.IP "\fB\-mno\-small\-exec\fR" 4 +.IX Item "-mno-small-exec" +.PD +Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction +to do subroutine calls. +This only works reliably if the total executable size does not +exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, +which does not have this limitation. +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD 0 +.IP "\fB\-m31\fR" 4 +.IX Item "-m31" +.PD +When \fB\-m31\fR is specified, generate code compliant to the +GNU/Linux for S/390 \s-1ABI.\s0 When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI.\s0 This allows \s-1GCC\s0 in +particular to generate 64\-bit instructions. For the \fBs390\fR +targets, the default is \fB\-m31\fR, while the \fBs390x\fR +targets default to \fB\-m64\fR. +.IP "\fB\-mzarch\fR" 4 +.IX Item "-mzarch" +.PD 0 +.IP "\fB\-mesa\fR" 4 +.IX Item "-mesa" +.PD +When \fB\-mzarch\fR is specified, generate code using the +instructions available on z/Architecture. +When \fB\-mesa\fR is specified, generate code using the +instructions available on \s-1ESA/390.\s0 Note that \fB\-mesa\fR is +not possible with \fB\-m64\fR. +When generating code compliant to the GNU/Linux for S/390 \s-1ABI,\s0 +the default is \fB\-mesa\fR. When generating code compliant +to the GNU/Linux for zSeries \s-1ABI,\s0 the default is \fB\-mzarch\fR. +.IP "\fB\-mhtm\fR" 4 +.IX Item "-mhtm" +.PD 0 +.IP "\fB\-mno\-htm\fR" 4 +.IX Item "-mno-htm" +.PD +The \fB\-mhtm\fR option enables a set of builtins making use of +instructions available with the transactional execution facility +introduced with the \s-1IBM\s0 zEnterprise \s-1EC12\s0 machine generation +\&\fBS/390 System z Built-in Functions\fR. +\&\fB\-mhtm\fR is enabled by default when using \fB\-march=zEC12\fR. +.IP "\fB\-mvx\fR" 4 +.IX Item "-mvx" +.PD 0 +.IP "\fB\-mno\-vx\fR" 4 +.IX Item "-mno-vx" +.PD +When \fB\-mvx\fR is specified, generate code using the instructions +available with the vector extension facility introduced with the \s-1IBM\s0 +z13 machine generation. +This option changes the \s-1ABI\s0 for some vector type values with regard to +alignment and calling conventions. In case vector type values are +being used in an ABI-relevant context a \s-1GAS\s0 \fB.gnu_attribute\fR +command will be added to mark the resulting binary with the \s-1ABI\s0 used. +\&\fB\-mvx\fR is enabled by default when using \fB\-march=z13\fR. +.IP "\fB\-mzvector\fR" 4 +.IX Item "-mzvector" +.PD 0 +.IP "\fB\-mno\-zvector\fR" 4 +.IX Item "-mno-zvector" +.PD +The \fB\-mzvector\fR option enables vector language extensions and +builtins using instructions available with the vector extension +facility introduced with the \s-1IBM\s0 z13 machine generation. +This option adds support for \fBvector\fR to be used as a keyword to +define vector type variables and arguments. \fBvector\fR is only +available when \s-1GNU\s0 extensions are enabled. It will not be expanded +when requesting strict standard compliance e.g. with \fB\-std=c99\fR. +In addition to the \s-1GCC\s0 low-level builtins \fB\-mzvector\fR enables +a set of builtins added for compatibility with AltiVec-style +implementations like Power and Cell. In order to make use of these +builtins the header file \fIvecintrin.h\fR needs to be included. +\&\fB\-mzvector\fR is disabled by default. +.IP "\fB\-mmvcle\fR" 4 +.IX Item "-mmvcle" +.PD 0 +.IP "\fB\-mno\-mvcle\fR" 4 +.IX Item "-mno-mvcle" +.PD +Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction +to perform block moves. When \fB\-mno\-mvcle\fR is specified, +use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for +size. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +.PD 0 +.IP "\fB\-mno\-debug\fR" 4 +.IX Item "-mno-debug" +.PD +Print (or do not print) additional debug information when compiling. +The default is to not print debug information. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate code that runs on \fIcpu-type\fR, which is the name of a +system representing a certain processor type. Possible values for +\&\fIcpu-type\fR are \fBz900\fR/\fBarch5\fR, \fBz990\fR/\fBarch6\fR, +\&\fBz9\-109\fR, \fBz9\-ec\fR/\fBarch7\fR, \fBz10\fR/\fBarch8\fR, +\&\fBz196\fR/\fBarch9\fR, \fBzEC12\fR, \fBz13\fR/\fBarch11\fR, +\&\fBz14\fR/\fBarch12\fR, and \fBnative\fR. +.Sp +The default is \fB\-march=z900\fR. +.Sp +Specifying \fBnative\fR as cpu type can be used to select the best +architecture option for the host processor. +\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize the +processor. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, +except for the \s-1ABI\s0 and the set of available instructions. +The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. +The default is the value used for \fB\-march\fR. +.IP "\fB\-mtpf\-trace\fR" 4 +.IX Item "-mtpf-trace" +.PD 0 +.IP "\fB\-mno\-tpf\-trace\fR" 4 +.IX Item "-mno-tpf-trace" +.PD +Generate code that adds (does not add) in \s-1TPF OS\s0 specific branches to trace +routines in the operating system. This option is off by default, even +when compiling for the \s-1TPF OS.\s0 +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default if +hardware floating point is used. +.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 +.IX Item "-mwarn-framesize=framesize" +Emit a warning if the current function exceeds the given frame size. Because +this is a compile-time check it doesn't need to be a real problem when the program +runs. It is intended to identify functions that most probably cause +a stack overflow. It is useful to be used in an environment with limited stack +size e.g. the linux kernel. +.IP "\fB\-mwarn\-dynamicstack\fR" 4 +.IX Item "-mwarn-dynamicstack" +Emit a warning if the function calls \f(CW\*(C`alloca\*(C'\fR or uses dynamically-sized +arrays. This is generally a bad idea with a limited stack size. +.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 +.IX Item "-mstack-guard=stack-guard" +.PD 0 +.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 +.IX Item "-mstack-size=stack-size" +.PD +If these options are provided the S/390 back end emits additional instructions in +the function prologue that trigger a trap if the stack size is \fIstack-guard\fR +bytes above the \fIstack-size\fR (remember that the stack on S/390 grows downward). +If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than +the frame size of the compiled function is chosen. +These options are intended to be used to help debugging stack overflow problems. +The additionally emitted code causes only little overhead and hence can also be +used in production-like systems without greater performance degradation. The given +values have to be exact powers of 2 and \fIstack-size\fR has to be greater than +\&\fIstack-guard\fR without exceeding 64k. +In order to be efficient the extra code makes the assumption that the stack starts +at an address aligned to the value given by \fIstack-size\fR. +The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch=\fR\fIpre-halfwords\fR\fB,\fR\fIpost-halfwords\fR" 4 +.IX Item "-mhotpatch=pre-halfwords,post-halfwords" +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +\&\s-1NOP\s0 instructions (\fIpre-halfwords\fR, maximum 1000000). After +the label, 2 * \fIpost-halfwords\fR bytes are appended, using the +largest \s-1NOP\s0 like instructions the architecture allows (maximum +1000000). +.Sp +If both arguments are zero, hotpatching is disabled. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. +.PP +\fIScore Options\fR +.IX Subsection "Score Options" +.PP +These options are defined for Score implementations: +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Compile code for big-endian mode. This is the default. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Compile code for little-endian mode. +.IP "\fB\-mnhwloop\fR" 4 +.IX Item "-mnhwloop" +Disable generation of \f(CW\*(C`bcnz\*(C'\fR instructions. +.IP "\fB\-muls\fR" 4 +.IX Item "-muls" +Enable generation of unaligned load and store instructions. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mscore5\fR" 4 +.IX Item "-mscore5" +Specify the \s-1SCORE5\s0 as the target architecture. +.IP "\fB\-mscore5u\fR" 4 +.IX Item "-mscore5u" +Specify the \s-1SCORE5U\s0 of the target architecture. +.IP "\fB\-mscore7\fR" 4 +.IX Item "-mscore7" +Specify the \s-1SCORE7\s0 as the target architecture. This is the default. +.IP "\fB\-mscore7d\fR" 4 +.IX Item "-mscore7d" +Specify the \s-1SCORE7D\s0 as the target architecture. +.PP +\fI\s-1SH\s0 Options\fR +.IX Subsection "SH Options" +.PP +These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: +.IP "\fB\-m1\fR" 4 +.IX Item "-m1" +Generate code for the \s-1SH1.\s0 +.IP "\fB\-m2\fR" 4 +.IX Item "-m2" +Generate code for the \s-1SH2.\s0 +.IP "\fB\-m2e\fR" 4 +.IX Item "-m2e" +Generate code for the SH2e. +.IP "\fB\-m2a\-nofpu\fR" 4 +.IX Item "-m2a-nofpu" +Generate code for the SH2a without \s-1FPU,\s0 or for a SH2a\-FPU in such a way +that the floating-point unit is not used. +.IP "\fB\-m2a\-single\-only\fR" 4 +.IX Item "-m2a-single-only" +Generate code for the SH2a\-FPU, in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m2a\-single\fR" 4 +.IX Item "-m2a-single" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m2a\fR" 4 +.IX Item "-m2a" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +double-precision mode by default. +.IP "\fB\-m3\fR" 4 +.IX Item "-m3" +Generate code for the \s-1SH3.\s0 +.IP "\fB\-m3e\fR" 4 +.IX Item "-m3e" +Generate code for the SH3e. +.IP "\fB\-m4\-nofpu\fR" 4 +.IX Item "-m4-nofpu" +Generate code for the \s-1SH4\s0 without a floating-point unit. +.IP "\fB\-m4\-single\-only\fR" 4 +.IX Item "-m4-single-only" +Generate code for the \s-1SH4\s0 with a floating-point unit that only +supports single-precision arithmetic. +.IP "\fB\-m4\-single\fR" 4 +.IX Item "-m4-single" +Generate code for the \s-1SH4\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\fR" 4 +.IX Item "-m4" +Generate code for the \s-1SH4.\s0 +.IP "\fB\-m4\-100\fR" 4 +.IX Item "-m4-100" +Generate code for \s-1SH4\-100.\s0 +.IP "\fB\-m4\-100\-nofpu\fR" 4 +.IX Item "-m4-100-nofpu" +Generate code for \s-1SH4\-100\s0 in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-100\-single\fR" 4 +.IX Item "-m4-100-single" +Generate code for \s-1SH4\-100\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\-100\-single\-only\fR" 4 +.IX Item "-m4-100-single-only" +Generate code for \s-1SH4\-100\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-200\fR" 4 +.IX Item "-m4-200" +Generate code for \s-1SH4\-200.\s0 +.IP "\fB\-m4\-200\-nofpu\fR" 4 +.IX Item "-m4-200-nofpu" +Generate code for \s-1SH4\-200\s0 without in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-200\-single\fR" 4 +.IX Item "-m4-200-single" +Generate code for \s-1SH4\-200\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\-200\-single\-only\fR" 4 +.IX Item "-m4-200-single-only" +Generate code for \s-1SH4\-200\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-300\fR" 4 +.IX Item "-m4-300" +Generate code for \s-1SH4\-300.\s0 +.IP "\fB\-m4\-300\-nofpu\fR" 4 +.IX Item "-m4-300-nofpu" +Generate code for \s-1SH4\-300\s0 without in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-300\-single\fR" 4 +.IX Item "-m4-300-single" +Generate code for \s-1SH4\-300\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-300\-single\-only\fR" 4 +.IX Item "-m4-300-single-only" +Generate code for \s-1SH4\-300\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-340\fR" 4 +.IX Item "-m4-340" +Generate code for \s-1SH4\-340\s0 (no \s-1MMU,\s0 no \s-1FPU\s0). +.IP "\fB\-m4\-500\fR" 4 +.IX Item "-m4-500" +Generate code for \s-1SH4\-500\s0 (no \s-1FPU\s0). Passes \fB\-isa=sh4\-nofpu\fR to the +assembler. +.IP "\fB\-m4a\-nofpu\fR" 4 +.IX Item "-m4a-nofpu" +Generate code for the SH4al\-dsp, or for a SH4a in such a way that the +floating-point unit is not used. +.IP "\fB\-m4a\-single\-only\fR" 4 +.IX Item "-m4a-single-only" +Generate code for the SH4a, in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4a\-single\fR" 4 +.IX Item "-m4a-single" +Generate code for the SH4a assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4a\fR" 4 +.IX Item "-m4a" +Generate code for the SH4a. +.IP "\fB\-m4al\fR" 4 +.IX Item "-m4al" +Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes +\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 +instructions at the moment. +.IP "\fB\-mb\fR" 4 +.IX Item "-mb" +Compile code for the processor in big-endian mode. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Compile code for the processor in little-endian mode. +.IP "\fB\-mdalign\fR" 4 +.IX Item "-mdalign" +Align doubles at 64\-bit boundaries. Note that this changes the calling +conventions, and thus some functions from the standard C library do +not work unless you recompile it first with \fB\-mdalign\fR. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mbigtable\fR" 4 +.IX Item "-mbigtable" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enable the use of bit manipulation instructions on \s-1SH2A.\s0 +.IP "\fB\-mfmovd\fR" 4 +.IX Item "-mfmovd" +Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for +alignment constraints. +.IP "\fB\-mrenesas\fR" 4 +.IX Item "-mrenesas" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mno\-renesas\fR" 4 +.IX Item "-mno-renesas" +Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas +conventions were available. This option is the default for all +targets of the \s-1SH\s0 toolchain. +.IP "\fB\-mnomacsave\fR" 4 +.IX Item "-mnomacsave" +Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if +\&\fB\-mrenesas\fR is given. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +.PD 0 +.IP "\fB\-mno\-ieee\fR" 4 +.IX Item "-mno-ieee" +.PD +Control the \s-1IEEE\s0 compliance of floating-point comparisons, which affects the +handling of cases where the result of a comparison is unordered. By default +\&\fB\-mieee\fR is implicitly enabled. If \fB\-ffinite\-math\-only\fR is +enabled \fB\-mno\-ieee\fR is implicitly set, which results in faster +floating-point greater-equal and less-equal comparisons. The implicit settings +can be overridden by specifying either \fB\-mieee\fR or \fB\-mno\-ieee\fR. +.IP "\fB\-minline\-ic_invalidate\fR" 4 +.IX Item "-minline-ic_invalidate" +Inline code to invalidate instruction cache entries after setting up +nested function trampolines. +This option has no effect if \fB\-musermode\fR is in effect and the selected +code generation option (e.g. \fB\-m4\fR) does not allow the use of the \f(CW\*(C`icbi\*(C'\fR +instruction. +If the selected code generation option does not allow the use of the \f(CW\*(C`icbi\*(C'\fR +instruction, and \fB\-musermode\fR is not in effect, the inlined code +manipulates the instruction cache address array directly with an associative +write. This not only requires privileged mode at run time, but it also +fails if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Dump instruction size and location in the assembly code. +.IP "\fB\-mpadstruct\fR" 4 +.IX Item "-mpadstruct" +This option is deprecated. It pads structures to multiple of 4 bytes, +which is incompatible with the \s-1SH ABI.\s0 +.IP "\fB\-matomic\-model=\fR\fImodel\fR" 4 +.IX Item "-matomic-model=model" +Sets the model of atomic operations and additional parameters as a comma +separated list. For details on the atomic built-in functions see +\&\fB_\|_atomic Builtins\fR. The following models and parameters are supported: +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable compiler generated atomic sequences and emit library calls for atomic +operations. This is the default if the target is not \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. +.IP "\fBsoft-gusa\fR" 4 +.IX Item "soft-gusa" +Generate GNU/Linux compatible gUSA software atomic sequences for the atomic +built-in functions. The generated atomic sequences require additional support +from the interrupt/exception handling code of the system and are only suitable +for SH3* and SH4* single-core systems. This option is enabled by default when +the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A,\s0 +this option also partially utilizes the hardware atomic instructions +\&\f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR to create more efficient code, unless +\&\fBstrict\fR is specified. +.IP "\fBsoft-tcb\fR" 4 +.IX Item "soft-tcb" +Generate software atomic sequences that use a variable in the thread control +block. This is a variation of the gUSA sequences which can also be used on +SH1* and SH2* targets. The generated atomic sequences require additional +support from the interrupt/exception handling code of the system and are only +suitable for single-core systems. When using this model, the \fBgbr\-offset=\fR +parameter has to be specified as well. +.IP "\fBsoft-imask\fR" 4 +.IX Item "soft-imask" +Generate software atomic sequences that temporarily disable interrupts by +setting \f(CW\*(C`SR.IMASK = 1111\*(C'\fR. This model works only when the program runs +in privileged mode and is only suitable for single-core systems. Additional +support from the interrupt/exception handling code of the system is not +required. This model is enabled by default when the target is +\&\f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH1* or SH2*. +.IP "\fBhard-llcs\fR" 4 +.IX Item "hard-llcs" +Generate hardware atomic sequences using the \f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR +instructions only. This is only available on \s-1SH4A\s0 and is suitable for +multi-core systems. Since the hardware instructions support only 32 bit atomic +variables access to 8 or 16 bit variables is emulated with 32 bit accesses. +Code compiled with this option is also compatible with other software +atomic model interrupt/exception handling systems if executed on an \s-1SH4A\s0 +system. Additional support from the interrupt/exception handling code of the +system is not required for this model. +.IP "\fBgbr\-offset=\fR" 4 +.IX Item "gbr-offset=" +This parameter specifies the offset in bytes of the variable in the thread +control block structure that should be used by the generated atomic sequences +when the \fBsoft-tcb\fR model has been selected. For other models this +parameter is ignored. The specified value must be an integer multiple of four +and in the range 0\-1020. +.IP "\fBstrict\fR" 4 +.IX Item "strict" +This parameter prevents mixed usage of multiple atomic models, even if they +are compatible, and makes the compiler generate atomic sequences of the +specified model only. +.RE +.RS 4 +.RE +.IP "\fB\-mtas\fR" 4 +.IX Item "-mtas" +Generate the \f(CW\*(C`tas.b\*(C'\fR opcode for \f(CW\*(C`_\|_atomic_test_and_set\*(C'\fR. +Notice that depending on the particular hardware and software configuration +this can degrade overall performance due to the operand cache line flushes +that are implied by the \f(CW\*(C`tas.b\*(C'\fR instruction. On multi-core \s-1SH4A\s0 +processors the \f(CW\*(C`tas.b\*(C'\fR instruction must be used with caution since it +can result in data corruption for certain cache configurations. +.IP "\fB\-mprefergot\fR" 4 +.IX Item "-mprefergot" +When generating position-independent code, emit function calls using +the Global Offset Table instead of the Procedure Linkage Table. +.IP "\fB\-musermode\fR" 4 +.IX Item "-musermode" +.PD 0 +.IP "\fB\-mno\-usermode\fR" 4 +.IX Item "-mno-usermode" +.PD +Don't allow (allow) the compiler generating privileged mode code. Specifying +\&\fB\-musermode\fR also implies \fB\-mno\-inline\-ic_invalidate\fR if the +inlined code would not work in user mode. \fB\-musermode\fR is the default +when the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. If the target is SH1* or SH2* +\&\fB\-musermode\fR has no effect, since there is no user mode. +.IP "\fB\-multcost=\fR\fInumber\fR" 4 +.IX Item "-multcost=number" +Set the cost to assume for a multiply insn. +.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 +.IX Item "-mdiv=strategy" +Set the division strategy to be used for integer division operations. +\&\fIstrategy\fR can be one of: +.RS 4 +.IP "\fBcall\-div1\fR" 4 +.IX Item "call-div1" +Calls a library function that uses the single-step division instruction +\&\f(CW\*(C`div1\*(C'\fR to perform the operation. Division by zero calculates an +unspecified result and does not trap. This is the default except for \s-1SH4, +SH2A\s0 and SHcompact. +.IP "\fBcall-fp\fR" 4 +.IX Item "call-fp" +Calls a library function that performs the operation in double precision +floating point. Division by zero causes a floating-point exception. This is +the default for SHcompact with \s-1FPU.\s0 Specifying this for targets that do not +have a double precision \s-1FPU\s0 defaults to \f(CW\*(C`call\-div1\*(C'\fR. +.IP "\fBcall-table\fR" 4 +.IX Item "call-table" +Calls a library function that uses a lookup table for small divisors and +the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division +by zero calculates an unspecified result and does not trap. This is the default +for \s-1SH4.\s0 Specifying this for targets that do not have dynamic shift +instructions defaults to \f(CW\*(C`call\-div1\*(C'\fR. +.RE +.RS 4 +.Sp +When a division strategy has not been specified the default strategy is +selected based on the current target. For \s-1SH2A\s0 the default strategy is to +use the \f(CW\*(C`divs\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions instead of library function +calls. +.RE +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +Reserve space once for outgoing arguments in the function prologue rather +than around each call. Generally beneficial for performance and size. Also +needed for unwinding to avoid changing the stack frame around conditional code. +.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 +.IX Item "-mdivsi3_libfunc=name" +Set the name of the library function used for 32\-bit signed division to +\&\fIname\fR. +This only affects the name used in the \fBcall\fR division strategies, and +the compiler still expects the same sets of input/output/clobbered registers as +if this option were not present. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 +.IX Item "-mbranch-cost=num" +Assume \fInum\fR to be the cost for a branch instruction. Higher numbers +make the compiler try to generate more branch-free code if possible. +If not specified the value is selected depending on the processor type that +is being compiled for. +.IP "\fB\-mzdcbranch\fR" 4 +.IX Item "-mzdcbranch" +.PD 0 +.IP "\fB\-mno\-zdcbranch\fR" 4 +.IX Item "-mno-zdcbranch" +.PD +Assume (do not assume) that zero displacement conditional branch instructions +\&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the +compiler prefers zero displacement branch code sequences. This is +enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A.\s0 It can be explicitly +disabled by specifying \fB\-mno\-zdcbranch\fR. +.IP "\fB\-mcbranch\-force\-delay\-slot\fR" 4 +.IX Item "-mcbranch-force-delay-slot" +Force the usage of delay slots for conditional branches, which stuffs the delay +slot with a \f(CW\*(C`nop\*(C'\fR if a suitable instruction cannot be found. By default +this option is disabled. It can be enabled to work around hardware bugs as +found in the original \s-1SH7055.\s0 +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine-dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mfsca\fR" 4 +.IX Item "-mfsca" +.PD 0 +.IP "\fB\-mno\-fsca\fR" 4 +.IX Item "-mno-fsca" +.PD +Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine +and cosine approximations. The option \fB\-mfsca\fR must be used in +combination with \fB\-funsafe\-math\-optimizations\fR. It is enabled by default +when generating code for \s-1SH4A.\s0 Using \fB\-mno\-fsca\fR disables sine and cosine +approximations even if \fB\-funsafe\-math\-optimizations\fR is in effect. +.IP "\fB\-mfsrra\fR" 4 +.IX Item "-mfsrra" +.PD 0 +.IP "\fB\-mno\-fsrra\fR" 4 +.IX Item "-mno-fsrra" +.PD +Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction for +reciprocal square root approximations. The option \fB\-mfsrra\fR must be used +in combination with \fB\-funsafe\-math\-optimizations\fR and +\&\fB\-ffinite\-math\-only\fR. It is enabled by default when generating code for +\&\s-1SH4A.\s0 Using \fB\-mno\-fsrra\fR disables reciprocal square root approximations +even if \fB\-funsafe\-math\-optimizations\fR and \fB\-ffinite\-math\-only\fR are +in effect. +.IP "\fB\-mpretend\-cmove\fR" 4 +.IX Item "-mpretend-cmove" +Prefer zero-displacement conditional branches for conditional move instruction +patterns. This can result in faster code on the \s-1SH4\s0 processor. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Generate code using the \s-1FDPIC ABI.\s0 +.PP +\fISolaris 2 Options\fR +.IX Subsection "Solaris 2 Options" +.PP +These \fB\-m\fR options are supported on Solaris 2: +.IP "\fB\-mclear\-hwcap\fR" 4 +.IX Item "-mclear-hwcap" +\&\fB\-mclear\-hwcap\fR tells the compiler to remove the hardware +capabilities generated by the Solaris assembler. This is only necessary +when object files use \s-1ISA\s0 extensions not supported by the current +machine, but check at runtime whether or not to use them. +.IP "\fB\-mimpure\-text\fR" 4 +.IX Item "-mimpure-text" +\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells +the compiler to not pass \fB\-z text\fR to the linker when linking a +shared object. Using this option, you can link position-dependent +code into a shared object. +.Sp +\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against +allocatable but non-writable sections\*(R" linker error message. +However, the necessary relocations trigger copy-on-write, and the +shared object is not actually shared across processes. Instead of +using \fB\-mimpure\-text\fR, you should compile all source code with +\&\fB\-fpic\fR or \fB\-fPIC\fR. +.PP +These switches are supported in addition to the above on Solaris 2: +.IP "\fB\-pthreads\fR" 4 +.IX Item "-pthreads" +This is a synonym for \fB\-pthread\fR. +.PP +\fI\s-1SPARC\s0 Options\fR +.IX Subsection "SPARC Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPARC:\s0 +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +.PD 0 +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +.PD +Specify \fB\-mapp\-regs\fR to generate output using the global registers +2 through 4, which the \s-1SPARC SVR4 ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. +.Sp +To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, +specify \fB\-mno\-app\-regs\fR. You should compile libraries and system +software with this option. +.IP "\fB\-mflat\fR" 4 +.IX Item "-mflat" +.PD 0 +.IP "\fB\-mno\-flat\fR" 4 +.IX Item "-mno-flat" +.PD +With \fB\-mflat\fR, the compiler does not generate save/restore instructions +and uses a \*(L"flat\*(R" or single register window model. This model is compatible +with the regular register window model. The local registers and the input +registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and are +saved on the stack as needed. +.Sp +With \fB\-mno\-flat\fR (the default), the compiler generates save/restore +instructions (except for leaf functions). This is the normal operating mode. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing floating-point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and +\&\fBsparclite\-*\-*\fR do provide software floating-point support. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mhard\-quad\-float\fR" 4 +.IX Item "-mhard-quad-float" +Generate output containing quad-word (long double) floating-point +instructions. +.IP "\fB\-msoft\-quad\-float\fR" 4 +.IX Item "-msoft-quad-float" +Generate output containing library calls for quad-word (long double) +floating-point instructions. The functions called are those specified +in the \s-1SPARC ABI.\s0 This is the default. +.Sp +As of this writing, there are no \s-1SPARC\s0 implementations that have hardware +support for the quad-word floating-point instructions. They all invoke +a trap handler for one of these instructions, and then the trap handler +emulates the effect of the instruction. Because of the trap handler overhead, +this is much slower than calling the \s-1ABI\s0 library routines. Thus the +\&\fB\-msoft\-quad\-float\fR option is the default. +.IP "\fB\-mno\-unaligned\-doubles\fR" 4 +.IX Item "-mno-unaligned-doubles" +.PD 0 +.IP "\fB\-munaligned\-doubles\fR" 4 +.IX Item "-munaligned-doubles" +.PD +Assume that doubles have 8\-byte alignment. This is the default. +.Sp +With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8\-byte +alignment only if they are contained in another type, or if they have an +absolute address. Otherwise, it assumes they have 4\-byte alignment. +Specifying this option avoids some rare compatibility problems with code +generated by other compilers. It is not the default because it results +in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. This +is the default. +.IP "\fB\-mfaster\-structs\fR" 4 +.IX Item "-mfaster-structs" +.PD 0 +.IP "\fB\-mno\-faster\-structs\fR" 4 +.IX Item "-mno-faster-structs" +.PD +With \fB\-mfaster\-structs\fR, the compiler assumes that structures +should have 8\-byte alignment. This enables the use of pairs of +\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure +assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. +However, the use of this changed alignment directly violates the \s-1SPARC +ABI.\s0 Thus, it's intended only for use on targets where the developer +acknowledges that their resulting code is not directly in line with +the rules of the \s-1ABI.\s0 +.IP "\fB\-mstd\-struct\-return\fR" 4 +.IX Item "-mstd-struct-return" +.PD 0 +.IP "\fB\-mno\-std\-struct\-return\fR" 4 +.IX Item "-mno-std-struct-return" +.PD +With \fB\-mstd\-struct\-return\fR, the compiler generates checking code +in functions returning structures or unions to detect size mismatches +between the two sides of function calls, as per the 32\-bit \s-1ABI.\s0 +.Sp +The default is \fB\-mno\-std\-struct\-return\fR. This option has no effect +in 64\-bit mode. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +.PD 0 +.IP "\fB\-mno\-lra\fR" 4 +.IX Item "-mno-lra" +.PD +Enable Local Register Allocation. This is the default for \s-1SPARC\s0 since \s-1GCC 7\s0 +so \fB\-mno\-lra\fR needs to be passed to get old Reload. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, +\&\fBleon\fR, \fBleon3\fR, \fBleon3v7\fR, \fBsparclite\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR, \fBniagara4\fR, \fBniagara7\fR and \fBm8\fR. +.Sp +Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +Default instruction scheduling parameters are used for values that select +an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, +\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. +.Sp +Here is a list of each supported architecture and their supported +implementations. +.RS 4 +.IP "v7" 4 +.IX Item "v7" +cypress, leon3v7 +.IP "v8" 4 +.IX Item "v8" +supersparc, hypersparc, leon, leon3 +.IP "sparclite" 4 +.IX Item "sparclite" +f930, f934, sparclite86x +.IP "sparclet" 4 +.IX Item "sparclet" +tsc701 +.IP "v9" 4 +.IX Item "v9" +ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, +niagara7, m8 +.RE +.RS 4 +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 +variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler +additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the +SPARCStation/SPARCServer 3xx series. This is also appropriate for the older +SPARCStation 1, 2, \s-1IPX\s0 etc. +.Sp +With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 +architecture. The only difference from V7 code is that the compiler emits +the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 +but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=supersparc\fR, the compiler additionally +optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and +2000 series. +.Sp +With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step +and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7.\s0 +With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU.\s0 With +\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu +\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU.\s0 +.Sp +With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, +integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet +but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=tsc701\fR, the compiler additionally +optimizes it for the \s-1TEMIC\s0 SPARClet chip. +.Sp +With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 +architecture. This adds 64\-bit integer and floating-point move instructions, +3 additional floating-point condition code registers and conditional move +instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally +optimizes it for the Sun UltraSPARC I/II/IIi chips. With +\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the +Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With +\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for +Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler +additionally optimizes it for Sun UltraSPARC T2 chips. With +\&\fB\-mcpu=niagara3\fR, the compiler additionally optimizes it for Sun +UltraSPARC T3 chips. With \fB\-mcpu=niagara4\fR, the compiler +additionally optimizes it for Sun UltraSPARC T4 chips. With +\&\fB\-mcpu=niagara7\fR, the compiler additionally optimizes it for +Oracle \s-1SPARC M7\s0 chips. With \fB\-mcpu=m8\fR, the compiler +additionally optimizes it for Oracle M8 chips. +.RE +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the instruction set or register set that the +option \fB\-mcpu=\fR\fIcpu_type\fR does. +.Sp +The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for +\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those +that select a particular \s-1CPU\s0 implementation. Those are +\&\fBcypress\fR, \fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, +\&\fBleon3\fR, \fBleon3v7\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, +\&\fBniagara4\fR, \fBniagara7\fR and \fBm8\fR. With native Solaris +and GNU/Linux toolchains, \fBnative\fR can also be used. +.IP "\fB\-mv8plus\fR" 4 +.IX Item "-mv8plus" +.PD 0 +.IP "\fB\-mno\-v8plus\fR" 4 +.IX Item "-mno-v8plus" +.PD +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+ ABI.\s0 The +difference from the V8 \s-1ABI\s0 is that the global and out registers are +considered 64 bits wide. This is enabled by default on Solaris in 32\-bit +mode for all \s-1SPARC\-V9\s0 processors. +.IP "\fB\-mvis\fR" 4 +.IX Item "-mvis" +.PD 0 +.IP "\fB\-mno\-vis\fR" 4 +.IX Item "-mno-vis" +.PD +With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. +.IP "\fB\-mvis2\fR" 4 +.IX Item "-mvis2" +.PD 0 +.IP "\fB\-mno\-vis2\fR" 4 +.IX Item "-mno-vis2" +.PD +With \fB\-mvis2\fR, \s-1GCC\s0 generates code that takes advantage of +version 2.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis2\fR when targeting a cpu that supports such +instructions, such as UltraSPARC-III and later. Setting \fB\-mvis2\fR +also sets \fB\-mvis\fR. +.IP "\fB\-mvis3\fR" 4 +.IX Item "-mvis3" +.PD 0 +.IP "\fB\-mno\-vis3\fR" 4 +.IX Item "-mno-vis3" +.PD +With \fB\-mvis3\fR, \s-1GCC\s0 generates code that takes advantage of +version 3.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis3\fR when targeting a cpu that supports such +instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR +also sets \fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mvis4\fR" 4 +.IX Item "-mvis4" +.PD 0 +.IP "\fB\-mno\-vis4\fR" 4 +.IX Item "-mno-vis4" +.PD +With \fB\-mvis4\fR, \s-1GCC\s0 generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis4\fR when targeting a cpu that supports such +instructions, such as niagara\-7 and later. Setting \fB\-mvis4\fR +also sets \fB\-mvis3\fR, \fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mvis4b\fR" 4 +.IX Item "-mvis4b" +.PD 0 +.IP "\fB\-mno\-vis4b\fR" 4 +.IX Item "-mno-vis4b" +.PD +With \fB\-mvis4b\fR, \s-1GCC\s0 generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus +the additional \s-1VIS\s0 instructions introduced in the Oracle \s-1SPARC\s0 +Architecture 2017. The default is \fB\-mvis4b\fR when targeting a +cpu that supports such instructions, such as m8 and later. Setting +\&\fB\-mvis4b\fR also sets \fB\-mvis4\fR, \fB\-mvis3\fR, +\&\fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mcbcond\fR" 4 +.IX Item "-mcbcond" +.PD 0 +.IP "\fB\-mno\-cbcond\fR" 4 +.IX Item "-mno-cbcond" +.PD +With \fB\-mcbcond\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Compare-and-Branch-on-Condition instructions. The default is \fB\-mcbcond\fR +when targeting a \s-1CPU\s0 that supports such instructions, such as Niagara\-4 and +later. +.IP "\fB\-mfmaf\fR" 4 +.IX Item "-mfmaf" +.PD 0 +.IP "\fB\-mno\-fmaf\fR" 4 +.IX Item "-mno-fmaf" +.PD +With \fB\-mfmaf\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Fused Multiply-Add Floating-point instructions. The default is \fB\-mfmaf\fR +when targeting a \s-1CPU\s0 that supports such instructions, such as Niagara\-3 and +later. +.IP "\fB\-mfsmuld\fR" 4 +.IX Item "-mfsmuld" +.PD 0 +.IP "\fB\-mno\-fsmuld\fR" 4 +.IX Item "-mno-fsmuld" +.PD +With \fB\-mfsmuld\fR, \s-1GCC\s0 generates code that takes advantage of the +Floating-point Multiply Single to Double (FsMULd) instruction. The default is +\&\fB\-mfsmuld\fR when targeting a \s-1CPU\s0 supporting the architecture versions V8 +or V9 with \s-1FPU\s0 except \fB\-mcpu=leon\fR. +.IP "\fB\-mpopc\fR" 4 +.IX Item "-mpopc" +.PD 0 +.IP "\fB\-mno\-popc\fR" 4 +.IX Item "-mno-popc" +.PD +With \fB\-mpopc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Population Count instruction. The default is \fB\-mpopc\fR +when targeting a \s-1CPU\s0 that supports such an instruction, such as Niagara\-2 and +later. +.IP "\fB\-msubxc\fR" 4 +.IX Item "-msubxc" +.PD 0 +.IP "\fB\-mno\-subxc\fR" 4 +.IX Item "-mno-subxc" +.PD +With \fB\-msubxc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Subtract-Extended-with-Carry instruction. The default is \fB\-msubxc\fR +when targeting a \s-1CPU\s0 that supports such an instruction, such as Niagara\-7 and +later. +.IP "\fB\-mfix\-at697f\fR" 4 +.IX Item "-mfix-at697f" +Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 +processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. +.IP "\fB\-mfix\-ut700\fR" 4 +.IX Item "-mfix-ut700" +Enable the documented workaround for the back-to-back store errata of +the \s-1UT699E/UT700\s0 processor. +.IP "\fB\-mfix\-gr712rc\fR" 4 +.IX Item "-mfix-gr712rc" +Enable the documented workaround for the back-to-back store errata of +the \s-1GR712RC\s0 processor. +.PP +These \fB\-m\fR options are supported in addition to the above +on \s-1SPARC\-V9\s0 processors in 64\-bit environments: +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. +.IP "\fB\-mcmodel=\fR\fIwhich\fR" 4 +.IX Item "-mcmodel=which" +Set the code model to one of +.RS 4 +.IP "\fBmedlow\fR" 4 +.IX Item "medlow" +The Medium/Low code model: 64\-bit addresses, programs +must be linked in the low 32 bits of memory. Programs can be statically +or dynamically linked. +.IP "\fBmedmid\fR" 4 +.IX Item "medmid" +The Medium/Middle code model: 64\-bit addresses, programs +must be linked in the low 44 bits of memory, the text and data segments must +be less than 2GB in size and the data segment must be located within 2GB of +the text segment. +.IP "\fBmedany\fR" 4 +.IX Item "medany" +The Medium/Anywhere code model: 64\-bit addresses, programs +may be linked anywhere in memory, the text and data segments must be less +than 2GB in size and the data segment must be located within 2GB of the +text segment. +.IP "\fBembmedany\fR" 4 +.IX Item "embmedany" +The Medium/Anywhere code model for embedded systems: +64\-bit addresses, the text and data segments must be less than 2GB in +size, both starting anywhere in memory (determined at link time). The +global register \f(CW%g4\fR points to the base of the data segment. Programs +are statically linked and \s-1PIC\s0 is not supported. +.RE +.RS 4 +.RE +.IP "\fB\-mmemory\-model=\fR\fImem-model\fR" 4 +.IX Item "-mmemory-model=mem-model" +Set the memory model in force on the processor to one of +.RS 4 +.IP "\fBdefault\fR" 4 +.IX Item "default" +The default memory model for the processor and operating system. +.IP "\fBrmo\fR" 4 +.IX Item "rmo" +Relaxed Memory Order +.IP "\fBpso\fR" 4 +.IX Item "pso" +Partial Store Order +.IP "\fBtso\fR" 4 +.IX Item "tso" +Total Store Order +.IP "\fBsc\fR" 4 +.IX Item "sc" +Sequential Consistency +.RE +.RS 4 +.Sp +These memory models are formally defined in Appendix D of the \s-1SPARC\-V9\s0 +architecture manual, as set in the processor's \f(CW\*(C`PSTATE.MM\*(C'\fR field. +.RE +.IP "\fB\-mstack\-bias\fR" 4 +.IX Item "-mstack-bias" +.PD 0 +.IP "\fB\-mno\-stack\-bias\fR" 4 +.IX Item "-mno-stack-bias" +.PD +With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and +frame pointer if present, are offset by \-2047 which must be added back +when making stack frame references. This is the default in 64\-bit mode. +Otherwise, assume no such offset is present. +.PP +\fI\s-1SPU\s0 Options\fR +.IX Subsection "SPU Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPU:\s0 +.IP "\fB\-mwarn\-reloc\fR" 4 +.IX Item "-mwarn-reloc" +.PD 0 +.IP "\fB\-merror\-reloc\fR" 4 +.IX Item "-merror-reloc" +.PD +The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 +gives an error when it generates code that requires a dynamic +relocation. \fB\-mno\-error\-reloc\fR disables the error, +\&\fB\-mwarn\-reloc\fR generates a warning instead. +.IP "\fB\-msafe\-dma\fR" 4 +.IX Item "-msafe-dma" +.PD 0 +.IP "\fB\-munsafe\-dma\fR" 4 +.IX Item "-munsafe-dma" +.PD +Instructions that initiate or test completion of \s-1DMA\s0 must not be +reordered with respect to loads and stores of the memory that is being +accessed. +With \fB\-munsafe\-dma\fR you must use the \f(CW\*(C`volatile\*(C'\fR keyword to protect +memory accesses, but that can lead to inefficient code in places where the +memory is known to not change. Rather than mark the memory as volatile, +you can use \fB\-msafe\-dma\fR to tell the compiler to treat +the \s-1DMA\s0 instructions as potentially affecting all memory. +.IP "\fB\-mbranch\-hints\fR" 4 +.IX Item "-mbranch-hints" +By default, \s-1GCC\s0 generates a branch hint instruction to avoid +pipeline stalls for always-taken or probably-taken branches. A hint +is not generated closer than 8 instructions away from its branch. +There is little reason to disable them, except for debugging purposes, +or to make an object a little bit smaller. +.IP "\fB\-msmall\-mem\fR" 4 +.IX Item "-msmall-mem" +.PD 0 +.IP "\fB\-mlarge\-mem\fR" 4 +.IX Item "-mlarge-mem" +.PD +By default, \s-1GCC\s0 generates code assuming that addresses are never larger +than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes +a full 32\-bit address. +.IP "\fB\-mstdmain\fR" 4 +.IX Item "-mstdmain" +By default, \s-1GCC\s0 links against startup code that assumes the SPU-style +main function interface (which has an unconventional parameter list). +With \fB\-mstdmain\fR, \s-1GCC\s0 links your program against startup +code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a +local copy of \f(CW\*(C`argv\*(C'\fR strings. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mea32\fR" 4 +.IX Item "-mea32" +.PD 0 +.IP "\fB\-mea64\fR" 4 +.IX Item "-mea64" +.PD +Compile code assuming that pointers to the \s-1PPU\s0 address space accessed +via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 +bits wide. The default is 32 bits. As this is an ABI-changing option, +all object code in an executable must be compiled with the same setting. +.IP "\fB\-maddress\-space\-conversion\fR" 4 +.IX Item "-maddress-space-conversion" +.PD 0 +.IP "\fB\-mno\-address\-space\-conversion\fR" 4 +.IX Item "-mno-address-space-conversion" +.PD +Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset +of the generic address space. This enables explicit type casts +between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit +conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The +default is to allow address space pointer conversions. +.IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 +.IX Item "-mcache-size=cache-size" +This option controls the version of libgcc that the compiler links to an +executable and selects a software-managed cache for accessing variables +in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible +options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR +and \fB128\fR. The default cache size is 64KB. +.IP "\fB\-matomic\-updates\fR" 4 +.IX Item "-matomic-updates" +.PD 0 +.IP "\fB\-mno\-atomic\-updates\fR" 4 +.IX Item "-mno-atomic-updates" +.PD +This option controls the version of libgcc that the compiler links to an +executable and selects whether atomic updates to the software-managed +cache of PPU-side variables are used. If you use atomic updates, changes +to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space +qualifier do not interfere with changes to other \s-1PPU\s0 variables residing +in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, +such interference may occur; however, writing back cache lines is +more efficient. The default behavior is to use atomic updates. +.IP "\fB\-mdual\-nops\fR" 4 +.IX Item "-mdual-nops" +.PD 0 +.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 +.IX Item "-mdual-nops=n" +.PD +By default, \s-1GCC\s0 inserts NOPs to increase dual issue when it expects +it to increase performance. \fIn\fR can be a value from 0 to 10. A +smaller \fIn\fR inserts fewer NOPs. 10 is the default, 0 is the +same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. +.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 +.IX Item "-mhint-max-nops=n" +Maximum number of NOPs to insert for a branch hint. A branch hint must +be at least 8 instructions away from the branch it is affecting. \s-1GCC\s0 +inserts up to \fIn\fR NOPs to enforce this, otherwise it does not +generate the branch hint. +.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 +.IX Item "-mhint-max-distance=n" +The encoding of the branch hint instruction limits the hint to be within +256 instructions of the branch it is affecting. By default, \s-1GCC\s0 makes +sure it is within 125. +.IP "\fB\-msafe\-hints\fR" 4 +.IX Item "-msafe-hints" +Work around a hardware bug that causes the \s-1SPU\s0 to stall indefinitely. +By default, \s-1GCC\s0 inserts the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure +this stall won't happen. +.PP +\fIOptions for System V\fR +.IX Subsection "Options for System V" +.PP +These additional options are available on System V Release 4 for +compatibility with other compilers on those systems: +.IP "\fB\-G\fR" 4 +.IX Item "-G" +Create a shared object. +It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. +.IP "\fB\-Qy\fR" 4 +.IX Item "-Qy" +Identify the versions of each tool used by the compiler, in a +\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. +.IP "\fB\-Qn\fR" 4 +.IX Item "-Qn" +Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is +the default). +.IP "\fB\-YP,\fR\fIdirs\fR" 4 +.IX Item "-YP,dirs" +Search the directories \fIdirs\fR, and no others, for libraries +specified with \fB\-l\fR. +.IP "\fB\-Ym,\fR\fIdir\fR" 4 +.IX Item "-Ym,dir" +Look in the directory \fIdir\fR to find the M4 preprocessor. +The assembler uses this option. +.PP +\fITILE-Gx Options\fR +.IX Subsection "TILE-Gx Options" +.PP +These \fB\-m\fR options are supported on the TILE-Gx: +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small model. The distance for direct calls is +limited to 500M in either direction. PC-relative addresses are 32 +bits. Absolute addresses support the full address range. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model. There is no limitation on call +distance, pc-relative addresses, or absolute addresses. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported +type is \fBtilegx\fR. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. The 32\-bit +environment sets int, long, and pointer to 32 bits. The 64\-bit +environment sets int to 32 bits and long and pointer to 64 bits. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +Generate code in big/little endian mode, respectively. +.PP +\fITILEPro Options\fR +.IX Subsection "TILEPro Options" +.PP +These \fB\-m\fR options are supported on the TILEPro: +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported +type is \fBtilepro\fR. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +Generate code for a 32\-bit environment, which sets int, long, and +pointer to 32 bits. This is the only supported behavior so the flag +is essentially ignored. +.PP +\fIV850 Options\fR +.IX Subsection "V850 Options" +.PP +These \fB\-m\fR options are defined for V850 implementations: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler always loads the function's address into a +register, and calls indirect through the pointer. +.IP "\fB\-mno\-ep\fR" 4 +.IX Item "-mno-ep" +.PD 0 +.IP "\fB\-mep\fR" 4 +.IX Item "-mep" +.PD +Do not optimize (do optimize) basic blocks that use the same index +pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and +use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR +option is on by default if you optimize. +.IP "\fB\-mno\-prolog\-function\fR" 4 +.IX Item "-mno-prolog-function" +.PD 0 +.IP "\fB\-mprolog\-function\fR" 4 +.IX Item "-mprolog-function" +.PD +Do not use (do use) external functions to save and restore registers +at the prologue and epilogue of a function. The external functions +are slower, but use less code space if more than one function saves +the same number of registers. The \fB\-mprolog\-function\fR option +is on by default if you optimize. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Try to make the code as small as possible. At present, this just turns +on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. +.IP "\fB\-mtda=\fR\fIn\fR" 4 +.IX Item "-mtda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data +area can hold up to 256 bytes in total (128 bytes for byte references). +.IP "\fB\-msda=\fR\fIn\fR" 4 +.IX Item "-msda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data +area can hold up to 64 kilobytes. +.IP "\fB\-mzda=\fR\fIn\fR" 4 +.IX Item "-mzda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the first 32 kilobytes of memory. +.IP "\fB\-mv850\fR" 4 +.IX Item "-mv850" +Specify that the target processor is the V850. +.IP "\fB\-mv850e3v5\fR" 4 +.IX Item "-mv850e3v5" +Specify that the target processor is the V850E3V5. The preprocessor +constant \f(CW\*(C`_\|_v850e3v5_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e2v4\fR" 4 +.IX Item "-mv850e2v4" +Specify that the target processor is the V850E3V5. This is an alias for +the \fB\-mv850e3v5\fR option. +.IP "\fB\-mv850e2v3\fR" 4 +.IX Item "-mv850e2v3" +Specify that the target processor is the V850E2V3. The preprocessor +constant \f(CW\*(C`_\|_v850e2v3_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e2\fR" 4 +.IX Item "-mv850e2" +Specify that the target processor is the V850E2. The preprocessor +constant \f(CW\*(C`_\|_v850e2_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e1\fR" 4 +.IX Item "-mv850e1" +Specify that the target processor is the V850E1. The preprocessor +constants \f(CW\*(C`_\|_v850e1_\|_\*(C'\fR and \f(CW\*(C`_\|_v850e_\|_\*(C'\fR are defined if +this option is used. +.IP "\fB\-mv850es\fR" 4 +.IX Item "-mv850es" +Specify that the target processor is the V850ES. This is an alias for +the \fB\-mv850e1\fR option. +.IP "\fB\-mv850e\fR" 4 +.IX Item "-mv850e" +Specify that the target processor is the V850E. The preprocessor +constant \f(CW\*(C`_\|_v850e_\|_\*(C'\fR is defined if this option is used. +.Sp +If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR +nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR nor \fB\-mv850e3v5\fR +are defined then a default target processor is chosen and the +relevant \fB_\|_v850*_\|_\fR preprocessor constant is defined. +.Sp +The preprocessor constants \f(CW\*(C`_\|_v850\*(C'\fR and \f(CW\*(C`_\|_v851_\|_\*(C'\fR are always +defined, regardless of which processor variant is the target. +.IP "\fB\-mdisable\-callt\fR" 4 +.IX Item "-mdisable-callt" +.PD 0 +.IP "\fB\-mno\-disable\-callt\fR" 4 +.IX Item "-mno-disable-callt" +.PD +This option suppresses generation of the \f(CW\*(C`CALLT\*(C'\fR instruction for the +v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 +architecture. +.Sp +This option is enabled by default when the \s-1RH850 ABI\s0 is +in use (see \fB\-mrh850\-abi\fR), and disabled by default when the +\&\s-1GCC ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated +then the C preprocessor symbol \f(CW\*(C`_\|_V850_CALLT_\|_\*(C'\fR is defined. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +.PD 0 +.IP "\fB\-mno\-relax\fR" 4 +.IX Item "-mno-relax" +.PD +Pass on (or do not pass on) the \fB\-mrelax\fR command-line option +to the assembler. +.IP "\fB\-mlong\-jumps\fR" 4 +.IX Item "-mlong-jumps" +.PD 0 +.IP "\fB\-mno\-long\-jumps\fR" 4 +.IX Item "-mno-long-jumps" +.PD +Disable (or re-enable) the generation of PC-relative jump instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Disable (or re-enable) the generation of hardware floating point +instructions. This option is only significant when the target +architecture is \fBV850E2V3\fR or higher. If hardware floating point +instructions are being generated then the C preprocessor symbol +\&\f(CW\*(C`_\|_FPU_OK_\|_\*(C'\fR is defined, otherwise the symbol +\&\f(CW\*(C`_\|_NO_FPU_\|_\*(C'\fR is defined. +.IP "\fB\-mloop\fR" 4 +.IX Item "-mloop" +Enables the use of the e3v5 \s-1LOOP\s0 instruction. The use of this +instruction is not enabled by default when the e3v5 architecture is +selected because its use is still experimental. +.IP "\fB\-mrh850\-abi\fR" 4 +.IX Item "-mrh850-abi" +.PD 0 +.IP "\fB\-mghs\fR" 4 +.IX Item "-mghs" +.PD +Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI.\s0 This is the +default. With this version of the \s-1ABI\s0 the following rules apply: +.RS 4 +.IP "*" 4 +Integer sized structures and unions are returned via a memory pointer +rather than a register. +.IP "*" 4 +Large structures and unions (more than 8 bytes in size) are passed by +value. +.IP "*" 4 +Functions are aligned to 16\-bit boundaries. +.IP "*" 4 +The \fB\-m8byte\-align\fR command-line option is supported. +.IP "*" 4 +The \fB\-mdisable\-callt\fR command-line option is enabled by +default. The \fB\-mno\-disable\-callt\fR command-line option is not +supported. +.RE +.RS 4 +.Sp +When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_RH850_ABI_\|_\*(C'\fR is defined. +.RE +.IP "\fB\-mgcc\-abi\fR" 4 +.IX Item "-mgcc-abi" +Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI.\s0 With this +version of the \s-1ABI\s0 the following rules apply: +.RS 4 +.IP "*" 4 +Integer sized structures and unions are returned in register \f(CW\*(C`r10\*(C'\fR. +.IP "*" 4 +Large structures and unions (more than 8 bytes in size) are passed by +reference. +.IP "*" 4 +Functions are aligned to 32\-bit boundaries, unless optimizing for +size. +.IP "*" 4 +The \fB\-m8byte\-align\fR command-line option is not supported. +.IP "*" 4 +The \fB\-mdisable\-callt\fR command-line option is supported but not +enabled by default. +.RE +.RS 4 +.Sp +When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_GCC_ABI_\|_\*(C'\fR is defined. +.RE +.IP "\fB\-m8byte\-align\fR" 4 +.IX Item "-m8byte-align" +.PD 0 +.IP "\fB\-mno\-8byte\-align\fR" 4 +.IX Item "-mno-8byte-align" +.PD +Enables support for \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long long\*(C'\fR types to be +aligned on 8\-byte boundaries. The default is to restrict the +alignment of all objects to at most 4\-bytes. When +\&\fB\-m8byte\-align\fR is in effect the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_8BYTE_ALIGN_\|_\*(C'\fR is defined. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +This option causes r2 and r5 to be used in the code generated by +the compiler. This setting is the default. +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +This option causes r2 and r5 to be treated as fixed registers. +.PP +\fI\s-1VAX\s0 Options\fR +.IX Subsection "VAX Options" +.PP +These \fB\-m\fR options are defined for the \s-1VAX:\s0 +.IP "\fB\-munix\fR" 4 +.IX Item "-munix" +Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) +that the Unix assembler for the \s-1VAX\s0 cannot handle across long +ranges. +.IP "\fB\-mgnu\fR" 4 +.IX Item "-mgnu" +Do output those jump instructions, on the assumption that the +\&\s-1GNU\s0 assembler is being used. +.IP "\fB\-mg\fR" 4 +.IX Item "-mg" +Output code for G\-format floating-point numbers instead of D\-format. +.PP +\fIVisium Options\fR +.IX Subsection "Visium Options" +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +A program which performs file I/O and is destined to run on an \s-1MCM\s0 target +should be linked with this option. It causes the libraries libc.a and +libdebug.a to be linked. The program should be run on the target under +the control of the \s-1GDB\s0 remote debugging stub. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +A program which performs file I/O and is destined to run on the simulator +should be linked with option. This causes libraries libc.a and libsim.a to +be linked. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code containing floating-point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate code containing library calls for floating-point. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBmcm\fR, \fBgr5\fR and \fBgr6\fR. +.Sp +\&\fBmcm\fR is a synonym of \fBgr5\fR present for backward compatibility. +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the \s-1GR5\s0 +variant of the Visium architecture. +.Sp +With \fB\-mcpu=gr6\fR, \s-1GCC\s0 generates code for the \s-1GR6\s0 variant of the Visium +architecture. The only difference from \s-1GR5\s0 code is that the compiler will +generate block move instructions. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type \fIcpu_type\fR, +but do not set the instruction set or register set that the option +\&\fB\-mcpu=\fR\fIcpu_type\fR would. +.IP "\fB\-msv\-mode\fR" 4 +.IX Item "-msv-mode" +Generate code for the supervisor mode, where there are no restrictions on +the access to general registers. This is the default. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +Generate code for the user mode, where the access to some general registers +is forbidden: on the \s-1GR5,\s0 registers r24 to r31 cannot be accessed in this +mode; on the \s-1GR6,\s0 only registers r29 to r31 are affected. +.PP +\fI\s-1VMS\s0 Options\fR +.IX Subsection "VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1VMS\s0 implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from \f(CW\*(C`main\*(C'\fR. The default is to return POSIX-style +condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64\-bit memory allocation routines. +.IP "\fB\-mpointer\-size=\fR\fIsize\fR" 4 +.IX Item "-mpointer-size=size" +Set the default size of pointers. Possible options for \fIsize\fR are +\&\fB32\fR or \fBshort\fR for 32 bit pointers, \fB64\fR or \fBlong\fR +for 64 bit pointers, and \fBno\fR for supporting only 32 bit pointers. +The later option disables \f(CW\*(C`pragma pointer_size\*(C'\fR. +.PP +\fIVxWorks Options\fR +.IX Subsection "VxWorks Options" +.PP +The options in this section are defined for all VxWorks targets. +Options specific to the target hardware are listed with the other +options for that target. +.IP "\fB\-mrtp\fR" 4 +.IX Item "-mrtp" +\&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes +(RTPs). This option switches from the former to the latter. It also +defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. +.IP "\fB\-non\-static\fR" 4 +.IX Item "-non-static" +Link an \s-1RTP\s0 executable against shared libraries rather than static +libraries. The options \fB\-static\fR and \fB\-shared\fR can +also be used for RTPs; \fB\-static\fR +is the default. +.IP "\fB\-Bstatic\fR" 4 +.IX Item "-Bstatic" +.PD 0 +.IP "\fB\-Bdynamic\fR" 4 +.IX Item "-Bdynamic" +.PD +These options are passed down to the linker. They are defined for +compatibility with Diab. +.IP "\fB\-Xbind\-lazy\fR" 4 +.IX Item "-Xbind-lazy" +Enable lazy binding of function calls. This option is equivalent to +\&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. +.IP "\fB\-Xbind\-now\fR" 4 +.IX Item "-Xbind-now" +Disable lazy binding of function calls. This option is the default and +is defined for compatibility with Diab. +.PP +\fIx86 Options\fR +.IX Subsection "x86 Options" +.PP +These \fB\-m\fR options are defined for the x86 family of computers. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate instructions for the machine type \fIcpu-type\fR. In contrast to +\&\fB\-mtune=\fR\fIcpu-type\fR, which merely tunes the generated code +for the specified \fIcpu-type\fR, \fB\-march=\fR\fIcpu-type\fR allows \s-1GCC\s0 +to generate code that may not run at all on processors other than the one +indicated. Specifying \fB\-march=\fR\fIcpu-type\fR implies +\&\fB\-mtune=\fR\fIcpu-type\fR. +.Sp +The choices for \fIcpu-type\fR are: +.RS 4 +.IP "\fBnative\fR" 4 +.IX Item "native" +This selects the \s-1CPU\s0 to generate code for at compilation time by determining +the processor type of the compiling machine. Using \fB\-march=native\fR +enables all instruction subsets supported by the local machine (hence +the result might not run on different machines). Using \fB\-mtune=native\fR +produces code optimized for the local machine under the constraints +of the selected instruction set. +.IP "\fBx86\-64\fR" 4 +.IX Item "x86-64" +A generic \s-1CPU\s0 with 64\-bit extensions. +.IP "\fBi386\fR" 4 +.IX Item "i386" +Original Intel i386 \s-1CPU.\s0 +.IP "\fBi486\fR" 4 +.IX Item "i486" +Intel i486 \s-1CPU.\s0 (No scheduling is implemented for this chip.) +.IP "\fBi586\fR" 4 +.IX Item "i586" +.PD 0 +.IP "\fBpentium\fR" 4 +.IX Item "pentium" +.PD +Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. +.IP "\fBlakemont\fR" 4 +.IX Item "lakemont" +Intel Lakemont \s-1MCU,\s0 based on Intel Pentium \s-1CPU.\s0 +.IP "\fBpentium-mmx\fR" 4 +.IX Item "pentium-mmx" +Intel Pentium \s-1MMX CPU,\s0 based on Pentium core with \s-1MMX\s0 instruction set support. +.IP "\fBpentiumpro\fR" 4 +.IX Item "pentiumpro" +Intel Pentium Pro \s-1CPU.\s0 +.IP "\fBi686\fR" 4 +.IX Item "i686" +When used with \fB\-march\fR, the Pentium Pro +instruction set is used, so the code runs on all i686 family chips. +When used with \fB\-mtune\fR, it has the same meaning as \fBgeneric\fR. +.IP "\fBpentium2\fR" 4 +.IX Item "pentium2" +Intel Pentium \s-1II CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 instruction set +support. +.IP "\fBpentium3\fR" 4 +.IX Item "pentium3" +.PD 0 +.IP "\fBpentium3m\fR" 4 +.IX Item "pentium3m" +.PD +Intel Pentium \s-1III CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction +set support. +.IP "\fBpentium-m\fR" 4 +.IX Item "pentium-m" +Intel Pentium M; low-power version of Intel Pentium \s-1III CPU\s0 +with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks. +.IP "\fBpentium4\fR" 4 +.IX Item "pentium4" +.PD 0 +.IP "\fBpentium4m\fR" 4 +.IX Item "pentium4m" +.PD +Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. +.IP "\fBprescott\fR" 4 +.IX Item "prescott" +Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction +set support. +.IP "\fBnocona\fR" 4 +.IX Item "nocona" +Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, +SSE2\s0 and \s-1SSE3\s0 instruction set support. +.IP "\fBcore2\fR" 4 +.IX Item "core2" +Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fBnehalem\fR" 4 +.IX Item "nehalem" +Intel Nehalem \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2\s0 and \s-1POPCNT\s0 instruction set support. +.IP "\fBwestmere\fR" 4 +.IX Item "westmere" +Intel Westmere \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fBsandybridge\fR" 4 +.IX Item "sandybridge" +Intel Sandy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fBivybridge\fR" 4 +.IX Item "ivybridge" +Intel Ivy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND\s0 and F16C +instruction set support. +.IP "\fBhaswell\fR" 4 +.IX Item "haswell" +Intel Haswell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2\s0 and F16C instruction set support. +.IP "\fBbroadwell\fR" 4 +.IX Item "broadwell" +Intel Broadwell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, +F16C, RDSEED ADCX\s0 and \s-1PREFETCHW\s0 instruction set support. +.IP "\fBskylake\fR" 4 +.IX Item "skylake" +Intel Skylake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC\s0 and \s-1XSAVES\s0 +instruction set support. +.IP "\fBbonnell\fR" 4 +.IX Item "bonnell" +Intel Bonnell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fBsilvermont\fR" 4 +.IX Item "silvermont" +Intel Silvermont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL\s0 and \s-1RDRND\s0 instruction set support. +.IP "\fBgoldmont\fR" 4 +.IX Item "goldmont" +Intel Goldmont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, +XSAVEOPT\s0 and \s-1FSGSBASE\s0 instruction set support. +.IP "\fBgoldmont-plus\fR" 4 +.IX Item "goldmont-plus" +Intel Goldmont Plus \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX\s0 and \s-1UMIP\s0 instruction set support. +.IP "\fBtremont\fR" 4 +.IX Item "tremont" +Intel Tremont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, +XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP,\s0 GFNI-SSE, \s-1CLWB, MOVDIRI, +MOVDIR64B, CLDEMOTE\s0 and \s-1WAITPKG\s0 instruction set support. +.IP "\fBknl\fR" 4 +.IX Item "knl" +Intel Knight's Landing \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF, +AVX512ER\s0 and \s-1AVX512CD\s0 instruction set support. +.IP "\fBknm\fR" 4 +.IX Item "knm" +Intel Knights Mill \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF, +AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS\s0 and \s-1AVX512VPOPCNTDQ\s0 instruction +set support. +.IP "\fBskylake\-avx512\fR" 4 +.IX Item "skylake-avx512" +Intel Skylake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, +CLWB, AVX512VL, AVX512BW, AVX512DQ\s0 and \s-1AVX512CD\s0 instruction set support. +.IP "\fBcannonlake\fR" 4 +.IX Item "cannonlake" +Intel Cannonlake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA\s0 and \s-1UMIP\s0 instruction set support. +.IP "\fBicelake-client\fR" 4 +.IX Item "icelake-client" +Intel Icelake Client \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES\s0 instruction set support. +.IP "\fBicelake-server\fR" 4 +.IX Item "icelake-server" +Intel Icelake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG\s0 and \s-1WBNOINVD\s0 instruction +set support. +.IP "\fBcascadelake\fR" 4 +.IX Item "cascadelake" +Intel Cascadelake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB, +AVX512VL, AVX512BW, AVX512DQ, AVX512CD\s0 and \s-1AVX512VNNI\s0 instruction set support. +.IP "\fBtigerlake\fR" 4 +.IX Item "tigerlake" +Intel Tigerlake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, +AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, +RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, +VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B\s0 and \s-1CLWB\s0 instruction set support. +.IP "\fBk6\fR" 4 +.IX Item "k6" +\&\s-1AMD K6 CPU\s0 with \s-1MMX\s0 instruction set support. +.IP "\fBk6\-2\fR" 4 +.IX Item "k6-2" +.PD 0 +.IP "\fBk6\-3\fR" 4 +.IX Item "k6-3" +.PD +Improved versions of \s-1AMD K6 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.IP "\fBathlon\fR" 4 +.IX Item "athlon" +.PD 0 +.IP "\fBathlon-tbird\fR" 4 +.IX Item "athlon-tbird" +.PD +\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions +support. +.IP "\fBathlon\-4\fR" 4 +.IX Item "athlon-4" +.PD 0 +.IP "\fBathlon-xp\fR" 4 +.IX Item "athlon-xp" +.IP "\fBathlon-mp\fR" 4 +.IX Item "athlon-mp" +.PD +Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 +instruction set support. +.IP "\fBk8\fR" 4 +.IX Item "k8" +.PD 0 +.IP "\fBopteron\fR" 4 +.IX Item "opteron" +.IP "\fBathlon64\fR" 4 +.IX Item "athlon64" +.IP "\fBathlon-fx\fR" 4 +.IX Item "athlon-fx" +.PD +Processors based on the \s-1AMD K8\s0 core with x86\-64 instruction set support, +including the \s-1AMD\s0 Opteron, Athlon 64, and Athlon 64 \s-1FX\s0 processors. +(This supersets \s-1MMX, SSE, SSE2,\s0 3DNow!, enhanced 3DNow! and 64\-bit +instruction set extensions.) +.IP "\fBk8\-sse3\fR" 4 +.IX Item "k8-sse3" +.PD 0 +.IP "\fBopteron\-sse3\fR" 4 +.IX Item "opteron-sse3" +.IP "\fBathlon64\-sse3\fR" 4 +.IX Item "athlon64-sse3" +.PD +Improved versions of \s-1AMD K8\s0 cores with \s-1SSE3\s0 instruction set support. +.IP "\fBamdfam10\fR" 4 +.IX Item "amdfam10" +.PD 0 +.IP "\fBbarcelona\fR" 4 +.IX Item "barcelona" +.PD +CPUs based on \s-1AMD\s0 Family 10h cores with x86\-64 instruction set support. (This +supersets \s-1MMX, SSE, SSE2, SSE3, SSE4A,\s0 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbdver1\fR" 4 +.IX Item "bdver1" +CPUs based on \s-1AMD\s0 Family 15h cores with x86\-64 instruction set support. (This +supersets \s-1FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set extensions.) +.IP "\fBbdver2\fR" 4 +.IX Item "bdver2" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, +SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set +extensions.) +.IP "\fBbdver3\fR" 4 +.IX Item "bdver3" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,\s0 +\&\s-1PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and +64\-bit instruction set extensions. +.IP "\fBbdver4\fR" 4 +.IX Item "bdver4" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,\s0 +\&\s-1AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,\s0 +\&\s-1SSE4.2, ABM\s0 and 64\-bit instruction set extensions. +.IP "\fBznver1\fR" 4 +.IX Item "znver1" +\&\s-1AMD\s0 Family 17h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, +SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, +SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT,\s0 and 64\-bit +instruction set extensions. +.IP "\fBznver2\fR" 4 +.IX Item "znver2" +\&\s-1AMD\s0 Family 17h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, +MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT,\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbtver1\fR" 4 +.IX Item "btver1" +CPUs based on \s-1AMD\s0 Family 14h cores with x86\-64 instruction set support. (This +supersets \s-1MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbtver2\fR" 4 +.IX Item "btver2" +CPUs based on \s-1AMD\s0 Family 16h cores with x86\-64 instruction set support. This +includes \s-1MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, +SSE4A, SSSE3, SSE3, SSE2, SSE, MMX\s0 and 64\-bit instruction set extensions. +.IP "\fBwinchip\-c6\fR" 4 +.IX Item "winchip-c6" +\&\s-1IDT\s0 WinChip C6 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 instruction +set support. +.IP "\fBwinchip2\fR" 4 +.IX Item "winchip2" +\&\s-1IDT\s0 WinChip 2 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! +instruction set support. +.IP "\fBc3\fR" 4 +.IX Item "c3" +\&\s-1VIA C3 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBc3\-2\fR" 4 +.IX Item "c3-2" +\&\s-1VIA C3\-2\s0 (Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBc7\fR" 4 +.IX Item "c7" +\&\s-1VIA C7\s0 (Esther) \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBsamuel\-2\fR" 4 +.IX Item "samuel-2" +\&\s-1VIA\s0 Eden Samuel 2 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnehemiah\fR" 4 +.IX Item "nehemiah" +\&\s-1VIA\s0 Eden Nehemiah \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBesther\fR" 4 +.IX Item "esther" +\&\s-1VIA\s0 Eden Esther \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBeden\-x2\fR" 4 +.IX Item "eden-x2" +\&\s-1VIA\s0 Eden X2 \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBeden\-x4\fR" 4 +.IX Item "eden-x4" +\&\s-1VIA\s0 Eden X4 \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, +AVX\s0 and \s-1AVX2\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\fR" 4 +.IX Item "nano" +Generic \s-1VIA\s0 Nano \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-1000\fR" 4 +.IX Item "nano-1000" +\&\s-1VIA\s0 Nano 1xxx \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-2000\fR" 4 +.IX Item "nano-2000" +\&\s-1VIA\s0 Nano 2xxx \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-3000\fR" 4 +.IX Item "nano-3000" +\&\s-1VIA\s0 Nano 3xxx \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3\s0 and \s-1SSE4.1\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-x2\fR" 4 +.IX Item "nano-x2" +\&\s-1VIA\s0 Nano Dual Core \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3\s0 and \s-1SSE4.1\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-x4\fR" 4 +.IX Item "nano-x4" +\&\s-1VIA\s0 Nano Quad Core \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3\s0 and \s-1SSE4.1\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBgeode\fR" 4 +.IX Item "geode" +\&\s-1AMD\s0 Geode embedded processor with \s-1MMX\s0 and 3DNow! instruction set support. +.RE +.RS 4 +.RE +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, except +for the \s-1ABI\s0 and the set of available instructions. +While picking a specific \fIcpu-type\fR schedules things appropriately +for that particular chip, the compiler does not generate any code that +cannot run on the default machine type unless you use a +\&\fB\-march=\fR\fIcpu-type\fR option. +For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu +then \fB\-mtune=pentium4\fR generates code that is tuned for Pentium 4 +but still runs on i686 machines. +.Sp +The choices for \fIcpu-type\fR are the same as for \fB\-march\fR. +In addition, \fB\-mtune\fR supports 2 extra choices for \fIcpu-type\fR: +.RS 4 +.IP "\fBgeneric\fR" 4 +.IX Item "generic" +Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. +If you know the \s-1CPU\s0 on which your code will run, then you should use +the corresponding \fB\-mtune\fR or \fB\-march\fR option instead of +\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users +of your application will have, then you should use this option. +.Sp +As new processors are deployed in the marketplace, the behavior of this +option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +the processors +that are most common at the time that version of \s-1GCC\s0 is released. +.Sp +There is no \fB\-march=generic\fR option because \fB\-march\fR +indicates the instruction set the compiler can use, and there is no +generic instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.IP "\fBintel\fR" 4 +.IX Item "intel" +Produce code optimized for the most current Intel processors, which are +Haswell and Silvermont for this version of \s-1GCC.\s0 If you know the \s-1CPU\s0 +on which your code will run, then you should use the corresponding +\&\fB\-mtune\fR or \fB\-march\fR option instead of \fB\-mtune=intel\fR. +But, if you want your application performs better on both Haswell and +Silvermont, then you should use this option. +.Sp +As new Intel processors are deployed in the marketplace, the behavior of +this option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +the most current Intel processors at the time that version of \s-1GCC\s0 is +released. +.Sp +There is no \fB\-march=intel\fR option because \fB\-march\fR indicates +the instruction set the compiler can use, and there is no common +instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.RE +.RS 4 +.RE +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +A deprecated synonym for \fB\-mtune\fR. +.IP "\fB\-mfpmath=\fR\fIunit\fR" 4 +.IX Item "-mfpmath=unit" +Generate floating-point arithmetic for selected unit \fIunit\fR. The choices +for \fIunit\fR are: +.RS 4 +.IP "\fB387\fR" 4 +.IX Item "387" +Use the standard 387 floating-point coprocessor present on the majority of chips and +emulated otherwise. Code compiled with this option runs almost everywhere. +The temporary results are computed in 80\-bit precision instead of the precision +specified by the type, resulting in slightly different results compared to most +of other chips. See \fB\-ffloat\-store\fR for more detailed description. +.Sp +This is the default choice for non-Darwin x86\-32 targets. +.IP "\fBsse\fR" 4 +.IX Item "sse" +Use scalar floating-point instructions present in the \s-1SSE\s0 instruction set. +This instruction set is supported by Pentium \s-1III\s0 and newer chips, +and in the \s-1AMD\s0 line +by Athlon\-4, Athlon \s-1XP\s0 and Athlon \s-1MP\s0 chips. The earlier version of the \s-1SSE\s0 +instruction set supports only single-precision arithmetic, thus the double and +extended-precision arithmetic are still done using 387. A later version, present +only in Pentium 4 and \s-1AMD\s0 x86\-64 chips, supports double-precision +arithmetic too. +.Sp +For the x86\-32 compiler, you must use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR +or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option +effective. For the x86\-64 compiler, these extensions are enabled by default. +.Sp +The resulting code should be considerably faster in the majority of cases and avoid +the numerical instability problems of 387 code, but may break some existing +code that expects temporaries to be 80 bits. +.Sp +This is the default choice for the x86\-64 compiler, Darwin x86\-32 targets, +and the default choice for x86\-32 targets with the \s-1SSE2\s0 instruction set +when \fB\-ffast\-math\fR is enabled. +.IP "\fBsse,387\fR" 4 +.IX Item "sse,387" +.PD 0 +.IP "\fBsse+387\fR" 4 +.IX Item "sse+387" +.IP "\fBboth\fR" 4 +.IX Item "both" +.PD +Attempt to utilize both instruction sets at once. This effectively doubles the +amount of available registers, and on chips with separate execution units for +387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is +still experimental, because the \s-1GCC\s0 register allocator does not model separate +functional units well, resulting in unstable performance. +.RE +.RS 4 +.RE +.IP "\fB\-masm=\fR\fIdialect\fR" 4 +.IX Item "-masm=dialect" +Output assembly instructions using selected \fIdialect\fR. Also affects +which dialect is used for basic \f(CW\*(C`asm\*(C'\fR and +extended \f(CW\*(C`asm\*(C'\fR. Supported choices (in dialect +order) are \fBatt\fR or \fBintel\fR. The default is \fBatt\fR. Darwin does +not support \fBintel\fR. +.IP "\fB\-mieee\-fp\fR" 4 +.IX Item "-mieee-fp" +.PD 0 +.IP "\fB\-mno\-ieee\-fp\fR" 4 +.IX Item "-mno-ieee-fp" +.PD +Control whether or not the compiler uses \s-1IEEE\s0 floating-point +comparisons. These correctly handle the case where the result of a +comparison is unordered. +.IP "\fB\-m80387\fR" 4 +.IX Item "-m80387" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing 80387 instructions for floating point. +.IP "\fB\-mno\-80387\fR" 4 +.IX Item "-mno-80387" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +.Sp +\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC.\s0 +Normally the facilities of the machine's usual C compiler are used, but +this cannot be done directly in cross-compilation. You must make your +own arrangements to provide suitable library functions for +cross-compilation. +.Sp +On machines where a function returns floating-point results in the 80387 +register stack, some floating-point opcodes may be emitted even if +\&\fB\-msoft\-float\fR is used. +.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 +.IX Item "-mno-fp-ret-in-387" +Do not use the \s-1FPU\s0 registers for return values of functions. +.Sp +The usual calling convention has functions return values of types +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there +is no \s-1FPU.\s0 The idea is that the operating system should emulate +an \s-1FPU.\s0 +.Sp +The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned +in ordinary \s-1CPU\s0 registers instead. +.IP "\fB\-mno\-fancy\-math\-387\fR" 4 +.IX Item "-mno-fancy-math-387" +Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and +\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid +generating those instructions. +This option is overridden when \fB\-march\fR +indicates that the target \s-1CPU\s0 always has an \s-1FPU\s0 and so the +instruction does not need emulation. These +instructions are not generated unless you also use the +\&\fB\-funsafe\-math\-optimizations\fR switch. +.IP "\fB\-malign\-double\fR" 4 +.IX Item "-malign-double" +.PD 0 +.IP "\fB\-mno\-align\-double\fR" 4 +.IX Item "-mno-align-double" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and +\&\f(CW\*(C`long long\*(C'\fR variables on a two-word boundary or a one-word +boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two-word boundary +produces code that runs somewhat faster on a Pentium at the +expense of more memory. +.Sp +On x86\-64, \fB\-malign\-double\fR is enabled by default. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, +structures containing the above types are aligned differently than +the published application binary interface specifications for the x86\-32 +and are not binary compatible with structures in code compiled +without that switch. +.IP "\fB\-m96bit\-long\-double\fR" 4 +.IX Item "-m96bit-long-double" +.PD 0 +.IP "\fB\-m128bit\-long\-double\fR" 4 +.IX Item "-m128bit-long-double" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The x86\-32 +application binary interface specifies the size to be 96 bits, +so \fB\-m96bit\-long\-double\fR is the default in 32\-bit mode. +.Sp +Modern architectures (Pentium and newer) prefer \f(CW\*(C`long double\*(C'\fR +to be aligned to an 8\- or 16\-byte boundary. In arrays or structures +conforming to the \s-1ABI,\s0 this is not possible. So specifying +\&\fB\-m128bit\-long\-double\fR aligns \f(CW\*(C`long double\*(C'\fR +to a 16\-byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional +32\-bit zero. +.Sp +In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as +its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is aligned on 16\-byte boundary. +.Sp +Notice that neither of these options enable any extra precision over the x87 +standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +changes the size of +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, +as well as modifying the function calling convention for functions taking +\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible +with code compiled without that switch. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-80\fR" 4 +.IX Item "-mlong-double-80" +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default for 32\-bit Bionic C library. A size +of 128 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the +\&\f(CW\*(C`_\|_float128\*(C'\fR type. This is the default for 64\-bit Bionic C library. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +changes the size of +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, +as well as modifying the function calling convention for functions taking +\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible +with code compiled without that switch. +.IP "\fB\-malign\-data=\fR\fItype\fR" 4 +.IX Item "-malign-data=type" +Control how \s-1GCC\s0 aligns variables. Supported values for \fItype\fR are +\&\fBcompat\fR uses increased alignment value compatible uses \s-1GCC 4.8\s0 +and earlier, \fBabi\fR uses alignment value as specified by the +psABI, and \fBcacheline\fR uses increased alignment value to match +the cache line size. \fBcompat\fR is the default. +.IP "\fB\-mlarge\-data\-threshold=\fR\fIthreshold\fR" 4 +.IX Item "-mlarge-data-threshold=threshold" +When \fB\-mcmodel=medium\fR is specified, data objects larger than +\&\fIthreshold\fR are placed in the large data section. This value must be the +same across all objects linked into the binary, and defaults to 65535. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions that +take a fixed number of arguments return with the \f(CW\*(C`ret \f(CInum\f(CW\*(C'\fR +instruction, which pops their arguments while returning. This saves one +instruction in the caller since there is no need to pop the arguments +there. +.Sp +You can specify that an individual function is called with this calling +sequence with the function attribute \f(CW\*(C`stdcall\*(C'\fR. You can also +override the \fB\-mrtd\fR option by using the function attribute +\&\f(CW\*(C`cdecl\*(C'\fR. +.Sp +\&\fBWarning:\fR this calling convention is incompatible with the one +normally used on Unix, so you cannot use it if you need to call +libraries compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code is generated for calls to those +functions. +.Sp +In addition, seriously incorrect code results if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.IP "\fB\-mregparm=\fR\fInum\fR" 4 +.IX Item "-mregparm=num" +Control how many registers are used to pass integer arguments. By +default, no registers are used to pass arguments, and at most 3 +registers can be used. You can control this behavior for a specific +function by using the function attribute \f(CW\*(C`regparm\*(C'\fR. +.Sp +\&\fBWarning:\fR if you use this switch, and +\&\fInum\fR is nonzero, then you must build all modules with the same +value, including any libraries. This includes the system libraries and +startup modules. +.IP "\fB\-msseregparm\fR" 4 +.IX Item "-msseregparm" +Use \s-1SSE\s0 register passing conventions for float and double arguments +and return values. You can control this behavior for a specific +function by using the function attribute \f(CW\*(C`sseregparm\*(C'\fR. +.Sp +\&\fBWarning:\fR if you use this switch then you must build all +modules with the same value, including any libraries. This includes +the system libraries and startup modules. +.IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 +.IX Item "-mvect8-ret-in-mem" +Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the +default on Solaris 8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun +Studio compilers until version 12. Later compiler versions (starting +with Studio 12 Update 1) follow the \s-1ABI\s0 used by other x86 targets, which +is the default on Solaris 10 and later. \fIOnly\fR use this option if +you need to remain compatible with existing code produced by those +previous compiler versions or older versions of \s-1GCC.\s0 +.IP "\fB\-mpc32\fR" 4 +.IX Item "-mpc32" +.PD 0 +.IP "\fB\-mpc64\fR" 4 +.IX Item "-mpc64" +.IP "\fB\-mpc80\fR" 4 +.IX Item "-mpc80" +.PD +Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR +is specified, the significands of results of floating-point operations are +rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the +significands of results of floating-point operations to 53 bits (double +precision) and \fB\-mpc80\fR rounds the significands of results of +floating-point operations to 64 bits (extended double precision), which is +the default. When this option is used, floating-point operations in higher +precisions are not available to the programmer without setting the \s-1FPU\s0 +control word explicitly. +.Sp +Setting the rounding of floating-point operations to less than the default +80 bits can speed some programs by 2% or more. Note that some mathematical +libraries assume that extended-precision (80\-bit) floating-point operations +are enabled by default; routines in such libraries could suffer significant +loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", +when this option is used to set the precision to less than extended precision. +.IP "\fB\-mstackrealign\fR" 4 +.IX Item "-mstackrealign" +Realign the stack at entry. On the x86, the \fB\-mstackrealign\fR +option generates an alternate prologue and epilogue that realigns the +run-time stack if necessary. This supports mixing legacy codes that keep +4\-byte stack alignment with modern codes that keep 16\-byte stack alignment for +\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, +applicable to individual functions. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128 bits). +.Sp +\&\fBWarning:\fR When generating code for the x86\-64 architecture with +\&\s-1SSE\s0 extensions disabled, \fB\-mpreferred\-stack\-boundary=3\fR can be +used to keep the stack boundary aligned to 8 byte boundary. Since +x86\-64 \s-1ABI\s0 require 16 byte stack alignment, this is \s-1ABI\s0 incompatible and +intended to be used in controlled environment where stack space is +important limitation. This option leads to wrong code when functions +compiled with 16 byte stack alignment (such as functions from a standard +library) are called with misaligned stack. In this case, \s-1SSE\s0 +instructions may lead to misaligned memory access traps. In addition, +variable arguments are handled incorrectly for 16 byte aligned +objects (including x87 long double and _\|_int128), leading to wrong +results. You must build all modules with +\&\fB\-mpreferred\-stack\-boundary=3\fR, including any libraries. This +includes the system libraries and startup modules. +.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mincoming-stack-boundary=num" +Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte +boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, +the one specified by \fB\-mpreferred\-stack\-boundary\fR is used. +.Sp +On Pentium and Pentium Pro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values +should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or +suffer significant run time performance penalties. On Pentium \s-1III,\s0 the +Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work +properly if it is not 16\-byte aligned. +.Sp +To ensure proper alignment of this values on the stack, the stack boundary +must be as aligned as that required by any value stored on the stack. +Further, every function must be generated such that it keeps the stack +aligned. Thus calling a function compiled with a higher preferred +stack boundary from a function compiled with a lower preferred stack +boundary most likely misaligns the stack. It is recommended that +libraries that use callbacks always use the default setting. +.Sp +This extra alignment does consume extra stack space, and generally +increases code size. Code that is sensitive to stack space usage, such +as embedded systems and operating system kernels, may want to reduce the +preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. +.IP "\fB\-mmmx\fR" 4 +.IX Item "-mmmx" +.PD 0 +.IP "\fB\-msse\fR" 4 +.IX Item "-msse" +.IP "\fB\-msse2\fR" 4 +.IX Item "-msse2" +.IP "\fB\-msse3\fR" 4 +.IX Item "-msse3" +.IP "\fB\-mssse3\fR" 4 +.IX Item "-mssse3" +.IP "\fB\-msse4\fR" 4 +.IX Item "-msse4" +.IP "\fB\-msse4a\fR" 4 +.IX Item "-msse4a" +.IP "\fB\-msse4.1\fR" 4 +.IX Item "-msse4.1" +.IP "\fB\-msse4.2\fR" 4 +.IX Item "-msse4.2" +.IP "\fB\-mavx\fR" 4 +.IX Item "-mavx" +.IP "\fB\-mavx2\fR" 4 +.IX Item "-mavx2" +.IP "\fB\-mavx512f\fR" 4 +.IX Item "-mavx512f" +.IP "\fB\-mavx512pf\fR" 4 +.IX Item "-mavx512pf" +.IP "\fB\-mavx512er\fR" 4 +.IX Item "-mavx512er" +.IP "\fB\-mavx512cd\fR" 4 +.IX Item "-mavx512cd" +.IP "\fB\-mavx512vl\fR" 4 +.IX Item "-mavx512vl" +.IP "\fB\-mavx512bw\fR" 4 +.IX Item "-mavx512bw" +.IP "\fB\-mavx512dq\fR" 4 +.IX Item "-mavx512dq" +.IP "\fB\-mavx512ifma\fR" 4 +.IX Item "-mavx512ifma" +.IP "\fB\-mavx512vbmi\fR" 4 +.IX Item "-mavx512vbmi" +.IP "\fB\-msha\fR" 4 +.IX Item "-msha" +.IP "\fB\-maes\fR" 4 +.IX Item "-maes" +.IP "\fB\-mpclmul\fR" 4 +.IX Item "-mpclmul" +.IP "\fB\-mclflushopt\fR" 4 +.IX Item "-mclflushopt" +.IP "\fB\-mclwb\fR" 4 +.IX Item "-mclwb" +.IP "\fB\-mfsgsbase\fR" 4 +.IX Item "-mfsgsbase" +.IP "\fB\-mptwrite\fR" 4 +.IX Item "-mptwrite" +.IP "\fB\-mrdrnd\fR" 4 +.IX Item "-mrdrnd" +.IP "\fB\-mf16c\fR" 4 +.IX Item "-mf16c" +.IP "\fB\-mfma\fR" 4 +.IX Item "-mfma" +.IP "\fB\-mpconfig\fR" 4 +.IX Item "-mpconfig" +.IP "\fB\-mwbnoinvd\fR" 4 +.IX Item "-mwbnoinvd" +.IP "\fB\-mfma4\fR" 4 +.IX Item "-mfma4" +.IP "\fB\-mprfchw\fR" 4 +.IX Item "-mprfchw" +.IP "\fB\-mrdpid\fR" 4 +.IX Item "-mrdpid" +.IP "\fB\-mprefetchwt1\fR" 4 +.IX Item "-mprefetchwt1" +.IP "\fB\-mrdseed\fR" 4 +.IX Item "-mrdseed" +.IP "\fB\-msgx\fR" 4 +.IX Item "-msgx" +.IP "\fB\-mxop\fR" 4 +.IX Item "-mxop" +.IP "\fB\-mlwp\fR" 4 +.IX Item "-mlwp" +.IP "\fB\-m3dnow\fR" 4 +.IX Item "-m3dnow" +.IP "\fB\-m3dnowa\fR" 4 +.IX Item "-m3dnowa" +.IP "\fB\-mpopcnt\fR" 4 +.IX Item "-mpopcnt" +.IP "\fB\-mabm\fR" 4 +.IX Item "-mabm" +.IP "\fB\-madx\fR" 4 +.IX Item "-madx" +.IP "\fB\-mbmi\fR" 4 +.IX Item "-mbmi" +.IP "\fB\-mbmi2\fR" 4 +.IX Item "-mbmi2" +.IP "\fB\-mlzcnt\fR" 4 +.IX Item "-mlzcnt" +.IP "\fB\-mfxsr\fR" 4 +.IX Item "-mfxsr" +.IP "\fB\-mxsave\fR" 4 +.IX Item "-mxsave" +.IP "\fB\-mxsaveopt\fR" 4 +.IX Item "-mxsaveopt" +.IP "\fB\-mxsavec\fR" 4 +.IX Item "-mxsavec" +.IP "\fB\-mxsaves\fR" 4 +.IX Item "-mxsaves" +.IP "\fB\-mrtm\fR" 4 +.IX Item "-mrtm" +.IP "\fB\-mhle\fR" 4 +.IX Item "-mhle" +.IP "\fB\-mtbm\fR" 4 +.IX Item "-mtbm" +.IP "\fB\-mmwaitx\fR" 4 +.IX Item "-mmwaitx" +.IP "\fB\-mclzero\fR" 4 +.IX Item "-mclzero" +.IP "\fB\-mpku\fR" 4 +.IX Item "-mpku" +.IP "\fB\-mavx512vbmi2\fR" 4 +.IX Item "-mavx512vbmi2" +.IP "\fB\-mgfni\fR" 4 +.IX Item "-mgfni" +.IP "\fB\-mvaes\fR" 4 +.IX Item "-mvaes" +.IP "\fB\-mwaitpkg\fR" 4 +.IX Item "-mwaitpkg" +.IP "\fB\-mvpclmulqdq\fR" 4 +.IX Item "-mvpclmulqdq" +.IP "\fB\-mavx512bitalg\fR" 4 +.IX Item "-mavx512bitalg" +.IP "\fB\-mmovdiri\fR" 4 +.IX Item "-mmovdiri" +.IP "\fB\-mmovdir64b\fR" 4 +.IX Item "-mmovdir64b" +.IP "\fB\-mavx512vpopcntdq\fR" 4 +.IX Item "-mavx512vpopcntdq" +.IP "\fB\-mavx5124fmaps\fR" 4 +.IX Item "-mavx5124fmaps" +.IP "\fB\-mavx512vnni\fR" 4 +.IX Item "-mavx512vnni" +.IP "\fB\-mavx5124vnniw\fR" 4 +.IX Item "-mavx5124vnniw" +.IP "\fB\-mcldemote\fR" 4 +.IX Item "-mcldemote" +.PD +These switches enable the use of instructions in the \s-1MMX, SSE, +SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, +AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, +AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, +WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,\s0 +3DNow!, enhanced 3DNow!, \s-1POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE, +XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2, +GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, +AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW,\s0 or \s-1CLDEMOTE\s0 +extended instruction sets. Each has a corresponding \fB\-mno\-\fR option to +disable use of these instructions. +.Sp +These extensions are also available as built-in functions: see +\&\fBx86 Built-in Functions\fR, for details of the functions enabled and +disabled by these switches. +.Sp +To generate \s-1SSE/SSE2\s0 instructions automatically from floating-point +code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. +.Sp +\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it +generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions +when needed. +.Sp +These options enable \s-1GCC\s0 to use these extended instructions in +generated code, even without \fB\-mfpmath=sse\fR. Applications that +perform run-time \s-1CPU\s0 detection must compile separate files for each +supported architecture, using the appropriate flags. In particular, +the file containing the \s-1CPU\s0 detection code should be compiled without +these options. +.IP "\fB\-mdump\-tune\-features\fR" 4 +.IX Item "-mdump-tune-features" +This option instructs \s-1GCC\s0 to dump the names of the x86 performance +tuning features and default settings. The names can be used in +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR. +.IP "\fB\-mtune\-ctrl=\fR\fIfeature-list\fR" 4 +.IX Item "-mtune-ctrl=feature-list" +This option is used to do fine grain control of x86 code generation features. +\&\fIfeature-list\fR is a comma separated list of \fIfeature\fR names. See also +\&\fB\-mdump\-tune\-features\fR. When specified, the \fIfeature\fR is turned +on if it is not preceded with \fB^\fR, otherwise, it is turned off. +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR is intended to be used by \s-1GCC\s0 +developers. Using it may lead to code paths not covered by testing and can +potentially result in compiler ICEs or runtime errors. +.IP "\fB\-mno\-default\fR" 4 +.IX Item "-mno-default" +This option instructs \s-1GCC\s0 to turn off all tunable features. See also +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR and \fB\-mdump\-tune\-features\fR. +.IP "\fB\-mcld\fR" 4 +.IX Item "-mcld" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue +of functions that use string instructions. String instructions depend on +the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the +\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating +systems violate this specification by not clearing the \s-1DF\s0 flag in their +exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag +set, which leads to wrong direction mode when string instructions are used. +This option can be enabled by default on 32\-bit x86 targets by configuring +\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR +instructions can be suppressed with the \fB\-mno\-cld\fR compiler option +in this case. +.IP "\fB\-mvzeroupper\fR" 4 +.IX Item "-mvzeroupper" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction +before a transfer of control flow out of the function to minimize +the \s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary \f(CW\*(C`zeroupper\*(C'\fR +intrinsics. +.IP "\fB\-mprefer\-avx128\fR" 4 +.IX Item "-mprefer-avx128" +This option instructs \s-1GCC\s0 to use 128\-bit \s-1AVX\s0 instructions instead of +256\-bit \s-1AVX\s0 instructions in the auto-vectorizer. +.IP "\fB\-mprefer\-vector\-width=\fR\fIopt\fR" 4 +.IX Item "-mprefer-vector-width=opt" +This option instructs \s-1GCC\s0 to use \fIopt\fR\-bit vector width in instructions +instead of default on the selected platform. +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +No extra limitations applied to \s-1GCC\s0 other than defined by the selected platform. +.IP "\fB128\fR" 4 +.IX Item "128" +Prefer 128\-bit vector width for instructions. +.IP "\fB256\fR" 4 +.IX Item "256" +Prefer 256\-bit vector width for instructions. +.IP "\fB512\fR" 4 +.IX Item "512" +Prefer 512\-bit vector width for instructions. +.RE +.RS 4 +.RE +.IP "\fB\-mcx16\fR" 4 +.IX Item "-mcx16" +This option enables \s-1GCC\s0 to generate \f(CW\*(C`CMPXCHG16B\*(C'\fR instructions in 64\-bit +code to implement compare-and-exchange operations on 16\-byte aligned 128\-bit +objects. This is useful for atomic updates of data structures exceeding one +machine word in size. The compiler uses this instruction to implement +\&\fB_\|_sync Builtins\fR. However, for \fB_\|_atomic Builtins\fR operating on +128\-bit integers, a library call is always used. +.IP "\fB\-msahf\fR" 4 +.IX Item "-msahf" +This option enables generation of \f(CW\*(C`SAHF\*(C'\fR instructions in 64\-bit code. +Early Intel Pentium 4 CPUs with Intel 64 support, +prior to the introduction of Pentium 4 G1 step in December 2005, +lacked the \f(CW\*(C`LAHF\*(C'\fR and \f(CW\*(C`SAHF\*(C'\fR instructions +which are supported by \s-1AMD64.\s0 +These are load and store instructions, respectively, for certain status flags. +In 64\-bit mode, the \f(CW\*(C`SAHF\*(C'\fR instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, +\&\f(CW\*(C`drem\*(C'\fR, and \f(CW\*(C`remainder\*(C'\fR built-in functions; +see \fBOther Builtins\fR for details. +.IP "\fB\-mmovbe\fR" 4 +.IX Item "-mmovbe" +This option enables use of the \f(CW\*(C`movbe\*(C'\fR instruction to implement +\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. +.IP "\fB\-mshstk\fR" 4 +.IX Item "-mshstk" +The \fB\-mshstk\fR option enables shadow stack built-in functions +from x86 Control-flow Enforcement Technology (\s-1CET\s0). +.IP "\fB\-mcrc32\fR" 4 +.IX Item "-mcrc32" +This option enables built-in functions \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, +\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR, \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and +\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the \f(CW\*(C`crc32\*(C'\fR machine instruction. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +This option enables use of \f(CW\*(C`RCPSS\*(C'\fR and \f(CW\*(C`RSQRTSS\*(C'\fR instructions +(and their vectorized variants \f(CW\*(C`RCPPS\*(C'\fR and \f(CW\*(C`RSQRTPS\*(C'\fR) +with an additional Newton-Raphson step +to increase precision instead of \f(CW\*(C`DIVSS\*(C'\fR and \f(CW\*(C`SQRTSS\*(C'\fR +(and their vectorized +variants) for single-precision floating-point arguments. These instructions +are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled +together with \fB\-ffinite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. +Note that while the throughput of the sequence is higher than the throughput +of the non-reciprocal instruction, the precision of the sequence can be +decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). +.Sp +Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \f(CW\*(C`RSQRTSS\*(C'\fR +(or \f(CW\*(C`RSQRTPS\*(C'\fR) already with \fB\-ffast\-math\fR (or the above option +combination), and doesn't need \fB\-mrecip\fR. +.Sp +Also note that \s-1GCC\s0 emits the above sequence with additional Newton-Raphson step +for vectorized single-float division and vectorized \f(CW\*(C`sqrtf(\f(CIx\f(CW)\*(C'\fR +already with \fB\-ffast\-math\fR (or the above option combination), and +doesn't need \fB\-mrecip\fR. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option controls which reciprocal estimate instructions +may be used. \fIopt\fR is a comma-separated list of options, which may +be preceded by a \fB!\fR to invert the option: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all estimate instructions. +.IP "\fBdefault\fR" 4 +.IX Item "default" +Enable the default instructions, equivalent to \fB\-mrecip\fR. +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR. +.IP "\fBdiv\fR" 4 +.IX Item "div" +Enable the approximation for scalar division. +.IP "\fBvec-div\fR" 4 +.IX Item "vec-div" +Enable the approximation for vectorized division. +.IP "\fBsqrt\fR" 4 +.IX Item "sqrt" +Enable the approximation for scalar square root. +.IP "\fBvec-sqrt\fR" 4 +.IX Item "vec-sqrt" +Enable the approximation for vectorized square root. +.RE +.RS 4 +.Sp +So, for example, \fB\-mrecip=all,!sqrt\fR enables +all of the reciprocal approximations, except for square root. +.RE +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. Supported values for \fItype\fR are \fBsvml\fR +for the Intel short +vector math library and \fBacml\fR for the \s-1AMD\s0 math core library. +To use this option, both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML\s0 +ABI-compatible library must be specified at link time. +.Sp +\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR, +\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, +\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, +\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, +\&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, +\&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, +\&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, +\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, +\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, +\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding +function type when \fB\-mveclibabi=svml\fR is used, and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for the corresponding function type +when \fB\-mveclibabi=acml\fR is used. +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified calling convention. Permissible values +are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and +\&\fBms\fR for the Microsoft \s-1ABI.\s0 The default is to use the Microsoft +\&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems. +You can control this behavior for specific functions by +using the function attributes \f(CW\*(C`ms_abi\*(C'\fR and \f(CW\*(C`sysv_abi\*(C'\fR. +.IP "\fB\-mforce\-indirect\-call\fR" 4 +.IX Item "-mforce-indirect-call" +Force all calls to functions to be indirect. This is useful +when using Intel Processor Trace where it generates more precise timing +information for function calls. +.IP "\fB\-mmanual\-endbr\fR" 4 +.IX Item "-mmanual-endbr" +Insert \s-1ENDBR\s0 instruction at function entry only via the \f(CW\*(C`cf_check\*(C'\fR +function attribute. This is useful when used with the option +\&\fB\-fcf\-protection=branch\fR to control \s-1ENDBR\s0 insertion at the +function entry. +.IP "\fB\-mcall\-ms2sysv\-xlogues\fR" 4 +.IX Item "-mcall-ms2sysv-xlogues" +Due to differences in 64\-bit ABIs, any Microsoft \s-1ABI\s0 function that calls a +System V \s-1ABI\s0 function must consider \s-1RSI, RDI\s0 and \s-1XMM6\-15\s0 as clobbered. By +default, the code for saving and restoring these registers is emitted inline, +resulting in fairly lengthy prologues and epilogues. Using +\&\fB\-mcall\-ms2sysv\-xlogues\fR emits prologues and epilogues that +use stubs in the static portion of libgcc to perform these saves and restores, +thus reducing function size at the cost of a few extra instructions. +.IP "\fB\-mtls\-dialect=\fR\fItype\fR" 4 +.IX Item "-mtls-dialect=type" +Generate code to access thread-local storage using the \fBgnu\fR or +\&\fBgnu2\fR conventions. \fBgnu\fR is the conservative default; +\&\fBgnu2\fR is more efficient, but it may add compile\- and run-time +requirements that cannot be satisfied on all systems. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" +.PD 0 +.IP "\fB\-mno\-push\-args\fR" 4 +.IX Item "-mno-push-args" +.PD +Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter +and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled +by default. In some cases disabling it may improve performance because of +improved scheduling and reduced dependencies. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +If enabled, the maximum amount of space required for outgoing arguments is +computed in the function prologue. This is faster on most modern CPUs +because of reduced dependencies, improved scheduling and reduced stack usage +when the preferred stack boundary is not equal to 2. The drawback is a notable +increase in code size. This switch implies \fB\-mno\-push\-args\fR. +.IP "\fB\-mthreads\fR" 4 +.IX Item "-mthreads" +Support thread-safe exception handling on MinGW. Programs that rely +on thread-safe exception handling must compile and link all code with the +\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines +\&\fB\-D_MT\fR; when linking, it links in a special thread helper library +\&\fB\-lmingwthrd\fR which cleans up per-thread exception-handling data. +.IP "\fB\-mms\-bitfields\fR" 4 +.IX Item "-mms-bitfields" +.PD 0 +.IP "\fB\-mno\-ms\-bitfields\fR" 4 +.IX Item "-mno-ms-bitfields" +.PD +Enable/disable bit-field layout compatible with the native Microsoft +Windows compiler. +.Sp +If \f(CW\*(C`packed\*(C'\fR is used on a structure, or if bit-fields are used, +it may be that the Microsoft \s-1ABI\s0 lays out the structure differently +than the way \s-1GCC\s0 normally does. Particularly when moving packed +data between functions compiled with \s-1GCC\s0 and the native Microsoft compiler +(either via function call or as data in a file), it may be necessary to access +either format. +.Sp +This option is enabled by default for Microsoft Windows +targets. This behavior can also be controlled locally by use of variable +or type attributes. For more information, see \fBx86 Variable Attributes\fR +and \fBx86 Type Attributes\fR. +.Sp +The Microsoft structure layout algorithm is fairly simple with the exception +of the bit-field packing. +The padding and alignment of members of structures and whether a bit-field +can straddle a storage-unit boundary are determine by these rules: +.RS 4 +.IP "1. Structure members are stored sequentially in the order in which they are" 4 +.IX Item "1. Structure members are stored sequentially in the order in which they are" +declared: the first member has the lowest memory address and the last member +the highest. +.IP "2. Every data object has an alignment requirement. The alignment requirement" 4 +.IX Item "2. Every data object has an alignment requirement. The alignment requirement" +for all data except structures, unions, and arrays is either the size of the +object or the current packing size (specified with either the +\&\f(CW\*(C`aligned\*(C'\fR attribute or the \f(CW\*(C`pack\*(C'\fR pragma), +whichever is less. For structures, unions, and arrays, +the alignment requirement is the largest alignment requirement of its members. +Every object is allocated an offset so that: +.Sp +.Vb 1 +\& offset % alignment_requirement == 0 +.Ve +.IP "3. Adjacent bit-fields are packed into the same 1\-, 2\-, or 4\-byte allocation" 4 +.IX Item "3. Adjacent bit-fields are packed into the same 1-, 2-, or 4-byte allocation" +unit if the integral types are the same size and if the next bit-field fits +into the current allocation unit without crossing the boundary imposed by the +common alignment requirements of the bit-fields. +.RE +.RS 4 +.Sp +\&\s-1MSVC\s0 interprets zero-length bit-fields in the following ways: +.IP "1. If a zero-length bit-field is inserted between two bit-fields that" 4 +.IX Item "1. If a zero-length bit-field is inserted between two bit-fields that" +are normally coalesced, the bit-fields are not coalesced. +.Sp +For example: +.Sp +.Vb 6 +\& struct +\& { +\& unsigned long bf_1 : 12; +\& unsigned long : 0; +\& unsigned long bf_2 : 12; +\& } t1; +.Ve +.Sp +The size of \f(CW\*(C`t1\*(C'\fR is 8 bytes with the zero-length bit-field. If the +zero-length bit-field were removed, \f(CW\*(C`t1\*(C'\fR's size would be 4 bytes. +.ie n .IP "2. If a zero-length bit-field is inserted after a bit-field, ""foo"", and the" 4 +.el .IP "2. If a zero-length bit-field is inserted after a bit-field, \f(CWfoo\fR, and the" 4 +.IX Item "2. If a zero-length bit-field is inserted after a bit-field, foo, and the" +alignment of the zero-length bit-field is greater than the member that follows it, +\&\f(CW\*(C`bar\*(C'\fR, \f(CW\*(C`bar\*(C'\fR is aligned as the type of the zero-length bit-field. +.Sp +For example: +.Sp +.Vb 6 +\& struct +\& { +\& char foo : 4; +\& short : 0; +\& char bar; +\& } t2; +\& +\& struct +\& { +\& char foo : 4; +\& short : 0; +\& double bar; +\& } t3; +.Ve +.Sp +For \f(CW\*(C`t2\*(C'\fR, \f(CW\*(C`bar\*(C'\fR is placed at offset 2, rather than offset 1. +Accordingly, the size of \f(CW\*(C`t2\*(C'\fR is 4. For \f(CW\*(C`t3\*(C'\fR, the zero-length +bit-field does not affect the alignment of \f(CW\*(C`bar\*(C'\fR or, as a result, the size +of the structure. +.Sp +Taking this into account, it is important to note the following: +.RS 4 +.IP "1. If a zero-length bit-field follows a normal bit-field, the type of the" 4 +.IX Item "1. If a zero-length bit-field follows a normal bit-field, the type of the" +zero-length bit-field may affect the alignment of the structure as whole. For +example, \f(CW\*(C`t2\*(C'\fR has a size of 4 bytes, since the zero-length bit-field follows a +normal bit-field, and is of type short. +.IP "2. Even if a zero-length bit-field is not followed by a normal bit-field, it may" 4 +.IX Item "2. Even if a zero-length bit-field is not followed by a normal bit-field, it may" +still affect the alignment of the structure: +.Sp +.Vb 5 +\& struct +\& { +\& char foo : 6; +\& long : 0; +\& } t4; +.Ve +.Sp +Here, \f(CW\*(C`t4\*(C'\fR takes up 4 bytes. +.RE +.RS 4 +.RE +.IP "3. Zero-length bit-fields following non-bit-field members are ignored:" 4 +.IX Item "3. Zero-length bit-fields following non-bit-field members are ignored:" +.Vb 6 +\& struct +\& { +\& char foo; +\& long : 0; +\& char bar; +\& } t5; +.Ve +.Sp +Here, \f(CW\*(C`t5\*(C'\fR takes up 2 bytes. +.RE +.RS 4 +.RE +.IP "\fB\-mno\-align\-stringops\fR" 4 +.IX Item "-mno-align-stringops" +Do not align the destination of inlined string operations. This switch reduces +code size and improves performance in case the destination is already aligned, +but \s-1GCC\s0 doesn't know about it. +.IP "\fB\-minline\-all\-stringops\fR" 4 +.IX Item "-minline-all-stringops" +By default \s-1GCC\s0 inlines string operations only when the destination is +known to be aligned to least a 4\-byte boundary. +This enables more inlining and increases code +size, but may improve performance of code that depends on fast +\&\f(CW\*(C`memcpy\*(C'\fR, \f(CW\*(C`strlen\*(C'\fR, +and \f(CW\*(C`memset\*(C'\fR for short lengths. +.IP "\fB\-minline\-stringops\-dynamically\fR" 4 +.IX Item "-minline-stringops-dynamically" +For string operations of unknown size, use run-time checks with +inline code for small blocks and a library call for large blocks. +.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 +.IX Item "-mstringop-strategy=alg" +Override the internal decision heuristic for the particular algorithm to use +for inlining string operations. The allowed values for \fIalg\fR are: +.RS 4 +.IP "\fBrep_byte\fR" 4 +.IX Item "rep_byte" +.PD 0 +.IP "\fBrep_4byte\fR" 4 +.IX Item "rep_4byte" +.IP "\fBrep_8byte\fR" 4 +.IX Item "rep_8byte" +.PD +Expand using i386 \f(CW\*(C`rep\*(C'\fR prefix of the specified size. +.IP "\fBbyte_loop\fR" 4 +.IX Item "byte_loop" +.PD 0 +.IP "\fBloop\fR" 4 +.IX Item "loop" +.IP "\fBunrolled_loop\fR" 4 +.IX Item "unrolled_loop" +.PD +Expand into an inline loop. +.IP "\fBlibcall\fR" 4 +.IX Item "libcall" +Always use a library call. +.RE +.RS 4 +.RE +.IP "\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR" 4 +.IX Item "-mmemcpy-strategy=strategy" +Override the internal decision heuristic to decide if \f(CW\*(C`_\|_builtin_memcpy\*(C'\fR +should be inlined and what inline algorithm to use when the expected size +of the copy operation is known. \fIstrategy\fR +is a comma-separated list of \fIalg\fR:\fImax_size\fR:\fIdest_align\fR triplets. +\&\fIalg\fR is specified in \fB\-mstringop\-strategy\fR, \fImax_size\fR specifies +the max byte size with which inline algorithm \fIalg\fR is allowed. For the last +triplet, the \fImax_size\fR must be \f(CW\*(C`\-1\*(C'\fR. The \fImax_size\fR of the triplets +in the list must be specified in increasing order. The minimal byte size for +\&\fIalg\fR is \f(CW0\fR for the first triplet and \f(CW\*(C`\f(CImax_size\f(CW + 1\*(C'\fR of the +preceding range. +.IP "\fB\-mmemset\-strategy=\fR\fIstrategy\fR" 4 +.IX Item "-mmemset-strategy=strategy" +The option is similar to \fB\-mmemcpy\-strategy=\fR except that it is to control +\&\f(CW\*(C`_\|_builtin_memset\*(C'\fR expansion. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up, and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-leaf\-frame\-pointer\fR removes the frame pointer for leaf functions, +which might make debugging harder. +.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 +.IX Item "-mtls-direct-seg-refs" +.PD 0 +.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 +.IX Item "-mno-tls-direct-seg-refs" +.PD +Controls whether \s-1TLS\s0 variables may be accessed with offsets from the +\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), +or whether the thread base pointer must be added. Whether or not this +is valid depends on the operating system, and whether it maps the +segment to cover the entire \s-1TLS\s0 area. +.Sp +For systems that use the \s-1GNU C\s0 Library, the default is on. +.IP "\fB\-msse2avx\fR" 4 +.IX Item "-msse2avx" +.PD 0 +.IP "\fB\-mno\-sse2avx\fR" 4 +.IX Item "-mno-sse2avx" +.PD +Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 +prefix. The option \fB\-mavx\fR turns this on by default. +.IP "\fB\-mfentry\fR" 4 +.IX Item "-mfentry" +.PD 0 +.IP "\fB\-mno\-fentry\fR" 4 +.IX Item "-mno-fentry" +.PD +If profiling is active (\fB\-pg\fR), put the profiling +counter call before the prologue. +Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR +isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. +.IP "\fB\-mrecord\-mcount\fR" 4 +.IX Item "-mrecord-mcount" +.PD 0 +.IP "\fB\-mno\-record\-mcount\fR" 4 +.IX Item "-mno-record-mcount" +.PD +If profiling is active (\fB\-pg\fR), generate a _\|_mcount_loc section +that contains pointers to each profiling call. This is useful for +automatically patching and out calls. +.IP "\fB\-mnop\-mcount\fR" 4 +.IX Item "-mnop-mcount" +.PD 0 +.IP "\fB\-mno\-nop\-mcount\fR" 4 +.IX Item "-mno-nop-mcount" +.PD +If profiling is active (\fB\-pg\fR), generate the calls to +the profiling functions as NOPs. This is useful when they +should be patched in later dynamically. This is likely only +useful together with \fB\-mrecord\-mcount\fR. +.IP "\fB\-minstrument\-return=\fR\fItype\fR" 4 +.IX Item "-minstrument-return=type" +Instrument function exit in \-pg \-mfentry instrumented functions with +call to specified function. This only instruments true returns ending +with ret, but not sibling calls ending with jump. Valid types +are \fInone\fR to not instrument, \fIcall\fR to generate a call to _\|_return_\|_, +or \fInop5\fR to generate a 5 byte nop. +.IP "\fB\-mrecord\-return\fR" 4 +.IX Item "-mrecord-return" +.PD 0 +.IP "\fB\-mno\-record\-return\fR" 4 +.IX Item "-mno-record-return" +.PD +Generate a _\|_return_loc section pointing to all return instrumentation code. +.IP "\fB\-mfentry\-name=\fR\fIname\fR" 4 +.IX Item "-mfentry-name=name" +Set name of _\|_fentry_\|_ symbol called at function entry for \-pg \-mfentry functions. +.IP "\fB\-mfentry\-section=\fR\fIname\fR" 4 +.IX Item "-mfentry-section=name" +Set name of section to record \-mrecord\-mcount calls (default _\|_mcount_loc). +.IP "\fB\-mskip\-rax\-setup\fR" 4 +.IX Item "-mskip-rax-setup" +.PD 0 +.IP "\fB\-mno\-skip\-rax\-setup\fR" 4 +.IX Item "-mno-skip-rax-setup" +.PD +When generating code for the x86\-64 architecture with \s-1SSE\s0 extensions +disabled, \fB\-mskip\-rax\-setup\fR can be used to skip setting up \s-1RAX\s0 +register when there are no variable arguments passed in vector registers. +.Sp +\&\fBWarning:\fR Since \s-1RAX\s0 register is used to avoid unnecessarily +saving vector registers on stack when passing variable arguments, the +impacts of this option are callees may waste some stack space, +misbehave or jump to a random location. \s-1GCC 4.4\s0 or newer don't have +those issues, regardless the \s-1RAX\s0 register value. +.IP "\fB\-m8bit\-idiv\fR" 4 +.IX Item "-m8bit-idiv" +.PD 0 +.IP "\fB\-mno\-8bit\-idiv\fR" 4 +.IX Item "-mno-8bit-idiv" +.PD +On some processors, like Intel Atom, 8\-bit unsigned integer divide is +much faster than 32\-bit/64\-bit integer divide. This option generates a +run-time check. If both dividend and divisor are within range of 0 +to 255, 8\-bit unsigned integer divide is used instead of +32\-bit/64\-bit integer divide. +.IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 +.IX Item "-mavx256-split-unaligned-load" +.PD 0 +.IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 +.IX Item "-mavx256-split-unaligned-store" +.PD +Split 32\-byte \s-1AVX\s0 unaligned load and store. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for global canary or \fBtls\fR for per-thread +canary in the \s-1TLS\s0 block (the default). This option has effect only when +\&\fB\-fstack\-protector\fR or \fB\-fstack\-protector\-all\fR is specified. +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which segment register (\f(CW%fs\fR or \f(CW%gs\fR) to use as base register +for reading the canary, and from what offset from that base register. +The default for those is as specified in the relevant \s-1ABI.\s0 +.IP "\fB\-mgeneral\-regs\-only\fR" 4 +.IX Item "-mgeneral-regs-only" +Generate code that uses only the general-purpose registers. This +prevents the compiler from using floating-point, vector, mask and bound +registers. +.IP "\fB\-mindirect\-branch=\fR\fIchoice\fR" 4 +.IX Item "-mindirect-branch=choice" +Convert indirect call and jump with \fIchoice\fR. The default is +\&\fBkeep\fR, which keeps indirect call and jump unmodified. +\&\fBthunk\fR converts indirect call and jump to call and return thunk. +\&\fBthunk-inline\fR converts indirect call and jump to inlined call +and return thunk. \fBthunk-extern\fR converts indirect call and jump +to external call and return thunk provided in a separate object file. +You can control this behavior for a specific function by using the +function attribute \f(CW\*(C`indirect_branch\*(C'\fR. +.Sp +Note that \fB\-mcmodel=large\fR is incompatible with +\&\fB\-mindirect\-branch=thunk\fR and +\&\fB\-mindirect\-branch=thunk\-extern\fR since the thunk function may +not be reachable in the large code model. +.Sp +Note that \fB\-mindirect\-branch=thunk\-extern\fR is compatible with +\&\fB\-fcf\-protection=branch\fR since the external thunk can be made +to enable control-flow check. +.IP "\fB\-mfunction\-return=\fR\fIchoice\fR" 4 +.IX Item "-mfunction-return=choice" +Convert function return with \fIchoice\fR. The default is \fBkeep\fR, +which keeps function return unmodified. \fBthunk\fR converts function +return to call and return thunk. \fBthunk-inline\fR converts function +return to inlined call and return thunk. \fBthunk-extern\fR converts +function return to external call and return thunk provided in a separate +object file. You can control this behavior for a specific function by +using the function attribute \f(CW\*(C`function_return\*(C'\fR. +.Sp +Note that \fB\-mindirect\-return=thunk\-extern\fR is compatible with +\&\fB\-fcf\-protection=branch\fR since the external thunk can be made +to enable control-flow check. +.Sp +Note that \fB\-mcmodel=large\fR is incompatible with +\&\fB\-mfunction\-return=thunk\fR and +\&\fB\-mfunction\-return=thunk\-extern\fR since the thunk function may +not be reachable in the large code model. +.IP "\fB\-mindirect\-branch\-register\fR" 4 +.IX Item "-mindirect-branch-register" +Force indirect call and jump via register. +.PP +These \fB\-m\fR switches are supported in addition to the above +on x86\-64 processors in 64\-bit environments. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.IP "\fB\-mx32\fR" 4 +.IX Item "-mx32" +.IP "\fB\-m16\fR" 4 +.IX Item "-m16" +.IP "\fB\-miamcu\fR" 4 +.IX Item "-miamcu" +.PD +Generate code for a 16\-bit, 32\-bit or 64\-bit environment. +The \fB\-m32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types +to 32 bits, and +generates code that runs on any i386 system. +.Sp +The \fB\-m64\fR option sets \f(CW\*(C`int\*(C'\fR to 32 bits and \f(CW\*(C`long\*(C'\fR and pointer +types to 64 bits, and generates code for the x86\-64 architecture. +For Darwin only the \fB\-m64\fR option also turns off the \fB\-fno\-pic\fR +and \fB\-mdynamic\-no\-pic\fR options. +.Sp +The \fB\-mx32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types +to 32 bits, and +generates code for the x86\-64 architecture. +.Sp +The \fB\-m16\fR option is the same as \fB\-m32\fR, except for that +it outputs the \f(CW\*(C`.code16gcc\*(C'\fR assembly directive at the beginning of +the assembly output so that the binary can run in 16\-bit mode. +.Sp +The \fB\-miamcu\fR option generates code which conforms to Intel \s-1MCU\s0 +psABI. It requires the \fB\-m32\fR option to be turned on. +.IP "\fB\-mno\-red\-zone\fR" 4 +.IX Item "-mno-red-zone" +Do not use a so-called \*(L"red zone\*(R" for x86\-64 code. The red zone is mandated +by the x86\-64 \s-1ABI\s0; it is a 128\-byte area beyond the location of the +stack pointer that is not modified by signal or interrupt handlers +and therefore can be used for temporary data without adjusting the stack +pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model: the program and its symbols must +be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. +Programs can be statically or dynamically linked. This is the default +code model. +.IP "\fB\-mcmodel=kernel\fR" 4 +.IX Item "-mcmodel=kernel" +Generate code for the kernel code model. The kernel runs in the +negative 2 \s-1GB\s0 of the address space. +This model has to be used for Linux kernel code. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate code for the medium model: the program is linked in the lower 2 +\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols +with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into +large data or \s-1BSS\s0 sections and can be located above 2GB. Programs can +be statically or dynamically linked. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model. This model makes no assumptions +about addresses and sizes of sections. +.IP "\fB\-maddress\-mode=long\fR" 4 +.IX Item "-maddress-mode=long" +Generate code for long address mode. This is only supported for 64\-bit +and x32 environments. It is the default address mode for 64\-bit +environments. +.IP "\fB\-maddress\-mode=short\fR" 4 +.IX Item "-maddress-mode=short" +Generate code for short address mode. This is only supported for 32\-bit +and x32 environments. It is the default address mode for 32\-bit and +x32 environments. +.PP +\fIx86 Windows Options\fR +.IX Subsection "x86 Windows Options" +.PP +These additional options are available for Microsoft Windows targets: +.IP "\fB\-mconsole\fR" 4 +.IX Item "-mconsole" +This option +specifies that a console application is to be generated, by +instructing the linker to set the \s-1PE\s0 header subsystem type +required for console applications. +This option is available for Cygwin and MinGW targets and is +enabled by default on those targets. +.IP "\fB\-mdll\fR" 4 +.IX Item "-mdll" +This option is available for Cygwin and MinGW targets. It +specifies that a DLL\-\-\-a dynamic link library\-\-\-is to be +generated, enabling the selection of the required runtime +startup object and entry point. +.IP "\fB\-mnop\-fun\-dllimport\fR" 4 +.IX Item "-mnop-fun-dllimport" +This option is available for Cygwin and MinGW targets. It +specifies that the \f(CW\*(C`dllimport\*(C'\fR attribute should be ignored. +.IP "\fB\-mthread\fR" 4 +.IX Item "-mthread" +This option is available for MinGW targets. It specifies +that MinGW-specific thread support is to be used. +.IP "\fB\-municode\fR" 4 +.IX Item "-municode" +This option is available for MinGW\-w64 targets. It causes +the \f(CW\*(C`UNICODE\*(C'\fR preprocessor macro to be predefined, and +chooses Unicode-capable runtime startup code. +.IP "\fB\-mwin32\fR" 4 +.IX Item "-mwin32" +This option is available for Cygwin and MinGW targets. It +specifies that the typical Microsoft Windows predefined macros are to +be set in the pre-processor, but does not influence the choice +of runtime library/startup code. +.IP "\fB\-mwindows\fR" 4 +.IX Item "-mwindows" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1GUI\s0 application is to be generated by +instructing the linker to set the \s-1PE\s0 header subsystem type +appropriately. +.IP "\fB\-fno\-set\-stack\-executable\fR" 4 +.IX Item "-fno-set-stack-executable" +This option is available for MinGW targets. It specifies that +the executable flag for the stack used by nested functions isn't +set. This is necessary for binaries running in kernel mode of +Microsoft Windows, as there the User32 \s-1API,\s0 which is used to set executable +privileges, isn't available. +.IP "\fB\-fwritable\-relocated\-rdata\fR" 4 +.IX Item "-fwritable-relocated-rdata" +This option is available for MinGW and Cygwin targets. It specifies +that relocated-data in read-only section is put into the \f(CW\*(C`.data\*(C'\fR +section. This is a necessary for older runtimes not supporting +modification of \f(CW\*(C`.rdata\*(C'\fR sections for pseudo-relocation. +.IP "\fB\-mpe\-aligned\-commons\fR" 4 +.IX Item "-mpe-aligned-commons" +This option is available for Cygwin and MinGW targets. It +specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that +permits the correct alignment of \s-1COMMON\s0 variables should be +used when generating code. It is enabled by default if +\&\s-1GCC\s0 detects that the target assembler found during configuration +supports the feature. +.PP +See also under \fBx86 Options\fR for standard options. +.PP +\fIXstormy16 Options\fR +.IX Subsection "Xstormy16 Options" +.PP +These options are defined for Xstormy16: +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Choose startup files and linker script suitable for the simulator. +.PP +\fIXtensa Options\fR +.IX Subsection "Xtensa Options" +.PP +These options are supported for Xtensa targets: +.IP "\fB\-mconst16\fR" 4 +.IX Item "-mconst16" +.PD 0 +.IP "\fB\-mno\-const16\fR" 4 +.IX Item "-mno-const16" +.PD +Enable or disable use of \f(CW\*(C`CONST16\*(C'\fR instructions for loading +constant values. The \f(CW\*(C`CONST16\*(C'\fR instruction is currently not a +standard option from Tensilica. When enabled, \f(CW\*(C`CONST16\*(C'\fR +instructions are always used in place of the standard \f(CW\*(C`L32R\*(C'\fR +instructions. The use of \f(CW\*(C`CONST16\*(C'\fR is enabled by default only if +the \f(CW\*(C`L32R\*(C'\fR instruction is not available. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable or disable use of fused multiply/add and multiply/subtract +instructions in the floating-point option. This has no effect if the +floating-point option is not also enabled. Disabling fused multiply/add +and multiply/subtract instructions forces the compiler to use separate +instructions for the multiply and add/subtract operations. This may be +desirable in some cases where strict \s-1IEEE\s0 754\-compliant results are +required: the fused multiply add/subtract instructions do not round the +intermediate result, thereby producing results with \fImore\fR bits of +precision than specified by the \s-1IEEE\s0 standard. Disabling fused multiply +add/subtract instructions also ensures that the program output is not +sensitive to the compiler's ability to combine multiply and add/subtract +operations. +.IP "\fB\-mserialize\-volatile\fR" 4 +.IX Item "-mserialize-volatile" +.PD 0 +.IP "\fB\-mno\-serialize\-volatile\fR" 4 +.IX Item "-mno-serialize-volatile" +.PD +When this option is enabled, \s-1GCC\s0 inserts \f(CW\*(C`MEMW\*(C'\fR instructions before +\&\f(CW\*(C`volatile\*(C'\fR memory references to guarantee sequential consistency. +The default is \fB\-mserialize\-volatile\fR. Use +\&\fB\-mno\-serialize\-volatile\fR to omit the \f(CW\*(C`MEMW\*(C'\fR instructions. +.IP "\fB\-mforce\-no\-pic\fR" 4 +.IX Item "-mforce-no-pic" +For targets, like GNU/Linux, where all user-mode Xtensa code must be +position-independent code (\s-1PIC\s0), this option disables \s-1PIC\s0 for compiling +kernel code. +.IP "\fB\-mtext\-section\-literals\fR" 4 +.IX Item "-mtext-section-literals" +.PD 0 +.IP "\fB\-mno\-text\-section\-literals\fR" 4 +.IX Item "-mno-text-section-literals" +.PD +These options control the treatment of literal pools. The default is +\&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate +section in the output file. This allows the literal pool to be placed +in a data \s-1RAM/ROM,\s0 and it also allows the linker to combine literal +pools from separate object files to remove redundant literals and +improve code size. With \fB\-mtext\-section\-literals\fR, the literals +are interspersed in the text section in order to keep them as close as +possible to their references. This may be necessary for large assembly +files. Literals for each function are placed right before that function. +.IP "\fB\-mauto\-litpools\fR" 4 +.IX Item "-mauto-litpools" +.PD 0 +.IP "\fB\-mno\-auto\-litpools\fR" 4 +.IX Item "-mno-auto-litpools" +.PD +These options control the treatment of literal pools. The default is +\&\fB\-mno\-auto\-litpools\fR, which places literals in a separate +section in the output file unless \fB\-mtext\-section\-literals\fR is +used. With \fB\-mauto\-litpools\fR the literals are interspersed in +the text section by the assembler. Compiler does not produce explicit +\&\f(CW\*(C`.literal\*(C'\fR directives and loads literals into registers with +\&\f(CW\*(C`MOVI\*(C'\fR instructions instead of \f(CW\*(C`L32R\*(C'\fR to let the assembler +do relaxation and place literals as necessary. This option allows +assembler to create several literal pools per function and assemble +very big functions, which may not be possible with +\&\fB\-mtext\-section\-literals\fR. +.IP "\fB\-mtarget\-align\fR" 4 +.IX Item "-mtarget-align" +.PD 0 +.IP "\fB\-mno\-target\-align\fR" 4 +.IX Item "-mno-target-align" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to +automatically align instructions to reduce branch penalties at the +expense of some code density. The assembler attempts to widen density +instructions to align branch targets and the instructions following call +instructions. If there are not enough preceding safe density +instructions to align a target, no widening is performed. The +default is \fB\-mtarget\-align\fR. These options do not affect the +treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the +assembler always aligns, either by widening density instructions or +by inserting \s-1NOP\s0 instructions. +.IP "\fB\-mlongcalls\fR" 4 +.IX Item "-mlongcalls" +.PD 0 +.IP "\fB\-mno\-longcalls\fR" 4 +.IX Item "-mno-longcalls" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to translate +direct calls to indirect calls unless it can determine that the target +of a direct call is in the range allowed by the call instruction. This +translation typically occurs for calls to functions in other source +files. Specifically, the assembler translates a direct \f(CW\*(C`CALL\*(C'\fR +instruction into an \f(CW\*(C`L32R\*(C'\fR followed by a \f(CW\*(C`CALLX\*(C'\fR instruction. +The default is \fB\-mno\-longcalls\fR. This option should be used in +programs where the call target can potentially be out of range. This +option is implemented in the assembler, not the compiler, so the +assembly code generated by \s-1GCC\s0 still shows direct call +instructions\-\-\-look at the disassembled object code to see the actual +instructions. Note that the assembler uses an indirect call for +every cross-file call, not just those that really are out of range. +.PP +\fIzSeries Options\fR +.IX Subsection "zSeries Options" +.PP +These are listed under +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +This section describes several environment variables that affect how \s-1GCC\s0 +operates. Some of them work by specifying directories or prefixes to use +when searching for various kinds of files. Some are used to specify other +aspects of the compilation environment. +.PP +Note that you can also specify places to search using options such as +\&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These +take precedence over places specified using environment variables, which +in turn take precedence over those specified by the configuration of \s-1GCC.\s0 +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +.PD 0 +.IP "\fB\s-1LC_CTYPE\s0\fR" 4 +.IX Item "LC_CTYPE" +.IP "\fB\s-1LC_MESSAGES\s0\fR" 4 +.IX Item "LC_MESSAGES" +.IP "\fB\s-1LC_ALL\s0\fR" 4 +.IX Item "LC_ALL" +.PD +These environment variables control the way that \s-1GCC\s0 uses +localization information which allows \s-1GCC\s0 to work with different +national conventions. \s-1GCC\s0 inspects the locale categories +\&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do +so. These locale categories can be set to any value supported by your +installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United +Kingdom encoded in \s-1UTF\-8.\s0 +.Sp +The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character +classification. \s-1GCC\s0 uses it to determine the character boundaries in +a string; this is needed for some multibyte encodings that contain quote +and escape characters that are otherwise interpreted as a string +end or escape. +.Sp +The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to +use in diagnostic messages. +.Sp +If the \fB\s-1LC_ALL\s0\fR environment variable is set, it overrides the value +of \fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR; otherwise, \fB\s-1LC_CTYPE\s0\fR +and \fB\s-1LC_MESSAGES\s0\fR default to the value of the \fB\s-1LANG\s0\fR +environment variable. If none of these variables are set, \s-1GCC\s0 +defaults to traditional C English behavior. +.IP "\fB\s-1TMPDIR\s0\fR" 4 +.IX Item "TMPDIR" +If \fB\s-1TMPDIR\s0\fR is set, it specifies the directory to use for temporary +files. \s-1GCC\s0 uses temporary files to hold the output of one stage of +compilation which is to be used as input to the next stage: for example, +the output of the preprocessor, which is the input to the compiler +proper. +.IP "\fB\s-1GCC_COMPARE_DEBUG\s0\fR" 4 +.IX Item "GCC_COMPARE_DEBUG" +Setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR is nearly equivalent to passing +\&\fB\-fcompare\-debug\fR to the compiler driver. See the documentation +of this option for more details. +.IP "\fB\s-1GCC_EXEC_PREFIX\s0\fR" 4 +.IX Item "GCC_EXEC_PREFIX" +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is set, it specifies a prefix to use in the +names of the subprograms executed by the compiler. No slash is added +when this prefix is combined with the name of a subprogram, but you can +specify a prefix that ends with a slash if you wish. +.Sp +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 attempts to figure out +an appropriate prefix to use based on the pathname it is invoked with. +.Sp +If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it +tries looking in the usual places for the subprogram. +.Sp +The default value of \fB\s-1GCC_EXEC_PREFIX\s0\fR is +\&\fI\fIprefix\fI/lib/gcc/\fR where \fIprefix\fR is the prefix to +the installed compiler. In many cases \fIprefix\fR is the value +of \f(CW\*(C`prefix\*(C'\fR when you ran the \fIconfigure\fR script. +.Sp +Other prefixes specified with \fB\-B\fR take precedence over this prefix. +.Sp +This prefix is also used for finding files such as \fIcrt0.o\fR that are +used for linking. +.Sp +In addition, the prefix is used in an unusual way in finding the +directories to search for header files. For each of the standard +directories whose name normally begins with \fB/usr/local/lib/gcc\fR +(more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries +replacing that beginning with the specified prefix to produce an +alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 searches +\&\fIfoo/bar\fR just before it searches the standard directory +\&\fI/usr/local/lib/bar\fR. +If a standard directory begins with the configured +\&\fIprefix\fR then the value of \fIprefix\fR is replaced by +\&\fB\s-1GCC_EXEC_PREFIX\s0\fR when looking for header files. +.IP "\fB\s-1COMPILER_PATH\s0\fR" 4 +.IX Item "COMPILER_PATH" +The value of \fB\s-1COMPILER_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. \s-1GCC\s0 tries the directories thus +specified when searching for subprograms, if it cannot find the +subprograms using \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\s-1LIBRARY_PATH\s0\fR" 4 +.IX Item "LIBRARY_PATH" +The value of \fB\s-1LIBRARY_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. When configured as a native compiler, +\&\s-1GCC\s0 tries the directories thus specified when searching for special +linker files, if it cannot find them using \fB\s-1GCC_EXEC_PREFIX\s0\fR. Linking +using \s-1GCC\s0 also uses these directories when searching for ordinary +libraries for the \fB\-l\fR option (but directories specified with +\&\fB\-L\fR come first). +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +This variable is used to pass locale information to the compiler. One way in +which this information is used is to determine the character set to be used +when character literals, string literals and comments are parsed in C and \*(C+. +When the compiler is configured to allow multibyte characters, +the following values for \fB\s-1LANG\s0\fR are recognized: +.RS 4 +.IP "\fBC\-JIS\fR" 4 +.IX Item "C-JIS" +Recognize \s-1JIS\s0 characters. +.IP "\fBC\-SJIS\fR" 4 +.IX Item "C-SJIS" +Recognize \s-1SJIS\s0 characters. +.IP "\fBC\-EUCJP\fR" 4 +.IX Item "C-EUCJP" +Recognize \s-1EUCJP\s0 characters. +.RE +.RS 4 +.Sp +If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the +compiler uses \f(CW\*(C`mblen\*(C'\fR and \f(CW\*(C`mbtowc\*(C'\fR as defined by the default locale to +recognize and translate multibyte characters. +.RE +.PP +Some additional environment variables affect the behavior of the +preprocessor. +.IP "\fB\s-1CPATH\s0\fR" 4 +.IX Item "CPATH" +.PD 0 +.IP "\fBC_INCLUDE_PATH\fR" 4 +.IX Item "C_INCLUDE_PATH" +.IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 +.IX Item "CPLUS_INCLUDE_PATH" +.IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 +.IX Item "OBJC_INCLUDE_PATH" +.PD +Each variable's value is a list of directories separated by a special +character, much like \fB\s-1PATH\s0\fR, in which to look for header files. +The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and +determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a +semicolon, and for almost all other targets it is a colon. +.Sp +\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if +specified with \fB\-I\fR, but after any paths given with \fB\-I\fR +options on the command line. This environment variable is used +regardless of which language is being preprocessed. +.Sp +The remaining environment variables apply only when preprocessing the +particular language indicated. Each specifies a list of directories +to be searched as if specified with \fB\-isystem\fR, but after any +paths given with \fB\-isystem\fR options on the command line. +.Sp +In all these variables, an empty element instructs the compiler to +search its current working directory. Empty elements can appear at the +beginning or end of a path. For instance, if the value of +\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same +effect as \fB\-I.\ \-I/special/include\fR. +.IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 +.IX Item "DEPENDENCIES_OUTPUT" +If this variable is set, its value specifies how to output +dependencies for Make based on the non-system header files processed +by the compiler. System header files are ignored in the dependency +output. +.Sp +The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in +which case the Make rules are written to that file, guessing the target +name from the source file name. Or the value can have the form +\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to +file \fIfile\fR using \fItarget\fR as the target name. +.Sp +In other words, this environment variable is equivalent to combining +the options \fB\-MM\fR and \fB\-MF\fR, +with an optional \fB\-MT\fR switch too. +.IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 +.IX Item "SUNPRO_DEPENDENCIES" +This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), +except that system header files are not ignored, so it implies +\&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the +main input file is omitted. +.IP "\fB\s-1SOURCE_DATE_EPOCH\s0\fR" 4 +.IX Item "SOURCE_DATE_EPOCH" +If this variable is set, its value specifies a \s-1UNIX\s0 timestamp to be +used in replacement of the current date and time in the \f(CW\*(C`_\|_DATE_\|_\*(C'\fR +and \f(CW\*(C`_\|_TIME_\|_\*(C'\fR macros, so that the embedded timestamps become +reproducible. +.Sp +The value of \fB\s-1SOURCE_DATE_EPOCH\s0\fR must be a \s-1UNIX\s0 timestamp, +defined as the number of seconds (excluding leap seconds) since +01 Jan 1970 00:00:00 represented in \s-1ASCII\s0; identical to the output of +\&\fB\f(CB@command\fB{date +%s\fR} on GNU/Linux and other systems that support the +\&\f(CW%s\fR extension in the \f(CW\*(C`date\*(C'\fR command. +.Sp +The value should be a known timestamp such as the last modification +time of the source or package and it should be set by the build +process. +.SH "BUGS" +.IX Header "BUGS" +For instructions on reporting bugs, see +<\fBhttps://github.com/conda\-forge/ctng\-compilers\-feedstock/issues/new/choose\fR>. +.SH "FOOTNOTES" +.IX Header "FOOTNOTES" +.IP "1." 4 +On some systems, \fBgcc \-shared\fR +needs to build supplementary stub code for constructors to work. On +multi-libbed systems, \fBgcc \-shared\fR must select the correct support +libraries to link against. Failing to supply the correct flags may lead +to subtle defects. Supplying them in cases where they are not necessary +is innocuous. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fBgpl\fR\|(7), \fBgfdl\fR\|(7), \fBfsf\-funding\fR\|(7), +\&\fBcpp\fR\|(1), \fBgcov\fR\|(1), \fBas\fR\|(1), \fBld\fR\|(1), \fBgdb\fR\|(1), \fBdbx\fR\|(1) +and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, +\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. +.SH "AUTHOR" +.IX Header "AUTHOR" +See the Info entry for \fBgcc\fR, or +<\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, +for contributors to \s-1GCC.\s0 +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1988\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fBgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man1/gcc.1 b/man/man1/gcc.1 new file mode 100644 index 0000000000000000000000000000000000000000..f1c604aec1d8b38d8b6c8bba37d37153aa75ff44 --- /dev/null +++ b/man/man1/gcc.1 @@ -0,0 +1,28260 @@ +.\" Automatically generated by Pod::Man 4.14 (Pod::Simple 3.40) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{\ +. if \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +. \} +.\} +.rr rF +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCC 1" +.TH GCC 1 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcc \- GNU project C and C++ compiler +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] + [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] + [\fB\-W\fR\fIwarn\fR...] [\fB\-Wpedantic\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] + [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...] + [\fB\-o\fR \fIoutfile\fR] [@\fIfile\fR] \fIinfile\fR... +.PP +Only the most useful options are listed here; see below for the +remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +When you invoke \s-1GCC,\s0 it normally does preprocessing, compilation, +assembly and linking. The \*(L"overall options\*(R" allow you to stop this +process at an intermediate stage. For example, the \fB\-c\fR option +says not to run the linker. Then the output consists of object files +output by the assembler. +.PP +Other options are passed on to one or more stages of processing. Some options +control the preprocessor and others the compiler itself. Yet other +options control the assembler and linker; most of these are not +documented here, since you rarely need to use any of them. +.PP +Most of the command-line options that you can use with \s-1GCC\s0 are useful +for C programs; when an option is only useful with another language +(usually \*(C+), the explanation says so explicitly. If the description +for a particular option does not mention a source language, you can use +that option with all supported languages. +.PP +The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or +\&\fImachine\fR\fB\-gcc\fR when cross-compiling, or +\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a specific version of \s-1GCC.\s0 +When you compile \*(C+ programs, you should invoke \s-1GCC\s0 as \fBg++\fR +instead. +.PP +The \fBgcc\fR program accepts options and file names as operands. Many +options have multi-letter names; therefore multiple single-letter options +may \fInot\fR be grouped: \fB\-dv\fR is very different from \fB\-d\ \-v\fR. +.PP +You can mix options and other arguments. For the most part, the order +you use doesn't matter. Order does matter when you use several +options of the same kind; for example, if you specify \fB\-L\fR more +than once, the directories are searched in the order specified. Also, +the placement of the \fB\-l\fR option is significant. +.PP +Many options have long names starting with \fB\-f\fR or with +\&\fB\-W\fR\-\-\-for example, +\&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of +these have both positive and negative forms; the negative form of +\&\fB\-ffoo\fR is \fB\-fno\-foo\fR. This manual documents +only one of these two forms, whichever one is not the default. +.PP +Some options take one or more arguments typically separated either +by a space or by the equals sign (\fB=\fR) from the option name. +Unless documented otherwise, an argument can be either numeric or +a string. Numeric arguments must typically be small unsigned decimal +or hexadecimal integers. Hexadecimal arguments must begin with +the \fB0x\fR prefix. Arguments to options that specify a size +threshold of some sort may be arbitrarily large decimal or hexadecimal +integers followed by a byte size suffix designating a multiple of bytes +such as \f(CW\*(C`kB\*(C'\fR and \f(CW\*(C`KiB\*(C'\fR for kilobyte and kibibyte, respectively, +\&\f(CW\*(C`MB\*(C'\fR and \f(CW\*(C`MiB\*(C'\fR for megabyte and mebibyte, \f(CW\*(C`GB\*(C'\fR and +\&\f(CW\*(C`GiB\*(C'\fR for gigabyte and gigibyte, and so on. Such arguments are +designated by \fIbyte-size\fR in the following text. Refer to the \s-1NIST, +IEC,\s0 and other relevant national and international standards for the full +listing and explanation of the binary and decimal byte size prefixes. +.SH "OPTIONS" +.IX Header "OPTIONS" +.SS "Option Summary" +.IX Subsection "Option Summary" +Here is a summary of all the options, grouped by type. Explanations are +in the following sections. +.IP "\fIOverall Options\fR" 4 +.IX Item "Overall Options" +\&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-x\fR \fIlanguage\fR +\&\fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \-\-version +\&\-pass\-exit\-codes \-pipe \-specs=\fR\fIfile\fR \fB\-wrapper +@\fR\fIfile\fR \fB\-ffile\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR +\&\fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +.IP "\fIC Language Options\fR" 4 +.IX Item "C Language Options" +\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline +\&\-fpermitted\-flt\-eval\-methods=\fR\fIstandard\fR +\&\fB\-aux\-info\fR \fIfilename\fR \fB\-fallow\-parameterless\-variadic\-functions +\&\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR \fB\-fgimple +\&\-fhosted \-ffreestanding +\&\-fopenacc \-fopenacc\-dim=\fR\fIgeom\fR +\&\fB\-fopenmp \-fopenmp\-simd +\&\-fms\-extensions \-fplan9\-extensions \-fsso\-struct=\fR\fIendianness\fR +\&\fB\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions +\&\-fsigned\-bitfields \-fsigned\-char +\&\-funsigned\-bitfields \-funsigned\-char\fR +.IP "\fI\*(C+ Language Options\fR" 4 +.IX Item " Language Options" +\&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control +\&\-faligned\-new=\fR\fIn\fR \fB\-fargs\-in\-order=\fR\fIn\fR \fB\-fchar8_t \-fcheck\-new +\&\-fconstexpr\-depth=\fR\fIn\fR \fB\-fconstexpr\-loop\-limit=\fR\fIn\fR +\&\fB\-fconstexpr\-ops\-limit=\fR\fIn\fR \fB\-fno\-elide\-constructors +\&\-fno\-enforce\-eh\-specs +\&\-fno\-gnu\-keywords +\&\-fno\-implicit\-templates +\&\-fno\-implicit\-inline\-templates +\&\-fno\-implement\-inlines \-fms\-extensions +\&\-fnew\-inheriting\-ctors +\&\-fnew\-ttp\-matching +\&\-fno\-nonansi\-builtins \-fnothrow\-opt \-fno\-operator\-names +\&\-fno\-optional\-diags \-fpermissive +\&\-fno\-pretty\-templates +\&\-frepo \-fno\-rtti \-fsized\-deallocation +\&\-ftemplate\-backtrace\-limit=\fR\fIn\fR +\&\fB\-ftemplate\-depth=\fR\fIn\fR +\&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit +\&\-fno\-weak \-nostdinc++ +\&\-fvisibility\-inlines\-hidden +\&\-fvisibility\-ms\-compat +\&\-fext\-numeric\-literals +\&\-Wabi=\fR\fIn\fR \fB\-Wabi\-tag \-Wconversion\-null \-Wctor\-dtor\-privacy +\&\-Wdelete\-non\-virtual\-dtor \-Wdeprecated\-copy \-Wdeprecated\-copy\-dtor +\&\-Wliteral\-suffix +\&\-Wmultiple\-inheritance \-Wno\-init\-list\-lifetime +\&\-Wnamespaces \-Wnarrowing +\&\-Wpessimizing\-move \-Wredundant\-move +\&\-Wnoexcept \-Wnoexcept\-type \-Wclass\-memaccess +\&\-Wnon\-virtual\-dtor \-Wreorder \-Wregister +\&\-Weffc++ \-Wstrict\-null\-sentinel \-Wtemplates +\&\-Wno\-non\-template\-friend \-Wold\-style\-cast +\&\-Woverloaded\-virtual \-Wno\-pmf\-conversions +\&\-Wno\-class\-conversion \-Wno\-terminate +\&\-Wsign\-promo \-Wvirtual\-inheritance\fR +.IP "\fIObjective-C and Objective\-\*(C+ Language Options\fR" 4 +.IX Item "Objective-C and Objective- Language Options" +\&\fB\-fconstant\-string\-class=\fR\fIclass-name\fR +\&\fB\-fgnu\-runtime \-fnext\-runtime +\&\-fno\-nil\-receivers +\&\-fobjc\-abi\-version=\fR\fIn\fR +\&\fB\-fobjc\-call\-cxx\-cdtors +\&\-fobjc\-direct\-dispatch +\&\-fobjc\-exceptions +\&\-fobjc\-gc +\&\-fobjc\-nilcheck +\&\-fobjc\-std=objc1 +\&\-fno\-local\-ivars +\&\-fivar\-visibility=\fR[\fBpublic\fR|\fBprotected\fR|\fBprivate\fR|\fBpackage\fR] +\&\fB\-freplace\-objc\-classes +\&\-fzero\-link +\&\-gen\-decls +\&\-Wassign\-intercept +\&\-Wno\-protocol \-Wselector +\&\-Wstrict\-selector\-match +\&\-Wundeclared\-selector\fR +.IP "\fIDiagnostic Message Formatting Options\fR" 4 +.IX Item "Diagnostic Message Formatting Options" +\&\fB\-fmessage\-length=\fR\fIn\fR +\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR] +\&\fB\-fdiagnostics\-color=\fR[\fBauto\fR|\fBnever\fR|\fBalways\fR] +\&\fB\-fdiagnostics\-format=\fR[\fBtext\fR|\fBjson\fR] +\&\fB\-fno\-diagnostics\-show\-option \-fno\-diagnostics\-show\-caret +\&\-fno\-diagnostics\-show\-labels \-fno\-diagnostics\-show\-line\-numbers +\&\-fdiagnostics\-minimum\-margin\-width=\fR\fIwidth\fR +\&\fB\-fdiagnostics\-parseable\-fixits \-fdiagnostics\-generate\-patch +\&\-fdiagnostics\-show\-template\-tree \-fno\-elide\-type +\&\-fno\-show\-column\fR +.IP "\fIWarning Options\fR" 4 +.IX Item "Warning Options" +\&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-Wpedantic +\&\-pedantic\-errors +\&\-w \-Wextra \-Wall \-Waddress \-Waddress\-of\-packed\-member +\&\-Waggregate\-return \-Waligned\-new +\&\-Walloc\-zero \-Walloc\-size\-larger\-than=\fR\fIbyte-size\fR +\&\fB\-Walloca \-Walloca\-larger\-than=\fR\fIbyte-size\fR +\&\fB\-Wno\-aggressive\-loop\-optimizations \-Warray\-bounds \-Warray\-bounds=\fR\fIn\fR +\&\fB\-Wno\-attributes \-Wattribute\-alias=\fR\fIn\fR +\&\fB\-Wbool\-compare \-Wbool\-operation +\&\-Wno\-builtin\-declaration\-mismatch +\&\-Wno\-builtin\-macro\-redefined \-Wc90\-c99\-compat \-Wc99\-c11\-compat +\&\-Wc11\-c2x\-compat +\&\-Wc++\-compat \-Wc++11\-compat \-Wc++14\-compat \-Wc++17\-compat +\&\-Wcast\-align \-Wcast\-align=strict \-Wcast\-function\-type \-Wcast\-qual +\&\-Wchar\-subscripts \-Wcatch\-value \-Wcatch\-value=\fR\fIn\fR +\&\fB\-Wclobbered \-Wcomment \-Wconditionally\-supported +\&\-Wconversion \-Wcoverage\-mismatch \-Wno\-cpp \-Wdangling\-else \-Wdate\-time +\&\-Wdelete\-incomplete +\&\-Wno\-attribute\-warning +\&\-Wno\-deprecated \-Wno\-deprecated\-declarations \-Wno\-designated\-init +\&\-Wdisabled\-optimization +\&\-Wno\-discarded\-qualifiers \-Wno\-discarded\-array\-qualifiers +\&\-Wno\-div\-by\-zero \-Wdouble\-promotion +\&\-Wduplicated\-branches \-Wduplicated\-cond +\&\-Wempty\-body \-Wenum\-compare \-Wno\-endif\-labels \-Wexpansion\-to\-defined +\&\-Werror \-Werror=* \-Wextra\-semi \-Wfatal\-errors +\&\-Wfloat\-equal \-Wformat \-Wformat=2 +\&\-Wno\-format\-contains\-nul \-Wno\-format\-extra\-args +\&\-Wformat\-nonliteral \-Wformat\-overflow=\fR\fIn\fR +\&\fB\-Wformat\-security \-Wformat\-signedness \-Wformat\-truncation=\fR\fIn\fR +\&\fB\-Wformat\-y2k \-Wframe\-address +\&\-Wframe\-larger\-than=\fR\fIbyte-size\fR \fB\-Wno\-free\-nonheap\-object +\&\-Wjump\-misses\-init +\&\-Whsa \-Wif\-not\-aligned +\&\-Wignored\-qualifiers \-Wignored\-attributes \-Wincompatible\-pointer\-types +\&\-Wimplicit \-Wimplicit\-fallthrough \-Wimplicit\-fallthrough=\fR\fIn\fR +\&\fB\-Wimplicit\-function\-declaration \-Wimplicit\-int +\&\-Winit\-self \-Winline \-Wno\-int\-conversion \-Wint\-in\-bool\-context +\&\-Wno\-int\-to\-pointer\-cast \-Winvalid\-memory\-model \-Wno\-invalid\-offsetof +\&\-Winvalid\-pch \-Wlarger\-than=\fR\fIbyte-size\fR +\&\fB\-Wlogical\-op \-Wlogical\-not\-parentheses \-Wlong\-long +\&\-Wmain \-Wmaybe\-uninitialized \-Wmemset\-elt\-size \-Wmemset\-transposed\-args +\&\-Wmisleading\-indentation \-Wmissing\-attributes \-Wmissing\-braces +\&\-Wmissing\-field\-initializers \-Wmissing\-format\-attribute +\&\-Wmissing\-include\-dirs \-Wmissing\-noreturn \-Wmissing\-profile +\&\-Wno\-multichar \-Wmultistatement\-macros \-Wnonnull \-Wnonnull\-compare +\&\-Wnormalized=\fR[\fBnone\fR|\fBid\fR|\fBnfc\fR|\fBnfkc\fR] +\&\fB\-Wnull\-dereference \-Wodr \-Wno\-overflow \-Wopenmp\-simd +\&\-Woverride\-init\-side\-effects \-Woverlength\-strings +\&\-Wpacked \-Wpacked\-bitfield\-compat \-Wpacked\-not\-aligned \-Wpadded +\&\-Wparentheses \-Wno\-pedantic\-ms\-format +\&\-Wplacement\-new \-Wplacement\-new=\fR\fIn\fR +\&\fB\-Wpointer\-arith \-Wpointer\-compare \-Wno\-pointer\-to\-int\-cast +\&\-Wno\-pragmas \-Wno\-prio\-ctor\-dtor \-Wredundant\-decls +\&\-Wrestrict \-Wno\-return\-local\-addr +\&\-Wreturn\-type \-Wsequence\-point \-Wshadow \-Wno\-shadow\-ivar +\&\-Wshadow=global, \-Wshadow=local, \-Wshadow=compatible\-local +\&\-Wshift\-overflow \-Wshift\-overflow=\fR\fIn\fR +\&\fB\-Wshift\-count\-negative \-Wshift\-count\-overflow \-Wshift\-negative\-value +\&\-Wsign\-compare \-Wsign\-conversion \-Wfloat\-conversion +\&\-Wno\-scalar\-storage\-order \-Wsizeof\-pointer\-div +\&\-Wsizeof\-pointer\-memaccess \-Wsizeof\-array\-argument +\&\-Wstack\-protector \-Wstack\-usage=\fR\fIbyte-size\fR \fB\-Wstrict\-aliasing +\&\-Wstrict\-aliasing=n \-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR +\&\fB\-Wstringop\-overflow=\fR\fIn\fR \fB\-Wstringop\-truncation \-Wsubobject\-linkage +\&\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR|\fBformat\fR|\fBmalloc\fR] +\&\fB\-Wsuggest\-final\-types \-Wsuggest\-final\-methods \-Wsuggest\-override +\&\-Wswitch \-Wswitch\-bool \-Wswitch\-default \-Wswitch\-enum +\&\-Wswitch\-unreachable \-Wsync\-nand +\&\-Wsystem\-headers \-Wtautological\-compare \-Wtrampolines \-Wtrigraphs +\&\-Wtype\-limits \-Wundef +\&\-Wuninitialized \-Wunknown\-pragmas +\&\-Wunsuffixed\-float\-constants \-Wunused \-Wunused\-function +\&\-Wunused\-label \-Wunused\-local\-typedefs \-Wunused\-macros +\&\-Wunused\-parameter \-Wno\-unused\-result +\&\-Wunused\-value \-Wunused\-variable +\&\-Wunused\-const\-variable \-Wunused\-const\-variable=\fR\fIn\fR +\&\fB\-Wunused\-but\-set\-parameter \-Wunused\-but\-set\-variable +\&\-Wuseless\-cast \-Wvariadic\-macros \-Wvector\-operation\-performance +\&\-Wvla \-Wvla\-larger\-than=\fR\fIbyte-size\fR \fB\-Wvolatile\-register\-var +\&\-Wwrite\-strings +\&\-Wzero\-as\-null\-pointer\-constant\fR +.IP "\fIC and Objective-C-only Warning Options\fR" 4 +.IX Item "C and Objective-C-only Warning Options" +\&\fB\-Wbad\-function\-cast \-Wmissing\-declarations +\&\-Wmissing\-parameter\-type \-Wmissing\-prototypes \-Wnested\-externs +\&\-Wold\-style\-declaration \-Wold\-style\-definition +\&\-Wstrict\-prototypes \-Wtraditional \-Wtraditional\-conversion +\&\-Wdeclaration\-after\-statement \-Wpointer\-sign\fR +.IP "\fIDebugging Options\fR" 4 +.IX Item "Debugging Options" +\&\fB\-g \-g\fR\fIlevel\fR \fB\-gdwarf \-gdwarf\-\fR\fIversion\fR +\&\fB\-ggdb \-grecord\-gcc\-switches \-gno\-record\-gcc\-switches +\&\-gstabs \-gstabs+ \-gstrict\-dwarf \-gno\-strict\-dwarf +\&\-gas\-loc\-support \-gno\-as\-loc\-support +\&\-gas\-locview\-support \-gno\-as\-locview\-support +\&\-gcolumn\-info \-gno\-column\-info +\&\-gstatement\-frontiers \-gno\-statement\-frontiers +\&\-gvariable\-location\-views \-gno\-variable\-location\-views +\&\-ginternal\-reset\-location\-views \-gno\-internal\-reset\-location\-views +\&\-ginline\-points \-gno\-inline\-points +\&\-gvms \-gxcoff \-gxcoff+ \-gz\fR[\fB=\fR\fItype\fR] +\&\fB\-gsplit\-dwarf \-gdescribe\-dies \-gno\-describe\-dies +\&\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR \fB\-fdebug\-types\-section +\&\-fno\-eliminate\-unused\-debug\-types +\&\-femit\-struct\-debug\-baseonly \-femit\-struct\-debug\-reduced +\&\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR] +\&\fB\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always +\&\-fno\-merge\-debug\-strings \-fno\-dwarf2\-cfi\-asm +\&\-fvar\-tracking \-fvar\-tracking\-assignments\fR +.IP "\fIOptimization Options\fR" 4 +.IX Item "Optimization Options" +\&\fB\-faggressive\-loop\-optimizations +\&\-falign\-functions[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-falign\-jumps[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-falign\-labels[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-falign\-loops[=\fR\fIn\fR\fB[:\fR\fIm\fR\fB:[\fR\fIn2\fR\fB[:\fR\fIm2\fR\fB]]]] +\&\-fassociative\-math \-fauto\-profile \-fauto\-profile[=\fR\fIpath\fR\fB] +\&\-fauto\-inc\-dec \-fbranch\-probabilities +\&\-fbranch\-target\-load\-optimize \-fbranch\-target\-load\-optimize2 +\&\-fbtr\-bb\-exclusive \-fcaller\-saves +\&\-fcombine\-stack\-adjustments \-fconserve\-stack +\&\-fcompare\-elim \-fcprop\-registers \-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fcx\-fortran\-rules +\&\-fcx\-limited\-range +\&\-fdata\-sections \-fdce \-fdelayed\-branch +\&\-fdelete\-null\-pointer\-checks \-fdevirtualize \-fdevirtualize\-speculatively +\&\-fdevirtualize\-at\-ltrans \-fdse +\&\-fearly\-inlining \-fipa\-sra \-fexpensive\-optimizations \-ffat\-lto\-objects +\&\-ffast\-math \-ffinite\-math\-only \-ffloat\-store \-fexcess\-precision=\fR\fIstyle\fR +\&\fB\-fforward\-propagate \-ffp\-contract=\fR\fIstyle\fR \fB\-ffunction\-sections +\&\-fgcse \-fgcse\-after\-reload \-fgcse\-las \-fgcse\-lm \-fgraphite\-identity +\&\-fgcse\-sm \-fhoist\-adjacent\-loads \-fif\-conversion +\&\-fif\-conversion2 \-findirect\-inlining +\&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR +\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone +\&\-fipa\-bit\-cp \-fipa\-vrp \-fipa\-pta \-fipa\-profile \-fipa\-pure\-const +\&\-fipa\-reference \-fipa\-reference\-addressable +\&\-fipa\-stack\-alignment \-fipa\-icf \-fira\-algorithm=\fR\fIalgorithm\fR +\&\fB\-flive\-patching=\fR\fIlevel\fR +\&\fB\-fira\-region=\fR\fIregion\fR \fB\-fira\-hoist\-pressure +\&\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots +\&\-fno\-ira\-share\-spill\-slots +\&\-fisolate\-erroneous\-paths\-dereference \-fisolate\-erroneous\-paths\-attribute +\&\-fivopts \-fkeep\-inline\-functions \-fkeep\-static\-functions +\&\-fkeep\-static\-consts \-flimit\-function\-alignment \-flive\-range\-shrinkage +\&\-floop\-block \-floop\-interchange \-floop\-strip\-mine +\&\-floop\-unroll\-and\-jam \-floop\-nest\-optimize +\&\-floop\-parallelize\-all \-flra\-remat \-flto \-flto\-compression\-level +\&\-flto\-partition=\fR\fIalg\fR \fB\-fmerge\-all\-constants +\&\-fmerge\-constants \-fmodulo\-sched \-fmodulo\-sched\-allow\-regmoves +\&\-fmove\-loop\-invariants \-fno\-branch\-count\-reg +\&\-fno\-defer\-pop \-fno\-fp\-int\-builtin\-inexact \-fno\-function\-cse +\&\-fno\-guess\-branch\-probability \-fno\-inline \-fno\-math\-errno \-fno\-peephole +\&\-fno\-peephole2 \-fno\-printf\-return\-value \-fno\-sched\-interblock +\&\-fno\-sched\-spec \-fno\-signed\-zeros +\&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss +\&\-fomit\-frame\-pointer \-foptimize\-sibling\-calls +\&\-fpartial\-inlining \-fpeel\-loops \-fpredictive\-commoning +\&\-fprefetch\-loop\-arrays +\&\-fprofile\-correction +\&\-fprofile\-use \-fprofile\-use=\fR\fIpath\fR \fB\-fprofile\-values +\&\-fprofile\-reorder\-functions +\&\-freciprocal\-math \-free \-frename\-registers \-freorder\-blocks +\&\-freorder\-blocks\-algorithm=\fR\fIalgorithm\fR +\&\fB\-freorder\-blocks\-and\-partition \-freorder\-functions +\&\-frerun\-cse\-after\-loop \-freschedule\-modulo\-scheduled\-loops +\&\-frounding\-math \-fsave\-optimization\-record +\&\-fsched2\-use\-superblocks \-fsched\-pressure +\&\-fsched\-spec\-load \-fsched\-spec\-load\-dangerous +\&\-fsched\-stalled\-insns\-dep[=\fR\fIn\fR\fB] \-fsched\-stalled\-insns[=\fR\fIn\fR\fB] +\&\-fsched\-group\-heuristic \-fsched\-critical\-path\-heuristic +\&\-fsched\-spec\-insn\-heuristic \-fsched\-rank\-heuristic +\&\-fsched\-last\-insn\-heuristic \-fsched\-dep\-count\-heuristic +\&\-fschedule\-fusion +\&\-fschedule\-insns \-fschedule\-insns2 \-fsection\-anchors +\&\-fselective\-scheduling \-fselective\-scheduling2 +\&\-fsel\-sched\-pipelining \-fsel\-sched\-pipelining\-outer\-loops +\&\-fsemantic\-interposition \-fshrink\-wrap \-fshrink\-wrap\-separate +\&\-fsignaling\-nans +\&\-fsingle\-precision\-constant \-fsplit\-ivs\-in\-unroller \-fsplit\-loops +\&\-fsplit\-paths +\&\-fsplit\-wide\-types \-fssa\-backprop \-fssa\-phiopt +\&\-fstdarg\-opt \-fstore\-merging \-fstrict\-aliasing +\&\-fthread\-jumps \-ftracer \-ftree\-bit\-ccp +\&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch +\&\-ftree\-coalesce\-vars \-ftree\-copy\-prop \-ftree\-dce \-ftree\-dominator\-opts +\&\-ftree\-dse \-ftree\-forwprop \-ftree\-fre \-fcode\-hoisting +\&\-ftree\-loop\-if\-convert \-ftree\-loop\-im +\&\-ftree\-phiprop \-ftree\-loop\-distribution \-ftree\-loop\-distribute\-patterns +\&\-ftree\-loop\-ivcanon \-ftree\-loop\-linear \-ftree\-loop\-optimize +\&\-ftree\-loop\-vectorize +\&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-partial\-pre \-ftree\-pta +\&\-ftree\-reassoc \-ftree\-scev\-cprop \-ftree\-sink \-ftree\-slsr \-ftree\-sra +\&\-ftree\-switch\-conversion \-ftree\-tail\-merge +\&\-ftree\-ter \-ftree\-vectorize \-ftree\-vrp \-funconstrained\-commons +\&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops +\&\-funsafe\-math\-optimizations \-funswitch\-loops +\&\-fipa\-ra \-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt +\&\-fweb \-fwhole\-program \-fwpa \-fuse\-linker\-plugin +\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR +\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast \-Og\fR +.IP "\fIProgram Instrumentation Options\fR" 4 +.IX Item "Program Instrumentation Options" +\&\fB\-p \-pg \-fprofile\-arcs \-\-coverage \-ftest\-coverage +\&\-fprofile\-abs\-path +\&\-fprofile\-dir=\fR\fIpath\fR \fB\-fprofile\-generate \-fprofile\-generate=\fR\fIpath\fR +\&\fB\-fprofile\-update=\fR\fImethod\fR \fB\-fprofile\-filter\-files=\fR\fIregex\fR +\&\fB\-fprofile\-exclude\-files=\fR\fIregex\fR +\&\fB\-fsanitize=\fR\fIstyle\fR \fB\-fsanitize\-recover \-fsanitize\-recover=\fR\fIstyle\fR +\&\fB\-fasan\-shadow\-offset=\fR\fInumber\fR \fB\-fsanitize\-sections=\fR\fIs1\fR\fB,\fR\fIs2\fR\fB,... +\&\-fsanitize\-undefined\-trap\-on\-error \-fbounds\-check +\&\-fcf\-protection=\fR[\fBfull\fR|\fBbranch\fR|\fBreturn\fR|\fBnone\fR] +\&\fB\-fstack\-protector \-fstack\-protector\-all \-fstack\-protector\-strong +\&\-fstack\-protector\-explicit \-fstack\-check +\&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR +\&\fB\-fno\-stack\-limit \-fsplit\-stack +\&\-fvtable\-verify=\fR[\fBstd\fR|\fBpreinit\fR|\fBnone\fR] +\&\fB\-fvtv\-counts \-fvtv\-debug +\&\-finstrument\-functions +\&\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,... +\&\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR +.IP "\fIPreprocessor Options\fR" 4 +.IX Item "Preprocessor Options" +\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR +\&\fB\-A\-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] +\&\fB\-C \-CC \-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR] +\&\fB\-dD \-dI \-dM \-dN \-dU +\&\-fdebug\-cpp \-fdirectives\-only \-fdollars\-in\-identifiers +\&\-fexec\-charset=\fR\fIcharset\fR \fB\-fextended\-identifiers +\&\-finput\-charset=\fR\fIcharset\fR \fB\-fmacro\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR +\&\fB\-fno\-canonical\-system\-headers \-fpch\-deps \-fpch\-preprocess +\&\-fpreprocessed \-ftabstop=\fR\fIwidth\fR \fB\-ftrack\-macro\-expansion +\&\-fwide\-exec\-charset=\fR\fIcharset\fR \fB\-fworking\-directory +\&\-H \-imacros\fR \fIfile\fR \fB\-include\fR \fIfile\fR +\&\fB\-M \-MD \-MF \-MG \-MM \-MMD \-MP \-MQ \-MT +\&\-no\-integrated\-cpp \-P \-pthread \-remap +\&\-traditional \-traditional\-cpp \-trigraphs +\&\-U\fR\fImacro\fR \fB\-undef +\&\-Wp,\fR\fIoption\fR \fB\-Xpreprocessor\fR \fIoption\fR +.IP "\fIAssembler Options\fR" 4 +.IX Item "Assembler Options" +\&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR +.IP "\fILinker Options\fR" 4 +.IX Item "Linker Options" +\&\fIobject-file-name\fR \fB\-fuse\-ld=\fR\fIlinker\fR \fB\-l\fR\fIlibrary\fR +\&\fB\-nostartfiles \-nodefaultlibs \-nolibc \-nostdlib +\&\-e\fR \fIentry\fR \fB\-\-entry=\fR\fIentry\fR +\&\fB\-pie \-pthread \-r \-rdynamic +\&\-s \-static \-static\-pie \-static\-libgcc \-static\-libstdc++ +\&\-static\-libasan \-static\-libtsan \-static\-liblsan \-static\-libubsan +\&\-shared \-shared\-libgcc \-symbolic +\&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR +\&\fB\-u\fR \fIsymbol\fR \fB\-z\fR \fIkeyword\fR +.IP "\fIDirectory Options\fR" 4 +.IX Item "Directory Options" +\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-I\- +\&\-idirafter\fR \fIdir\fR +\&\fB\-imacros\fR \fIfile\fR \fB\-imultilib\fR \fIdir\fR +\&\fB\-iplugindir=\fR\fIdir\fR \fB\-iprefix\fR \fIfile\fR +\&\fB\-iquote\fR \fIdir\fR \fB\-isysroot\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR +\&\fB\-iwithprefix\fR \fIdir\fR \fB\-iwithprefixbefore\fR \fIdir\fR +\&\fB\-L\fR\fIdir\fR \fB\-no\-canonical\-prefixes \-\-no\-sysroot\-suffix +\&\-nostdinc \-nostdinc++ \-\-sysroot=\fR\fIdir\fR +.IP "\fICode Generation Options\fR" 4 +.IX Item "Code Generation Options" +\&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR +\&\fB\-ffixed\-\fR\fIreg\fR \fB\-fexceptions +\&\-fnon\-call\-exceptions \-fdelete\-dead\-exceptions \-funwind\-tables +\&\-fasynchronous\-unwind\-tables +\&\-fno\-gnu\-unique +\&\-finhibit\-size\-directive \-fno\-common \-fno\-ident +\&\-fpcc\-struct\-return \-fpic \-fPIC \-fpie \-fPIE \-fno\-plt +\&\-fno\-jump\-tables +\&\-frecord\-gcc\-switches +\&\-freg\-struct\-return \-fshort\-enums \-fshort\-wchar +\&\-fverbose\-asm \-fpack\-struct[=\fR\fIn\fR\fB] +\&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR +\&\fB\-fstack\-reuse=\fR\fIreuse_level\fR +\&\fB\-ftrampolines \-ftrapv \-fwrapv +\&\-fvisibility=\fR[\fBdefault\fR|\fBinternal\fR|\fBhidden\fR|\fBprotected\fR] +\&\fB\-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR +.IP "\fIDeveloper Options\fR" 4 +.IX Item "Developer Options" +\&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion +\&\-dumpfullversion \-fchecking \-fchecking=\fR\fIn\fR \fB\-fdbg\-cnt\-list +\&\-fdbg\-cnt=\fR\fIcounter-value-list\fR +\&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdisable\-tree\-\fR\fIpass_name\fR +\&\fB\-fdisable\-tree\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdump\-debug \-fdump\-earlydebug +\&\-fdump\-noaddr \-fdump\-unnumbered \-fdump\-unnumbered\-links +\&\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR] +\&\fB\-fdump\-ipa\-all \-fdump\-ipa\-cgraph \-fdump\-ipa\-inline +\&\-fdump\-lang\-all +\&\-fdump\-lang\-\fR\fIswitch\fR +\&\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR +\&\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR +\&\fB\-fdump\-passes +\&\-fdump\-rtl\-\fR\fIpass\fR \fB\-fdump\-rtl\-\fR\fIpass\fR\fB=\fR\fIfilename\fR +\&\fB\-fdump\-statistics +\&\-fdump\-tree\-all +\&\-fdump\-tree\-\fR\fIswitch\fR +\&\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR +\&\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR +\&\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR] \fB\-fcompare\-debug\-second +\&\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR +\&\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR +\&\fB\-fira\-verbose=\fR\fIn\fR +\&\fB\-flto\-report \-flto\-report\-wpa \-fmem\-report\-wpa +\&\-fmem\-report \-fpre\-ipa\-mem\-report \-fpost\-ipa\-mem\-report +\&\-fopt\-info \-fopt\-info\-\fR\fIoptions\fR[\fB=\fR\fIfile\fR] +\&\fB\-fprofile\-report +\&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR +\&\fB\-fsel\-sched\-verbose \-fsel\-sched\-dump\-cfg \-fsel\-sched\-pipelining\-verbose +\&\-fstats \-fstack\-usage \-ftime\-report \-ftime\-report\-details +\&\-fvar\-tracking\-assignments\-toggle \-gtoggle +\&\-print\-file\-name=\fR\fIlibrary\fR \fB\-print\-libgcc\-file\-name +\&\-print\-multi\-directory \-print\-multi\-lib \-print\-multi\-os\-directory +\&\-print\-prog\-name=\fR\fIprogram\fR \fB\-print\-search\-dirs \-Q +\&\-print\-sysroot \-print\-sysroot\-headers\-suffix +\&\-save\-temps \-save\-temps=cwd \-save\-temps=obj \-time\fR[\fB=\fR\fIfile\fR] +.IP "\fIMachine-Dependent Options\fR" 4 +.IX Item "Machine-Dependent Options" +\&\fIAArch64 Options\fR +\&\fB\-mabi=\fR\fIname\fR \fB\-mbig\-endian \-mlittle\-endian +\&\-mgeneral\-regs\-only +\&\-mcmodel=tiny \-mcmodel=small \-mcmodel=large +\&\-mstrict\-align \-mno\-strict\-align +\&\-momit\-leaf\-frame\-pointer +\&\-mtls\-dialect=desc \-mtls\-dialect=traditional +\&\-mtls\-size=\fR\fIsize\fR +\&\fB\-mfix\-cortex\-a53\-835769 \-mfix\-cortex\-a53\-843419 +\&\-mlow\-precision\-recip\-sqrt \-mlow\-precision\-sqrt \-mlow\-precision\-div +\&\-mpc\-relative\-literal\-loads +\&\-msign\-return\-address=\fR\fIscope\fR +\&\fB\-mbranch\-protection=\fR\fInone\fR\fB|\fR\fIstandard\fR\fB|\fR\fIpac-ret\fR\fB[+\fR\fIleaf\fR\fB]|\fR\fIbti\fR +\&\fB\-mharden\-sls=\fR\fIopts\fR +\&\fB\-march=\fR\fIname\fR \fB\-mcpu=\fR\fIname\fR \fB\-mtune=\fR\fIname\fR +\&\fB\-moverride=\fR\fIstring\fR \fB\-mverbose\-cost\-dump +\&\-mstack\-protector\-guard=\fR\fIguard\fR \fB\-mstack\-protector\-guard\-reg=\fR\fIsysreg\fR +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR \fB\-mtrack\-speculation +\&\-moutline\-atomics\fR +.Sp +\&\fIAdapteva Epiphany Options\fR +\&\fB\-mhalf\-reg\-file \-mprefer\-short\-insn\-regs +\&\-mbranch\-cost=\fR\fInum\fR \fB\-mcmove \-mnops=\fR\fInum\fR \fB\-msoft\-cmpsf +\&\-msplit\-lohi \-mpost\-inc \-mpost\-modify \-mstack\-offset=\fR\fInum\fR +\&\fB\-mround\-nearest \-mlong\-calls \-mshort\-calls \-msmall16 +\&\-mfp\-mode=\fR\fImode\fR \fB\-mvect\-double \-max\-vect\-align=\fR\fInum\fR +\&\fB\-msplit\-vecmove\-early \-m1reg\-\fR\fIreg\fR +.Sp +\&\fI\s-1AMD GCN\s0 Options\fR +\&\fB\-march=\fR\fIgpu\fR \fB\-mtune=\fR\fIgpu\fR \fB\-mstack\-size=\fR\fIbytes\fR +.Sp +\&\fI\s-1ARC\s0 Options\fR +\&\fB\-mbarrel\-shifter \-mjli\-always +\&\-mcpu=\fR\fIcpu\fR \fB\-mA6 \-mARC600 \-mA7 \-mARC700 +\&\-mdpfp \-mdpfp\-compact \-mdpfp\-fast \-mno\-dpfp\-lrsr +\&\-mea \-mno\-mpy \-mmul32x16 \-mmul64 \-matomic +\&\-mnorm \-mspfp \-mspfp\-compact \-mspfp\-fast \-msimd \-msoft\-float \-mswap +\&\-mcrc \-mdsp\-packa \-mdvbf \-mlock \-mmac\-d16 \-mmac\-24 \-mrtsc \-mswape +\&\-mtelephony \-mxy \-misize \-mannotate\-align \-marclinux \-marclinux_prof +\&\-mlong\-calls \-mmedium\-calls \-msdata \-mirq\-ctrl\-saved +\&\-mrgf\-banked\-regs \-mlpc\-width=\fR\fIwidth\fR \fB\-G\fR \fInum\fR +\&\fB\-mvolatile\-cache \-mtp\-regno=\fR\fIregno\fR +\&\fB\-malign\-call \-mauto\-modify\-reg \-mbbit\-peephole \-mno\-brcc +\&\-mcase\-vector\-pcrel \-mcompact\-casesi \-mno\-cond\-exec \-mearly\-cbranchsi +\&\-mexpand\-adddi \-mindexed\-loads \-mlra \-mlra\-priority\-none +\&\-mlra\-priority\-compact mlra-priority-noncompact \-mmillicode +\&\-mmixed\-code \-mq\-class \-mRcq \-mRcw \-msize\-level=\fR\fIlevel\fR +\&\fB\-mtune=\fR\fIcpu\fR \fB\-mmultcost=\fR\fInum\fR \fB\-mcode\-density\-frame +\&\-munalign\-prob\-threshold=\fR\fIprobability\fR \fB\-mmpy\-option=\fR\fImulto\fR +\&\fB\-mdiv\-rem \-mcode\-density \-mll64 \-mfpu=\fR\fIfpu\fR \fB\-mrf16 \-mbranch\-index\fR +.Sp +\&\fI\s-1ARM\s0 Options\fR +\&\fB\-mapcs\-frame \-mno\-apcs\-frame +\&\-mabi=\fR\fIname\fR +\&\fB\-mapcs\-stack\-check \-mno\-apcs\-stack\-check +\&\-mapcs\-reentrant \-mno\-apcs\-reentrant +\&\-mgeneral\-regs\-only +\&\-msched\-prolog \-mno\-sched\-prolog +\&\-mlittle\-endian \-mbig\-endian +\&\-mbe8 \-mbe32 +\&\-mfloat\-abi=\fR\fIname\fR +\&\fB\-mfp16\-format=\fR\fIname\fR +\&\fB\-mthumb\-interwork \-mno\-thumb\-interwork +\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR +\&\fB\-mtune=\fR\fIname\fR \fB\-mprint\-tune\-info +\&\-mstructure\-size\-boundary=\fR\fIn\fR +\&\fB\-mabort\-on\-noreturn +\&\-mlong\-calls \-mno\-long\-calls +\&\-msingle\-pic\-base \-mno\-single\-pic\-base +\&\-mpic\-register=\fR\fIreg\fR +\&\fB\-mnop\-fun\-dllimport +\&\-mpoke\-function\-name +\&\-mthumb \-marm \-mflip\-thumb +\&\-mtpcs\-frame \-mtpcs\-leaf\-frame +\&\-mcaller\-super\-interworking \-mcallee\-super\-interworking +\&\-mtp=\fR\fIname\fR \fB\-mtls\-dialect=\fR\fIdialect\fR +\&\fB\-mword\-relocations +\&\-mfix\-cortex\-m3\-ldrd +\&\-munaligned\-access +\&\-mneon\-for\-64bits +\&\-mslow\-flash\-data +\&\-masm\-syntax\-unified +\&\-mrestrict\-it +\&\-mverbose\-cost\-dump +\&\-mpure\-code +\&\-mcmse\fR +.Sp +\&\fI\s-1AVR\s0 Options\fR +\&\fB\-mmcu=\fR\fImcu\fR \fB\-mabsdata \-maccumulate\-args +\&\-mbranch\-cost=\fR\fIcost\fR +\&\fB\-mcall\-prologues \-mgas\-isr\-prologues \-mint8 +\&\-mn_flash=\fR\fIsize\fR \fB\-mno\-interrupts +\&\-mmain\-is\-OS_task \-mrelax \-mrmw \-mstrict\-X \-mtiny\-stack +\&\-mfract\-convert\-truncate +\&\-mshort\-calls \-nodevicelib \-nodevicespecs +\&\-Waddr\-space\-convert \-Wmisspelled\-isr\fR +.Sp +\&\fIBlackfin Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR] +\&\fB\-msim \-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer +\&\-mspecld\-anomaly \-mno\-specld\-anomaly \-mcsync\-anomaly \-mno\-csync\-anomaly +\&\-mlow\-64k \-mno\-low64k \-mstack\-check\-l1 \-mid\-shared\-library +\&\-mno\-id\-shared\-library \-mshared\-library\-id=\fR\fIn\fR +\&\fB\-mleaf\-id\-shared\-library \-mno\-leaf\-id\-shared\-library +\&\-msep\-data \-mno\-sep\-data \-mlong\-calls \-mno\-long\-calls +\&\-mfast\-fp \-minline\-plt \-mmulticore \-mcorea \-mcoreb \-msdram +\&\-micplb\fR +.Sp +\&\fIC6X Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian \-march=\fR\fIcpu\fR +\&\fB\-msim \-msdata=\fR\fIsdata-type\fR +.Sp +\&\fI\s-1CRIS\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR +\&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR +\&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects +\&\-mstack\-align \-mdata\-align \-mconst\-align +\&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt +\&\-melf \-maout \-melinux \-mlinux \-sim \-sim2 +\&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR +.Sp +\&\fI\s-1CR16\s0 Options\fR +\&\fB\-mmac +\&\-mcr16cplus \-mcr16c +\&\-msim \-mint32 \-mbit\-ops +\&\-mdata\-model=\fR\fImodel\fR +.Sp +\&\fIC\-SKY Options\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR +\&\fB\-mbig\-endian \-EB \-mlittle\-endian \-EL +\&\-mhard\-float \-msoft\-float \-mfpu=\fR\fIfpu\fR \fB\-mdouble\-float \-mfdivdu +\&\-melrw \-mistack \-mmp \-mcp \-mcache \-msecurity \-mtrust +\&\-mdsp \-medsp \-mvdsp +\&\-mdiv \-msmart \-mhigh\-registers \-manchor +\&\-mpushpop \-mmultiple\-stld \-mconstpool \-mstack\-size \-mccrt +\&\-mbranch\-cost=\fR\fIn\fR \fB\-mcse\-cc \-msched\-prolog\fR +.Sp +\&\fIDarwin Options\fR +\&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal +\&\-arch_only \-bind_at_load \-bundle \-bundle_loader +\&\-client_name \-compatibility_version \-current_version +\&\-dead_strip +\&\-dependency\-file \-dylib_file \-dylinker_install_name +\&\-dynamic \-dynamiclib \-exported_symbols_list +\&\-filelist \-flat_namespace \-force_cpusubtype_ALL +\&\-force_flat_namespace \-headerpad_max_install_names +\&\-iframework +\&\-image_base \-init \-install_name \-keep_private_externs +\&\-multi_module \-multiply_defined \-multiply_defined_unused +\&\-noall_load \-no_dead_strip_inits_and_terms +\&\-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit +\&\-pagezero_size \-prebind \-prebind_all_twolevel_modules +\&\-private_bundle \-read_only_relocs \-sectalign +\&\-sectobjectsymbols \-whyload \-seg1addr +\&\-sectcreate \-sectobjectsymbols \-sectorder +\&\-segaddr \-segs_read_only_addr \-segs_read_write_addr +\&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit +\&\-segprot \-segs_read_only_addr \-segs_read_write_addr +\&\-single_module \-static \-sub_library \-sub_umbrella +\&\-twolevel_namespace \-umbrella \-undefined +\&\-unexported_symbols_list \-weak_reference_mismatches +\&\-whatsloaded \-F \-gused \-gfull \-mmacosx\-version\-min=\fR\fIversion\fR +\&\fB\-mkernel \-mone\-byte\-bool\fR +.Sp +\&\fI\s-1DEC\s0 Alpha Options\fR +\&\fB\-mno\-fp\-regs \-msoft\-float +\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant +\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR +\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants +\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mbwx \-mmax \-mfix \-mcix +\&\-mfloat\-vax \-mfloat\-ieee +\&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data +\&\-msmall\-text \-mlarge\-text +\&\-mmemory\-latency=\fR\fItime\fR +.Sp +\&\fI\s-1FR30\s0 Options\fR +\&\fB\-msmall\-model \-mno\-lsim\fR +.Sp +\&\fI\s-1FT32\s0 Options\fR +\&\fB\-msim \-mlra \-mnodiv \-mft32b \-mcompress \-mnopm\fR +.Sp +\&\fI\s-1FRV\s0 Options\fR +\&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64 +\&\-mhard\-float \-msoft\-float +\&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword +\&\-mdouble \-mno\-double +\&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd +\&\-mfdpic \-minline\-plt \-mgprel\-ro \-multilib\-library\-pic +\&\-mlinked\-fp \-mlong\-calls \-malign\-labels +\&\-mlibrary\-pic \-macc\-4 \-macc\-8 +\&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move +\&\-moptimize\-membar \-mno\-optimize\-membar +\&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec +\&\-mvliw\-branch \-mno\-vliw\-branch +\&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec +\&\-mno\-nested\-cond\-exec \-mtomcat\-stats +\&\-mTLS \-mtls +\&\-mcpu=\fR\fIcpu\fR +.Sp +\&\fIGNU/Linux Options\fR +\&\fB\-mglibc \-muclibc \-mmusl \-mbionic \-mandroid +\&\-tno\-android\-cc \-tno\-android\-ld\fR +.Sp +\&\fIH8/300 Options\fR +\&\fB\-mrelax \-mh \-ms \-mn \-mexr \-mno\-exr \-mint32 \-malign\-300\fR +.Sp +\&\fI\s-1HPPA\s0 Options\fR +\&\fB\-march=\fR\fIarchitecture-type\fR +\&\fB\-mcaller\-copies \-mdisable\-fpregs \-mdisable\-indexing +\&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls +\&\-mlong\-load\-store \-mno\-disable\-fpregs +\&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas +\&\-mno\-jump\-in\-delay \-mno\-long\-load\-store +\&\-mno\-portable\-runtime \-mno\-soft\-float +\&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0 +\&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime +\&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio +\&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR +.Sp +\&\fI\s-1IA\-64\s0 Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic +\&\-mvolatile\-asm\-stop \-mregister\-names \-msdata \-mno\-sdata +\&\-mconstant\-gp \-mauto\-pic \-mfused\-madd +\&\-minline\-float\-divide\-min\-latency +\&\-minline\-float\-divide\-max\-throughput +\&\-mno\-inline\-float\-divide +\&\-minline\-int\-divide\-min\-latency +\&\-minline\-int\-divide\-max\-throughput +\&\-mno\-inline\-int\-divide +\&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput +\&\-mno\-inline\-sqrt +\&\-mdwarf2\-asm \-mearly\-stop\-bits +\&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-milp32 \-mlp64 +\&\-msched\-br\-data\-spec \-msched\-ar\-data\-spec \-msched\-control\-spec +\&\-msched\-br\-in\-data\-spec \-msched\-ar\-in\-data\-spec \-msched\-in\-control\-spec +\&\-msched\-spec\-ldc \-msched\-spec\-control\-ldc +\&\-msched\-prefer\-non\-data\-spec\-insns \-msched\-prefer\-non\-control\-spec\-insns +\&\-msched\-stop\-bits\-after\-every\-cycle \-msched\-count\-spec\-in\-critical\-path +\&\-msel\-sched\-dont\-check\-control\-spec \-msched\-fp\-mem\-deps\-zero\-cost +\&\-msched\-max\-memory\-insns\-hard\-limit \-msched\-max\-memory\-insns=\fR\fImax-insns\fR +.Sp +\&\fI\s-1LM32\s0 Options\fR +\&\fB\-mbarrel\-shift\-enabled \-mdivide\-enabled \-mmultiply\-enabled +\&\-msign\-extend\-enabled \-muser\-enabled\fR +.Sp +\&\fIM32R/D Options\fR +\&\fB\-m32r2 \-m32rx \-m32r +\&\-mdebug +\&\-malign\-loops \-mno\-align\-loops +\&\-missue\-rate=\fR\fInumber\fR +\&\fB\-mbranch\-cost=\fR\fInumber\fR +\&\fB\-mmodel=\fR\fIcode-size-model-type\fR +\&\fB\-msdata=\fR\fIsdata-type\fR +\&\fB\-mno\-flush\-func \-mflush\-func=\fR\fIname\fR +\&\fB\-mno\-flush\-trap \-mflush\-trap=\fR\fInumber\fR +\&\fB\-G\fR \fInum\fR +.Sp +\&\fIM32C Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-msim \-memregs=\fR\fInumber\fR +.Sp +\&\fIM680x0 Options\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR \fB\-mtune=\fR\fItune\fR +\&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040 +\&\-m68060 \-mcpu32 \-m5200 \-m5206e \-m528x \-m5307 \-m5407 +\&\-mcfv4e \-mbitfield \-mno\-bitfield \-mc68000 \-mc68020 +\&\-mnobitfield \-mrtd \-mno\-rtd \-mdiv \-mno\-div \-mshort +\&\-mno\-short \-mhard\-float \-m68881 \-msoft\-float \-mpcrel +\&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data +\&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library +\&\-mxgot \-mno\-xgot \-mlong\-jump\-table\-offsets\fR +.Sp +\&\fIMCore Options\fR +\&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates +\&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields +\&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data +\&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim +\&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR +.Sp +\&\fIMeP Options\fR +\&\fB\-mabsdiff \-mall\-opts \-maverage \-mbased=\fR\fIn\fR \fB\-mbitops +\&\-mc=\fR\fIn\fR \fB\-mclip \-mconfig=\fR\fIname\fR \fB\-mcop \-mcop32 \-mcop64 \-mivc2 +\&\-mdc \-mdiv \-meb \-mel \-mio\-volatile \-ml \-mleadz \-mm \-mminmax +\&\-mmult \-mno\-opts \-mrepeat \-ms \-msatur \-msdram \-msim \-msimnovec \-mtf +\&\-mtiny=\fR\fIn\fR +.Sp +\&\fIMicroBlaze Options\fR +\&\fB\-msoft\-float \-mhard\-float \-msmall\-divides \-mcpu=\fR\fIcpu\fR +\&\fB\-mmemcpy \-mxl\-soft\-mul \-mxl\-soft\-div \-mxl\-barrel\-shift +\&\-mxl\-pattern\-compare \-mxl\-stack\-check \-mxl\-gp\-opt \-mno\-clearbss +\&\-mxl\-multiply\-high \-mxl\-float\-convert \-mxl\-float\-sqrt +\&\-mbig\-endian \-mlittle\-endian \-mxl\-reorder \-mxl\-mode\-\fR\fIapp-model\fR +\&\fB\-mpic\-data\-is\-text\-relative\fR +.Sp +\&\fI\s-1MIPS\s0 Options\fR +\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR +\&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 \-mips32r3 \-mips32r5 +\&\-mips32r6 \-mips64 \-mips64r2 \-mips64r3 \-mips64r5 \-mips64r6 +\&\-mips16 \-mno\-mips16 \-mflip\-mips16 +\&\-minterlink\-compressed \-mno\-interlink\-compressed +\&\-minterlink\-mips16 \-mno\-interlink\-mips16 +\&\-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls +\&\-mshared \-mno\-shared \-mplt \-mno\-plt \-mxgot \-mno\-xgot +\&\-mgp32 \-mgp64 \-mfp32 \-mfpxx \-mfp64 \-mhard\-float \-msoft\-float +\&\-mno\-float \-msingle\-float \-mdouble\-float +\&\-modd\-spreg \-mno\-odd\-spreg +\&\-mabs=\fR\fImode\fR \fB\-mnan=\fR\fIencoding\fR +\&\fB\-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2 +\&\-mmcu \-mmno\-mcu +\&\-meva \-mno\-eva +\&\-mvirt \-mno\-virt +\&\-mxpa \-mno\-xpa +\&\-mcrc \-mno\-crc +\&\-mginv \-mno\-ginv +\&\-mmicromips \-mno\-micromips +\&\-mmsa \-mno\-msa +\&\-mloongson\-mmi \-mno\-loongson\-mmi +\&\-mloongson\-ext \-mno\-loongson\-ext +\&\-mloongson\-ext2 \-mno\-loongson\-ext2 +\&\-mfpu=\fR\fIfpu-type\fR +\&\fB\-msmartmips \-mno\-smartmips +\&\-mpaired\-single \-mno\-paired\-single \-mdmx \-mno\-mdmx +\&\-mips3d \-mno\-mips3d \-mmt \-mno\-mt \-mllsc \-mno\-llsc +\&\-mlong64 \-mlong32 \-msym32 \-mno\-sym32 +\&\-G\fR\fInum\fR \fB\-mlocal\-sdata \-mno\-local\-sdata +\&\-mextern\-sdata \-mno\-extern\-sdata \-mgpopt \-mno\-gopt +\&\-membedded\-data \-mno\-embedded\-data +\&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata +\&\-mcode\-readable=\fR\fIsetting\fR +\&\fB\-msplit\-addresses \-mno\-split\-addresses +\&\-mexplicit\-relocs \-mno\-explicit\-relocs +\&\-mcheck\-zero\-division \-mno\-check\-zero\-division +\&\-mdivide\-traps \-mdivide\-breaks +\&\-mload\-store\-pairs \-mno\-load\-store\-pairs +\&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls +\&\-mmad \-mno\-mad \-mimadd \-mno\-imadd \-mfused\-madd \-mno\-fused\-madd \-nocpp +\&\-mfix\-24k \-mno\-fix\-24k +\&\-mfix\-r4000 \-mno\-fix\-r4000 \-mfix\-r4400 \-mno\-fix\-r4400 +\&\-mfix\-r5900 \-mno\-fix\-r5900 +\&\-mfix\-r10000 \-mno\-fix\-r10000 \-mfix\-rm7000 \-mno\-fix\-rm7000 +\&\-mfix\-vr4120 \-mno\-fix\-vr4120 +\&\-mfix\-vr4130 \-mno\-fix\-vr4130 \-mfix\-sb1 \-mno\-fix\-sb1 +\&\-mflush\-func=\fR\fIfunc\fR \fB\-mno\-flush\-func +\&\-mbranch\-cost=\fR\fInum\fR \fB\-mbranch\-likely \-mno\-branch\-likely +\&\-mcompact\-branches=\fR\fIpolicy\fR +\&\fB\-mfp\-exceptions \-mno\-fp\-exceptions +\&\-mvr4130\-align \-mno\-vr4130\-align \-msynci \-mno\-synci +\&\-mlxc1\-sxc1 \-mno\-lxc1\-sxc1 \-mmadd4 \-mno\-madd4 +\&\-mrelax\-pic\-calls \-mno\-relax\-pic\-calls \-mmcount\-ra\-address +\&\-mframe\-header\-opt \-mno\-frame\-header\-opt\fR +.Sp +\&\fI\s-1MMIX\s0 Options\fR +\&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu +\&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols +\&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses +\&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR +.Sp +\&\fI\s-1MN10300\s0 Options\fR +\&\fB\-mmult\-bug \-mno\-mult\-bug +\&\-mno\-am33 \-mam33 \-mam33\-2 \-mam34 +\&\-mtune=\fR\fIcpu-type\fR +\&\fB\-mreturn\-pointer\-on\-d0 +\&\-mno\-crt0 \-mrelax \-mliw \-msetlb\fR +.Sp +\&\fIMoxie Options\fR +\&\fB\-meb \-mel \-mmul.x \-mno\-crt0\fR +.Sp +\&\fI\s-1MSP430\s0 Options\fR +\&\fB\-msim \-masm\-hex \-mmcu= \-mcpu= \-mlarge \-msmall \-mrelax +\&\-mwarn\-mcu +\&\-mcode\-region= \-mdata\-region= +\&\-msilicon\-errata= \-msilicon\-errata\-warn= +\&\-mhwmult= \-minrt\fR +.Sp +\&\fI\s-1NDS32\s0 Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian +\&\-mreduced\-regs \-mfull\-regs +\&\-mcmov \-mno\-cmov +\&\-mext\-perf \-mno\-ext\-perf +\&\-mext\-perf2 \-mno\-ext\-perf2 +\&\-mext\-string \-mno\-ext\-string +\&\-mv3push \-mno\-v3push +\&\-m16bit \-mno\-16bit +\&\-misr\-vector\-size=\fR\fInum\fR +\&\fB\-mcache\-block\-size=\fR\fInum\fR +\&\fB\-march=\fR\fIarch\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mctor\-dtor \-mrelax\fR +.Sp +\&\fINios \s-1II\s0 Options\fR +\&\fB\-G\fR \fInum\fR \fB\-mgpopt=\fR\fIoption\fR \fB\-mgpopt \-mno\-gpopt +\&\-mgprel\-sec=\fR\fIregexp\fR \fB\-mr0rel\-sec=\fR\fIregexp\fR +\&\fB\-mel \-meb +\&\-mno\-bypass\-cache \-mbypass\-cache +\&\-mno\-cache\-volatile \-mcache\-volatile +\&\-mno\-fast\-sw\-div \-mfast\-sw\-div +\&\-mhw\-mul \-mno\-hw\-mul \-mhw\-mulx \-mno\-hw\-mulx \-mno\-hw\-div \-mhw\-div +\&\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR \fB\-mno\-custom\-\fR\fIinsn\fR +\&\fB\-mcustom\-fpu\-cfg=\fR\fIname\fR +\&\fB\-mhal \-msmallc \-msys\-crt0=\fR\fIname\fR \fB\-msys\-lib=\fR\fIname\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mbmx \-mno\-bmx \-mcdx \-mno\-cdx\fR +.Sp +\&\fINvidia \s-1PTX\s0 Options\fR +\&\fB\-m32 \-m64 \-mmainkernel \-moptimize\fR +.Sp +\&\fIOpenRISC Options\fR +\&\fB\-mboard=\fR\fIname\fR \fB\-mnewlib \-mhard\-mul \-mhard\-div +\&\-msoft\-mul \-msoft\-div +\&\-mcmov \-mror \-msext \-msfimm \-mshftimm\fR +.Sp +\&\fI\s-1PDP\-11\s0 Options\fR +\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10 +\&\-mint32 \-mno\-int16 \-mint16 \-mno\-int32 +\&\-msplit \-munix\-asm \-mdec\-asm \-mgnu\-asm \-mlra\fR +.Sp +\&\fIpicoChip Options\fR +\&\fB\-mae=\fR\fIae_type\fR \fB\-mvliw\-lookahead=\fR\fIN\fR +\&\fB\-msymbol\-as\-address \-mno\-inefficient\-warnings\fR +.Sp +\&\fIPowerPC Options\fR +See \s-1RS/6000\s0 and PowerPC Options. +.Sp +\&\fIRISC-V Options\fR +\&\fB\-mbranch\-cost=\fR\fIN\-instruction\fR +\&\fB\-mplt \-mno\-plt +\&\-mabi=\fR\fIABI-string\fR +\&\fB\-mfdiv \-mno\-fdiv +\&\-mdiv \-mno\-div +\&\-march=\fR\fIISA-string\fR +\&\fB\-mtune=\fR\fIprocessor-string\fR +\&\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-msmall\-data\-limit=\fR\fIN\-bytes\fR +\&\fB\-msave\-restore \-mno\-save\-restore +\&\-mstrict\-align \-mno\-strict\-align +\&\-mcmodel=medlow \-mcmodel=medany +\&\-mexplicit\-relocs \-mno\-explicit\-relocs +\&\-mrelax \-mno\-relax +\&\-mriscv\-attribute \-mmo\-riscv\-attribute\fR +.Sp +\&\fI\s-1RL78\s0 Options\fR +\&\fB\-msim \-mmul=none \-mmul=g13 \-mmul=g14 \-mallregs +\&\-mcpu=g10 \-mcpu=g13 \-mcpu=g14 \-mg10 \-mg13 \-mg14 +\&\-m64bit\-doubles \-m32bit\-doubles \-msave\-mduc\-in\-interrupts\fR +.Sp +\&\fI\s-1RS/6000\s0 and PowerPC Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mpowerpc64 +\&\-maltivec \-mno\-altivec +\&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt +\&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt +\&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mpopcntd \-mno\-popcntd +\&\-mfprnd \-mno\-fprnd +\&\-mcmpb \-mno\-cmpb \-mmfpgpr \-mno\-mfpgpr \-mhard\-dfp \-mno\-hard\-dfp +\&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc +\&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe +\&\-malign\-power \-malign\-natural +\&\-msoft\-float \-mhard\-float \-mmultiple \-mno\-multiple +\&\-mupdate \-mno\-update +\&\-mavoid\-indexed\-addresses \-mno\-avoid\-indexed\-addresses +\&\-mfused\-madd \-mno\-fused\-madd \-mbit\-align \-mno\-bit\-align +\&\-mstrict\-align \-mno\-strict\-align \-mrelocatable +\&\-mno\-relocatable \-mrelocatable\-lib \-mno\-relocatable\-lib +\&\-mtoc \-mno\-toc \-mlittle \-mlittle\-endian \-mbig \-mbig\-endian +\&\-mdynamic\-no\-pic \-mswdiv \-msingle\-pic\-base +\&\-mprioritize\-restricted\-insns=\fR\fIpriority\fR +\&\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR +\&\fB\-minsert\-sched\-nops=\fR\fIscheme\fR +\&\fB\-mcall\-aixdesc \-mcall\-eabi \-mcall\-freebsd +\&\-mcall\-linux \-mcall\-netbsd \-mcall\-openbsd +\&\-mcall\-sysv \-mcall\-sysv\-eabi \-mcall\-sysv\-noeabi +\&\-mtraceback=\fR\fItraceback_type\fR +\&\fB\-maix\-struct\-return \-msvr4\-struct\-return +\&\-mabi=\fR\fIabi-type\fR \fB\-msecure\-plt \-mbss\-plt +\&\-mlongcall \-mno\-longcall \-mpltseq \-mno\-pltseq +\&\-mblock\-move\-inline\-limit=\fR\fInum\fR +\&\fB\-mblock\-compare\-inline\-limit=\fR\fInum\fR +\&\fB\-mblock\-compare\-inline\-loop\-limit=\fR\fInum\fR +\&\fB\-mstring\-compare\-inline\-limit=\fR\fInum\fR +\&\fB\-misel \-mno\-isel +\&\-mvrsave \-mno\-vrsave +\&\-mmulhw \-mno\-mulhw +\&\-mdlmzb \-mno\-dlmzb +\&\-mprototype \-mno\-prototype +\&\-msim \-mmvme \-mads \-myellowknife \-memb \-msdata +\&\-msdata=\fR\fIopt\fR \fB\-mreadonly\-in\-sdata \-mvxworks \-G\fR \fInum\fR +\&\fB\-mrecip \-mrecip=\fR\fIopt\fR \fB\-mno\-recip \-mrecip\-precision +\&\-mno\-recip\-precision +\&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz +\&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mhtm \-mno\-htm +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm +\&\-mfloat128 \-mno\-float128 \-mfloat128\-hardware \-mno\-float128\-hardware +\&\-mgnu\-attribute \-mno\-gnu\-attribute +\&\-mstack\-protector\-guard=\fR\fIguard\fR \fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR +.Sp +\&\fI\s-1RX\s0 Options\fR +\&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu +\&\-mcpu= +\&\-mbig\-endian\-data \-mlittle\-endian\-data +\&\-msmall\-data +\&\-msim \-mno\-sim +\&\-mas100\-syntax \-mno\-as100\-syntax +\&\-mrelax +\&\-mmax\-constant\-size= +\&\-mint\-register= +\&\-mpid +\&\-mallow\-string\-insns \-mno\-allow\-string\-insns +\&\-mjsr +\&\-mno\-warn\-multiple\-fast\-interrupts +\&\-msave\-acc\-in\-interrupts\fR +.Sp +\&\fIS/390 and zSeries Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mhard\-float \-msoft\-float \-mhard\-dfp \-mno\-hard\-dfp +\&\-mlong\-double\-64 \-mlong\-double\-128 +\&\-mbackchain \-mno\-backchain \-mpacked\-stack \-mno\-packed\-stack +\&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle +\&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch +\&\-mhtm \-mvx \-mzvector +\&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch=\fR\fIhalfwords\fR\fB,\fR\fIhalfwords\fR +.Sp +\&\fIScore Options\fR +\&\fB\-meb \-mel +\&\-mnhwloop +\&\-muls +\&\-mmac +\&\-mscore5 \-mscore5u \-mscore7 \-mscore7d\fR +.Sp +\&\fI\s-1SH\s0 Options\fR +\&\fB\-m1 \-m2 \-m2e +\&\-m2a\-nofpu \-m2a\-single\-only \-m2a\-single \-m2a +\&\-m3 \-m3e +\&\-m4\-nofpu \-m4\-single\-only \-m4\-single \-m4 +\&\-m4a\-nofpu \-m4a\-single\-only \-m4a\-single \-m4a \-m4al +\&\-mb \-ml \-mdalign \-mrelax +\&\-mbigtable \-mfmovd \-mrenesas \-mno\-renesas \-mnomacsave +\&\-mieee \-mno\-ieee \-mbitops \-misize \-minline\-ic_invalidate \-mpadstruct +\&\-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR +\&\fB\-mdivsi3_libfunc=\fR\fIname\fR \fB\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-maccumulate\-outgoing\-args +\&\-matomic\-model=\fR\fIatomic-model\fR +\&\fB\-mbranch\-cost=\fR\fInum\fR \fB\-mzdcbranch \-mno\-zdcbranch +\&\-mcbranch\-force\-delay\-slot +\&\-mfused\-madd \-mno\-fused\-madd \-mfsca \-mno\-fsca \-mfsrra \-mno\-fsrra +\&\-mpretend\-cmove \-mtas\fR +.Sp +\&\fISolaris 2 Options\fR +\&\fB\-mclear\-hwcap \-mno\-clear\-hwcap \-mimpure\-text \-mno\-impure\-text +\&\-pthreads\fR +.Sp +\&\fI\s-1SPARC\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mmemory\-model=\fR\fImem-model\fR +\&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs +\&\-mfaster\-structs \-mno\-faster\-structs \-mflat \-mno\-flat +\&\-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float +\&\-mhard\-quad\-float \-msoft\-quad\-float +\&\-mstack\-bias \-mno\-stack\-bias +\&\-mstd\-struct\-return \-mno\-std\-struct\-return +\&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode +\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis +\&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 +\&\-mvis4 \-mno\-vis4 \-mvis4b \-mno\-vis4b +\&\-mcbcond \-mno\-cbcond \-mfmaf \-mno\-fmaf \-mfsmuld \-mno\-fsmuld +\&\-mpopc \-mno\-popc \-msubxc \-mno\-subxc +\&\-mfix\-at697f \-mfix\-ut699 \-mfix\-ut700 \-mfix\-gr712rc +\&\-mlra \-mno\-lra\fR +.Sp +\&\fI\s-1SPU\s0 Options\fR +\&\fB\-mwarn\-reloc \-merror\-reloc +\&\-msafe\-dma \-munsafe\-dma +\&\-mbranch\-hints +\&\-msmall\-mem \-mlarge\-mem \-mstdmain +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mea32 \-mea64 +\&\-maddress\-space\-conversion \-mno\-address\-space\-conversion +\&\-mcache\-size=\fR\fIcache-size\fR +\&\fB\-matomic\-updates \-mno\-atomic\-updates\fR +.Sp +\&\fISystem V Options\fR +\&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR +.Sp +\&\fITILE-Gx Options\fR +\&\fB\-mcpu=CPU \-m32 \-m64 \-mbig\-endian \-mlittle\-endian +\&\-mcmodel=\fR\fIcode-model\fR +.Sp +\&\fITILEPro Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32\fR +.Sp +\&\fIV850 Options\fR +\&\fB\-mlong\-calls \-mno\-long\-calls \-mep \-mno\-ep +\&\-mprolog\-function \-mno\-prolog\-function \-mspace +\&\-mtda=\fR\fIn\fR \fB\-msda=\fR\fIn\fR \fB\-mzda=\fR\fIn\fR +\&\fB\-mapp\-regs \-mno\-app\-regs +\&\-mdisable\-callt \-mno\-disable\-callt +\&\-mv850e2v3 \-mv850e2 \-mv850e1 \-mv850es +\&\-mv850e \-mv850 \-mv850e3v5 +\&\-mloop +\&\-mrelax +\&\-mlong\-jumps +\&\-msoft\-float +\&\-mhard\-float +\&\-mgcc\-abi +\&\-mrh850\-abi +\&\-mbig\-switch\fR +.Sp +\&\fI\s-1VAX\s0 Options\fR +\&\fB\-mg \-mgnu \-munix\fR +.Sp +\&\fIVisium Options\fR +\&\fB\-mdebug \-msim \-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float +\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR \fB\-msv\-mode \-muser\-mode\fR +.Sp +\&\fI\s-1VMS\s0 Options\fR +\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64 +\&\-mpointer\-size=\fR\fIsize\fR +.Sp +\&\fIVxWorks Options\fR +\&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic +\&\-Xbind\-lazy \-Xbind\-now\fR +.Sp +\&\fIx86 Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR \fB\-mdump\-tune\-features \-mno\-default +\&\-mfpmath=\fR\fIunit\fR +\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 +\&\-mno\-fp\-ret\-in\-387 \-m80387 \-mhard\-float \-msoft\-float +\&\-mno\-wide\-multiply \-mrtd \-malign\-double +\&\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR +\&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 +\&\-mrecip \-mrecip=\fR\fIopt\fR +\&\fB\-mvzeroupper \-mprefer\-avx128 \-mprefer\-vector\-width=\fR\fIopt\fR +\&\fB\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx +\&\-mavx2 \-mavx512f \-mavx512pf \-mavx512er \-mavx512cd \-mavx512vl +\&\-mavx512bw \-mavx512dq \-mavx512ifma \-mavx512vbmi \-msha \-maes +\&\-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfma \-mpconfig \-mwbnoinvd +\&\-mptwrite \-mprefetchwt1 \-mclflushopt \-mclwb \-mxsavec \-mxsaves +\&\-msse4a \-m3dnow \-m3dnowa \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop +\&\-madx \-mlzcnt \-mbmi2 \-mfxsr \-mxsave \-mxsaveopt \-mrtm \-mhle \-mlwp +\&\-mmwaitx \-mclzero \-mpku \-mthreads \-mgfni \-mvaes \-mwaitpkg +\&\-mshstk \-mmanual\-endbr \-mforce\-indirect\-call \-mavx512vbmi2 +\&\-mvpclmulqdq \-mavx512bitalg \-mmovdiri \-mmovdir64b \-mavx512vpopcntdq +\&\-mavx5124fmaps \-mavx512vnni \-mavx5124vnniw \-mprfchw \-mrdpid +\&\-mrdseed \-msgx +\&\-mcldemote \-mms\-bitfields \-mno\-align\-stringops \-minline\-all\-stringops +\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR +\&\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR \fB\-mmemset\-strategy=\fR\fIstrategy\fR +\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double +\&\-m96bit\-long\-double \-mlong\-double\-64 \-mlong\-double\-80 \-mlong\-double\-128 +\&\-mregparm=\fR\fInum\fR \fB\-msseregparm +\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem +\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign +\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs +\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR \fB\-maddress\-mode=\fR\fImode\fR +\&\fB\-m32 \-m64 \-mx32 \-m16 \-miamcu \-mlarge\-data\-threshold=\fR\fInum\fR +\&\fB\-msse2avx \-mfentry \-mrecord\-mcount \-mnop\-mcount \-m8bit\-idiv +\&\-minstrument\-return=\fR\fItype\fR \fB\-mfentry\-name=\fR\fIname\fR \fB\-mfentry\-section=\fR\fIname\fR +\&\fB\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store +\&\-malign\-data=\fR\fItype\fR \fB\-mstack\-protector\-guard=\fR\fIguard\fR +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR +\&\fB\-mstack\-protector\-guard\-symbol=\fR\fIsymbol\fR +\&\fB\-mgeneral\-regs\-only \-mcall\-ms2sysv\-xlogues +\&\-mindirect\-branch=\fR\fIchoice\fR \fB\-mfunction\-return=\fR\fIchoice\fR +\&\fB\-mindirect\-branch\-register\fR +.Sp +\&\fIx86 Windows Options\fR +\&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll +\&\-mnop\-fun\-dllimport \-mthread +\&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR +.Sp +\&\fIXstormy16 Options\fR +\&\fB\-msim\fR +.Sp +\&\fIXtensa Options\fR +\&\fB\-mconst16 \-mno\-const16 +\&\-mfused\-madd \-mno\-fused\-madd +\&\-mforce\-no\-pic +\&\-mserialize\-volatile \-mno\-serialize\-volatile +\&\-mtext\-section\-literals \-mno\-text\-section\-literals +\&\-mauto\-litpools \-mno\-auto\-litpools +\&\-mtarget\-align \-mno\-target\-align +\&\-mlongcalls \-mno\-longcalls\fR +.Sp +\&\fIzSeries Options\fR +See S/390 and zSeries Options. +.SS "Options Controlling the Kind of Output" +.IX Subsection "Options Controlling the Kind of Output" +Compilation can involve up to four stages: preprocessing, compilation +proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of +preprocessing and compiling several files either into several +assembler input files, or into one assembler input file; then each +assembler input file produces an object file, and linking combines all +the object files (those newly compiled, and those specified as input) +into an executable file. +.PP +For any given input file, the file name suffix determines what kind of +compilation is done: +.IP "\fIfile\fR\fB.c\fR" 4 +.IX Item "file.c" +C source code that must be preprocessed. +.IP "\fIfile\fR\fB.i\fR" 4 +.IX Item "file.i" +C source code that should not be preprocessed. +.IP "\fIfile\fR\fB.ii\fR" 4 +.IX Item "file.ii" +\&\*(C+ source code that should not be preprocessed. +.IP "\fIfile\fR\fB.m\fR" 4 +.IX Item "file.m" +Objective-C source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective-C program work. +.IP "\fIfile\fR\fB.mi\fR" 4 +.IX Item "file.mi" +Objective-C source code that should not be preprocessed. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective\-\*(C+ program work. Note that \fB.M\fR refers +to a literal capital M. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code that should not be preprocessed. +.IP "\fIfile\fR\fB.h\fR" 4 +.IX Item "file.h" +C, \*(C+, Objective-C or Objective\-\*(C+ header file to be turned into a +precompiled header (default), or C, \*(C+ header file to be turned into an +Ada spec (via the \fB\-fdump\-ada\-spec\fR switch). +.IP "\fIfile\fR\fB.cc\fR" 4 +.IX Item "file.cc" +.PD 0 +.IP "\fIfile\fR\fB.cp\fR" 4 +.IX Item "file.cp" +.IP "\fIfile\fR\fB.cxx\fR" 4 +.IX Item "file.cxx" +.IP "\fIfile\fR\fB.cpp\fR" 4 +.IX Item "file.cpp" +.IP "\fIfile\fR\fB.CPP\fR" 4 +.IX Item "file.CPP" +.IP "\fIfile\fR\fB.c++\fR" 4 +.IX Item "file.c++" +.IP "\fIfile\fR\fB.C\fR" 4 +.IX Item "file.C" +.PD +\&\*(C+ source code that must be preprocessed. Note that in \fB.cxx\fR, +the last two letters must both be literally \fBx\fR. Likewise, +\&\fB.C\fR refers to a literal capital C. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code that must be preprocessed. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code that should not be preprocessed. +.IP "\fIfile\fR\fB.hh\fR" 4 +.IX Item "file.hh" +.PD 0 +.IP "\fIfile\fR\fB.H\fR" 4 +.IX Item "file.H" +.IP "\fIfile\fR\fB.hp\fR" 4 +.IX Item "file.hp" +.IP "\fIfile\fR\fB.hxx\fR" 4 +.IX Item "file.hxx" +.IP "\fIfile\fR\fB.hpp\fR" 4 +.IX Item "file.hpp" +.IP "\fIfile\fR\fB.HPP\fR" 4 +.IX Item "file.HPP" +.IP "\fIfile\fR\fB.h++\fR" 4 +.IX Item "file.h++" +.IP "\fIfile\fR\fB.tcc\fR" 4 +.IX Item "file.tcc" +.PD +\&\*(C+ header file to be turned into a precompiled header or Ada spec. +.IP "\fIfile\fR\fB.f\fR" 4 +.IX Item "file.f" +.PD 0 +.IP "\fIfile\fR\fB.for\fR" 4 +.IX Item "file.for" +.IP "\fIfile\fR\fB.ftn\fR" 4 +.IX Item "file.ftn" +.PD +Fixed form Fortran source code that should not be preprocessed. +.IP "\fIfile\fR\fB.F\fR" 4 +.IX Item "file.F" +.PD 0 +.IP "\fIfile\fR\fB.FOR\fR" 4 +.IX Item "file.FOR" +.IP "\fIfile\fR\fB.fpp\fR" 4 +.IX Item "file.fpp" +.IP "\fIfile\fR\fB.FPP\fR" 4 +.IX Item "file.FPP" +.IP "\fIfile\fR\fB.FTN\fR" 4 +.IX Item "file.FTN" +.PD +Fixed form Fortran source code that must be preprocessed (with the traditional +preprocessor). +.IP "\fIfile\fR\fB.f90\fR" 4 +.IX Item "file.f90" +.PD 0 +.IP "\fIfile\fR\fB.f95\fR" 4 +.IX Item "file.f95" +.IP "\fIfile\fR\fB.f03\fR" 4 +.IX Item "file.f03" +.IP "\fIfile\fR\fB.f08\fR" 4 +.IX Item "file.f08" +.PD +Free form Fortran source code that should not be preprocessed. +.IP "\fIfile\fR\fB.F90\fR" 4 +.IX Item "file.F90" +.PD 0 +.IP "\fIfile\fR\fB.F95\fR" 4 +.IX Item "file.F95" +.IP "\fIfile\fR\fB.F03\fR" 4 +.IX Item "file.F03" +.IP "\fIfile\fR\fB.F08\fR" 4 +.IX Item "file.F08" +.PD +Free form Fortran source code that must be preprocessed (with the +traditional preprocessor). +.IP "\fIfile\fR\fB.go\fR" 4 +.IX Item "file.go" +Go source code. +.IP "\fIfile\fR\fB.brig\fR" 4 +.IX Item "file.brig" +\&\s-1BRIG\s0 files (binary representation of \s-1HSAIL\s0). +.IP "\fIfile\fR\fB.d\fR" 4 +.IX Item "file.d" +D source code. +.IP "\fIfile\fR\fB.di\fR" 4 +.IX Item "file.di" +D interface file. +.IP "\fIfile\fR\fB.dd\fR" 4 +.IX Item "file.dd" +D documentation code (Ddoc). +.IP "\fIfile\fR\fB.ads\fR" 4 +.IX Item "file.ads" +Ada source code file that contains a library unit declaration (a +declaration of a package, subprogram, or generic, or a generic +instantiation), or a library unit renaming declaration (a package, +generic, or subprogram renaming declaration). Such files are also +called \fIspecs\fR. +.IP "\fIfile\fR\fB.adb\fR" 4 +.IX Item "file.adb" +Ada source code file containing a library unit body (a subprogram or +package body). Such files are also called \fIbodies\fR. +.IP "\fIfile\fR\fB.s\fR" 4 +.IX Item "file.s" +Assembler code. +.IP "\fIfile\fR\fB.S\fR" 4 +.IX Item "file.S" +.PD 0 +.IP "\fIfile\fR\fB.sx\fR" 4 +.IX Item "file.sx" +.PD +Assembler code that must be preprocessed. +.IP "\fIother\fR" 4 +.IX Item "other" +An object file to be fed straight into linking. +Any file name with no recognized suffix is treated this way. +.PP +You can specify the input language explicitly with the \fB\-x\fR option: +.IP "\fB\-x\fR \fIlanguage\fR" 4 +.IX Item "-x language" +Specify explicitly the \fIlanguage\fR for the following input files +(rather than letting the compiler choose a default based on the file +name suffix). This option applies to all following input files until +the next \fB\-x\fR option. Possible values for \fIlanguage\fR are: +.Sp +.Vb 10 +\& c c\-header cpp\-output +\& c++ c++\-header c++\-cpp\-output +\& objective\-c objective\-c\-header objective\-c\-cpp\-output +\& objective\-c++ objective\-c++\-header objective\-c++\-cpp\-output +\& assembler assembler\-with\-cpp +\& ada +\& d +\& f77 f77\-cpp\-input f95 f95\-cpp\-input +\& go +\& brig +.Ve +.IP "\fB\-x none\fR" 4 +.IX Item "-x none" +Turn off any specification of a language, so that subsequent files are +handled according to their file name suffixes (as they are if \fB\-x\fR +has not been used at all). +.PP +If you only want some of the stages of compilation, you can use +\&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and +one of the options \fB\-c\fR, \fB\-S\fR, or \fB\-E\fR to say where +\&\fBgcc\fR is to stop. Note that some combinations (for example, +\&\fB\-x cpp-output \-E\fR) instruct \fBgcc\fR to do nothing at all. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +Compile or assemble the source files, but do not link. The linking +stage simply is not done. The ultimate output is in the form of an +object file for each source file. +.Sp +By default, the object file name for a source file is made by replacing +the suffix \fB.c\fR, \fB.i\fR, \fB.s\fR, etc., with \fB.o\fR. +.Sp +Unrecognized input files, not requiring compilation or assembly, are +ignored. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +Stop after the stage of compilation proper; do not assemble. The output +is in the form of an assembler code file for each non-assembler input +file specified. +.Sp +By default, the assembler file name for a source file is made by +replacing the suffix \fB.c\fR, \fB.i\fR, etc., with \fB.s\fR. +.Sp +Input files that don't require compilation are ignored. +.IP "\fB\-E\fR" 4 +.IX Item "-E" +Stop after the preprocessing stage; do not run the compiler proper. The +output is in the form of preprocessed source code, which is sent to the +standard output. +.Sp +Input files that don't require preprocessing are ignored. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Place output in file \fIfile\fR. This applies to whatever +sort of output is being produced, whether it be an executable file, +an object file, an assembler file or preprocessed C code. +.Sp +If \fB\-o\fR is not specified, the default is to put an executable +file in \fIa.out\fR, the object file for +\&\fI\fIsource\fI.\fIsuffix\fI\fR in \fI\fIsource\fI.o\fR, its +assembler file in \fI\fIsource\fI.s\fR, a precompiled header file in +\&\fI\fIsource\fI.\fIsuffix\fI.gch\fR, and all preprocessed C source on +standard output. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Print (on standard error output) the commands executed to run the stages +of compilation. Also print the version number of the compiler driver +program and of the preprocessor and the compiler proper. +.IP "\fB\-###\fR" 4 +.IX Item "-###" +Like \fB\-v\fR except the commands are not executed and arguments +are quoted unless they contain only alphanumeric characters or \f(CW\*(C`./\-_\*(C'\fR. +This is useful for shell scripts to capture the driver-generated command lines. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print (on the standard output) a description of the command-line options +understood by \fBgcc\fR. If the \fB\-v\fR option is also specified +then \fB\-\-help\fR is also passed on to the various processes +invoked by \fBgcc\fR, so that they can display the command-line options +they accept. If the \fB\-Wextra\fR option has also been specified +(prior to the \fB\-\-help\fR option), then command-line options that +have no documentation associated with them are also displayed. +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +Print (on the standard output) a description of target-specific command-line +options for each tool. For some targets extra target-specific +information may also be printed. +.IP "\fB\-\-help={\fR\fIclass\fR|[\fB^\fR]\fIqualifier\fR\fB}\fR[\fB,...\fR]" 4 +.IX Item "--help={class|[^]qualifier}[,...]" +Print (on the standard output) a description of the command-line +options understood by the compiler that fit into all specified classes +and qualifiers. These are the supported classes: +.RS 4 +.IP "\fBoptimizers\fR" 4 +.IX Item "optimizers" +Display all of the optimization options supported by the +compiler. +.IP "\fBwarnings\fR" 4 +.IX Item "warnings" +Display all of the options controlling warning messages +produced by the compiler. +.IP "\fBtarget\fR" 4 +.IX Item "target" +Display target-specific options. Unlike the +\&\fB\-\-target\-help\fR option however, target-specific options of the +linker and assembler are not displayed. This is because those +tools do not currently support the extended \fB\-\-help=\fR syntax. +.IP "\fBparams\fR" 4 +.IX Item "params" +Display the values recognized by the \fB\-\-param\fR +option. +.IP "\fIlanguage\fR" 4 +.IX Item "language" +Display the options supported for \fIlanguage\fR, where +\&\fIlanguage\fR is the name of one of the languages supported in this +version of \s-1GCC.\s0 +.IP "\fBcommon\fR" 4 +.IX Item "common" +Display the options that are common to all languages. +.RE +.RS 4 +.Sp +These are the supported qualifiers: +.IP "\fBundocumented\fR" 4 +.IX Item "undocumented" +Display only those options that are undocumented. +.IP "\fBjoined\fR" 4 +.IX Item "joined" +Display options taking an argument that appears after an equal +sign in the same continuous piece of text, such as: +\&\fB\-\-help=target\fR. +.IP "\fBseparate\fR" 4 +.IX Item "separate" +Display options taking an argument that appears as a separate word +following the original option, such as: \fB\-o output-file\fR. +.RE +.RS 4 +.Sp +Thus for example to display all the undocumented target-specific +switches supported by the compiler, use: +.Sp +.Vb 1 +\& \-\-help=target,undocumented +.Ve +.Sp +The sense of a qualifier can be inverted by prefixing it with the +\&\fB^\fR character, so for example to display all binary warning +options (i.e., ones that are either on or off and that do not take an +argument) that have a description, use: +.Sp +.Vb 1 +\& \-\-help=warnings,^joined,^undocumented +.Ve +.Sp +The argument to \fB\-\-help=\fR should not consist solely of inverted +qualifiers. +.Sp +Combining several classes is possible, although this usually +restricts the output so much that there is nothing to display. One +case where it does work, however, is when one of the classes is +\&\fItarget\fR. For example, to display all the target-specific +optimization options, use: +.Sp +.Vb 1 +\& \-\-help=target,optimizers +.Ve +.Sp +The \fB\-\-help=\fR option can be repeated on the command line. Each +successive use displays its requested class of options, skipping +those that have already been displayed. If \fB\-\-help\fR is also +specified anywhere on the command line then this takes precedence +over any \fB\-\-help=\fR option. +.Sp +If the \fB\-Q\fR option appears on the command line before the +\&\fB\-\-help=\fR option, then the descriptive text displayed by +\&\fB\-\-help=\fR is changed. Instead of describing the displayed +options, an indication is given as to whether the option is enabled, +disabled or set to a specific value (assuming that the compiler +knows this at the point where the \fB\-\-help=\fR option is used). +.Sp +Here is a truncated example from the \s-1ARM\s0 port of \fBgcc\fR: +.Sp +.Vb 5 +\& % gcc \-Q \-mabi=2 \-\-help=target \-c +\& The following options are target specific: +\& \-mabi= 2 +\& \-mabort\-on\-noreturn [disabled] +\& \-mapcs [disabled] +.Ve +.Sp +The output is sensitive to the effects of previous command-line +options, so for example it is possible to find out which optimizations +are enabled at \fB\-O2\fR by using: +.Sp +.Vb 1 +\& \-Q \-O2 \-\-help=optimizers +.Ve +.Sp +Alternatively you can discover which binary optimizations are enabled +by \fB\-O3\fR by using: +.Sp +.Vb 3 +\& gcc \-c \-Q \-O3 \-\-help=optimizers > /tmp/O3\-opts +\& gcc \-c \-Q \-O2 \-\-help=optimizers > /tmp/O2\-opts +\& diff /tmp/O2\-opts /tmp/O3\-opts | grep enabled +.Ve +.RE +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +Display the version number and copyrights of the invoked \s-1GCC.\s0 +.IP "\fB\-pass\-exit\-codes\fR" 4 +.IX Item "-pass-exit-codes" +Normally the \fBgcc\fR program exits with the code of 1 if any +phase of the compiler returns a non-success return code. If you specify +\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program instead returns with +the numerically highest error produced by any phase returning an error +indication. The C, \*(C+, and Fortran front ends return 4 if an internal +compiler error is encountered. +.IP "\fB\-pipe\fR" 4 +.IX Item "-pipe" +Use pipes rather than temporary files for communication between the +various stages of compilation. This fails to work on some systems where +the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has +no trouble. +.IP "\fB\-specs=\fR\fIfile\fR" 4 +.IX Item "-specs=file" +Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR +file, in order to override the defaults which the \fBgcc\fR driver +program uses when determining what switches to pass to \fBcc1\fR, +\&\fBcc1plus\fR, \fBas\fR, \fBld\fR, etc. More than one +\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they +are processed in order, from left to right. +.IP "\fB\-wrapper\fR" 4 +.IX Item "-wrapper" +Invoke all subcommands under a wrapper program. The name of the +wrapper program and its parameters are passed as a comma separated +list. +.Sp +.Vb 1 +\& gcc \-c t.c \-wrapper gdb,\-\-args +.Ve +.Sp +This invokes all subprograms of \fBgcc\fR under +\&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR is +\&\fBgdb \-\-args cc1 ...\fR. +.IP "\fB\-ffile\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-ffile-prefix-map=old=new" +When compiling files residing in directory \fI\fIold\fI\fR, record +any references to them in the result of the compilation as if the +files resided in directory \fI\fInew\fI\fR instead. Specifying this +option is equivalent to specifying all the individual +\&\fB\-f*\-prefix\-map\fR options. This can be used to make reproducible +builds that are location independent. See also +\&\fB\-fmacro\-prefix\-map\fR and \fB\-fdebug\-prefix\-map\fR. +.IP "\fB\-fplugin=\fR\fIname\fR\fB.so\fR" 4 +.IX Item "-fplugin=name.so" +Load the plugin code in file \fIname\fR.so, assumed to be a +shared object to be dlopen'd by the compiler. The base name of +the shared object file is used to identify the plugin for the +purposes of argument parsing (See +\&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). +Each plugin should define the callback functions specified in the +Plugins \s-1API.\s0 +.IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "-fplugin-arg-name-key=value" +Define an argument called \fIkey\fR with a value of \fIvalue\fR +for the plugin called \fIname\fR. +.IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 +.IX Item "-fdump-ada-spec[-slim]" +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. +.IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 +.IX Item "-fdump-go-spec=file" +For input files in any language, generate corresponding Go +declarations in \fIfile\fR. This generates Go \f(CW\*(C`const\*(C'\fR, +\&\f(CW\*(C`type\*(C'\fR, \f(CW\*(C`var\*(C'\fR, and \f(CW\*(C`func\*(C'\fR declarations which may be a +useful way to start writing a Go interface to code written in some +other language. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SS "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" +\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, +\&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or +\&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, +\&\fB.H\fR, or (for shared template code) \fB.tcc\fR; and +preprocessed \*(C+ files use the suffix \fB.ii\fR. \s-1GCC\s0 recognizes +files with these names and compiles them as \*(C+ programs even if you +call the compiler the same way as for compiling C programs (usually +with the name \fBgcc\fR). +.PP +However, the use of \fBgcc\fR does not add the \*(C+ library. +\&\fBg++\fR is a program that calls \s-1GCC\s0 and automatically specifies linking +against the \*(C+ library. It treats \fB.c\fR, +\&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source +files unless \fB\-x\fR is used. This program is also useful when +precompiling a C header file with a \fB.h\fR extension for use in \*(C+ +compilations. On many systems, \fBg++\fR is also installed with +the name \fBc++\fR. +.PP +When you compile \*(C+ programs, you may specify many of the same +command-line options that you use for compiling programs in any +language; or command-line options meaningful for C and related +languages; or options that are meaningful only for \*(C+ programs. +.SS "Options Controlling C Dialect" +.IX Subsection "Options Controlling C Dialect" +The following options control the dialect of C (or languages derived +from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler +accepts: +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is +equivalent to \fB\-std=c++98\fR. +.Sp +This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO +C90\s0 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and +predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the +type of system you are using. It also enables the undesirable and +rarely used \s-1ISO\s0 trigraph feature. For the C compiler, +it disables recognition of \*(C+ style \fB//\fR comments as well as +the \f(CW\*(C`inline\*(C'\fR keyword. +.Sp +The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite +\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO C\s0 program, of +course, but it is useful to put them in header files that might be included +in compilations done with \fB\-ansi\fR. Alternate predefined macros +such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or +without \fB\-ansi\fR. +.Sp +The \fB\-ansi\fR option does not cause non-ISO programs to be +rejected gratuitously. For that, \fB\-Wpedantic\fR is required in +addition to \fB\-ansi\fR. +.Sp +The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR +option is used. Some header files may notice this macro and refrain +from declaring certain functions or defining certain macros that the +\&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any +programs that might use these names for other things. +.Sp +Functions that are normally built in but do not have semantics +defined by \s-1ISO C\s0 (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +functions when \fB\-ansi\fR is used. +.IP "\fB\-std=\fR" 4 +.IX Item "-std=" +Determine the language standard. This option +is currently only supported when compiling C or \*(C+. +.Sp +The compiler can accept several base standards, such as \fBc90\fR or +\&\fBc++98\fR, and \s-1GNU\s0 dialects of those standards, such as +\&\fBgnu90\fR or \fBgnu++98\fR. When a base standard is specified, the +compiler accepts all programs following that standard plus those +using \s-1GNU\s0 extensions that do not contradict it. For example, +\&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are +incompatible with \s-1ISO C90,\s0 such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR +keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in +\&\s-1ISO C90,\s0 such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR +expression. On the other hand, when a \s-1GNU\s0 dialect of a standard is +specified, all features supported by the compiler are enabled, even when +those features change the meaning of the base standard. As a result, some +strict-conforming programs may be rejected. The particular standard +is used by \fB\-Wpedantic\fR to identify which features are \s-1GNU\s0 +extensions given that version of the standard. For example +\&\fB\-std=gnu90 \-Wpedantic\fR warns about \*(C+ style \fB//\fR +comments, while \fB\-std=gnu99 \-Wpedantic\fR does not. +.Sp +A value for this option must be provided; possible values are +.RS 4 +.IP "\fBc90\fR" 4 +.IX Item "c90" +.PD 0 +.IP "\fBc89\fR" 4 +.IX Item "c89" +.IP "\fBiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +Support all \s-1ISO C90\s0 programs (certain \s-1GNU\s0 extensions that conflict +with \s-1ISO C90\s0 are disabled). Same as \fB\-ansi\fR for C code. +.IP "\fBiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +\&\s-1ISO C90\s0 as modified in amendment 1. +.IP "\fBc99\fR" 4 +.IX Item "c99" +.PD 0 +.IP "\fBc9x\fR" 4 +.IX Item "c9x" +.IP "\fBiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.IP "\fBiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.PD +\&\s-1ISO C99.\s0 This standard is substantially completely supported, modulo +bugs and floating-point issues +(mainly but not entirely relating to optional C99 features from +Annexes F and G). See +<\fBhttp://gcc.gnu.org/c99status.html\fR> for more information. The +names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. +.IP "\fBc11\fR" 4 +.IX Item "c11" +.PD 0 +.IP "\fBc1x\fR" 4 +.IX Item "c1x" +.IP "\fBiso9899:2011\fR" 4 +.IX Item "iso9899:2011" +.PD +\&\s-1ISO C11,\s0 the 2011 revision of the \s-1ISO C\s0 standard. This standard is +substantially completely supported, modulo bugs, floating-point issues +(mainly but not entirely relating to optional C11 features from +Annexes F and G) and the optional Annexes K (Bounds-checking +interfaces) and L (Analyzability). The name \fBc1x\fR is deprecated. +.IP "\fBc17\fR" 4 +.IX Item "c17" +.PD 0 +.IP "\fBc18\fR" 4 +.IX Item "c18" +.IP "\fBiso9899:2017\fR" 4 +.IX Item "iso9899:2017" +.IP "\fBiso9899:2018\fR" 4 +.IX Item "iso9899:2018" +.PD +\&\s-1ISO C17,\s0 the 2017 revision of the \s-1ISO C\s0 standard +(published in 2018). This standard is +same as C11 except for corrections of defects (all of which are also +applied with \fB\-std=c11\fR) and a new value of +\&\f(CW\*(C`_\|_STDC_VERSION_\|_\*(C'\fR, and so is supported to the same extent as C11. +.IP "\fBc2x\fR" 4 +.IX Item "c2x" +The next version of the \s-1ISO C\s0 standard, still under development. The +support for this version is experimental and incomplete. +.IP "\fBgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.IP "\fBgnu89\fR" 4 +.IX Item "gnu89" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C90\s0 (including some C99 features). +.IP "\fBgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.IP "\fBgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C99.\s0 The name \fBgnu9x\fR is deprecated. +.IP "\fBgnu11\fR" 4 +.IX Item "gnu11" +.PD 0 +.IP "\fBgnu1x\fR" 4 +.IX Item "gnu1x" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C11.\s0 +The name \fBgnu1x\fR is deprecated. +.IP "\fBgnu17\fR" 4 +.IX Item "gnu17" +.PD 0 +.IP "\fBgnu18\fR" 4 +.IX Item "gnu18" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO C17.\s0 This is the default for C code. +.IP "\fBgnu2x\fR" 4 +.IX Item "gnu2x" +The next version of the \s-1ISO C\s0 standard, still under development, plus +\&\s-1GNU\s0 extensions. The support for this version is experimental and +incomplete. +.IP "\fBc++98\fR" 4 +.IX Item "c++98" +.PD 0 +.IP "\fBc++03\fR" 4 +.IX Item "c++03" +.PD +The 1998 \s-1ISO \*(C+\s0 standard plus the 2003 technical corrigendum and some +additional defect reports. Same as \fB\-ansi\fR for \*(C+ code. +.IP "\fBgnu++98\fR" 4 +.IX Item "gnu++98" +.PD 0 +.IP "\fBgnu++03\fR" 4 +.IX Item "gnu++03" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++98\fR. +.IP "\fBc++11\fR" 4 +.IX Item "c++11" +.PD 0 +.IP "\fBc++0x\fR" 4 +.IX Item "c++0x" +.PD +The 2011 \s-1ISO \*(C+\s0 standard plus amendments. +The name \fBc++0x\fR is deprecated. +.IP "\fBgnu++11\fR" 4 +.IX Item "gnu++11" +.PD 0 +.IP "\fBgnu++0x\fR" 4 +.IX Item "gnu++0x" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++11\fR. +The name \fBgnu++0x\fR is deprecated. +.IP "\fBc++14\fR" 4 +.IX Item "c++14" +.PD 0 +.IP "\fBc++1y\fR" 4 +.IX Item "c++1y" +.PD +The 2014 \s-1ISO \*(C+\s0 standard plus amendments. +The name \fBc++1y\fR is deprecated. +.IP "\fBgnu++14\fR" 4 +.IX Item "gnu++14" +.PD 0 +.IP "\fBgnu++1y\fR" 4 +.IX Item "gnu++1y" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++14\fR. +This is the default for \*(C+ code. +The name \fBgnu++1y\fR is deprecated. +.IP "\fBc++17\fR" 4 +.IX Item "c++17" +.PD 0 +.IP "\fBc++1z\fR" 4 +.IX Item "c++1z" +.PD +The 2017 \s-1ISO \*(C+\s0 standard plus amendments. +The name \fBc++1z\fR is deprecated. +.IP "\fBgnu++17\fR" 4 +.IX Item "gnu++17" +.PD 0 +.IP "\fBgnu++1z\fR" 4 +.IX Item "gnu++1z" +.PD +\&\s-1GNU\s0 dialect of \fB\-std=c++17\fR. +The name \fBgnu++1z\fR is deprecated. +.IP "\fBc++2a\fR" 4 +.IX Item "c++2a" +The next revision of the \s-1ISO \*(C+\s0 standard, tentatively planned for +2020. Support is highly experimental, and will almost certainly +change in incompatible ways in future releases. +.IP "\fBgnu++2a\fR" 4 +.IX Item "gnu++2a" +\&\s-1GNU\s0 dialect of \fB\-std=c++2a\fR. Support is highly experimental, +and will almost certainly change in incompatible ways in future +releases. +.RE +.RS 4 +.RE +.IP "\fB\-fgnu89\-inline\fR" 4 +.IX Item "-fgnu89-inline" +The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional +\&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode. +.Sp +Using this option is roughly equivalent to adding the +\&\f(CW\*(C`gnu_inline\*(C'\fR function attribute to all inline functions. +.Sp +The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the +C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it +specifies the default behavior). +This option is not supported in \fB\-std=c90\fR or +\&\fB\-std=gnu90\fR mode. +.Sp +The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and +\&\f(CW\*(C`_\|_GNUC_STDC_INLINE_\|_\*(C'\fR may be used to check which semantics are +in effect for \f(CW\*(C`inline\*(C'\fR functions. +.IP "\fB\-fpermitted\-flt\-eval\-methods=\fR\fIstyle\fR" 4 +.IX Item "-fpermitted-flt-eval-methods=style" +\&\s-1ISO/IEC TS 18661\-3\s0 defines new permissible values for +\&\f(CW\*(C`FLT_EVAL_METHOD\*(C'\fR that indicate that operations and constants with +a semantic type that is an interchange or extended format should be +evaluated to the precision and range of that type. These new values are +a superset of those permitted under C99/C11, which does not specify the +meaning of other positive values of \f(CW\*(C`FLT_EVAL_METHOD\*(C'\fR. As such, code +conforming to C11 may not have been written expecting the possibility of +the new values. +.Sp +\&\fB\-fpermitted\-flt\-eval\-methods\fR specifies whether the compiler +should allow only the values of \f(CW\*(C`FLT_EVAL_METHOD\*(C'\fR specified in C99/C11, +or the extended set of values specified in \s-1ISO/IEC TS 18661\-3.\s0 +.Sp +\&\fIstyle\fR is either \f(CW\*(C`c11\*(C'\fR or \f(CW\*(C`ts\-18661\-3\*(C'\fR as appropriate. +.Sp +The default when in a standards compliant mode (\fB\-std=c11\fR or similar) +is \fB\-fpermitted\-flt\-eval\-methods=c11\fR. The default when in a \s-1GNU\s0 +dialect (\fB\-std=gnu11\fR or similar) is +\&\fB\-fpermitted\-flt\-eval\-methods=ts\-18661\-3\fR. +.IP "\fB\-aux\-info\fR \fIfilename\fR" 4 +.IX Item "-aux-info filename" +Output to the given filename prototyped declarations for all functions +declared and/or defined in a translation unit, including those in header +files. This option is silently ignored in any language other than C. +.Sp +Besides declarations, the file indicates, in comments, the origin of +each declaration (source file and line), whether the declaration was +implicit, prototyped or unprototyped (\fBI\fR, \fBN\fR for new or +\&\fBO\fR for old, respectively, in the first character after the line +number and the colon), and whether it came from a declaration or a +definition (\fBC\fR or \fBF\fR, respectively, in the following +character). In the case of function definitions, a K&R\-style list of +arguments followed by their declarations is also provided, inside +comments, after the declaration. +.IP "\fB\-fallow\-parameterless\-variadic\-functions\fR" 4 +.IX Item "-fallow-parameterless-variadic-functions" +Accept variadic functions without named parameters. +.Sp +Although it is possible to define such a function, this is not very +useful as it is not possible to read the arguments. This is only +supported for C as this construct is allowed by \*(C+. +.IP "\fB\-fno\-asm\fR" 4 +.IX Item "-fno-asm" +Do not recognize \f(CW\*(C`asm\*(C'\fR, \f(CW\*(C`inline\*(C'\fR or \f(CW\*(C`typeof\*(C'\fR as a +keyword, so that code can use these words as identifiers. You can use +the keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR +instead. \fB\-ansi\fR implies \fB\-fno\-asm\fR. +.Sp +In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since +\&\f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`inline\*(C'\fR are standard keywords. You may want to +use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same +effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this +switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since +\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO C99.\s0 +.IP "\fB\-fno\-builtin\fR" 4 +.IX Item "-fno-builtin" +.PD 0 +.IP "\fB\-fno\-builtin\-\fR\fIfunction\fR" 4 +.IX Item "-fno-builtin-function" +.PD +Don't recognize built-in functions that do not begin with +\&\fB_\|_builtin_\fR as prefix. +.Sp +\&\s-1GCC\s0 normally generates special code to handle certain built-in functions +more efficiently; for instance, calls to \f(CW\*(C`alloca\*(C'\fR may become single +instructions which adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\fR +may become inline copy loops. The resulting code is often both smaller +and faster, but since the function calls no longer appear as such, you +cannot set a breakpoint on those calls, nor can you change the behavior +of the functions by linking with a different library. In addition, +when a function is recognized as a built-in function, \s-1GCC\s0 may use +information about that function to warn about problems with calls to +that function, or to generate more efficient code, even if the +resulting code still contains calls to that function. For example, +warnings are given with \fB\-Wformat\fR for bad calls to +\&\f(CW\*(C`printf\*(C'\fR when \f(CW\*(C`printf\*(C'\fR is built in and \f(CW\*(C`strlen\*(C'\fR is +known not to modify global memory. +.Sp +With the \fB\-fno\-builtin\-\fR\fIfunction\fR option +only the built-in function \fIfunction\fR is +disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a +function is named that is not built-in in this version of \s-1GCC,\s0 this +option is ignored. There is no corresponding +\&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable +built-in functions selectively when using \fB\-fno\-builtin\fR or +\&\fB\-ffreestanding\fR, you may define macros such as: +.Sp +.Vb 2 +\& #define abs(n) _\|_builtin_abs ((n)) +\& #define strcpy(d, s) _\|_builtin_strcpy ((d), (s)) +.Ve +.IP "\fB\-fgimple\fR" 4 +.IX Item "-fgimple" +Enable parsing of function definitions marked with \f(CW\*(C`_\|_GIMPLE\*(C'\fR. +This is an experimental feature that allows unit testing of \s-1GIMPLE\s0 +passes. +.IP "\fB\-fhosted\fR" 4 +.IX Item "-fhosted" +Assert that compilation targets a hosted environment. This implies +\&\fB\-fbuiltin\fR. A hosted environment is one in which the +entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return +type of \f(CW\*(C`int\*(C'\fR. Examples are nearly everything except a kernel. +This is equivalent to \fB\-fno\-freestanding\fR. +.IP "\fB\-ffreestanding\fR" 4 +.IX Item "-ffreestanding" +Assert that compilation targets a freestanding environment. This +implies \fB\-fno\-builtin\fR. A freestanding environment +is one in which the standard library may not exist, and program startup may +not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel. +This is equivalent to \fB\-fno\-hosted\fR. +.IP "\fB\-fopenacc\fR" 4 +.IX Item "-fopenacc" +Enable handling of OpenACC directives \f(CW\*(C`#pragma acc\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$acc\*(C'\fR in Fortran. When \fB\-fopenacc\fR is specified, the +compiler generates accelerated code according to the OpenACC Application +Programming Interface v2.0 <\fBhttps://www.openacc.org\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. +.IP "\fB\-fopenacc\-dim=\fR\fIgeom\fR" 4 +.IX Item "-fopenacc-dim=geom" +Specify default compute dimensions for parallel offload regions that do +not explicitly specify. The \fIgeom\fR value is a triple of +\&':'\-separated sizes, in order 'gang', 'worker' and, 'vector'. A size +can be omitted, to use a target-specific default value. +.IP "\fB\-fopenmp\fR" 4 +.IX Item "-fopenmp" +Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$omp\*(C'\fR in Fortran. When \fB\-fopenmp\fR is specified, the +compiler generates parallel code according to the OpenMP Application +Program Interface v4.5 <\fBhttps://www.openmp.org\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. \fB\-fopenmp\fR implies +\&\fB\-fopenmp\-simd\fR. +.IP "\fB\-fopenmp\-simd\fR" 4 +.IX Item "-fopenmp-simd" +Enable handling of OpenMP's \s-1SIMD\s0 directives with \f(CW\*(C`#pragma omp\*(C'\fR +in C/\*(C+ and \f(CW\*(C`!$omp\*(C'\fR in Fortran. Other OpenMP directives +are ignored. +.IP "\fB\-fgnu\-tm\fR" 4 +.IX Item "-fgnu-tm" +When the option \fB\-fgnu\-tm\fR is specified, the compiler +generates code for the Linux variant of Intel's current Transactional +Memory \s-1ABI\s0 specification document (Revision 1.1, May 6 2009). This is +an experimental feature whose interface may change in future versions +of \s-1GCC,\s0 as the official specification changes. Please note that not +all architectures are supported for this feature. +.Sp +For more information on \s-1GCC\s0's support for transactional memory, +.Sp +Note that the transactional memory feature is not supported with +non-call exceptions (\fB\-fnon\-call\-exceptions\fR). +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Accept some non-standard constructs used in Microsoft header files. +.Sp +In \*(C+ code, this allows member names in structures to be similar +to previous types declarations. +.Sp +.Vb 4 +\& typedef int UOW; +\& struct ABC { +\& UOW UOW; +\& }; +.Ve +.Sp +Some cases of unnamed fields in structures and unions are only +accepted with this option. +.Sp +Note that this option is off for all targets but x86 +targets using ms-abi. +.IP "\fB\-fplan9\-extensions\fR" 4 +.IX Item "-fplan9-extensions" +Accept some non-standard constructs used in Plan 9 code. +.Sp +This enables \fB\-fms\-extensions\fR, permits passing pointers to +structures with anonymous fields to functions that expect pointers to +elements of the type of the field, and permits referring to anonymous +fields declared using a typedef. This is only +supported for C, not \*(C+. +.IP "\fB\-fcond\-mismatch\fR" 4 +.IX Item "-fcond-mismatch" +Allow conditional expressions with mismatched types in the second and +third arguments. The value of such an expression is void. This option +is not supported for \*(C+. +.IP "\fB\-flax\-vector\-conversions\fR" 4 +.IX Item "-flax-vector-conversions" +Allow implicit conversions between vectors with differing numbers of +elements and/or incompatible element types. This option should not be +used for new code. +.IP "\fB\-funsigned\-char\fR" 4 +.IX Item "-funsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be unsigned, like \f(CW\*(C`unsigned char\*(C'\fR. +.Sp +Each kind of machine has a default for what \f(CW\*(C`char\*(C'\fR should +be. It is either like \f(CW\*(C`unsigned char\*(C'\fR by default or like +\&\f(CW\*(C`signed char\*(C'\fR by default. +.Sp +Ideally, a portable program should always use \f(CW\*(C`signed char\*(C'\fR or +\&\f(CW\*(C`unsigned char\*(C'\fR when it depends on the signedness of an object. +But many programs have been written to use plain \f(CW\*(C`char\*(C'\fR and +expect it to be signed, or expect it to be unsigned, depending on the +machines they were written for. This option, and its inverse, let you +make such a program work with the opposite default. +.Sp +The type \f(CW\*(C`char\*(C'\fR is always a distinct type from each of +\&\f(CW\*(C`signed char\*(C'\fR or \f(CW\*(C`unsigned char\*(C'\fR, even though its behavior +is always just like one of those two. +.IP "\fB\-fsigned\-char\fR" 4 +.IX Item "-fsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be signed, like \f(CW\*(C`signed char\*(C'\fR. +.Sp +Note that this is equivalent to \fB\-fno\-unsigned\-char\fR, which is +the negative form of \fB\-funsigned\-char\fR. Likewise, the option +\&\fB\-fno\-signed\-char\fR is equivalent to \fB\-funsigned\-char\fR. +.IP "\fB\-fsigned\-bitfields\fR" 4 +.IX Item "-fsigned-bitfields" +.PD 0 +.IP "\fB\-funsigned\-bitfields\fR" 4 +.IX Item "-funsigned-bitfields" +.IP "\fB\-fno\-signed\-bitfields\fR" 4 +.IX Item "-fno-signed-bitfields" +.IP "\fB\-fno\-unsigned\-bitfields\fR" 4 +.IX Item "-fno-unsigned-bitfields" +.PD +These options control whether a bit-field is signed or unsigned, when the +declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By +default, such a bit-field is signed, because this is consistent: the +basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. +.IP "\fB\-fsso\-struct=\fR\fIendianness\fR" 4 +.IX Item "-fsso-struct=endianness" +Set the default scalar storage order of structures and unions to the +specified endianness. The accepted values are \fBbig-endian\fR, +\&\fBlittle-endian\fR and \fBnative\fR for the native endianness of +the target (the default). This option is not supported for \*(C+. +.Sp +\&\fBWarning:\fR the \fB\-fsso\-struct\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without it if the +specified endianness is not the native endianness of the target. +.SS "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" +This section describes the command-line options that are only meaningful +for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options +regardless of what language your program is in. For example, you +might compile a file \fIfirstClass.C\fR like this: +.PP +.Vb 1 +\& g++ \-g \-fstrict\-enums \-O \-c firstClass.C +.Ve +.PP +In this example, only \fB\-fstrict\-enums\fR is an option meant +only for \*(C+ programs; you can use the other options with any +language supported by \s-1GCC.\s0 +.PP +Some options for compiling C programs, such as \fB\-std\fR, are also +relevant for \*(C+ programs. +.PP +Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: +.IP "\fB\-fabi\-version=\fR\fIn\fR" 4 +.IX Item "-fabi-version=n" +Use version \fIn\fR of the \*(C+ \s-1ABI.\s0 The default is version 0. +.Sp +Version 0 refers to the version conforming most closely to +the \*(C+ \s-1ABI\s0 specification. Therefore, the \s-1ABI\s0 obtained using version 0 +will change in different versions of G++ as \s-1ABI\s0 bugs are fixed. +.Sp +Version 1 is the version of the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2. +.Sp +Version 2 is the version of the \*(C+ \s-1ABI\s0 that first appeared in G++ +3.4, and was the default through G++ 4.9. +.Sp +Version 3 corrects an error in mangling a constant address as a +template argument. +.Sp +Version 4, which first appeared in G++ 4.5, implements a standard +mangling for vector types. +.Sp +Version 5, which first appeared in G++ 4.6, corrects the mangling of +attribute const/volatile on function pointer types, decltype of a +plain decl, and use of a function parameter in the declaration of +another parameter. +.Sp +Version 6, which first appeared in G++ 4.7, corrects the promotion +behavior of \*(C+11 scoped enums and the mangling of template argument +packs, const/static_cast, prefix ++ and \-\-, and a class scope function +used as a template argument. +.Sp +Version 7, which first appeared in G++ 4.8, that treats nullptr_t as a +builtin type and corrects the mangling of lambdas in default argument +scope. +.Sp +Version 8, which first appeared in G++ 4.9, corrects the substitution +behavior of function types with function-cv-qualifiers. +.Sp +Version 9, which first appeared in G++ 5.2, corrects the alignment of +\&\f(CW\*(C`nullptr_t\*(C'\fR. +.Sp +Version 10, which first appeared in G++ 6.1, adds mangling of +attributes that affect type identity, such as ia32 calling convention +attributes (e.g. \fBstdcall\fR). +.Sp +Version 11, which first appeared in G++ 7, corrects the mangling of +sizeof... expressions and operator names. For multiple entities with +the same name within a function, that are declared in different scopes, +the mangling now changes starting with the twelfth occurrence. It also +implies \fB\-fnew\-inheriting\-ctors\fR. +.Sp +Version 12, which first appeared in G++ 8, corrects the calling +conventions for empty classes on the x86_64 target and for classes +with only deleted copy/move constructors. It accidentally changes the +calling convention for classes with a deleted copy constructor and a +trivial move constructor. +.Sp +Version 13, which first appeared in G++ 8.2, fixes the accidental +change in version 12. +.Sp +See also \fB\-Wabi\fR. +.IP "\fB\-fabi\-compat\-version=\fR\fIn\fR" 4 +.IX Item "-fabi-compat-version=n" +On targets that support strong aliases, G++ +works around mangling changes by creating an alias with the correct +mangled name when defining a symbol with an incorrect mangled name. +This switch specifies which \s-1ABI\s0 version to use for the alias. +.Sp +With \fB\-fabi\-version=0\fR (the default), this defaults to 11 (\s-1GCC 7\s0 +compatibility). If another \s-1ABI\s0 version is explicitly selected, this +defaults to 0. For compatibility with \s-1GCC\s0 versions 3.2 through 4.9, +use \fB\-fabi\-compat\-version=2\fR. +.Sp +If this option is not provided but \fB\-Wabi=\fR\fIn\fR is, that +version is used for compatibility aliases. If this option is provided +along with \fB\-Wabi\fR (without the version), the version from this +option is used for the warning. +.IP "\fB\-fno\-access\-control\fR" 4 +.IX Item "-fno-access-control" +Turn off all access checking. This switch is mainly useful for working +around bugs in the access control code. +.IP "\fB\-faligned\-new\fR" 4 +.IX Item "-faligned-new" +Enable support for \*(C+17 \f(CW\*(C`new\*(C'\fR of types that require more +alignment than \f(CW\*(C`void* ::operator new(std::size_t)\*(C'\fR provides. A +numeric argument such as \f(CW\*(C`\-faligned\-new=32\*(C'\fR can be used to +specify how much alignment (in bytes) is provided by that function, +but few users will need to override the default of +\&\f(CW\*(C`alignof(std::max_align_t)\*(C'\fR. +.Sp +This flag is enabled by default for \fB\-std=c++17\fR. +.IP "\fB\-fchar8_t\fR" 4 +.IX Item "-fchar8_t" +.PD 0 +.IP "\fB\-fno\-char8_t\fR" 4 +.IX Item "-fno-char8_t" +.PD +Enable support for \f(CW\*(C`char8_t\*(C'\fR as adopted for \*(C+2a. This includes +the addition of a new \f(CW\*(C`char8_t\*(C'\fR fundamental type, changes to the +types of \s-1UTF\-8\s0 string and character literals, new signatures for +user-defined literals, associated standard library updates, and new +\&\f(CW\*(C`_\|_cpp_char8_t\*(C'\fR and \f(CW\*(C`_\|_cpp_lib_char8_t\*(C'\fR feature test macros. +.Sp +This option enables functions to be overloaded for ordinary and \s-1UTF\-8\s0 +strings: +.Sp +.Vb 4 +\& int f(const char *); // #1 +\& int f(const char8_t *); // #2 +\& int v1 = f("text"); // Calls #1 +\& int v2 = f(u8"text"); // Calls #2 +.Ve +.Sp +and introduces new signatures for user-defined literals: +.Sp +.Vb 6 +\& int operator""_udl1(char8_t); +\& int v3 = u8\*(Aqx\*(Aq_udl1; +\& int operator""_udl2(const char8_t*, std::size_t); +\& int v4 = u8"text"_udl2; +\& template int operator""_udl3(); +\& int v5 = u8"text"_udl3; +.Ve +.Sp +The change to the types of \s-1UTF\-8\s0 string and character literals introduces +incompatibilities with \s-1ISO \*(C+11\s0 and later standards. For example, the +following code is well-formed under \s-1ISO \*(C+11,\s0 but is ill-formed when +\&\fB\-fchar8_t\fR is specified. +.Sp +.Vb 10 +\& char ca[] = u8"xx"; // error: char\-array initialized from wide +\& // string +\& const char *cp = u8"xx";// error: invalid conversion from +\& // \`const char8_t*\*(Aq to \`const char*\*(Aq +\& int f(const char*); +\& auto v = f(u8"xx"); // error: invalid conversion from +\& // \`const char8_t*\*(Aq to \`const char*\*(Aq +\& std::string s{u8"xx"}; // error: no matching function for call to +\& // \`std::basic_string::basic_string()\*(Aq +\& using namespace std::literals; +\& s = u8"xx"s; // error: conversion from +\& // \`basic_string\*(Aq to non\-scalar +\& // type \`basic_string\*(Aq requested +.Ve +.IP "\fB\-fcheck\-new\fR" 4 +.IX Item "-fcheck-new" +Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null +before attempting to modify the storage allocated. This check is +normally unnecessary because the \*(C+ standard specifies that +\&\f(CW\*(C`operator new\*(C'\fR only returns \f(CW0\fR if it is declared +\&\f(CW\*(C`throw()\*(C'\fR, in which case the compiler always checks the +return value even without this option. In all other cases, when +\&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory +exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also +\&\fBnew (nothrow)\fR. +.IP "\fB\-fconcepts\fR" 4 +.IX Item "-fconcepts" +Enable support for the \*(C+ Extensions for Concepts Technical +Specification, \s-1ISO 19217\s0 (2015), which allows code like +.Sp +.Vb 2 +\& template concept bool Addable = requires (T t) { t + t; }; +\& template T add (T a, T b) { return a + b; } +.Ve +.IP "\fB\-fconstexpr\-depth=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-depth=n" +Set the maximum nested evaluation depth for \*(C+11 constexpr functions +to \fIn\fR. A limit is needed to detect endless recursion during +constant expression evaluation. The minimum specified by the standard +is 512. +.IP "\fB\-fconstexpr\-loop\-limit=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-loop-limit=n" +Set the maximum number of iterations for a loop in \*(C+14 constexpr functions +to \fIn\fR. A limit is needed to detect infinite loops during +constant expression evaluation. The default is 262144 (1<<18). +.IP "\fB\-fconstexpr\-ops\-limit=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-ops-limit=n" +Set the maximum number of operations during a single constexpr evaluation. +Even when number of iterations of a single loop is limited with the above limit, +if there are several nested loops and each of them has many iterations but still +smaller than the above limit, or if in a body of some loop or even outside +of a loop too many expressions need to be evaluated, the resulting constexpr +evaluation might take too long. +The default is 33554432 (1<<25). +.IP "\fB\-fdeduce\-init\-list\fR" 4 +.IX Item "-fdeduce-init-list" +Enable deduction of a template type parameter as +\&\f(CW\*(C`std::initializer_list\*(C'\fR from a brace-enclosed initializer list, i.e. +.Sp +.Vb 4 +\& template auto forward(T t) \-> decltype (realfn (t)) +\& { +\& return realfn (t); +\& } +\& +\& void f() +\& { +\& forward({1,2}); // call forward> +\& } +.Ve +.Sp +This deduction was implemented as a possible extension to the +originally proposed semantics for the \*(C+11 standard, but was not part +of the final standard, so it is disabled by default. This option is +deprecated, and may be removed in a future version of G++. +.IP "\fB\-fno\-elide\-constructors\fR" 4 +.IX Item "-fno-elide-constructors" +The \*(C+ standard allows an implementation to omit creating a temporary +that is only used to initialize another object of the same type. +Specifying this option disables that optimization, and forces G++ to +call the copy constructor in all cases. This option also causes G++ +to call trivial member functions which otherwise would be expanded inline. +.Sp +In \*(C+17, the compiler is required to omit these temporaries, but this +option still affects trivial member functions. +.IP "\fB\-fno\-enforce\-eh\-specs\fR" 4 +.IX Item "-fno-enforce-eh-specs" +Don't generate code to check for violation of exception specifications +at run time. This option violates the \*(C+ standard, but may be useful +for reducing code size in production builds, much like defining +\&\f(CW\*(C`NDEBUG\*(C'\fR. This does not give user code permission to throw +exceptions in violation of the exception specifications; the compiler +still optimizes based on the specifications, so throwing an +unexpected exception results in undefined behavior at run time. +.IP "\fB\-fextern\-tls\-init\fR" 4 +.IX Item "-fextern-tls-init" +.PD 0 +.IP "\fB\-fno\-extern\-tls\-init\fR" 4 +.IX Item "-fno-extern-tls-init" +.PD +The \*(C+11 and OpenMP standards allow \f(CW\*(C`thread_local\*(C'\fR and +\&\f(CW\*(C`threadprivate\*(C'\fR variables to have dynamic (runtime) +initialization. To support this, any use of such a variable goes +through a wrapper function that performs any necessary initialization. +When the use and definition of the variable are in the same +translation unit, this overhead can be optimized away, but when the +use is in a different translation unit there is significant overhead +even if the variable doesn't actually need dynamic initialization. If +the programmer can be sure that no use of the variable in a +non-defining \s-1TU\s0 needs to trigger dynamic initialization (either +because the variable is statically initialized, or a use of the +variable in the defining \s-1TU\s0 will be executed before any uses in +another \s-1TU\s0), they can avoid this overhead with the +\&\fB\-fno\-extern\-tls\-init\fR option. +.Sp +On targets that support symbol aliases, the default is +\&\fB\-fextern\-tls\-init\fR. On targets that do not support symbol +aliases, the default is \fB\-fno\-extern\-tls\-init\fR. +.IP "\fB\-fno\-gnu\-keywords\fR" 4 +.IX Item "-fno-gnu-keywords" +Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this +word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead. +This option is implied by the strict \s-1ISO \*(C+\s0 dialects: \fB\-ansi\fR, +\&\fB\-std=c++98\fR, \fB\-std=c++11\fR, etc. +.IP "\fB\-fno\-implicit\-templates\fR" 4 +.IX Item "-fno-implicit-templates" +Never emit code for non-inline templates that are instantiated +implicitly (i.e. by use); only emit code for explicit instantiations. +If you use this option, you must take care to structure your code to +include all the necessary explicit instantiations to avoid getting +undefined symbols at link time. +.IP "\fB\-fno\-implicit\-inline\-templates\fR" 4 +.IX Item "-fno-implicit-inline-templates" +Don't emit code for implicit instantiations of inline templates, either. +The default is to handle inlines differently so that compiles with and +without optimization need the same set of explicit instantiations. +.IP "\fB\-fno\-implement\-inlines\fR" 4 +.IX Item "-fno-implement-inlines" +To save space, do not emit out-of-line copies of inline functions +controlled by \f(CW\*(C`#pragma implementation\*(C'\fR. This causes linker +errors if these functions are not inlined everywhere they are called. +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Disable Wpedantic warnings about constructs used in \s-1MFC,\s0 such as implicit +int and getting a pointer to member function via non-standard syntax. +.IP "\fB\-fnew\-inheriting\-ctors\fR" 4 +.IX Item "-fnew-inheriting-ctors" +Enable the P0136 adjustment to the semantics of \*(C+11 constructor +inheritance. This is part of \*(C+17 but also considered to be a Defect +Report against \*(C+11 and \*(C+14. This flag is enabled by default +unless \fB\-fabi\-version=10\fR or lower is specified. +.IP "\fB\-fnew\-ttp\-matching\fR" 4 +.IX Item "-fnew-ttp-matching" +Enable the P0522 resolution to Core issue 150, template template +parameters and default arguments: this allows a template with default +template arguments as an argument for a template template parameter +with fewer template parameters. This flag is enabled by default for +\&\fB\-std=c++17\fR. +.IP "\fB\-fno\-nonansi\-builtins\fR" 4 +.IX Item "-fno-nonansi-builtins" +Disable built-in declarations of functions that are not mandated by +\&\s-1ANSI/ISO C.\s0 These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. +.IP "\fB\-fnothrow\-opt\fR" 4 +.IX Item "-fnothrow-opt" +Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as if it were a +\&\f(CW\*(C`noexcept\*(C'\fR specification to reduce or eliminate the text size +overhead relative to a function with no exception specification. If +the function has local variables of types with non-trivial +destructors, the exception specification actually makes the +function smaller because the \s-1EH\s0 cleanups for those variables can be +optimized away. The semantic effect is that an exception thrown out of +a function with such an exception specification results in a call +to \f(CW\*(C`terminate\*(C'\fR rather than \f(CW\*(C`unexpected\*(C'\fR. +.IP "\fB\-fno\-operator\-names\fR" 4 +.IX Item "-fno-operator-names" +Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR, +\&\f(CW\*(C`bitor\*(C'\fR, \f(CW\*(C`compl\*(C'\fR, \f(CW\*(C`not\*(C'\fR, \f(CW\*(C`or\*(C'\fR and \f(CW\*(C`xor\*(C'\fR as +synonyms as keywords. +.IP "\fB\-fno\-optional\-diags\fR" 4 +.IX Item "-fno-optional-diags" +Disable diagnostics that the standard says a compiler does not need to +issue. Currently, the only such diagnostic issued by G++ is the one for +a name having multiple meanings within a class. +.IP "\fB\-fpermissive\fR" 4 +.IX Item "-fpermissive" +Downgrade some diagnostics about nonconformant code from errors to +warnings. Thus, using \fB\-fpermissive\fR allows some +nonconforming code to compile. +.IP "\fB\-fno\-pretty\-templates\fR" 4 +.IX Item "-fno-pretty-templates" +When an error message refers to a specialization of a function +template, the compiler normally prints the signature of the +template followed by the template arguments and any typedefs or +typenames in the signature (e.g. \f(CW\*(C`void f(T) [with T = int]\*(C'\fR +rather than \f(CW\*(C`void f(int)\*(C'\fR) so that it's clear which template is +involved. When an error message refers to a specialization of a class +template, the compiler omits any template arguments that match +the default template arguments for that template. If either of these +behaviors make it harder to understand the error message rather than +easier, you can use \fB\-fno\-pretty\-templates\fR to disable them. +.IP "\fB\-frepo\fR" 4 +.IX Item "-frepo" +Enable automatic template instantiation at link time. This option also +implies \fB\-fno\-implicit\-templates\fR. +.IP "\fB\-fno\-rtti\fR" 4 +.IX Item "-fno-rtti" +Disable generation of information about every class with virtual +functions for use by the \*(C+ run-time type identification features +(\f(CW\*(C`dynamic_cast\*(C'\fR and \f(CW\*(C`typeid\*(C'\fR). If you don't use those parts +of the language, you can save some space by using this flag. Note that +exception handling uses the same information, but G++ generates it as +needed. The \f(CW\*(C`dynamic_cast\*(C'\fR operator can still be used for casts that +do not require run-time type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to +unambiguous base classes. +.Sp +Mixing code compiled with \fB\-frtti\fR with that compiled with +\&\fB\-fno\-rtti\fR may not work. For example, programs may +fail to link if a class compiled with \fB\-fno\-rtti\fR is used as a base +for a class compiled with \fB\-frtti\fR. +.IP "\fB\-fsized\-deallocation\fR" 4 +.IX Item "-fsized-deallocation" +Enable the built-in global declarations +.Sp +.Vb 2 +\& void operator delete (void *, std::size_t) noexcept; +\& void operator delete[] (void *, std::size_t) noexcept; +.Ve +.Sp +as introduced in \*(C+14. This is useful for user-defined replacement +deallocation functions that, for example, use the size of the object +to make deallocation faster. Enabled by default under +\&\fB\-std=c++14\fR and above. The flag \fB\-Wsized\-deallocation\fR +warns about places that might want to add a definition. +.IP "\fB\-fstrict\-enums\fR" 4 +.IX Item "-fstrict-enums" +Allow the compiler to optimize using the assumption that a value of +enumerated type can only be one of the values of the enumeration (as +defined in the \*(C+ standard; basically, a value that can be +represented in the minimum number of bits needed to represent all the +enumerators). This assumption may not be valid if the program uses a +cast to convert an arbitrary integer value to the enumerated type. +.IP "\fB\-fstrong\-eval\-order\fR" 4 +.IX Item "-fstrong-eval-order" +Evaluate member access, array subscripting, and shift expressions in +left-to-right order, and evaluate assignment in right-to-left order, +as adopted for \*(C+17. Enabled by default with \fB\-std=c++17\fR. +\&\fB\-fstrong\-eval\-order=some\fR enables just the ordering of member +access and shift expressions, and is the default without +\&\fB\-std=c++17\fR. +.IP "\fB\-ftemplate\-backtrace\-limit=\fR\fIn\fR" 4 +.IX Item "-ftemplate-backtrace-limit=n" +Set the maximum number of template instantiation notes for a single +warning or error to \fIn\fR. The default value is 10. +.IP "\fB\-ftemplate\-depth=\fR\fIn\fR" 4 +.IX Item "-ftemplate-depth=n" +Set the maximum instantiation depth for template classes to \fIn\fR. +A limit on the template instantiation depth is needed to detect +endless recursions during template class instantiation. \s-1ANSI/ISO \*(C+\s0 +conforming programs must not rely on a maximum depth greater than 17 +(changed to 1024 in \*(C+11). The default value is 900, as the compiler +can run out of stack space before hitting 1024 in some situations. +.IP "\fB\-fno\-threadsafe\-statics\fR" 4 +.IX Item "-fno-threadsafe-statics" +Do not emit the extra code to use the routines specified in the \*(C+ +\&\s-1ABI\s0 for thread-safe initialization of local statics. You can use this +option to reduce code size slightly in code that doesn't need to be +thread-safe. +.IP "\fB\-fuse\-cxa\-atexit\fR" 4 +.IX Item "-fuse-cxa-atexit" +Register destructors for objects with static storage duration with the +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function. +This option is required for fully standards-compliant handling of static +destructors, but only works if your C library supports +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR. +.IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4 +.IX Item "-fno-use-cxa-get-exception-ptr" +Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This +causes \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary +if the runtime routine is not available. +.IP "\fB\-fvisibility\-inlines\-hidden\fR" 4 +.IX Item "-fvisibility-inlines-hidden" +This switch declares that the user does not attempt to compare +pointers to inline functions or methods where the addresses of the two functions +are taken in different shared objects. +.Sp +The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with +\&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not +appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection +when used within the \s-1DSO.\s0 Enabling this option can have a dramatic effect +on load and link times of a \s-1DSO\s0 as it massively reduces the size of the +dynamic export table when the library makes heavy use of templates. +.Sp +The behavior of this switch is not quite the same as marking the +methods as hidden directly, because it does not affect static variables +local to the function or cause the compiler to deduce that +the function is defined in only one shared object. +.Sp +You may mark a method as having a visibility explicitly to negate the +effect of the switch for that method. For example, if you do want to +compare pointers to a particular inline method, you might mark it as +having default visibility. Marking the enclosing class with explicit +visibility has no effect. +.Sp +Explicitly instantiated inline methods are unaffected by this option +as their linkage might otherwise cross a shared library boundary. +.IP "\fB\-fvisibility\-ms\-compat\fR" 4 +.IX Item "-fvisibility-ms-compat" +This flag attempts to use visibility settings to make \s-1GCC\s0's \*(C+ +linkage model compatible with that of Microsoft Visual Studio. +.Sp +The flag makes these changes to \s-1GCC\s0's linkage model: +.RS 4 +.IP "1." 4 +.IX Item "1." +It sets the default visibility to \f(CW\*(C`hidden\*(C'\fR, like +\&\fB\-fvisibility=hidden\fR. +.IP "2." 4 +.IX Item "2." +Types, but not their members, are not hidden by default. +.IP "3." 4 +.IX Item "3." +The One Definition Rule is relaxed for types without explicit +visibility specifications that are defined in more than one +shared object: those declarations are permitted if they are +permitted when this option is not used. +.RE +.RS 4 +.Sp +In new code it is better to use \fB\-fvisibility=hidden\fR and +export those classes that are intended to be externally visible. +Unfortunately it is possible for code to rely, perhaps accidentally, +on the Visual Studio behavior. +.Sp +Among the consequences of these changes are that static data members +of the same type with the same name but defined in different shared +objects are different, so changing one does not change the other; +and that pointers to function members defined in different shared +objects may not compare equal. When this flag is given, it is a +violation of the \s-1ODR\s0 to define types with the same name differently. +.RE +.IP "\fB\-fno\-weak\fR" 4 +.IX Item "-fno-weak" +Do not use weak symbol support, even if it is provided by the linker. +By default, G++ uses weak symbols if they are available. This +option exists only for testing, and should not be used by end-users; +it results in inferior code and has no benefits. This option may +be removed in a future release of G++. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the standard directories specific to +\&\*(C+, but do still search the other standard directories. (This option +is used when building the \*(C+ library.) +.PP +In addition, these optimization, warning, and code generation options +have meanings only for \*(C+ programs: +.IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi (C, Objective-C, and Objective- only)" +Warn when G++ it generates code that is probably not compatible with +the vendor-neutral \*(C+ \s-1ABI.\s0 Since G++ now defaults to updating the +\&\s-1ABI\s0 with each major release, normally \fB\-Wabi\fR will warn only if +there is a check added later in a release series for an \s-1ABI\s0 issue +discovered since the initial release. \fB\-Wabi\fR will warn about +more things if an older \s-1ABI\s0 version is selected (with +\&\fB\-fabi\-version=\fR\fIn\fR). +.Sp +\&\fB\-Wabi\fR can also be used with an explicit version number to +warn about compatibility with a particular \fB\-fabi\-version\fR +level, e.g. \fB\-Wabi=2\fR to warn about changes relative to +\&\fB\-fabi\-version=2\fR. +.Sp +If an explicit version number is provided and +\&\fB\-fabi\-compat\-version\fR is not specified, the version number +from this option is used for compatibility aliases. If no explicit +version number is provided with this option, but +\&\fB\-fabi\-compat\-version\fR is specified, that version number is +used for \s-1ABI\s0 warnings. +.Sp +Although an effort has been made to warn about +all such cases, there are probably some cases that are not warned about, +even though G++ is generating incompatible code. There may also be +cases where warnings are emitted even though the code that is generated +is compatible. +.Sp +You should rewrite your code to avoid these warnings if you are +concerned about the fact that code generated by G++ may not be binary +compatible with code generated by other compilers. +.Sp +Known incompatibilities in \fB\-fabi\-version=2\fR (which was the +default from \s-1GCC 3.4\s0 to 4.9) include: +.RS 4 +.IP "*" 4 +A template with a non-type template parameter of reference type was +mangled incorrectly: +.Sp +.Vb 3 +\& extern int N; +\& template struct S {}; +\& void n (S) {2} +.Ve +.Sp +This was fixed in \fB\-fabi\-version=3\fR. +.IP "*" 4 +\&\s-1SIMD\s0 vector types declared using \f(CW\*(C`_\|_attribute ((vector_size))\*(C'\fR were +mangled in a non-standard way that does not allow for overloading of +functions taking vectors of different sizes. +.Sp +The mangling was changed in \fB\-fabi\-version=4\fR. +.IP "*" 4 +\&\f(CW\*(C`_\|_attribute ((const))\*(C'\fR and \f(CW\*(C`noreturn\*(C'\fR were mangled as type +qualifiers, and \f(CW\*(C`decltype\*(C'\fR of a plain declaration was folded away. +.Sp +These mangling issues were fixed in \fB\-fabi\-version=5\fR. +.IP "*" 4 +Scoped enumerators passed as arguments to a variadic function are +promoted like unscoped enumerators, causing \f(CW\*(C`va_arg\*(C'\fR to complain. +On most targets this does not actually affect the parameter passing +\&\s-1ABI,\s0 as there is no way to pass an argument smaller than \f(CW\*(C`int\*(C'\fR. +.Sp +Also, the \s-1ABI\s0 changed the mangling of template argument packs, +\&\f(CW\*(C`const_cast\*(C'\fR, \f(CW\*(C`static_cast\*(C'\fR, prefix increment/decrement, and +a class scope function used as a template argument. +.Sp +These issues were corrected in \fB\-fabi\-version=6\fR. +.IP "*" 4 +Lambdas in default argument scope were mangled incorrectly, and the +\&\s-1ABI\s0 changed the mangling of \f(CW\*(C`nullptr_t\*(C'\fR. +.Sp +These issues were corrected in \fB\-fabi\-version=7\fR. +.IP "*" 4 +When mangling a function type with function-cv-qualifiers, the +un-qualified function type was incorrectly treated as a substitution +candidate. +.Sp +This was fixed in \fB\-fabi\-version=8\fR, the default for \s-1GCC 5.1.\s0 +.IP "*" 4 +\&\f(CW\*(C`decltype(nullptr)\*(C'\fR incorrectly had an alignment of 1, leading to +unaligned accesses. Note that this did not affect the \s-1ABI\s0 of a +function with a \f(CW\*(C`nullptr_t\*(C'\fR parameter, as parameters have a +minimum alignment. +.Sp +This was fixed in \fB\-fabi\-version=9\fR, the default for \s-1GCC 5.2.\s0 +.IP "*" 4 +Target-specific attributes that affect the identity of a type, such as +ia32 calling conventions on a function type (stdcall, regparm, etc.), +did not affect the mangled name, leading to name collisions when +function pointers were used as template arguments. +.Sp +This was fixed in \fB\-fabi\-version=10\fR, the default for \s-1GCC 6.1.\s0 +.RE +.RS 4 +.Sp +It also warns about psABI-related changes. The known psABI changes at this +point include: +.IP "*" 4 +For SysV/x86\-64, unions with \f(CW\*(C`long double\*(C'\fR members are +passed in memory as specified in psABI. For example: +.Sp +.Vb 4 +\& union U { +\& long double ld; +\& int i; +\& }; +.Ve +.Sp +\&\f(CW\*(C`union U\*(C'\fR is always passed in memory. +.RE +.RS 4 +.RE +.IP "\fB\-Wabi\-tag\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi-tag ( and Objective- only)" +Warn when a type with an \s-1ABI\s0 tag is used in a context that does not +have that \s-1ABI\s0 tag. See \fB\*(C+ Attributes\fR for more information +about \s-1ABI\s0 tags. +.IP "\fB\-Wctor\-dtor\-privacy\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wctor-dtor-privacy ( and Objective- only)" +Warn when a class seems unusable because all the constructors or +destructors in that class are private, and it has neither friends nor +public static member functions. Also warn if there are no non-private +methods, and there's at least one private member function that isn't +a constructor or destructor. +.IP "\fB\-Wdelete\-non\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wdelete-non-virtual-dtor ( and Objective- only)" +Warn when \f(CW\*(C`delete\*(C'\fR is used to destroy an instance of a class that +has virtual functions and non-virtual destructor. It is unsafe to delete +an instance of a derived class through a pointer to a base class if the +base class does not have a virtual destructor. This warning is enabled +by \fB\-Wall\fR. +.IP "\fB\-Wdeprecated\-copy\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wdeprecated-copy ( and Objective- only)" +Warn that the implicit declaration of a copy constructor or copy +assignment operator is deprecated if the class has a user-provided +copy constructor or copy assignment operator, in \*(C+11 and up. This +warning is enabled by \fB\-Wextra\fR. With +\&\fB\-Wdeprecated\-copy\-dtor\fR, also deprecate if the class has a +user-provided destructor. +.IP "\fB\-Wno\-init\-list\-lifetime\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-init-list-lifetime ( and Objective- only)" +Do not warn about uses of \f(CW\*(C`std::initializer_list\*(C'\fR that are likely +to result in dangling pointers. Since the underlying array for an +\&\f(CW\*(C`initializer_list\*(C'\fR is handled like a normal \*(C+ temporary object, +it is easy to inadvertently keep a pointer to the array past the end +of the array's lifetime. For example: +.RS 4 +.IP "*" 4 +If a function returns a temporary \f(CW\*(C`initializer_list\*(C'\fR, or a local +\&\f(CW\*(C`initializer_list\*(C'\fR variable, the array's lifetime ends at the end +of the return statement, so the value returned has a dangling pointer. +.IP "*" 4 +If a new-expression creates an \f(CW\*(C`initializer_list\*(C'\fR, the array only +lives until the end of the enclosing full-expression, so the +\&\f(CW\*(C`initializer_list\*(C'\fR in the heap has a dangling pointer. +.IP "*" 4 +When an \f(CW\*(C`initializer_list\*(C'\fR variable is assigned from a +brace-enclosed initializer list, the temporary array created for the +right side of the assignment only lives until the end of the +full-expression, so at the next statement the \f(CW\*(C`initializer_list\*(C'\fR +variable has a dangling pointer. +.Sp +.Vb 6 +\& // li\*(Aqs initial underlying array lives as long as li +\& std::initializer_list li = { 1,2,3 }; +\& // assignment changes li to point to a temporary array +\& li = { 4, 5 }; +\& // now the temporary is gone and li has a dangling pointer +\& int i = li.begin()[0] // undefined behavior +.Ve +.IP "*" 4 +When a list constructor stores the \f(CW\*(C`begin\*(C'\fR pointer from the +\&\f(CW\*(C`initializer_list\*(C'\fR argument, this doesn't extend the lifetime of +the array, so if a class variable is constructed from a temporary +\&\f(CW\*(C`initializer_list\*(C'\fR, the pointer is left dangling by the end of +the variable declaration statement. +.RE +.RS 4 +.RE +.IP "\fB\-Wliteral\-suffix\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wliteral-suffix ( and Objective- only)" +Warn when a string or character literal is followed by a ud-suffix which does +not begin with an underscore. As a conforming extension, \s-1GCC\s0 treats such +suffixes as separate preprocessing tokens in order to maintain backwards +compatibility with code that uses formatting macros from \f(CW\*(C`\*(C'\fR. +For example: +.Sp +.Vb 3 +\& #define _\|_STDC_FORMAT_MACROS +\& #include +\& #include +\& +\& int main() { +\& int64_t i64 = 123; +\& printf("My int64: %" PRId64"\en", i64); +\& } +.Ve +.Sp +In this case, \f(CW\*(C`PRId64\*(C'\fR is treated as a separate preprocessing token. +.Sp +Additionally, warn when a user-defined literal operator is declared with +a literal suffix identifier that doesn't begin with an underscore. Literal +suffix identifiers that don't begin with an underscore are reserved for +future standardization. +.Sp +This warning is enabled by default. +.IP "\fB\-Wlto\-type\-mismatch\fR" 4 +.IX Item "-Wlto-type-mismatch" +During the link-time optimization warn about type mismatches in +global declarations from different compilation units. +Requires \fB\-flto\fR to be enabled. Enabled by default. +.IP "\fB\-Wno\-narrowing\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-narrowing ( and Objective- only)" +For \*(C+11 and later standards, narrowing conversions are diagnosed by default, +as required by the standard. A narrowing conversion from a constant produces +an error, and a narrowing conversion from a non-constant produces a warning, +but \fB\-Wno\-narrowing\fR suppresses the diagnostic. +Note that this does not affect the meaning of well-formed code; +narrowing conversions are still considered ill-formed in \s-1SFINAE\s0 contexts. +.Sp +With \fB\-Wnarrowing\fR in \*(C+98, warn when a narrowing +conversion prohibited by \*(C+11 occurs within +\&\fB{ }\fR, e.g. +.Sp +.Vb 1 +\& int i = { 2.2 }; // error: narrowing from double to int +.Ve +.Sp +This flag is included in \fB\-Wall\fR and \fB\-Wc++11\-compat\fR. +.IP "\fB\-Wnoexcept\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnoexcept ( and Objective- only)" +Warn when a noexcept-expression evaluates to false because of a call +to a function that does not have a non-throwing exception +specification (i.e. \f(CW\*(C`throw()\*(C'\fR or \f(CW\*(C`noexcept\*(C'\fR) but is known by +the compiler to never throw an exception. +.IP "\fB\-Wnoexcept\-type\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnoexcept-type ( and Objective- only)" +Warn if the \*(C+17 feature making \f(CW\*(C`noexcept\*(C'\fR part of a function +type changes the mangled name of a symbol relative to \*(C+14. Enabled +by \fB\-Wabi\fR and \fB\-Wc++17\-compat\fR. +.Sp +As an example: +.Sp +.Vb 3 +\& template void f(T t) { t(); }; +\& void g() noexcept; +\& void h() { f(g); } +.Ve +.Sp +In \*(C+14, \f(CW\*(C`f\*(C'\fR calls \f(CW\*(C`f\*(C'\fR, but in +\&\*(C+17 it calls \f(CW\*(C`f\*(C'\fR. +.IP "\fB\-Wclass\-memaccess\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wclass-memaccess ( and Objective- only)" +Warn when the destination of a call to a raw memory function such as +\&\f(CW\*(C`memset\*(C'\fR or \f(CW\*(C`memcpy\*(C'\fR is an object of class type, and when writing +into such an object might bypass the class non-trivial or deleted constructor +or copy assignment, violate const-correctness or encapsulation, or corrupt +virtual table pointers. Modifying the representation of such objects may +violate invariants maintained by member functions of the class. For example, +the call to \f(CW\*(C`memset\*(C'\fR below is undefined because it modifies a non-trivial +class object and is, therefore, diagnosed. The safe way to either initialize +or clear the storage of objects of such types is by using the appropriate +constructor or assignment operator, if one is available. +.Sp +.Vb 2 +\& std::string str = "abc"; +\& memset (&str, 0, sizeof str); +.Ve +.Sp +The \fB\-Wclass\-memaccess\fR option is enabled by \fB\-Wall\fR. +Explicitly casting the pointer to the class object to \f(CW\*(C`void *\*(C'\fR or +to a type that can be safely accessed by the raw memory function suppresses +the warning. +.IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnon-virtual-dtor ( and Objective- only)" +Warn when a class has virtual functions and an accessible non-virtual +destructor itself or in an accessible polymorphic base class, in which +case it is possible but unsafe to delete an instance of a derived +class through a pointer to the class itself or base class. This +warning is automatically enabled if \fB\-Weffc++\fR is specified. +.IP "\fB\-Wregister\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wregister ( and Objective- only)" +Warn on uses of the \f(CW\*(C`register\*(C'\fR storage class specifier, except +when it is part of the \s-1GNU\s0 \fBExplicit Register Variables\fR extension. +The use of the \f(CW\*(C`register\*(C'\fR keyword as storage class specifier has +been deprecated in \*(C+11 and removed in \*(C+17. +Enabled by default with \fB\-std=c++17\fR. +.IP "\fB\-Wreorder\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wreorder ( and Objective- only)" +Warn when the order of member initializers given in the code does not +match the order in which they must be executed. For instance: +.Sp +.Vb 5 +\& struct A { +\& int i; +\& int j; +\& A(): j (0), i (1) { } +\& }; +.Ve +.Sp +The compiler rearranges the member initializers for \f(CW\*(C`i\*(C'\fR +and \f(CW\*(C`j\*(C'\fR to match the declaration order of the members, emitting +a warning to that effect. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-pessimizing\-move\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-pessimizing-move ( and Objective- only)" +This warning warns when a call to \f(CW\*(C`std::move\*(C'\fR prevents copy +elision. A typical scenario when copy elision can occur is when returning in +a function with a class return type, when the expression being returned is the +name of a non-volatile automatic object, and is not a function parameter, and +has the same type as the function return type. +.Sp +.Vb 9 +\& struct T { +\& ... +\& }; +\& T fn() +\& { +\& T t; +\& ... +\& return std::move (t); +\& } +.Ve +.Sp +But in this example, the \f(CW\*(C`std::move\*(C'\fR call prevents copy elision. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-redundant\-move\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-redundant-move ( and Objective- only)" +This warning warns about redundant calls to \f(CW\*(C`std::move\*(C'\fR; that is, when +a move operation would have been performed even without the \f(CW\*(C`std::move\*(C'\fR +call. This happens because the compiler is forced to treat the object as if +it were an rvalue in certain situations such as returning a local variable, +where copy elision isn't applicable. Consider: +.Sp +.Vb 8 +\& struct T { +\& ... +\& }; +\& T fn(T t) +\& { +\& ... +\& return std::move (t); +\& } +.Ve +.Sp +Here, the \f(CW\*(C`std::move\*(C'\fR call is redundant. Because G++ implements Core +Issue 1579, another example is: +.Sp +.Vb 12 +\& struct T { // convertible to U +\& ... +\& }; +\& struct U { +\& ... +\& }; +\& U fn() +\& { +\& T t; +\& ... +\& return std::move (t); +\& } +.Ve +.Sp +In this example, copy elision isn't applicable because the type of the +expression being returned and the function return type differ, yet G++ +treats the return value as if it were designated by an rvalue. +.Sp +This warning is enabled by \fB\-Wextra\fR. +.IP "\fB\-fext\-numeric\-literals\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-fext-numeric-literals ( and Objective- only)" +Accept imaginary, fixed-point, or machine-defined +literal number suffixes as \s-1GNU\s0 extensions. +When this option is turned off these suffixes are treated +as \*(C+11 user-defined literal numeric suffixes. +This is on by default for all pre\-\*(C+11 dialects and all \s-1GNU\s0 dialects: +\&\fB\-std=c++98\fR, \fB\-std=gnu++98\fR, \fB\-std=gnu++11\fR, +\&\fB\-std=gnu++14\fR. +This option is off by default +for \s-1ISO \*(C+11\s0 onwards (\fB\-std=c++11\fR, ...). +.PP +The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. +.IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Weffc++ ( and Objective- only)" +Warn about violations of the following style guidelines from Scott Meyers' +\&\fIEffective \*(C+\fR series of books: +.RS 4 +.IP "*" 4 +Define a copy constructor and an assignment operator for classes +with dynamically-allocated memory. +.IP "*" 4 +Prefer initialization to assignment in constructors. +.IP "*" 4 +Have \f(CW\*(C`operator=\*(C'\fR return a reference to \f(CW*this\fR. +.IP "*" 4 +Don't try to return a reference when you must return an object. +.IP "*" 4 +Distinguish between prefix and postfix forms of increment and +decrement operators. +.IP "*" 4 +Never overload \f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, or \f(CW\*(C`,\*(C'\fR. +.RE +.RS 4 +.Sp +This option also enables \fB\-Wnon\-virtual\-dtor\fR, which is also +one of the effective \*(C+ recommendations. However, the check is +extended to warn about the lack of virtual destructor in accessible +non-polymorphic bases classes too. +.Sp +When selecting this option, be aware that the standard library +headers do not obey all of these guidelines; use \fBgrep \-v\fR +to filter out those warnings. +.RE +.IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-null-sentinel ( and Objective- only)" +Warn about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When +compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined +to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant rather than a +null pointer, it is guaranteed to be of the same size as a pointer. +But this use is not portable across different compilers. +.IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-non-template-friend ( and Objective- only)" +Disable warnings when non-template friend functions are declared +within a template. In very old versions of \s-1GCC\s0 that predate implementation +of the \s-1ISO\s0 standard, declarations such as +\&\fBfriend int foo(int)\fR, where the name of the friend is an unqualified-id, +could be interpreted as a particular specialization of a template +function; the warning exists to diagnose compatibility problems, +and is enabled by default. +.IP "\fB\-Wold\-style\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wold-style-cast ( and Objective- only)" +Warn if an old-style (C\-style) cast to a non-void type is used within +a \*(C+ program. The new-style casts (\f(CW\*(C`dynamic_cast\*(C'\fR, +\&\f(CW\*(C`static_cast\*(C'\fR, \f(CW\*(C`reinterpret_cast\*(C'\fR, and \f(CW\*(C`const_cast\*(C'\fR) are +less vulnerable to unintended effects and much easier to search for. +.IP "\fB\-Woverloaded\-virtual\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Woverloaded-virtual ( and Objective- only)" +Warn when a function declaration hides virtual functions from a +base class. For example, in: +.Sp +.Vb 3 +\& struct A { +\& virtual void f(); +\& }; +\& +\& struct B: public A { +\& void f(int); +\& }; +.Ve +.Sp +the \f(CW\*(C`A\*(C'\fR class version of \f(CW\*(C`f\*(C'\fR is hidden in \f(CW\*(C`B\*(C'\fR, and code +like: +.Sp +.Vb 2 +\& B* b; +\& b\->f(); +.Ve +.Sp +fails to compile. +.IP "\fB\-Wno\-pmf\-conversions\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-pmf-conversions ( and Objective- only)" +Disable the diagnostic for converting a bound pointer to member function +to a plain pointer. +.IP "\fB\-Wsign\-promo\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsign-promo ( and Objective- only)" +Warn when overload resolution chooses a promotion from unsigned or +enumerated type to a signed type, over a conversion to an unsigned type of +the same size. Previous versions of G++ tried to preserve +unsignedness, but the standard mandates the current behavior. +.IP "\fB\-Wtemplates\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wtemplates ( and Objective- only)" +Warn when a primary template declaration is encountered. Some coding +rules disallow templates, and this may be used to enforce that rule. +The warning is inactive inside a system header file, such as the \s-1STL,\s0 so +one can still use the \s-1STL.\s0 One may also instantiate or specialize +templates. +.IP "\fB\-Wmultiple\-inheritance\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wmultiple-inheritance ( and Objective- only)" +Warn when a class is defined with multiple direct base classes. Some +coding rules disallow multiple inheritance, and this may be used to +enforce that rule. The warning is inactive inside a system header file, +such as the \s-1STL,\s0 so one can still use the \s-1STL.\s0 One may also define +classes that indirectly use multiple inheritance. +.IP "\fB\-Wvirtual\-inheritance\fR" 4 +.IX Item "-Wvirtual-inheritance" +Warn when a class is defined with a virtual direct base class. Some +coding rules disallow multiple inheritance, and this may be used to +enforce that rule. The warning is inactive inside a system header file, +such as the \s-1STL,\s0 so one can still use the \s-1STL.\s0 One may also define +classes that indirectly use virtual inheritance. +.IP "\fB\-Wnamespaces\fR" 4 +.IX Item "-Wnamespaces" +Warn when a namespace definition is opened. Some coding rules disallow +namespaces, and this may be used to enforce that rule. The warning is +inactive inside a system header file, such as the \s-1STL,\s0 so one can still +use the \s-1STL.\s0 One may also use using directives and qualified names. +.IP "\fB\-Wno\-terminate\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-terminate ( and Objective- only)" +Disable the warning about a throw-expression that will immediately +result in a call to \f(CW\*(C`terminate\*(C'\fR. +.IP "\fB\-Wno\-class\-conversion\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-class-conversion ( and Objective- only)" +Disable the warning about the case when a conversion function converts an +object to the same type, to a base class of that type, or to void; such +a conversion function will never be called. +.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.IX Subsection "Options Controlling Objective-C and Objective- Dialects" +(\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ +languages themselves. +.PP +This section describes the command-line options that are only meaningful +for Objective-C and Objective\-\*(C+ programs. You can also use most of +the language-independent \s-1GNU\s0 compiler options. +For example, you might compile a file \fIsome_class.m\fR like this: +.PP +.Vb 1 +\& gcc \-g \-fgnu\-runtime \-O \-c some_class.m +.Ve +.PP +In this example, \fB\-fgnu\-runtime\fR is an option meant only for +Objective-C and Objective\-\*(C+ programs; you can use the other options with +any language supported by \s-1GCC.\s0 +.PP +Note that since Objective-C is an extension of the C language, Objective-C +compilations may also use options specific to the C front-end (e.g., +\&\fB\-Wtraditional\fR). Similarly, Objective\-\*(C+ compilations may use +\&\*(C+\-specific options (e.g., \fB\-Wabi\fR). +.PP +Here is a list of options that are \fIonly\fR for compiling Objective-C +and Objective\-\*(C+ programs: +.IP "\fB\-fconstant\-string\-class=\fR\fIclass-name\fR" 4 +.IX Item "-fconstant-string-class=class-name" +Use \fIclass-name\fR as the name of the class to instantiate for each +literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default +class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and +\&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below). The +\&\fB\-fconstant\-cfstrings\fR option, if also present, overrides the +\&\fB\-fconstant\-string\-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals +to be laid out as constant CoreFoundation strings. +.IP "\fB\-fgnu\-runtime\fR" 4 +.IX Item "-fgnu-runtime" +Generate object code compatible with the standard \s-1GNU\s0 Objective-C +runtime. This is the default for most types of systems. +.IP "\fB\-fnext\-runtime\fR" 4 +.IX Item "-fnext-runtime" +Generate output compatible with the NeXT runtime. This is the default +for NeXT-based systems, including Darwin and Mac \s-1OS X.\s0 The macro +\&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is +used. +.IP "\fB\-fno\-nil\-receivers\fR" 4 +.IX Item "-fno-nil-receivers" +Assume that all Objective-C message dispatches (\f(CW\*(C`[receiver +message:arg]\*(C'\fR) in this translation unit ensure that the receiver is +not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the +runtime to be used. This option is only available in conjunction with +the NeXT runtime and \s-1ABI\s0 version 0 or 1. +.IP "\fB\-fobjc\-abi\-version=\fR\fIn\fR" 4 +.IX Item "-fobjc-abi-version=n" +Use version \fIn\fR of the Objective-C \s-1ABI\s0 for the selected runtime. +This option is currently supported only for the NeXT runtime. In that +case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for +properties and other Objective-C 2.0 additions. Version 1 is the +traditional (32\-bit) \s-1ABI\s0 with support for properties and other +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI.\s0 If +nothing is specified, the default is Version 0 on 32\-bit target +machines, and Version 2 on 64\-bit target machines. +.IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 +.IX Item "-fobjc-call-cxx-cdtors" +For each Objective-C class, check if any of its instance variables is a +\&\*(C+ object with a non-trivial default constructor. If so, synthesize a +special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method which runs +non-trivial default constructors on any such instance variables, in order, +and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable +is a \*(C+ object with a non-trivial destructor, and if so, synthesize a +special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method which runs +all such default destructors, in reverse order. +.Sp +The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR +methods thusly generated only operate on instance variables +declared in the current Objective-C class, and not those inherited +from superclasses. It is the responsibility of the Objective-C +runtime to invoke all such methods in an object's inheritance +hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods are invoked +by the runtime immediately after a new object instance is allocated; +the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods are invoked immediately +before the runtime deallocates an object instance. +.Sp +As of this writing, only the NeXT runtime on Mac \s-1OS X 10.4\s0 and later has +support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and +\&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. +.IP "\fB\-fobjc\-direct\-dispatch\fR" 4 +.IX Item "-fobjc-direct-dispatch" +Allow fast jumps to the message dispatcher. On Darwin this is +accomplished via the comm page. +.IP "\fB\-fobjc\-exceptions\fR" 4 +.IX Item "-fobjc-exceptions" +Enable syntactic support for structured exception handling in +Objective-C, similar to what is offered by \*(C+. This option +is required to use the Objective-C keywords \f(CW@try\fR, +\&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and +\&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 +runtime and the NeXT runtime (but not available in conjunction with +the NeXT runtime on Mac \s-1OS X 10.2\s0 and earlier). +.IP "\fB\-fobjc\-gc\fR" 4 +.IX Item "-fobjc-gc" +Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ +programs. This option is only available with the NeXT runtime; the +\&\s-1GNU\s0 runtime has a different garbage collection implementation that +does not require special compiler flags. +.IP "\fB\-fobjc\-nilcheck\fR" 4 +.IX Item "-fobjc-nilcheck" +For the NeXT runtime with version 2 of the \s-1ABI,\s0 check for a nil +receiver in method invocations before doing the actual method call. +This is the default and can be disabled using +\&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never +checked for nil in this way no matter what this flag is set to. +Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older +version of the NeXT runtime \s-1ABI,\s0 is used. +.IP "\fB\-fobjc\-std=objc1\fR" 4 +.IX Item "-fobjc-std=objc1" +Conform to the language syntax of Objective-C 1.0, the language +recognized by \s-1GCC 4.0.\s0 This only affects the Objective-C additions to +the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, +which is controlled by the separate C/\*(C+ dialect option flags. When +this option is used with the Objective-C or Objective\-\*(C+ compiler, +any Objective-C syntax that is not recognized by \s-1GCC 4.0\s0 is rejected. +This is useful if you need to make sure that your Objective-C code can +be compiled with older versions of \s-1GCC.\s0 +.IP "\fB\-freplace\-objc\-classes\fR" 4 +.IX Item "-freplace-objc-classes" +Emit a special marker instructing \fB\fBld\fB\|(1)\fR not to statically link in +the resulting object file, and allow \fB\fBdyld\fB\|(1)\fR to load it in at +run time instead. This is used in conjunction with the Fix-and-Continue +debugging mode, where the object file in question may be recompiled and +dynamically reloaded in the course of program execution, without the need +to restart the program itself. Currently, Fix-and-Continue functionality +is only available in conjunction with the NeXT runtime on Mac \s-1OS X 10.3\s0 +and later. +.IP "\fB\-fzero\-link\fR" 4 +.IX Item "-fzero-link" +When compiling for the NeXT runtime, the compiler ordinarily replaces calls +to \f(CW\*(C`objc_getClass("...")\*(C'\fR (when the name of the class is known at +compile time) with static class references that get initialized at load time, +which improves run-time performance. Specifying the \fB\-fzero\-link\fR flag +suppresses this behavior and causes calls to \f(CW\*(C`objc_getClass("...")\*(C'\fR +to be retained. This is useful in Zero-Link debugging mode, since it allows +for individual class implementations to be modified during program execution. +The \s-1GNU\s0 runtime currently always retains calls to \f(CW\*(C`objc_get_class("...")\*(C'\fR +regardless of command-line options. +.IP "\fB\-fno\-local\-ivars\fR" 4 +.IX Item "-fno-local-ivars" +By default instance variables in Objective-C can be accessed as if +they were local variables from within the methods of the class they're +declared in. This can lead to shadowing between instance variables +and other variables declared either locally inside a class method or +globally with the same name. Specifying the \fB\-fno\-local\-ivars\fR +flag disables this behavior thus avoiding variable shadowing issues. +.IP "\fB\-fivar\-visibility=\fR[\fBpublic\fR|\fBprotected\fR|\fBprivate\fR|\fBpackage\fR]" 4 +.IX Item "-fivar-visibility=[public|protected|private|package]" +Set the default instance variable visibility to the specified option +so that instance variables declared outside the scope of any access +modifier directives default to the specified visibility. +.IP "\fB\-gen\-decls\fR" 4 +.IX Item "-gen-decls" +Dump interface declarations for all classes seen in the source file to a +file named \fI\fIsourcename\fI.decl\fR. +.IP "\fB\-Wassign\-intercept\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wassign-intercept (Objective-C and Objective- only)" +Warn whenever an Objective-C assignment is being intercepted by the +garbage collector. +.IP "\fB\-Wno\-protocol\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-protocol (Objective-C and Objective- only)" +If a class is declared to implement a protocol, a warning is issued for +every method in the protocol that is not implemented by the class. The +default behavior is to issue a warning for every method not explicitly +implemented in the class, even if a method implementation is inherited +from the superclass. If you use the \fB\-Wno\-protocol\fR option, then +methods inherited from the superclass are considered to be implemented, +and no warning is issued for them. +.IP "\fB\-Wselector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wselector (Objective-C and Objective- only)" +Warn if multiple methods of different types for the same selector are +found during compilation. The check is performed on the list of methods +in the final stage of compilation. Additionally, a check is performed +for each selector appearing in a \f(CW\*(C`@selector(...)\*(C'\fR +expression, and a corresponding method for that selector has been found +during compilation. Because these checks scan the method table only at +the end of compilation, these warnings are not produced if the final +stage of compilation is not reached, for example because an error is +found during compilation, or because the \fB\-fsyntax\-only\fR option is +being used. +.IP "\fB\-Wstrict\-selector\-match\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-selector-match (Objective-C and Objective- only)" +Warn if multiple methods with differing argument and/or return types are +found for a given selector when attempting to send a message using this +selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag +is off (which is the default behavior), the compiler omits such warnings +if any differences found are confined to types that share the same size +and alignment. +.IP "\fB\-Wundeclared\-selector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wundeclared-selector (Objective-C and Objective- only)" +Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an +undeclared selector is found. A selector is considered undeclared if no +method with that name has been declared before the +\&\f(CW\*(C`@selector(...)\*(C'\fR expression, either explicitly in an +\&\f(CW@interface\fR or \f(CW@protocol\fR declaration, or implicitly in +an \f(CW@implementation\fR section. This option always performs its +checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found, +while \fB\-Wselector\fR only performs its checks in the final stage of +compilation. This also enforces the coding style convention +that methods and selectors must be declared before being used. +.IP "\fB\-print\-objc\-runtime\-info\fR" 4 +.IX Item "-print-objc-runtime-info" +Generate C header describing the largest structure that is passed by +value, if any. +.SS "Options to Control Diagnostic Messages Formatting" +.IX Subsection "Options to Control Diagnostic Messages Formatting" +Traditionally, diagnostic messages have been formatted irrespective of +the output device's aspect (e.g. its width, ...). You can use the +options described below +to control the formatting algorithm for diagnostic messages, +e.g. how many characters per line, how often source location +information should be reported. Note that some language front ends may not +honor these options. +.IP "\fB\-fmessage\-length=\fR\fIn\fR" 4 +.IX Item "-fmessage-length=n" +Try to format error messages so that they fit on lines of about +\&\fIn\fR characters. If \fIn\fR is zero, then no line-wrapping is +done; each error message appears on a single line. This is the +default for all front ends. +.Sp +Note \- this option also affects the display of the \fB#error\fR and +\&\fB#warning\fR pre-processor directives, and the \fBdeprecated\fR +function/type/variable attribute. It does not however affect the +\&\fBpragma \s-1GCC\s0 warning\fR and \fBpragma \s-1GCC\s0 error\fR pragmas. +.IP "\fB\-fdiagnostics\-show\-location=once\fR" 4 +.IX Item "-fdiagnostics-show-location=once" +Only meaningful in line-wrapping mode. Instructs the diagnostic messages +reporter to emit source location information \fIonce\fR; that is, in +case the message is too long to fit on a single physical line and has to +be wrapped, the source location won't be emitted (as prefix) again, +over and over, in subsequent continuation lines. This is the default +behavior. +.IP "\fB\-fdiagnostics\-show\-location=every\-line\fR" 4 +.IX Item "-fdiagnostics-show-location=every-line" +Only meaningful in line-wrapping mode. Instructs the diagnostic +messages reporter to emit the same source location information (as +prefix) for physical lines that result from the process of breaking +a message which is too long to fit on a single line. +.IP "\fB\-fdiagnostics\-color[=\fR\fI\s-1WHEN\s0\fR\fB]\fR" 4 +.IX Item "-fdiagnostics-color[=WHEN]" +.PD 0 +.IP "\fB\-fno\-diagnostics\-color\fR" 4 +.IX Item "-fno-diagnostics-color" +.PD +Use color in diagnostics. \fI\s-1WHEN\s0\fR is \fBnever\fR, \fBalways\fR, +or \fBauto\fR. The default depends on how the compiler has been configured, +it can be any of the above \fI\s-1WHEN\s0\fR options or also \fBnever\fR +if \fB\s-1GCC_COLORS\s0\fR environment variable isn't present in the environment, +and \fBauto\fR otherwise. +\&\fBauto\fR means to use color only when the standard error is a terminal. +The forms \fB\-fdiagnostics\-color\fR and \fB\-fno\-diagnostics\-color\fR are +aliases for \fB\-fdiagnostics\-color=always\fR and +\&\fB\-fdiagnostics\-color=never\fR, respectively. +.Sp +The colors are defined by the environment variable \fB\s-1GCC_COLORS\s0\fR. +Its value is a colon-separated list of capabilities and Select Graphic +Rendition (\s-1SGR\s0) substrings. \s-1SGR\s0 commands are interpreted by the +terminal or terminal emulator. (See the section in the documentation +of your text terminal for permitted values and their meanings as +character attributes.) These substring values are integers in decimal +representation and can be concatenated with semicolons. +Common values to concatenate include +\&\fB1\fR for bold, +\&\fB4\fR for underline, +\&\fB5\fR for blink, +\&\fB7\fR for inverse, +\&\fB39\fR for default foreground color, +\&\fB30\fR to \fB37\fR for foreground colors, +\&\fB90\fR to \fB97\fR for 16\-color mode foreground colors, +\&\fB38;5;0\fR to \fB38;5;255\fR +for 88\-color and 256\-color modes foreground colors, +\&\fB49\fR for default background color, +\&\fB40\fR to \fB47\fR for background colors, +\&\fB100\fR to \fB107\fR for 16\-color mode background colors, +and \fB48;5;0\fR to \fB48;5;255\fR +for 88\-color and 256\-color modes background colors. +.Sp +The default \fB\s-1GCC_COLORS\s0\fR is +.Sp +.Vb 4 +\& error=01;31:warning=01;35:note=01;36:range1=32:range2=34:locus=01:\e +\& quote=01:fixit\-insert=32:fixit\-delete=31:\e +\& diff\-filename=01:diff\-hunk=32:diff\-delete=31:diff\-insert=32:\e +\& type\-diff=01;32 +.Ve +.Sp +where \fB01;31\fR is bold red, \fB01;35\fR is bold magenta, +\&\fB01;36\fR is bold cyan, \fB32\fR is green, \fB34\fR is blue, +\&\fB01\fR is bold, and \fB31\fR is red. +Setting \fB\s-1GCC_COLORS\s0\fR to the empty string disables colors. +Supported capabilities are as follows. +.RS 4 +.ie n .IP """error=""" 4 +.el .IP "\f(CWerror=\fR" 4 +.IX Item "error=" +\&\s-1SGR\s0 substring for error: markers. +.ie n .IP """warning=""" 4 +.el .IP "\f(CWwarning=\fR" 4 +.IX Item "warning=" +\&\s-1SGR\s0 substring for warning: markers. +.ie n .IP """note=""" 4 +.el .IP "\f(CWnote=\fR" 4 +.IX Item "note=" +\&\s-1SGR\s0 substring for note: markers. +.ie n .IP """range1=""" 4 +.el .IP "\f(CWrange1=\fR" 4 +.IX Item "range1=" +\&\s-1SGR\s0 substring for first additional range. +.ie n .IP """range2=""" 4 +.el .IP "\f(CWrange2=\fR" 4 +.IX Item "range2=" +\&\s-1SGR\s0 substring for second additional range. +.ie n .IP """locus=""" 4 +.el .IP "\f(CWlocus=\fR" 4 +.IX Item "locus=" +\&\s-1SGR\s0 substring for location information, \fBfile:line\fR or +\&\fBfile:line:column\fR etc. +.ie n .IP """quote=""" 4 +.el .IP "\f(CWquote=\fR" 4 +.IX Item "quote=" +\&\s-1SGR\s0 substring for information printed within quotes. +.ie n .IP """fixit\-insert=""" 4 +.el .IP "\f(CWfixit\-insert=\fR" 4 +.IX Item "fixit-insert=" +\&\s-1SGR\s0 substring for fix-it hints suggesting text to +be inserted or replaced. +.ie n .IP """fixit\-delete=""" 4 +.el .IP "\f(CWfixit\-delete=\fR" 4 +.IX Item "fixit-delete=" +\&\s-1SGR\s0 substring for fix-it hints suggesting text to +be deleted. +.ie n .IP """diff\-filename=""" 4 +.el .IP "\f(CWdiff\-filename=\fR" 4 +.IX Item "diff-filename=" +\&\s-1SGR\s0 substring for filename headers within generated patches. +.ie n .IP """diff\-hunk=""" 4 +.el .IP "\f(CWdiff\-hunk=\fR" 4 +.IX Item "diff-hunk=" +\&\s-1SGR\s0 substring for the starts of hunks within generated patches. +.ie n .IP """diff\-delete=""" 4 +.el .IP "\f(CWdiff\-delete=\fR" 4 +.IX Item "diff-delete=" +\&\s-1SGR\s0 substring for deleted lines within generated patches. +.ie n .IP """diff\-insert=""" 4 +.el .IP "\f(CWdiff\-insert=\fR" 4 +.IX Item "diff-insert=" +\&\s-1SGR\s0 substring for inserted lines within generated patches. +.ie n .IP """type\-diff=""" 4 +.el .IP "\f(CWtype\-diff=\fR" 4 +.IX Item "type-diff=" +\&\s-1SGR\s0 substring for highlighting mismatching types within template +arguments in the \*(C+ frontend. +.RE +.RS 4 +.RE +.IP "\fB\-fno\-diagnostics\-show\-option\fR" 4 +.IX Item "-fno-diagnostics-show-option" +By default, each diagnostic emitted includes text indicating the +command-line option that directly controls the diagnostic (if such an +option is known to the diagnostic machinery). Specifying the +\&\fB\-fno\-diagnostics\-show\-option\fR flag suppresses that behavior. +.IP "\fB\-fno\-diagnostics\-show\-caret\fR" 4 +.IX Item "-fno-diagnostics-show-caret" +By default, each diagnostic emitted includes the original source line +and a caret \fB^\fR indicating the column. This option suppresses this +information. The source line is truncated to \fIn\fR characters, if +the \fB\-fmessage\-length=n\fR option is given. When the output is done +to the terminal, the width is limited to the width given by the +\&\fB\s-1COLUMNS\s0\fR environment variable or, if not set, to the terminal width. +.IP "\fB\-fno\-diagnostics\-show\-labels\fR" 4 +.IX Item "-fno-diagnostics-show-labels" +By default, when printing source code (via \fB\-fdiagnostics\-show\-caret\fR), +diagnostics can label ranges of source code with pertinent information, such +as the types of expressions: +.Sp +.Vb 4 +\& printf ("foo %s bar", long_i + long_j); +\& ~^ ~~~~~~~~~~~~~~~ +\& | | +\& char * long int +.Ve +.Sp +This option suppresses the printing of these labels (in the example above, +the vertical bars and the \*(L"char *\*(R" and \*(L"long int\*(R" text). +.IP "\fB\-fno\-diagnostics\-show\-line\-numbers\fR" 4 +.IX Item "-fno-diagnostics-show-line-numbers" +By default, when printing source code (via \fB\-fdiagnostics\-show\-caret\fR), +a left margin is printed, showing line numbers. This option suppresses this +left margin. +.IP "\fB\-fdiagnostics\-minimum\-margin\-width=\fR\fIwidth\fR" 4 +.IX Item "-fdiagnostics-minimum-margin-width=width" +This option controls the minimum width of the left margin printed by +\&\fB\-fdiagnostics\-show\-line\-numbers\fR. It defaults to 6. +.IP "\fB\-fdiagnostics\-parseable\-fixits\fR" 4 +.IX Item "-fdiagnostics-parseable-fixits" +Emit fix-it hints in a machine-parseable format, suitable for consumption +by IDEs. For each fix-it, a line will be printed after the relevant +diagnostic, starting with the string \*(L"fix-it:\*(R". For example: +.Sp +.Vb 1 +\& fix\-it:"test.c":{45:3\-45:21}:"gtk_widget_show_all" +.Ve +.Sp +The location is expressed as a half-open range, expressed as a count of +bytes, starting at byte 1 for the initial column. In the above example, +bytes 3 through 20 of line 45 of \*(L"test.c\*(R" are to be replaced with the +given string: +.Sp +.Vb 5 +\& 00000000011111111112222222222 +\& 12345678901234567890123456789 +\& gtk_widget_showall (dlg); +\& ^^^^^^^^^^^^^^^^^^ +\& gtk_widget_show_all +.Ve +.Sp +The filename and replacement string escape backslash as \*(L"\e\e\*(R", tab as \*(L"\et\*(R", +newline as \*(L"\en\*(R", double quotes as \*(L"\e\*(R"\*(L", non-printable characters as octal +(e.g. vertical tab as \*(R"\e013"). +.Sp +An empty replacement string indicates that the given range is to be removed. +An empty range (e.g. \*(L"45:3\-45:3\*(R") indicates that the string is to +be inserted at the given position. +.IP "\fB\-fdiagnostics\-generate\-patch\fR" 4 +.IX Item "-fdiagnostics-generate-patch" +Print fix-it hints to stderr in unified diff format, after any diagnostics +are printed. For example: +.Sp +.Vb 3 +\& \-\-\- test.c +\& +++ test.c +\& @ \-42,5 +42,5 @ +\& +\& void show_cb(GtkDialog *dlg) +\& { +\& \- gtk_widget_showall(dlg); +\& + gtk_widget_show_all(dlg); +\& } +.Ve +.Sp +The diff may or may not be colorized, following the same rules +as for diagnostics (see \fB\-fdiagnostics\-color\fR). +.IP "\fB\-fdiagnostics\-show\-template\-tree\fR" 4 +.IX Item "-fdiagnostics-show-template-tree" +In the \*(C+ frontend, when printing diagnostics showing mismatching +template types, such as: +.Sp +.Vb 2 +\& could not convert \*(Aqstd::map >()\*(Aq +\& from \*(Aqmap<[...],vector>\*(Aq to \*(Aqmap<[...],vector> +.Ve +.Sp +the \fB\-fdiagnostics\-show\-template\-tree\fR flag enables printing a +tree-like structure showing the common and differing parts of the types, +such as: +.Sp +.Vb 4 +\& map< +\& [...], +\& vector< +\& [double != float]>> +.Ve +.Sp +The parts that differ are highlighted with color (\*(L"double\*(R" and +\&\*(L"float\*(R" in this case). +.IP "\fB\-fno\-elide\-type\fR" 4 +.IX Item "-fno-elide-type" +By default when the \*(C+ frontend prints diagnostics showing mismatching +template types, common parts of the types are printed as \*(L"[...]\*(R" to +simplify the error message. For example: +.Sp +.Vb 2 +\& could not convert \*(Aqstd::map >()\*(Aq +\& from \*(Aqmap<[...],vector>\*(Aq to \*(Aqmap<[...],vector> +.Ve +.Sp +Specifying the \fB\-fno\-elide\-type\fR flag suppresses that behavior. +This flag also affects the output of the +\&\fB\-fdiagnostics\-show\-template\-tree\fR flag. +.IP "\fB\-fno\-show\-column\fR" 4 +.IX Item "-fno-show-column" +Do not print column numbers in diagnostics. This may be necessary if +diagnostics are being scanned by a program that does not understand the +column numbers, such as \fBdejagnu\fR. +.IP "\fB\-fdiagnostics\-format=\fR\fI\s-1FORMAT\s0\fR" 4 +.IX Item "-fdiagnostics-format=FORMAT" +Select a different format for printing diagnostics. +\&\fI\s-1FORMAT\s0\fR is \fBtext\fR or \fBjson\fR. +The default is \fBtext\fR. +.Sp +The \fBjson\fR format consists of a top-level \s-1JSON\s0 array containing \s-1JSON\s0 +objects representing the diagnostics. +.Sp +The \s-1JSON\s0 is emitted as one line, without formatting; the examples below +have been formatted for clarity. +.Sp +Diagnostics can have child diagnostics. For example, this error and note: +.Sp +.Vb 8 +\& misleading\-indentation.c:15:3: warning: this \*(Aqif\*(Aq clause does not +\& guard... [\-Wmisleading\-indentation] +\& 15 | if (flag) +\& | ^~ +\& misleading\-indentation.c:17:5: note: ...this statement, but the latter +\& is misleadingly indented as if it were guarded by the \*(Aqif\*(Aq +\& 17 | y = 2; +\& | ^ +.Ve +.Sp +might be printed in \s-1JSON\s0 form (after formatting) like this: +.Sp +.Vb 10 +\& [ +\& { +\& "kind": "warning", +\& "locations": [ +\& { +\& "caret": { +\& "column": 3, +\& "file": "misleading\-indentation.c", +\& "line": 15 +\& }, +\& "finish": { +\& "column": 4, +\& "file": "misleading\-indentation.c", +\& "line": 15 +\& } +\& } +\& ], +\& "message": "this \eu2018if\eu2019 clause does not guard...", +\& "option": "\-Wmisleading\-indentation", +\& "children": [ +\& { +\& "kind": "note", +\& "locations": [ +\& { +\& "caret": { +\& "column": 5, +\& "file": "misleading\-indentation.c", +\& "line": 17 +\& } +\& } +\& ], +\& "message": "...this statement, but the latter is ..." +\& } +\& ] +\& }, +\& ... +\& ] +.Ve +.Sp +where the \f(CW\*(C`note\*(C'\fR is a child of the \f(CW\*(C`warning\*(C'\fR. +.Sp +A diagnostic has a \f(CW\*(C`kind\*(C'\fR. If this is \f(CW\*(C`warning\*(C'\fR, then there is +an \f(CW\*(C`option\*(C'\fR key describing the command-line option controlling the +warning. +.Sp +A diagnostic can contain zero or more locations. Each location has up +to three positions within it: a \f(CW\*(C`caret\*(C'\fR position and optional +\&\f(CW\*(C`start\*(C'\fR and \f(CW\*(C`finish\*(C'\fR positions. A location can also have +an optional \f(CW\*(C`label\*(C'\fR string. For example, this error: +.Sp +.Vb 7 +\& bad\-binary\-ops.c:64:23: error: invalid operands to binary + (have \*(AqS\*(Aq {aka +\& \*(Aqstruct s\*(Aq} and \*(AqT\*(Aq {aka \*(Aqstruct t\*(Aq}) +\& 64 | return callee_4a () + callee_4b (); +\& | ~~~~~~~~~~~~ ^ ~~~~~~~~~~~~ +\& | | | +\& | | T {aka struct t} +\& | S {aka struct s} +.Ve +.Sp +has three locations. Its primary location is at the \*(L"+\*(R" token at column +23. It has two secondary locations, describing the left and right-hand sides +of the expression, which have labels. It might be printed in \s-1JSON\s0 form as: +.Sp +.Vb 10 +\& { +\& "children": [], +\& "kind": "error", +\& "locations": [ +\& { +\& "caret": { +\& "column": 23, "file": "bad\-binary\-ops.c", "line": 64 +\& } +\& }, +\& { +\& "caret": { +\& "column": 10, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "finish": { +\& "column": 21, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "label": "S {aka struct s}" +\& }, +\& { +\& "caret": { +\& "column": 25, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "finish": { +\& "column": 36, "file": "bad\-binary\-ops.c", "line": 64 +\& }, +\& "label": "T {aka struct t}" +\& } +\& ], +\& "message": "invalid operands to binary + ..." +\& } +.Ve +.Sp +If a diagnostic contains fix-it hints, it has a \f(CW\*(C`fixits\*(C'\fR array, +consisting of half-open intervals, similar to the output of +\&\fB\-fdiagnostics\-parseable\-fixits\fR. For example, this diagnostic +with a replacement fix-it hint: +.Sp +.Vb 5 +\& demo.c:8:15: error: \*(Aqstruct s\*(Aq has no member named \*(Aqcolour\*(Aq; did you +\& mean \*(Aqcolor\*(Aq? +\& 8 | return ptr\->colour; +\& | ^~~~~~ +\& | color +.Ve +.Sp +might be printed in \s-1JSON\s0 form as: +.Sp +.Vb 10 +\& { +\& "children": [], +\& "fixits": [ +\& { +\& "next": { +\& "column": 21, +\& "file": "demo.c", +\& "line": 8 +\& }, +\& "start": { +\& "column": 15, +\& "file": "demo.c", +\& "line": 8 +\& }, +\& "string": "color" +\& } +\& ], +\& "kind": "error", +\& "locations": [ +\& { +\& "caret": { +\& "column": 15, +\& "file": "demo.c", +\& "line": 8 +\& }, +\& "finish": { +\& "column": 20, +\& "file": "demo.c", +\& "line": 8 +\& } +\& } +\& ], +\& "message": "\eu2018struct s\eu2019 has no member named ..." +\& } +.Ve +.Sp +where the fix-it hint suggests replacing the text from \f(CW\*(C`start\*(C'\fR up +to but not including \f(CW\*(C`next\*(C'\fR with \f(CW\*(C`string\*(C'\fR's value. Deletions +are expressed via an empty value for \f(CW\*(C`string\*(C'\fR, insertions by +having \f(CW\*(C`start\*(C'\fR equal \f(CW\*(C`next\*(C'\fR. +.SS "Options to Request or Suppress Warnings" +.IX Subsection "Options to Request or Suppress Warnings" +Warnings are diagnostic messages that report constructions that +are not inherently erroneous but that are risky or suggest there +may have been an error. +.PP +The following language-independent options do not enable specific +warnings but control the kinds of diagnostics produced by \s-1GCC.\s0 +.IP "\fB\-fsyntax\-only\fR" 4 +.IX Item "-fsyntax-only" +Check the code for syntax errors, but don't do anything beyond that. +.IP "\fB\-fmax\-errors=\fR\fIn\fR" 4 +.IX Item "-fmax-errors=n" +Limits the maximum number of error messages to \fIn\fR, at which point +\&\s-1GCC\s0 bails out rather than attempting to continue processing the source +code. If \fIn\fR is 0 (the default), there is no limit on the number +of error messages produced. If \fB\-Wfatal\-errors\fR is also +specified, then \fB\-Wfatal\-errors\fR takes precedence over this +option. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Inhibit all warning messages. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into errors. +.IP "\fB\-Werror=\fR" 4 +.IX Item "-Werror=" +Make the specified warning into an error. The specifier for a warning +is appended; for example \fB\-Werror=switch\fR turns the warnings +controlled by \fB\-Wswitch\fR into errors. This switch takes a +negative form, to be used to negate \fB\-Werror\fR for specific +warnings; for example \fB\-Wno\-error=switch\fR makes +\&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR +is in effect. +.Sp +The warning message for each controllable warning includes the +option that controls the warning. That option can then be used with +\&\fB\-Werror=\fR and \fB\-Wno\-error=\fR as described above. +(Printing of the option in the warning message can be disabled using the +\&\fB\-fno\-diagnostics\-show\-option\fR flag.) +.Sp +Note that specifying \fB\-Werror=\fR\fIfoo\fR automatically implies +\&\fB\-W\fR\fIfoo\fR. However, \fB\-Wno\-error=\fR\fIfoo\fR does not +imply anything. +.IP "\fB\-Wfatal\-errors\fR" 4 +.IX Item "-Wfatal-errors" +This option causes the compiler to abort compilation on the first error +occurred rather than trying to keep going and printing further error +messages. +.PP +You can request many specific warnings with options beginning with +\&\fB\-W\fR, for example \fB\-Wimplicit\fR to request warnings on +implicit declarations. Each of these specific warning options also +has a negative form beginning \fB\-Wno\-\fR to turn off warnings; for +example, \fB\-Wno\-implicit\fR. This manual lists only one of the +two forms, whichever is not the default. For further +language-specific options also refer to \fB\*(C+ Dialect Options\fR and +\&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.PP +Some options, such as \fB\-Wall\fR and \fB\-Wextra\fR, turn on other +options, such as \fB\-Wunused\fR, which may turn on further options, +such as \fB\-Wunused\-value\fR. The combined effect of positive and +negative forms is that more specific options have priority over less +specific ones, independently of their position in the command-line. For +options of the same specificity, the last one takes effect. Options +enabled or disabled via pragmas take effect +as if they appeared at the end of the command-line. +.PP +When an unrecognized warning option is requested (e.g., +\&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 emits a diagnostic stating +that the option is not recognized. However, if the \fB\-Wno\-\fR form +is used, the behavior is slightly different: no diagnostic is +produced for \fB\-Wno\-unknown\-warning\fR unless other diagnostics +are being produced. This allows the use of new \fB\-Wno\-\fR options +with old compilers, but if something goes wrong, the compiler +warns that an unrecognized option is present. +.PP +The effectiveness of some warnings depends on optimizations also being +enabled. For example \fB\-Wsuggest\-final\-types\fR is more effective +with link-time optimization and \fB\-Wmaybe\-uninitialized\fR will not +warn at all unless optimization is enabled. +.IP "\fB\-Wpedantic\fR" 4 +.IX Item "-Wpedantic" +.PD 0 +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +.PD +Issue all the warnings demanded by strict \s-1ISO C\s0 and \s-1ISO \*(C+\s0; +reject all programs that use forbidden extensions, and some other +programs that do not follow \s-1ISO C\s0 and \s-1ISO \*(C+.\s0 For \s-1ISO C,\s0 follows the +version of the \s-1ISO C\s0 standard specified by any \fB\-std\fR option used. +.Sp +Valid \s-1ISO C\s0 and \s-1ISO \*(C+\s0 programs should compile properly with or without +this option (though a rare few require \fB\-ansi\fR or a +\&\fB\-std\fR option specifying the required version of \s-1ISO C\s0). However, +without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ +features are supported as well. With this option, they are rejected. +.Sp +\&\fB\-Wpedantic\fR does not cause warning messages for use of the +alternate keywords whose names begin and end with \fB_\|_\fR. Pedantic +warnings are also disabled in the expression that follows +\&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use +these escape routes; application programs should avoid them. +.Sp +Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO +C\s0 conformance. They soon find that it does not do quite what they want: +it finds some non-ISO practices, but not all\-\-\-only those for which +\&\s-1ISO C\s0 \fIrequires\fR a diagnostic, and some others for which +diagnostics have been added. +.Sp +A feature to report any failure to conform to \s-1ISO C\s0 might be useful in +some instances, but would require considerable additional work and would +be quite different from \fB\-Wpedantic\fR. We don't have plans to +support such a feature in the near future. +.Sp +Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 +extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a +corresponding \fIbase standard\fR, the version of \s-1ISO C\s0 on which the \s-1GNU\s0 +extended dialect is based. Warnings from \fB\-Wpedantic\fR are given +where they are required by the base standard. (It does not make sense +for such warnings to be given only for features not in the specified \s-1GNU +C\s0 dialect, since by definition the \s-1GNU\s0 dialects of C include all +features the compiler supports with the given option, and there would be +nothing to warn about.) +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Give an error whenever the \fIbase standard\fR (see \fB\-Wpedantic\fR) +requires a diagnostic, in some cases where there is undefined behavior +at compile-time and in some other cases that do not prevent compilation +of programs that are valid according to the standard. This is not +equivalent to \fB\-Werror=pedantic\fR, since there are errors enabled +by this option and not enabled by the latter and vice versa. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +This enables all the warnings about constructions that some users +consider questionable, and that are easy to avoid (or modify to +prevent the warning), even in conjunction with macros. This also +enables some language-specific warnings described in \fB\*(C+ Dialect +Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.Sp +\&\fB\-Wall\fR turns on the following warning flags: +.Sp +\&\fB\-Waddress +\&\-Warray\-bounds=1\fR (only with\fB \fR\fB\-O2\fR) +\&\fB\-Wbool\-compare +\&\-Wbool\-operation +\&\-Wc++11\-compat \-Wc++14\-compat +\&\-Wcatch\-value\fR (\*(C+ and Objective\-\*(C+ only) +\&\fB\-Wchar\-subscripts +\&\-Wcomment +\&\-Wduplicate\-decl\-specifier\fR (C and Objective-C only) +\&\fB\-Wenum\-compare\fR (in C/ObjC; this is on by default in \*(C+) +\&\fB\-Wformat +\&\-Wint\-in\-bool\-context +\&\-Wimplicit\fR (C and Objective-C only) +\&\fB\-Wimplicit\-int\fR (C and Objective-C only) +\&\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only) +\&\fB\-Winit\-self\fR (only for \*(C+) +\&\fB\-Wlogical\-not\-parentheses +\&\-Wmain\fR (only for C/ObjC and unless\fB \fR\fB\-ffreestanding\fR) +\&\fB\-Wmaybe\-uninitialized +\&\-Wmemset\-elt\-size +\&\-Wmemset\-transposed\-args +\&\-Wmisleading\-indentation\fR (only for C/\*(C+) +\&\fB\-Wmissing\-attributes +\&\-Wmissing\-braces\fR (only for C/ObjC) +\&\fB\-Wmultistatement\-macros +\&\-Wnarrowing\fR (only for \*(C+) +\&\fB\-Wnonnull +\&\-Wnonnull\-compare +\&\-Wopenmp\-simd +\&\-Wparentheses +\&\-Wpessimizing\-move\fR (only for \*(C+) +\&\fB\-Wpointer\-sign +\&\-Wreorder +\&\-Wrestrict +\&\-Wreturn\-type +\&\-Wsequence\-point +\&\-Wsign\-compare\fR (only in \*(C+) +\&\fB\-Wsizeof\-pointer\-div +\&\-Wsizeof\-pointer\-memaccess +\&\-Wstrict\-aliasing +\&\-Wstrict\-overflow=1 +\&\-Wswitch +\&\-Wtautological\-compare +\&\-Wtrigraphs +\&\-Wuninitialized +\&\-Wunknown\-pragmas +\&\-Wunused\-function +\&\-Wunused\-label +\&\-Wunused\-value +\&\-Wunused\-variable +\&\-Wvolatile\-register\-var\fR +.Sp +Note that some warning flags are not implied by \fB\-Wall\fR. Some of +them warn about constructions that users generally do not consider +questionable, but which occasionally you might wish to check for; +others warn about constructions that are necessary or hard to avoid in +some cases, and there is no simple way to modify the code to suppress +the warning. Some of them are enabled by \fB\-Wextra\fR but many of +them must be enabled individually. +.IP "\fB\-Wextra\fR" 4 +.IX Item "-Wextra" +This enables some extra warning flags that are not enabled by +\&\fB\-Wall\fR. (This option used to be called \fB\-W\fR. The older +name is still supported, but the newer name is more descriptive.) +.Sp +\&\fB\-Wclobbered +\&\-Wcast\-function\-type +\&\-Wdeprecated\-copy\fR (\*(C+ only) +\&\fB\-Wempty\-body +\&\-Wignored\-qualifiers +\&\-Wimplicit\-fallthrough=3 +\&\-Wmissing\-field\-initializers +\&\-Wmissing\-parameter\-type\fR (C only) +\&\fB\-Wold\-style\-declaration\fR (C only) +\&\fB\-Woverride\-init +\&\-Wsign\-compare\fR (C only) +\&\fB\-Wredundant\-move\fR (only for \*(C+) +\&\fB\-Wtype\-limits +\&\-Wuninitialized +\&\-Wshift\-negative\-value\fR (in \*(C+11 to \*(C+17 and in C99 and newer) +\&\fB\-Wunused\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) +\&\fB\-Wunused\-but\-set\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) +.Sp +The option \fB\-Wextra\fR also prints warning messages for the +following cases: +.RS 4 +.IP "*" 4 +A pointer is compared against integer zero with \f(CW\*(C`<\*(C'\fR, \f(CW\*(C`<=\*(C'\fR, +\&\f(CW\*(C`>\*(C'\fR, or \f(CW\*(C`>=\*(C'\fR. +.IP "*" 4 +(\*(C+ only) An enumerator and a non-enumerator both appear in a +conditional expression. +.IP "*" 4 +(\*(C+ only) Ambiguous virtual bases. +.IP "*" 4 +(\*(C+ only) Subscripting an array that has been declared \f(CW\*(C`register\*(C'\fR. +.IP "*" 4 +(\*(C+ only) Taking the address of a variable that has been declared +\&\f(CW\*(C`register\*(C'\fR. +.IP "*" 4 +(\*(C+ only) A base class is not initialized in the copy constructor +of a derived class. +.RE +.RS 4 +.RE +.IP "\fB\-Wchar\-subscripts\fR" 4 +.IX Item "-Wchar-subscripts" +Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR. This is a common cause +of error, as programmers often forget that this type is signed on some +machines. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-coverage\-mismatch\fR" 4 +.IX Item "-Wno-coverage-mismatch" +Warn if feedback profiles do not match when using the +\&\fB\-fprofile\-use\fR option. +If a source file is changed between compiling with \fB\-fprofile\-generate\fR +and with \fB\-fprofile\-use\fR, the files with the profile feedback can fail +to match the source file and \s-1GCC\s0 cannot use the profile feedback +information. By default, this warning is enabled and is treated as an +error. \fB\-Wno\-coverage\-mismatch\fR can be used to disable the +warning or \fB\-Wno\-error=coverage\-mismatch\fR can be used to +disable the error. Disabling the error for this warning can result in +poorly optimized code and is useful only in the +case of very minor changes such as bug fixes to an existing code-base. +Completely disabling the warning is not recommended. +.IP "\fB\-Wno\-cpp\fR" 4 +.IX Item "-Wno-cpp" +(C, Objective-C, \*(C+, Objective\-\*(C+ and Fortran only) +.Sp +Suppress warning messages emitted by \f(CW\*(C`#warning\*(C'\fR directives. +.IP "\fB\-Wdouble\-promotion\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wdouble-promotion (C, , Objective-C and Objective- only)" +Give a warning when a value of type \f(CW\*(C`float\*(C'\fR is implicitly +promoted to \f(CW\*(C`double\*(C'\fR. CPUs with a 32\-bit \*(L"single-precision\*(R" +floating-point unit implement \f(CW\*(C`float\*(C'\fR in hardware, but emulate +\&\f(CW\*(C`double\*(C'\fR in software. On such a machine, doing computations +using \f(CW\*(C`double\*(C'\fR values is much more expensive because of the +overhead required for software emulation. +.Sp +It is easy to accidentally do computations with \f(CW\*(C`double\*(C'\fR because +floating-point literals are implicitly of type \f(CW\*(C`double\*(C'\fR. For +example, in: +.Sp +.Vb 4 +\& float area(float radius) +\& { +\& return 3.14159 * radius * radius; +\& } +.Ve +.Sp +the compiler performs the entire computation with \f(CW\*(C`double\*(C'\fR +because the floating-point literal is a \f(CW\*(C`double\*(C'\fR. +.IP "\fB\-Wduplicate\-decl\-specifier\fR (C and Objective-C only)" 4 +.IX Item "-Wduplicate-decl-specifier (C and Objective-C only)" +Warn if a declaration has duplicate \f(CW\*(C`const\*(C'\fR, \f(CW\*(C`volatile\*(C'\fR, +\&\f(CW\*(C`restrict\*(C'\fR or \f(CW\*(C`_Atomic\*(C'\fR specifier. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wformat\fR" 4 +.IX Item "-Wformat" +.PD 0 +.IP "\fB\-Wformat=\fR\fIn\fR" 4 +.IX Item "-Wformat=n" +.PD +Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that +the arguments supplied have types appropriate to the format string +specified, and that the conversions specified in the format string make +sense. This includes standard functions, and others specified by format +attributes, in the \f(CW\*(C`printf\*(C'\fR, +\&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension, +not in the C standard) families (or other target-specific families). +Which functions are checked without format attributes having been +specified depends on the standard version selected, and such checks of +functions without the attribute specified are disabled by +\&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. +.Sp +The formats are checked against the format features supported by \s-1GNU\s0 +libc version 2.2. These include all \s-1ISO C90\s0 and C99 features, as well +as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 +extensions. Other library implementations may not support all these +features; \s-1GCC\s0 does not support warning about features that go beyond a +particular library's limitations. However, if \fB\-Wpedantic\fR is used +with \fB\-Wformat\fR, warnings are given about format features not +in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats, +since those are not in any version of the C standard). +.RS 4 +.IP "\fB\-Wformat=1\fR" 4 +.IX Item "-Wformat=1" +.PD 0 +.IP "\fB\-Wformat\fR" 4 +.IX Item "-Wformat" +.PD +Option \fB\-Wformat\fR is equivalent to \fB\-Wformat=1\fR, and +\&\fB\-Wno\-format\fR is equivalent to \fB\-Wformat=0\fR. Since +\&\fB\-Wformat\fR also checks for null format arguments for several +functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR. Some +aspects of this level of format checking can be disabled by the +options: \fB\-Wno\-format\-contains\-nul\fR, +\&\fB\-Wno\-format\-extra\-args\fR, and \fB\-Wno\-format\-zero\-length\fR. +\&\fB\-Wformat\fR is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-format\-contains\-nul\fR" 4 +.IX Item "-Wno-format-contains-nul" +If \fB\-Wformat\fR is specified, do not warn about format strings that +contain \s-1NUL\s0 bytes. +.IP "\fB\-Wno\-format\-extra\-args\fR" 4 +.IX Item "-Wno-format-extra-args" +If \fB\-Wformat\fR is specified, do not warn about excess arguments to a +\&\f(CW\*(C`printf\*(C'\fR or \f(CW\*(C`scanf\*(C'\fR format function. The C standard specifies +that such arguments are ignored. +.Sp +Where the unused arguments lie between used arguments that are +specified with \fB$\fR operand number specifications, normally +warnings are still given, since the implementation could not know what +type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments. However, +in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option suppresses the +warning if the unused arguments are all pointers, since the Single +Unix Specification says that such unused arguments are allowed. +.IP "\fB\-Wformat\-overflow\fR" 4 +.IX Item "-Wformat-overflow" +.PD 0 +.IP "\fB\-Wformat\-overflow=\fR\fIlevel\fR" 4 +.IX Item "-Wformat-overflow=level" +.PD +Warn about calls to formatted input/output functions such as \f(CW\*(C`sprintf\*(C'\fR +and \f(CW\*(C`vsprintf\*(C'\fR that might overflow the destination buffer. When the +exact number of bytes written by a format directive cannot be determined +at compile-time it is estimated based on heuristics that depend on the +\&\fIlevel\fR argument and on optimization. While enabling optimization +will in most cases improve the accuracy of the warning, it may also +result in false positives. +.RS 4 +.IP "\fB\-Wformat\-overflow\fR" 4 +.IX Item "-Wformat-overflow" +.PD 0 +.IP "\fB\-Wformat\-overflow=1\fR" 4 +.IX Item "-Wformat-overflow=1" +.PD +Level \fI1\fR of \fB\-Wformat\-overflow\fR enabled by \fB\-Wformat\fR +employs a conservative approach that warns only about calls that most +likely overflow the buffer. At this level, numeric arguments to format +directives with unknown values are assumed to have the value of one, and +strings of unknown length to be empty. Numeric arguments that are known +to be bounded to a subrange of their type, or string arguments whose output +is bounded either by their directive's precision or by a finite set of +string literals, are assumed to take on the value within the range that +results in the most bytes on output. For example, the call to \f(CW\*(C`sprintf\*(C'\fR +below is diagnosed because even with both \fIa\fR and \fIb\fR equal to zero, +the terminating \s-1NUL\s0 character (\f(CW\*(Aq\e0\*(Aq\fR) appended by the function +to the destination buffer will be written past its end. Increasing +the size of the buffer by a single byte is sufficient to avoid the +warning, though it may not be sufficient to avoid the overflow. +.Sp +.Vb 5 +\& void f (int a, int b) +\& { +\& char buf [13]; +\& sprintf (buf, "a = %i, b = %i\en", a, b); +\& } +.Ve +.IP "\fB\-Wformat\-overflow=2\fR" 4 +.IX Item "-Wformat-overflow=2" +Level \fI2\fR warns also about calls that might overflow the destination +buffer given an argument of sufficient length or magnitude. At level +\&\fI2\fR, unknown numeric arguments are assumed to have the minimum +representable value for signed types with a precision greater than 1, and +the maximum representable value otherwise. Unknown string arguments whose +length cannot be assumed to be bounded either by the directive's precision, +or by a finite set of string literals they may evaluate to, or the character +array they may point to, are assumed to be 1 character long. +.Sp +At level \fI2\fR, the call in the example above is again diagnosed, but +this time because with \fIa\fR equal to a 32\-bit \f(CW\*(C`INT_MIN\*(C'\fR the first +\&\f(CW%i\fR directive will write some of its digits beyond the end of +the destination buffer. To make the call safe regardless of the values +of the two variables, the size of the destination buffer must be increased +to at least 34 bytes. \s-1GCC\s0 includes the minimum size of the buffer in +an informational note following the warning. +.Sp +An alternative to increasing the size of the destination buffer is to +constrain the range of formatted values. The maximum length of string +arguments can be bounded by specifying the precision in the format +directive. When numeric arguments of format directives can be assumed +to be bounded by less than the precision of their type, choosing +an appropriate length modifier to the format specifier will reduce +the required buffer size. For example, if \fIa\fR and \fIb\fR in the +example above can be assumed to be within the precision of +the \f(CW\*(C`short int\*(C'\fR type then using either the \f(CW%hi\fR format +directive or casting the argument to \f(CW\*(C`short\*(C'\fR reduces the maximum +required size of the buffer to 24 bytes. +.Sp +.Vb 5 +\& void f (int a, int b) +\& { +\& char buf [23]; +\& sprintf (buf, "a = %hi, b = %i\en", a, (short)b); +\& } +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-Wno\-format\-zero\-length\fR" 4 +.IX Item "-Wno-format-zero-length" +If \fB\-Wformat\fR is specified, do not warn about zero-length formats. +The C standard specifies that zero-length formats are allowed. +.IP "\fB\-Wformat=2\fR" 4 +.IX Item "-Wformat=2" +Enable \fB\-Wformat\fR plus additional format checks. Currently +equivalent to \fB\-Wformat \-Wformat\-nonliteral \-Wformat\-security +\&\-Wformat\-y2k\fR. +.IP "\fB\-Wformat\-nonliteral\fR" 4 +.IX Item "-Wformat-nonliteral" +If \fB\-Wformat\fR is specified, also warn if the format string is not a +string literal and so cannot be checked, unless the format function +takes its format arguments as a \f(CW\*(C`va_list\*(C'\fR. +.IP "\fB\-Wformat\-security\fR" 4 +.IX Item "-Wformat-security" +If \fB\-Wformat\fR is specified, also warn about uses of format +functions that represent possible security problems. At present, this +warns about calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR functions where the +format string is not a string literal and there are no format arguments, +as in \f(CW\*(C`printf (foo);\*(C'\fR. This may be a security hole if the format +string came from untrusted input and contains \fB\f(CB%n\fB\fR. (This is +currently a subset of what \fB\-Wformat\-nonliteral\fR warns about, but +in future warnings may be added to \fB\-Wformat\-security\fR that are not +included in \fB\-Wformat\-nonliteral\fR.) +.IP "\fB\-Wformat\-signedness\fR" 4 +.IX Item "-Wformat-signedness" +If \fB\-Wformat\fR is specified, also warn if the format string +requires an unsigned argument and the argument is signed and vice versa. +.IP "\fB\-Wformat\-truncation\fR" 4 +.IX Item "-Wformat-truncation" +.PD 0 +.IP "\fB\-Wformat\-truncation=\fR\fIlevel\fR" 4 +.IX Item "-Wformat-truncation=level" +.PD +Warn about calls to formatted input/output functions such as \f(CW\*(C`snprintf\*(C'\fR +and \f(CW\*(C`vsnprintf\*(C'\fR that might result in output truncation. When the exact +number of bytes written by a format directive cannot be determined at +compile-time it is estimated based on heuristics that depend on +the \fIlevel\fR argument and on optimization. While enabling optimization +will in most cases improve the accuracy of the warning, it may also result +in false positives. Except as noted otherwise, the option uses the same +logic \fB\-Wformat\-overflow\fR. +.RS 4 +.IP "\fB\-Wformat\-truncation\fR" 4 +.IX Item "-Wformat-truncation" +.PD 0 +.IP "\fB\-Wformat\-truncation=1\fR" 4 +.IX Item "-Wformat-truncation=1" +.PD +Level \fI1\fR of \fB\-Wformat\-truncation\fR enabled by \fB\-Wformat\fR +employs a conservative approach that warns only about calls to bounded +functions whose return value is unused and that will most likely result +in output truncation. +.IP "\fB\-Wformat\-truncation=2\fR" 4 +.IX Item "-Wformat-truncation=2" +Level \fI2\fR warns also about calls to bounded functions whose return +value is used and that might result in truncation given an argument of +sufficient length or magnitude. +.RE +.RS 4 +.RE +.IP "\fB\-Wformat\-y2k\fR" 4 +.IX Item "-Wformat-y2k" +If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR +formats that may yield only a two-digit year. +.RE +.RS 4 +.RE +.IP "\fB\-Wnonnull\fR" 4 +.IX Item "-Wnonnull" +Warn about passing a null pointer for arguments marked as +requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute. +.Sp +\&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR. It +can be disabled with the \fB\-Wno\-nonnull\fR option. +.IP "\fB\-Wnonnull\-compare\fR" 4 +.IX Item "-Wnonnull-compare" +Warn when comparing an argument marked with the \f(CW\*(C`nonnull\*(C'\fR +function attribute against null inside the function. +.Sp +\&\fB\-Wnonnull\-compare\fR is included in \fB\-Wall\fR. It +can be disabled with the \fB\-Wno\-nonnull\-compare\fR option. +.IP "\fB\-Wnull\-dereference\fR" 4 +.IX Item "-Wnull-dereference" +Warn if the compiler detects paths that trigger erroneous or +undefined behavior due to dereferencing a null pointer. This option +is only active when \fB\-fdelete\-null\-pointer\-checks\fR is active, +which is enabled by optimizations in most targets. The precision of +the warnings depends on the optimization options used. +.IP "\fB\-Winit\-self\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Winit-self (C, , Objective-C and Objective- only)" +Warn about uninitialized variables that are initialized with themselves. +Note this option can only be used with the \fB\-Wuninitialized\fR option. +.Sp +For example, \s-1GCC\s0 warns about \f(CW\*(C`i\*(C'\fR being uninitialized in the +following snippet only when \fB\-Winit\-self\fR has been specified: +.Sp +.Vb 5 +\& int f() +\& { +\& int i = i; +\& return i; +\& } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR in \*(C+. +.IP "\fB\-Wimplicit\-int\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-int (C and Objective-C only)" +Warn when a declaration does not specify a type. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-function-declaration (C and Objective-C only)" +Give a warning whenever a function is used before being declared. In +C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this warning is +enabled by default and it is made into an error by +\&\fB\-pedantic\-errors\fR. This warning is also enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wimplicit\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit (C and Objective-C only)" +Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wimplicit\-fallthrough\fR" 4 +.IX Item "-Wimplicit-fallthrough" +\&\fB\-Wimplicit\-fallthrough\fR is the same as \fB\-Wimplicit\-fallthrough=3\fR +and \fB\-Wno\-implicit\-fallthrough\fR is the same as +\&\fB\-Wimplicit\-fallthrough=0\fR. +.IP "\fB\-Wimplicit\-fallthrough=\fR\fIn\fR" 4 +.IX Item "-Wimplicit-fallthrough=n" +Warn when a switch case falls through. For example: +.Sp +.Vb 11 +\& switch (cond) +\& { +\& case 1: +\& a = 1; +\& break; +\& case 2: +\& a = 2; +\& case 3: +\& a = 3; +\& break; +\& } +.Ve +.Sp +This warning does not warn when the last statement of a case cannot +fall through, e.g. when there is a return statement or a call to function +declared with the noreturn attribute. \fB\-Wimplicit\-fallthrough=\fR +also takes into account control flow statements, such as ifs, and only +warns when appropriate. E.g. +.Sp +.Vb 10 +\& switch (cond) +\& { +\& case 1: +\& if (i > 3) { +\& bar (5); +\& break; +\& } else if (i < 1) { +\& bar (0); +\& } else +\& return; +\& default: +\& ... +\& } +.Ve +.Sp +Since there are occasions where a switch case fall through is desirable, +\&\s-1GCC\s0 provides an attribute, \f(CW\*(C`_\|_attribute_\|_ ((fallthrough))\*(C'\fR, that is +to be used along with a null statement to suppress this warning that +would normally occur: +.Sp +.Vb 8 +\& switch (cond) +\& { +\& case 1: +\& bar (0); +\& _\|_attribute_\|_ ((fallthrough)); +\& default: +\& ... +\& } +.Ve +.Sp +\&\*(C+17 provides a standard way to suppress the \fB\-Wimplicit\-fallthrough\fR +warning using \f(CW\*(C`[[fallthrough]];\*(C'\fR instead of the \s-1GNU\s0 attribute. In \*(C+11 +or \*(C+14 users can use \f(CW\*(C`[[gnu::fallthrough]];\*(C'\fR, which is a \s-1GNU\s0 extension. +Instead of these attributes, it is also possible to add a fallthrough comment +to silence the warning. The whole body of the C or \*(C+ style comment should +match the given regular expressions listed below. The option argument \fIn\fR +specifies what kind of comments are accepted: +.RS 4 +.IP "*<\fB\-Wimplicit\-fallthrough=0\fR disables the warning altogether.>" 4 +.IX Item "*<-Wimplicit-fallthrough=0 disables the warning altogether.>" +.PD 0 +.ie n .IP "*<\fB\-Wimplicit\-fallthrough=1\fR matches "".*"" regular>" 4 +.el .IP "*<\fB\-Wimplicit\-fallthrough=1\fR matches \f(CW.*\fR regular>" 4 +.IX Item "*<-Wimplicit-fallthrough=1 matches .* regular>" +.PD +expression, any comment is used as fallthrough comment. +.IP "*<\fB\-Wimplicit\-fallthrough=2\fR case insensitively matches>" 4 +.IX Item "*<-Wimplicit-fallthrough=2 case insensitively matches>" +\&\f(CW\*(C`.*falls?[ \et\-]*thr(ough|u).*\*(C'\fR regular expression. +.IP "*<\fB\-Wimplicit\-fallthrough=3\fR case sensitively matches one of the>" 4 +.IX Item "*<-Wimplicit-fallthrough=3 case sensitively matches one of the>" +following regular expressions: +.RS 4 +.ie n .IP "*<""\-fallthrough"">" 4 +.el .IP "*<\f(CW\-fallthrough\fR>" 4 +.IX Item "*<-fallthrough>" +.PD 0 +.ie n .IP "*<""@fallthrough@"">" 4 +.el .IP "*<\f(CW@fallthrough@\fR>" 4 +.IX Item "*<@fallthrough@>" +.ie n .IP "*<""lint \-fallthrough[ \et]*"">" 4 +.el .IP "*<\f(CWlint \-fallthrough[ \et]*\fR>" 4 +.IX Item "*" +.ie n .IP "*<""[ \et.!]*(ELSE,? |INTENTIONAL(LY)? )?FALL(S | |\-)?THR(OUGH|U)[ \et.!]*(\-[^\en\er]*)?"">" 4 +.el .IP "*<\f(CW[ \et.!]*(ELSE,? |INTENTIONAL(LY)? )?FALL(S | |\-)?THR(OUGH|U)[ \et.!]*(\-[^\en\er]*)?\fR>" 4 +.IX Item "*<[ t.!]*(ELSE,? |INTENTIONAL(LY)? )?FALL(S | |-)?THR(OUGH|U)[ t.!]*(-[^nr]*)?>" +.ie n .IP "*<""[ \et.!]*(Else,? |Intentional(ly)? )?Fall((s | |\-)[Tt]|t)hr(ough|u)[ \et.!]*(\-[^\en\er]*)?"">" 4 +.el .IP "*<\f(CW[ \et.!]*(Else,? |Intentional(ly)? )?Fall((s | |\-)[Tt]|t)hr(ough|u)[ \et.!]*(\-[^\en\er]*)?\fR>" 4 +.IX Item "*<[ t.!]*(Else,? |Intentional(ly)? )?Fall((s | |-)[Tt]|t)hr(ough|u)[ t.!]*(-[^nr]*)?>" +.ie n .IP "*<""[ \et.!]*([Ee]lse,? |[Ii]ntentional(ly)? )?fall(s | |\-)?thr(ough|u)[ \et.!]*(\-[^\en\er]*)?"">" 4 +.el .IP "*<\f(CW[ \et.!]*([Ee]lse,? |[Ii]ntentional(ly)? )?fall(s | |\-)?thr(ough|u)[ \et.!]*(\-[^\en\er]*)?\fR>" 4 +.IX Item "*<[ t.!]*([Ee]lse,? |[Ii]ntentional(ly)? )?fall(s | |-)?thr(ough|u)[ t.!]*(-[^nr]*)?>" +.RE +.RS 4 +.RE +.IP "*<\fB\-Wimplicit\-fallthrough=4\fR case sensitively matches one of the>" 4 +.IX Item "*<-Wimplicit-fallthrough=4 case sensitively matches one of the>" +.PD +following regular expressions: +.RS 4 +.ie n .IP "*<""\-fallthrough"">" 4 +.el .IP "*<\f(CW\-fallthrough\fR>" 4 +.IX Item "*<-fallthrough>" +.PD 0 +.ie n .IP "*<""@fallthrough@"">" 4 +.el .IP "*<\f(CW@fallthrough@\fR>" 4 +.IX Item "*<@fallthrough@>" +.ie n .IP "*<""lint \-fallthrough[ \et]*"">" 4 +.el .IP "*<\f(CWlint \-fallthrough[ \et]*\fR>" 4 +.IX Item "*" +.ie n .IP "*<""[ \et]*FALLTHR(OUGH|U)[ \et]*"">" 4 +.el .IP "*<\f(CW[ \et]*FALLTHR(OUGH|U)[ \et]*\fR>" 4 +.IX Item "*<[ t]*FALLTHR(OUGH|U)[ t]*>" +.RE +.RS 4 +.RE +.IP "*<\fB\-Wimplicit\-fallthrough=5\fR doesn't recognize any comments as>" 4 +.IX Item "*<-Wimplicit-fallthrough=5 doesn't recognize any comments as>" +.PD +fallthrough comments, only attributes disable the warning. +.RE +.RS 4 +.Sp +The comment needs to be followed after optional whitespace and other comments +by \f(CW\*(C`case\*(C'\fR or \f(CW\*(C`default\*(C'\fR keywords or by a user label that precedes some +\&\f(CW\*(C`case\*(C'\fR or \f(CW\*(C`default\*(C'\fR label. +.Sp +.Vb 8 +\& switch (cond) +\& { +\& case 1: +\& bar (0); +\& /* FALLTHRU */ +\& default: +\& ... +\& } +.Ve +.Sp +The \fB\-Wimplicit\-fallthrough=3\fR warning is enabled by \fB\-Wextra\fR. +.RE +.IP "\fB\-Wif\-not\-aligned\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wif-not-aligned (C, , Objective-C and Objective- only)" +Control if warning triggered by the \f(CW\*(C`warn_if_not_aligned\*(C'\fR attribute +should be issued. This is enabled by default. +Use \fB\-Wno\-if\-not\-aligned\fR to disable it. +.IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 +.IX Item "-Wignored-qualifiers (C and only)" +Warn if the return type of a function has a type qualifier +such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO C\s0 such a type qualifier has no effect, +since the value returned by a function is not an lvalue. +For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. +\&\s-1ISO C\s0 prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function +definitions, so such return types always receive a warning +even without this option. +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wignored\-attributes\fR (C and \*(C+ only)" 4 +.IX Item "-Wignored-attributes (C and only)" +Warn when an attribute is ignored. This is different from the +\&\fB\-Wattributes\fR option in that it warns whenever the compiler decides +to drop an attribute, not that the attribute is either unknown, used in a +wrong place, etc. This warning is enabled by default. +.IP "\fB\-Wmain\fR" 4 +.IX Item "-Wmain" +Warn if the type of \f(CW\*(C`main\*(C'\fR is suspicious. \f(CW\*(C`main\*(C'\fR should be +a function with external linkage, returning int, taking either zero +arguments, two, or three arguments of appropriate types. This warning +is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR +or \fB\-Wpedantic\fR. +.IP "\fB\-Wmisleading\-indentation\fR (C and \*(C+ only)" 4 +.IX Item "-Wmisleading-indentation (C and only)" +Warn when the indentation of the code does not reflect the block structure. +Specifically, a warning is issued for \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR, \f(CW\*(C`while\*(C'\fR, and +\&\f(CW\*(C`for\*(C'\fR clauses with a guarded statement that does not use braces, +followed by an unguarded statement with the same indentation. +.Sp +In the following example, the call to \*(L"bar\*(R" is misleadingly indented as +if it were guarded by the \*(L"if\*(R" conditional. +.Sp +.Vb 3 +\& if (some_condition ()) +\& foo (); +\& bar (); /* Gotcha: this is not guarded by the "if". */ +.Ve +.Sp +In the case of mixed tabs and spaces, the warning uses the +\&\fB\-ftabstop=\fR option to determine if the statements line up +(defaulting to 8). +.Sp +The warning is not issued for code involving multiline preprocessor logic +such as the following example. +.Sp +.Vb 6 +\& if (flagA) +\& foo (0); +\& #if SOME_CONDITION_THAT_DOES_NOT_HOLD +\& if (flagB) +\& #endif +\& foo (1); +.Ve +.Sp +The warning is not issued after a \f(CW\*(C`#line\*(C'\fR directive, since this +typically indicates autogenerated code, and no assumptions can be made +about the layout of the file that the directive references. +.Sp +This warning is enabled by \fB\-Wall\fR in C and \*(C+. +.IP "\fB\-Wmissing\-attributes\fR" 4 +.IX Item "-Wmissing-attributes" +Warn when a declaration of a function is missing one or more attributes +that a related function is declared with and whose absence may adversely +affect the correctness or efficiency of generated code. For example, +the warning is issued for declarations of aliases that use attributes +to specify less restrictive requirements than those of their targets. +This typically represents a potential optimization opportunity. +By contrast, the \fB\-Wattribute\-alias=2\fR option controls warnings +issued when the alias is more restrictive than the target, which could +lead to incorrect code generation. +Attributes considered include \f(CW\*(C`alloc_align\*(C'\fR, \f(CW\*(C`alloc_size\*(C'\fR, +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`const\*(C'\fR, \f(CW\*(C`hot\*(C'\fR, \f(CW\*(C`leaf\*(C'\fR, \f(CW\*(C`malloc\*(C'\fR, +\&\f(CW\*(C`nonnull\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, \f(CW\*(C`nothrow\*(C'\fR, \f(CW\*(C`pure\*(C'\fR, +\&\f(CW\*(C`returns_nonnull\*(C'\fR, and \f(CW\*(C`returns_twice\*(C'\fR. +.Sp +In \*(C+, the warning is issued when an explicit specialization of a primary +template declared with attribute \f(CW\*(C`alloc_align\*(C'\fR, \f(CW\*(C`alloc_size\*(C'\fR, +\&\f(CW\*(C`assume_aligned\*(C'\fR, \f(CW\*(C`format\*(C'\fR, \f(CW\*(C`format_arg\*(C'\fR, \f(CW\*(C`malloc\*(C'\fR, +or \f(CW\*(C`nonnull\*(C'\fR is declared without it. Attributes \f(CW\*(C`deprecated\*(C'\fR, +\&\f(CW\*(C`error\*(C'\fR, and \f(CW\*(C`warning\*(C'\fR suppress the warning.. +.Sp +You can use the \f(CW\*(C`copy\*(C'\fR attribute to apply the same +set of attributes to a declaration as that on another declaration without +explicitly enumerating the attributes. This attribute can be applied +to declarations of functions, +variables, or types. +.Sp +\&\fB\-Wmissing\-attributes\fR is enabled by \fB\-Wall\fR. +.Sp +For example, since the declaration of the primary function template +below makes use of both attribute \f(CW\*(C`malloc\*(C'\fR and \f(CW\*(C`alloc_size\*(C'\fR +the declaration of the explicit specialization of the template is +diagnosed because it is missing one of the attributes. +.Sp +.Vb 3 +\& template +\& T* _\|_attribute_\|_ ((malloc, alloc_size (1))) +\& allocate (size_t); +\& +\& template <> +\& void* _\|_attribute_\|_ ((malloc)) // missing alloc_size +\& allocate (size_t); +.Ve +.IP "\fB\-Wmissing\-braces\fR" 4 +.IX Item "-Wmissing-braces" +Warn if an aggregate or union initializer is not fully bracketed. In +the following example, the initializer for \f(CW\*(C`a\*(C'\fR is not fully +bracketed, but that for \f(CW\*(C`b\*(C'\fR is fully bracketed. This warning is +enabled by \fB\-Wall\fR in C. +.Sp +.Vb 2 +\& int a[2][2] = { 0, 1, 2, 3 }; +\& int b[2][2] = { { 0, 1 }, { 2, 3 } }; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wmissing\-include\-dirs\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wmissing-include-dirs (C, , Objective-C and Objective- only)" +Warn if a user-supplied include directory does not exist. +.IP "\fB\-Wmissing\-profile\fR" 4 +.IX Item "-Wmissing-profile" +Warn if feedback profiles are missing when using the +\&\fB\-fprofile\-use\fR option. +This option diagnoses those cases where a new function or a new file is added +to the user code between compiling with \fB\-fprofile\-generate\fR and with +\&\fB\-fprofile\-use\fR, without regenerating the profiles. In these cases, the +profile feedback data files do not contain any profile feedback information for +the newly added function or file respectively. Also, in the case when profile +count data (.gcda) files are removed, \s-1GCC\s0 cannot use any profile feedback +information. In all these cases, warnings are issued to inform the user that a +profile generation step is due. \fB\-Wno\-missing\-profile\fR can be used to +disable the warning. Ignoring the warning can result in poorly optimized code. +Completely disabling the warning is not recommended and should be done only +when non-existent profile data is justified. +.IP "\fB\-Wmultistatement\-macros\fR" 4 +.IX Item "-Wmultistatement-macros" +Warn about unsafe multiple statement macros that appear to be guarded +by a clause such as \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR, \f(CW\*(C`for\*(C'\fR, \f(CW\*(C`switch\*(C'\fR, or +\&\f(CW\*(C`while\*(C'\fR, in which only the first statement is actually guarded after +the macro is expanded. +.Sp +For example: +.Sp +.Vb 3 +\& #define DOIT x++; y++ +\& if (c) +\& DOIT; +.Ve +.Sp +will increment \f(CW\*(C`y\*(C'\fR unconditionally, not just when \f(CW\*(C`c\*(C'\fR holds. +The can usually be fixed by wrapping the macro in a do-while loop: +.Sp +.Vb 3 +\& #define DOIT do { x++; y++; } while (0) +\& if (c) +\& DOIT; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR in C and \*(C+. +.IP "\fB\-Wparentheses\fR" 4 +.IX Item "-Wparentheses" +Warn if parentheses are omitted in certain contexts, such +as when there is an assignment in a context where a truth value +is expected, or when operators are nested whose precedence people +often get confused about. +.Sp +Also warn if a comparison like \f(CW\*(C`x<=y<=z\*(C'\fR appears; this is +equivalent to \f(CW\*(C`(x<=y ? 1 : 0) <= z\*(C'\fR, which is a different +interpretation from that of ordinary mathematical notation. +.Sp +Also warn for dangerous uses of the \s-1GNU\s0 extension to +\&\f(CW\*(C`?:\*(C'\fR with omitted middle operand. When the condition +in the \f(CW\*(C`?\*(C'\fR: operator is a boolean expression, the omitted value is +always 1. Often programmers expect it to be a value computed +inside the conditional expression instead. +.Sp +For \*(C+ this also warns for some cases of unnecessary parentheses in +declarations, which can indicate an attempt at a function call instead +of a declaration: +.Sp +.Vb 5 +\& { +\& // Declares a local variable called mymutex. +\& std::unique_lock (mymutex); +\& // User meant std::unique_lock lock (mymutex); +\& } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsequence\-point\fR" 4 +.IX Item "-Wsequence-point" +Warn about code that may have undefined semantics because of violations +of sequence point rules in the C and \*(C+ standards. +.Sp +The C and \*(C+ standards define the order in which expressions in a C/\*(C+ +program are evaluated in terms of \fIsequence points\fR, which represent +a partial ordering between the execution of parts of the program: those +executed before the sequence point, and those executed after it. These +occur after the evaluation of a full expression (one which is not part +of a larger expression), after the evaluation of the first operand of a +\&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a +function is called (but after the evaluation of its arguments and the +expression denoting the called function), and in certain other places. +Other than as expressed by the sequence point rules, the order of +evaluation of subexpressions of an expression is not specified. All +these rules describe only a partial order rather than a total order, +since, for example, if two functions are called within one expression +with no sequence point between them, the order in which the functions +are called is not specified. However, the standards committee have +ruled that function calls do not overlap. +.Sp +It is not specified when between sequence points modifications to the +values of objects take effect. Programs whose behavior depends on this +have undefined behavior; the C and \*(C+ standards specify that \*(L"Between +the previous and next sequence point an object shall have its stored +value modified at most once by the evaluation of an expression. +Furthermore, the prior value shall be read only to determine the value +to be stored.\*(R". If a program breaks these rules, the results on any +particular implementation are entirely unpredictable. +.Sp +Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n] += b[n++]\*(C'\fR and \f(CW\*(C`a[i++] = i;\*(C'\fR. Some more complicated cases are not +diagnosed by this option, and it may give an occasional false positive +result, but in general it has been found fairly effective at detecting +this sort of problem in programs. +.Sp +The \*(C+17 standard will define the order of evaluation of operands in +more cases: in particular it requires that the right-hand side of an +assignment be evaluated before the left-hand side, so the above +examples are no longer undefined. But this warning will still warn +about them, to help people avoid writing code that is undefined in C +and earlier revisions of \*(C+. +.Sp +The standard is worded confusingly, therefore there is some debate +over the precise meaning of the sequence point rules in subtle cases. +Links to discussions of the problem, including proposed formal +definitions, may be found on the \s-1GCC\s0 readings page, at +<\fBhttp://gcc.gnu.org/readings.html\fR>. +.Sp +This warning is enabled by \fB\-Wall\fR for C and \*(C+. +.IP "\fB\-Wno\-return\-local\-addr\fR" 4 +.IX Item "-Wno-return-local-addr" +Do not warn about returning a pointer (or in \*(C+, a reference) to a +variable that goes out of scope after the function returns. +.IP "\fB\-Wreturn\-type\fR" 4 +.IX Item "-Wreturn-type" +Warn whenever a function is defined with a return type that defaults +to \f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no +return value in a function whose return type is not \f(CW\*(C`void\*(C'\fR +(falling off the end of the function body is considered returning +without a value). +.Sp +For C only, warn about a \f(CW\*(C`return\*(C'\fR statement with an expression in a +function whose return type is \f(CW\*(C`void\*(C'\fR, unless the expression type is +also \f(CW\*(C`void\*(C'\fR. As a \s-1GNU\s0 extension, the latter case is accepted +without a warning unless \fB\-Wpedantic\fR is used. Attempting +to use the return value of a non\-\f(CW\*(C`void\*(C'\fR function other than \f(CW\*(C`main\*(C'\fR +that flows off the end by reaching the closing curly brace that terminates +the function is undefined. +.Sp +Unlike in C, in \*(C+, flowing off the end of a non\-\f(CW\*(C`void\*(C'\fR function other +than \f(CW\*(C`main\*(C'\fR results in undefined behavior even when the value of +the function is not used. +.Sp +This warning is enabled by default in \*(C+ and by \fB\-Wall\fR otherwise. +.IP "\fB\-Wshift\-count\-negative\fR" 4 +.IX Item "-Wshift-count-negative" +Warn if shift count is negative. This warning is enabled by default. +.IP "\fB\-Wshift\-count\-overflow\fR" 4 +.IX Item "-Wshift-count-overflow" +Warn if shift count >= width of type. This warning is enabled by default. +.IP "\fB\-Wshift\-negative\-value\fR" 4 +.IX Item "-Wshift-negative-value" +Warn if left shifting a negative value. This warning is enabled by +\&\fB\-Wextra\fR in C99 (and newer) and \*(C+11 to \*(C+17 modes. +.IP "\fB\-Wshift\-overflow\fR" 4 +.IX Item "-Wshift-overflow" +.PD 0 +.IP "\fB\-Wshift\-overflow=\fR\fIn\fR" 4 +.IX Item "-Wshift-overflow=n" +.PD +Warn about left shift overflows. This warning is enabled by +default in C99 and \*(C+11 modes (and newer). +.RS 4 +.IP "\fB\-Wshift\-overflow=1\fR" 4 +.IX Item "-Wshift-overflow=1" +This is the warning level of \fB\-Wshift\-overflow\fR and is enabled +by default in C99 and \*(C+11 modes (and newer). This warning level does +not warn about left-shifting 1 into the sign bit. (However, in C, such +an overflow is still rejected in contexts where an integer constant expression +is required.) No warning is emitted in \*(C+2A mode (and newer), as signed left +shifts always wrap. +.IP "\fB\-Wshift\-overflow=2\fR" 4 +.IX Item "-Wshift-overflow=2" +This warning level also warns about left-shifting 1 into the sign bit, +unless \*(C+14 mode (or newer) is active. +.RE +.RS 4 +.RE +.IP "\fB\-Wswitch\fR" 4 +.IX Item "-Wswitch" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this +warning.) \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used (even if there is a +\&\f(CW\*(C`default\*(C'\fR label). +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wswitch\-default\fR" 4 +.IX Item "-Wswitch-default" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR +case. +.IP "\fB\-Wswitch\-enum\fR" 4 +.IX Item "-Wswitch-enum" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used. The only difference +between \fB\-Wswitch\fR and this option is that this option gives a +warning about an omitted enumeration code even if there is a +\&\f(CW\*(C`default\*(C'\fR label. +.IP "\fB\-Wswitch\-bool\fR" 4 +.IX Item "-Wswitch-bool" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of boolean type +and the case values are outside the range of a boolean type. +It is possible to suppress this warning by casting the controlling +expression to a type other than \f(CW\*(C`bool\*(C'\fR. For example: +.Sp +.Vb 4 +\& switch ((int) (a == 4)) +\& { +\& ... +\& } +.Ve +.Sp +This warning is enabled by default for C and \*(C+ programs. +.IP "\fB\-Wswitch\-unreachable\fR" 4 +.IX Item "-Wswitch-unreachable" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement contains statements between the +controlling expression and the first case label, which will never be +executed. For example: +.Sp +.Vb 7 +\& switch (cond) +\& { +\& i = 15; +\& ... +\& case 5: +\& ... +\& } +.Ve +.Sp +\&\fB\-Wswitch\-unreachable\fR does not warn if the statement between the +controlling expression and the first case label is just a declaration: +.Sp +.Vb 8 +\& switch (cond) +\& { +\& int i; +\& ... +\& case 5: +\& i = 5; +\& ... +\& } +.Ve +.Sp +This warning is enabled by default for C and \*(C+ programs. +.IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 +.IX Item "-Wsync-nand (C and only)" +Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR +built-in functions are used. These functions changed semantics in \s-1GCC 4.4.\s0 +.IP "\fB\-Wunused\-but\-set\-parameter\fR" 4 +.IX Item "-Wunused-but-set-parameter" +Warn whenever a function parameter is assigned to, but otherwise unused +(aside from its declaration). +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR together with +\&\fB\-Wextra\fR. +.IP "\fB\-Wunused\-but\-set\-variable\fR" 4 +.IX Item "-Wunused-but-set-variable" +Warn whenever a local variable is assigned to, but otherwise unused +(aside from its declaration). +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR, which is enabled +by \fB\-Wall\fR. +.IP "\fB\-Wunused\-function\fR" 4 +.IX Item "-Wunused-function" +Warn whenever a static function is declared but not defined or a +non-inline static function is unused. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-label\fR" 4 +.IX Item "-Wunused-label" +Warn whenever a label is declared but not used. +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +Warn when a typedef locally defined in a function is not used. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-parameter\fR" 4 +.IX Item "-Wunused-parameter" +Warn whenever a function parameter is unused aside from its declaration. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.IP "\fB\-Wno\-unused\-result\fR" 4 +.IX Item "-Wno-unused-result" +Do not warn if a caller of a function marked with attribute +\&\f(CW\*(C`warn_unused_result\*(C'\fR does not use +its return value. The default is \fB\-Wunused\-result\fR. +.IP "\fB\-Wunused\-variable\fR" 4 +.IX Item "-Wunused-variable" +Warn whenever a local or static variable is unused aside from its +declaration. This option implies \fB\-Wunused\-const\-variable=1\fR for C, +but not for \*(C+. This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.IP "\fB\-Wunused\-const\-variable\fR" 4 +.IX Item "-Wunused-const-variable" +.PD 0 +.IP "\fB\-Wunused\-const\-variable=\fR\fIn\fR" 4 +.IX Item "-Wunused-const-variable=n" +.PD +Warn whenever a constant static variable is unused aside from its declaration. +\&\fB\-Wunused\-const\-variable=1\fR is enabled by \fB\-Wunused\-variable\fR +for C, but not for \*(C+. In C this declares variable storage, but in \*(C+ this +is not an error since const variables take the place of \f(CW\*(C`#define\*(C'\fRs. +.Sp +To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. +.RS 4 +.IP "\fB\-Wunused\-const\-variable=1\fR" 4 +.IX Item "-Wunused-const-variable=1" +This is the warning level that is enabled by \fB\-Wunused\-variable\fR for +C. It warns only about unused static const variables defined in the main +compilation unit, but not about static const variables declared in any +header included. +.IP "\fB\-Wunused\-const\-variable=2\fR" 4 +.IX Item "-Wunused-const-variable=2" +This warning level also warns for unused constant static variables in +headers (excluding system headers). This is the warning level of +\&\fB\-Wunused\-const\-variable\fR and must be explicitly requested since +in \*(C+ this isn't an error and in C it might be harder to clean up all +headers included. +.RE +.RS 4 +.RE +.IP "\fB\-Wunused\-value\fR" 4 +.IX Item "-Wunused-value" +Warn whenever a statement computes a result that is explicitly not +used. To suppress this warning cast the unused expression to +\&\f(CW\*(C`void\*(C'\fR. This includes an expression-statement or the left-hand +side of a comma expression that contains no side effects. For example, +an expression such as \f(CW\*(C`x[i,j]\*(C'\fR causes a warning, while +\&\f(CW\*(C`x[(void)i,j]\*(C'\fR does not. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\fR" 4 +.IX Item "-Wunused" +All the above \fB\-Wunused\fR options combined. +.Sp +In order to get a warning about an unused function parameter, you must +either specify \fB\-Wextra \-Wunused\fR (note that \fB\-Wall\fR implies +\&\fB\-Wunused\fR), or separately specify \fB\-Wunused\-parameter\fR. +.IP "\fB\-Wuninitialized\fR" 4 +.IX Item "-Wuninitialized" +Warn if an automatic variable is used without first being initialized +or if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call. In \*(C+, +warn if a non-static reference or non-static \f(CW\*(C`const\*(C'\fR member +appears in a class without constructors. +.Sp +If you want to warn about code that uses the uninitialized value of the +variable in its own initializer, use the \fB\-Winit\-self\fR option. +.Sp +These warnings occur for individual uninitialized or clobbered +elements of structure, union or array variables as well as for +variables that are uninitialized or clobbered as a whole. They do +not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because +these warnings depend on optimization, the exact variables or elements +for which there are warnings depends on the precise optimization +options and version of \s-1GCC\s0 used. +.Sp +Note that there may be no warning about a variable that is used only +to compute a value that itself is never used, because such +computations may be deleted by data flow analysis before the warnings +are printed. +.IP "\fB\-Winvalid\-memory\-model\fR" 4 +.IX Item "-Winvalid-memory-model" +Warn for invocations of \fB_\|_atomic Builtins\fR, \fB_\|_sync Builtins\fR, +and the C11 atomic generic functions with a memory consistency argument +that is either invalid for the operation or outside the range of values +of the \f(CW\*(C`memory_order\*(C'\fR enumeration. For example, since the +\&\f(CW\*(C`_\|_atomic_store\*(C'\fR and \f(CW\*(C`_\|_atomic_store_n\*(C'\fR built-ins are only +defined for the relaxed, release, and sequentially consistent memory +orders the following code is diagnosed: +.Sp +.Vb 4 +\& void store (int *i) +\& { +\& _\|_atomic_store_n (i, 0, memory_order_consume); +\& } +.Ve +.Sp +\&\fB\-Winvalid\-memory\-model\fR is enabled by default. +.IP "\fB\-Wmaybe\-uninitialized\fR" 4 +.IX Item "-Wmaybe-uninitialized" +For an automatic (i.e. local) variable, if there exists a path from the +function entry to a use of the variable that is initialized, but there exist +some other paths for which the variable is not initialized, the compiler +emits a warning if it cannot prove the uninitialized paths are not +executed at run time. +.Sp +These warnings are only possible in optimizing compilation, because otherwise +\&\s-1GCC\s0 does not keep track of the state of variables. +.Sp +These warnings are made optional because \s-1GCC\s0 may not be able to determine when +the code is correct in spite of appearing to have an error. Here is one +example of how this can happen: +.Sp +.Vb 12 +\& { +\& int x; +\& switch (y) +\& { +\& case 1: x = 1; +\& break; +\& case 2: x = 4; +\& break; +\& case 3: x = 5; +\& } +\& foo (x); +\& } +.Ve +.Sp +If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is +always initialized, but \s-1GCC\s0 doesn't know this. To suppress the +warning, you need to provide a default case with \fBassert\fR\|(0) or +similar code. +.Sp +This option also warns when a non-volatile automatic variable might be +changed by a call to \f(CW\*(C`longjmp\*(C'\fR. +The compiler sees only the calls to \f(CW\*(C`setjmp\*(C'\fR. It cannot know +where \f(CW\*(C`longjmp\*(C'\fR will be called; in fact, a signal handler could +call it at any point in the code. As a result, you may get a warning +even when there is in fact no problem because \f(CW\*(C`longjmp\*(C'\fR cannot +in fact be called at the place that would cause a problem. +.Sp +Some spurious warnings can be avoided if you declare all the functions +you use that never return as \f(CW\*(C`noreturn\*(C'\fR. +.Sp +This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. +.IP "\fB\-Wunknown\-pragmas\fR" 4 +.IX Item "-Wunknown-pragmas" +Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by +\&\s-1GCC.\s0 If this command-line option is used, warnings are even issued +for unknown pragmas in system header files. This is not the case if +the warnings are only enabled by the \fB\-Wall\fR command-line option. +.IP "\fB\-Wno\-pragmas\fR" 4 +.IX Item "-Wno-pragmas" +Do not warn about misuses of pragmas, such as incorrect parameters, +invalid syntax, or conflicts between pragmas. See also +\&\fB\-Wunknown\-pragmas\fR. +.IP "\fB\-Wno\-prio\-ctor\-dtor\fR" 4 +.IX Item "-Wno-prio-ctor-dtor" +Do not warn if a priority from 0 to 100 is used for constructor or destructor. +The use of constructor and destructor attributes allow you to assign a +priority to the constructor/destructor to control its order of execution +before \f(CW\*(C`main\*(C'\fR is called or after it returns. The priority values must be +greater than 100 as the compiler reserves priority values between 0\-\-100 for +the implementation. +.IP "\fB\-Wstrict\-aliasing\fR" 4 +.IX Item "-Wstrict-aliasing" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code that might break the strict aliasing rules that the +compiler is using for optimization. The warning does not catch all +cases, but does attempt to catch the more common pitfalls. It is +included in \fB\-Wall\fR. +It is equivalent to \fB\-Wstrict\-aliasing=3\fR +.IP "\fB\-Wstrict\-aliasing=n\fR" 4 +.IX Item "-Wstrict-aliasing=n" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code that might break the strict aliasing rules that the +compiler is using for optimization. +Higher levels correspond to higher accuracy (fewer false positives). +Higher levels also correspond to more effort, similar to the way \fB\-O\fR +works. +\&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=3\fR. +.Sp +Level 1: Most aggressive, quick, least accurate. +Possibly useful when higher levels +do not warn but \fB\-fstrict\-aliasing\fR still breaks the code, as it has very few +false negatives. However, it has many false positives. +Warns for all pointer conversions between possibly incompatible types, +even if never dereferenced. Runs in the front end only. +.Sp +Level 2: Aggressive, quick, not too precise. +May still have many false positives (not as many as level 1 though), +and few false negatives (but possibly more than level 1). +Unlike level 1, it only warns when an address is taken. Warns about +incomplete types. Runs in the front end only. +.Sp +Level 3 (default for \fB\-Wstrict\-aliasing\fR): +Should have very few false positives and few false +negatives. Slightly slower than levels 1 or 2 when optimization is enabled. +Takes care of the common pun+dereference pattern in the front end: +\&\f(CW\*(C`*(int*)&some_float\*(C'\fR. +If optimization is enabled, it also runs in the back end, where it deals +with multiple statement cases using flow-sensitive points-to information. +Only warns when the converted pointer is dereferenced. +Does not warn about incomplete types. +.IP "\fB\-Wstrict\-overflow\fR" 4 +.IX Item "-Wstrict-overflow" +.PD 0 +.IP "\fB\-Wstrict\-overflow=\fR\fIn\fR" 4 +.IX Item "-Wstrict-overflow=n" +.PD +This option is only active when signed overflow is undefined. +It warns about cases where the compiler optimizes based on the +assumption that signed overflow does not occur. Note that it does not +warn about all cases where the code might overflow: it only warns +about cases where the compiler implements some optimization. Thus +this warning depends on the optimization level. +.Sp +An optimization that assumes that signed overflow does not occur is +perfectly safe if the values of the variables involved are such that +overflow never does, in fact, occur. Therefore this warning can +easily give a false positive: a warning about code that is not +actually a problem. To help focus on important issues, several +warning levels are defined. No warnings are issued for the use of +undefined signed overflow when estimating how many iterations a loop +requires, in particular when determining whether a loop will be +executed at all. +.RS 4 +.IP "\fB\-Wstrict\-overflow=1\fR" 4 +.IX Item "-Wstrict-overflow=1" +Warn about cases that are both questionable and easy to avoid. For +example the compiler simplifies +\&\f(CW\*(C`x + 1 > x\*(C'\fR to \f(CW1\fR. This level of +\&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels +are not, and must be explicitly requested. +.IP "\fB\-Wstrict\-overflow=2\fR" 4 +.IX Item "-Wstrict-overflow=2" +Also warn about other cases where a comparison is simplified to a +constant. For example: \f(CW\*(C`abs (x) >= 0\*(C'\fR. This can only be +simplified when signed integer overflow is undefined, because +\&\f(CW\*(C`abs (INT_MIN)\*(C'\fR overflows to \f(CW\*(C`INT_MIN\*(C'\fR, which is less than +zero. \fB\-Wstrict\-overflow\fR (with no level) is the same as +\&\fB\-Wstrict\-overflow=2\fR. +.IP "\fB\-Wstrict\-overflow=3\fR" 4 +.IX Item "-Wstrict-overflow=3" +Also warn about other cases where a comparison is simplified. For +example: \f(CW\*(C`x + 1 > 1\*(C'\fR is simplified to \f(CW\*(C`x > 0\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=4\fR" 4 +.IX Item "-Wstrict-overflow=4" +Also warn about other simplifications not covered by the above cases. +For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR is simplified to \f(CW\*(C`x * 2\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=5\fR" 4 +.IX Item "-Wstrict-overflow=5" +Also warn about cases where the compiler reduces the magnitude of a +constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR is +simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the +highest warning level because this simplification applies to many +comparisons, so this warning level gives a very large number of +false positives. +.RE +.RS 4 +.RE +.IP "\fB\-Wstringop\-overflow\fR" 4 +.IX Item "-Wstringop-overflow" +.PD 0 +.IP "\fB\-Wstringop\-overflow=\fR\fItype\fR" 4 +.IX Item "-Wstringop-overflow=type" +.PD +Warn for calls to string manipulation functions such as \f(CW\*(C`memcpy\*(C'\fR and +\&\f(CW\*(C`strcpy\*(C'\fR that are determined to overflow the destination buffer. The +optional argument is one greater than the type of Object Size Checking to +perform to determine the size of the destination. +The argument is meaningful only for functions that operate on character arrays +but not for raw memory functions like \f(CW\*(C`memcpy\*(C'\fR which always make use +of Object Size type\-0. The option also warns for calls that specify a size +in excess of the largest possible object or at most \f(CW\*(C`SIZE_MAX / 2\*(C'\fR bytes. +The option produces the best results with optimization enabled but can detect +a small subset of simple buffer overflows even without optimization in +calls to the \s-1GCC\s0 built-in functions like \f(CW\*(C`_\|_builtin_memcpy\*(C'\fR that +correspond to the standard functions. In any case, the option warns about +just a subset of buffer overflows detected by the corresponding overflow +checking built-ins. For example, the option will issue a warning for +the \f(CW\*(C`strcpy\*(C'\fR call below because it copies at least 5 characters +(the string \f(CW"blue"\fR including the terminating \s-1NUL\s0) into the buffer +of size 4. +.Sp +.Vb 11 +\& enum Color { blue, purple, yellow }; +\& const char* f (enum Color clr) +\& { +\& static char buf [4]; +\& const char *str; +\& switch (clr) +\& { +\& case blue: str = "blue"; break; +\& case purple: str = "purple"; break; +\& case yellow: str = "yellow"; break; +\& } +\& +\& return strcpy (buf, str); // warning here +\& } +.Ve +.Sp +Option \fB\-Wstringop\-overflow=2\fR is enabled by default. +.RS 4 +.IP "\fB\-Wstringop\-overflow\fR" 4 +.IX Item "-Wstringop-overflow" +.PD 0 +.IP "\fB\-Wstringop\-overflow=1\fR" 4 +.IX Item "-Wstringop-overflow=1" +.PD +The \fB\-Wstringop\-overflow=1\fR option uses type-zero Object Size Checking +to determine the sizes of destination objects. This is the default setting +of the option. At this setting the option will not warn for writes past +the end of subobjects of larger objects accessed by pointers unless the +size of the largest surrounding object is known. When the destination may +be one of several objects it is assumed to be the largest one of them. On +Linux systems, when optimization is enabled at this setting the option warns +for the same code as when the \f(CW\*(C`_FORTIFY_SOURCE\*(C'\fR macro is defined to +a non-zero value. +.IP "\fB\-Wstringop\-overflow=2\fR" 4 +.IX Item "-Wstringop-overflow=2" +The \fB\-Wstringop\-overflow=2\fR option uses type-one Object Size Checking +to determine the sizes of destination objects. At this setting the option +will warn about overflows when writing to members of the largest complete +objects whose exact size is known. It will, however, not warn for excessive +writes to the same members of unknown objects referenced by pointers since +they may point to arrays containing unknown numbers of elements. +.IP "\fB\-Wstringop\-overflow=3\fR" 4 +.IX Item "-Wstringop-overflow=3" +The \fB\-Wstringop\-overflow=3\fR option uses type-two Object Size Checking +to determine the sizes of destination objects. At this setting the option +warns about overflowing the smallest object or data member. This is the +most restrictive setting of the option that may result in warnings for safe +code. +.IP "\fB\-Wstringop\-overflow=4\fR" 4 +.IX Item "-Wstringop-overflow=4" +The \fB\-Wstringop\-overflow=4\fR option uses type-three Object Size Checking +to determine the sizes of destination objects. At this setting the option +will warn about overflowing any data members, and when the destination is +one of several objects it uses the size of the largest of them to decide +whether to issue a warning. Similarly to \fB\-Wstringop\-overflow=3\fR this +setting of the option may result in warnings for benign code. +.RE +.RS 4 +.RE +.IP "\fB\-Wstringop\-truncation\fR" 4 +.IX Item "-Wstringop-truncation" +Warn for calls to bounded string manipulation functions such as \f(CW\*(C`strncat\*(C'\fR, +\&\f(CW\*(C`strncpy\*(C'\fR, and \f(CW\*(C`stpncpy\*(C'\fR that may either truncate the copied string +or leave the destination unchanged. +.Sp +In the following example, the call to \f(CW\*(C`strncat\*(C'\fR specifies a bound that +is less than the length of the source string. As a result, the copy of +the source will be truncated and so the call is diagnosed. To avoid the +warning use \f(CW\*(C`bufsize \- strlen (buf) \- 1)\*(C'\fR as the bound. +.Sp +.Vb 4 +\& void append (char *buf, size_t bufsize) +\& { +\& strncat (buf, ".txt", 3); +\& } +.Ve +.Sp +As another example, the following call to \f(CW\*(C`strncpy\*(C'\fR results in copying +to \f(CW\*(C`d\*(C'\fR just the characters preceding the terminating \s-1NUL,\s0 without +appending the \s-1NUL\s0 to the end. Assuming the result of \f(CW\*(C`strncpy\*(C'\fR is +necessarily a NUL-terminated string is a common mistake, and so the call +is diagnosed. To avoid the warning when the result is not expected to be +NUL-terminated, call \f(CW\*(C`memcpy\*(C'\fR instead. +.Sp +.Vb 4 +\& void copy (char *d, const char *s) +\& { +\& strncpy (d, s, strlen (s)); +\& } +.Ve +.Sp +In the following example, the call to \f(CW\*(C`strncpy\*(C'\fR specifies the size +of the destination buffer as the bound. If the length of the source +string is equal to or greater than this size the result of the copy will +not be NUL-terminated. Therefore, the call is also diagnosed. To avoid +the warning, specify \f(CW\*(C`sizeof buf \- 1\*(C'\fR as the bound and set the last +element of the buffer to \f(CW\*(C`NUL\*(C'\fR. +.Sp +.Vb 6 +\& void copy (const char *s) +\& { +\& char buf[80]; +\& strncpy (buf, s, sizeof buf); +\& ... +\& } +.Ve +.Sp +In situations where a character array is intended to store a sequence +of bytes with no terminating \f(CW\*(C`NUL\*(C'\fR such an array may be annotated +with attribute \f(CW\*(C`nonstring\*(C'\fR to avoid this warning. Such arrays, +however, are not suitable arguments to functions that expect +\&\f(CW\*(C`NUL\*(C'\fR\-terminated strings. To help detect accidental misuses of +such arrays \s-1GCC\s0 issues warnings unless it can prove that the use is +safe. +.IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR|\fBformat\fR|\fBcold\fR|\fBmalloc\fR]" 4 +.IX Item "-Wsuggest-attribute=[pure|const|noreturn|format|cold|malloc]" +Warn for cases where adding an attribute may be beneficial. The +attributes currently supported are listed below. +.RS 4 +.IP "\fB\-Wsuggest\-attribute=pure\fR" 4 +.IX Item "-Wsuggest-attribute=pure" +.PD 0 +.IP "\fB\-Wsuggest\-attribute=const\fR" 4 +.IX Item "-Wsuggest-attribute=const" +.IP "\fB\-Wsuggest\-attribute=noreturn\fR" 4 +.IX Item "-Wsuggest-attribute=noreturn" +.IP "\fB\-Wmissing\-noreturn\fR" 4 +.IX Item "-Wmissing-noreturn" +.IP "\fB\-Wsuggest\-attribute=malloc\fR" 4 +.IX Item "-Wsuggest-attribute=malloc" +.PD +Warn about functions that might be candidates for attributes +\&\f(CW\*(C`pure\*(C'\fR, \f(CW\*(C`const\*(C'\fR or \f(CW\*(C`noreturn\*(C'\fR or \f(CW\*(C`malloc\*(C'\fR. The compiler +only warns for functions visible in other compilation units or (in the case of +\&\f(CW\*(C`pure\*(C'\fR and \f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns +normally. A function returns normally if it doesn't contain an infinite loop or +return abnormally by throwing, calling \f(CW\*(C`abort\*(C'\fR or trapping. This analysis +requires option \fB\-fipa\-pure\-const\fR, which is enabled by default at +\&\fB\-O\fR and higher. Higher optimization levels improve the accuracy +of the analysis. +.IP "\fB\-Wsuggest\-attribute=format\fR" 4 +.IX Item "-Wsuggest-attribute=format" +.PD 0 +.IP "\fB\-Wmissing\-format\-attribute\fR" 4 +.IX Item "-Wmissing-format-attribute" +.PD +Warn about function pointers that might be candidates for \f(CW\*(C`format\*(C'\fR +attributes. Note these are only possible candidates, not absolute ones. +\&\s-1GCC\s0 guesses that function pointers with \f(CW\*(C`format\*(C'\fR attributes that +are used in assignment, initialization, parameter passing or return +statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the +resulting type. I.e. the left-hand side of the assignment or +initialization, the type of the parameter variable, or the return type +of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR +attribute to avoid the warning. +.Sp +\&\s-1GCC\s0 also warns about function definitions that might be +candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only +possible candidates. \s-1GCC\s0 guesses that \f(CW\*(C`format\*(C'\fR attributes +might be appropriate for any function that calls a function like +\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the +case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are +appropriate may not be detected. +.IP "\fB\-Wsuggest\-attribute=cold\fR" 4 +.IX Item "-Wsuggest-attribute=cold" +Warn about functions that might be candidates for \f(CW\*(C`cold\*(C'\fR attribute. This +is based on static detection and generally will only warn about functions which +always leads to a call to another \f(CW\*(C`cold\*(C'\fR function such as wrappers of +\&\*(C+ \f(CW\*(C`throw\*(C'\fR or fatal error reporting functions leading to \f(CW\*(C`abort\*(C'\fR. +.RE +.RS 4 +.RE +.IP "\fB\-Wsuggest\-final\-types\fR" 4 +.IX Item "-Wsuggest-final-types" +Warn about types with virtual methods where code quality would be improved +if the type were declared with the \*(C+11 \f(CW\*(C`final\*(C'\fR specifier, +or, if possible, +declared in an anonymous namespace. This allows \s-1GCC\s0 to more aggressively +devirtualize the polymorphic calls. This warning is more effective with link +time optimization, where the information about the class hierarchy graph is +more complete. +.IP "\fB\-Wsuggest\-final\-methods\fR" 4 +.IX Item "-Wsuggest-final-methods" +Warn about virtual methods where code quality would be improved if the method +were declared with the \*(C+11 \f(CW\*(C`final\*(C'\fR specifier, +or, if possible, its type were +declared in an anonymous namespace or with the \f(CW\*(C`final\*(C'\fR specifier. +This warning is +more effective with link-time optimization, where the information about the +class hierarchy graph is more complete. It is recommended to first consider +suggestions of \fB\-Wsuggest\-final\-types\fR and then rebuild with new +annotations. +.IP "\fB\-Wsuggest\-override\fR" 4 +.IX Item "-Wsuggest-override" +Warn about overriding virtual functions that are not marked with the override +keyword. +.IP "\fB\-Walloc\-zero\fR" 4 +.IX Item "-Walloc-zero" +Warn about calls to allocation functions decorated with attribute +\&\f(CW\*(C`alloc_size\*(C'\fR that specify zero bytes, including those to the built-in +forms of the functions \f(CW\*(C`aligned_alloc\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`calloc\*(C'\fR, +\&\f(CW\*(C`malloc\*(C'\fR, and \f(CW\*(C`realloc\*(C'\fR. Because the behavior of these functions +when called with a zero size differs among implementations (and in the case +of \f(CW\*(C`realloc\*(C'\fR has been deprecated) relying on it may result in subtle +portability bugs and should be avoided. +.IP "\fB\-Walloc\-size\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Walloc-size-larger-than=byte-size" +Warn about calls to functions decorated with attribute \f(CW\*(C`alloc_size\*(C'\fR +that attempt to allocate objects larger than the specified number of bytes, +or where the result of the size computation in an integer type with infinite +precision would exceed the value of \fB\s-1PTRDIFF_MAX\s0\fR on the target. +\&\fB\-Walloc\-size\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-alloc\-size\-larger\-than\fR. +.IP "\fB\-Wno\-alloc\-size\-larger\-than\fR" 4 +.IX Item "-Wno-alloc-size-larger-than" +Disable \fB\-Walloc\-size\-larger\-than=\fR warnings. The option is +equivalent to \fB\-Walloc\-size\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or +larger. +.IP "\fB\-Walloca\fR" 4 +.IX Item "-Walloca" +This option warns on all uses of \f(CW\*(C`alloca\*(C'\fR in the source. +.IP "\fB\-Walloca\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Walloca-larger-than=byte-size" +This option warns on calls to \f(CW\*(C`alloca\*(C'\fR with an integer argument whose +value is either zero, or that is not bounded by a controlling predicate +that limits its value to at most \fIbyte-size\fR. It also warns for calls +to \f(CW\*(C`alloca\*(C'\fR where the bound value is unknown. Arguments of non-integer +types are considered unbounded even if they appear to be constrained to +the expected range. +.Sp +For example, a bounded case of \f(CW\*(C`alloca\*(C'\fR could be: +.Sp +.Vb 9 +\& void func (size_t n) +\& { +\& void *p; +\& if (n <= 1000) +\& p = alloca (n); +\& else +\& p = malloc (n); +\& f (p); +\& } +.Ve +.Sp +In the above example, passing \f(CW\*(C`\-Walloca\-larger\-than=1000\*(C'\fR would not +issue a warning because the call to \f(CW\*(C`alloca\*(C'\fR is known to be at most +1000 bytes. However, if \f(CW\*(C`\-Walloca\-larger\-than=500\*(C'\fR were passed, +the compiler would emit a warning. +.Sp +Unbounded uses, on the other hand, are uses of \f(CW\*(C`alloca\*(C'\fR with no +controlling predicate constraining its integer argument. For example: +.Sp +.Vb 5 +\& void func () +\& { +\& void *p = alloca (n); +\& f (p); +\& } +.Ve +.Sp +If \f(CW\*(C`\-Walloca\-larger\-than=500\*(C'\fR were passed, the above would trigger +a warning, but this time because of the lack of bounds checking. +.Sp +Note, that even seemingly correct code involving signed integers could +cause a warning: +.Sp +.Vb 8 +\& void func (signed int n) +\& { +\& if (n < 500) +\& { +\& p = alloca (n); +\& f (p); +\& } +\& } +.Ve +.Sp +In the above example, \fIn\fR could be negative, causing a larger than +expected argument to be implicitly cast into the \f(CW\*(C`alloca\*(C'\fR call. +.Sp +This option also warns when \f(CW\*(C`alloca\*(C'\fR is used in a loop. +.Sp +\&\fB\-Walloca\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default +but is usually only effective when \fB\-ftree\-vrp\fR is active (default +for \fB\-O2\fR and above). +.Sp +See also \fB\-Wvla\-larger\-than=\fR\fBbyte-size\fR. +.IP "\fB\-Wno\-alloca\-larger\-than\fR" 4 +.IX Item "-Wno-alloca-larger-than" +Disable \fB\-Walloca\-larger\-than=\fR warnings. The option is +equivalent to \fB\-Walloca\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Warray\-bounds\fR" 4 +.IX Item "-Warray-bounds" +.PD 0 +.IP "\fB\-Warray\-bounds=\fR\fIn\fR" 4 +.IX Item "-Warray-bounds=n" +.PD +This option is only active when \fB\-ftree\-vrp\fR is active +(default for \fB\-O2\fR and above). It warns about subscripts to arrays +that are always out of bounds. This warning is enabled by \fB\-Wall\fR. +.RS 4 +.IP "\fB\-Warray\-bounds=1\fR" 4 +.IX Item "-Warray-bounds=1" +This is the warning level of \fB\-Warray\-bounds\fR and is enabled +by \fB\-Wall\fR; higher levels are not, and must be explicitly requested. +.IP "\fB\-Warray\-bounds=2\fR" 4 +.IX Item "-Warray-bounds=2" +This warning level also warns about out of bounds access for +arrays at the end of a struct and for arrays accessed through +pointers. This warning level may give a larger number of +false positives and is deactivated by default. +.RE +.RS 4 +.RE +.IP "\fB\-Wattribute\-alias=\fR\fIn\fR" 4 +.IX Item "-Wattribute-alias=n" +.PD 0 +.IP "\fB\-Wno\-attribute\-alias\fR" 4 +.IX Item "-Wno-attribute-alias" +.PD +Warn about declarations using the \f(CW\*(C`alias\*(C'\fR and similar attributes whose +target is incompatible with the type of the alias. +.RS 4 +.IP "\fB\-Wattribute\-alias=1\fR" 4 +.IX Item "-Wattribute-alias=1" +The default warning level of the \fB\-Wattribute\-alias\fR option diagnoses +incompatibilities between the type of the alias declaration and that of its +target. Such incompatibilities are typically indicative of bugs. +.IP "\fB\-Wattribute\-alias=2\fR" 4 +.IX Item "-Wattribute-alias=2" +At this level \fB\-Wattribute\-alias\fR also diagnoses cases where +the attributes of the alias declaration are more restrictive than the +attributes applied to its target. These mismatches can potentially +result in incorrect code generation. In other cases they may be +benign and could be resolved simply by adding the missing attribute to +the target. For comparison, see the \fB\-Wmissing\-attributes\fR +option, which controls diagnostics when the alias declaration is less +restrictive than the target, rather than more restrictive. +.Sp +Attributes considered include \f(CW\*(C`alloc_align\*(C'\fR, \f(CW\*(C`alloc_size\*(C'\fR, +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`const\*(C'\fR, \f(CW\*(C`hot\*(C'\fR, \f(CW\*(C`leaf\*(C'\fR, \f(CW\*(C`malloc\*(C'\fR, +\&\f(CW\*(C`nonnull\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, \f(CW\*(C`nothrow\*(C'\fR, \f(CW\*(C`pure\*(C'\fR, +\&\f(CW\*(C`returns_nonnull\*(C'\fR, and \f(CW\*(C`returns_twice\*(C'\fR. +.RE +.RS 4 +.Sp +\&\fB\-Wattribute\-alias\fR is equivalent to \fB\-Wattribute\-alias=1\fR. +This is the default. You can disable these warnings with either +\&\fB\-Wno\-attribute\-alias\fR or \fB\-Wattribute\-alias=0\fR. +.RE +.IP "\fB\-Wbool\-compare\fR" 4 +.IX Item "-Wbool-compare" +Warn about boolean expression compared with an integer value different from +\&\f(CW\*(C`true\*(C'\fR/\f(CW\*(C`false\*(C'\fR. For instance, the following comparison is +always false: +.Sp +.Vb 3 +\& int n = 5; +\& ... +\& if ((n > 1) == 2) { ... } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wbool\-operation\fR" 4 +.IX Item "-Wbool-operation" +Warn about suspicious operations on expressions of a boolean type. For +instance, bitwise negation of a boolean is very likely a bug in the program. +For C, this warning also warns about incrementing or decrementing a boolean, +which rarely makes sense. (In \*(C+, decrementing a boolean is always invalid. +Incrementing a boolean is invalid in \*(C+17, and deprecated otherwise.) +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wduplicated\-branches\fR" 4 +.IX Item "-Wduplicated-branches" +Warn when an if-else has identical branches. This warning detects cases like +.Sp +.Vb 4 +\& if (p != NULL) +\& return 0; +\& else +\& return 0; +.Ve +.Sp +It doesn't warn when both branches contain just a null statement. This warning +also warn for conditional operators: +.Sp +.Vb 1 +\& int i = x ? *p : *p; +.Ve +.IP "\fB\-Wduplicated\-cond\fR" 4 +.IX Item "-Wduplicated-cond" +Warn about duplicated conditions in an if-else-if chain. For instance, +warn for the following code: +.Sp +.Vb 2 +\& if (p\->q != NULL) { ... } +\& else if (p\->q != NULL) { ... } +.Ve +.IP "\fB\-Wframe\-address\fR" 4 +.IX Item "-Wframe-address" +Warn when the \fB_\|_builtin_frame_address\fR or \fB_\|_builtin_return_address\fR +is called with an argument greater than 0. Such calls may return indeterminate +values or crash the program. The warning is included in \fB\-Wall\fR. +.IP "\fB\-Wno\-discarded\-qualifiers\fR (C and Objective-C only)" 4 +.IX Item "-Wno-discarded-qualifiers (C and Objective-C only)" +Do not warn if type qualifiers on pointers are being discarded. +Typically, the compiler warns if a \f(CW\*(C`const char *\*(C'\fR variable is +passed to a function that takes a \f(CW\*(C`char *\*(C'\fR parameter. This option +can be used to suppress such a warning. +.IP "\fB\-Wno\-discarded\-array\-qualifiers\fR (C and Objective-C only)" 4 +.IX Item "-Wno-discarded-array-qualifiers (C and Objective-C only)" +Do not warn if type qualifiers on arrays which are pointer targets +are being discarded. Typically, the compiler warns if a +\&\f(CW\*(C`const int (*)[]\*(C'\fR variable is passed to a function that +takes a \f(CW\*(C`int (*)[]\*(C'\fR parameter. This option can be used to +suppress such a warning. +.IP "\fB\-Wno\-incompatible\-pointer\-types\fR (C and Objective-C only)" 4 +.IX Item "-Wno-incompatible-pointer-types (C and Objective-C only)" +Do not warn when there is a conversion between pointers that have incompatible +types. This warning is for cases not covered by \fB\-Wno\-pointer\-sign\fR, +which warns for pointer argument passing or assignment with different +signedness. +.IP "\fB\-Wno\-int\-conversion\fR (C and Objective-C only)" 4 +.IX Item "-Wno-int-conversion (C and Objective-C only)" +Do not warn about incompatible integer to pointer and pointer to integer +conversions. This warning is about implicit conversions; for explicit +conversions the warnings \fB\-Wno\-int\-to\-pointer\-cast\fR and +\&\fB\-Wno\-pointer\-to\-int\-cast\fR may be used. +.IP "\fB\-Wno\-div\-by\-zero\fR" 4 +.IX Item "-Wno-div-by-zero" +Do not warn about compile-time integer division by zero. Floating-point +division by zero is not warned about, as it can be a legitimate way of +obtaining infinities and NaNs. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Print warning messages for constructs found in system header files. +Warnings from system headers are normally suppressed, on the assumption +that they usually do not indicate real problems and would only make the +compiler output harder to read. Using this command-line option tells +\&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user +code. However, note that using \fB\-Wall\fR in conjunction with this +option does \fInot\fR warn about unknown pragmas in system +headers\-\-\-for that, \fB\-Wunknown\-pragmas\fR must also be used. +.IP "\fB\-Wtautological\-compare\fR" 4 +.IX Item "-Wtautological-compare" +Warn if a self-comparison always evaluates to true or false. This +warning detects various mistakes such as: +.Sp +.Vb 3 +\& int i = 1; +\& ... +\& if (i > i) { ... } +.Ve +.Sp +This warning also warns about bitwise comparisons that always evaluate +to true or false, for instance: +.Sp +.Vb 1 +\& if ((a & 16) == 10) { ... } +.Ve +.Sp +will always be false. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wtrampolines\fR" 4 +.IX Item "-Wtrampolines" +Warn about trampolines generated for pointers to nested functions. +A trampoline is a small piece of data or code that is created at run +time on the stack when the address of a nested function is taken, and is +used to call the nested function indirectly. For some targets, it is +made up of data only and thus requires no special treatment. But, for +most targets, it is made up of code and thus requires the stack to be +made executable in order for the program to work properly. +.IP "\fB\-Wfloat\-equal\fR" 4 +.IX Item "-Wfloat-equal" +Warn if floating-point values are used in equality comparisons. +.Sp +The idea behind this is that sometimes it is convenient (for the +programmer) to consider floating-point values as approximations to +infinitely precise real numbers. If you are doing this, then you need +to compute (by analyzing the code, or in some other way) the maximum or +likely maximum error that the computation introduces, and allow for it +when performing comparisons (and when producing output, but that's a +different problem). In particular, instead of testing for equality, you +should check to see whether the two values have ranges that overlap; and +this is done with the relational operators, so equality comparisons are +probably mistaken. +.IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional (C and Objective-C only)" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO C.\s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C +equivalent, and/or problematic constructs that should be avoided. +.RS 4 +.IP "*" 4 +Macro parameters that appear within string literals in the macro body. +In traditional C macro replacement takes place within string literals, +but in \s-1ISO C\s0 it does not. +.IP "*" 4 +In traditional C, some preprocessor directives did not exist. +Traditional preprocessors only considered a line to be a directive +if the \fB#\fR appeared in column 1 on the line. Therefore +\&\fB\-Wtraditional\fR warns about directives that traditional C +understands but ignores because the \fB#\fR does not appear as the +first character on the line. It also suggests you hide directives like +\&\f(CW\*(C`#pragma\*(C'\fR not understood by traditional C by indenting them. Some +traditional implementations do not recognize \f(CW\*(C`#elif\*(C'\fR, so this option +suggests avoiding it altogether. +.IP "*" 4 +A function-like macro that appears without arguments. +.IP "*" 4 +The unary plus operator. +.IP "*" 4 +The \fBU\fR integer constant suffix, or the \fBF\fR or \fBL\fR floating-point +constant suffixes. (Traditional C does support the \fBL\fR suffix on integer +constants.) Note, these suffixes appear in macros defined in the system +headers of most modern systems, e.g. the \fB_MIN\fR/\fB_MAX\fR macros in \f(CW\*(C`\*(C'\fR. +Use of these macros in user code might normally lead to spurious +warnings, however \s-1GCC\s0's integrated preprocessor has enough context to +avoid warning in these cases. +.IP "*" 4 +A function declared external in one block and then used after the end of +the block. +.IP "*" 4 +A \f(CW\*(C`switch\*(C'\fR statement has an operand of type \f(CW\*(C`long\*(C'\fR. +.IP "*" 4 +A non\-\f(CW\*(C`static\*(C'\fR function declaration follows a \f(CW\*(C`static\*(C'\fR one. +This construct is not accepted by some traditional C compilers. +.IP "*" 4 +The \s-1ISO\s0 type of an integer constant has a different width or +signedness from its traditional type. This warning is only issued if +the base of the constant is ten. I.e. hexadecimal or octal values, which +typically represent bit patterns, are not warned about. +.IP "*" 4 +Usage of \s-1ISO\s0 string concatenation is detected. +.IP "*" 4 +Initialization of automatic aggregates. +.IP "*" 4 +Identifier conflicts with labels. Traditional C lacks a separate +namespace for labels. +.IP "*" 4 +Initialization of unions. If the initializer is zero, the warning is +omitted. This is done under the assumption that the zero initializer in +user code appears conditioned on e.g. \f(CW\*(C`_\|_STDC_\|_\*(C'\fR to avoid missing +initializer warnings and relies on default initialization to zero in the +traditional C case. +.IP "*" 4 +Conversions by prototypes between fixed/floating\-point values and vice +versa. The absence of these prototypes when compiling with traditional +C causes serious problems. This is a subset of the possible +conversion warnings; for the full set use \fB\-Wtraditional\-conversion\fR. +.IP "*" 4 +Use of \s-1ISO C\s0 style function definitions. This warning intentionally is +\&\fInot\fR issued for prototype declarations or variadic functions +because these \s-1ISO C\s0 features appear in your code when using +libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and +\&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions +because that feature is already a \s-1GCC\s0 extension and thus not relevant to +traditional C compatibility. +.RE +.RS 4 +.RE +.IP "\fB\-Wtraditional\-conversion\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional-conversion (C and Objective-C only)" +Warn if a prototype causes a type conversion that is different from what +would happen to the same argument in the absence of a prototype. This +includes conversions of fixed point to floating and vice versa, and +conversions changing the width or signedness of a fixed-point argument +except when the same as the default promotion. +.IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 +.IX Item "-Wdeclaration-after-statement (C and Objective-C only)" +Warn when a declaration is found after a statement in a block. This +construct, known from \*(C+, was introduced with \s-1ISO C99\s0 and is by default +allowed in \s-1GCC.\s0 It is not supported by \s-1ISO C90.\s0 +.IP "\fB\-Wshadow\fR" 4 +.IX Item "-Wshadow" +Warn whenever a local variable or type declaration shadows another +variable, parameter, type, class member (in \*(C+), or instance variable +(in Objective-C) or whenever a built-in function is shadowed. Note +that in \*(C+, the compiler warns if a local variable shadows an +explicit typedef, but not if it shadows a struct/class/enum. +Same as \fB\-Wshadow=global\fR. +.IP "\fB\-Wno\-shadow\-ivar\fR (Objective-C only)" 4 +.IX Item "-Wno-shadow-ivar (Objective-C only)" +Do not warn whenever a local variable shadows an instance variable in an +Objective-C method. +.IP "\fB\-Wshadow=global\fR" 4 +.IX Item "-Wshadow=global" +The default for \fB\-Wshadow\fR. Warns for any (global) shadowing. +.IP "\fB\-Wshadow=local\fR" 4 +.IX Item "-Wshadow=local" +Warn when a local variable shadows another local variable or parameter. +This warning is enabled by \fB\-Wshadow=global\fR. +.IP "\fB\-Wshadow=compatible\-local\fR" 4 +.IX Item "-Wshadow=compatible-local" +Warn when a local variable shadows another local variable or parameter +whose type is compatible with that of the shadowing variable. In \*(C+, +type compatibility here means the type of the shadowing variable can be +converted to that of the shadowed variable. The creation of this flag +(in addition to \fB\-Wshadow=local\fR) is based on the idea that when +a local variable shadows another one of incompatible type, it is most +likely intentional, not a bug or typo, as shown in the following example: +.Sp +.Vb 8 +\& for (SomeIterator i = SomeObj.begin(); i != SomeObj.end(); ++i) +\& { +\& for (int i = 0; i < N; ++i) +\& { +\& ... +\& } +\& ... +\& } +.Ve +.Sp +Since the two variable \f(CW\*(C`i\*(C'\fR in the example above have incompatible types, +enabling only \fB\-Wshadow=compatible\-local\fR will not emit a warning. +Because their types are incompatible, if a programmer accidentally uses one +in place of the other, type checking will catch that and emit an error or +warning. So not warning (about shadowing) in this case will not lead to +undetected bugs. Use of this flag instead of \fB\-Wshadow=local\fR can +possibly reduce the number of warnings triggered by intentional shadowing. +.Sp +This warning is enabled by \fB\-Wshadow=local\fR. +.IP "\fB\-Wlarger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Wlarger-than=byte-size" +Warn whenever an object is defined whose size exceeds \fIbyte-size\fR. +\&\fB\-Wlarger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-larger\-than\fR. +.IP "\fB\-Wno\-larger\-than\fR" 4 +.IX Item "-Wno-larger-than" +Disable \fB\-Wlarger\-than=\fR warnings. The option is equivalent +to \fB\-Wlarger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wframe\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Wframe-larger-than=byte-size" +Warn if the size of a function frame exceeds \fIbyte-size\fR. +The computation done to determine the stack frame size is approximate +and not conservative. +The actual requirements may be somewhat greater than \fIbyte-size\fR +even if you do not get a warning. In addition, any space allocated +via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related constructs +is not included by the compiler when determining +whether or not to issue a warning. +\&\fB\-Wframe\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-frame\-larger\-than\fR. +.IP "\fB\-Wno\-frame\-larger\-than\fR" 4 +.IX Item "-Wno-frame-larger-than" +Disable \fB\-Wframe\-larger\-than=\fR warnings. The option is equivalent +to \fB\-Wframe\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wno\-free\-nonheap\-object\fR" 4 +.IX Item "-Wno-free-nonheap-object" +Do not warn when attempting to free an object that was not allocated +on the heap. +.IP "\fB\-Wstack\-usage=\fR\fIbyte-size\fR" 4 +.IX Item "-Wstack-usage=byte-size" +Warn if the stack usage of a function might exceed \fIbyte-size\fR. +The computation done to determine the stack usage is conservative. +Any space allocated via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related +constructs is included by the compiler when determining whether or not to +issue a warning. +.Sp +The message is in keeping with the output of \fB\-fstack\-usage\fR. +.RS 4 +.IP "*" 4 +If the stack usage is fully static but exceeds the specified amount, it's: +.Sp +.Vb 1 +\& warning: stack usage is 1120 bytes +.Ve +.IP "*" 4 +If the stack usage is (partly) dynamic but bounded, it's: +.Sp +.Vb 1 +\& warning: stack usage might be 1648 bytes +.Ve +.IP "*" 4 +If the stack usage is (partly) dynamic and not bounded, it's: +.Sp +.Vb 1 +\& warning: stack usage might be unbounded +.Ve +.RE +.RS 4 +.Sp +\&\fB\-Wstack\-usage=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default. +Warnings controlled by the option can be disabled either by specifying +\&\fIbyte-size\fR of \fB\s-1SIZE_MAX\s0\fR or more or by +\&\fB\-Wno\-stack\-usage\fR. +.RE +.IP "\fB\-Wno\-stack\-usage\fR" 4 +.IX Item "-Wno-stack-usage" +Disable \fB\-Wstack\-usage=\fR warnings. The option is equivalent +to \fB\-Wstack\-usage=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4 +.IX Item "-Wunsafe-loop-optimizations" +Warn if the loop cannot be optimized because the compiler cannot +assume anything on the bounds of the loop indices. With +\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler makes +such assumptions. +.IP "\fB\-Wno\-pedantic\-ms\-format\fR (MinGW targets only)" 4 +.IX Item "-Wno-pedantic-ms-format (MinGW targets only)" +When used in combination with \fB\-Wformat\fR +and \fB\-pedantic\fR without \s-1GNU\s0 extensions, this option +disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format +width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets, +which depend on the \s-1MS\s0 runtime. +.IP "\fB\-Waligned\-new\fR" 4 +.IX Item "-Waligned-new" +Warn about a new-expression of a type that requires greater alignment +than the \f(CW\*(C`alignof(std::max_align_t)\*(C'\fR but uses an allocation +function without an explicit alignment parameter. This option is +enabled by \fB\-Wall\fR. +.Sp +Normally this only warns about global allocation functions, but +\&\fB\-Waligned\-new=all\fR also warns about class member allocation +functions. +.IP "\fB\-Wplacement\-new\fR" 4 +.IX Item "-Wplacement-new" +.PD 0 +.IP "\fB\-Wplacement\-new=\fR\fIn\fR" 4 +.IX Item "-Wplacement-new=n" +.PD +Warn about placement new expressions with undefined behavior, such as +constructing an object in a buffer that is smaller than the type of +the object. For example, the placement new expression below is diagnosed +because it attempts to construct an array of 64 integers in a buffer only +64 bytes large. +.Sp +.Vb 2 +\& char buf [64]; +\& new (buf) int[64]; +.Ve +.Sp +This warning is enabled by default. +.RS 4 +.IP "\fB\-Wplacement\-new=1\fR" 4 +.IX Item "-Wplacement-new=1" +This is the default warning level of \fB\-Wplacement\-new\fR. At this +level the warning is not issued for some strictly undefined constructs that +\&\s-1GCC\s0 allows as extensions for compatibility with legacy code. For example, +the following \f(CW\*(C`new\*(C'\fR expression is not diagnosed at this level even +though it has undefined behavior according to the \*(C+ standard because +it writes past the end of the one-element array. +.Sp +.Vb 3 +\& struct S { int n, a[1]; }; +\& S *s = (S *)malloc (sizeof *s + 31 * sizeof s\->a[0]); +\& new (s\->a)int [32](); +.Ve +.IP "\fB\-Wplacement\-new=2\fR" 4 +.IX Item "-Wplacement-new=2" +At this level, in addition to diagnosing all the same constructs as at level +1, a diagnostic is also issued for placement new expressions that construct +an object in the last member of structure whose type is an array of a single +element and whose size is less than the size of the object being constructed. +While the previous example would be diagnosed, the following construct makes +use of the flexible member array extension to avoid the warning at level 2. +.Sp +.Vb 3 +\& struct S { int n, a[]; }; +\& S *s = (S *)malloc (sizeof *s + 32 * sizeof s\->a[0]); +\& new (s\->a)int [32](); +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-Wpointer\-arith\fR" 4 +.IX Item "-Wpointer-arith" +Warn about anything that depends on the \*(L"size of\*(R" a function type or +of \f(CW\*(C`void\*(C'\fR. \s-1GNU C\s0 assigns these types a size of 1, for +convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers +to functions. In \*(C+, warn also when an arithmetic operation involves +\&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-Wpedantic\fR. +.IP "\fB\-Wpointer\-compare\fR" 4 +.IX Item "-Wpointer-compare" +Warn if a pointer is compared with a zero character constant. This usually +means that the pointer was meant to be dereferenced. For example: +.Sp +.Vb 3 +\& const char *p = foo (); +\& if (p == \*(Aq\e0\*(Aq) +\& return 42; +.Ve +.Sp +Note that the code above is invalid in \*(C+11. +.Sp +This warning is enabled by default. +.IP "\fB\-Wtype\-limits\fR" 4 +.IX Item "-Wtype-limits" +Warn if a comparison is always true or always false due to the limited +range of the data type, but do not warn for constant expressions. For +example, warn if an unsigned variable is compared against zero with +\&\f(CW\*(C`<\*(C'\fR or \f(CW\*(C`>=\*(C'\fR. This warning is also enabled by +\&\fB\-Wextra\fR. +.IP "\fB\-Wabsolute\-value\fR (C and Objective-C only)" 4 +.IX Item "-Wabsolute-value (C and Objective-C only)" +Warn for calls to standard functions that compute the absolute value +of an argument when a more appropriate standard function is available. +For example, calling \f(CW\*(C`abs(3.14)\*(C'\fR triggers the warning because the +appropriate function to call to compute the absolute value of a double +argument is \f(CW\*(C`fabs\*(C'\fR. The option also triggers warnings when the +argument in a call to such a function has an unsigned type. This +warning can be suppressed with an explicit type cast and it is also +enabled by \fB\-Wextra\fR. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +.PD 0 +.IP "\fB\-Wcomments\fR" 4 +.IX Item "-Wcomments" +.PD +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a backslash-newline appears in a \fB//\fR comment. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Warn if any trigraphs are encountered that might change the meaning of +the program. Trigraphs within comments are not warned about, +except those that would form escaped newlines. +.Sp +This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not +given, this option is still enabled unless trigraphs are enabled. To +get trigraph conversion without warnings, but get the other +\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn if an undefined identifier is evaluated in an \f(CW\*(C`#if\*(C'\fR directive. +Such identifiers are replaced with zero. +.IP "\fB\-Wexpansion\-to\-defined\fR" 4 +.IX Item "-Wexpansion-to-defined" +Warn whenever \fBdefined\fR is encountered in the expansion of a macro +(including the case where the macro is expanded by an \fB#if\fR directive). +Such usage is not portable. +This warning is also enabled by \fB\-Wpedantic\fR and \fB\-Wextra\fR. +.IP "\fB\-Wunused\-macros\fR" 4 +.IX Item "-Wunused-macros" +Warn about macros defined in the main file that are unused. A macro +is \fIused\fR if it is expanded or tested for existence at least once. +The preprocessor also warns if the macro has not been used at the +time it is redefined or undefined. +.Sp +Built-in macros, macros defined on the command line, and macros +defined in include files are not warned about. +.Sp +\&\fINote:\fR If a macro is actually used, but only used in skipped +conditional blocks, then the preprocessor reports it as unused. To avoid the +warning in such a case, you might improve the scope of the macro's +definition by, for example, moving it into the first skipped block. +Alternatively, you could provide a dummy use with something like: +.Sp +.Vb 2 +\& #if defined the_macro_causing_the_warning +\& #endif +.Ve +.IP "\fB\-Wno\-endif\-labels\fR" 4 +.IX Item "-Wno-endif-labels" +Do not warn whenever an \f(CW\*(C`#else\*(C'\fR or an \f(CW\*(C`#endif\*(C'\fR are followed by text. +This sometimes happens in older programs with code of the form +.Sp +.Vb 5 +\& #if FOO +\& ... +\& #else FOO +\& ... +\& #endif FOO +.Ve +.Sp +The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments. +This warning is on by default. +.IP "\fB\-Wbad\-function\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wbad-function-cast (C and Objective-C only)" +Warn when a function call is cast to a non-matching type. +For example, warn if a call to a function returning an integer type +is cast to a pointer type. +.IP "\fB\-Wc90\-c99\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc90-c99-compat (C and Objective-C only)" +Warn about features not present in \s-1ISO C90,\s0 but present in \s-1ISO C99.\s0 +For instance, warn about use of variable length arrays, \f(CW\*(C`long long\*(C'\fR +type, \f(CW\*(C`bool\*(C'\fR type, compound literals, designated initializers, and so +on. This option is independent of the standards mode. Warnings are disabled +in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. +.IP "\fB\-Wc99\-c11\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc99-c11-compat (C and Objective-C only)" +Warn about features not present in \s-1ISO C99,\s0 but present in \s-1ISO C11.\s0 +For instance, warn about use of anonymous structures and unions, +\&\f(CW\*(C`_Atomic\*(C'\fR type qualifier, \f(CW\*(C`_Thread_local\*(C'\fR storage-class specifier, +\&\f(CW\*(C`_Alignas\*(C'\fR specifier, \f(CW\*(C`Alignof\*(C'\fR operator, \f(CW\*(C`_Generic\*(C'\fR keyword, +and so on. This option is independent of the standards mode. Warnings are +disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. +.IP "\fB\-Wc11\-c2x\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc11-c2x-compat (C and Objective-C only)" +Warn about features not present in \s-1ISO C11,\s0 but present in \s-1ISO C2X.\s0 +For instance, warn about omitting the string in \f(CW\*(C`_Static_assert\*(C'\fR. +This option is independent of the standards mode. Warnings are +disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. +.IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc++-compat (C and Objective-C only)" +Warn about \s-1ISO C\s0 constructs that are outside of the common subset of +\&\s-1ISO C\s0 and \s-1ISO \*(C+,\s0 e.g. request for implicit conversion from +\&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. +.IP "\fB\-Wc++11\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++11-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 1998\s0 +and \s-1ISO \*(C+ 2011,\s0 e.g., identifiers in \s-1ISO \*(C+ 1998\s0 that are keywords +in \s-1ISO \*(C+ 2011.\s0 This warning turns on \fB\-Wnarrowing\fR and is +enabled by \fB\-Wall\fR. +.IP "\fB\-Wc++14\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++14-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 2011\s0 +and \s-1ISO \*(C+ 2014.\s0 This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wc++17\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++17-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 2014\s0 +and \s-1ISO \*(C+ 2017.\s0 This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wcast\-qual\fR" 4 +.IX Item "-Wcast-qual" +Warn whenever a pointer is cast so as to remove a type qualifier from +the target type. For example, warn if a \f(CW\*(C`const char *\*(C'\fR is cast +to an ordinary \f(CW\*(C`char *\*(C'\fR. +.Sp +Also warn when making a cast that introduces a type qualifier in an +unsafe way. For example, casting \f(CW\*(C`char **\*(C'\fR to \f(CW\*(C`const char **\*(C'\fR +is unsafe, as in this example: +.Sp +.Vb 6 +\& /* p is char ** value. */ +\& const char **q = (const char **) p; +\& /* Assignment of readonly string to const char * is OK. */ +\& *q = "string"; +\& /* Now char** pointer points to read\-only memory. */ +\& **p = \*(Aqb\*(Aq; +.Ve +.IP "\fB\-Wcast\-align\fR" 4 +.IX Item "-Wcast-align" +Warn whenever a pointer is cast such that the required alignment of the +target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to +an \f(CW\*(C`int *\*(C'\fR on machines where integers can only be accessed at +two\- or four-byte boundaries. +.IP "\fB\-Wcast\-align=strict\fR" 4 +.IX Item "-Wcast-align=strict" +Warn whenever a pointer is cast such that the required alignment of the +target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to +an \f(CW\*(C`int *\*(C'\fR regardless of the target machine. +.IP "\fB\-Wcast\-function\-type\fR" 4 +.IX Item "-Wcast-function-type" +Warn when a function pointer is cast to an incompatible function pointer. +In a cast involving function types with a variable argument list only +the types of initial arguments that are provided are considered. +Any parameter of pointer-type matches any other pointer-type. Any benign +differences in integral types are ignored, like \f(CW\*(C`int\*(C'\fR vs. \f(CW\*(C`long\*(C'\fR +on \s-1ILP32\s0 targets. Likewise type qualifiers are ignored. The function +type \f(CW\*(C`void (*) (void)\*(C'\fR is special and matches everything, which can +be used to suppress this warning. +In a cast involving pointer to member types this warning warns whenever +the type cast is changing the pointer to member type. +This warning is enabled by \fB\-Wextra\fR. +.IP "\fB\-Wwrite\-strings\fR" 4 +.IX Item "-Wwrite-strings" +When compiling C, give string constants the type \f(CW\*(C`const +char[\f(CIlength\f(CW]\*(C'\fR so that copying the address of one into a +non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer produces a warning. These +warnings help you find at compile time code that can try to write +into a string constant, but only if you have been very careful about +using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it is +just a nuisance. This is why we did not make \fB\-Wall\fR request +these warnings. +.Sp +When compiling \*(C+, warn about the deprecated conversion from string +literals to \f(CW\*(C`char *\*(C'\fR. This warning is enabled by default for \*(C+ +programs. +.IP "\fB\-Wcatch\-value\fR" 4 +.IX Item "-Wcatch-value" +.PD 0 +.IP "\fB\-Wcatch\-value=\fR\fIn\fR\fB \fR(\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wcatch-value=n ( and Objective- only)" +.PD +Warn about catch handlers that do not catch via reference. +With \fB\-Wcatch\-value=1\fR (or \fB\-Wcatch\-value\fR for short) +warn about polymorphic class types that are caught by value. +With \fB\-Wcatch\-value=2\fR warn about all class types that are caught +by value. With \fB\-Wcatch\-value=3\fR warn about all types that are +not caught by reference. \fB\-Wcatch\-value\fR is enabled by \fB\-Wall\fR. +.IP "\fB\-Wclobbered\fR" 4 +.IX Item "-Wclobbered" +Warn for variables that might be changed by \f(CW\*(C`longjmp\*(C'\fR or +\&\f(CW\*(C`vfork\*(C'\fR. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wconditionally\-supported\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wconditionally-supported ( and Objective- only)" +Warn for conditionally-supported (\*(C+11 [intro.defs]) constructs. +.IP "\fB\-Wconversion\fR" 4 +.IX Item "-Wconversion" +Warn for implicit conversions that may alter a value. This includes +conversions between real and integer, like \f(CW\*(C`abs (x)\*(C'\fR when +\&\f(CW\*(C`x\*(C'\fR is \f(CW\*(C`double\*(C'\fR; conversions between signed and unsigned, +like \f(CW\*(C`unsigned ui = \-1\*(C'\fR; and conversions to smaller types, like +\&\f(CW\*(C`sqrtf (M_PI)\*(C'\fR. Do not warn for explicit casts like \f(CW\*(C`abs +((int) x)\*(C'\fR and \f(CW\*(C`ui = (unsigned) \-1\*(C'\fR, or if the value is not +changed by the conversion like in \f(CW\*(C`abs (2.0)\*(C'\fR. Warnings about +conversions between signed and unsigned integers can be disabled by +using \fB\-Wno\-sign\-conversion\fR. +.Sp +For \*(C+, also warn for confusing overload resolution for user-defined +conversions; and conversions that never use a type conversion +operator: conversions to \f(CW\*(C`void\*(C'\fR, the same type, a base class or a +reference to them. Warnings about conversions between signed and +unsigned integers are disabled by default in \*(C+ unless +\&\fB\-Wsign\-conversion\fR is explicitly enabled. +.IP "\fB\-Wno\-conversion\-null\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-conversion-null ( and Objective- only)" +Do not warn for conversions between \f(CW\*(C`NULL\*(C'\fR and non-pointer +types. \fB\-Wconversion\-null\fR is enabled by default. +.IP "\fB\-Wzero\-as\-null\-pointer\-constant\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wzero-as-null-pointer-constant ( and Objective- only)" +Warn when a literal \fB0\fR is used as null pointer constant. This can +be useful to facilitate the conversion to \f(CW\*(C`nullptr\*(C'\fR in \*(C+11. +.IP "\fB\-Wsubobject\-linkage\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsubobject-linkage ( and Objective- only)" +Warn if a class type has a base or a field whose type uses the anonymous +namespace or depends on a type with no linkage. If a type A depends on +a type B with no or internal linkage, defining it in multiple +translation units would be an \s-1ODR\s0 violation because the meaning of B +is different in each translation unit. If A only appears in a single +translation unit, the best way to silence the warning is to give it +internal linkage by putting it in an anonymous namespace as well. The +compiler doesn't give this warning for types defined in the main .C +file, as those are unlikely to have multiple definitions. +\&\fB\-Wsubobject\-linkage\fR is enabled by default. +.IP "\fB\-Wdangling\-else\fR" 4 +.IX Item "-Wdangling-else" +Warn about constructions where there may be confusion to which +\&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs. Here is an example of +such a case: +.Sp +.Vb 7 +\& { +\& if (a) +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +.Ve +.Sp +In C/\*(C+, every \f(CW\*(C`else\*(C'\fR branch belongs to the innermost possible +\&\f(CW\*(C`if\*(C'\fR statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR. This is +often not what the programmer expected, as illustrated in the above +example by indentation the programmer chose. When there is the +potential for this confusion, \s-1GCC\s0 issues a warning when this flag +is specified. To eliminate the warning, add explicit braces around +the innermost \f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR +can belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code +looks like this: +.Sp +.Vb 9 +\& { +\& if (a) +\& { +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +\& } +.Ve +.Sp +This warning is enabled by \fB\-Wparentheses\fR. +.IP "\fB\-Wdate\-time\fR" 4 +.IX Item "-Wdate-time" +Warn when macros \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, \f(CW\*(C`_\|_DATE_\|_\*(C'\fR or \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR +are encountered as they might prevent bit-wise-identical reproducible +compilations. +.IP "\fB\-Wdelete\-incomplete\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wdelete-incomplete ( and Objective- only)" +Warn when deleting a pointer to incomplete type, which may cause +undefined behavior at runtime. This warning is enabled by default. +.IP "\fB\-Wuseless\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wuseless-cast ( and Objective- only)" +Warn when an expression is casted to its own type. +.IP "\fB\-Wempty\-body\fR" 4 +.IX Item "-Wempty-body" +Warn if an empty body occurs in an \f(CW\*(C`if\*(C'\fR, \f(CW\*(C`else\*(C'\fR or \f(CW\*(C`do +while\*(C'\fR statement. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wenum\-compare\fR" 4 +.IX Item "-Wenum-compare" +Warn about a comparison between values of different enumerated types. +In \*(C+ enumerated type mismatches in conditional expressions are also +diagnosed and the warning is enabled by default. In C this warning is +enabled by \fB\-Wall\fR. +.IP "\fB\-Wextra\-semi\fR (\*(C+, Objective\-\*(C+ only)" 4 +.IX Item "-Wextra-semi (, Objective- only)" +Warn about redundant semicolon after in-class function definition. +.IP "\fB\-Wjump\-misses\-init\fR (C, Objective-C only)" 4 +.IX Item "-Wjump-misses-init (C, Objective-C only)" +Warn if a \f(CW\*(C`goto\*(C'\fR statement or a \f(CW\*(C`switch\*(C'\fR statement jumps +forward across the initialization of a variable, or jumps backward to a +label after the variable has been initialized. This only warns about +variables that are initialized when they are declared. This warning is +only supported for C and Objective-C; in \*(C+ this sort of branch is an +error in any case. +.Sp +\&\fB\-Wjump\-misses\-init\fR is included in \fB\-Wc++\-compat\fR. It +can be disabled with the \fB\-Wno\-jump\-misses\-init\fR option. +.IP "\fB\-Wsign\-compare\fR" 4 +.IX Item "-Wsign-compare" +Warn when a comparison between signed and unsigned values could produce +an incorrect result when the signed value is converted to unsigned. +In \*(C+, this warning is also enabled by \fB\-Wall\fR. In C, it is +also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wsign\-conversion\fR" 4 +.IX Item "-Wsign-conversion" +Warn for implicit conversions that may change the sign of an integer +value, like assigning a signed integer expression to an unsigned +integer variable. An explicit cast silences the warning. In C, this +option is enabled also by \fB\-Wconversion\fR. +.IP "\fB\-Wfloat\-conversion\fR" 4 +.IX Item "-Wfloat-conversion" +Warn for implicit conversions that reduce the precision of a real value. +This includes conversions from real to integer, and from higher precision +real to lower precision real values. This option is also enabled by +\&\fB\-Wconversion\fR. +.IP "\fB\-Wno\-scalar\-storage\-order\fR" 4 +.IX Item "-Wno-scalar-storage-order" +Do not warn on suspicious constructs involving reverse scalar storage order. +.IP "\fB\-Wsized\-deallocation\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsized-deallocation ( and Objective- only)" +Warn about a definition of an unsized deallocation function +.Sp +.Vb 2 +\& void operator delete (void *) noexcept; +\& void operator delete[] (void *) noexcept; +.Ve +.Sp +without a definition of the corresponding sized deallocation function +.Sp +.Vb 2 +\& void operator delete (void *, std::size_t) noexcept; +\& void operator delete[] (void *, std::size_t) noexcept; +.Ve +.Sp +or vice versa. Enabled by \fB\-Wextra\fR along with +\&\fB\-fsized\-deallocation\fR. +.IP "\fB\-Wsizeof\-pointer\-div\fR" 4 +.IX Item "-Wsizeof-pointer-div" +Warn for suspicious divisions of two sizeof expressions that divide +the pointer size by the element size, which is the usual way to compute +the array size but won't work out correctly with pointers. This warning +warns e.g. about \f(CW\*(C`sizeof (ptr) / sizeof (ptr[0])\*(C'\fR if \f(CW\*(C`ptr\*(C'\fR is +not an array, but a pointer. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsizeof\-pointer\-memaccess\fR" 4 +.IX Item "-Wsizeof-pointer-memaccess" +Warn for suspicious length parameters to certain string and memory built-in +functions if the argument uses \f(CW\*(C`sizeof\*(C'\fR. This warning triggers for +example for \f(CW\*(C`memset (ptr, 0, sizeof (ptr));\*(C'\fR if \f(CW\*(C`ptr\*(C'\fR is not +an array, but a pointer, and suggests a possible fix, or about +\&\f(CW\*(C`memcpy (&foo, ptr, sizeof (&foo));\*(C'\fR. \fB\-Wsizeof\-pointer\-memaccess\fR +also warns about calls to bounded string copy functions like \f(CW\*(C`strncat\*(C'\fR +or \f(CW\*(C`strncpy\*(C'\fR that specify as the bound a \f(CW\*(C`sizeof\*(C'\fR expression of +the source array. For example, in the following function the call to +\&\f(CW\*(C`strncat\*(C'\fR specifies the size of the source string as the bound. That +is almost certainly a mistake and so the call is diagnosed. +.Sp +.Vb 7 +\& void make_file (const char *name) +\& { +\& char path[PATH_MAX]; +\& strncpy (path, name, sizeof path \- 1); +\& strncat (path, ".text", sizeof ".text"); +\& ... +\& } +.Ve +.Sp +The \fB\-Wsizeof\-pointer\-memaccess\fR option is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsizeof\-array\-argument\fR" 4 +.IX Item "-Wsizeof-array-argument" +Warn when the \f(CW\*(C`sizeof\*(C'\fR operator is applied to a parameter that is +declared as an array in a function definition. This warning is enabled by +default for C and \*(C+ programs. +.IP "\fB\-Wmemset\-elt\-size\fR" 4 +.IX Item "-Wmemset-elt-size" +Warn for suspicious calls to the \f(CW\*(C`memset\*(C'\fR built-in function, if the +first argument references an array, and the third argument is a number +equal to the number of elements, but not equal to the size of the array +in memory. This indicates that the user has omitted a multiplication by +the element size. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wmemset\-transposed\-args\fR" 4 +.IX Item "-Wmemset-transposed-args" +Warn for suspicious calls to the \f(CW\*(C`memset\*(C'\fR built-in function where +the second argument is not zero and the third argument is zero. For +example, the call \f(CW\*(C`memset (buf, sizeof buf, 0)\*(C'\fR is diagnosed because +\&\f(CW\*(C`memset (buf, 0, sizeof buf)\*(C'\fR was meant instead. The diagnostic +is only emitted if the third argument is a literal zero. Otherwise, if +it is an expression that is folded to zero, or a cast of zero to some +type, it is far less likely that the arguments have been mistakenly +transposed and no warning is emitted. This warning is enabled +by \fB\-Wall\fR. +.IP "\fB\-Waddress\fR" 4 +.IX Item "-Waddress" +Warn about suspicious uses of memory addresses. These include using +the address of a function in a conditional expression, such as +\&\f(CW\*(C`void func(void); if (func)\*(C'\fR, and comparisons against the memory +address of a string literal, such as \f(CW\*(C`if (x == "abc")\*(C'\fR. Such +uses typically indicate a programmer error: the address of a function +always evaluates to true, so their use in a conditional usually +indicate that the programmer forgot the parentheses in a function +call; and comparisons against string literals result in unspecified +behavior and are not portable in C, so they usually indicate that the +programmer intended to use \f(CW\*(C`strcmp\*(C'\fR. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Waddress\-of\-packed\-member\fR" 4 +.IX Item "-Waddress-of-packed-member" +Warn when the address of packed member of struct or union is taken, +which usually results in an unaligned pointer value. This is +enabled by default. +.IP "\fB\-Wlogical\-op\fR" 4 +.IX Item "-Wlogical-op" +Warn about suspicious uses of logical operators in expressions. +This includes using logical operators in contexts where a +bit-wise operator is likely to be expected. Also warns when +the operands of a logical operator are the same: +.Sp +.Vb 2 +\& extern int a; +\& if (a < 0 && a < 0) { ... } +.Ve +.IP "\fB\-Wlogical\-not\-parentheses\fR" 4 +.IX Item "-Wlogical-not-parentheses" +Warn about logical not used on the left hand side operand of a comparison. +This option does not warn if the right operand is considered to be a boolean +expression. Its purpose is to detect suspicious code like the following: +.Sp +.Vb 3 +\& int a; +\& ... +\& if (!a > 1) { ... } +.Ve +.Sp +It is possible to suppress the warning by wrapping the \s-1LHS\s0 into +parentheses: +.Sp +.Vb 1 +\& if ((!a) > 1) { ... } +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Waggregate\-return\fR" 4 +.IX Item "-Waggregate-return" +Warn if any functions that return structures or unions are defined or +called. (In languages where you can return an array, this also elicits +a warning.) +.IP "\fB\-Wno\-aggressive\-loop\-optimizations\fR" 4 +.IX Item "-Wno-aggressive-loop-optimizations" +Warn if in a loop with constant number of iterations the compiler detects +undefined behavior in some statement during one or more of the iterations. +.IP "\fB\-Wno\-attributes\fR" 4 +.IX Item "-Wno-attributes" +Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as +unrecognized attributes, function attributes applied to variables, +etc. This does not stop errors for incorrect use of supported +attributes. +.IP "\fB\-Wno\-builtin\-declaration\-mismatch\fR" 4 +.IX Item "-Wno-builtin-declaration-mismatch" +Warn if a built-in function is declared with an incompatible signature +or as a non-function, or when a built-in function declared with a type +that does not include a prototype is called with arguments whose promoted +types do not match those expected by the function. When \fB\-Wextra\fR +is specified, also warn when a built-in function that takes arguments is +declared without a prototype. The \fB\-Wno\-builtin\-declaration\-mismatch\fR +warning is enabled by default. To avoid the warning include the appropriate +header to bring the prototypes of built-in functions into scope. +.Sp +For example, the call to \f(CW\*(C`memset\*(C'\fR below is diagnosed by the warning +because the function expects a value of type \f(CW\*(C`size_t\*(C'\fR as its argument +but the type of \f(CW32\fR is \f(CW\*(C`int\*(C'\fR. With \fB\-Wextra\fR, +the declaration of the function is diagnosed as well. +.Sp +.Vb 5 +\& extern void* memset (); +\& void f (void *d) +\& { +\& memset (d, \*(Aq\e0\*(Aq, 32); +\& } +.Ve +.IP "\fB\-Wno\-builtin\-macro\-redefined\fR" 4 +.IX Item "-Wno-builtin-macro-redefined" +Do not warn if certain built-in macros are redefined. This suppresses +warnings for redefinition of \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR, \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_DATE_\|_\*(C'\fR, \f(CW\*(C`_\|_FILE_\|_\*(C'\fR, and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR. +.IP "\fB\-Wstrict\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wstrict-prototypes (C and Objective-C only)" +Warn if a function is declared or defined without specifying the +argument types. (An old-style function definition is permitted without +a warning if preceded by a declaration that specifies the argument +types.) +.IP "\fB\-Wold\-style\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-declaration (C and Objective-C only)" +Warn for obsolescent usages, according to the C Standard, in a +declaration. For example, warn if storage-class specifiers like +\&\f(CW\*(C`static\*(C'\fR are not the first things in a declaration. This warning +is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wold\-style\-definition\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-definition (C and Objective-C only)" +Warn if an old-style function definition is used. A warning is given +even if there is a previous prototype. +.IP "\fB\-Wmissing\-parameter\-type\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-parameter-type (C and Objective-C only)" +A function parameter is declared without a type specifier in K&R\-style +functions: +.Sp +.Vb 1 +\& void foo(bar) { } +.Ve +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wmissing\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-prototypes (C and Objective-C only)" +Warn if a global function is defined without a previous prototype +declaration. This warning is issued even if the definition itself +provides a prototype. Use this option to detect global functions +that do not have a matching prototype declaration in a header file. +This option is not valid for \*(C+ because all function declarations +provide prototypes and a non-matching declaration declares an +overload rather than conflict with an earlier declaration. +Use \fB\-Wmissing\-declarations\fR to detect missing declarations in \*(C+. +.IP "\fB\-Wmissing\-declarations\fR" 4 +.IX Item "-Wmissing-declarations" +Warn if a global function is defined without a previous declaration. +Do so even if the definition itself provides a prototype. +Use this option to detect global functions that are not declared in +header files. In C, no warnings are issued for functions with previous +non-prototype declarations; use \fB\-Wmissing\-prototypes\fR to detect +missing prototypes. In \*(C+, no warnings are issued for function templates, +or for inline functions, or for functions in anonymous namespaces. +.IP "\fB\-Wmissing\-field\-initializers\fR" 4 +.IX Item "-Wmissing-field-initializers" +Warn if a structure's initializer has some fields missing. For +example, the following code causes such a warning, because +\&\f(CW\*(C`x.h\*(C'\fR is implicitly zero: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { 3, 4 }; +.Ve +.Sp +This option does not warn about designated initializers, so the following +modification does not trigger a warning: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { .f = 3, .g = 4 }; +.Ve +.Sp +In C this option does not warn about the universal zero initializer +\&\fB{ 0 }\fR: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { 0 }; +.Ve +.Sp +Likewise, in \*(C+ this option does not warn about the empty { } +initializer, for example: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& s x = { }; +.Ve +.Sp +This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR +warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR. +.IP "\fB\-Wno\-multichar\fR" 4 +.IX Item "-Wno-multichar" +Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used. +Usually they indicate a typo in the user's code, as they have +implementation-defined values, and should not be used in portable code. +.IP "\fB\-Wnormalized=\fR[\fBnone\fR|\fBid\fR|\fBnfc\fR|\fBnfkc\fR]" 4 +.IX Item "-Wnormalized=[none|id|nfc|nfkc]" +In \s-1ISO C\s0 and \s-1ISO \*(C+,\s0 two identifiers are different if they are +different sequences of characters. However, sometimes when characters +outside the basic \s-1ASCII\s0 character set are used, you can have two +different character sequences that look the same. To avoid confusion, +the \s-1ISO 10646\s0 standard sets out some \fInormalization rules\fR which +when applied ensure that two sequences that look the same are turned into +the same sequence. \s-1GCC\s0 can warn you if you are using identifiers that +have not been normalized; this option controls that warning. +.Sp +There are four levels of warning supported by \s-1GCC.\s0 The default is +\&\fB\-Wnormalized=nfc\fR, which warns about any identifier that is +not in the \s-1ISO 10646 \*(L"C\*(R"\s0 normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the +recommended form for most uses. It is equivalent to +\&\fB\-Wnormalized\fR. +.Sp +Unfortunately, there are some characters allowed in identifiers by +\&\s-1ISO C\s0 and \s-1ISO \*(C+\s0 that, when turned into \s-1NFC,\s0 are not allowed in +identifiers. That is, there's no way to use these symbols in portable +\&\s-1ISO C\s0 or \*(C+ and have all your identifiers in \s-1NFC.\s0 +\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. +It is hoped that future versions of the standards involved will correct +this, which is why this option is not the default. +.Sp +You can switch the warning off for all characters by writing +\&\fB\-Wnormalized=none\fR or \fB\-Wno\-normalized\fR. You should +only do this if you are using some other normalization scheme (like +\&\*(L"D\*(R"), because otherwise you can easily create bugs that are +literally impossible to see. +.Sp +Some characters in \s-1ISO 10646\s0 have distinct meanings but look identical +in some fonts or display methodologies, especially once formatting has +been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT LATIN SMALL +LETTER N\*(R",\s0 displays just like a regular \f(CW\*(C`n\*(C'\fR that has been +placed in a superscript. \s-1ISO 10646\s0 defines the \fI\s-1NFKC\s0\fR +normalization scheme to convert all these into a standard form as +well, and \s-1GCC\s0 warns if your code is not in \s-1NFKC\s0 if you use +\&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning +about every identifier that contains the letter O because it might be +confused with the digit 0, and so is not the default, but may be +useful as a local coding convention if the programming environment +cannot be fixed to display these characters distinctly. +.IP "\fB\-Wno\-attribute\-warning\fR" 4 +.IX Item "-Wno-attribute-warning" +Do not warn about usage of functions +declared with \f(CW\*(C`warning\*(C'\fR attribute. By default, this warning is +enabled. \fB\-Wno\-attribute\-warning\fR can be used to disable the +warning or \fB\-Wno\-error=attribute\-warning\fR can be used to +disable the error when compiled with \fB\-Werror\fR flag. +.IP "\fB\-Wno\-deprecated\fR" 4 +.IX Item "-Wno-deprecated" +Do not warn about usage of deprecated features. +.IP "\fB\-Wno\-deprecated\-declarations\fR" 4 +.IX Item "-Wno-deprecated-declarations" +Do not warn about uses of functions, +variables, and types marked as deprecated by using the \f(CW\*(C`deprecated\*(C'\fR +attribute. +.IP "\fB\-Wno\-overflow\fR" 4 +.IX Item "-Wno-overflow" +Do not warn about compile-time overflow in constant expressions. +.IP "\fB\-Wno\-odr\fR" 4 +.IX Item "-Wno-odr" +Warn about One Definition Rule violations during link-time optimization. +Requires \fB\-flto\-odr\-type\-merging\fR to be enabled. Enabled by default. +.IP "\fB\-Wopenmp\-simd\fR" 4 +.IX Item "-Wopenmp-simd" +Warn if the vectorizer cost model overrides the OpenMP +simd directive set by user. The \fB\-fsimd\-cost\-model=unlimited\fR +option can be used to relax the cost model. +.IP "\fB\-Woverride\-init\fR (C and Objective-C only)" 4 +.IX Item "-Woverride-init (C and Objective-C only)" +Warn if an initialized field without side effects is overridden when +using designated initializers. +.Sp +This warning is included in \fB\-Wextra\fR. To get other +\&\fB\-Wextra\fR warnings without this one, use \fB\-Wextra +\&\-Wno\-override\-init\fR. +.IP "\fB\-Woverride\-init\-side\-effects\fR (C and Objective-C only)" 4 +.IX Item "-Woverride-init-side-effects (C and Objective-C only)" +Warn if an initialized field with side effects is overridden when +using designated initializers. This warning is enabled by default. +.IP "\fB\-Wpacked\fR" 4 +.IX Item "-Wpacked" +Warn if a structure is given the packed attribute, but the packed +attribute has no effect on the layout or size of the structure. +Such structures may be mis-aligned for little benefit. For +instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR +is misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself +have the packed attribute: +.Sp +.Vb 8 +\& struct foo { +\& int x; +\& char a, b, c, d; +\& } _\|_attribute_\|_((packed)); +\& struct bar { +\& char z; +\& struct foo f; +\& }; +.Ve +.IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 +.IX Item "-Wpacked-bitfield-compat" +The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute +on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC 4.4\s0 but +the change can lead to differences in the structure layout. \s-1GCC\s0 +informs you when the offset of such a field has changed in \s-1GCC 4.4.\s0 +For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR +and \f(CW\*(C`b\*(C'\fR in this structure: +.Sp +.Vb 5 +\& struct foo +\& { +\& char a:4; +\& char b:8; +\& } _\|_attribute_\|_ ((packed)); +.Ve +.Sp +This warning is enabled by default. Use +\&\fB\-Wno\-packed\-bitfield\-compat\fR to disable this warning. +.IP "\fB\-Wpacked\-not\-aligned\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wpacked-not-aligned (C, , Objective-C and Objective- only)" +Warn if a structure field with explicitly specified alignment in a +packed struct or union is misaligned. For example, a warning will +be issued on \f(CW\*(C`struct S\*(C'\fR, like, \f(CW\*(C`warning: alignment 1 of +\&\*(Aqstruct S\*(Aq is less than 8\*(C'\fR, in this code: +.Sp +.Vb 4 +\& struct _\|_attribute_\|_ ((aligned (8))) S8 { char a[8]; }; +\& struct _\|_attribute_\|_ ((packed)) S { +\& struct S8 s8; +\& }; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wpadded\fR" 4 +.IX Item "-Wpadded" +Warn if padding is included in a structure, either to align an element +of the structure or to align the whole structure. Sometimes when this +happens it is possible to rearrange the fields of the structure to +reduce the padding and so make the structure smaller. +.IP "\fB\-Wredundant\-decls\fR" 4 +.IX Item "-Wredundant-decls" +Warn if anything is declared more than once in the same scope, even in +cases where multiple declaration is valid and changes nothing. +.IP "\fB\-Wno\-restrict\fR" 4 +.IX Item "-Wno-restrict" +Warn when an object referenced by a \f(CW\*(C`restrict\*(C'\fR\-qualified parameter +(or, in \*(C+, a \f(CW\*(C`_\|_restrict\*(C'\fR\-qualified parameter) is aliased by another +argument, or when copies between such objects overlap. For example, +the call to the \f(CW\*(C`strcpy\*(C'\fR function below attempts to truncate the string +by replacing its initial characters with the last four. However, because +the call writes the terminating \s-1NUL\s0 into \f(CW\*(C`a[4]\*(C'\fR, the copies overlap and +the call is diagnosed. +.Sp +.Vb 6 +\& void foo (void) +\& { +\& char a[] = "abcd1234"; +\& strcpy (a, a + 4); +\& ... +\& } +.Ve +.Sp +The \fB\-Wrestrict\fR option detects some instances of simple overlap +even without optimization but works best at \fB\-O2\fR and above. It +is included in \fB\-Wall\fR. +.IP "\fB\-Wnested\-externs\fR (C and Objective-C only)" 4 +.IX Item "-Wnested-externs (C and Objective-C only)" +Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function. +.IP "\fB\-Wno\-inherited\-variadic\-ctor\fR" 4 +.IX Item "-Wno-inherited-variadic-ctor" +Suppress warnings about use of \*(C+11 inheriting constructors when the +base class inherited from has a C variadic constructor; the warning is +on by default because the ellipsis is not inherited. +.IP "\fB\-Winline\fR" 4 +.IX Item "-Winline" +Warn if a function that is declared as inline cannot be inlined. +Even with this option, the compiler does not warn about failures to +inline functions declared in system headers. +.Sp +The compiler uses a variety of heuristics to determine whether or not +to inline a function. For example, the compiler takes into account +the size of the function being inlined and the amount of inlining +that has already been done in the current function. Therefore, +seemingly insignificant changes in the source program can cause the +warnings produced by \fB\-Winline\fR to appear or disappear. +.IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-invalid-offsetof ( and Objective- only)" +Suppress warnings from applying the \f(CW\*(C`offsetof\*(C'\fR macro to a non-POD +type. According to the 2014 \s-1ISO \*(C+\s0 standard, applying \f(CW\*(C`offsetof\*(C'\fR +to a non-standard-layout type is undefined. In existing \*(C+ implementations, +however, \f(CW\*(C`offsetof\*(C'\fR typically gives meaningful results. +This flag is for users who are aware that they are +writing nonportable code and who have deliberately chosen to ignore the +warning about it. +.Sp +The restrictions on \f(CW\*(C`offsetof\*(C'\fR may be relaxed in a future version +of the \*(C+ standard. +.IP "\fB\-Wint\-in\-bool\-context\fR" 4 +.IX Item "-Wint-in-bool-context" +Warn for suspicious use of integer values where boolean values are expected, +such as conditional expressions (?:) using non-boolean integer constants in +boolean context, like \f(CW\*(C`if (a <= b ? 2 : 3)\*(C'\fR. Or left shifting of signed +integers in boolean context, like \f(CW\*(C`for (a = 0; 1 << a; a++);\*(C'\fR. Likewise +for all kinds of multiplications regardless of the data type. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-int\-to\-pointer\-cast\fR" 4 +.IX Item "-Wno-int-to-pointer-cast" +Suppress warnings from casts to pointer type of an integer of a +different size. In \*(C+, casting to a pointer type of smaller size is +an error. \fBWint-to-pointer-cast\fR is enabled by default. +.IP "\fB\-Wno\-pointer\-to\-int\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wno-pointer-to-int-cast (C and Objective-C only)" +Suppress warnings from casts from a pointer to an integer type of a +different size. +.IP "\fB\-Winvalid\-pch\fR" 4 +.IX Item "-Winvalid-pch" +Warn if a precompiled header is found in +the search path but cannot be used. +.IP "\fB\-Wlong\-long\fR" 4 +.IX Item "-Wlong-long" +Warn if \f(CW\*(C`long long\*(C'\fR type is used. This is enabled by either +\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO C90\s0 and \*(C+98 +modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. +.IP "\fB\-Wvariadic\-macros\fR" 4 +.IX Item "-Wvariadic-macros" +Warn if variadic macros are used in \s-1ISO C90\s0 mode, or if the \s-1GNU\s0 +alternate syntax is used in \s-1ISO C99\s0 mode. This is enabled by either +\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR. To inhibit the warning +messages, use \fB\-Wno\-variadic\-macros\fR. +.IP "\fB\-Wvarargs\fR" 4 +.IX Item "-Wvarargs" +Warn upon questionable usage of the macros used to handle variable +arguments like \f(CW\*(C`va_start\*(C'\fR. This is default. To inhibit the +warning messages, use \fB\-Wno\-varargs\fR. +.IP "\fB\-Wvector\-operation\-performance\fR" 4 +.IX Item "-Wvector-operation-performance" +Warn if vector operation is not implemented via \s-1SIMD\s0 capabilities of the +architecture. Mainly useful for the performance tuning. +Vector operation can be implemented \f(CW\*(C`piecewise\*(C'\fR, which means that the +scalar operation is performed on every vector element; +\&\f(CW\*(C`in parallel\*(C'\fR, which means that the vector operation is implemented +using scalars of wider type, which normally is more performance efficient; +and \f(CW\*(C`as a single scalar\*(C'\fR, which means that vector fits into a +scalar type. +.IP "\fB\-Wno\-virtual\-move\-assign\fR" 4 +.IX Item "-Wno-virtual-move-assign" +Suppress warnings about inheriting from a virtual base with a +non-trivial \*(C+11 move assignment operator. This is dangerous because +if the virtual base is reachable along more than one path, it is +moved multiple times, which can mean both objects end up in the +moved-from state. If the move assignment operator is written to avoid +moving from a moved-from object, this warning can be disabled. +.IP "\fB\-Wvla\fR" 4 +.IX Item "-Wvla" +Warn if a variable-length array is used in the code. +\&\fB\-Wno\-vla\fR prevents the \fB\-Wpedantic\fR warning of +the variable-length array. +.IP "\fB\-Wvla\-larger\-than=\fR\fIbyte-size\fR" 4 +.IX Item "-Wvla-larger-than=byte-size" +If this option is used, the compiler will warn for declarations of +variable-length arrays whose size is either unbounded, or bounded +by an argument that allows the array size to exceed \fIbyte-size\fR +bytes. This is similar to how \fB\-Walloca\-larger\-than=\fR\fIbyte-size\fR +works, but with variable-length arrays. +.Sp +Note that \s-1GCC\s0 may optimize small variable-length arrays of a known +value into plain arrays, so this warning may not get triggered for +such arrays. +.Sp +\&\fB\-Wvla\-larger\-than=\fR\fB\s-1PTRDIFF_MAX\s0\fR is enabled by default but +is typically only effective when \fB\-ftree\-vrp\fR is active (default +for \fB\-O2\fR and above). +.Sp +See also \fB\-Walloca\-larger\-than=\fR\fIbyte-size\fR. +.IP "\fB\-Wno\-vla\-larger\-than\fR" 4 +.IX Item "-Wno-vla-larger-than" +Disable \fB\-Wvla\-larger\-than=\fR warnings. The option is equivalent +to \fB\-Wvla\-larger\-than=\fR\fB\s-1SIZE_MAX\s0\fR or larger. +.IP "\fB\-Wvolatile\-register\-var\fR" 4 +.IX Item "-Wvolatile-register-var" +Warn if a register variable is declared volatile. The volatile +modifier does not inhibit all optimizations that may eliminate reads +and/or writes to register variables. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wdisabled\-optimization\fR" 4 +.IX Item "-Wdisabled-optimization" +Warn if a requested optimization pass is disabled. This warning does +not generally indicate that there is anything wrong with your code; it +merely indicates that \s-1GCC\s0's optimizers are unable to handle the code +effectively. Often, the problem is that your code is too big or too +complex; \s-1GCC\s0 refuses to optimize programs when the optimization +itself is likely to take inordinate amounts of time. +.IP "\fB\-Wpointer\-sign\fR (C and Objective-C only)" 4 +.IX Item "-Wpointer-sign (C and Objective-C only)" +Warn for pointer argument passing or assignment with different signedness. +This option is only supported for C and Objective-C. It is implied by +\&\fB\-Wall\fR and by \fB\-Wpedantic\fR, which can be disabled with +\&\fB\-Wno\-pointer\-sign\fR. +.IP "\fB\-Wstack\-protector\fR" 4 +.IX Item "-Wstack-protector" +This option is only active when \fB\-fstack\-protector\fR is active. It +warns about functions that are not protected against stack smashing. +.IP "\fB\-Woverlength\-strings\fR" 4 +.IX Item "-Woverlength-strings" +Warn about string constants that are longer than the \*(L"minimum +maximum\*(R" length specified in the C standard. Modern compilers +generally allow string constants that are much longer than the +standard's minimum limit, but very portable programs should avoid +using longer strings. +.Sp +The limit applies \fIafter\fR string constant concatenation, and does +not count the trailing \s-1NUL.\s0 In C90, the limit was 509 characters; in +C99, it was raised to 4095. \*(C+98 does not specify a normative +minimum maximum, so we do not diagnose overlength strings in \*(C+. +.Sp +This option is implied by \fB\-Wpedantic\fR, and can be disabled with +\&\fB\-Wno\-overlength\-strings\fR. +.IP "\fB\-Wunsuffixed\-float\-constants\fR (C and Objective-C only)" 4 +.IX Item "-Wunsuffixed-float-constants (C and Objective-C only)" +Issue a warning for any floating constant that does not have +a suffix. When used together with \fB\-Wsystem\-headers\fR it +warns about such constants in system header files. This can be useful +when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma +from the decimal floating-point extension to C99. +.IP "\fB\-Wno\-designated\-init\fR (C and Objective-C only)" 4 +.IX Item "-Wno-designated-init (C and Objective-C only)" +Suppress warnings when a positional initializer is used to initialize +a structure that has been marked with the \f(CW\*(C`designated_init\*(C'\fR +attribute. +.IP "\fB\-Whsa\fR" 4 +.IX Item "-Whsa" +Issue a warning when \s-1HSAIL\s0 cannot be emitted for the compiled function or +OpenMP construct. +.SS "Options for Debugging Your Program" +.IX Subsection "Options for Debugging Your Program" +To tell \s-1GCC\s0 to emit extra information for use by a debugger, in almost +all cases you need only to add \fB\-g\fR to your other options. +.PP +\&\s-1GCC\s0 allows you to use \fB\-g\fR with +\&\fB\-O\fR. The shortcuts taken by optimized code may occasionally +be surprising: some variables you declared may not exist +at all; flow of control may briefly move where you did not expect it; +some statements may not be executed because they compute constant +results or their values are already at hand; some statements may +execute in different places because they have been moved out of loops. +Nevertheless it is possible to debug optimized output. This makes +it reasonable to use the optimizer for programs that might have bugs. +.PP +If you are not using some other optimization option, consider +using \fB\-Og\fR with \fB\-g\fR. +With no \fB\-O\fR option at all, some compiler passes that collect +information useful for debugging do not run at all, so that +\&\fB\-Og\fR may result in a better debugging experience. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +Produce debugging information in the operating system's native format +(stabs, \s-1COFF, XCOFF,\s0 or \s-1DWARF\s0). \s-1GDB\s0 can work with this debugging +information. +.Sp +On most systems that use stabs format, \fB\-g\fR enables use of extra +debugging information that only \s-1GDB\s0 can use; this extra information +makes debugging work better in \s-1GDB\s0 but probably makes other debuggers +crash or +refuse to read the program. If you want to control for certain whether +to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR, +\&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below). +.IP "\fB\-ggdb\fR" 4 +.IX Item "-ggdb" +Produce debugging information for use by \s-1GDB.\s0 This means to use the +most expressive format available (\s-1DWARF,\s0 stabs, or the native format +if neither of those are supported), including \s-1GDB\s0 extensions if at all +possible. +.IP "\fB\-gdwarf\fR" 4 +.IX Item "-gdwarf" +.PD 0 +.IP "\fB\-gdwarf\-\fR\fIversion\fR" 4 +.IX Item "-gdwarf-version" +.PD +Produce debugging information in \s-1DWARF\s0 format (if that is supported). +The value of \fIversion\fR may be either 2, 3, 4 or 5; the default version +for most targets is 4. \s-1DWARF\s0 Version 5 is only experimental. +.Sp +Note that with \s-1DWARF\s0 Version 2, some ports require and always +use some non-conflicting \s-1DWARF 3\s0 extensions in the unwind tables. +.Sp +Version 4 may require \s-1GDB 7.0\s0 and \fB\-fvar\-tracking\-assignments\fR +for maximum benefit. +.Sp +\&\s-1GCC\s0 no longer supports \s-1DWARF\s0 Version 1, which is substantially +different than Version 2 and later. For historical reasons, some +other DWARF-related options such as +\&\fB\-fno\-dwarf2\-cfi\-asm\fR) retain a reference to \s-1DWARF\s0 Version 2 +in their names, but apply to all currently-supported versions of \s-1DWARF.\s0 +.IP "\fB\-gstabs\fR" 4 +.IX Item "-gstabs" +Produce debugging information in stabs format (if that is supported), +without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 +systems. On \s-1MIPS,\s0 Alpha and System V Release 4 systems this option +produces stabs debugging output that is not understood by \s-1DBX.\s0 +On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. +.IP "\fB\-gstabs+\fR" 4 +.IX Item "-gstabs+" +Produce debugging information in stabs format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program. +.IP "\fB\-gxcoff\fR" 4 +.IX Item "-gxcoff" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported). +This is the format used by the \s-1DBX\s0 debugger on \s-1IBM RS/6000\s0 systems. +.IP "\fB\-gxcoff+\fR" 4 +.IX Item "-gxcoff+" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program, and may cause assemblers other than the \s-1GNU\s0 +assembler (\s-1GAS\s0) to fail with an error. +.IP "\fB\-gvms\fR" 4 +.IX Item "-gvms" +Produce debugging information in Alpha/VMS debug format (if that is +supported). This is the format used by \s-1DEBUG\s0 on Alpha/VMS systems. +.IP "\fB\-g\fR\fIlevel\fR" 4 +.IX Item "-glevel" +.PD 0 +.IP "\fB\-ggdb\fR\fIlevel\fR" 4 +.IX Item "-ggdblevel" +.IP "\fB\-gstabs\fR\fIlevel\fR" 4 +.IX Item "-gstabslevel" +.IP "\fB\-gxcoff\fR\fIlevel\fR" 4 +.IX Item "-gxcofflevel" +.IP "\fB\-gvms\fR\fIlevel\fR" 4 +.IX Item "-gvmslevel" +.PD +Request debugging information and also use \fIlevel\fR to specify how +much information. The default level is 2. +.Sp +Level 0 produces no debug information at all. Thus, \fB\-g0\fR negates +\&\fB\-g\fR. +.Sp +Level 1 produces minimal information, enough for making backtraces in +parts of the program that you don't plan to debug. This includes +descriptions of functions and external variables, and line number +tables, but no information about local variables. +.Sp +Level 3 includes extra information, such as all the macro definitions +present in the program. Some debuggers support macro expansion when +you use \fB\-g3\fR. +.Sp +If you use multiple \fB\-g\fR options, with or without level numbers, +the last such option is the one that is effective. +.Sp +\&\fB\-gdwarf\fR does not accept a concatenated debug level, to avoid +confusion with \fB\-gdwarf\-\fR\fIlevel\fR. +Instead use an additional \fB\-g\fR\fIlevel\fR option to change the +debug level for \s-1DWARF.\s0 +.IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 +.IX Item "-feliminate-unused-debug-symbols" +Produce debugging information in stabs format (if that is supported), +for only symbols that are actually used. +.IP "\fB\-femit\-class\-debug\-always\fR" 4 +.IX Item "-femit-class-debug-always" +Instead of emitting debugging information for a \*(C+ class in only one +object file, emit it in all object files using the class. This option +should be used only with debuggers that are unable to handle the way \s-1GCC\s0 +normally emits debugging information for classes because using this +option increases the size of debugging information by as much as a +factor of two. +.IP "\fB\-fno\-merge\-debug\-strings\fR" 4 +.IX Item "-fno-merge-debug-strings" +Direct the linker to not merge together strings in the debugging +information that are identical in different object files. Merging is +not supported by all assemblers or linkers. Merging decreases the size +of the debug information in the output file at the cost of increasing +link processing time. Merging is enabled by default. +.IP "\fB\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fdebug-prefix-map=old=new" +When compiling files residing in directory \fI\fIold\fI\fR, record +debugging information describing them as if the files resided in +directory \fI\fInew\fI\fR instead. This can be used to replace a +build-time path with an install-time path in the debug info. It can +also be used to change an absolute path to a relative path by using +\&\fI.\fR for \fInew\fR. This can give more reproducible builds, which +are location independent, but may require an extra command to tell \s-1GDB\s0 +where to find the source files. See also \fB\-ffile\-prefix\-map\fR. +.IP "\fB\-fvar\-tracking\fR" 4 +.IX Item "-fvar-tracking" +Run variable tracking pass. It computes where variables are stored at each +position in code. Better debugging information is then generated +(if the debugging information format supports this information). +.Sp +It is enabled by default when compiling with optimization (\fB\-Os\fR, +\&\fB\-O\fR, \fB\-O2\fR, ...), debugging information (\fB\-g\fR) and +the debug info format supports it. +.IP "\fB\-fvar\-tracking\-assignments\fR" 4 +.IX Item "-fvar-tracking-assignments" +Annotate assignments to user variables early in the compilation and +attempt to carry the annotations over throughout the compilation all the +way to the end, in an attempt to improve debug information while +optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it. +.Sp +It can be enabled even if var-tracking is disabled, in which case +annotations are created and maintained, but discarded at the end. +By default, this flag is enabled together with \fB\-fvar\-tracking\fR, +except when selective scheduling is enabled. +.IP "\fB\-gsplit\-dwarf\fR" 4 +.IX Item "-gsplit-dwarf" +Separate as much \s-1DWARF\s0 debugging information as possible into a +separate output file with the extension \fI.dwo\fR. This option allows +the build system to avoid linking files with debug information. To +be useful, this option requires a debugger capable of reading \fI.dwo\fR +files. +.IP "\fB\-gdescribe\-dies\fR" 4 +.IX Item "-gdescribe-dies" +Add description attributes to some \s-1DWARF\s0 DIEs that have no name attribute, +such as artificial variables, external references and call site +parameter DIEs. +.IP "\fB\-gpubnames\fR" 4 +.IX Item "-gpubnames" +Generate \s-1DWARF\s0 \f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections. +.IP "\fB\-ggnu\-pubnames\fR" 4 +.IX Item "-ggnu-pubnames" +Generate \f(CW\*(C`.debug_pubnames\*(C'\fR and \f(CW\*(C`.debug_pubtypes\*(C'\fR sections in a format +suitable for conversion into a \s-1GDB\s0 index. This option is only useful +with a linker that can produce \s-1GDB\s0 index version 7. +.IP "\fB\-fdebug\-types\-section\fR" 4 +.IX Item "-fdebug-types-section" +When using \s-1DWARF\s0 Version 4 or higher, type DIEs can be put into +their own \f(CW\*(C`.debug_types\*(C'\fR section instead of making them part of the +\&\f(CW\*(C`.debug_info\*(C'\fR section. It is more efficient to put them in a separate +comdat section since the linker can then remove duplicates. +But not all \s-1DWARF\s0 consumers support \f(CW\*(C`.debug_types\*(C'\fR sections yet +and on some objects \f(CW\*(C`.debug_types\*(C'\fR produces larger instead of smaller +debugging information. +.IP "\fB\-grecord\-gcc\-switches\fR" 4 +.IX Item "-grecord-gcc-switches" +.PD 0 +.IP "\fB\-gno\-record\-gcc\-switches\fR" 4 +.IX Item "-gno-record-gcc-switches" +.PD +This switch causes the command-line options used to invoke the +compiler that may affect code generation to be appended to the +DW_AT_producer attribute in \s-1DWARF\s0 debugging information. The options +are concatenated with spaces separating them from each other and from +the compiler version. +It is enabled by default. +See also \fB\-frecord\-gcc\-switches\fR for another +way of storing compiler options into the object file. +.IP "\fB\-gstrict\-dwarf\fR" 4 +.IX Item "-gstrict-dwarf" +Disallow using extensions of later \s-1DWARF\s0 standard version than selected +with \fB\-gdwarf\-\fR\fIversion\fR. On most targets using non-conflicting +\&\s-1DWARF\s0 extensions from later standard versions is allowed. +.IP "\fB\-gno\-strict\-dwarf\fR" 4 +.IX Item "-gno-strict-dwarf" +Allow using extensions of later \s-1DWARF\s0 standard version than selected with +\&\fB\-gdwarf\-\fR\fIversion\fR. +.IP "\fB\-gas\-loc\-support\fR" 4 +.IX Item "-gas-loc-support" +Inform the compiler that the assembler supports \f(CW\*(C`.loc\*(C'\fR directives. +It may then use them for the assembler to generate \s-1DWARF2+\s0 line number +tables. +.Sp +This is generally desirable, because assembler-generated line-number +tables are a lot more compact than those the compiler can generate +itself. +.Sp +This option will be enabled by default if, at \s-1GCC\s0 configure time, the +assembler was found to support such directives. +.IP "\fB\-gno\-as\-loc\-support\fR" 4 +.IX Item "-gno-as-loc-support" +Force \s-1GCC\s0 to generate \s-1DWARF2+\s0 line number tables internally, if \s-1DWARF2+\s0 +line number tables are to be generated. +.IP "\fBgas-locview-support\fR" 4 +.IX Item "gas-locview-support" +Inform the compiler that the assembler supports \f(CW\*(C`view\*(C'\fR assignment +and reset assertion checking in \f(CW\*(C`.loc\*(C'\fR directives. +.Sp +This option will be enabled by default if, at \s-1GCC\s0 configure time, the +assembler was found to support them. +.IP "\fBgno-as-locview-support\fR" 4 +.IX Item "gno-as-locview-support" +Force \s-1GCC\s0 to assign view numbers internally, if +\&\fB\-gvariable\-location\-views\fR are explicitly requested. +.IP "\fB\-gcolumn\-info\fR" 4 +.IX Item "-gcolumn-info" +.PD 0 +.IP "\fB\-gno\-column\-info\fR" 4 +.IX Item "-gno-column-info" +.PD +Emit location column information into \s-1DWARF\s0 debugging information, rather +than just file and line. +This option is enabled by default. +.IP "\fB\-gstatement\-frontiers\fR" 4 +.IX Item "-gstatement-frontiers" +.PD 0 +.IP "\fB\-gno\-statement\-frontiers\fR" 4 +.IX Item "-gno-statement-frontiers" +.PD +This option causes \s-1GCC\s0 to create markers in the internal representation +at the beginning of statements, and to keep them roughly in place +throughout compilation, using them to guide the output of \f(CW\*(C`is_stmt\*(C'\fR +markers in the line number table. This is enabled by default when +compiling with optimization (\fB\-Os\fR, \fB\-O\fR, \fB\-O2\fR, +\&...), and outputting \s-1DWARF 2\s0 debug information at the normal level. +.IP "\fB\-gvariable\-location\-views\fR" 4 +.IX Item "-gvariable-location-views" +.PD 0 +.IP "\fB\-gvariable\-location\-views=incompat5\fR" 4 +.IX Item "-gvariable-location-views=incompat5" +.IP "\fB\-gno\-variable\-location\-views\fR" 4 +.IX Item "-gno-variable-location-views" +.PD +Augment variable location lists with progressive view numbers implied +from the line number table. This enables debug information consumers to +inspect state at certain points of the program, even if no instructions +associated with the corresponding source locations are present at that +point. If the assembler lacks support for view numbers in line number +tables, this will cause the compiler to emit the line number table, +which generally makes them somewhat less compact. The augmented line +number tables and location lists are fully backward-compatible, so they +can be consumed by debug information consumers that are not aware of +these augmentations, but they won't derive any benefit from them either. +.Sp +This is enabled by default when outputting \s-1DWARF 2\s0 debug information at +the normal level, as long as there is assembler support, +\&\fB\-fvar\-tracking\-assignments\fR is enabled and +\&\fB\-gstrict\-dwarf\fR is not. When assembler support is not +available, this may still be enabled, but it will force \s-1GCC\s0 to output +internal line number tables, and if +\&\fB\-ginternal\-reset\-location\-views\fR is not enabled, that will most +certainly lead to silently mismatching location views. +.Sp +There is a proposed representation for view numbers that is not backward +compatible with the location list format introduced in \s-1DWARF 5,\s0 that can +be enabled with \fB\-gvariable\-location\-views=incompat5\fR. This +option may be removed in the future, is only provided as a reference +implementation of the proposed representation. Debug information +consumers are not expected to support this extended format, and they +would be rendered unable to decode location lists using it. +.IP "\fB\-ginternal\-reset\-location\-views\fR" 4 +.IX Item "-ginternal-reset-location-views" +.PD 0 +.IP "\fB\-gno\-internal\-reset\-location\-views\fR" 4 +.IX Item "-gno-internal-reset-location-views" +.PD +Attempt to determine location views that can be omitted from location +view lists. This requires the compiler to have very accurate insn +length estimates, which isn't always the case, and it may cause +incorrect view lists to be generated silently when using an assembler +that does not support location view lists. The \s-1GNU\s0 assembler will flag +any such error as a \f(CW\*(C`view number mismatch\*(C'\fR. This is only enabled +on ports that define a reliable estimation function. +.IP "\fB\-ginline\-points\fR" 4 +.IX Item "-ginline-points" +.PD 0 +.IP "\fB\-gno\-inline\-points\fR" 4 +.IX Item "-gno-inline-points" +.PD +Generate extended debug information for inlined functions. Location +view tracking markers are inserted at inlined entry points, so that +address and view numbers can be computed and output in debug +information. This can be enabled independently of location views, in +which case the view numbers won't be output, but it can only be enabled +along with statement frontiers, and it is only enabled by default if +location views are enabled. +.IP "\fB\-gz\fR[\fB=\fR\fItype\fR]" 4 +.IX Item "-gz[=type]" +Produce compressed debug sections in \s-1DWARF\s0 format, if that is supported. +If \fItype\fR is not given, the default type depends on the capabilities +of the assembler and linker used. \fItype\fR may be one of +\&\fBnone\fR (don't compress debug sections), \fBzlib\fR (use zlib +compression in \s-1ELF\s0 gABI format), or \fBzlib-gnu\fR (use zlib +compression in traditional \s-1GNU\s0 format). If the linker doesn't support +writing compressed debug sections, the option is rejected. Otherwise, +if the assembler does not support them, \fB\-gz\fR is silently ignored +when producing object files. +.IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4 +.IX Item "-femit-struct-debug-baseonly" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the struct is defined. +.Sp +This option substantially reduces the size of debugging information, +but at significant potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-reduced\fR for a less aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 debug output. +.IP "\fB\-femit\-struct\-debug\-reduced\fR" 4 +.IX Item "-femit-struct-debug-reduced" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the type is defined, +unless the struct is a template or defined in a system header. +.Sp +This option significantly reduces the size of debugging information, +with some potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-baseonly\fR for a more aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 debug output. +.IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4 +.IX Item "-femit-struct-debug-detailed[=spec-list]" +Specify the struct-like types +for which the compiler generates debug information. +The intent is to reduce duplicate struct debug information +between different object files within the same program. +.Sp +This option is a detailed version of +\&\fB\-femit\-struct\-debug\-reduced\fR and \fB\-femit\-struct\-debug\-baseonly\fR, +which serves for most needs. +.Sp +A specification has the syntax[\fBdir:\fR|\fBind:\fR][\fBord:\fR|\fBgen:\fR](\fBany\fR|\fBsys\fR|\fBbase\fR|\fBnone\fR) +.Sp +The optional first word limits the specification to +structs that are used directly (\fBdir:\fR) or used indirectly (\fBind:\fR). +A struct type is used directly when it is the type of a variable, member. +Indirect uses arise through pointers to structs. +That is, when use of an incomplete struct is valid, the use is indirect. +An example is +\&\fBstruct one direct; struct two * indirect;\fR. +.Sp +The optional second word limits the specification to +ordinary structs (\fBord:\fR) or generic structs (\fBgen:\fR). +Generic structs are a bit complicated to explain. +For \*(C+, these are non-explicit specializations of template classes, +or non-template classes within the above. +Other programming languages have generics, +but \fB\-femit\-struct\-debug\-detailed\fR does not yet implement them. +.Sp +The third word specifies the source files for those +structs for which the compiler should emit debug information. +The values \fBnone\fR and \fBany\fR have the normal meaning. +The value \fBbase\fR means that +the base of name of the file in which the type declaration appears +must match the base of the name of the main compilation file. +In practice, this means that when compiling \fIfoo.c\fR, debug information +is generated for types declared in that file and \fIfoo.h\fR, +but not other header files. +The value \fBsys\fR means those types satisfying \fBbase\fR +or declared in system or compiler headers. +.Sp +You may need to experiment to determine the best settings for your application. +.Sp +The default is \fB\-femit\-struct\-debug\-detailed=all\fR. +.Sp +This option works only with \s-1DWARF\s0 debug output. +.IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 +.IX Item "-fno-dwarf2-cfi-asm" +Emit \s-1DWARF\s0 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section +instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. +.IP "\fB\-fno\-eliminate\-unused\-debug\-types\fR" 4 +.IX Item "-fno-eliminate-unused-debug-types" +Normally, when producing \s-1DWARF\s0 output, \s-1GCC\s0 avoids producing debug symbol +output for types that are nowhere used in the source file being compiled. +Sometimes it is useful to have \s-1GCC\s0 emit debugging +information for all types declared in a compilation +unit, regardless of whether or not they are actually used +in that compilation unit, for example +if, in the debugger, you want to cast a value to a type that is +not actually used in your program (but is declared). More often, +however, this results in a significant amount of wasted space. +.SS "Options That Control Optimization" +.IX Subsection "Options That Control Optimization" +These options control various sorts of optimizations. +.PP +Without any optimization option, the compiler's goal is to reduce the +cost of compilation and to make debugging produce the expected +results. Statements are independent: if you stop the program with a +breakpoint between statements, you can then assign a new value to any +variable or change the program counter to any other statement in the +function and get exactly the results you expect from the source +code. +.PP +Turning on optimization flags makes the compiler attempt to improve +the performance and/or code size at the expense of compilation time +and possibly the ability to debug the program. +.PP +The compiler performs optimization based on the knowledge it has of the +program. Compiling multiple files at once to a single output file mode allows +the compiler to use information gained from all of the files when compiling +each of them. +.PP +Not all optimizations are controlled directly by a flag. Only +optimizations that have a flag are listed in this section. +.PP +Most optimizations are completely disabled at \fB\-O0\fR or if an +\&\fB\-O\fR level is not set on the command line, even if individual +optimization flags are specified. Similarly, \fB\-Og\fR suppresses +many optimization passes. +.PP +Depending on the target and how \s-1GCC\s0 was configured, a slightly different +set of optimizations may be enabled at each \fB\-O\fR level than +those listed here. You can invoke \s-1GCC\s0 with \fB\-Q \-\-help=optimizers\fR +to find out the exact set of optimizations that are enabled at each level. +.IP "\fB\-O\fR" 4 +.IX Item "-O" +.PD 0 +.IP "\fB\-O1\fR" 4 +.IX Item "-O1" +.PD +Optimize. Optimizing compilation takes somewhat more time, and a lot +more memory for a large function. +.Sp +With \fB\-O\fR, the compiler tries to reduce code size and execution +time, without performing any optimizations that take a great deal of +compilation time. +.Sp +\&\fB\-O\fR turns on the following optimization flags: +.Sp +\&\fB\-fauto\-inc\-dec +\&\-fbranch\-count\-reg +\&\-fcombine\-stack\-adjustments +\&\-fcompare\-elim +\&\-fcprop\-registers +\&\-fdce +\&\-fdefer\-pop +\&\-fdelayed\-branch +\&\-fdse +\&\-fforward\-propagate +\&\-fguess\-branch\-probability +\&\-fif\-conversion +\&\-fif\-conversion2 +\&\-finline\-functions\-called\-once +\&\-fipa\-profile +\&\-fipa\-pure\-const +\&\-fipa\-reference +\&\-fipa\-reference\-addressable +\&\-fmerge\-constants +\&\-fmove\-loop\-invariants +\&\-fomit\-frame\-pointer +\&\-freorder\-blocks +\&\-fshrink\-wrap +\&\-fshrink\-wrap\-separate +\&\-fsplit\-wide\-types +\&\-fssa\-backprop +\&\-fssa\-phiopt +\&\-ftree\-bit\-ccp +\&\-ftree\-ccp +\&\-ftree\-ch +\&\-ftree\-coalesce\-vars +\&\-ftree\-copy\-prop +\&\-ftree\-dce +\&\-ftree\-dominator\-opts +\&\-ftree\-dse +\&\-ftree\-forwprop +\&\-ftree\-fre +\&\-ftree\-phiprop +\&\-ftree\-pta +\&\-ftree\-scev\-cprop +\&\-ftree\-sink +\&\-ftree\-slsr +\&\-ftree\-sra +\&\-ftree\-ter +\&\-funit\-at\-a\-time\fR +.IP "\fB\-O2\fR" 4 +.IX Item "-O2" +Optimize even more. \s-1GCC\s0 performs nearly all supported optimizations +that do not involve a space-speed tradeoff. +As compared to \fB\-O\fR, this option increases both compilation time +and the performance of the generated code. +.Sp +\&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR. It +also turns on the following optimization flags: +.Sp +\&\fB\-falign\-functions \-falign\-jumps +\&\-falign\-labels \-falign\-loops +\&\-fcaller\-saves +\&\-fcode\-hoisting +\&\-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks +\&\-fdelete\-null\-pointer\-checks +\&\-fdevirtualize \-fdevirtualize\-speculatively +\&\-fexpensive\-optimizations +\&\-fgcse \-fgcse\-lm +\&\-fhoist\-adjacent\-loads +\&\-finline\-small\-functions +\&\-findirect\-inlining +\&\-fipa\-bit\-cp \-fipa\-cp \-fipa\-icf +\&\-fipa\-ra \-fipa\-sra \-fipa\-vrp +\&\-fisolate\-erroneous\-paths\-dereference +\&\-flra\-remat +\&\-foptimize\-sibling\-calls +\&\-foptimize\-strlen +\&\-fpartial\-inlining +\&\-fpeephole2 +\&\-freorder\-blocks\-algorithm=stc +\&\-freorder\-blocks\-and\-partition \-freorder\-functions +\&\-frerun\-cse\-after\-loop +\&\-fschedule\-insns \-fschedule\-insns2 +\&\-fsched\-interblock \-fsched\-spec +\&\-fstore\-merging +\&\-fstrict\-aliasing +\&\-fthread\-jumps +\&\-ftree\-builtin\-call\-dce +\&\-ftree\-pre +\&\-ftree\-switch\-conversion \-ftree\-tail\-merge +\&\-ftree\-vrp\fR +.Sp +Please note the warning under \fB\-fgcse\fR about +invoking \fB\-O2\fR on programs that use computed gotos. +.IP "\fB\-O3\fR" 4 +.IX Item "-O3" +Optimize yet more. \fB\-O3\fR turns on all optimizations specified +by \fB\-O2\fR and also turns on the following optimization flags: +.Sp +\&\fB\-fgcse\-after\-reload +\&\-finline\-functions +\&\-fipa\-cp\-clone +\&\-floop\-interchange +\&\-floop\-unroll\-and\-jam +\&\-fpeel\-loops +\&\-fpredictive\-commoning +\&\-fsplit\-paths +\&\-ftree\-loop\-distribute\-patterns +\&\-ftree\-loop\-distribution +\&\-ftree\-loop\-vectorize +\&\-ftree\-partial\-pre +\&\-ftree\-slp\-vectorize +\&\-funswitch\-loops +\&\-fvect\-cost\-model +\&\-fversion\-loops\-for\-strides\fR +.IP "\fB\-O0\fR" 4 +.IX Item "-O0" +Reduce compilation time and make debugging produce the expected +results. This is the default. +.IP "\fB\-Os\fR" 4 +.IX Item "-Os" +Optimize for size. \fB\-Os\fR enables all \fB\-O2\fR optimizations +except those that often increase code size: +.Sp +\&\fB\-falign\-functions \-falign\-jumps +\&\-falign\-labels \-falign\-loops +\&\-fprefetch\-loop\-arrays \-freorder\-blocks\-algorithm=stc\fR +.Sp +It also enables \fB\-finline\-functions\fR, causes the compiler to tune for +code size rather than execution speed, and performs further optimizations +designed to reduce code size. +.IP "\fB\-Ofast\fR" 4 +.IX Item "-Ofast" +Disregard strict standards compliance. \fB\-Ofast\fR enables all +\&\fB\-O3\fR optimizations. It also enables optimizations that are not +valid for all standard-compliant programs. +It turns on \fB\-ffast\-math\fR and the Fortran-specific +\&\fB\-fstack\-arrays\fR, unless \fB\-fmax\-stack\-var\-size\fR is +specified, and \fB\-fno\-protect\-parens\fR. +.IP "\fB\-Og\fR" 4 +.IX Item "-Og" +Optimize debugging experience. \fB\-Og\fR should be the optimization +level of choice for the standard edit-compile-debug cycle, offering +a reasonable level of optimization while maintaining fast compilation +and a good debugging experience. It is a better choice than \fB\-O0\fR +for producing debuggable code because some compiler passes +that collect debug information are disabled at \fB\-O0\fR. +.Sp +Like \fB\-O0\fR, \fB\-Og\fR completely disables a number of +optimization passes so that individual options controlling them have +no effect. Otherwise \fB\-Og\fR enables all \fB\-O1\fR +optimization flags except for those that may interfere with debugging: +.Sp +\&\fB\-fbranch\-count\-reg \-fdelayed\-branch +\&\-fif\-conversion \-fif\-conversion2 +\&\-finline\-functions\-called\-once +\&\-fmove\-loop\-invariants \-fssa\-phiopt +\&\-ftree\-bit\-ccp \-ftree\-pta \-ftree\-sra\fR +.PP +If you use multiple \fB\-O\fR options, with or without level numbers, +the last such option is the one that is effective. +.PP +Options of the form \fB\-f\fR\fIflag\fR specify machine-independent +flags. Most flags have both positive and negative forms; the negative +form of \fB\-ffoo\fR is \fB\-fno\-foo\fR. In the table +below, only one of the forms is listed\-\-\-the one you typically +use. You can figure out the other form by either removing \fBno\-\fR +or adding it. +.PP +The following options control specific optimizations. They are either +activated by \fB\-O\fR options or are related to ones that are. You +can use the following flags in the rare cases when \*(L"fine-tuning\*(R" of +optimizations to be performed is desired. +.IP "\fB\-fno\-defer\-pop\fR" 4 +.IX Item "-fno-defer-pop" +For machines that must pop arguments after a function call, always pop +the arguments as soon as each function returns. +At levels \fB\-O1\fR and higher, \fB\-fdefer\-pop\fR is the default; +this allows the compiler to let arguments accumulate on the stack for several +function calls and pop them all at once. +.IP "\fB\-fforward\-propagate\fR" 4 +.IX Item "-fforward-propagate" +Perform a forward propagation pass on \s-1RTL.\s0 The pass tries to combine two +instructions and checks if the result can be simplified. If loop unrolling +is active, two passes are performed and the second is scheduled after +loop unrolling. +.Sp +This option is enabled by default at optimization levels \fB\-O\fR, +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-ffp\-contract=\fR\fIstyle\fR" 4 +.IX Item "-ffp-contract=style" +\&\fB\-ffp\-contract=off\fR disables floating-point expression contraction. +\&\fB\-ffp\-contract=fast\fR enables floating-point expression contraction +such as forming of fused multiply-add operations if the target has +native support for them. +\&\fB\-ffp\-contract=on\fR enables floating-point expression contraction +if allowed by the language standard. This is currently not implemented +and treated equal to \fB\-ffp\-contract=off\fR. +.Sp +The default is \fB\-ffp\-contract=fast\fR. +.IP "\fB\-fomit\-frame\-pointer\fR" 4 +.IX Item "-fomit-frame-pointer" +Omit the frame pointer in functions that don't need one. This avoids the +instructions to save, set up and restore the frame pointer; on many targets +it also makes an extra register available. +.Sp +On some targets this flag has no effect because the standard calling sequence +always uses a frame pointer, so it cannot be omitted. +.Sp +Note that \fB\-fno\-omit\-frame\-pointer\fR doesn't guarantee the frame pointer +is used in all functions. Several targets always omit the frame pointer in +leaf functions. +.Sp +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-foptimize\-sibling\-calls\fR" 4 +.IX Item "-foptimize-sibling-calls" +Optimize sibling and tail recursive calls. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-foptimize\-strlen\fR" 4 +.IX Item "-foptimize-strlen" +Optimize various standard C string functions (e.g. \f(CW\*(C`strlen\*(C'\fR, +\&\f(CW\*(C`strchr\*(C'\fR or \f(CW\*(C`strcpy\*(C'\fR) and +their \f(CW\*(C`_FORTIFY_SOURCE\*(C'\fR counterparts into faster alternatives. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fno\-inline\fR" 4 +.IX Item "-fno-inline" +Do not expand any functions inline apart from those marked with +the \f(CW\*(C`always_inline\*(C'\fR attribute. This is the default when not +optimizing. +.Sp +Single functions can be exempted from inlining by marking them +with the \f(CW\*(C`noinline\*(C'\fR attribute. +.IP "\fB\-finline\-small\-functions\fR" 4 +.IX Item "-finline-small-functions" +Integrate functions into their callers when their body is smaller than expected +function call code (so overall size of program gets smaller). The compiler +heuristically decides which functions are simple enough to be worth integrating +in this way. This inlining applies to all functions, even those not declared +inline. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-findirect\-inlining\fR" 4 +.IX Item "-findirect-inlining" +Inline also indirect calls that are discovered to be known at compile +time thanks to previous inlining. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-finline\-functions\fR" 4 +.IX Item "-finline-functions" +Consider all functions for inlining, even if they are not declared inline. +The compiler heuristically decides which functions are worth integrating +in this way. +.Sp +If all calls to a given function are integrated, and the function is +declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as +assembler code in its own right. +.Sp +Enabled at levels \fB\-O3\fR, \fB\-Os\fR. Also enabled +by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-finline\-functions\-called\-once\fR" 4 +.IX Item "-finline-functions-called-once" +Consider all \f(CW\*(C`static\*(C'\fR functions called once for inlining into their +caller even if they are not marked \f(CW\*(C`inline\*(C'\fR. If a call to a given +function is integrated, then the function is not output as assembler code +in its own right. +.Sp +Enabled at levels \fB\-O1\fR, \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR, +but not \fB\-Og\fR. +.IP "\fB\-fearly\-inlining\fR" 4 +.IX Item "-fearly-inlining" +Inline functions marked by \f(CW\*(C`always_inline\*(C'\fR and functions whose body seems +smaller than the function call overhead early before doing +\&\fB\-fprofile\-generate\fR instrumentation and real inlining pass. Doing so +makes profiling significantly cheaper and usually inlining faster on programs +having large chains of nested wrapper functions. +.Sp +Enabled by default. +.IP "\fB\-fipa\-sra\fR" 4 +.IX Item "-fipa-sra" +Perform interprocedural scalar replacement of aggregates, removal of +unused parameters and replacement of parameters passed by reference +by parameters passed by value. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. +.IP "\fB\-finline\-limit=\fR\fIn\fR" 4 +.IX Item "-finline-limit=n" +By default, \s-1GCC\s0 limits the size of functions that can be inlined. This flag +allows coarse control of this limit. \fIn\fR is the size of functions that +can be inlined in number of pseudo instructions. +.Sp +Inlining is actually controlled by a number of parameters, which may be +specified individually by using \fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR. +The \fB\-finline\-limit=\fR\fIn\fR option sets some of these parameters +as follows: +.RS 4 +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +is set to \fIn\fR/2. +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +is set to \fIn\fR/2. +.RE +.RS 4 +.Sp +See below for a documentation of the individual +parameters controlling inlining and for the defaults of these parameters. +.Sp +\&\fINote:\fR there may be no value to \fB\-finline\-limit\fR that results +in default behavior. +.Sp +\&\fINote:\fR pseudo instruction represents, in this particular context, an +abstract measurement of function's size. In no way does it represent a count +of assembly instructions and as such its exact meaning might change from one +release to an another. +.RE +.IP "\fB\-fno\-keep\-inline\-dllexport\fR" 4 +.IX Item "-fno-keep-inline-dllexport" +This is a more fine-grained version of \fB\-fkeep\-inline\-functions\fR, +which applies only to functions that are declared using the \f(CW\*(C`dllexport\*(C'\fR +attribute or declspec. +.IP "\fB\-fkeep\-inline\-functions\fR" 4 +.IX Item "-fkeep-inline-functions" +In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR +into the object file, even if the function has been inlined into all +of its callers. This switch does not affect functions using the +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU C90.\s0 In \*(C+, emit any and all +inline functions into the object file. +.IP "\fB\-fkeep\-static\-functions\fR" 4 +.IX Item "-fkeep-static-functions" +Emit \f(CW\*(C`static\*(C'\fR functions into the object file, even if the function +is never used. +.IP "\fB\-fkeep\-static\-consts\fR" 4 +.IX Item "-fkeep-static-consts" +Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned +on, even if the variables aren't referenced. +.Sp +\&\s-1GCC\s0 enables this option by default. If you want to force the compiler to +check if a variable is referenced, regardless of whether or not +optimization is turned on, use the \fB\-fno\-keep\-static\-consts\fR option. +.IP "\fB\-fmerge\-constants\fR" 4 +.IX Item "-fmerge-constants" +Attempt to merge identical constants (string constants and floating-point +constants) across compilation units. +.Sp +This option is the default for optimized compilation if the assembler and +linker support it. Use \fB\-fno\-merge\-constants\fR to inhibit this +behavior. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fmerge\-all\-constants\fR" 4 +.IX Item "-fmerge-all-constants" +Attempt to merge identical constants and identical variables. +.Sp +This option implies \fB\-fmerge\-constants\fR. In addition to +\&\fB\-fmerge\-constants\fR this considers e.g. even constant initialized +arrays or initialized constant variables with integral or floating-point +types. Languages like C or \*(C+ require each variable, including multiple +instances of the same variable in recursive calls, to have distinct locations, +so using this option results in non-conforming +behavior. +.IP "\fB\-fmodulo\-sched\fR" 4 +.IX Item "-fmodulo-sched" +Perform swing modulo scheduling immediately before the first scheduling +pass. This pass looks at innermost loops and reorders their +instructions by overlapping different iterations. +.IP "\fB\-fmodulo\-sched\-allow\-regmoves\fR" 4 +.IX Item "-fmodulo-sched-allow-regmoves" +Perform more aggressive SMS-based modulo scheduling with register moves +allowed. By setting this flag certain anti-dependences edges are +deleted, which triggers the generation of reg-moves based on the +life-range analysis. This option is effective only with +\&\fB\-fmodulo\-sched\fR enabled. +.IP "\fB\-fno\-branch\-count\-reg\fR" 4 +.IX Item "-fno-branch-count-reg" +Disable the optimization pass that scans for opportunities to use +\&\*(L"decrement and branch\*(R" instructions on a count register instead of +instruction sequences that decrement a register, compare it against zero, and +then branch based upon the result. This option is only meaningful on +architectures that support such instructions, which include x86, PowerPC, +\&\s-1IA\-64\s0 and S/390. Note that the \fB\-fno\-branch\-count\-reg\fR option +doesn't remove the decrement and branch instructions from the generated +instruction stream introduced by other optimization passes. +.Sp +The default is \fB\-fbranch\-count\-reg\fR at \fB\-O1\fR and higher, +except for \fB\-Og\fR. +.IP "\fB\-fno\-function\-cse\fR" 4 +.IX Item "-fno-function-cse" +Do not put function addresses in registers; make each instruction that +calls a constant function contain the function's address explicitly. +.Sp +This option results in less efficient code, but some strange hacks +that alter the assembler output may be confused by the optimizations +performed when this option is not used. +.Sp +The default is \fB\-ffunction\-cse\fR +.IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 +.IX Item "-fno-zero-initialized-in-bss" +If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that +are initialized to zero into \s-1BSS.\s0 This can save space in the resulting +code. +.Sp +This option turns off this behavior because some programs explicitly +rely on variables going to the data section\-\-\-e.g., so that the +resulting executable can find the beginning of that section and/or make +assumptions based on that. +.Sp +The default is \fB\-fzero\-initialized\-in\-bss\fR. +.IP "\fB\-fthread\-jumps\fR" 4 +.IX Item "-fthread-jumps" +Perform optimizations that check to see if a jump branches to a +location where another comparison subsumed by the first is found. If +so, the first branch is redirected to either the destination of the +second branch or a point immediately following it, depending on whether +the condition is known to be true or false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fsplit\-wide\-types\fR" 4 +.IX Item "-fsplit-wide-types" +When using a type that occupies multiple registers, such as \f(CW\*(C`long +long\*(C'\fR on a 32\-bit system, split the registers apart and allocate them +independently. This normally generates better code for those types, +but may make debugging more difficult. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, +\&\fB\-Os\fR. +.IP "\fB\-fcse\-follow\-jumps\fR" 4 +.IX Item "-fcse-follow-jumps" +In common subexpression elimination (\s-1CSE\s0), scan through jump instructions +when the target of the jump is not reached by any other path. For +example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an +\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 follows the jump when the condition +tested is false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcse\-skip\-blocks\fR" 4 +.IX Item "-fcse-skip-blocks" +This is similar to \fB\-fcse\-follow\-jumps\fR, but causes \s-1CSE\s0 to +follow jumps that conditionally skip over blocks. When \s-1CSE\s0 +encounters a simple \f(CW\*(C`if\*(C'\fR statement with no else clause, +\&\fB\-fcse\-skip\-blocks\fR causes \s-1CSE\s0 to follow the jump around the +body of the \f(CW\*(C`if\*(C'\fR. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-frerun\-cse\-after\-loop\fR" 4 +.IX Item "-frerun-cse-after-loop" +Re-run common subexpression elimination after loop optimizations are +performed. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\fR" 4 +.IX Item "-fgcse" +Perform a global common subexpression elimination pass. +This pass also performs global constant and copy propagation. +.Sp +\&\fINote:\fR When compiling a program using computed gotos, a \s-1GCC\s0 +extension, you may get better run-time performance if you disable +the global common subexpression elimination pass by adding +\&\fB\-fno\-gcse\fR to the command line. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\-lm\fR" 4 +.IX Item "-fgcse-lm" +When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination +attempts to move loads that are only killed by stores into themselves. This +allows a loop containing a load/store sequence to be changed to a load outside +the loop, and a copy/store within the loop. +.Sp +Enabled by default when \fB\-fgcse\fR is enabled. +.IP "\fB\-fgcse\-sm\fR" 4 +.IX Item "-fgcse-sm" +When \fB\-fgcse\-sm\fR is enabled, a store motion pass is run after +global common subexpression elimination. This pass attempts to move +stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR, +loops containing a load/store sequence can be changed to a load before +the loop and a store after the loop. +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-las\fR" 4 +.IX Item "-fgcse-las" +When \fB\-fgcse\-las\fR is enabled, the global common subexpression +elimination pass eliminates redundant loads that come after stores to the +same memory location (both partial and full redundancies). +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-after\-reload\fR" 4 +.IX Item "-fgcse-after-reload" +When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination +pass is performed after reload. The purpose of this pass is to clean up +redundant spilling. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-faggressive\-loop\-optimizations\fR" 4 +.IX Item "-faggressive-loop-optimizations" +This option tells the loop optimizer to use language constraints to +derive bounds for the number of iterations of a loop. This assumes that +loop code does not invoke undefined behavior by for example causing signed +integer overflows or out-of-bound array accesses. The bounds for the +number of iterations of a loop are used to guide loop unrolling and peeling +and loop exit test optimizations. +This option is enabled by default. +.IP "\fB\-funconstrained\-commons\fR" 4 +.IX Item "-funconstrained-commons" +This option tells the compiler that variables declared in common blocks +(e.g. Fortran) may later be overridden with longer trailing arrays. This +prevents certain optimizations that depend on knowing the array bounds. +.IP "\fB\-fcrossjumping\fR" 4 +.IX Item "-fcrossjumping" +Perform cross-jumping transformation. +This transformation unifies equivalent code and saves code size. The +resulting code may or may not perform better than without cross-jumping. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fauto\-inc\-dec\fR" 4 +.IX Item "-fauto-inc-dec" +Combine increments or decrements of addresses with memory accesses. +This pass is always skipped on architectures that do not have +instructions to support this. Enabled by default at \fB\-O\fR and +higher on architectures that support this. +.IP "\fB\-fdce\fR" 4 +.IX Item "-fdce" +Perform dead code elimination (\s-1DCE\s0) on \s-1RTL.\s0 +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fdse\fR" 4 +.IX Item "-fdse" +Perform dead store elimination (\s-1DSE\s0) on \s-1RTL.\s0 +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fif\-conversion\fR" 4 +.IX Item "-fif-conversion" +Attempt to transform conditional jumps into branch-less equivalents. This +includes use of conditional moves, min, max, set flags and abs instructions, and +some tricks doable by standard arithmetics. The use of conditional execution +on chips where it is available is controlled by \fB\-fif\-conversion2\fR. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, but +not with \fB\-Og\fR. +.IP "\fB\-fif\-conversion2\fR" 4 +.IX Item "-fif-conversion2" +Use conditional execution (where available) to transform conditional jumps into +branch-less equivalents. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, but +not with \fB\-Og\fR. +.IP "\fB\-fdeclone\-ctor\-dtor\fR" 4 +.IX Item "-fdeclone-ctor-dtor" +The \*(C+ \s-1ABI\s0 requires multiple entry points for constructors and +destructors: one for a base subobject, one for a complete object, and +one for a virtual destructor that calls operator delete afterwards. +For a hierarchy with virtual bases, the base and complete variants are +clones, which means two copies of the function. With this option, the +base and complete variants are changed to be thunks that call a common +implementation. +.Sp +Enabled by \fB\-Os\fR. +.IP "\fB\-fdelete\-null\-pointer\-checks\fR" 4 +.IX Item "-fdelete-null-pointer-checks" +Assume that programs cannot safely dereference null pointers, and that +no code or data element resides at address zero. +This option enables simple constant +folding optimizations at all optimization levels. In addition, other +optimization passes in \s-1GCC\s0 use this flag to control global dataflow +analyses that eliminate useless checks for null pointers; these assume +that a memory access to address zero always results in a trap, so +that if a pointer is checked after it has already been dereferenced, +it cannot be null. +.Sp +Note however that in some environments this assumption is not true. +Use \fB\-fno\-delete\-null\-pointer\-checks\fR to disable this optimization +for programs that depend on that behavior. +.Sp +This option is enabled by default on most targets. On Nios \s-1II ELF,\s0 it +defaults to off. On \s-1AVR, CR16,\s0 and \s-1MSP430,\s0 this option is completely disabled. +.Sp +Passes that use the dataflow information +are enabled independently at different optimization levels. +.IP "\fB\-fdevirtualize\fR" 4 +.IX Item "-fdevirtualize" +Attempt to convert calls to virtual functions to direct calls. This +is done both within a procedure and interprocedurally as part of +indirect inlining (\fB\-findirect\-inlining\fR) and interprocedural constant +propagation (\fB\-fipa\-cp\fR). +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fdevirtualize\-speculatively\fR" 4 +.IX Item "-fdevirtualize-speculatively" +Attempt to convert calls to virtual functions to speculative direct calls. +Based on the analysis of the type inheritance graph, determine for a given call +the set of likely targets. If the set is small, preferably of size 1, change +the call into a conditional deciding between direct and indirect calls. The +speculative calls enable more optimizations, such as inlining. When they seem +useless after further optimization, they are converted back into original form. +.IP "\fB\-fdevirtualize\-at\-ltrans\fR" 4 +.IX Item "-fdevirtualize-at-ltrans" +Stream extra information needed for aggressive devirtualization when running +the link-time optimizer in local transformation mode. +This option enables more devirtualization but +significantly increases the size of streamed data. For this reason it is +disabled by default. +.IP "\fB\-fexpensive\-optimizations\fR" 4 +.IX Item "-fexpensive-optimizations" +Perform a number of minor optimizations that are relatively expensive. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-free\fR" 4 +.IX Item "-free" +Attempt to remove redundant extension instructions. This is especially +helpful for the x86\-64 architecture, which implicitly zero-extends in 64\-bit +registers after writing to their lower 32\-bit half. +.Sp +Enabled for Alpha, AArch64 and x86 at levels \fB\-O2\fR, +\&\fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-lifetime\-dse\fR" 4 +.IX Item "-fno-lifetime-dse" +In \*(C+ the value of an object is only affected by changes within its +lifetime: when the constructor begins, the object has an indeterminate +value, and any changes during the lifetime of the object are dead when +the object is destroyed. Normally dead store elimination will take +advantage of this; if your code relies on the value of the object +storage persisting beyond the lifetime of the object, you can use this +flag to disable this optimization. To preserve stores before the +constructor starts (e.g. because your operator new clears the object +storage) but still treat the object as dead after the destructor you, +can use \fB\-flifetime\-dse=1\fR. The default behavior can be +explicitly selected with \fB\-flifetime\-dse=2\fR. +\&\fB\-flifetime\-dse=0\fR is equivalent to \fB\-fno\-lifetime\-dse\fR. +.IP "\fB\-flive\-range\-shrinkage\fR" 4 +.IX Item "-flive-range-shrinkage" +Attempt to decrease register pressure through register live range +shrinkage. This is helpful for fast processors with small or moderate +size register sets. +.IP "\fB\-fira\-algorithm=\fR\fIalgorithm\fR" 4 +.IX Item "-fira-algorithm=algorithm" +Use the specified coloring algorithm for the integrated register +allocator. The \fIalgorithm\fR argument can be \fBpriority\fR, which +specifies Chow's priority coloring, or \fB\s-1CB\s0\fR, which specifies +Chaitin-Briggs coloring. Chaitin-Briggs coloring is not implemented +for all architectures, but for those targets that do support it, it is +the default because it generates better code. +.IP "\fB\-fira\-region=\fR\fIregion\fR" 4 +.IX Item "-fira-region=region" +Use specified regions for the integrated register allocator. The +\&\fIregion\fR argument should be one of the following: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Use all loops as register allocation regions. +This can give the best results for machines with a small and/or +irregular register set. +.IP "\fBmixed\fR" 4 +.IX Item "mixed" +Use all loops except for loops with small register pressure +as the regions. This value usually gives +the best results in most cases and for most architectures, +and is enabled by default when compiling with optimization for speed +(\fB\-O\fR, \fB\-O2\fR, ...). +.IP "\fBone\fR" 4 +.IX Item "one" +Use all functions as a single region. +This typically results in the smallest code size, and is enabled by default for +\&\fB\-Os\fR or \fB\-O0\fR. +.RE +.RS 4 +.RE +.IP "\fB\-fira\-hoist\-pressure\fR" 4 +.IX Item "-fira-hoist-pressure" +Use \s-1IRA\s0 to evaluate register pressure in the code hoisting pass for +decisions to hoist expressions. This option usually results in smaller +code, but it can slow the compiler down. +.Sp +This option is enabled at level \fB\-Os\fR for all targets. +.IP "\fB\-fira\-loop\-pressure\fR" 4 +.IX Item "-fira-loop-pressure" +Use \s-1IRA\s0 to evaluate register pressure in loops for decisions to move +loop invariants. This option usually results in generation +of faster and smaller code on machines with large register files (>= 32 +registers), but it can slow the compiler down. +.Sp +This option is enabled at level \fB\-O3\fR for some targets. +.IP "\fB\-fno\-ira\-share\-save\-slots\fR" 4 +.IX Item "-fno-ira-share-save-slots" +Disable sharing of stack slots used for saving call-used hard +registers living through a call. Each hard register gets a +separate stack slot, and as a result function stack frames are +larger. +.IP "\fB\-fno\-ira\-share\-spill\-slots\fR" 4 +.IX Item "-fno-ira-share-spill-slots" +Disable sharing of stack slots allocated for pseudo-registers. Each +pseudo-register that does not get a hard register gets a separate +stack slot, and as a result function stack frames are larger. +.IP "\fB\-flra\-remat\fR" 4 +.IX Item "-flra-remat" +Enable CFG-sensitive rematerialization in \s-1LRA.\s0 Instead of loading +values of spilled pseudos, \s-1LRA\s0 tries to rematerialize (recalculate) +values if it is profitable. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fdelayed\-branch\fR" 4 +.IX Item "-fdelayed-branch" +If supported for the target machine, attempt to reorder instructions +to exploit instruction slots available after delayed branch +instructions. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, +but not at \fB\-Og\fR. +.IP "\fB\-fschedule\-insns\fR" 4 +.IX Item "-fschedule-insns" +If supported for the target machine, attempt to reorder instructions to +eliminate execution stalls due to required data being unavailable. This +helps machines that have slow floating point or memory load instructions +by allowing other instructions to be issued until the result of the load +or floating-point instruction is required. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fschedule\-insns2\fR" 4 +.IX Item "-fschedule-insns2" +Similar to \fB\-fschedule\-insns\fR, but requests an additional pass of +instruction scheduling after register allocation has been done. This is +especially useful on machines with a relatively small number of +registers and where memory load instructions take more than one cycle. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-sched\-interblock\fR" 4 +.IX Item "-fno-sched-interblock" +Disable instruction scheduling across basic blocks, which +is normally enabled when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fno\-sched\-spec\fR" 4 +.IX Item "-fno-sched-spec" +Disable speculative motion of non-load instructions, which +is normally enabled when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-pressure\fR" 4 +.IX Item "-fsched-pressure" +Enable register pressure sensitive insn scheduling before register +allocation. This only makes sense when scheduling before register +allocation is enabled, i.e. with \fB\-fschedule\-insns\fR or at +\&\fB\-O2\fR or higher. Usage of this option can improve the +generated code and decrease its size by preventing register pressure +increase above the number of available hard registers and subsequent +spills in register allocation. +.IP "\fB\-fsched\-spec\-load\fR" 4 +.IX Item "-fsched-spec-load" +Allow speculative motion of some load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-load\-dangerous\fR" 4 +.IX Item "-fsched-spec-load-dangerous" +Allow speculative motion of more load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-stalled\-insns\fR" 4 +.IX Item "-fsched-stalled-insns" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns=n" +.PD +Define how many insns (if any) can be moved prematurely from the queue +of stalled insns into the ready list during the second scheduling pass. +\&\fB\-fno\-sched\-stalled\-insns\fR means that no insns are moved +prematurely, \fB\-fsched\-stalled\-insns=0\fR means there is no limit +on how many queued insns can be moved prematurely. +\&\fB\-fsched\-stalled\-insns\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns=1\fR. +.IP "\fB\-fsched\-stalled\-insns\-dep\fR" 4 +.IX Item "-fsched-stalled-insns-dep" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns-dep=n" +.PD +Define how many insn groups (cycles) are examined for a dependency +on a stalled insn that is a candidate for premature removal from the queue +of stalled insns. This has an effect only during the second scheduling pass, +and only if \fB\-fsched\-stalled\-insns\fR is used. +\&\fB\-fno\-sched\-stalled\-insns\-dep\fR is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=0\fR. +\&\fB\-fsched\-stalled\-insns\-dep\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=1\fR. +.IP "\fB\-fsched2\-use\-superblocks\fR" 4 +.IX Item "-fsched2-use-superblocks" +When scheduling after register allocation, use superblock scheduling. +This allows motion across basic block boundaries, +resulting in faster schedules. This option is experimental, as not all machine +descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable +results from the algorithm. +.Sp +This only makes sense when scheduling after register allocation, i.e. with +\&\fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-group\-heuristic\fR" 4 +.IX Item "-fsched-group-heuristic" +Enable the group heuristic in the scheduler. This heuristic favors +the instruction that belongs to a schedule group. This is enabled +by default when scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-critical\-path\-heuristic\fR" 4 +.IX Item "-fsched-critical-path-heuristic" +Enable the critical-path heuristic in the scheduler. This heuristic favors +instructions on the critical path. This is enabled by default when +scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-insn\-heuristic\fR" 4 +.IX Item "-fsched-spec-insn-heuristic" +Enable the speculative instruction heuristic in the scheduler. This +heuristic favors speculative instructions with greater dependency weakness. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR +or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-rank\-heuristic\fR" 4 +.IX Item "-fsched-rank-heuristic" +Enable the rank heuristic in the scheduler. This heuristic favors +the instruction belonging to a basic block with greater size or frequency. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-last\-insn\-heuristic\fR" 4 +.IX Item "-fsched-last-insn-heuristic" +Enable the last-instruction heuristic in the scheduler. This heuristic +favors the instruction that is less dependent on the last instruction +scheduled. This is enabled by default when scheduling is enabled, +i.e. with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-dep\-count\-heuristic\fR" 4 +.IX Item "-fsched-dep-count-heuristic" +Enable the dependent-count heuristic in the scheduler. This heuristic +favors the instruction that has more instructions depending on it. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4 +.IX Item "-freschedule-modulo-scheduled-loops" +Modulo scheduling is performed before traditional scheduling. If a loop +is modulo scheduled, later scheduling passes may change its schedule. +Use this option to control that behavior. +.IP "\fB\-fselective\-scheduling\fR" 4 +.IX Item "-fselective-scheduling" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the first scheduler pass. +.IP "\fB\-fselective\-scheduling2\fR" 4 +.IX Item "-fselective-scheduling2" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the second scheduler pass. +.IP "\fB\-fsel\-sched\-pipelining\fR" 4 +.IX Item "-fsel-sched-pipelining" +Enable software pipelining of innermost loops during selective scheduling. +This option has no effect unless one of \fB\-fselective\-scheduling\fR or +\&\fB\-fselective\-scheduling2\fR is turned on. +.IP "\fB\-fsel\-sched\-pipelining\-outer\-loops\fR" 4 +.IX Item "-fsel-sched-pipelining-outer-loops" +When pipelining loops during selective scheduling, also pipeline outer loops. +This option has no effect unless \fB\-fsel\-sched\-pipelining\fR is turned on. +.IP "\fB\-fsemantic\-interposition\fR" 4 +.IX Item "-fsemantic-interposition" +Some object formats, like \s-1ELF,\s0 allow interposing of symbols by the +dynamic linker. +This means that for symbols exported from the \s-1DSO,\s0 the compiler cannot perform +interprocedural propagation, inlining and other optimizations in anticipation +that the function or variable in question may change. While this feature is +useful, for example, to rewrite memory allocation functions by a debugging +implementation, it is expensive in the terms of code quality. +With \fB\-fno\-semantic\-interposition\fR the compiler assumes that +if interposition happens for functions the overwriting function will have +precisely the same semantics (and side effects). +Similarly if interposition happens +for variables, the constructor of the variable will be the same. The flag +has no effect for functions explicitly declared inline +(where it is never allowed for interposition to change semantics) +and for symbols explicitly declared weak. +.IP "\fB\-fshrink\-wrap\fR" 4 +.IX Item "-fshrink-wrap" +Emit function prologues only before parts of the function that need it, +rather than at the top of the function. This flag is enabled by default at +\&\fB\-O\fR and higher. +.IP "\fB\-fshrink\-wrap\-separate\fR" 4 +.IX Item "-fshrink-wrap-separate" +Shrink-wrap separate parts of the prologue and epilogue separately, so that +those parts are only executed when needed. +This option is on by default, but has no effect unless \fB\-fshrink\-wrap\fR +is also turned on and the target supports this. +.IP "\fB\-fcaller\-saves\fR" 4 +.IX Item "-fcaller-saves" +Enable allocation of values to registers that are clobbered by +function calls, by emitting extra instructions to save and restore the +registers around such calls. Such allocation is done only when it +seems to result in better code. +.Sp +This option is always enabled by default on certain machines, usually +those which have no call-preserved registers to use instead. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcombine\-stack\-adjustments\fR" 4 +.IX Item "-fcombine-stack-adjustments" +Tracks stack adjustments (pushes and pops) and stack memory references +and then tries to find ways to combine them. +.Sp +Enabled by default at \fB\-O1\fR and higher. +.IP "\fB\-fipa\-ra\fR" 4 +.IX Item "-fipa-ra" +Use caller save registers for allocation if those registers are not used by +any called function. In that case it is not necessary to save and restore +them around calls. This is only possible if called functions are part of +same compilation unit as current function and they are compiled before it. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR, however the option +is disabled if generated code will be instrumented for profiling +(\fB\-p\fR, or \fB\-pg\fR) or if callee's register usage cannot be known +exactly (this happens on targets that do not expose prologues +and epilogues in \s-1RTL\s0). +.IP "\fB\-fconserve\-stack\fR" 4 +.IX Item "-fconserve-stack" +Attempt to minimize stack usage. The compiler attempts to use less +stack space, even if that makes the program slower. This option +implies setting the \fBlarge-stack-frame\fR parameter to 100 +and the \fBlarge-stack-frame-growth\fR parameter to 400. +.IP "\fB\-ftree\-reassoc\fR" 4 +.IX Item "-ftree-reassoc" +Perform reassociation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-fcode\-hoisting\fR" 4 +.IX Item "-fcode-hoisting" +Perform code hoisting. Code hoisting tries to move the +evaluation of expressions executed on all paths to the function exit +as early as possible. This is especially useful as a code size +optimization, but it often helps for code speed as well. +This flag is enabled by default at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-pre\fR" 4 +.IX Item "-ftree-pre" +Perform partial redundancy elimination (\s-1PRE\s0) on trees. This flag is +enabled by default at \fB\-O2\fR and \fB\-O3\fR. +.IP "\fB\-ftree\-partial\-pre\fR" 4 +.IX Item "-ftree-partial-pre" +Make partial redundancy elimination (\s-1PRE\s0) more aggressive. This flag is +enabled by default at \fB\-O3\fR. +.IP "\fB\-ftree\-forwprop\fR" 4 +.IX Item "-ftree-forwprop" +Perform forward propagation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-fre\fR" 4 +.IX Item "-ftree-fre" +Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference +between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions +that are computed on all paths leading to the redundant computation. +This analysis is faster than \s-1PRE,\s0 though it exposes fewer redundancies. +This flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-phiprop\fR" 4 +.IX Item "-ftree-phiprop" +Perform hoisting of loads from conditional pointers on trees. This +pass is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fhoist\-adjacent\-loads\fR" 4 +.IX Item "-fhoist-adjacent-loads" +Speculatively hoist loads from both branches of an if-then-else if the +loads are from adjacent locations in the same structure and the target +architecture has a conditional move instruction. This flag is enabled +by default at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-copy\-prop\fR" 4 +.IX Item "-ftree-copy-prop" +Perform copy propagation on trees. This pass eliminates unnecessary +copy operations. This flag is enabled by default at \fB\-O\fR and +higher. +.IP "\fB\-fipa\-pure\-const\fR" 4 +.IX Item "-fipa-pure-const" +Discover which functions are pure or constant. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-reference\fR" 4 +.IX Item "-fipa-reference" +Discover which static variables do not escape the +compilation unit. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-reference\-addressable\fR" 4 +.IX Item "-fipa-reference-addressable" +Discover read-only, write-only and non-addressable static variables. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-stack\-alignment\fR" 4 +.IX Item "-fipa-stack-alignment" +Reduce stack alignment on call sites if possible. +Enabled by default. +.IP "\fB\-fipa\-pta\fR" 4 +.IX Item "-fipa-pta" +Perform interprocedural pointer analysis and interprocedural modification +and reference analysis. This option can cause excessive memory and +compile-time usage on large compilation units. It is not enabled by +default at any optimization level. +.IP "\fB\-fipa\-profile\fR" 4 +.IX Item "-fipa-profile" +Perform interprocedural profile propagation. The functions called only from +cold functions are marked as cold. Also functions executed once (such as +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, static constructors or destructors) are identified. Cold +functions and loop less parts of functions executed once are then optimized for +size. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-cp\fR" 4 +.IX Item "-fipa-cp" +Perform interprocedural constant propagation. +This optimization analyzes the program to determine when values passed +to functions are constants and then optimizes accordingly. +This optimization can substantially increase performance +if the application has constants passed to functions. +This flag is enabled by default at \fB\-O2\fR, \fB\-Os\fR and \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fipa\-cp\-clone\fR" 4 +.IX Item "-fipa-cp-clone" +Perform function cloning to make interprocedural constant propagation stronger. +When enabled, interprocedural constant propagation performs function cloning +when externally visible function can be called with constant arguments. +Because this optimization can create multiple copies of functions, +it may significantly increase code size +(see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR). +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fipa\-bit\-cp\fR" 4 +.IX Item "-fipa-bit-cp" +When enabled, perform interprocedural bitwise constant +propagation. This flag is enabled by default at \fB\-O2\fR and +by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +It requires that \fB\-fipa\-cp\fR is enabled. +.IP "\fB\-fipa\-vrp\fR" 4 +.IX Item "-fipa-vrp" +When enabled, perform interprocedural propagation of value +ranges. This flag is enabled by default at \fB\-O2\fR. It requires +that \fB\-fipa\-cp\fR is enabled. +.IP "\fB\-fipa\-icf\fR" 4 +.IX Item "-fipa-icf" +Perform Identical Code Folding for functions and read-only variables. +The optimization reduces code size and may disturb unwind stacks by replacing +a function by equivalent one with a different name. The optimization works +more effectively with link-time optimization enabled. +.Sp +Although the behavior is similar to the Gold Linker's \s-1ICF\s0 optimization, \s-1GCC ICF\s0 +works on different levels and thus the optimizations are not same \- there are +equivalences that are found only by \s-1GCC\s0 and equivalences found only by Gold. +.Sp +This flag is enabled by default at \fB\-O2\fR and \fB\-Os\fR. +.IP "\fB\-flive\-patching=\fR\fIlevel\fR" 4 +.IX Item "-flive-patching=level" +Control \s-1GCC\s0's optimizations to produce output suitable for live-patching. +.Sp +If the compiler's optimization uses a function's body or information extracted +from its body to optimize/change another function, the latter is called an +impacted function of the former. If a function is patched, its impacted +functions should be patched too. +.Sp +The impacted functions are determined by the compiler's interprocedural +optimizations. For example, a caller is impacted when inlining a function +into its caller, +cloning a function and changing its caller to call this new clone, +or extracting a function's pureness/constness information to optimize +its direct or indirect callers, etc. +.Sp +Usually, the more \s-1IPA\s0 optimizations enabled, the larger the number of +impacted functions for each function. In order to control the number of +impacted functions and more easily compute the list of impacted function, +\&\s-1IPA\s0 optimizations can be partially enabled at two different levels. +.Sp +The \fIlevel\fR argument should be one of the following: +.RS 4 +.IP "\fBinline-clone\fR" 4 +.IX Item "inline-clone" +Only enable inlining and cloning optimizations, which includes inlining, +cloning, interprocedural scalar replacement of aggregates and partial inlining. +As a result, when patching a function, all its callers and its clones' +callers are impacted, therefore need to be patched as well. +.Sp +\&\fB\-flive\-patching=inline\-clone\fR disables the following optimization flags: +\&\fB\-fwhole\-program \-fipa\-pta \-fipa\-reference \-fipa\-ra +\&\-fipa\-icf \-fipa\-icf\-functions \-fipa\-icf\-variables +\&\-fipa\-bit\-cp \-fipa\-vrp \-fipa\-pure\-const \-fipa\-reference\-addressable +\&\-fipa\-stack\-alignment\fR +.IP "\fBinline-only-static\fR" 4 +.IX Item "inline-only-static" +Only enable inlining of static functions. +As a result, when patching a static function, all its callers are impacted +and so need to be patched as well. +.Sp +In addition to all the flags that \fB\-flive\-patching=inline\-clone\fR +disables, +\&\fB\-flive\-patching=inline\-only\-static\fR disables the following additional +optimization flags: +\&\fB\-fipa\-cp\-clone \-fipa\-sra \-fpartial\-inlining \-fipa\-cp\fR +.RE +.RS 4 +.Sp +When \fB\-flive\-patching\fR is specified without any value, the default value +is \fIinline-clone\fR. +.Sp +This flag is disabled by default. +.Sp +Note that \fB\-flive\-patching\fR is not supported with link-time optimization +(\fB\-flto\fR). +.RE +.IP "\fB\-fisolate\-erroneous\-paths\-dereference\fR" 4 +.IX Item "-fisolate-erroneous-paths-dereference" +Detect paths that trigger erroneous or undefined behavior due to +dereferencing a null pointer. Isolate those paths from the main control +flow and turn the statement with erroneous or undefined behavior into a trap. +This flag is enabled by default at \fB\-O2\fR and higher and depends on +\&\fB\-fdelete\-null\-pointer\-checks\fR also being enabled. +.IP "\fB\-fisolate\-erroneous\-paths\-attribute\fR" 4 +.IX Item "-fisolate-erroneous-paths-attribute" +Detect paths that trigger erroneous or undefined behavior due to a null value +being used in a way forbidden by a \f(CW\*(C`returns_nonnull\*(C'\fR or \f(CW\*(C`nonnull\*(C'\fR +attribute. Isolate those paths from the main control flow and turn the +statement with erroneous or undefined behavior into a trap. This is not +currently enabled, but may be enabled by \fB\-O2\fR in the future. +.IP "\fB\-ftree\-sink\fR" 4 +.IX Item "-ftree-sink" +Perform forward store motion on trees. This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-bit\-ccp\fR" 4 +.IX Item "-ftree-bit-ccp" +Perform sparse conditional bit constant propagation on trees and propagate +pointer alignment information. +This pass only operates on local scalar variables and is enabled by default +at \fB\-O1\fR and higher, except for \fB\-Og\fR. +It requires that \fB\-ftree\-ccp\fR is enabled. +.IP "\fB\-ftree\-ccp\fR" 4 +.IX Item "-ftree-ccp" +Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This +pass only operates on local scalar variables and is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-fssa\-backprop\fR" 4 +.IX Item "-fssa-backprop" +Propagate information about uses of a value up the definition chain +in order to simplify the definitions. For example, this pass strips +sign operations if the sign of a value never matters. The flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fssa\-phiopt\fR" 4 +.IX Item "-fssa-phiopt" +Perform pattern matching on \s-1SSA PHI\s0 nodes to optimize conditional +code. This pass is enabled by default at \fB\-O1\fR and higher, +except for \fB\-Og\fR. +.IP "\fB\-ftree\-switch\-conversion\fR" 4 +.IX Item "-ftree-switch-conversion" +Perform conversion of simple initializations in a switch to +initializations from a scalar array. This flag is enabled by default +at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-tail\-merge\fR" 4 +.IX Item "-ftree-tail-merge" +Look for identical code sequences. When found, replace one with a jump to the +other. This optimization is known as tail merging or cross jumping. This flag +is enabled by default at \fB\-O2\fR and higher. The compilation time +in this pass can +be limited using \fBmax-tail-merge-comparisons\fR parameter and +\&\fBmax-tail-merge-iterations\fR parameter. +.IP "\fB\-ftree\-dce\fR" 4 +.IX Item "-ftree-dce" +Perform dead code elimination (\s-1DCE\s0) on trees. This flag is enabled by +default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-builtin\-call\-dce\fR" 4 +.IX Item "-ftree-builtin-call-dce" +Perform conditional dead code elimination (\s-1DCE\s0) for calls to built-in functions +that may set \f(CW\*(C`errno\*(C'\fR but are otherwise free of side effects. This flag is +enabled by default at \fB\-O2\fR and higher if \fB\-Os\fR is not also +specified. +.IP "\fB\-ftree\-dominator\-opts\fR" 4 +.IX Item "-ftree-dominator-opts" +Perform a variety of simple scalar cleanups (constant/copy +propagation, redundancy elimination, range propagation and expression +simplification) based on a dominator tree traversal. This also +performs jump threading (to reduce jumps to jumps). This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-dse\fR" 4 +.IX Item "-ftree-dse" +Perform dead store elimination (\s-1DSE\s0) on trees. A dead store is a store into +a memory location that is later overwritten by another store without +any intervening loads. In this case the earlier store can be deleted. This +flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-ch\fR" 4 +.IX Item "-ftree-ch" +Perform loop header copying on trees. This is beneficial since it increases +effectiveness of code motion optimizations. It also saves one jump. This flag +is enabled by default at \fB\-O\fR and higher. It is not enabled +for \fB\-Os\fR, since it usually increases code size. +.IP "\fB\-ftree\-loop\-optimize\fR" 4 +.IX Item "-ftree-loop-optimize" +Perform loop optimizations on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-loop\-linear\fR" 4 +.IX Item "-ftree-loop-linear" +.PD 0 +.IP "\fB\-floop\-strip\-mine\fR" 4 +.IX Item "-floop-strip-mine" +.IP "\fB\-floop\-block\fR" 4 +.IX Item "-floop-block" +.PD +Perform loop nest optimizations. Same as +\&\fB\-floop\-nest\-optimize\fR. To use this code transformation, \s-1GCC\s0 has +to be configured with \fB\-\-with\-isl\fR to enable the Graphite loop +transformation infrastructure. +.IP "\fB\-fgraphite\-identity\fR" 4 +.IX Item "-fgraphite-identity" +Enable the identity transformation for graphite. For every SCoP we generate +the polyhedral representation and transform it back to gimple. Using +\&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the +\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations +are also performed by the code generator isl, like index splitting and +dead code elimination in loops. +.IP "\fB\-floop\-nest\-optimize\fR" 4 +.IX Item "-floop-nest-optimize" +Enable the isl based loop nest optimizer. This is a generic loop nest +optimizer based on the Pluto optimization algorithms. It calculates a loop +structure optimized for data-locality and parallelism. This option +is experimental. +.IP "\fB\-floop\-parallelize\-all\fR" 4 +.IX Item "-floop-parallelize-all" +Use the Graphite data dependence analysis to identify loops that can +be parallelized. Parallelize all the loops that can be analyzed to +not contain loop carried dependences without checking that it is +profitable to parallelize the loops. +.IP "\fB\-ftree\-coalesce\-vars\fR" 4 +.IX Item "-ftree-coalesce-vars" +While transforming the program out of the \s-1SSA\s0 representation, attempt to +reduce copying by coalescing versions of different user-defined +variables, instead of just compiler temporaries. This may severely +limit the ability to debug an optimized program compiled with +\&\fB\-fno\-var\-tracking\-assignments\fR. In the negated form, this flag +prevents \s-1SSA\s0 coalescing of user variables. This option is enabled by +default if optimization is enabled, and it does very little otherwise. +.IP "\fB\-ftree\-loop\-if\-convert\fR" 4 +.IX Item "-ftree-loop-if-convert" +Attempt to transform conditional jumps in the innermost loops to +branch-less equivalents. The intent is to remove control-flow from +the innermost loops in order to improve the ability of the +vectorization pass to handle these loops. This is enabled by default +if vectorization is enabled. +.IP "\fB\-ftree\-loop\-distribution\fR" 4 +.IX Item "-ftree-loop-distribution" +Perform loop distribution. This flag can improve cache performance on +big loop bodies and allow further loop optimizations, like +parallelization or vectorization, to take place. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = B(I) + C +\& D(I) = E(I) * F +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = B(I) + C +\& ENDDO +\& DO I = 1, N +\& D(I) = E(I) * F +\& ENDDO +.Ve +.Sp +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-ftree\-loop\-distribute\-patterns\fR" 4 +.IX Item "-ftree-loop-distribute-patterns" +Perform loop distribution of patterns that can be code generated with +calls to a library. This flag is enabled by default at \fB\-O3\fR, and +by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.Sp +This pass distributes the initialization loops and generates a call to +memset zero. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = 0 +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = 0 +\& ENDDO +\& DO I = 1, N +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +and the initialization loop is transformed into a call to memset zero. +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-floop\-interchange\fR" 4 +.IX Item "-floop-interchange" +Perform loop interchange outside of graphite. This flag can improve cache +performance on loop nest and allow further loop optimizations, like +vectorization, to take place. For example, the loop +.Sp +.Vb 4 +\& for (int i = 0; i < N; i++) +\& for (int j = 0; j < N; j++) +\& for (int k = 0; k < N; k++) +\& c[i][j] = c[i][j] + a[i][k]*b[k][j]; +.Ve +.Sp +is transformed to +.Sp +.Vb 4 +\& for (int i = 0; i < N; i++) +\& for (int k = 0; k < N; k++) +\& for (int j = 0; j < N; j++) +\& c[i][j] = c[i][j] + a[i][k]*b[k][j]; +.Ve +.Sp +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-floop\-unroll\-and\-jam\fR" 4 +.IX Item "-floop-unroll-and-jam" +Apply unroll and jam transformations on feasible loops. In a loop +nest this unrolls the outer loop by some factor and fuses the resulting +multiple inner loops. This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-ftree\-loop\-im\fR" 4 +.IX Item "-ftree-loop-im" +Perform loop invariant motion on trees. This pass moves only invariants that +are hard to handle at \s-1RTL\s0 level (function calls, operations that expand to +nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves +operands of conditions that are invariant out of the loop, so that we can use +just trivial invariantness analysis in loop unswitching. The pass also includes +store motion. +.IP "\fB\-ftree\-loop\-ivcanon\fR" 4 +.IX Item "-ftree-loop-ivcanon" +Create a canonical counter for number of iterations in loops for which +determining number of iterations requires complicated analysis. Later +optimizations then may determine the number easily. Useful especially +in connection with unrolling. +.IP "\fB\-ftree\-scev\-cprop\fR" 4 +.IX Item "-ftree-scev-cprop" +Perform final value replacement. If a variable is modified in a loop +in such a way that its value when exiting the loop can be determined using +only its initial value and the number of loop iterations, replace uses of +the final value by such a computation, provided it is sufficiently cheap. +This reduces data dependencies and may allow further simplifications. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fivopts\fR" 4 +.IX Item "-fivopts" +Perform induction variable optimizations (strength reduction, induction +variable merging and induction variable elimination) on trees. +.IP "\fB\-ftree\-parallelize\-loops=n\fR" 4 +.IX Item "-ftree-parallelize-loops=n" +Parallelize loops, i.e., split their iteration space to run in n threads. +This is only possible for loops whose iterations are independent +and can be arbitrarily reordered. The optimization is only +profitable on multiprocessor machines, for loops that are CPU-intensive, +rather than constrained e.g. by memory bandwidth. This option +implies \fB\-pthread\fR, and thus is only supported on targets +that have support for \fB\-pthread\fR. +.IP "\fB\-ftree\-pta\fR" 4 +.IX Item "-ftree-pta" +Perform function-local points-to analysis on trees. This flag is +enabled by default at \fB\-O1\fR and higher, except for \fB\-Og\fR. +.IP "\fB\-ftree\-sra\fR" 4 +.IX Item "-ftree-sra" +Perform scalar replacement of aggregates. This pass replaces structure +references with scalars to prevent committing structures to memory too +early. This flag is enabled by default at \fB\-O1\fR and higher, +except for \fB\-Og\fR. +.IP "\fB\-fstore\-merging\fR" 4 +.IX Item "-fstore-merging" +Perform merging of narrow stores to consecutive memory addresses. This pass +merges contiguous stores of immediate values narrower than a word into fewer +wider stores to reduce the number of instructions. This is enabled by default +at \fB\-O2\fR and higher as well as \fB\-Os\fR. +.IP "\fB\-ftree\-ter\fR" 4 +.IX Item "-ftree-ter" +Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single +use/single def temporaries are replaced at their use location with their +defining expression. This results in non-GIMPLE code, but gives the expanders +much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-slsr\fR" 4 +.IX Item "-ftree-slsr" +Perform straight-line strength reduction on trees. This recognizes related +expressions involving multiplications and replaces them by less expensive +calculations when possible. This is enabled by default at \fB\-O\fR and +higher. +.IP "\fB\-ftree\-vectorize\fR" 4 +.IX Item "-ftree-vectorize" +Perform vectorization on trees. This flag enables \fB\-ftree\-loop\-vectorize\fR +and \fB\-ftree\-slp\-vectorize\fR if not explicitly specified. +.IP "\fB\-ftree\-loop\-vectorize\fR" 4 +.IX Item "-ftree-loop-vectorize" +Perform loop vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR and by \fB\-ftree\-vectorize\fR, \fB\-fprofile\-use\fR, +and \fB\-fauto\-profile\fR. +.IP "\fB\-ftree\-slp\-vectorize\fR" 4 +.IX Item "-ftree-slp-vectorize" +Perform basic block vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR and by \fB\-ftree\-vectorize\fR, \fB\-fprofile\-use\fR, +and \fB\-fauto\-profile\fR. +.IP "\fB\-fvect\-cost\-model=\fR\fImodel\fR" 4 +.IX Item "-fvect-cost-model=model" +Alter the cost model used for vectorization. The \fImodel\fR argument +should be one of \fBunlimited\fR, \fBdynamic\fR or \fBcheap\fR. +With the \fBunlimited\fR model the vectorized code-path is assumed +to be profitable while with the \fBdynamic\fR model a runtime check +guards the vectorized code-path to enable it only for iteration +counts that will likely execute faster than when executing the original +scalar loop. The \fBcheap\fR model disables vectorization of +loops where doing so would be cost prohibitive for example due to +required runtime checks for data dependence or alignment but otherwise +is equal to the \fBdynamic\fR model. +The default cost model depends on other optimization flags and is +either \fBdynamic\fR or \fBcheap\fR. +.IP "\fB\-fsimd\-cost\-model=\fR\fImodel\fR" 4 +.IX Item "-fsimd-cost-model=model" +Alter the cost model used for vectorization of loops marked with the OpenMP +simd directive. The \fImodel\fR argument should be one of +\&\fBunlimited\fR, \fBdynamic\fR, \fBcheap\fR. All values of \fImodel\fR +have the same meaning as described in \fB\-fvect\-cost\-model\fR and by +default a cost model defined with \fB\-fvect\-cost\-model\fR is used. +.IP "\fB\-ftree\-vrp\fR" 4 +.IX Item "-ftree-vrp" +Perform Value Range Propagation on trees. This is similar to the +constant propagation pass, but instead of values, ranges of values are +propagated. This allows the optimizers to remove unnecessary range +checks like array bound checks and null pointer checks. This is +enabled by default at \fB\-O2\fR and higher. Null pointer check +elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is +enabled. +.IP "\fB\-fsplit\-paths\fR" 4 +.IX Item "-fsplit-paths" +Split paths leading to loop backedges. This can improve dead code +elimination and common subexpression elimination. This is enabled by +default at \fB\-O3\fR and above. +.IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4 +.IX Item "-fsplit-ivs-in-unroller" +Enables expression of values of induction variables in later iterations +of the unrolled loop using the value in the first iteration. This breaks +long dependency chains, thus improving efficiency of the scheduling passes. +.Sp +A combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the +same effect. However, that is not reliable in cases where the loop body +is more complicated than a single basic block. It also does not work at all +on some architectures due to restrictions in the \s-1CSE\s0 pass. +.Sp +This optimization is enabled by default. +.IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4 +.IX Item "-fvariable-expansion-in-unroller" +With this option, the compiler creates multiple copies of some +local variables when unrolling a loop, which can result in superior code. +.IP "\fB\-fpartial\-inlining\fR" 4 +.IX Item "-fpartial-inlining" +Inline parts of functions. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fpredictive\-commoning\fR" 4 +.IX Item "-fpredictive-commoning" +Perform predictive commoning optimization, i.e., reusing computations +(especially memory loads and stores) performed in previous +iterations of loops. +.Sp +This option is enabled at level \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fprefetch\-loop\-arrays\fR" 4 +.IX Item "-fprefetch-loop-arrays" +If supported by the target machine, generate instructions to prefetch +memory to improve the performance of loops that access large arrays. +.Sp +This option may generate better or worse code; results are highly +dependent on the structure of loops within the source code. +.Sp +Disabled at level \fB\-Os\fR. +.IP "\fB\-fno\-printf\-return\-value\fR" 4 +.IX Item "-fno-printf-return-value" +Do not substitute constants for known return value of formatted output +functions such as \f(CW\*(C`sprintf\*(C'\fR, \f(CW\*(C`snprintf\*(C'\fR, \f(CW\*(C`vsprintf\*(C'\fR, and +\&\f(CW\*(C`vsnprintf\*(C'\fR (but not \f(CW\*(C`printf\*(C'\fR of \f(CW\*(C`fprintf\*(C'\fR). This +transformation allows \s-1GCC\s0 to optimize or even eliminate branches based +on the known return value of these functions called with arguments that +are either constant, or whose values are known to be in a range that +makes determining the exact return value possible. For example, when +\&\fB\-fprintf\-return\-value\fR is in effect, both the branch and the +body of the \f(CW\*(C`if\*(C'\fR statement (but not the call to \f(CW\*(C`snprint\*(C'\fR) +can be optimized away when \f(CW\*(C`i\*(C'\fR is a 32\-bit or smaller integer +because the return value is guaranteed to be at most 8. +.Sp +.Vb 3 +\& char buf[9]; +\& if (snprintf (buf, "%08x", i) >= sizeof buf) +\& ... +.Ve +.Sp +The \fB\-fprintf\-return\-value\fR option relies on other optimizations +and yields best results with \fB\-O2\fR and above. It works in tandem +with the \fB\-Wformat\-overflow\fR and \fB\-Wformat\-truncation\fR +options. The \fB\-fprintf\-return\-value\fR option is enabled by default. +.IP "\fB\-fno\-peephole\fR" 4 +.IX Item "-fno-peephole" +.PD 0 +.IP "\fB\-fno\-peephole2\fR" 4 +.IX Item "-fno-peephole2" +.PD +Disable any machine-specific peephole optimizations. The difference +between \fB\-fno\-peephole\fR and \fB\-fno\-peephole2\fR is in how they +are implemented in the compiler; some targets use one, some use the +other, a few use both. +.Sp +\&\fB\-fpeephole\fR is enabled by default. +\&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-guess\-branch\-probability\fR" 4 +.IX Item "-fno-guess-branch-probability" +Do not guess branch probabilities using heuristics. +.Sp +\&\s-1GCC\s0 uses heuristics to guess branch probabilities if they are +not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These +heuristics are based on the control flow graph. If some branch probabilities +are specified by \f(CW\*(C`_\|_builtin_expect\*(C'\fR, then the heuristics are +used to guess branch probabilities for the rest of the control flow graph, +taking the \f(CW\*(C`_\|_builtin_expect\*(C'\fR info into account. The interactions +between the heuristics and \f(CW\*(C`_\|_builtin_expect\*(C'\fR can be complex, and in +some cases, it may be useful to disable the heuristics so that the effects +of \f(CW\*(C`_\|_builtin_expect\*(C'\fR are easier to understand. +.Sp +It is also possible to specify expected probability of the expression +with \f(CW\*(C`_\|_builtin_expect_with_probability\*(C'\fR built-in function. +.Sp +The default is \fB\-fguess\-branch\-probability\fR at levels +\&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-blocks\fR" 4 +.IX Item "-freorder-blocks" +Reorder basic blocks in the compiled function in order to reduce number of +taken branches and improve code locality. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-blocks\-algorithm=\fR\fIalgorithm\fR" 4 +.IX Item "-freorder-blocks-algorithm=algorithm" +Use the specified algorithm for basic block reordering. The +\&\fIalgorithm\fR argument can be \fBsimple\fR, which does not increase +code size (except sometimes due to secondary effects like alignment), +or \fBstc\fR, the \*(L"software trace cache\*(R" algorithm, which tries to +put all often executed code together, minimizing the number of branches +executed by making extra copies of code. +.Sp +The default is \fBsimple\fR at levels \fB\-O\fR, \fB\-Os\fR, and +\&\fBstc\fR at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-freorder\-blocks\-and\-partition\fR" 4 +.IX Item "-freorder-blocks-and-partition" +In addition to reordering basic blocks in the compiled function, in order +to reduce number of taken branches, partitions hot and cold basic blocks +into separate sections of the assembly and \fI.o\fR files, to improve +paging and cache locality performance. +.Sp +This optimization is automatically turned off in the presence of +exception handling or unwind tables (on targets using setjump/longjump or target specific scheme), for linkonce sections, for functions with a user-defined +section attribute and on any architecture that does not support named +sections. When \fB\-fsplit\-stack\fR is used this option is not +enabled by default (to avoid linker errors), but may be enabled +explicitly (if using a working linker). +.Sp +Enabled for x86 at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-functions\fR" 4 +.IX Item "-freorder-functions" +Reorder functions in the object file in order to +improve code locality. This is implemented by using special +subsections \f(CW\*(C`.text.hot\*(C'\fR for most frequently executed functions and +\&\f(CW\*(C`.text.unlikely\*(C'\fR for unlikely executed functions. Reordering is done by +the linker so object file format must support named sections and linker must +place them in a reasonable way. +.Sp +This option isn't effective unless you either provide profile feedback +(see \fB\-fprofile\-arcs\fR for details) or manually annotate functions with +\&\f(CW\*(C`hot\*(C'\fR or \f(CW\*(C`cold\*(C'\fR attributes. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fstrict\-aliasing\fR" 4 +.IX Item "-fstrict-aliasing" +Allow the compiler to assume the strictest aliasing rules applicable to +the language being compiled. For C (and \*(C+), this activates +optimizations based on the type of expressions. In particular, an +object of one type is assumed never to reside at the same address as an +object of a different type, unless the types are almost the same. For +example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a +\&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR. A character type may alias any other +type. +.Sp +Pay special attention to code like this: +.Sp +.Vb 4 +\& union a_union { +\& int i; +\& double d; +\& }; +\& +\& int f() { +\& union a_union t; +\& t.d = 3.0; +\& return t.i; +\& } +.Ve +.Sp +The practice of reading from a different union member than the one most +recently written to (called \*(L"type-punning\*(R") is common. Even with +\&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory +is accessed through the union type. So, the code above works as +expected. However, this code might not: +.Sp +.Vb 7 +\& int f() { +\& union a_union t; +\& int* ip; +\& t.d = 3.0; +\& ip = &t.i; +\& return *ip; +\& } +.Ve +.Sp +Similarly, access by taking the address, casting the resulting pointer +and dereferencing the result has undefined behavior, even if the cast +uses a union type, e.g.: +.Sp +.Vb 4 +\& int f() { +\& double d = 3.0; +\& return ((union a_union *) &d)\->i; +\& } +.Ve +.Sp +The \fB\-fstrict\-aliasing\fR option is enabled at levels +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-falign\-functions\fR" 4 +.IX Item "-falign-functions" +.PD 0 +.IP "\fB\-falign\-functions=\fR\fIn\fR" 4 +.IX Item "-falign-functions=n" +.IP "\fB\-falign\-functions=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-functions=n:m" +.IP "\fB\-falign\-functions=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-functions=n:m:n2" +.IP "\fB\-falign\-functions=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-functions=n:m:n2:m2" +.PD +Align the start of functions to the next power-of-two greater than +\&\fIn\fR, skipping up to \fIm\fR\-1 bytes. This ensures that at least +the first \fIm\fR bytes of the function can be fetched by the \s-1CPU\s0 +without crossing an \fIn\fR\-byte alignment boundary. +.Sp +If \fIm\fR is not specified, it defaults to \fIn\fR. +.Sp +Examples: \fB\-falign\-functions=32\fR aligns functions to the next +32\-byte boundary, \fB\-falign\-functions=24\fR aligns to the next +32\-byte boundary only if this can be done by skipping 23 bytes or less, +\&\fB\-falign\-functions=32:7\fR aligns to the next +32\-byte boundary only if this can be done by skipping 6 bytes or less. +.Sp +The second pair of \fIn2\fR:\fIm2\fR values allows you to specify +a secondary alignment: \fB\-falign\-functions=64:7:32:3\fR aligns to +the next 64\-byte boundary if this can be done by skipping 6 bytes or less, +otherwise aligns to the next 32\-byte boundary if this can be done +by skipping 2 bytes or less. +If \fIm2\fR is not specified, it defaults to \fIn2\fR. +.Sp +Some assemblers only support this flag when \fIn\fR is a power of two; +in that case, it is rounded up. +.Sp +\&\fB\-fno\-align\-functions\fR and \fB\-falign\-functions=1\fR are +equivalent and mean that functions are not aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +The maximum allowed \fIn\fR option value is 65536. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-flimit\-function\-alignment\fR" 4 +.IX Item "-flimit-function-alignment" +If this option is enabled, the compiler tries to avoid unnecessarily +overaligning functions. It attempts to instruct the assembler to align +by the amount specified by \fB\-falign\-functions\fR, but not to +skip more bytes than the size of the function. +.IP "\fB\-falign\-labels\fR" 4 +.IX Item "-falign-labels" +.PD 0 +.IP "\fB\-falign\-labels=\fR\fIn\fR" 4 +.IX Item "-falign-labels=n" +.IP "\fB\-falign\-labels=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-labels=n:m" +.IP "\fB\-falign\-labels=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-labels=n:m:n2" +.IP "\fB\-falign\-labels=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-labels=n:m:n2:m2" +.PD +Align all branch targets to a power-of-two boundary. +.Sp +Parameters of this option are analogous to the \fB\-falign\-functions\fR option. +\&\fB\-fno\-align\-labels\fR and \fB\-falign\-labels=1\fR are +equivalent and mean that labels are not aligned. +.Sp +If \fB\-falign\-loops\fR or \fB\-falign\-jumps\fR are applicable and +are greater than this value, then their values are used instead. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default +which is very likely to be \fB1\fR, meaning no alignment. +The maximum allowed \fIn\fR option value is 65536. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-loops\fR" 4 +.IX Item "-falign-loops" +.PD 0 +.IP "\fB\-falign\-loops=\fR\fIn\fR" 4 +.IX Item "-falign-loops=n" +.IP "\fB\-falign\-loops=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-loops=n:m" +.IP "\fB\-falign\-loops=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-loops=n:m:n2" +.IP "\fB\-falign\-loops=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-loops=n:m:n2:m2" +.PD +Align loops to a power-of-two boundary. If the loops are executed +many times, this makes up for any execution of the dummy padding +instructions. +.Sp +Parameters of this option are analogous to the \fB\-falign\-functions\fR option. +\&\fB\-fno\-align\-loops\fR and \fB\-falign\-loops=1\fR are +equivalent and mean that loops are not aligned. +The maximum allowed \fIn\fR option value is 65536. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-jumps\fR" 4 +.IX Item "-falign-jumps" +.PD 0 +.IP "\fB\-falign\-jumps=\fR\fIn\fR" 4 +.IX Item "-falign-jumps=n" +.IP "\fB\-falign\-jumps=\fR\fIn\fR\fB:\fR\fIm\fR" 4 +.IX Item "-falign-jumps=n:m" +.IP "\fB\-falign\-jumps=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR" 4 +.IX Item "-falign-jumps=n:m:n2" +.IP "\fB\-falign\-jumps=\fR\fIn\fR\fB:\fR\fIm\fR\fB:\fR\fIn2\fR\fB:\fR\fIm2\fR" 4 +.IX Item "-falign-jumps=n:m:n2:m2" +.PD +Align branch targets to a power-of-two boundary, for branch targets +where the targets can only be reached by jumping. In this case, +no dummy operations need be executed. +.Sp +Parameters of this option are analogous to the \fB\-falign\-functions\fR option. +\&\fB\-fno\-align\-jumps\fR and \fB\-falign\-jumps=1\fR are +equivalent and mean that loops are not aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +The maximum allowed \fIn\fR option value is 65536. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-funit\-at\-a\-time\fR" 4 +.IX Item "-funit-at-a-time" +This option is left for compatibility reasons. \fB\-funit\-at\-a\-time\fR +has no effect, while \fB\-fno\-unit\-at\-a\-time\fR implies +\&\fB\-fno\-toplevel\-reorder\fR and \fB\-fno\-section\-anchors\fR. +.Sp +Enabled by default. +.IP "\fB\-fno\-toplevel\-reorder\fR" 4 +.IX Item "-fno-toplevel-reorder" +Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR +statements. Output them in the same order that they appear in the +input file. When this option is used, unreferenced static variables +are not removed. This option is intended to support existing code +that relies on a particular ordering. For new code, it is better to +use attributes when possible. +.Sp +\&\fB\-ftoplevel\-reorder\fR is the default at \fB\-O1\fR and higher, and +also at \fB\-O0\fR if \fB\-fsection\-anchors\fR is explicitly requested. +Additionally \fB\-fno\-toplevel\-reorder\fR implies +\&\fB\-fno\-section\-anchors\fR. +.IP "\fB\-fweb\fR" 4 +.IX Item "-fweb" +Constructs webs as commonly used for register allocation purposes and assign +each web individual pseudo register. This allows the register allocation pass +to operate on pseudos directly, but also strengthens several other optimization +passes, such as \s-1CSE,\s0 loop optimizer and trivial dead code remover. It can, +however, make debugging impossible, since variables no longer stay in a +\&\*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR. +.IP "\fB\-fwhole\-program\fR" 4 +.IX Item "-fwhole-program" +Assume that the current compilation unit represents the whole program being +compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR +and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions +and in effect are optimized more aggressively by interprocedural optimizers. +.Sp +This option should not be used in combination with \fB\-flto\fR. +Instead relying on a linker plugin should provide safer and more precise +information. +.IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-flto[=n]" +This option runs the standard link-time optimizer. When invoked +with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal +representations) and writes it to special \s-1ELF\s0 sections in the object +file. When the object files are linked together, all the function +bodies are read from these \s-1ELF\s0 sections and instantiated as if they +had been part of the same translation unit. +.Sp +To use the link-time optimizer, \fB\-flto\fR and optimization +options should be specified at compile time and during the final link. +It is recommended that you compile all the files participating in the +same link with the same options and also specify those options at +link time. +For example: +.Sp +.Vb 3 +\& gcc \-c \-O2 \-flto foo.c +\& gcc \-c \-O2 \-flto bar.c +\& gcc \-o myprog \-flto \-O2 foo.o bar.o +.Ve +.Sp +The first two invocations to \s-1GCC\s0 save a bytecode representation +of \s-1GIMPLE\s0 into special \s-1ELF\s0 sections inside \fIfoo.o\fR and +\&\fIbar.o\fR. The final invocation reads the \s-1GIMPLE\s0 bytecode from +\&\fIfoo.o\fR and \fIbar.o\fR, merges the two files into a single +internal image, and compiles the result as usual. Since both +\&\fIfoo.o\fR and \fIbar.o\fR are merged into a single image, this +causes all the interprocedural analyses and optimizations in \s-1GCC\s0 to +work across the two files as if they were a single one. This means, +for example, that the inliner is able to inline functions in +\&\fIbar.o\fR into functions in \fIfoo.o\fR and vice-versa. +.Sp +Another (simpler) way to enable link-time optimization is: +.Sp +.Vb 1 +\& gcc \-o myprog \-flto \-O2 foo.c bar.c +.Ve +.Sp +The above generates bytecode for \fIfoo.c\fR and \fIbar.c\fR, +merges them together into a single \s-1GIMPLE\s0 representation and optimizes +them as usual to produce \fImyprog\fR. +.Sp +The important thing to keep in mind is that to enable link-time +optimizations you need to use the \s-1GCC\s0 driver to perform the link step. +\&\s-1GCC\s0 automatically performs link-time optimization if any of the +objects involved were compiled with the \fB\-flto\fR command-line option. +You can always override +the automatic decision to do link-time optimization +by passing \fB\-fno\-lto\fR to the link command. +.Sp +To make whole program optimization effective, it is necessary to make +certain whole program assumptions. The compiler needs to know +what functions and variables can be accessed by libraries and runtime +outside of the link-time optimized unit. When supported by the linker, +the linker plugin (see \fB\-fuse\-linker\-plugin\fR) passes information +to the compiler about used and externally visible symbols. When +the linker plugin is not available, \fB\-fwhole\-program\fR should be +used to allow the compiler to make these assumptions, which leads +to more aggressive optimization decisions. +.Sp +When a file is compiled with \fB\-flto\fR without +\&\fB\-fuse\-linker\-plugin\fR, the generated object file is larger than +a regular object file because it contains \s-1GIMPLE\s0 bytecodes and the usual +final code (see \fB\-ffat\-lto\-objects\fR. This means that +object files with \s-1LTO\s0 information can be linked as normal object +files; if \fB\-fno\-lto\fR is passed to the linker, no +interprocedural optimizations are applied. Note that when +\&\fB\-fno\-fat\-lto\-objects\fR is enabled the compile stage is faster +but you cannot perform a regular, non-LTO link on them. +.Sp +When producing the final binary, \s-1GCC\s0 only +applies link-time optimizations to those files that contain bytecode. +Therefore, you can mix and match object files and libraries with +\&\s-1GIMPLE\s0 bytecodes and final object code. \s-1GCC\s0 automatically selects +which files to optimize in \s-1LTO\s0 mode and which files to link without +further processing. +.Sp +Generally, options specified at link time override those +specified at compile time, although in some cases \s-1GCC\s0 attempts to infer +link-time options from the settings used to compile the input files. +.Sp +If you do not specify an optimization level option \fB\-O\fR at +link time, then \s-1GCC\s0 uses the highest optimization level +used when compiling the object files. Note that it is generally +ineffective to specify an optimization level option only at link time and +not at compile time, for two reasons. First, compiling without +optimization suppresses compiler passes that gather information +needed for effective optimization at link time. Second, some early +optimization passes can be performed only at compile time and +not at link time. +.Sp +There are some code generation flags preserved by \s-1GCC\s0 when +generating bytecodes, as they need to be used during the final link. +Currently, the following options and their settings are taken from +the first object file that explicitly specifies them: +\&\fB\-fPIC\fR, \fB\-fpic\fR, \fB\-fpie\fR, \fB\-fcommon\fR, +\&\fB\-fexceptions\fR, \fB\-fnon\-call\-exceptions\fR, \fB\-fgnu\-tm\fR +and all the \fB\-m\fR target flags. +.Sp +Certain ABI-changing flags are required to match in all compilation units, +and trying to override this at link time with a conflicting value +is ignored. This includes options such as \fB\-freg\-struct\-return\fR +and \fB\-fpcc\-struct\-return\fR. +.Sp +Other options such as \fB\-ffp\-contract\fR, \fB\-fno\-strict\-overflow\fR, +\&\fB\-fwrapv\fR, \fB\-fno\-trapv\fR or \fB\-fno\-strict\-aliasing\fR +are passed through to the link stage and merged conservatively for +conflicting translation units. Specifically +\&\fB\-fno\-strict\-overflow\fR, \fB\-fwrapv\fR and \fB\-fno\-trapv\fR take +precedence; and for example \fB\-ffp\-contract=off\fR takes precedence +over \fB\-ffp\-contract=fast\fR. You can override them at link time. +.Sp +When you need to pass options to the assembler via \fB\-Wa\fR or +\&\fB\-Xassembler\fR make sure to either compile such translation +units with \fB\-fno\-lto\fR or consistently use the same assembler +options on all translation units. You can alternatively also +specify assembler options at \s-1LTO\s0 link time. +.Sp +If \s-1LTO\s0 encounters objects with C linkage declared with incompatible +types in separate translation units to be linked together (undefined +behavior according to \s-1ISO C99 6.2.7\s0), a non-fatal diagnostic may be +issued. The behavior is still undefined at run time. Similar +diagnostics may be raised for other languages. +.Sp +Another feature of \s-1LTO\s0 is that it is possible to apply interprocedural +optimizations on files written in different languages: +.Sp +.Vb 4 +\& gcc \-c \-flto foo.c +\& g++ \-c \-flto bar.cc +\& gfortran \-c \-flto baz.f90 +\& g++ \-o myprog \-flto \-O3 foo.o bar.o baz.o \-lgfortran +.Ve +.Sp +Notice that the final link is done with \fBg++\fR to get the \*(C+ +runtime libraries and \fB\-lgfortran\fR is added to get the Fortran +runtime libraries. In general, when mixing languages in \s-1LTO\s0 mode, you +should use the same link command options as when mixing languages in a +regular (non-LTO) compilation. +.Sp +If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say +\&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you +are using a linker with plugin support. To create static libraries suitable +for \s-1LTO,\s0 use \fBgcc-ar\fR and \fBgcc-ranlib\fR instead of \fBar\fR +and \fBranlib\fR; +to show the symbols of object files with \s-1GIMPLE\s0 bytecode, use +\&\fBgcc-nm\fR. Those commands require that \fBar\fR, \fBranlib\fR +and \fBnm\fR have been compiled with plugin support. At link time, use the +flag \fB\-fuse\-linker\-plugin\fR to ensure that the library participates in +the \s-1LTO\s0 optimization process: +.Sp +.Vb 1 +\& gcc \-o myprog \-O2 \-flto \-fuse\-linker\-plugin a.o b.o \-lfoo +.Ve +.Sp +With the linker plugin enabled, the linker extracts the needed +\&\s-1GIMPLE\s0 files from \fIlibfoo.a\fR and passes them on to the running \s-1GCC\s0 +to make them part of the aggregated \s-1GIMPLE\s0 image to be optimized. +.Sp +If you are not using a linker with plugin support and/or do not +enable the linker plugin, then the objects inside \fIlibfoo.a\fR +are extracted and linked as usual, but they do not participate +in the \s-1LTO\s0 optimization process. In order to make a static library suitable +for both \s-1LTO\s0 optimization and usual linkage, compile its object files with +\&\fB\-flto\fR \fB\-ffat\-lto\-objects\fR. +.Sp +Link-time optimizations do not require the presence of the whole program to +operate. If the program does not require any symbols to be exported, it is +possible to combine \fB\-flto\fR and \fB\-fwhole\-program\fR to allow +the interprocedural optimizers to use more aggressive assumptions which may +lead to improved optimization opportunities. +Use of \fB\-fwhole\-program\fR is not needed when linker plugin is +active (see \fB\-fuse\-linker\-plugin\fR). +.Sp +The current implementation of \s-1LTO\s0 makes no +attempt to generate bytecode that is portable between different +types of hosts. The bytecode files are versioned and there is a +strict version check, so bytecode files generated in one version of +\&\s-1GCC\s0 do not work with an older or newer version of \s-1GCC.\s0 +.Sp +Link-time optimization does not work well with generation of debugging +information on systems other than those using a combination of \s-1ELF\s0 and +\&\s-1DWARF.\s0 +.Sp +If you specify the optional \fIn\fR, the optimization and code +generation done at link time is executed in parallel using \fIn\fR +parallel jobs by utilizing an installed \fBmake\fR program. The +environment variable \fB\s-1MAKE\s0\fR may be used to override the program +used. The default value for \fIn\fR is 1. +.Sp +You can also specify \fB\-flto=jobserver\fR to use \s-1GNU\s0 make's +job server mode to determine the number of parallel jobs. This +is useful when the Makefile calling \s-1GCC\s0 is already executing in parallel. +You must prepend a \fB+\fR to the command recipe in the parent Makefile +for this to work. This option likely only works if \fB\s-1MAKE\s0\fR is +\&\s-1GNU\s0 make. +.IP "\fB\-flto\-partition=\fR\fIalg\fR" 4 +.IX Item "-flto-partition=alg" +Specify the partitioning algorithm used by the link-time optimizer. +The value is either \fB1to1\fR to specify a partitioning mirroring +the original source files or \fBbalanced\fR to specify partitioning +into equally sized chunks (whenever possible) or \fBmax\fR to create +new partition for every symbol where possible. Specifying \fBnone\fR +as an algorithm disables partitioning and streaming completely. +The default value is \fBbalanced\fR. While \fB1to1\fR can be used +as an workaround for various code ordering issues, the \fBmax\fR +partitioning is intended for internal testing only. +The value \fBone\fR specifies that exactly one partition should be +used while the value \fBnone\fR bypasses partitioning and executes +the link-time optimization step directly from the \s-1WPA\s0 phase. +.IP "\fB\-flto\-odr\-type\-merging\fR" 4 +.IX Item "-flto-odr-type-merging" +Enable streaming of mangled types names of \*(C+ types and their unification +at link time. This increases size of \s-1LTO\s0 object files, but enables +diagnostics about One Definition Rule violations. +.IP "\fB\-flto\-compression\-level=\fR\fIn\fR" 4 +.IX Item "-flto-compression-level=n" +This option specifies the level of compression used for intermediate +language written to \s-1LTO\s0 object files, and is only meaningful in +conjunction with \s-1LTO\s0 mode (\fB\-flto\fR). Valid +values are 0 (no compression) to 9 (maximum compression). Values +outside this range are clamped to either 0 or 9. If the option is not +given, a default balanced compression setting is used. +.IP "\fB\-fuse\-linker\-plugin\fR" 4 +.IX Item "-fuse-linker-plugin" +Enables the use of a linker plugin during link-time optimization. This +option relies on plugin support in the linker, which is available in gold +or in \s-1GNU\s0 ld 2.21 or newer. +.Sp +This option enables the extraction of object files with \s-1GIMPLE\s0 bytecode out +of library archives. This improves the quality of optimization by exposing +more code to the link-time optimizer. This information specifies what +symbols can be accessed externally (by non-LTO object or during dynamic +linking). Resulting code quality improvements on binaries (and shared +libraries that use hidden visibility) are similar to \fB\-fwhole\-program\fR. +See \fB\-flto\fR for a description of the effect of this flag and how to +use it. +.Sp +This option is enabled by default when \s-1LTO\s0 support in \s-1GCC\s0 is enabled +and \s-1GCC\s0 was configured for use with +a linker supporting plugins (\s-1GNU\s0 ld 2.21 or newer or gold). +.IP "\fB\-ffat\-lto\-objects\fR" 4 +.IX Item "-ffat-lto-objects" +Fat \s-1LTO\s0 objects are object files that contain both the intermediate language +and the object code. This makes them usable for both \s-1LTO\s0 linking and normal +linking. This option is effective only when compiling with \fB\-flto\fR +and is ignored at link time. +.Sp +\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO,\s0 but +requires the complete toolchain to be aware of \s-1LTO.\s0 It requires a linker with +linker plugin support for basic functionality. Additionally, +\&\fBnm\fR, \fBar\fR and \fBranlib\fR +need to support linker plugins to allow a full-featured build environment +(capable of building static libraries etc). \s-1GCC\s0 provides the \fBgcc-ar\fR, +\&\fBgcc-nm\fR, \fBgcc-ranlib\fR wrappers to pass the right options +to these tools. With non fat \s-1LTO\s0 makefiles need to be modified to use them. +.Sp +Note that modern binutils provide plugin auto-load mechanism. +Installing the linker plugin into \fI\f(CI$libdir\fI/bfd\-plugins\fR has the same +effect as usage of the command wrappers (\fBgcc-ar\fR, \fBgcc-nm\fR and +\&\fBgcc-ranlib\fR). +.Sp +The default is \fB\-fno\-fat\-lto\-objects\fR on targets with linker plugin +support. +.IP "\fB\-fcompare\-elim\fR" 4 +.IX Item "-fcompare-elim" +After register allocation and post-register allocation instruction splitting, +identify arithmetic instructions that compute processor flags similar to a +comparison operation based on that arithmetic. If possible, eliminate the +explicit comparison operation. +.Sp +This pass only applies to certain targets that cannot explicitly represent +the comparison operation before register allocation is complete. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcprop\-registers\fR" 4 +.IX Item "-fcprop-registers" +After register allocation and post-register allocation instruction splitting, +perform a copy-propagation pass to try to reduce scheduling dependencies +and occasionally eliminate the copy. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fprofile\-correction\fR" 4 +.IX Item "-fprofile-correction" +Profiles collected using an instrumented binary for multi-threaded programs may +be inconsistent due to missed counter updates. When this option is specified, +\&\s-1GCC\s0 uses heuristics to correct or smooth out such inconsistencies. By +default, \s-1GCC\s0 emits an error message when an inconsistent profile is detected. +.Sp +This option is enabled by \fB\-fauto\-profile\fR. +.IP "\fB\-fprofile\-use\fR" 4 +.IX Item "-fprofile-use" +.PD 0 +.IP "\fB\-fprofile\-use=\fR\fIpath\fR" 4 +.IX Item "-fprofile-use=path" +.PD +Enable profile feedback-directed optimizations, +and the following optimizations, many of which +are generally profitable only with profile feedback available: +.Sp +\&\fB\-fbranch\-probabilities \-fprofile\-values +\&\-funroll\-loops \-fpeel\-loops \-ftracer \-fvpt +\&\-finline\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-bit\-cp +\&\-fpredictive\-commoning \-fsplit\-loops \-funswitch\-loops +\&\-fgcse\-after\-reload \-ftree\-loop\-vectorize \-ftree\-slp\-vectorize +\&\-fvect\-cost\-model=dynamic \-ftree\-loop\-distribute\-patterns +\&\-fprofile\-reorder\-functions\fR +.Sp +Before you can use this option, you must first generate profiling information. +.Sp +By default, \s-1GCC\s0 emits an error message if the feedback profiles do not +match the source code. This error can be turned into a warning by using +\&\fB\-Wno\-error=coverage\-mismatch\fR. Note this may result in poorly +optimized code. Additionally, by default, \s-1GCC\s0 also emits a warning message if +the feedback profiles do not exist (see \fB\-Wmissing\-profile\fR). +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 looks at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.IP "\fB\-fauto\-profile\fR" 4 +.IX Item "-fauto-profile" +.PD 0 +.IP "\fB\-fauto\-profile=\fR\fIpath\fR" 4 +.IX Item "-fauto-profile=path" +.PD +Enable sampling-based feedback-directed optimizations, +and the following optimizations, +many of which are generally profitable only with profile feedback available: +.Sp +\&\fB\-fbranch\-probabilities \-fprofile\-values +\&\-funroll\-loops \-fpeel\-loops \-ftracer \-fvpt +\&\-finline\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-bit\-cp +\&\-fpredictive\-commoning \-fsplit\-loops \-funswitch\-loops +\&\-fgcse\-after\-reload \-ftree\-loop\-vectorize \-ftree\-slp\-vectorize +\&\-fvect\-cost\-model=dynamic \-ftree\-loop\-distribute\-patterns +\&\-fprofile\-correction\fR +.Sp +\&\fIpath\fR is the name of a file containing AutoFDO profile information. +If omitted, it defaults to \fIfbdata.afdo\fR in the current directory. +.Sp +Producing an AutoFDO profile data file requires running your program +with the \fBperf\fR utility on a supported GNU/Linux target system. +For more information, see <\fBhttps://perf.wiki.kernel.org/\fR>. +.Sp +E.g. +.Sp +.Vb 2 +\& perf record \-e br_inst_retired:near_taken \-b \-o perf.data \e +\& \-\- your_program +.Ve +.Sp +Then use the \fBcreate_gcov\fR tool to convert the raw profile data +to a format that can be used by \s-1GCC.\s0 You must also supply the +unstripped binary for your program to this tool. +See <\fBhttps://github.com/google/autofdo\fR>. +.Sp +E.g. +.Sp +.Vb 2 +\& create_gcov \-\-binary=your_program.unstripped \-\-profile=perf.data \e +\& \-\-gcov=profile.afdo +.Ve +.PP +The following options control compiler behavior regarding floating-point +arithmetic. These options trade off between speed and +correctness. All must be specifically enabled. +.IP "\fB\-ffloat\-store\fR" 4 +.IX Item "-ffloat-store" +Do not store floating-point variables in registers, and inhibit other +options that might change whether a floating-point value is taken from a +register or memory. +.Sp +This option prevents undesirable excess precision on machines such as +the 68000 where the floating registers (of the 68881) keep more +precision than a \f(CW\*(C`double\*(C'\fR is supposed to have. Similarly for the +x86 architecture. For most programs, the excess precision does only +good, but a few programs rely on the precise definition of \s-1IEEE\s0 floating +point. Use \fB\-ffloat\-store\fR for such programs, after modifying +them to store all pertinent intermediate computations into variables. +.IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 +.IX Item "-fexcess-precision=style" +This option allows further control over excess precision on machines +where floating-point operations occur in a format with more precision or +range than the \s-1IEEE\s0 standard and interchange floating-point types. By +default, \fB\-fexcess\-precision=fast\fR is in effect; this means that +operations may be carried out in a wider precision than the types specified +in the source if that would result in faster code, and it is unpredictable +when rounding to the types specified in the source code takes place. +When compiling C, if \fB\-fexcess\-precision=standard\fR is specified then +excess precision follows the rules specified in \s-1ISO C99\s0; in particular, +both casts and assignments cause values to be rounded to their +semantic types (whereas \fB\-ffloat\-store\fR only affects +assignments). This option is enabled by default for C if a strict +conformance option such as \fB\-std=c99\fR is used. +\&\fB\-ffast\-math\fR enables \fB\-fexcess\-precision=fast\fR by default +regardless of whether a strict conformance option is used. +.Sp +\&\fB\-fexcess\-precision=standard\fR is not implemented for languages +other than C. On the x86, it has no effect if \fB\-mfpmath=sse\fR +or \fB\-mfpmath=sse+387\fR is specified; in the former case, \s-1IEEE\s0 +semantics apply without excess precision, and in the latter, rounding +is unpredictable. +.IP "\fB\-ffast\-math\fR" 4 +.IX Item "-ffast-math" +Sets the options \fB\-fno\-math\-errno\fR, \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-ffinite\-math\-only\fR, \fB\-fno\-rounding\-math\fR, +\&\fB\-fno\-signaling\-nans\fR, \fB\-fcx\-limited\-range\fR and +\&\fB\-fexcess\-precision=fast\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined. +.Sp +This option is not turned on by any \fB\-O\fR option besides +\&\fB\-Ofast\fR since it can result in incorrect output for programs +that depend on an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications +for math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.IP "\fB\-fno\-math\-errno\fR" 4 +.IX Item "-fno-math-errno" +Do not set \f(CW\*(C`errno\*(C'\fR after calling math functions that are executed +with a single instruction, e.g., \f(CW\*(C`sqrt\*(C'\fR. A program that relies on +\&\s-1IEEE\s0 exceptions for math error handling may want to use this flag +for speed while maintaining \s-1IEEE\s0 arithmetic compatibility. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fmath\-errno\fR. +.Sp +On Darwin systems, the math library never sets \f(CW\*(C`errno\*(C'\fR. There is +therefore no reason for the compiler to consider the possibility that +it might, and \fB\-fno\-math\-errno\fR is the default. +.IP "\fB\-funsafe\-math\-optimizations\fR" 4 +.IX Item "-funsafe-math-optimizations" +Allow optimizations for floating-point arithmetic that (a) assume +that arguments and results are valid and (b) may violate \s-1IEEE\s0 or +\&\s-1ANSI\s0 standards. When used at link time, it may include libraries +or startup files that change the default \s-1FPU\s0 control word or other +similar optimizations. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +Enables \fB\-fno\-signed\-zeros\fR, \fB\-fno\-trapping\-math\fR, +\&\fB\-fassociative\-math\fR and \fB\-freciprocal\-math\fR. +.Sp +The default is \fB\-fno\-unsafe\-math\-optimizations\fR. +.IP "\fB\-fassociative\-math\fR" 4 +.IX Item "-fassociative-math" +Allow re-association of operands in series of floating-point operations. +This violates the \s-1ISO C\s0 and \*(C+ language standard by possibly changing +computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as +well as ignore NaNs and inhibit or create underflow or overflow (and +thus cannot be used on code that relies on rounding behavior like +\&\f(CW\*(C`(x + 2**52) \- 2**52\*(C'\fR. May also reorder floating-point comparisons +and thus may not be used when ordered comparisons are required. +This option requires that both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR be in effect. Moreover, it doesn't make +much sense with \fB\-frounding\-math\fR. For Fortran the option +is automatically enabled when both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR are in effect. +.Sp +The default is \fB\-fno\-associative\-math\fR. +.IP "\fB\-freciprocal\-math\fR" 4 +.IX Item "-freciprocal-math" +Allow the reciprocal of a value to be used instead of dividing by +the value if this enables optimizations. For example \f(CW\*(C`x / y\*(C'\fR +can be replaced with \f(CW\*(C`x * (1/y)\*(C'\fR, which is useful if \f(CW\*(C`(1/y)\*(C'\fR +is subject to common subexpression elimination. Note that this loses +precision and increases the number of flops operating on the value. +.Sp +The default is \fB\-fno\-reciprocal\-math\fR. +.IP "\fB\-ffinite\-math\-only\fR" 4 +.IX Item "-ffinite-math-only" +Allow optimizations for floating-point arithmetic that assume +that arguments and results are not NaNs or +\-Infs. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fno\-finite\-math\-only\fR. +.IP "\fB\-fno\-signed\-zeros\fR" 4 +.IX Item "-fno-signed-zeros" +Allow optimizations for floating-point arithmetic that ignore the +signedness of zero. \s-1IEEE\s0 arithmetic specifies the behavior of +distinct +0.0 and \-0.0 values, which then prohibits simplification +of expressions such as x+0.0 or 0.0*x (even with \fB\-ffinite\-math\-only\fR). +This option implies that the sign of a zero result isn't significant. +.Sp +The default is \fB\-fsigned\-zeros\fR. +.IP "\fB\-fno\-trapping\-math\fR" 4 +.IX Item "-fno-trapping-math" +Compile code assuming that floating-point operations cannot generate +user-visible traps. These traps include division by zero, overflow, +underflow, inexact result and invalid operation. This option requires +that \fB\-fno\-signaling\-nans\fR be in effect. Setting this option may +allow faster code if one relies on \*(L"non-stop\*(R" \s-1IEEE\s0 arithmetic, for example. +.Sp +This option should never be turned on by any \fB\-O\fR option since +it can result in incorrect output for programs that depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. +.Sp +The default is \fB\-ftrapping\-math\fR. +.IP "\fB\-frounding\-math\fR" 4 +.IX Item "-frounding-math" +Disable transformations and optimizations that assume default floating-point +rounding behavior. This is round-to-zero for all floating point +to integer conversions, and round-to-nearest for all other arithmetic +truncations. This option should be specified for programs that change +the \s-1FP\s0 rounding mode dynamically, or that may be executed with a +non-default rounding mode. This option disables constant folding of +floating-point expressions at compile time (which may be affected by +rounding mode) and arithmetic transformations that are unsafe in the +presence of sign-dependent rounding modes. +.Sp +The default is \fB\-fno\-rounding\-math\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that are affected by rounding mode. +Future versions of \s-1GCC\s0 may provide finer control of this setting +using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma. This command-line option +will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR. +.IP "\fB\-fsignaling\-nans\fR" 4 +.IX Item "-fsignaling-nans" +Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible +traps during floating-point operations. Setting this option disables +optimizations that may change the number of exceptions visible with +signaling NaNs. This option implies \fB\-ftrapping\-math\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_SUPPORT_SNAN_\|_\*(C'\fR to +be defined. +.Sp +The default is \fB\-fno\-signaling\-nans\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior. +.IP "\fB\-fno\-fp\-int\-builtin\-inexact\fR" 4 +.IX Item "-fno-fp-int-builtin-inexact" +Do not allow the built-in functions \f(CW\*(C`ceil\*(C'\fR, \f(CW\*(C`floor\*(C'\fR, +\&\f(CW\*(C`round\*(C'\fR and \f(CW\*(C`trunc\*(C'\fR, and their \f(CW\*(C`float\*(C'\fR and \f(CW\*(C`long +double\*(C'\fR variants, to generate code that raises the \*(L"inexact\*(R" +floating-point exception for noninteger arguments. \s-1ISO C99\s0 and C11 +allow these functions to raise the \*(L"inexact\*(R" exception, but \s-1ISO/IEC +TS 18661\-1:2014,\s0 the C bindings to \s-1IEEE 754\-2008,\s0 does not allow these +functions to do so. +.Sp +The default is \fB\-ffp\-int\-builtin\-inexact\fR, allowing the +exception to be raised. This option does nothing unless +\&\fB\-ftrapping\-math\fR is in effect. +.Sp +Even if \fB\-fno\-fp\-int\-builtin\-inexact\fR is used, if the functions +generate a call to a library function then the \*(L"inexact\*(R" exception +may be raised if the library implementation does not follow \s-1TS 18661.\s0 +.IP "\fB\-fsingle\-precision\-constant\fR" 4 +.IX Item "-fsingle-precision-constant" +Treat floating-point constants as single precision instead of +implicitly converting them to double-precision constants. +.IP "\fB\-fcx\-limited\-range\fR" 4 +.IX Item "-fcx-limited-range" +When enabled, this option states that a range reduction step is not +needed when performing complex division. Also, there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. The +default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by +\&\fB\-ffast\-math\fR. +.Sp +This option controls the default setting of the \s-1ISO C99\s0 +\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +all languages. +.IP "\fB\-fcx\-fortran\-rules\fR" 4 +.IX Item "-fcx-fortran-rules" +Complex multiplication and division follow Fortran rules. Range +reduction is done as part of complex division, but there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. +.Sp +The default is \fB\-fno\-cx\-fortran\-rules\fR. +.PP +The following options control optimizations that may improve +performance, but are not enabled by any \fB\-O\fR options. This +section includes experimental options that may produce broken code. +.IP "\fB\-fbranch\-probabilities\fR" 4 +.IX Item "-fbranch-probabilities" +After running a program compiled with \fB\-fprofile\-arcs\fR, +you can compile it a second time using +\&\fB\-fbranch\-probabilities\fR, to improve optimizations based on +the number of times each branch was taken. When a program +compiled with \fB\-fprofile\-arcs\fR exits, it saves arc execution +counts to a file called \fI\fIsourcename\fI.gcda\fR for each source +file. The information in this data file is very dependent on the +structure of the generated code, so you must use the same source code +and the same optimization options for both compilations. +.Sp +With \fB\-fbranch\-probabilities\fR, \s-1GCC\s0 puts a +\&\fB\s-1REG_BR_PROB\s0\fR note on each \fB\s-1JUMP_INSN\s0\fR and \fB\s-1CALL_INSN\s0\fR. +These can be used to improve optimization. Currently, they are only +used in one place: in \fIreorg.c\fR, instead of guessing which path a +branch is most likely to take, the \fB\s-1REG_BR_PROB\s0\fR values are used to +exactly determine which path is taken more often. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fprofile\-values\fR" 4 +.IX Item "-fprofile-values" +If combined with \fB\-fprofile\-arcs\fR, it adds code so that some +data about values of expressions in the program is gathered. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +from profiling values of expressions for usage in optimizations. +.Sp +Enabled by \fB\-fprofile\-generate\fR, \fB\-fprofile\-use\fR, and +\&\fB\-fauto\-profile\fR. +.IP "\fB\-fprofile\-reorder\-functions\fR" 4 +.IX Item "-fprofile-reorder-functions" +Function reordering based on profile instrumentation collects +first time of execution of a function and orders these functions +in ascending order. +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-fvpt\fR" 4 +.IX Item "-fvpt" +If combined with \fB\-fprofile\-arcs\fR, this option instructs the compiler +to add code to gather information about values of expressions. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +and actually performs the optimizations based on them. +Currently the optimizations include specialization of division operations +using the knowledge about the value of the denominator. +.Sp +Enabled with \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-frename\-registers\fR" 4 +.IX Item "-frename-registers" +Attempt to avoid false dependencies in scheduled code by making use +of registers left over after register allocation. This optimization +most benefits processors with lots of registers. Depending on the +debug information format adopted by the target, however, it can +make debugging impossible, since variables no longer stay in +a \*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR. +.IP "\fB\-fschedule\-fusion\fR" 4 +.IX Item "-fschedule-fusion" +Performs a target dependent pass over the instruction stream to schedule +instructions of same type together because target machine can execute them +more efficiently if they are adjacent to each other in the instruction flow. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-ftracer\fR" 4 +.IX Item "-ftracer" +Perform tail duplication to enlarge superblock size. This transformation +simplifies the control flow of the function allowing other optimizations to do +a better job. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-funroll\-loops\fR" 4 +.IX Item "-funroll-loops" +Unroll loops whose number of iterations can be determined at compile time or +upon entry to the loop. \fB\-funroll\-loops\fR implies +\&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR. +It also turns on complete loop peeling (i.e. complete removal of loops with +a small constant number of iterations). This option makes code larger, and may +or may not make it run faster. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-funroll\-all\-loops\fR" 4 +.IX Item "-funroll-all-loops" +Unroll all loops, even if their number of iterations is uncertain when +the loop is entered. This usually makes programs run more slowly. +\&\fB\-funroll\-all\-loops\fR implies the same options as +\&\fB\-funroll\-loops\fR. +.IP "\fB\-fpeel\-loops\fR" 4 +.IX Item "-fpeel-loops" +Peels loops for which there is enough information that they do not +roll much (from profile feedback or static analysis). It also turns on +complete loop peeling (i.e. complete removal of loops with small constant +number of iterations). +.Sp +Enabled by \fB\-O3\fR, \fB\-fprofile\-use\fR, and \fB\-fauto\-profile\fR. +.IP "\fB\-fmove\-loop\-invariants\fR" 4 +.IX Item "-fmove-loop-invariants" +Enables the loop invariant motion pass in the \s-1RTL\s0 loop optimizer. Enabled +at level \fB\-O1\fR and higher, except for \fB\-Og\fR. +.IP "\fB\-fsplit\-loops\fR" 4 +.IX Item "-fsplit-loops" +Split a loop into two if it contains a condition that's always true +for one side of the iteration space and false for the other. +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-funswitch\-loops\fR" 4 +.IX Item "-funswitch-loops" +Move branches with loop invariant conditions out of the loop, with duplicates +of the loop on both branches (modified according to result of the condition). +.Sp +Enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-fversion\-loops\-for\-strides\fR" 4 +.IX Item "-fversion-loops-for-strides" +If a loop iterates over an array with a variable stride, create another +version of the loop that assumes the stride is always one. For example: +.Sp +.Vb 2 +\& for (int i = 0; i < n; ++i) +\& x[i * stride] = ...; +.Ve +.Sp +becomes: +.Sp +.Vb 6 +\& if (stride == 1) +\& for (int i = 0; i < n; ++i) +\& x[i] = ...; +\& else +\& for (int i = 0; i < n; ++i) +\& x[i * stride] = ...; +.Ve +.Sp +This is particularly useful for assumed-shape arrays in Fortran where +(for example) it allows better vectorization assuming contiguous accesses. +This flag is enabled by default at \fB\-O3\fR. +It is also enabled by \fB\-fprofile\-use\fR and \fB\-fauto\-profile\fR. +.IP "\fB\-ffunction\-sections\fR" 4 +.IX Item "-ffunction-sections" +.PD 0 +.IP "\fB\-fdata\-sections\fR" 4 +.IX Item "-fdata-sections" +.PD +Place each function or data item into its own section in the output +file if the target supports arbitrary sections. The name of the +function or the name of the data item determines the section's name +in the output file. +.Sp +Use these options on systems where the linker can perform optimizations to +improve locality of reference in the instruction space. Most systems using the +\&\s-1ELF\s0 object format have linkers with such optimizations. On \s-1AIX,\s0 the linker +rearranges sections (CSECTs) based on the call graph. The performance impact +varies. +.Sp +Together with a linker garbage collection (linker \fB\-\-gc\-sections\fR +option) these options may lead to smaller statically-linked executables (after +stripping). +.Sp +On \s-1ELF/DWARF\s0 systems these options do not degenerate the quality of the debug +information. There could be issues with other object files/debug info formats. +.Sp +Only use these options when there are significant benefits from doing so. When +you specify these options, the assembler and linker create larger object and +executable files and are also slower. These options affect code generation. +They prevent optimizations by the compiler and assembler using relative +locations inside a translation unit since the locations are unknown until +link time. An example of such an optimization is relaxing calls to short call +instructions. +.IP "\fB\-fbranch\-target\-load\-optimize\fR" 4 +.IX Item "-fbranch-target-load-optimize" +Perform branch target register load optimization before prologue / epilogue +threading. +The use of target registers can typically be exposed only during reload, +thus hoisting loads out of loops and doing inter-block scheduling needs +a separate optimization pass. +.IP "\fB\-fbranch\-target\-load\-optimize2\fR" 4 +.IX Item "-fbranch-target-load-optimize2" +Perform branch target register load optimization after prologue / epilogue +threading. +.IP "\fB\-fbtr\-bb\-exclusive\fR" 4 +.IX Item "-fbtr-bb-exclusive" +When performing branch target register load optimization, don't reuse +branch target registers within any basic block. +.IP "\fB\-fstdarg\-opt\fR" 4 +.IX Item "-fstdarg-opt" +Optimize the prologue of variadic argument functions with respect to usage of +those arguments. +.IP "\fB\-fsection\-anchors\fR" 4 +.IX Item "-fsection-anchors" +Try to reduce the number of symbolic address calculations by using +shared \*(L"anchor\*(R" symbols to address nearby objects. This transformation +can help to reduce the number of \s-1GOT\s0 entries and \s-1GOT\s0 accesses on some +targets. +.Sp +For example, the implementation of the following function \f(CW\*(C`foo\*(C'\fR: +.Sp +.Vb 2 +\& static int a, b, c; +\& int foo (void) { return a + b + c; } +.Ve +.Sp +usually calculates the addresses of all three variables, but if you +compile it with \fB\-fsection\-anchors\fR, it accesses the variables +from a common anchor point instead. The effect is similar to the +following pseudocode (which isn't valid C): +.Sp +.Vb 5 +\& int foo (void) +\& { +\& register int *xr = &x; +\& return xr[&a \- &x] + xr[&b \- &x] + xr[&c \- &x]; +\& } +.Ve +.Sp +Not all targets support this option. +.IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "--param name=value" +In some places, \s-1GCC\s0 uses various constants to control the amount of +optimization that is done. For example, \s-1GCC\s0 does not inline functions +that contain more than a certain number of instructions. You can +control some of these constants on the command line using the +\&\fB\-\-param\fR option. +.Sp +The names of specific parameters, and the meaning of the values, are +tied to the internals of the compiler, and are subject to change +without notice in future releases. +.Sp +In order to get minimal, maximal and default value of a parameter, +one can use \fB\-\-help=param \-Q\fR options. +.Sp +In each case, the \fIvalue\fR is an integer. The allowable choices for +\&\fIname\fR are: +.RS 4 +.IP "\fBpredictable-branch-outcome\fR" 4 +.IX Item "predictable-branch-outcome" +When branch is predicted to be taken with probability lower than this threshold +(in percent), then it is considered well predictable. +.IP "\fBmax-rtl-if-conversion-insns\fR" 4 +.IX Item "max-rtl-if-conversion-insns" +\&\s-1RTL\s0 if-conversion tries to remove conditional branches around a block and +replace them with conditionally executed instructions. This parameter +gives the maximum number of instructions in a block which should be +considered for if-conversion. The compiler will +also use other heuristics to decide whether if-conversion is likely to be +profitable. +.IP "\fBmax-rtl-if-conversion-predictable-cost\fR" 4 +.IX Item "max-rtl-if-conversion-predictable-cost" +.PD 0 +.IP "\fBmax-rtl-if-conversion-unpredictable-cost\fR" 4 +.IX Item "max-rtl-if-conversion-unpredictable-cost" +.PD +\&\s-1RTL\s0 if-conversion will try to remove conditional branches around a block +and replace them with conditionally executed instructions. These parameters +give the maximum permissible cost for the sequence that would be generated +by if-conversion depending on whether the branch is statically determined +to be predictable or not. The units for this parameter are the same as +those for the \s-1GCC\s0 internal seq_cost metric. The compiler will try to +provide a reasonable default for this parameter using the \s-1BRANCH_COST\s0 +target macro. +.IP "\fBmax-crossjump-edges\fR" 4 +.IX Item "max-crossjump-edges" +The maximum number of incoming edges to consider for cross-jumping. +The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in +the number of edges incoming to each block. Increasing values mean +more aggressive optimization, making the compilation time increase with +probably small improvement in executable size. +.IP "\fBmin-crossjump-insns\fR" 4 +.IX Item "min-crossjump-insns" +The minimum number of instructions that must be matched at the end +of two blocks before cross-jumping is performed on them. This +value is ignored in the case where all instructions in the block being +cross-jumped from are matched. +.IP "\fBmax-grow-copy-bb-insns\fR" 4 +.IX Item "max-grow-copy-bb-insns" +The maximum code size expansion factor when copying basic blocks +instead of jumping. The expansion is relative to a jump instruction. +.IP "\fBmax-goto-duplication-insns\fR" 4 +.IX Item "max-goto-duplication-insns" +The maximum number of instructions to duplicate to a block that jumps +to a computed goto. To avoid O(N^2) behavior in a number of +passes, \s-1GCC\s0 factors computed gotos early in the compilation process, +and unfactors them as late as possible. Only computed jumps at the +end of a basic blocks with no more than max-goto-duplication-insns are +unfactored. +.IP "\fBmax-delay-slot-insn-search\fR" 4 +.IX Item "max-delay-slot-insn-search" +The maximum number of instructions to consider when looking for an +instruction to fill a delay slot. If more than this arbitrary number of +instructions are searched, the time savings from filling the delay slot +are minimal, so stop searching. Increasing values mean more +aggressive optimization, making the compilation time increase with probably +small improvement in execution time. +.IP "\fBmax-delay-slot-live-search\fR" 4 +.IX Item "max-delay-slot-live-search" +When trying to fill delay slots, the maximum number of instructions to +consider when searching for a block with valid live register +information. Increasing this arbitrarily chosen value means more +aggressive optimization, increasing the compilation time. This parameter +should be removed when the delay slot code is rewritten to maintain the +control-flow graph. +.IP "\fBmax-gcse-memory\fR" 4 +.IX Item "max-gcse-memory" +The approximate maximum amount of memory that can be allocated in +order to perform the global common subexpression elimination +optimization. If more memory than specified is required, the +optimization is not done. +.IP "\fBmax-gcse-insertion-ratio\fR" 4 +.IX Item "max-gcse-insertion-ratio" +If the ratio of expression insertions to deletions is larger than this value +for any expression, then \s-1RTL PRE\s0 inserts or removes the expression and thus +leaves partially redundant computations in the instruction stream. +.IP "\fBmax-pending-list-length\fR" 4 +.IX Item "max-pending-list-length" +The maximum number of pending dependencies scheduling allows +before flushing the current state and starting over. Large functions +with few branches or calls can create excessively large lists which +needlessly consume memory and resources. +.IP "\fBmax-modulo-backtrack-attempts\fR" 4 +.IX Item "max-modulo-backtrack-attempts" +The maximum number of backtrack attempts the scheduler should make +when modulo scheduling a loop. Larger values can exponentially increase +compilation time. +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +Several parameters control the tree inliner used in \s-1GCC.\s0 +This number sets the maximum number of instructions (counted in \s-1GCC\s0's +internal representation) in a single function that the tree inliner +considers for inlining. This only affects functions declared +inline and methods implemented in a class declaration (\*(C+). +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR), +a lot of functions that would otherwise not be considered for inlining +by the compiler are investigated. To those functions, a different +(more restrictive) limit compared to functions declared inline can +be applied. +.IP "\fBmax-inline-insns-small\fR" 4 +.IX Item "max-inline-insns-small" +This is bound applied to calls which are considered relevant with +\&\fB\-finline\-small\-functions\fR. +.IP "\fBmax-inline-insns-size\fR" 4 +.IX Item "max-inline-insns-size" +This is bound applied to calls which are optimized for size. Small growth +may be desirable to anticipate optimization oppurtunities exposed by inlining. +.IP "\fBuninlined-function-insns\fR" 4 +.IX Item "uninlined-function-insns" +Number of instructions accounted by inliner for function overhead such as +function prologue and epilogue. +.IP "\fBuninlined-function-time\fR" 4 +.IX Item "uninlined-function-time" +Extra time accounted by inliner for function overhead such as time needed to +execute function prologue and epilogue +.IP "\fBuninlined-thunk-insns\fR" 4 +.IX Item "uninlined-thunk-insns" +.PD 0 +.IP "\fBuninlined-thunk-time\fR" 4 +.IX Item "uninlined-thunk-time" +.PD +Same as \fB\-\-param uninlined-function-insns\fR and +\&\fB\-\-param uninlined-function-time\fR but applied to function thunks +.IP "\fBinline-min-speedup\fR" 4 +.IX Item "inline-min-speedup" +When estimated performance improvement of caller + callee runtime exceeds this +threshold (in percent), the function can be inlined regardless of the limit on +\&\fB\-\-param max-inline-insns-single\fR and \fB\-\-param +max-inline-insns-auto\fR. +.IP "\fBlarge-function-insns\fR" 4 +.IX Item "large-function-insns" +The limit specifying really large functions. For functions larger than this +limit after inlining, inlining is constrained by +\&\fB\-\-param large-function-growth\fR. This parameter is useful primarily +to avoid extreme compilation time caused by non-linear algorithms used by the +back end. +.IP "\fBlarge-function-growth\fR" 4 +.IX Item "large-function-growth" +Specifies maximal growth of large function caused by inlining in percents. +For example, parameter value 100 limits large function growth to 2.0 times +the original size. +.IP "\fBlarge-unit-insns\fR" 4 +.IX Item "large-unit-insns" +The limit specifying large translation unit. Growth caused by inlining of +units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR. +For small units this might be too tight. +For example, consider a unit consisting of function A +that is inline and B that just calls A three times. If B is small relative to +A, the growth of unit is 300\e% and yet such inlining is very sane. For very +large units consisting of small inlineable functions, however, the overall unit +growth limit is needed to avoid exponential explosion of code size. Thus for +smaller units, the size is increased to \fB\-\-param large-unit-insns\fR +before applying \fB\-\-param inline-unit-growth\fR. +.IP "\fBinline-unit-growth\fR" 4 +.IX Item "inline-unit-growth" +Specifies maximal overall growth of the compilation unit caused by inlining. +For example, parameter value 20 limits unit growth to 1.2 times the original +size. Cold functions (either marked cold via an attribute or by profile +feedback) are not accounted into the unit size. +.IP "\fBipcp-unit-growth\fR" 4 +.IX Item "ipcp-unit-growth" +Specifies maximal overall growth of the compilation unit caused by +interprocedural constant propagation. For example, parameter value 10 limits +unit growth to 1.1 times the original size. +.IP "\fBlarge-stack-frame\fR" 4 +.IX Item "large-stack-frame" +The limit specifying large stack frames. While inlining the algorithm is trying +to not grow past this limit too much. +.IP "\fBlarge-stack-frame-growth\fR" 4 +.IX Item "large-stack-frame-growth" +Specifies maximal growth of large stack frames caused by inlining in percents. +For example, parameter value 1000 limits large stack frame growth to 11 times +the original size. +.IP "\fBmax-inline-insns-recursive\fR" 4 +.IX Item "max-inline-insns-recursive" +.PD 0 +.IP "\fBmax-inline-insns-recursive-auto\fR" 4 +.IX Item "max-inline-insns-recursive-auto" +.PD +Specifies the maximum number of instructions an out-of-line copy of a +self-recursive inline +function can grow into by performing recursive inlining. +.Sp +\&\fB\-\-param max-inline-insns-recursive\fR applies to functions +declared inline. +For functions not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled; \fB\-\-param max-inline-insns-recursive-auto\fR applies instead. +.IP "\fBmax-inline-recursive-depth\fR" 4 +.IX Item "max-inline-recursive-depth" +.PD 0 +.IP "\fBmax-inline-recursive-depth-auto\fR" 4 +.IX Item "max-inline-recursive-depth-auto" +.PD +Specifies the maximum recursion depth used for recursive inlining. +.Sp +\&\fB\-\-param max-inline-recursive-depth\fR applies to functions +declared inline. For functions not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled; \fB\-\-param max-inline-recursive-depth-auto\fR applies instead. +.IP "\fBmin-inline-recursive-probability\fR" 4 +.IX Item "min-inline-recursive-probability" +Recursive inlining is profitable only for function having deep recursion +in average and can hurt for function having little recursion depth by +increasing the prologue size or complexity of function body to other +optimizers. +.Sp +When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual +recursion depth can be guessed from the probability that function recurses +via a given call expression. This parameter limits inlining only to call +expressions whose probability exceeds the given threshold (in percents). +.IP "\fBearly-inlining-insns\fR" 4 +.IX Item "early-inlining-insns" +Specify growth that the early inliner can make. In effect it increases +the amount of inlining for code having a large abstraction penalty. +.IP "\fBmax-early-inliner-iterations\fR" 4 +.IX Item "max-early-inliner-iterations" +Limit of iterations of the early inliner. This basically bounds +the number of nested indirect calls the early inliner can resolve. +Deeper chains are still handled by late inlining. +.IP "\fBcomdat-sharing-probability\fR" 4 +.IX Item "comdat-sharing-probability" +Probability (in percent) that \*(C+ inline function with comdat visibility +are shared across multiple compilation units. +.IP "\fBprofile-func-internal-id\fR" 4 +.IX Item "profile-func-internal-id" +A parameter to control whether to use function internal id in profile +database lookup. If the value is 0, the compiler uses an id that +is based on function assembler name and filename, which makes old profile +data more tolerant to source changes such as function reordering etc. +.IP "\fBmin-vect-loop-bound\fR" 4 +.IX Item "min-vect-loop-bound" +The minimum number of iterations under which loops are not vectorized +when \fB\-ftree\-vectorize\fR is used. The number of iterations after +vectorization needs to be greater than the value specified by this option +to allow vectorization. +.IP "\fBgcse-cost-distance-ratio\fR" 4 +.IX Item "gcse-cost-distance-ratio" +Scaling factor in calculation of maximum distance an expression +can be moved by \s-1GCSE\s0 optimizations. This is currently supported only in the +code hoisting pass. The bigger the ratio, the more aggressive code hoisting +is with simple expressions, i.e., the expressions that have cost +less than \fBgcse-unrestricted-cost\fR. Specifying 0 disables +hoisting of simple expressions. +.IP "\fBgcse-unrestricted-cost\fR" 4 +.IX Item "gcse-unrestricted-cost" +Cost, roughly measured as the cost of a single typical machine +instruction, at which \s-1GCSE\s0 optimizations do not constrain +the distance an expression can travel. This is currently +supported only in the code hoisting pass. The lesser the cost, +the more aggressive code hoisting is. Specifying 0 +allows all expressions to travel unrestricted distances. +.IP "\fBmax-hoist-depth\fR" 4 +.IX Item "max-hoist-depth" +The depth of search in the dominator tree for expressions to hoist. +This is used to avoid quadratic behavior in hoisting algorithm. +The value of 0 does not limit on the search, but may slow down compilation +of huge functions. +.IP "\fBmax-tail-merge-comparisons\fR" 4 +.IX Item "max-tail-merge-comparisons" +The maximum amount of similar bbs to compare a bb with. This is used to +avoid quadratic behavior in tree tail merging. +.IP "\fBmax-tail-merge-iterations\fR" 4 +.IX Item "max-tail-merge-iterations" +The maximum amount of iterations of the pass over the function. This is used to +limit compilation time in tree tail merging. +.IP "\fBstore-merging-allow-unaligned\fR" 4 +.IX Item "store-merging-allow-unaligned" +Allow the store merging pass to introduce unaligned stores if it is legal to +do so. +.IP "\fBmax-stores-to-merge\fR" 4 +.IX Item "max-stores-to-merge" +The maximum number of stores to attempt to merge into wider stores in the store +merging pass. +.IP "\fBmax-unrolled-insns\fR" 4 +.IX Item "max-unrolled-insns" +The maximum number of instructions that a loop may have to be unrolled. +If a loop is unrolled, this parameter also determines how many times +the loop code is unrolled. +.IP "\fBmax-average-unrolled-insns\fR" 4 +.IX Item "max-average-unrolled-insns" +The maximum number of instructions biased by probabilities of their execution +that a loop may have to be unrolled. If a loop is unrolled, +this parameter also determines how many times the loop code is unrolled. +.IP "\fBmax-unroll-times\fR" 4 +.IX Item "max-unroll-times" +The maximum number of unrollings of a single loop. +.IP "\fBmax-peeled-insns\fR" 4 +.IX Item "max-peeled-insns" +The maximum number of instructions that a loop may have to be peeled. +If a loop is peeled, this parameter also determines how many times +the loop code is peeled. +.IP "\fBmax-peel-times\fR" 4 +.IX Item "max-peel-times" +The maximum number of peelings of a single loop. +.IP "\fBmax-peel-branches\fR" 4 +.IX Item "max-peel-branches" +The maximum number of branches on the hot path through the peeled sequence. +.IP "\fBmax-completely-peeled-insns\fR" 4 +.IX Item "max-completely-peeled-insns" +The maximum number of insns of a completely peeled loop. +.IP "\fBmax-completely-peel-times\fR" 4 +.IX Item "max-completely-peel-times" +The maximum number of iterations of a loop to be suitable for complete peeling. +.IP "\fBmax-completely-peel-loop-nest-depth\fR" 4 +.IX Item "max-completely-peel-loop-nest-depth" +The maximum depth of a loop nest suitable for complete peeling. +.IP "\fBmax-unswitch-insns\fR" 4 +.IX Item "max-unswitch-insns" +The maximum number of insns of an unswitched loop. +.IP "\fBmax-unswitch-level\fR" 4 +.IX Item "max-unswitch-level" +The maximum number of branches unswitched in a single loop. +.IP "\fBlim-expensive\fR" 4 +.IX Item "lim-expensive" +The minimum cost of an expensive expression in the loop invariant motion. +.IP "\fBiv-consider-all-candidates-bound\fR" 4 +.IX Item "iv-consider-all-candidates-bound" +Bound on number of candidates for induction variables, below which +all candidates are considered for each use in induction variable +optimizations. If there are more candidates than this, +only the most relevant ones are considered to avoid quadratic time complexity. +.IP "\fBiv-max-considered-uses\fR" 4 +.IX Item "iv-max-considered-uses" +The induction variable optimizations give up on loops that contain more +induction variable uses. +.IP "\fBiv-always-prune-cand-set-bound\fR" 4 +.IX Item "iv-always-prune-cand-set-bound" +If the number of candidates in the set is smaller than this value, +always try to remove unnecessary ivs from the set +when adding a new one. +.IP "\fBavg-loop-niter\fR" 4 +.IX Item "avg-loop-niter" +Average number of iterations of a loop. +.IP "\fBdse-max-object-size\fR" 4 +.IX Item "dse-max-object-size" +Maximum size (in bytes) of objects tracked bytewise by dead store elimination. +Larger values may result in larger compilation times. +.IP "\fBdse-max-alias-queries-per-store\fR" 4 +.IX Item "dse-max-alias-queries-per-store" +Maximum number of queries into the alias oracle per store. +Larger values result in larger compilation times and may result in more +removed dead stores. +.IP "\fBscev-max-expr-size\fR" 4 +.IX Item "scev-max-expr-size" +Bound on size of expressions used in the scalar evolutions analyzer. +Large expressions slow the analyzer. +.IP "\fBscev-max-expr-complexity\fR" 4 +.IX Item "scev-max-expr-complexity" +Bound on the complexity of the expressions in the scalar evolutions analyzer. +Complex expressions slow the analyzer. +.IP "\fBmax-tree-if-conversion-phi-args\fR" 4 +.IX Item "max-tree-if-conversion-phi-args" +Maximum number of arguments in a \s-1PHI\s0 supported by \s-1TREE\s0 if conversion +unless the loop is marked with simd pragma. +.IP "\fBvect-max-version-for-alignment-checks\fR" 4 +.IX Item "vect-max-version-for-alignment-checks" +The maximum number of run-time checks that can be performed when +doing loop versioning for alignment in the vectorizer. +.IP "\fBvect-max-version-for-alias-checks\fR" 4 +.IX Item "vect-max-version-for-alias-checks" +The maximum number of run-time checks that can be performed when +doing loop versioning for alias in the vectorizer. +.IP "\fBvect-max-peeling-for-alignment\fR" 4 +.IX Item "vect-max-peeling-for-alignment" +The maximum number of loop peels to enhance access alignment +for vectorizer. Value \-1 means no limit. +.IP "\fBmax-iterations-to-track\fR" 4 +.IX Item "max-iterations-to-track" +The maximum number of iterations of a loop the brute-force algorithm +for analysis of the number of iterations of the loop tries to evaluate. +.IP "\fBhot-bb-count-ws-permille\fR" 4 +.IX Item "hot-bb-count-ws-permille" +A basic block profile count is considered hot if it contributes to +the given permillage (i.e. 0...1000) of the entire profiled execution. +.IP "\fBhot-bb-frequency-fraction\fR" 4 +.IX Item "hot-bb-frequency-fraction" +Select fraction of the entry block frequency of executions of basic block in +function given basic block needs to have to be considered hot. +.IP "\fBmax-predicted-iterations\fR" 4 +.IX Item "max-predicted-iterations" +The maximum number of loop iterations we predict statically. This is useful +in cases where a function contains a single loop with known bound and +another loop with unknown bound. +The known number of iterations is predicted correctly, while +the unknown number of iterations average to roughly 10. This means that the +loop without bounds appears artificially cold relative to the other one. +.IP "\fBbuiltin-expect-probability\fR" 4 +.IX Item "builtin-expect-probability" +Control the probability of the expression having the specified value. This +parameter takes a percentage (i.e. 0 ... 100) as input. +.IP "\fBbuiltin-string-cmp-inline-length\fR" 4 +.IX Item "builtin-string-cmp-inline-length" +The maximum length of a constant string for a builtin string cmp call +eligible for inlining. +.IP "\fBalign-threshold\fR" 4 +.IX Item "align-threshold" +Select fraction of the maximal frequency of executions of a basic block in +a function to align the basic block. +.IP "\fBalign-loop-iterations\fR" 4 +.IX Item "align-loop-iterations" +A loop expected to iterate at least the selected number of iterations is +aligned. +.IP "\fBtracer-dynamic-coverage\fR" 4 +.IX Item "tracer-dynamic-coverage" +.PD 0 +.IP "\fBtracer-dynamic-coverage-feedback\fR" 4 +.IX Item "tracer-dynamic-coverage-feedback" +.PD +This value is used to limit superblock formation once the given percentage of +executed instructions is covered. This limits unnecessary code size +expansion. +.Sp +The \fBtracer-dynamic-coverage-feedback\fR parameter +is used only when profile +feedback is available. The real profiles (as opposed to statically estimated +ones) are much less balanced allowing the threshold to be larger value. +.IP "\fBtracer-max-code-growth\fR" 4 +.IX Item "tracer-max-code-growth" +Stop tail duplication once code growth has reached given percentage. This is +a rather artificial limit, as most of the duplicates are eliminated later in +cross jumping, so it may be set to much higher values than is the desired code +growth. +.IP "\fBtracer-min-branch-ratio\fR" 4 +.IX Item "tracer-min-branch-ratio" +Stop reverse growth when the reverse probability of best edge is less than this +threshold (in percent). +.IP "\fBtracer-min-branch-probability\fR" 4 +.IX Item "tracer-min-branch-probability" +.PD 0 +.IP "\fBtracer-min-branch-probability-feedback\fR" 4 +.IX Item "tracer-min-branch-probability-feedback" +.PD +Stop forward growth if the best edge has probability lower than this +threshold. +.Sp +Similarly to \fBtracer-dynamic-coverage\fR two parameters are +provided. \fBtracer-min-branch-probability-feedback\fR is used for +compilation with profile feedback and \fBtracer-min-branch-probability\fR +compilation without. The value for compilation with profile feedback +needs to be more conservative (higher) in order to make tracer +effective. +.IP "\fBstack-clash-protection-guard-size\fR" 4 +.IX Item "stack-clash-protection-guard-size" +Specify the size of the operating system provided stack guard as +2 raised to \fInum\fR bytes. Higher values may reduce the +number of explicit probes, but a value larger than the operating system +provided guard will leave code vulnerable to stack clash style attacks. +.IP "\fBstack-clash-protection-probe-interval\fR" 4 +.IX Item "stack-clash-protection-probe-interval" +Stack clash protection involves probing stack space as it is allocated. This +param controls the maximum distance between probes into the stack as 2 raised +to \fInum\fR bytes. Higher values may reduce the number of explicit probes, but a value +larger than the operating system provided guard will leave code vulnerable to +stack clash style attacks. +.IP "\fBmax-cse-path-length\fR" 4 +.IX Item "max-cse-path-length" +The maximum number of basic blocks on path that \s-1CSE\s0 considers. +.IP "\fBmax-cse-insns\fR" 4 +.IX Item "max-cse-insns" +The maximum number of instructions \s-1CSE\s0 processes before flushing. +.IP "\fBggc-min-expand\fR" 4 +.IX Item "ggc-min-expand" +\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This +parameter specifies the minimum percentage by which the garbage +collector's heap should be allowed to expand between collections. +Tuning this may improve compilation speed; it has no effect on code +generation. +.Sp +The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when +\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\*(R"\s0 is +the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If +\&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower +bound of 30% is used. Setting this parameter and +\&\fBggc-min-heapsize\fR to zero causes a full collection to occur at +every opportunity. This is extremely slow, but can be useful for +debugging. +.IP "\fBggc-min-heapsize\fR" 4 +.IX Item "ggc-min-heapsize" +Minimum size of the garbage collector's heap before it begins bothering +to collect garbage. The first collection occurs after the heap expands +by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, +tuning this may improve compilation speed, and has no effect on code +generation. +.Sp +The default is the smaller of \s-1RAM/8, RLIMIT_RSS,\s0 or a limit that +tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but +with a lower bound of 4096 (four megabytes) and an upper bound of +131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a +particular platform, the lower bound is used. Setting this parameter +very large effectively disables garbage collection. Setting this +parameter and \fBggc-min-expand\fR to zero causes a full collection +to occur at every opportunity. +.IP "\fBmax-reload-search-insns\fR" 4 +.IX Item "max-reload-search-insns" +The maximum number of instruction reload should look backward for equivalent +register. Increasing values mean more aggressive optimization, making the +compilation time increase with probably slightly better performance. +.IP "\fBmax-cselib-memory-locations\fR" 4 +.IX Item "max-cselib-memory-locations" +The maximum number of memory locations cselib should take into account. +Increasing values mean more aggressive optimization, making the compilation time +increase with probably slightly better performance. +.IP "\fBmax-sched-ready-insns\fR" 4 +.IX Item "max-sched-ready-insns" +The maximum number of instructions ready to be issued the scheduler should +consider at any given time during the first scheduling pass. Increasing +values mean more thorough searches, making the compilation time increase +with probably little benefit. +.IP "\fBmax-sched-region-blocks\fR" 4 +.IX Item "max-sched-region-blocks" +The maximum number of blocks in a region to be considered for +interblock scheduling. +.IP "\fBmax-pipeline-region-blocks\fR" 4 +.IX Item "max-pipeline-region-blocks" +The maximum number of blocks in a region to be considered for +pipelining in the selective scheduler. +.IP "\fBmax-sched-region-insns\fR" 4 +.IX Item "max-sched-region-insns" +The maximum number of insns in a region to be considered for +interblock scheduling. +.IP "\fBmax-pipeline-region-insns\fR" 4 +.IX Item "max-pipeline-region-insns" +The maximum number of insns in a region to be considered for +pipelining in the selective scheduler. +.IP "\fBmin-spec-prob\fR" 4 +.IX Item "min-spec-prob" +The minimum probability (in percents) of reaching a source block +for interblock speculative scheduling. +.IP "\fBmax-sched-extend-regions-iters\fR" 4 +.IX Item "max-sched-extend-regions-iters" +The maximum number of iterations through \s-1CFG\s0 to extend regions. +A value of 0 disables region extensions. +.IP "\fBmax-sched-insn-conflict-delay\fR" 4 +.IX Item "max-sched-insn-conflict-delay" +The maximum conflict delay for an insn to be considered for speculative motion. +.IP "\fBsched-spec-prob-cutoff\fR" 4 +.IX Item "sched-spec-prob-cutoff" +The minimal probability of speculation success (in percents), so that +speculative insns are scheduled. +.IP "\fBsched-state-edge-prob-cutoff\fR" 4 +.IX Item "sched-state-edge-prob-cutoff" +The minimum probability an edge must have for the scheduler to save its +state across it. +.IP "\fBsched-mem-true-dep-cost\fR" 4 +.IX Item "sched-mem-true-dep-cost" +Minimal distance (in \s-1CPU\s0 cycles) between store and load targeting same +memory locations. +.IP "\fBselsched-max-lookahead\fR" 4 +.IX Item "selsched-max-lookahead" +The maximum size of the lookahead window of selective scheduling. It is a +depth of search for available instructions. +.IP "\fBselsched-max-sched-times\fR" 4 +.IX Item "selsched-max-sched-times" +The maximum number of times that an instruction is scheduled during +selective scheduling. This is the limit on the number of iterations +through which the instruction may be pipelined. +.IP "\fBselsched-insns-to-rename\fR" 4 +.IX Item "selsched-insns-to-rename" +The maximum number of best instructions in the ready list that are considered +for renaming in the selective scheduler. +.IP "\fBsms-min-sc\fR" 4 +.IX Item "sms-min-sc" +The minimum value of stage count that swing modulo scheduler +generates. +.IP "\fBmax-last-value-rtl\fR" 4 +.IX Item "max-last-value-rtl" +The maximum size measured as number of RTLs that can be recorded in an expression +in combiner for a pseudo register as last known value of that register. +.IP "\fBmax-combine-insns\fR" 4 +.IX Item "max-combine-insns" +The maximum number of instructions the \s-1RTL\s0 combiner tries to combine. +.IP "\fBinteger-share-limit\fR" 4 +.IX Item "integer-share-limit" +Small integer constants can use a shared data structure, reducing the +compiler's memory usage and increasing its speed. This sets the maximum +value of a shared integer constant. +.IP "\fBssp-buffer-size\fR" 4 +.IX Item "ssp-buffer-size" +The minimum size of buffers (i.e. arrays) that receive stack smashing +protection when \fB\-fstack\-protection\fR is used. +.IP "\fBmin-size-for-stack-sharing\fR" 4 +.IX Item "min-size-for-stack-sharing" +The minimum size of variables taking part in stack slot sharing when not +optimizing. +.IP "\fBmax-jump-thread-duplication-stmts\fR" 4 +.IX Item "max-jump-thread-duplication-stmts" +Maximum number of statements allowed in a block that needs to be +duplicated when threading jumps. +.IP "\fBmax-fields-for-field-sensitive\fR" 4 +.IX Item "max-fields-for-field-sensitive" +Maximum number of fields in a structure treated in +a field sensitive manner during pointer analysis. +.IP "\fBprefetch-latency\fR" 4 +.IX Item "prefetch-latency" +Estimate on average number of instructions that are executed before +prefetch finishes. The distance prefetched ahead is proportional +to this constant. Increasing this number may also lead to less +streams being prefetched (see \fBsimultaneous-prefetches\fR). +.IP "\fBsimultaneous-prefetches\fR" 4 +.IX Item "simultaneous-prefetches" +Maximum number of prefetches that can run at the same time. +.IP "\fBl1\-cache\-line\-size\fR" 4 +.IX Item "l1-cache-line-size" +The size of cache line in L1 data cache, in bytes. +.IP "\fBl1\-cache\-size\fR" 4 +.IX Item "l1-cache-size" +The size of L1 data cache, in kilobytes. +.IP "\fBl2\-cache\-size\fR" 4 +.IX Item "l2-cache-size" +The size of L2 data cache, in kilobytes. +.IP "\fBprefetch-dynamic-strides\fR" 4 +.IX Item "prefetch-dynamic-strides" +Whether the loop array prefetch pass should issue software prefetch hints +for strides that are non-constant. In some cases this may be +beneficial, though the fact the stride is non-constant may make it +hard to predict when there is clear benefit to issuing these hints. +.Sp +Set to 1 if the prefetch hints should be issued for non-constant +strides. Set to 0 if prefetch hints should be issued only for strides that +are known to be constant and below \fBprefetch-minimum-stride\fR. +.IP "\fBprefetch-minimum-stride\fR" 4 +.IX Item "prefetch-minimum-stride" +Minimum constant stride, in bytes, to start using prefetch hints for. If +the stride is less than this threshold, prefetch hints will not be issued. +.Sp +This setting is useful for processors that have hardware prefetchers, in +which case there may be conflicts between the hardware prefetchers and +the software prefetchers. If the hardware prefetchers have a maximum +stride they can handle, it should be used here to improve the use of +software prefetchers. +.Sp +A value of \-1 means we don't have a threshold and therefore +prefetch hints can be issued for any constant stride. +.Sp +This setting is only useful for strides that are known and constant. +.IP "\fBloop-interchange-max-num-stmts\fR" 4 +.IX Item "loop-interchange-max-num-stmts" +The maximum number of stmts in a loop to be interchanged. +.IP "\fBloop-interchange-stride-ratio\fR" 4 +.IX Item "loop-interchange-stride-ratio" +The minimum ratio between stride of two loops for interchange to be profitable. +.IP "\fBmin-insn-to-prefetch-ratio\fR" 4 +.IX Item "min-insn-to-prefetch-ratio" +The minimum ratio between the number of instructions and the +number of prefetches to enable prefetching in a loop. +.IP "\fBprefetch-min-insn-to-mem-ratio\fR" 4 +.IX Item "prefetch-min-insn-to-mem-ratio" +The minimum ratio between the number of instructions and the +number of memory references to enable prefetching in a loop. +.IP "\fBuse-canonical-types\fR" 4 +.IX Item "use-canonical-types" +Whether the compiler should use the \*(L"canonical\*(R" type system. +Should always be 1, which uses a more efficient internal +mechanism for comparing types in \*(C+ and Objective\-\*(C+. However, if +bugs in the canonical type system are causing compilation failures, +set this value to 0 to disable canonical types. +.IP "\fBswitch-conversion-max-branch-ratio\fR" 4 +.IX Item "switch-conversion-max-branch-ratio" +Switch initialization conversion refuses to create arrays that are +bigger than \fBswitch-conversion-max-branch-ratio\fR times the number of +branches in the switch. +.IP "\fBmax-partial-antic-length\fR" 4 +.IX Item "max-partial-antic-length" +Maximum length of the partial antic set computed during the tree +partial redundancy elimination optimization (\fB\-ftree\-pre\fR) when +optimizing at \fB\-O3\fR and above. For some sorts of source code +the enhanced partial redundancy elimination optimization can run away, +consuming all of the memory available on the host machine. This +parameter sets a limit on the length of the sets that are computed, +which prevents the runaway behavior. Setting a value of 0 for +this parameter allows an unlimited set length. +.IP "\fBrpo-vn-max-loop-depth\fR" 4 +.IX Item "rpo-vn-max-loop-depth" +Maximum loop depth that is value-numbered optimistically. +When the limit hits the innermost +\&\fIrpo-vn-max-loop-depth\fR loops and the outermost loop in the +loop nest are value-numbered optimistically and the remaining ones not. +.IP "\fBsccvn-max-alias-queries-per-access\fR" 4 +.IX Item "sccvn-max-alias-queries-per-access" +Maximum number of alias-oracle queries we perform when looking for +redundancies for loads and stores. If this limit is hit the search +is aborted and the load or store is not considered redundant. The +number of queries is algorithmically limited to the number of +stores on all paths from the load to the function entry. +.IP "\fBira-max-loops-num\fR" 4 +.IX Item "ira-max-loops-num" +\&\s-1IRA\s0 uses regional register allocation by default. If a function +contains more loops than the number given by this parameter, only at most +the given number of the most frequently-executed loops form regions +for regional register allocation. +.IP "\fBira-max-conflict-table-size\fR" 4 +.IX Item "ira-max-conflict-table-size" +Although \s-1IRA\s0 uses a sophisticated algorithm to compress the conflict +table, the table can still require excessive amounts of memory for +huge functions. If the conflict table for a function could be more +than the size in \s-1MB\s0 given by this parameter, the register allocator +instead uses a faster, simpler, and lower-quality +algorithm that does not require building a pseudo-register conflict table. +.IP "\fBira-loop-reserved-regs\fR" 4 +.IX Item "ira-loop-reserved-regs" +\&\s-1IRA\s0 can be used to evaluate more accurate register pressure in loops +for decisions to move loop invariants (see \fB\-O3\fR). The number +of available registers reserved for some other purposes is given +by this parameter. Default of the parameter +is the best found from numerous experiments. +.IP "\fBlra-inheritance-ebb-probability-cutoff\fR" 4 +.IX Item "lra-inheritance-ebb-probability-cutoff" +\&\s-1LRA\s0 tries to reuse values reloaded in registers in subsequent insns. +This optimization is called inheritance. \s-1EBB\s0 is used as a region to +do this optimization. The parameter defines a minimal fall-through +edge probability in percentage used to add \s-1BB\s0 to inheritance \s-1EBB\s0 in +\&\s-1LRA.\s0 The default value was chosen +from numerous runs of \s-1SPEC2000\s0 on x86\-64. +.IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 +.IX Item "loop-invariant-max-bbs-in-loop" +Loop invariant motion can be very expensive, both in compilation time and +in amount of needed compile-time memory, with very large loops. Loops +with more basic blocks than this parameter won't have loop invariant +motion optimization performed on them. +.IP "\fBloop-max-datarefs-for-datadeps\fR" 4 +.IX Item "loop-max-datarefs-for-datadeps" +Building data dependencies is expensive for very large loops. This +parameter limits the number of data references in loops that are +considered for data dependence analysis. These large loops are no +handled by the optimizations using loop data dependencies. +.IP "\fBmax-vartrack-size\fR" 4 +.IX Item "max-vartrack-size" +Sets a maximum number of hash table slots to use during variable +tracking dataflow analysis of any function. If this limit is exceeded +with variable tracking at assignments enabled, analysis for that +function is retried without it, after removing all debug insns from +the function. If the limit is exceeded even without debug insns, var +tracking analysis is completely disabled for the function. Setting +the parameter to zero makes it unlimited. +.IP "\fBmax-vartrack-expr-depth\fR" 4 +.IX Item "max-vartrack-expr-depth" +Sets a maximum number of recursion levels when attempting to map +variable names or debug temporaries to value expressions. This trades +compilation time for more complete debug information. If this is set too +low, value expressions that are available and could be represented in +debug information may end up not being used; setting this higher may +enable the compiler to find more complex debug expressions, but compile +time and memory use may grow. +.IP "\fBmax-debug-marker-count\fR" 4 +.IX Item "max-debug-marker-count" +Sets a threshold on the number of debug markers (e.g. begin stmt +markers) to avoid complexity explosion at inlining or expanding to \s-1RTL.\s0 +If a function has more such gimple stmts than the set limit, such stmts +will be dropped from the inlined copy of a function, and from its \s-1RTL\s0 +expansion. +.IP "\fBmin-nondebug-insn-uid\fR" 4 +.IX Item "min-nondebug-insn-uid" +Use uids starting at this parameter for nondebug insns. The range below +the parameter is reserved exclusively for debug insns created by +\&\fB\-fvar\-tracking\-assignments\fR, but debug insns may get +(non-overlapping) uids above it if the reserved range is exhausted. +.IP "\fBipa-sra-ptr-growth-factor\fR" 4 +.IX Item "ipa-sra-ptr-growth-factor" +IPA-SRA replaces a pointer to an aggregate with one or more new +parameters only when their cumulative size is less or equal to +\&\fBipa-sra-ptr-growth-factor\fR times the size of the original +pointer parameter. +.IP "\fBsra-max-scalarization-size-Ospeed\fR" 4 +.IX Item "sra-max-scalarization-size-Ospeed" +.PD 0 +.IP "\fBsra-max-scalarization-size-Osize\fR" 4 +.IX Item "sra-max-scalarization-size-Osize" +.PD +The two Scalar Reduction of Aggregates passes (\s-1SRA\s0 and IPA-SRA) aim to +replace scalar parts of aggregates with uses of independent scalar +variables. These parameters control the maximum size, in storage units, +of aggregate which is considered for replacement when compiling for +speed +(\fBsra-max-scalarization-size-Ospeed\fR) or size +(\fBsra-max-scalarization-size-Osize\fR) respectively. +.IP "\fBsra-max-propagations\fR" 4 +.IX Item "sra-max-propagations" +The maximum number of artificial accesses that Scalar Replacement of +Aggregates (\s-1SRA\s0) will track, per one local variable, in order to +facilitate copy propagation. +.IP "\fBtm-max-aggregate-size\fR" 4 +.IX Item "tm-max-aggregate-size" +When making copies of thread-local variables in a transaction, this +parameter specifies the size in bytes after which variables are +saved with the logging functions as opposed to save/restore code +sequence pairs. This option only applies when using +\&\fB\-fgnu\-tm\fR. +.IP "\fBgraphite-max-nb-scop-params\fR" 4 +.IX Item "graphite-max-nb-scop-params" +To avoid exponential effects in the Graphite loop transforms, the +number of parameters in a Static Control Part (SCoP) is bounded. +A value of zero can be used to lift +the bound. A variable whose value is unknown at compilation time and +defined outside a SCoP is a parameter of the SCoP. +.IP "\fBloop-block-tile-size\fR" 4 +.IX Item "loop-block-tile-size" +Loop blocking or strip mining transforms, enabled with +\&\fB\-floop\-block\fR or \fB\-floop\-strip\-mine\fR, strip mine each +loop in the loop nest by a given number of iterations. The strip +length can be changed using the \fBloop-block-tile-size\fR +parameter. +.IP "\fBipa-cp-value-list-size\fR" 4 +.IX Item "ipa-cp-value-list-size" +IPA-CP attempts to track all possible values and types passed to a function's +parameter in order to propagate them and perform devirtualization. +\&\fBipa-cp-value-list-size\fR is the maximum number of values and types it +stores per one formal parameter of a function. +.IP "\fBipa-cp-eval-threshold\fR" 4 +.IX Item "ipa-cp-eval-threshold" +IPA-CP calculates its own score of cloning profitability heuristics +and performs those cloning opportunities with scores that exceed +\&\fBipa-cp-eval-threshold\fR. +.IP "\fBipa-cp-recursion-penalty\fR" 4 +.IX Item "ipa-cp-recursion-penalty" +Percentage penalty the recursive functions will receive when they +are evaluated for cloning. +.IP "\fBipa-cp-single-call-penalty\fR" 4 +.IX Item "ipa-cp-single-call-penalty" +Percentage penalty functions containing a single call to another +function will receive when they are evaluated for cloning. +.IP "\fBipa-max-agg-items\fR" 4 +.IX Item "ipa-max-agg-items" +IPA-CP is also capable to propagate a number of scalar values passed +in an aggregate. \fBipa-max-agg-items\fR controls the maximum +number of such values per one parameter. +.IP "\fBipa-cp-loop-hint-bonus\fR" 4 +.IX Item "ipa-cp-loop-hint-bonus" +When IPA-CP determines that a cloning candidate would make the number +of iterations of a loop known, it adds a bonus of +\&\fBipa-cp-loop-hint-bonus\fR to the profitability score of +the candidate. +.IP "\fBipa-cp-array-index-hint-bonus\fR" 4 +.IX Item "ipa-cp-array-index-hint-bonus" +When IPA-CP determines that a cloning candidate would make the index of +an array access known, it adds a bonus of +\&\fBipa-cp-array-index-hint-bonus\fR to the profitability +score of the candidate. +.IP "\fBipa-max-aa-steps\fR" 4 +.IX Item "ipa-max-aa-steps" +During its analysis of function bodies, IPA-CP employs alias analysis +in order to track values pointed to by function parameters. In order +not spend too much time analyzing huge functions, it gives up and +consider all memory clobbered after examining +\&\fBipa-max-aa-steps\fR statements modifying memory. +.IP "\fBlto-partitions\fR" 4 +.IX Item "lto-partitions" +Specify desired number of partitions produced during \s-1WHOPR\s0 compilation. +The number of partitions should exceed the number of CPUs used for compilation. +.IP "\fBlto-min-partition\fR" 4 +.IX Item "lto-min-partition" +Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). +This prevents expenses of splitting very small programs into too many +partitions. +.IP "\fBlto-max-partition\fR" 4 +.IX Item "lto-max-partition" +Size of max partition for \s-1WHOPR\s0 (in estimated instructions). +to provide an upper bound for individual size of partition. +Meant to be used only with balanced partitioning. +.IP "\fBlto-max-streaming-parallelism\fR" 4 +.IX Item "lto-max-streaming-parallelism" +Maximal number of parallel processes used for \s-1LTO\s0 streaming. +.IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 +.IX Item "cxx-max-namespaces-for-diagnostic-help" +The maximum number of namespaces to consult for suggestions when \*(C+ +name lookup fails for an identifier. +.IP "\fBsink-frequency-threshold\fR" 4 +.IX Item "sink-frequency-threshold" +The maximum relative execution frequency (in percents) of the target block +relative to a statement's original block to allow statement sinking of a +statement. Larger numbers result in more aggressive statement sinking. +A small positive adjustment is applied for +statements with memory operands as those are even more profitable so sink. +.IP "\fBmax-stores-to-sink\fR" 4 +.IX Item "max-stores-to-sink" +The maximum number of conditional store pairs that can be sunk. Set to 0 +if either vectorization (\fB\-ftree\-vectorize\fR) or if-conversion +(\fB\-ftree\-loop\-if\-convert\fR) is disabled. +.IP "\fBallow-store-data-races\fR" 4 +.IX Item "allow-store-data-races" +Allow optimizers to introduce new data races on stores. +Set to 1 to allow, otherwise to 0. +.IP "\fBcase-values-threshold\fR" 4 +.IX Item "case-values-threshold" +The smallest number of different values for which it is best to use a +jump-table instead of a tree of conditional branches. If the value is +0, use the default for the machine. +.IP "\fBtree-reassoc-width\fR" 4 +.IX Item "tree-reassoc-width" +Set the maximum number of instructions executed in parallel in +reassociated tree. This parameter overrides target dependent +heuristics used by default if has non zero value. +.IP "\fBsched-pressure-algorithm\fR" 4 +.IX Item "sched-pressure-algorithm" +Choose between the two available implementations of +\&\fB\-fsched\-pressure\fR. Algorithm 1 is the original implementation +and is the more likely to prevent instructions from being reordered. +Algorithm 2 was designed to be a compromise between the relatively +conservative approach taken by algorithm 1 and the rather aggressive +approach taken by the default scheduler. It relies more heavily on +having a regular register file and accurate register pressure classes. +See \fIhaifa\-sched.c\fR in the \s-1GCC\s0 sources for more details. +.Sp +The default choice depends on the target. +.IP "\fBmax-slsr-cand-scan\fR" 4 +.IX Item "max-slsr-cand-scan" +Set the maximum number of existing candidates that are considered when +seeking a basis for a new straight-line strength reduction candidate. +.IP "\fBasan-globals\fR" 4 +.IX Item "asan-globals" +Enable buffer overflow detection for global objects. This kind +of protection is enabled by default if you are using +\&\fB\-fsanitize=address\fR option. +To disable global objects protection use \fB\-\-param asan\-globals=0\fR. +.IP "\fBasan-stack\fR" 4 +.IX Item "asan-stack" +Enable buffer overflow detection for stack objects. This kind of +protection is enabled by default when using \fB\-fsanitize=address\fR. +To disable stack protection use \fB\-\-param asan\-stack=0\fR option. +.IP "\fBasan-instrument-reads\fR" 4 +.IX Item "asan-instrument-reads" +Enable buffer overflow detection for memory reads. This kind of +protection is enabled by default when using \fB\-fsanitize=address\fR. +To disable memory reads protection use +\&\fB\-\-param asan\-instrument\-reads=0\fR. +.IP "\fBasan-instrument-writes\fR" 4 +.IX Item "asan-instrument-writes" +Enable buffer overflow detection for memory writes. This kind of +protection is enabled by default when using \fB\-fsanitize=address\fR. +To disable memory writes protection use +\&\fB\-\-param asan\-instrument\-writes=0\fR option. +.IP "\fBasan-memintrin\fR" 4 +.IX Item "asan-memintrin" +Enable detection for built-in functions. This kind of protection +is enabled by default when using \fB\-fsanitize=address\fR. +To disable built-in functions protection use +\&\fB\-\-param asan\-memintrin=0\fR. +.IP "\fBasan-use-after-return\fR" 4 +.IX Item "asan-use-after-return" +Enable detection of use-after-return. This kind of protection +is enabled by default when using the \fB\-fsanitize=address\fR option. +To disable it use \fB\-\-param asan\-use\-after\-return=0\fR. +.Sp +Note: By default the check is disabled at run time. To enable it, +add \f(CW\*(C`detect_stack_use_after_return=1\*(C'\fR to the environment variable +\&\fB\s-1ASAN_OPTIONS\s0\fR. +.IP "\fBasan-instrumentation-with-call-threshold\fR" 4 +.IX Item "asan-instrumentation-with-call-threshold" +If number of memory accesses in function being instrumented +is greater or equal to this number, use callbacks instead of inline checks. +E.g. to disable inline code use +\&\fB\-\-param asan\-instrumentation\-with\-call\-threshold=0\fR. +.IP "\fBuse-after-scope-direct-emission-threshold\fR" 4 +.IX Item "use-after-scope-direct-emission-threshold" +If the size of a local variable in bytes is smaller or equal to this +number, directly poison (or unpoison) shadow memory instead of using +run-time callbacks. +.IP "\fBmax-fsm-thread-path-insns\fR" 4 +.IX Item "max-fsm-thread-path-insns" +Maximum number of instructions to copy when duplicating blocks on a +finite state automaton jump thread path. +.IP "\fBmax-fsm-thread-length\fR" 4 +.IX Item "max-fsm-thread-length" +Maximum number of basic blocks on a finite state automaton jump thread +path. +.IP "\fBmax-fsm-thread-paths\fR" 4 +.IX Item "max-fsm-thread-paths" +Maximum number of new jump thread paths to create for a finite state +automaton. +.IP "\fBparloops-chunk-size\fR" 4 +.IX Item "parloops-chunk-size" +Chunk size of omp schedule for loops parallelized by parloops. +.IP "\fBparloops-schedule\fR" 4 +.IX Item "parloops-schedule" +Schedule type of omp schedule for loops parallelized by parloops (static, +dynamic, guided, auto, runtime). +.IP "\fBparloops-min-per-thread\fR" 4 +.IX Item "parloops-min-per-thread" +The minimum number of iterations per thread of an innermost parallelized +loop for which the parallelized variant is preferred over the single threaded +one. Note that for a parallelized loop nest the +minimum number of iterations of the outermost loop per thread is two. +.IP "\fBmax-ssa-name-query-depth\fR" 4 +.IX Item "max-ssa-name-query-depth" +Maximum depth of recursion when querying properties of \s-1SSA\s0 names in things +like fold routines. One level of recursion corresponds to following a +use-def chain. +.IP "\fBhsa-gen-debug-stores\fR" 4 +.IX Item "hsa-gen-debug-stores" +Enable emission of special debug stores within \s-1HSA\s0 kernels which are +then read and reported by libgomp plugin. Generation of these stores +is disabled by default, use \fB\-\-param hsa\-gen\-debug\-stores=1\fR to +enable it. +.IP "\fBmax-speculative-devirt-maydefs\fR" 4 +.IX Item "max-speculative-devirt-maydefs" +The maximum number of may-defs we analyze when looking for a must-def +specifying the dynamic type of an object that invokes a virtual call +we may be able to devirtualize speculatively. +.IP "\fBmax-vrp-switch-assertions\fR" 4 +.IX Item "max-vrp-switch-assertions" +The maximum number of assertions to add along the default edge of a switch +statement during \s-1VRP.\s0 +.IP "\fBunroll-jam-min-percent\fR" 4 +.IX Item "unroll-jam-min-percent" +The minimum percentage of memory references that must be optimized +away for the unroll-and-jam transformation to be considered profitable. +.IP "\fBunroll-jam-max-unroll\fR" 4 +.IX Item "unroll-jam-max-unroll" +The maximum number of times the outer loop should be unrolled by +the unroll-and-jam transformation. +.IP "\fBmax-rtl-if-conversion-unpredictable-cost\fR" 4 +.IX Item "max-rtl-if-conversion-unpredictable-cost" +Maximum permissible cost for the sequence that would be generated +by the \s-1RTL\s0 if-conversion pass for a branch that is considered unpredictable. +.IP "\fBmax-variable-expansions-in-unroller\fR" 4 +.IX Item "max-variable-expansions-in-unroller" +If \fB\-fvariable\-expansion\-in\-unroller\fR is used, the maximum number +of times that an individual variable will be expanded during loop unrolling. +.IP "\fBtracer-min-branch-probability-feedback\fR" 4 +.IX Item "tracer-min-branch-probability-feedback" +Stop forward growth if the probability of best edge is less than +this threshold (in percent). Used when profile feedback is available. +.IP "\fBpartial-inlining-entry-probability\fR" 4 +.IX Item "partial-inlining-entry-probability" +Maximum probability of the entry \s-1BB\s0 of split region +(in percent relative to entry \s-1BB\s0 of the function) +to make partial inlining happen. +.IP "\fBmax-tracked-strlens\fR" 4 +.IX Item "max-tracked-strlens" +Maximum number of strings for which strlen optimization pass will +track string lengths. +.IP "\fBgcse-after-reload-partial-fraction\fR" 4 +.IX Item "gcse-after-reload-partial-fraction" +The threshold ratio for performing partial redundancy +elimination after reload. +.IP "\fBgcse-after-reload-critical-fraction\fR" 4 +.IX Item "gcse-after-reload-critical-fraction" +The threshold ratio of critical edges execution count that +permit performing redundancy elimination after reload. +.IP "\fBmax-loop-header-insns\fR" 4 +.IX Item "max-loop-header-insns" +The maximum number of insns in loop header duplicated +by the copy loop headers pass. +.IP "\fBvect-epilogues-nomask\fR" 4 +.IX Item "vect-epilogues-nomask" +Enable loop epilogue vectorization using smaller vector size. +.IP "\fBslp-max-insns-in-bb\fR" 4 +.IX Item "slp-max-insns-in-bb" +Maximum number of instructions in basic block to be +considered for \s-1SLP\s0 vectorization. +.IP "\fBavoid-fma-max-bits\fR" 4 +.IX Item "avoid-fma-max-bits" +Maximum number of bits for which we avoid creating FMAs. +.IP "\fBsms-loop-average-count-threshold\fR" 4 +.IX Item "sms-loop-average-count-threshold" +A threshold on the average loop count considered by the swing modulo scheduler. +.IP "\fBsms-dfa-history\fR" 4 +.IX Item "sms-dfa-history" +The number of cycles the swing modulo scheduler considers when checking +conflicts using \s-1DFA.\s0 +.IP "\fBhot-bb-count-fraction\fR" 4 +.IX Item "hot-bb-count-fraction" +Select fraction of the maximal count of repetitions of basic block +in program given basic block needs +to have to be considered hot (used in non-LTO mode) +.IP "\fBmax-inline-insns-recursive-auto\fR" 4 +.IX Item "max-inline-insns-recursive-auto" +The maximum number of instructions non-inline function +can grow to via recursive inlining. +.IP "\fBgraphite-allow-codegen-errors\fR" 4 +.IX Item "graphite-allow-codegen-errors" +Whether codegen errors should be ICEs when \fB\-fchecking\fR. +.IP "\fBsms-max-ii-factor\fR" 4 +.IX Item "sms-max-ii-factor" +A factor for tuning the upper bound that swing modulo scheduler +uses for scheduling a loop. +.IP "\fBlra-max-considered-reload-pseudos\fR" 4 +.IX Item "lra-max-considered-reload-pseudos" +The max number of reload pseudos which are considered during +spilling a non-reload pseudo. +.IP "\fBmax-pow-sqrt-depth\fR" 4 +.IX Item "max-pow-sqrt-depth" +Maximum depth of sqrt chains to use when synthesizing exponentiation +by a real constant. +.IP "\fBmax-dse-active-local-stores\fR" 4 +.IX Item "max-dse-active-local-stores" +Maximum number of active local stores in \s-1RTL\s0 dead store elimination. +.IP "\fBasan-instrument-allocas\fR" 4 +.IX Item "asan-instrument-allocas" +Enable asan allocas/VLAs protection. +.IP "\fBmax-iterations-computation-cost\fR" 4 +.IX Item "max-iterations-computation-cost" +Bound on the cost of an expression to compute the number of iterations. +.IP "\fBmax-isl-operations\fR" 4 +.IX Item "max-isl-operations" +Maximum number of isl operations, 0 means unlimited. +.IP "\fBgraphite-max-arrays-per-scop\fR" 4 +.IX Item "graphite-max-arrays-per-scop" +Maximum number of arrays per scop. +.IP "\fBmax-vartrack-reverse-op-size\fR" 4 +.IX Item "max-vartrack-reverse-op-size" +Max. size of loc list for which reverse ops should be added. +.IP "\fBunlikely-bb-count-fraction\fR" 4 +.IX Item "unlikely-bb-count-fraction" +The minimum fraction of profile runs a given basic block execution count +must be not to be considered unlikely. +.IP "\fBtracer-dynamic-coverage-feedback\fR" 4 +.IX Item "tracer-dynamic-coverage-feedback" +The percentage of function, weighted by execution frequency, +that must be covered by trace formation. +Used when profile feedback is available. +.IP "\fBmax-inline-recursive-depth-auto\fR" 4 +.IX Item "max-inline-recursive-depth-auto" +The maximum depth of recursive inlining for non-inline functions. +.IP "\fBfsm-scale-path-stmts\fR" 4 +.IX Item "fsm-scale-path-stmts" +Scale factor to apply to the number of statements in a threading path +when comparing to the number of (scaled) blocks. +.IP "\fBfsm-maximum-phi-arguments\fR" 4 +.IX Item "fsm-maximum-phi-arguments" +Maximum number of arguments a \s-1PHI\s0 may have before the \s-1FSM\s0 threader +will not try to thread through its block. +.IP "\fBuninit-control-dep-attempts\fR" 4 +.IX Item "uninit-control-dep-attempts" +Maximum number of nested calls to search for control dependencies +during uninitialized variable analysis. +.IP "\fBindir-call-topn-profile\fR" 4 +.IX Item "indir-call-topn-profile" +Track top N target addresses in indirect-call profile. +.IP "\fBmax-once-peeled-insns\fR" 4 +.IX Item "max-once-peeled-insns" +The maximum number of insns of a peeled loop that rolls only once. +.IP "\fBsra-max-scalarization-size-Osize\fR" 4 +.IX Item "sra-max-scalarization-size-Osize" +Maximum size, in storage units, of an aggregate +which should be considered for scalarization when compiling for size. +.IP "\fBfsm-scale-path-blocks\fR" 4 +.IX Item "fsm-scale-path-blocks" +Scale factor to apply to the number of blocks in a threading path +when comparing to the number of (scaled) statements. +.IP "\fBsched-autopref-queue-depth\fR" 4 +.IX Item "sched-autopref-queue-depth" +Hardware autoprefetcher scheduler model control flag. +Number of lookahead cycles the model looks into; at ' +\&' only enable instruction sorting heuristic. +.IP "\fBloop-versioning-max-inner-insns\fR" 4 +.IX Item "loop-versioning-max-inner-insns" +The maximum number of instructions that an inner loop can have +before the loop versioning pass considers it too big to copy. +.IP "\fBloop-versioning-max-outer-insns\fR" 4 +.IX Item "loop-versioning-max-outer-insns" +The maximum number of instructions that an outer loop can have +before the loop versioning pass considers it too big to copy, +discounting any instructions in inner loops that directly benefit +from versioning. +.IP "\fBssa-name-def-chain-limit\fR" 4 +.IX Item "ssa-name-def-chain-limit" +The maximum number of \s-1SSA_NAME\s0 assignments to follow in determining +a property of a variable such as its value. This limits the number +of iterations or recursive calls \s-1GCC\s0 performs when optimizing certain +statements or when determining their validity prior to issuing +diagnostics. +.RE +.RS 4 +.RE +.SS "Program Instrumentation Options" +.IX Subsection "Program Instrumentation Options" +\&\s-1GCC\s0 supports a number of command-line options that control adding +run-time instrumentation to the code it normally generates. +For example, one purpose of instrumentation is collect profiling +statistics for use in finding program hot spots, code coverage +analysis, or profile-guided optimizations. +Another class of program instrumentation is adding run-time checking +to detect programming errors like invalid pointer +dereferences or out-of-bounds array accesses, as well as deliberately +hostile attacks such as stack smashing or \*(C+ vtable hijacking. +There is also a general hook which can be used to implement other +forms of tracing or function-level instrumentation for debug or +program analysis purposes. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-pg\fR" 4 +.IX Item "-pg" +.PD +Generate extra code to write profile information suitable for the +analysis program \fBprof\fR (for \fB\-p\fR) or \fBgprof\fR +(for \fB\-pg\fR). You must use this option when compiling +the source files you want data about, and you must also use it when +linking. +.Sp +You can use the function attribute \f(CW\*(C`no_instrument_function\*(C'\fR to +suppress profiling of individual functions when compiling with these options. +.IP "\fB\-fprofile\-arcs\fR" 4 +.IX Item "-fprofile-arcs" +Add code so that program flow \fIarcs\fR are instrumented. During +execution the program records how many times each branch and call is +executed and how many times it is taken or returns. On targets that support +constructors with priority support, profiling properly handles constructors, +destructors and \*(C+ constructors (and destructors) of classes which are used +as a type of a global variable. +.Sp +When the compiled +program exits it saves this data to a file called +\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for +profile-directed optimizations (\fB\-fbranch\-probabilities\fR), or for +test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's +\&\fIauxname\fR is generated from the name of the output file, if +explicitly specified and it is not the final executable, otherwise it is +the basename of the source file. In both cases any suffix is removed +(e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or +\&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR). +.IP "\fB\-\-coverage\fR" 4 +.IX Item "--coverage" +This option is used to compile and link code instrumented for coverage +analysis. The option is a synonym for \fB\-fprofile\-arcs\fR +\&\fB\-ftest\-coverage\fR (when compiling) and \fB\-lgcov\fR (when +linking). See the documentation for those options for more details. +.RS 4 +.IP "*" 4 +Compile the source files with \fB\-fprofile\-arcs\fR plus optimization +and code generation options. For test coverage analysis, use the +additional \fB\-ftest\-coverage\fR option. You do not need to profile +every source file in a program. +.IP "*" 4 +Compile the source files additionally with \fB\-fprofile\-abs\-path\fR +to create absolute path names in the \fI.gcno\fR files. This allows +\&\fBgcov\fR to find the correct sources in projects where compilations +occur with different working directories. +.IP "*" 4 +Link your object files with \fB\-lgcov\fR or \fB\-fprofile\-arcs\fR +(the latter implies the former). +.IP "*" 4 +Run the program on a representative workload to generate the arc profile +information. This may be repeated any number of times. You can run +concurrent instances of your program, and provided that the file system +supports locking, the data files will be correctly updated. Unless +a strict \s-1ISO C\s0 dialect option is in effect, \f(CW\*(C`fork\*(C'\fR calls are +detected and correctly handled without double counting. +.IP "*" 4 +For profile-directed optimizations, compile the source files again with +the same optimization and code generation options plus +\&\fB\-fbranch\-probabilities\fR. +.IP "*" 4 +For test coverage analysis, use \fBgcov\fR to produce human readable +information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the +\&\fBgcov\fR documentation for further information. +.RE +.RS 4 +.Sp +With \fB\-fprofile\-arcs\fR, for each function of your program \s-1GCC\s0 +creates a program flow graph, then finds a spanning tree for the graph. +Only arcs that are not on the spanning tree have to be instrumented: the +compiler adds code to count the number of times that these arcs are +executed. When an arc is the only exit or only entrance to a block, the +instrumentation code can be added to the block; otherwise, a new basic +block must be created to hold the instrumentation code. +.RE +.IP "\fB\-ftest\-coverage\fR" 4 +.IX Item "-ftest-coverage" +Produce a notes file that the \fBgcov\fR code-coverage utility can use to +show program coverage. Each source file's note file is called +\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option +above for a description of \fIauxname\fR and instructions on how to +generate test coverage data. Coverage data matches the source files +more closely if you do not optimize. +.IP "\fB\-fprofile\-abs\-path\fR" 4 +.IX Item "-fprofile-abs-path" +Automatically convert relative source file names to absolute path names +in the \fI.gcno\fR files. This allows \fBgcov\fR to find the correct +sources in projects where compilations occur with different working +directories. +.IP "\fB\-fprofile\-dir=\fR\fIpath\fR" 4 +.IX Item "-fprofile-dir=path" +Set the directory to search for the profile data files in to \fIpath\fR. +This option affects only the profile data generated by +\&\fB\-fprofile\-generate\fR, \fB\-ftest\-coverage\fR, \fB\-fprofile\-arcs\fR +and used by \fB\-fprofile\-use\fR and \fB\-fbranch\-probabilities\fR +and its related options. Both absolute and relative paths can be used. +By default, \s-1GCC\s0 uses the current directory as \fIpath\fR, thus the +profile data file appears in the same directory as the object file. +In order to prevent the file name clashing, if the object file name is +not an absolute path, we mangle the absolute path of the +\&\fI\fIsourcename\fI.gcda\fR file and use it as the file name of a +\&\fI.gcda\fR file. +.Sp +When an executable is run in a massive parallel environment, it is recommended +to save profile to different folders. That can be done with variables +in \fIpath\fR that are exported during run-time: +.RS 4 +.IP "\fB\f(CB%p\fB\fR" 4 +.IX Item "%p" +process \s-1ID.\s0 +.IP "\fB\f(CB%q\fB{\s-1VAR\s0}\fR" 4 +.IX Item "%q{VAR}" +value of environment variable \fI\s-1VAR\s0\fR +.RE +.RS 4 +.RE +.IP "\fB\-fprofile\-generate\fR" 4 +.IX Item "-fprofile-generate" +.PD 0 +.IP "\fB\-fprofile\-generate=\fR\fIpath\fR" 4 +.IX Item "-fprofile-generate=path" +.PD +Enable options usually used for instrumenting application to produce +profile useful for later recompilation with profile feedback based +optimization. You must use \fB\-fprofile\-generate\fR both when +compiling and when linking your program. +.Sp +The following options are enabled: +\&\fB\-fprofile\-arcs\fR, \fB\-fprofile\-values\fR, +\&\fB\-finline\-functions\fR, and \fB\-fipa\-bit\-cp\fR. +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 looks at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.Sp +To optimize the program based on the collected profile information, use +\&\fB\-fprofile\-use\fR. +.IP "\fB\-fprofile\-update=\fR\fImethod\fR" 4 +.IX Item "-fprofile-update=method" +Alter the update method for an application instrumented for profile +feedback based optimization. The \fImethod\fR argument should be one of +\&\fBsingle\fR, \fBatomic\fR or \fBprefer-atomic\fR. +The first one is useful for single-threaded applications, +while the second one prevents profile corruption by emitting thread-safe code. +.Sp +\&\fBWarning:\fR When an application does not properly join all threads +(or creates an detached thread), a profile file can be still corrupted. +.Sp +Using \fBprefer-atomic\fR would be transformed either to \fBatomic\fR, +when supported by a target, or to \fBsingle\fR otherwise. The \s-1GCC\s0 driver +automatically selects \fBprefer-atomic\fR when \fB\-pthread\fR +is present in the command line. +.IP "\fB\-fprofile\-filter\-files=\fR\fIregex\fR" 4 +.IX Item "-fprofile-filter-files=regex" +Instrument only functions from files where names match +any regular expression (separated by a semi-colon). +.Sp +For example, \fB\-fprofile\-filter\-files=main.c;module.*.c\fR will instrument +only \fImain.c\fR and all C files starting with 'module'. +.IP "\fB\-fprofile\-exclude\-files=\fR\fIregex\fR" 4 +.IX Item "-fprofile-exclude-files=regex" +Instrument only functions from files where names do not match +all the regular expressions (separated by a semi-colon). +.Sp +For example, \fB\-fprofile\-exclude\-files=/usr/*\fR will prevent instrumentation +of all files that are located in \fI/usr/\fR folder. +.IP "\fB\-fsanitize=address\fR" 4 +.IX Item "-fsanitize=address" +Enable AddressSanitizer, a fast memory error detector. +Memory access instructions are instrumented to detect +out-of-bounds and use-after-free bugs. +The option enables \fB\-fsanitize\-address\-use\-after\-scope\fR. +See <\fBhttps://github.com/google/sanitizers/wiki/AddressSanitizer\fR> for +more details. The run-time behavior can be influenced using the +\&\fB\s-1ASAN_OPTIONS\s0\fR environment variable. When set to \f(CW\*(C`help=1\*(C'\fR, +the available options are shown at startup of the instrumented program. See +<\fBhttps://github.com/google/sanitizers/wiki/AddressSanitizerFlags#run\-time\-flags\fR> +for a list of supported options. +The option cannot be combined with \fB\-fsanitize=thread\fR. +.IP "\fB\-fsanitize=kernel\-address\fR" 4 +.IX Item "-fsanitize=kernel-address" +Enable AddressSanitizer for Linux kernel. +See <\fBhttps://github.com/google/kasan/wiki\fR> for more details. +.IP "\fB\-fsanitize=pointer\-compare\fR" 4 +.IX Item "-fsanitize=pointer-compare" +Instrument comparison operation (<, <=, >, >=) with pointer operands. +The option must be combined with either \fB\-fsanitize=kernel\-address\fR or +\&\fB\-fsanitize=address\fR +The option cannot be combined with \fB\-fsanitize=thread\fR. +Note: By default the check is disabled at run time. To enable it, +add \f(CW\*(C`detect_invalid_pointer_pairs=2\*(C'\fR to the environment variable +\&\fB\s-1ASAN_OPTIONS\s0\fR. Using \f(CW\*(C`detect_invalid_pointer_pairs=1\*(C'\fR detects +invalid operation only when both pointers are non-null. +.IP "\fB\-fsanitize=pointer\-subtract\fR" 4 +.IX Item "-fsanitize=pointer-subtract" +Instrument subtraction with pointer operands. +The option must be combined with either \fB\-fsanitize=kernel\-address\fR or +\&\fB\-fsanitize=address\fR +The option cannot be combined with \fB\-fsanitize=thread\fR. +Note: By default the check is disabled at run time. To enable it, +add \f(CW\*(C`detect_invalid_pointer_pairs=2\*(C'\fR to the environment variable +\&\fB\s-1ASAN_OPTIONS\s0\fR. Using \f(CW\*(C`detect_invalid_pointer_pairs=1\*(C'\fR detects +invalid operation only when both pointers are non-null. +.IP "\fB\-fsanitize=thread\fR" 4 +.IX Item "-fsanitize=thread" +Enable ThreadSanitizer, a fast data race detector. +Memory access instructions are instrumented to detect +data race bugs. See <\fBhttps://github.com/google/sanitizers/wiki#threadsanitizer\fR> for more +details. The run-time behavior can be influenced using the \fB\s-1TSAN_OPTIONS\s0\fR +environment variable; see +<\fBhttps://github.com/google/sanitizers/wiki/ThreadSanitizerFlags\fR> for a list of +supported options. +The option cannot be combined with \fB\-fsanitize=address\fR, +\&\fB\-fsanitize=leak\fR. +.Sp +Note that sanitized atomic builtins cannot throw exceptions when +operating on invalid memory addresses with non-call exceptions +(\fB\-fnon\-call\-exceptions\fR). +.IP "\fB\-fsanitize=leak\fR" 4 +.IX Item "-fsanitize=leak" +Enable LeakSanitizer, a memory leak detector. +This option only matters for linking of executables and +the executable is linked against a library that overrides \f(CW\*(C`malloc\*(C'\fR +and other allocator functions. See +<\fBhttps://github.com/google/sanitizers/wiki/AddressSanitizerLeakSanitizer\fR> for more +details. The run-time behavior can be influenced using the +\&\fB\s-1LSAN_OPTIONS\s0\fR environment variable. +The option cannot be combined with \fB\-fsanitize=thread\fR. +.IP "\fB\-fsanitize=undefined\fR" 4 +.IX Item "-fsanitize=undefined" +Enable UndefinedBehaviorSanitizer, a fast undefined behavior detector. +Various computations are instrumented to detect undefined behavior +at runtime. See <\fBhttps://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html\fR> for more details. The run-time behavior can be influenced using the +\&\fB\s-1UBSAN_OPTIONS\s0\fR environment variable. Current suboptions are: +.RS 4 +.IP "\fB\-fsanitize=shift\fR" 4 +.IX Item "-fsanitize=shift" +This option enables checking that the result of a shift operation is +not undefined. Note that what exactly is considered undefined differs +slightly between C and \*(C+, as well as between \s-1ISO C90\s0 and C99, etc. +This option has two suboptions, \fB\-fsanitize=shift\-base\fR and +\&\fB\-fsanitize=shift\-exponent\fR. +.IP "\fB\-fsanitize=shift\-exponent\fR" 4 +.IX Item "-fsanitize=shift-exponent" +This option enables checking that the second argument of a shift operation +is not negative and is smaller than the precision of the promoted first +argument. +.IP "\fB\-fsanitize=shift\-base\fR" 4 +.IX Item "-fsanitize=shift-base" +If the second argument of a shift operation is within range, check that the +result of a shift operation is not undefined. Note that what exactly is +considered undefined differs slightly between C and \*(C+, as well as between +\&\s-1ISO C90\s0 and C99, etc. +.IP "\fB\-fsanitize=integer\-divide\-by\-zero\fR" 4 +.IX Item "-fsanitize=integer-divide-by-zero" +Detect integer division by zero as well as \f(CW\*(C`INT_MIN / \-1\*(C'\fR division. +.IP "\fB\-fsanitize=unreachable\fR" 4 +.IX Item "-fsanitize=unreachable" +With this option, the compiler turns the \f(CW\*(C`_\|_builtin_unreachable\*(C'\fR +call into a diagnostics message call instead. When reaching the +\&\f(CW\*(C`_\|_builtin_unreachable\*(C'\fR call, the behavior is undefined. +.IP "\fB\-fsanitize=vla\-bound\fR" 4 +.IX Item "-fsanitize=vla-bound" +This option instructs the compiler to check that the size of a variable +length array is positive. +.IP "\fB\-fsanitize=null\fR" 4 +.IX Item "-fsanitize=null" +This option enables pointer checking. Particularly, the application +built with this option turned on will issue an error message when it +tries to dereference a \s-1NULL\s0 pointer, or if a reference (possibly an +rvalue reference) is bound to a \s-1NULL\s0 pointer, or if a method is invoked +on an object pointed by a \s-1NULL\s0 pointer. +.IP "\fB\-fsanitize=return\fR" 4 +.IX Item "-fsanitize=return" +This option enables return statement checking. Programs +built with this option turned on will issue an error message +when the end of a non-void function is reached without actually +returning a value. This option works in \*(C+ only. +.IP "\fB\-fsanitize=signed\-integer\-overflow\fR" 4 +.IX Item "-fsanitize=signed-integer-overflow" +This option enables signed integer overflow checking. We check that +the result of \f(CW\*(C`+\*(C'\fR, \f(CW\*(C`*\*(C'\fR, and both unary and binary \f(CW\*(C`\-\*(C'\fR +does not overflow in the signed arithmetics. Note, integer promotion +rules must be taken into account. That is, the following is not an +overflow: +.Sp +.Vb 2 +\& signed char a = SCHAR_MAX; +\& a++; +.Ve +.IP "\fB\-fsanitize=bounds\fR" 4 +.IX Item "-fsanitize=bounds" +This option enables instrumentation of array bounds. Various out of bounds +accesses are detected. Flexible array members, flexible array member-like +arrays, and initializers of variables with static storage are not instrumented. +.IP "\fB\-fsanitize=bounds\-strict\fR" 4 +.IX Item "-fsanitize=bounds-strict" +This option enables strict instrumentation of array bounds. Most out of bounds +accesses are detected, including flexible array members and flexible array +member-like arrays. Initializers of variables with static storage are not +instrumented. +.IP "\fB\-fsanitize=alignment\fR" 4 +.IX Item "-fsanitize=alignment" +This option enables checking of alignment of pointers when they are +dereferenced, or when a reference is bound to insufficiently aligned target, +or when a method or constructor is invoked on insufficiently aligned object. +.IP "\fB\-fsanitize=object\-size\fR" 4 +.IX Item "-fsanitize=object-size" +This option enables instrumentation of memory references using the +\&\f(CW\*(C`_\|_builtin_object_size\*(C'\fR function. Various out of bounds pointer +accesses are detected. +.IP "\fB\-fsanitize=float\-divide\-by\-zero\fR" 4 +.IX Item "-fsanitize=float-divide-by-zero" +Detect floating-point division by zero. Unlike other similar options, +\&\fB\-fsanitize=float\-divide\-by\-zero\fR is not enabled by +\&\fB\-fsanitize=undefined\fR, since floating-point division by zero can +be a legitimate way of obtaining infinities and NaNs. +.IP "\fB\-fsanitize=float\-cast\-overflow\fR" 4 +.IX Item "-fsanitize=float-cast-overflow" +This option enables floating-point type to integer conversion checking. +We check that the result of the conversion does not overflow. +Unlike other similar options, \fB\-fsanitize=float\-cast\-overflow\fR is +not enabled by \fB\-fsanitize=undefined\fR. +This option does not work well with \f(CW\*(C`FE_INVALID\*(C'\fR exceptions enabled. +.IP "\fB\-fsanitize=nonnull\-attribute\fR" 4 +.IX Item "-fsanitize=nonnull-attribute" +This option enables instrumentation of calls, checking whether null values +are not passed to arguments marked as requiring a non-null value by the +\&\f(CW\*(C`nonnull\*(C'\fR function attribute. +.IP "\fB\-fsanitize=returns\-nonnull\-attribute\fR" 4 +.IX Item "-fsanitize=returns-nonnull-attribute" +This option enables instrumentation of return statements in functions +marked with \f(CW\*(C`returns_nonnull\*(C'\fR function attribute, to detect returning +of null values from such functions. +.IP "\fB\-fsanitize=bool\fR" 4 +.IX Item "-fsanitize=bool" +This option enables instrumentation of loads from bool. If a value other +than 0/1 is loaded, a run-time error is issued. +.IP "\fB\-fsanitize=enum\fR" 4 +.IX Item "-fsanitize=enum" +This option enables instrumentation of loads from an enum type. If +a value outside the range of values for the enum type is loaded, +a run-time error is issued. +.IP "\fB\-fsanitize=vptr\fR" 4 +.IX Item "-fsanitize=vptr" +This option enables instrumentation of \*(C+ member function calls, member +accesses and some conversions between pointers to base and derived classes, +to verify the referenced object has the correct dynamic type. +.IP "\fB\-fsanitize=pointer\-overflow\fR" 4 +.IX Item "-fsanitize=pointer-overflow" +This option enables instrumentation of pointer arithmetics. If the pointer +arithmetics overflows, a run-time error is issued. +.IP "\fB\-fsanitize=builtin\fR" 4 +.IX Item "-fsanitize=builtin" +This option enables instrumentation of arguments to selected builtin +functions. If an invalid value is passed to such arguments, a run-time +error is issued. E.g. passing 0 as the argument to \f(CW\*(C`_\|_builtin_ctz\*(C'\fR +or \f(CW\*(C`_\|_builtin_clz\*(C'\fR invokes undefined behavior and is diagnosed +by this option. +.RE +.RS 4 +.Sp +While \fB\-ftrapv\fR causes traps for signed overflows to be emitted, +\&\fB\-fsanitize=undefined\fR gives a diagnostic message. +This currently works only for the C family of languages. +.RE +.IP "\fB\-fno\-sanitize=all\fR" 4 +.IX Item "-fno-sanitize=all" +This option disables all previously enabled sanitizers. +\&\fB\-fsanitize=all\fR is not allowed, as some sanitizers cannot be used +together. +.IP "\fB\-fasan\-shadow\-offset=\fR\fInumber\fR" 4 +.IX Item "-fasan-shadow-offset=number" +This option forces \s-1GCC\s0 to use custom shadow offset in AddressSanitizer checks. +It is useful for experimenting with different shadow memory layouts in +Kernel AddressSanitizer. +.IP "\fB\-fsanitize\-sections=\fR\fIs1\fR\fB,\fR\fIs2\fR\fB,...\fR" 4 +.IX Item "-fsanitize-sections=s1,s2,..." +Sanitize global variables in selected user-defined sections. \fIsi\fR may +contain wildcards. +.IP "\fB\-fsanitize\-recover\fR[\fB=\fR\fIopts\fR]" 4 +.IX Item "-fsanitize-recover[=opts]" +\&\fB\-fsanitize\-recover=\fR controls error recovery mode for sanitizers +mentioned in comma-separated list of \fIopts\fR. Enabling this option +for a sanitizer component causes it to attempt to continue +running the program as if no error happened. This means multiple +runtime errors can be reported in a single program run, and the exit +code of the program may indicate success even when errors +have been reported. The \fB\-fno\-sanitize\-recover=\fR option +can be used to alter +this behavior: only the first detected error is reported +and program then exits with a non-zero exit code. +.Sp +Currently this feature only works for \fB\-fsanitize=undefined\fR (and its suboptions +except for \fB\-fsanitize=unreachable\fR and \fB\-fsanitize=return\fR), +\&\fB\-fsanitize=float\-cast\-overflow\fR, \fB\-fsanitize=float\-divide\-by\-zero\fR, +\&\fB\-fsanitize=bounds\-strict\fR, +\&\fB\-fsanitize=kernel\-address\fR and \fB\-fsanitize=address\fR. +For these sanitizers error recovery is turned on by default, +except \fB\-fsanitize=address\fR, for which this feature is experimental. +\&\fB\-fsanitize\-recover=all\fR and \fB\-fno\-sanitize\-recover=all\fR is also +accepted, the former enables recovery for all sanitizers that support it, +the latter disables recovery for all sanitizers that support it. +.Sp +Even if a recovery mode is turned on the compiler side, it needs to be also +enabled on the runtime library side, otherwise the failures are still fatal. +The runtime library defaults to \f(CW\*(C`halt_on_error=0\*(C'\fR for +ThreadSanitizer and UndefinedBehaviorSanitizer, while default value for +AddressSanitizer is \f(CW\*(C`halt_on_error=1\*(C'\fR. This can be overridden through +setting the \f(CW\*(C`halt_on_error\*(C'\fR flag in the corresponding environment variable. +.Sp +Syntax without an explicit \fIopts\fR parameter is deprecated. It is +equivalent to specifying an \fIopts\fR list of: +.Sp +.Vb 1 +\& undefined,float\-cast\-overflow,float\-divide\-by\-zero,bounds\-strict +.Ve +.IP "\fB\-fsanitize\-address\-use\-after\-scope\fR" 4 +.IX Item "-fsanitize-address-use-after-scope" +Enable sanitization of local variables to detect use-after-scope bugs. +The option sets \fB\-fstack\-reuse\fR to \fBnone\fR. +.IP "\fB\-fsanitize\-undefined\-trap\-on\-error\fR" 4 +.IX Item "-fsanitize-undefined-trap-on-error" +The \fB\-fsanitize\-undefined\-trap\-on\-error\fR option instructs the compiler to +report undefined behavior using \f(CW\*(C`_\|_builtin_trap\*(C'\fR rather than +a \f(CW\*(C`libubsan\*(C'\fR library routine. The advantage of this is that the +\&\f(CW\*(C`libubsan\*(C'\fR library is not needed and is not linked in, so this +is usable even in freestanding environments. +.IP "\fB\-fsanitize\-coverage=trace\-pc\fR" 4 +.IX Item "-fsanitize-coverage=trace-pc" +Enable coverage-guided fuzzing code instrumentation. +Inserts a call to \f(CW\*(C`_\|_sanitizer_cov_trace_pc\*(C'\fR into every basic block. +.IP "\fB\-fsanitize\-coverage=trace\-cmp\fR" 4 +.IX Item "-fsanitize-coverage=trace-cmp" +Enable dataflow guided fuzzing code instrumentation. +Inserts a call to \f(CW\*(C`_\|_sanitizer_cov_trace_cmp1\*(C'\fR, +\&\f(CW\*(C`_\|_sanitizer_cov_trace_cmp2\*(C'\fR, \f(CW\*(C`_\|_sanitizer_cov_trace_cmp4\*(C'\fR or +\&\f(CW\*(C`_\|_sanitizer_cov_trace_cmp8\*(C'\fR for integral comparison with both operands +variable or \f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp1\*(C'\fR, +\&\f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp2\*(C'\fR, +\&\f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp4\*(C'\fR or +\&\f(CW\*(C`_\|_sanitizer_cov_trace_const_cmp8\*(C'\fR for integral comparison with one +operand constant, \f(CW\*(C`_\|_sanitizer_cov_trace_cmpf\*(C'\fR or +\&\f(CW\*(C`_\|_sanitizer_cov_trace_cmpd\*(C'\fR for float or double comparisons and +\&\f(CW\*(C`_\|_sanitizer_cov_trace_switch\*(C'\fR for switch statements. +.IP "\fB\-fcf\-protection=\fR[\fBfull\fR|\fBbranch\fR|\fBreturn\fR|\fBnone\fR]" 4 +.IX Item "-fcf-protection=[full|branch|return|none]" +Enable code instrumentation of control-flow transfers to increase +program security by checking that target addresses of control-flow +transfer instructions (such as indirect function call, function return, +indirect jump) are valid. This prevents diverting the flow of control +to an unexpected target. This is intended to protect against such +threats as Return-oriented Programming (\s-1ROP\s0), and similarly +call/jmp\-oriented programming (\s-1COP/JOP\s0). +.Sp +The value \f(CW\*(C`branch\*(C'\fR tells the compiler to implement checking of +validity of control-flow transfer at the point of indirect branch +instructions, i.e. call/jmp instructions. The value \f(CW\*(C`return\*(C'\fR +implements checking of validity at the point of returning from a +function. The value \f(CW\*(C`full\*(C'\fR is an alias for specifying both +\&\f(CW\*(C`branch\*(C'\fR and \f(CW\*(C`return\*(C'\fR. The value \f(CW\*(C`none\*(C'\fR turns off +instrumentation. +.Sp +The macro \f(CW\*(C`_\|_CET_\|_\*(C'\fR is defined when \fB\-fcf\-protection\fR is +used. The first bit of \f(CW\*(C`_\|_CET_\|_\*(C'\fR is set to 1 for the value +\&\f(CW\*(C`branch\*(C'\fR and the second bit of \f(CW\*(C`_\|_CET_\|_\*(C'\fR is set to 1 for +the \f(CW\*(C`return\*(C'\fR. +.Sp +You can also use the \f(CW\*(C`nocf_check\*(C'\fR attribute to identify +which functions and calls should be skipped from instrumentation. +.Sp +Currently the x86 GNU/Linux target provides an implementation based +on Intel Control-flow Enforcement Technology (\s-1CET\s0) which works for +i686 processor or newer. +.IP "\fB\-fstack\-protector\fR" 4 +.IX Item "-fstack-protector" +Emit extra code to check for buffer overflows, such as stack smashing +attacks. This is done by adding a guard variable to functions with +vulnerable objects. This includes functions that call \f(CW\*(C`alloca\*(C'\fR, and +functions with buffers larger than 8 bytes. The guards are initialized +when a function is entered and then checked when the function exits. +If a guard check fails, an error message is printed and the program exits. +.IP "\fB\-fstack\-protector\-all\fR" 4 +.IX Item "-fstack-protector-all" +Like \fB\-fstack\-protector\fR except that all functions are protected. +.IP "\fB\-fstack\-protector\-strong\fR" 4 +.IX Item "-fstack-protector-strong" +Like \fB\-fstack\-protector\fR but includes additional functions to +be protected \-\-\- those that have local array definitions, or have +references to local frame addresses. +.IP "\fB\-fstack\-protector\-explicit\fR" 4 +.IX Item "-fstack-protector-explicit" +Like \fB\-fstack\-protector\fR but only protects those functions which +have the \f(CW\*(C`stack_protect\*(C'\fR attribute. +.IP "\fB\-fstack\-check\fR" 4 +.IX Item "-fstack-check" +Generate code to verify that you do not go beyond the boundary of the +stack. You should specify this flag if you are running in an +environment with multiple threads, but you only rarely need to specify it in +a single-threaded environment since stack overflow is automatically +detected on nearly all systems if there is only one stack. +.Sp +Note that this switch does not actually cause checking to be done; the +operating system or the language runtime must do that. The switch causes +generation of code to ensure that they see the stack being extended. +.Sp +You can additionally specify a string parameter: \fBno\fR means no +checking, \fBgeneric\fR means force the use of old-style checking, +\&\fBspecific\fR means use the best checking method and is equivalent +to bare \fB\-fstack\-check\fR. +.Sp +Old-style checking is a generic mechanism that requires no specific +target support in the compiler but comes with the following drawbacks: +.RS 4 +.IP "1." 4 +.IX Item "1." +Modified allocation strategy for large objects: they are always +allocated dynamically if their size exceeds a fixed threshold. Note this +may change the semantics of some code. +.IP "2." 4 +.IX Item "2." +Fixed limit on the size of the static frame of functions: when it is +topped by a particular function, stack checking is not reliable and +a warning is issued by the compiler. +.IP "3." 4 +.IX Item "3." +Inefficiency: because of both the modified allocation strategy and the +generic implementation, code performance is hampered. +.RE +.RS 4 +.Sp +Note that old-style stack checking is also the fallback method for +\&\fBspecific\fR if no target support has been added in the compiler. +.Sp +\&\fB\-fstack\-check=\fR is designed for Ada's needs to detect infinite recursion +and stack overflows. \fBspecific\fR is an excellent choice when compiling +Ada code. It is not generally sufficient to protect against stack-clash +attacks. To protect against those you want \fB\-fstack\-clash\-protection\fR. +.RE +.IP "\fB\-fstack\-clash\-protection\fR" 4 +.IX Item "-fstack-clash-protection" +Generate code to prevent stack clash style attacks. When this option is +enabled, the compiler will only allocate one page of stack space at a time +and each page is accessed immediately after allocation. Thus, it prevents +allocations from jumping over any stack guard page provided by the +operating system. +.Sp +Most targets do not fully support stack clash protection. However, on +those targets \fB\-fstack\-clash\-protection\fR will protect dynamic stack +allocations. \fB\-fstack\-clash\-protection\fR may also provide limited +protection for static stack allocations if the target supports +\&\fB\-fstack\-check=specific\fR. +.IP "\fB\-fstack\-limit\-register=\fR\fIreg\fR" 4 +.IX Item "-fstack-limit-register=reg" +.PD 0 +.IP "\fB\-fstack\-limit\-symbol=\fR\fIsym\fR" 4 +.IX Item "-fstack-limit-symbol=sym" +.IP "\fB\-fno\-stack\-limit\fR" 4 +.IX Item "-fno-stack-limit" +.PD +Generate code to ensure that the stack does not grow beyond a certain value, +either the value of a register or the address of a symbol. If a larger +stack is required, a signal is raised at run time. For most targets, +the signal is raised before the stack overruns the boundary, so +it is possible to catch the signal without taking special precautions. +.Sp +For instance, if the stack starts at absolute address \fB0x80000000\fR +and grows downwards, you can use the flags +\&\fB\-fstack\-limit\-symbol=_\|_stack_limit\fR and +\&\fB\-Wl,\-\-defsym,_\|_stack_limit=0x7ffe0000\fR to enforce a stack limit +of 128KB. Note that this may only work with the \s-1GNU\s0 linker. +.Sp +You can locally override stack limit checking by using the +\&\f(CW\*(C`no_stack_limit\*(C'\fR function attribute. +.IP "\fB\-fsplit\-stack\fR" 4 +.IX Item "-fsplit-stack" +Generate code to automatically split the stack before it overflows. +The resulting program has a discontiguous stack which can only +overflow if the program is unable to allocate any more memory. This +is most useful when running threaded programs, as it is no longer +necessary to calculate a good stack size to use for each thread. This +is currently only implemented for the x86 targets running +GNU/Linux. +.Sp +When code compiled with \fB\-fsplit\-stack\fR calls code compiled +without \fB\-fsplit\-stack\fR, there may not be much stack space +available for the latter code to run. If compiling all code, +including library code, with \fB\-fsplit\-stack\fR is not an option, +then the linker can fix up these calls so that the code compiled +without \fB\-fsplit\-stack\fR always has a large stack. Support for +this is implemented in the gold linker in \s-1GNU\s0 binutils release 2.21 +and later. +.IP "\fB\-fvtable\-verify=\fR[\fBstd\fR|\fBpreinit\fR|\fBnone\fR]" 4 +.IX Item "-fvtable-verify=[std|preinit|none]" +This option is only available when compiling \*(C+ code. +It turns on (or off, if using \fB\-fvtable\-verify=none\fR) the security +feature that verifies at run time, for every virtual call, that +the vtable pointer through which the call is made is valid for the type of +the object, and has not been corrupted or overwritten. If an invalid vtable +pointer is detected at run time, an error is reported and execution of the +program is immediately halted. +.Sp +This option causes run-time data structures to be built at program startup, +which are used for verifying the vtable pointers. +The options \fBstd\fR and \fBpreinit\fR +control the timing of when these data structures are built. In both cases the +data structures are built before execution reaches \f(CW\*(C`main\*(C'\fR. Using +\&\fB\-fvtable\-verify=std\fR causes the data structures to be built after +shared libraries have been loaded and initialized. +\&\fB\-fvtable\-verify=preinit\fR causes them to be built before shared +libraries have been loaded and initialized. +.Sp +If this option appears multiple times in the command line with different +values specified, \fBnone\fR takes highest priority over both \fBstd\fR and +\&\fBpreinit\fR; \fBpreinit\fR takes priority over \fBstd\fR. +.IP "\fB\-fvtv\-debug\fR" 4 +.IX Item "-fvtv-debug" +When used in conjunction with \fB\-fvtable\-verify=std\fR or +\&\fB\-fvtable\-verify=preinit\fR, causes debug versions of the +runtime functions for the vtable verification feature to be called. +This flag also causes the compiler to log information about which +vtable pointers it finds for each class. +This information is written to a file named \fIvtv_set_ptr_data.log\fR +in the directory named by the environment variable \fB\s-1VTV_LOGS_DIR\s0\fR +if that is defined or the current working directory otherwise. +.Sp +Note: This feature \fIappends\fR data to the log file. If you want a fresh log +file, be sure to delete any existing one. +.IP "\fB\-fvtv\-counts\fR" 4 +.IX Item "-fvtv-counts" +This is a debugging flag. When used in conjunction with +\&\fB\-fvtable\-verify=std\fR or \fB\-fvtable\-verify=preinit\fR, this +causes the compiler to keep track of the total number of virtual calls +it encounters and the number of verifications it inserts. It also +counts the number of calls to certain run-time library functions +that it inserts and logs this information for each compilation unit. +The compiler writes this information to a file named +\&\fIvtv_count_data.log\fR in the directory named by the environment +variable \fB\s-1VTV_LOGS_DIR\s0\fR if that is defined or the current working +directory otherwise. It also counts the size of the vtable pointer sets +for each class, and writes this information to \fIvtv_class_set_sizes.log\fR +in the same directory. +.Sp +Note: This feature \fIappends\fR data to the log files. To get fresh log +files, be sure to delete any existing ones. +.IP "\fB\-finstrument\-functions\fR" 4 +.IX Item "-finstrument-functions" +Generate instrumentation calls for entry and exit to functions. Just +after function entry and just before function exit, the following +profiling functions are called with the address of the current +function and its call site. (On some platforms, +\&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current +function, so the call site information may not be available to the +profiling functions otherwise.) +.Sp +.Vb 4 +\& void _\|_cyg_profile_func_enter (void *this_fn, +\& void *call_site); +\& void _\|_cyg_profile_func_exit (void *this_fn, +\& void *call_site); +.Ve +.Sp +The first argument is the address of the start of the current function, +which may be looked up exactly in the symbol table. +.Sp +This instrumentation is also done for functions expanded inline in other +functions. The profiling calls indicate where, conceptually, the +inline function is entered and exited. This means that addressable +versions of such functions must be available. If all your uses of a +function are expanded inline, this may mean an additional expansion of +code size. If you use \f(CW\*(C`extern inline\*(C'\fR in your C code, an +addressable version of such functions must be provided. (This is +normally the case anyway, but if you get lucky and the optimizer always +expands the functions inline, you might have gotten away without +providing static copies.) +.Sp +A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in +which case this instrumentation is not done. This can be used, for +example, for the profiling functions listed above, high-priority +interrupt routines, and any functions from which the profiling functions +cannot safely be called (perhaps signal handlers, if the profiling +routines generate output or allocate memory). +.IP "\fB\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-file-list=file,file,..." +Set the list of functions that are excluded from instrumentation (see +the description of \fB\-finstrument\-functions\fR). If the file that +contains a function definition matches with one of \fIfile\fR, then +that function is not instrumented. The match is done on substrings: +if the \fIfile\fR parameter is a substring of the file name, it is +considered to be a match. +.Sp +For example: +.Sp +.Vb 1 +\& \-finstrument\-functions\-exclude\-file\-list=/bits/stl,include/sys +.Ve +.Sp +excludes any inline function defined in files whose pathnames +contain \fI/bits/stl\fR or \fIinclude/sys\fR. +.Sp +If, for some reason, you want to include letter \fB,\fR in one of +\&\fIsym\fR, write \fB,\fR. For example, +\&\fB\-finstrument\-functions\-exclude\-file\-list=',,tmp'\fR +(note the single quote surrounding the option). +.IP "\fB\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-function-list=sym,sym,..." +This is similar to \fB\-finstrument\-functions\-exclude\-file\-list\fR, +but this option sets the list of function names to be excluded from +instrumentation. The function name to be matched is its user-visible +name, such as \f(CW\*(C`vector blah(const vector &)\*(C'\fR, not the +internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The +match is done on substrings: if the \fIsym\fR parameter is a substring +of the function name, it is considered to be a match. For C99 and \*(C+ +extended identifiers, the function name must be given in \s-1UTF\-8,\s0 not +using universal character names. +.IP "\fB\-fpatchable\-function\-entry=\fR\fIN\fR\fB[,\fR\fIM\fR\fB]\fR" 4 +.IX Item "-fpatchable-function-entry=N[,M]" +Generate \fIN\fR NOPs right at the beginning +of each function, with the function entry point before the \fIM\fRth \s-1NOP.\s0 +If \fIM\fR is omitted, it defaults to \f(CW0\fR so the +function entry points to the address just at the first \s-1NOP.\s0 +The \s-1NOP\s0 instructions reserve extra space which can be used to patch in +any desired instrumentation at run time, provided that the code segment +is writable. The amount of space is controllable indirectly via +the number of NOPs; the \s-1NOP\s0 instruction used corresponds to the instruction +emitted by the internal \s-1GCC\s0 back-end interface \f(CW\*(C`gen_nop\*(C'\fR. This behavior +is target-specific and may also depend on the architecture variant and/or +other compilation options. +.Sp +For run-time identification, the starting addresses of these areas, +which correspond to their respective function entries minus \fIM\fR, +are additionally collected in the \f(CW\*(C`_\|_patchable_function_entries\*(C'\fR +section of the resulting binary. +.Sp +Note that the value of \f(CW\*(C`_\|_attribute_\|_ ((patchable_function_entry +(N,M)))\*(C'\fR takes precedence over command-line option +\&\fB\-fpatchable\-function\-entry=N,M\fR. This can be used to increase +the area size or to remove it completely on a single function. +If \f(CW\*(C`N=0\*(C'\fR, no pad location is recorded. +.Sp +The \s-1NOP\s0 instructions are inserted at\-\-\-and maybe before, depending on +\&\fIM\fR\-\-\-the function entry address, even before the prologue. +.SS "Options Controlling the Preprocessor" +.IX Subsection "Options Controlling the Preprocessor" +These options control the C preprocessor, which is run on each C source +file before actual compilation. +.PP +If you use the \fB\-E\fR option, nothing is done except preprocessing. +Some of these options make sense only together with \fB\-E\fR because +they cause the preprocessor output to be unsuitable for actual +compilation. +.PP +In addition to the options listed here, there are a number of options +to control search paths for include files documented in +\&\fBDirectory Options\fR. +Options to control preprocessor diagnostics are listed in +\&\fBWarning Options\fR. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +Predefine \fIname\fR as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-D name=definition" +The contents of \fIdefinition\fR are tokenized and processed as if +they appeared during translation phase three in a \fB#define\fR +directive. In particular, the definition is truncated by +embedded newline characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like +program you may need to use the shell's quoting syntax to protect +characters such as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you should +quote the option. With \fBsh\fR and \fBcsh\fR, +\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they +are given on the command line. All \fB\-imacros\fR \fIfile\fR and +\&\fB\-include\fR \fIfile\fR options are processed after all +\&\fB\-D\fR and \fB\-U\fR options. +.IP "\fB\-U\fR \fIname\fR" 4 +.IX Item "-U name" +Cancel any previous definition of \fIname\fR, either built in or +provided with a \fB\-D\fR option. +.IP "\fB\-include\fR \fIfile\fR" 4 +.IX Item "-include file" +Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first +line of the primary source file. However, the first directory searched +for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR +the directory containing the main source file. If not found there, it +is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search +chain as normal. +.Sp +If multiple \fB\-include\fR options are given, the files are included +in the order they appear on the command line. +.IP "\fB\-imacros\fR \fIfile\fR" 4 +.IX Item "-imacros file" +Exactly like \fB\-include\fR, except that any output produced by +scanning \fIfile\fR is thrown away. Macros it defines remain defined. +This allows you to acquire all the macros from a header without also +processing its declarations. +.Sp +All files specified by \fB\-imacros\fR are processed before all files +specified by \fB\-include\fR. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. The +standard predefined macros remain defined. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Define additional macros required for using the \s-1POSIX\s0 threads library. +You should use this option consistently for both compilation and linking. +This option is supported on GNU/Linux targets, most other Unix derivatives, +and also on x86 Cygwin and MinGW targets. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +Instead of outputting the result of preprocessing, output a rule +suitable for \fBmake\fR describing the dependencies of the main +source file. The preprocessor outputs one \fBmake\fR rule containing +the object file name for that source file, a colon, and the names of all +the included files, including those coming from \fB\-include\fR or +\&\fB\-imacros\fR command-line options. +.Sp +Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the +object file name consists of the name of the source file with any +suffix replaced with object file suffix and with any leading directory +parts removed. If there are many included files then the rule is +split into several lines using \fB\e\fR\-newline. The rule has no +commands. +.Sp +This option does not suppress the preprocessor's debug output, such as +\&\fB\-dM\fR. To avoid mixing such debug output with the dependency +rules you should explicitly specify the dependency output file with +\&\fB\-MF\fR, or use an environment variable like +\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output +is still sent to the regular output stream as normal. +.Sp +Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses +warnings with an implicit \fB\-w\fR. +.IP "\fB\-MM\fR" 4 +.IX Item "-MM" +Like \fB\-M\fR but do not mention header files that are found in +system header directories, nor header files that are included, +directly or indirectly, from such a header. +.Sp +This implies that the choice of angle brackets or double quotes in an +\&\fB#include\fR directive does not in itself determine whether that +header appears in \fB\-MM\fR dependency output. +.IP "\fB\-MF\fR \fIfile\fR" 4 +.IX Item "-MF file" +When used with \fB\-M\fR or \fB\-MM\fR, specifies a +file to write the dependencies to. If no \fB\-MF\fR switch is given +the preprocessor sends the rules to the same place it would send +preprocessed output. +.Sp +When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, +\&\fB\-MF\fR overrides the default dependency output file. +.Sp +If \fIfile\fR is \fI\-\fR, then the dependencies are written to \fIstdout\fR. +.IP "\fB\-MG\fR" 4 +.IX Item "-MG" +In conjunction with an option such as \fB\-M\fR requesting +dependency generation, \fB\-MG\fR assumes missing header files are +generated files and adds them to the dependency list without raising +an error. The dependency filename is taken directly from the +\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR +also suppresses preprocessed output, as a missing header file renders +this useless. +.Sp +This feature is used in automatic updating of makefiles. +.IP "\fB\-MP\fR" 4 +.IX Item "-MP" +This option instructs \s-1CPP\s0 to add a phony target for each dependency +other than the main file, causing each to depend on nothing. These +dummy rules work around errors \fBmake\fR gives if you remove header +files without updating the \fIMakefile\fR to match. +.Sp +This is typical output: +.Sp +.Vb 1 +\& test.o: test.c test.h +\& +\& test.h: +.Ve +.IP "\fB\-MT\fR \fItarget\fR" 4 +.IX Item "-MT target" +Change the target of the rule emitted by dependency generation. By +default \s-1CPP\s0 takes the name of the main input file, deletes any +directory components and any file suffix such as \fB.c\fR, and +appends the platform's usual object suffix. The result is the target. +.Sp +An \fB\-MT\fR option sets the target to be exactly the string you +specify. If you want multiple targets, you can specify them as a single +argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. +.Sp +For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give +.Sp +.Vb 1 +\& $(objpfx)foo.o: foo.c +.Ve +.IP "\fB\-MQ\fR \fItarget\fR" 4 +.IX Item "-MQ target" +Same as \fB\-MT\fR, but it quotes any characters which are special to +Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives +.Sp +.Vb 1 +\& $$(objpfx)foo.o: foo.c +.Ve +.Sp +The default target is automatically quoted, as if it were given with +\&\fB\-MQ\fR. +.IP "\fB\-MD\fR" 4 +.IX Item "-MD" +\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that +\&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on +whether an \fB\-o\fR option is given. If it is, the driver uses its +argument but with a suffix of \fI.d\fR, otherwise it takes the name +of the input file, removes any directory components and suffix, and +applies a \fI.d\fR suffix. +.Sp +If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any +\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR +is understood to specify a target object file. +.Sp +Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate +a dependency output file as a side effect of the compilation process. +.IP "\fB\-MMD\fR" 4 +.IX Item "-MMD" +Like \fB\-MD\fR except mention only user header files, not system +header files. +.IP "\fB\-fpreprocessed\fR" 4 +.IX Item "-fpreprocessed" +Indicate to the preprocessor that the input file has already been +preprocessed. This suppresses things like macro expansion, trigraph +conversion, escaped newline splicing, and processing of most directives. +The preprocessor still recognizes and removes comments, so that you can +pass a file preprocessed with \fB\-C\fR to the compiler without +problems. In this mode the integrated preprocessor is little more than +a tokenizer for the front ends. +.Sp +\&\fB\-fpreprocessed\fR is implicit if the input file has one of the +extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the +extensions that \s-1GCC\s0 uses for preprocessed files created by +\&\fB\-save\-temps\fR. +.IP "\fB\-fdirectives\-only\fR" 4 +.IX Item "-fdirectives-only" +When preprocessing, handle directives, but do not expand macros. +.Sp +The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR +options. +.Sp +With \fB\-E\fR, preprocessing is limited to the handling of directives +such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other +preprocessor operations, such as macro expansion and trigraph +conversion are not performed. In addition, the \fB\-dD\fR option is +implicitly enabled. +.Sp +With \fB\-fpreprocessed\fR, predefinition of command line and most +builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are +contextually dependent, are handled normally. This enables compilation of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.Sp +With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for +\&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.IP "\fB\-fdollars\-in\-identifiers\fR" 4 +.IX Item "-fdollars-in-identifiers" +Accept \fB$\fR in identifiers. +.IP "\fB\-fextended\-identifiers\fR" 4 +.IX Item "-fextended-identifiers" +Accept universal character names in identifiers. This option is +enabled by default for C99 (and later C standard versions) and \*(C+. +.IP "\fB\-fno\-canonical\-system\-headers\fR" 4 +.IX Item "-fno-canonical-system-headers" +When preprocessing, do not shorten system header paths with canonicalization. +.IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 +.IX Item "-ftabstop=width" +Set the distance between tab stops. This helps the preprocessor report +correct column numbers in warnings or errors, even if tabs appear on the +line. If the value is less than 1 or greater than 100, the option is +ignored. The default is 8. +.IP "\fB\-ftrack\-macro\-expansion\fR[\fB=\fR\fIlevel\fR]" 4 +.IX Item "-ftrack-macro-expansion[=level]" +Track locations of tokens across macro expansions. This allows the +compiler to emit diagnostic about the current macro expansion stack +when a compilation error occurs in a macro expansion. Using this +option makes the preprocessor and the compiler consume more +memory. The \fIlevel\fR parameter can be used to choose the level of +precision of token location tracking thus decreasing the memory +consumption if necessary. Value \fB0\fR of \fIlevel\fR de-activates +this option. Value \fB1\fR tracks tokens locations in a +degraded mode for the sake of minimal memory overhead. In this mode +all tokens resulting from the expansion of an argument of a +function-like macro have the same location. Value \fB2\fR tracks +tokens locations completely. This value is the most memory hungry. +When this option is given no argument, the default parameter value is +\&\fB2\fR. +.Sp +Note that \f(CW\*(C`\-ftrack\-macro\-expansion=2\*(C'\fR is activated by default. +.IP "\fB\-fmacro\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fmacro-prefix-map=old=new" +When preprocessing files residing in directory \fI\fIold\fI\fR, +expand the \f(CW\*(C`_\|_FILE_\|_\*(C'\fR and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR macros as if the +files resided in directory \fI\fInew\fI\fR instead. This can be used +to change an absolute path to a relative path by using \fI.\fR for +\&\fInew\fR which can result in more reproducible builds that are +location independent. This option also affects +\&\f(CW\*(C`_\|_builtin_FILE()\*(C'\fR during compilation. See also +\&\fB\-ffile\-prefix\-map\fR. +.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fexec-charset=charset" +Set the execution character set, used for string and character +constants. The default is \s-1UTF\-8.\s0 \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fwide-exec-charset=charset" +Set the wide execution character set, used for wide string and +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16,\s0 whichever +corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with +\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported +by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have +problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. +.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 +.IX Item "-finput-charset=charset" +Set the input character set, used for translation from the character +set of the input file to the source character set used by \s-1GCC.\s0 If the +locale does not specify, or \s-1GCC\s0 cannot get this information from the +locale, the default is \s-1UTF\-8.\s0 This can be overridden by either the locale +or this command-line option. Currently the command-line option takes +precedence if there's a conflict. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fpch\-deps\fR" 4 +.IX Item "-fpch-deps" +When using precompiled headers, this flag +causes the dependency-output flags to also list the files from the +precompiled header's dependencies. If not specified, only the +precompiled header are listed and not the files that were used to +create it, because those files are not consulted when a precompiled +header is used. +.IP "\fB\-fpch\-preprocess\fR" 4 +.IX Item "-fpch-preprocess" +This option allows use of a precompiled header together with \fB\-E\fR. It inserts a special \f(CW\*(C`#pragma\*(C'\fR, +\&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark +the place where the precompiled header was found, and its \fIfilename\fR. +When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR +and loads the \s-1PCH.\s0 +.Sp +This option is off by default, because the resulting preprocessed output +is only really suitable as input to \s-1GCC.\s0 It is switched on by +\&\fB\-save\-temps\fR. +.Sp +You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is +safe to edit the filename if the \s-1PCH\s0 file is available in a different +location. The filename may be absolute or it may be relative to \s-1GCC\s0's +current directory. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor +emits, after the initial linemarker, a second linemarker with the +current working directory followed by two slashes. \s-1GCC\s0 uses this +directory, when it's present in the preprocessed input, as the +directory emitted as the current working directory in some debugging +information formats. This option is implicitly enabled if debugging +information is enabled, but this can be inhibited with the negated +form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is +present in the command line, this option has no effect, since no +\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. +.IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A predicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR +\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because +it does not use shell special characters. +.IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A -predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it +causes the preprocessor to treat comments as tokens in their own right. +For example, comments appearing at the start of what would be a +directive line have the effect of turning that line into an ordinary +source line, since the first token on the line is no longer a \fB#\fR. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is +like \fB\-C\fR, except that comments contained within macros are +also passed through to the output file where the macro is expanded. +.Sp +In addition to the side effects of the \fB\-C\fR option, the +\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro +to be converted to C\-style comments. This is to prevent later use +of that macro from inadvertently commenting out the remainder of +the source line. +.Sp +The \fB\-CC\fR option is generally used to support lint comments. +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that is +not C code, and will be sent to a program which might be confused by the +linemarkers. +.IP "\fB\-traditional\fR" 4 +.IX Item "-traditional" +.PD 0 +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +.PD +Try to imitate the behavior of pre-standard C preprocessors, as +opposed to \s-1ISO C\s0 preprocessors. +See the \s-1GNU CPP\s0 manual for details. +.Sp +Note that \s-1GCC\s0 does not otherwise attempt to emulate a pre-standard +C compiler, and these options are only supported with the \fB\-E\fR +switch, or when invoking \s-1CPP\s0 explicitly. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Support \s-1ISO C\s0 trigraphs. +These are three-character sequences, all starting with \fB??\fR, that +are defined by \s-1ISO C\s0 to stand for single characters. For example, +\&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character +constant for a newline. +.Sp +The nine trigraphs and their replacements are +.Sp +.Vb 2 +\& Trigraph: ??( ??) ??< ??> ??= ??/ ??\*(Aq ??! ??\- +\& Replacement: [ ] { } # \e ^ | ~ +.Ve +.Sp +By default, \s-1GCC\s0 ignores trigraphs, but in +standard-conforming modes it converts them. See the \fB\-std\fR and +\&\fB\-ansi\fR options. +.IP "\fB\-remap\fR" 4 +.IX Item "-remap" +Enable special code to work around file systems which only permit very +short file names, such as MS-DOS. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the +\&\fB#include\fR stack it is. Precompiled header files are also +printed, even if they are found to be invalid; an invalid precompiled +header file is printed with \fB...x\fR and a valid one with \fB...!\fR . +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +Says to make debugging dumps during compilation as specified by +\&\fIletters\fR. The flags documented here are those relevant to the +preprocessor. Other \fIletters\fR are interpreted +by the compiler proper, or reserved for future versions of \s-1GCC,\s0 and so +are silently ignored. If you specify \fIletters\fR whose behavior +conflicts, the result is undefined. +.RS 4 +.IP "\fB\-dM\fR" 4 +.IX Item "-dM" +Instead of the normal output, generate a list of \fB#define\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way of +finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.h\fR, the command +.Sp +.Vb 1 +\& touch foo.h; cpp \-dM foo.h +.Ve +.Sp +shows all the predefined macros. +.Sp +If you use \fB\-dM\fR without the \fB\-E\fR option, \fB\-dM\fR is +interpreted as a synonym for \fB\-fdump\-rtl\-mach\fR. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Like \fB\-dM\fR except in two respects: it does \fInot\fR include the +predefined macros, and it outputs \fIboth\fR the \fB#define\fR +directives and the result of preprocessing. Both kinds of output go to +the standard output file. +.IP "\fB\-dN\fR" 4 +.IX Item "-dN" +Like \fB\-dD\fR, but emit only the macro names, not their expansions. +.IP "\fB\-dI\fR" 4 +.IX Item "-dI" +Output \fB#include\fR directives in addition to the result of +preprocessing. +.IP "\fB\-dU\fR" 4 +.IX Item "-dU" +Like \fB\-dD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and +\&\fB#undef\fR directives are also output for macros tested but +undefined at the time. +.RE +.RS 4 +.RE +.IP "\fB\-fdebug\-cpp\fR" 4 +.IX Item "-fdebug-cpp" +This option is only useful for debugging \s-1GCC.\s0 When used from \s-1CPP\s0 or with +\&\fB\-E\fR, it dumps debugging information about location maps. Every +token in the output is preceded by the dump of the map its location +belongs to. +.Sp +When used from \s-1GCC\s0 without \fB\-E\fR, this option has no effect. +.IP "\fB\-Wp,\fR\fIoption\fR" 4 +.IX Item "-Wp,option" +You can use \fB\-Wp,\fR\fIoption\fR to bypass the compiler driver +and pass \fIoption\fR directly through to the preprocessor. If +\&\fIoption\fR contains commas, it is split into multiple options at the +commas. However, many options are modified, translated or interpreted +by the compiler driver before being passed to the preprocessor, and +\&\fB\-Wp\fR forcibly bypasses this phase. The preprocessor's direct +interface is undocumented and subject to change, so whenever possible +you should avoid using \fB\-Wp\fR and let the driver handle the +options instead. +.IP "\fB\-Xpreprocessor\fR \fIoption\fR" 4 +.IX Item "-Xpreprocessor option" +Pass \fIoption\fR as an option to the preprocessor. You can use this to +supply system-specific preprocessor options that \s-1GCC\s0 does not +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument. +.IP "\fB\-no\-integrated\-cpp\fR" 4 +.IX Item "-no-integrated-cpp" +Perform preprocessing as a separate pass before compilation. +By default, \s-1GCC\s0 performs preprocessing as an integrated part of +input tokenization and parsing. +If this option is provided, the appropriate language front end +(\fBcc1\fR, \fBcc1plus\fR, or \fBcc1obj\fR for C, \*(C+, +and Objective-C, respectively) is instead invoked twice, +once for preprocessing only and once for actual compilation +of the preprocessed input. +This option may be useful in conjunction with the \fB\-B\fR or +\&\fB\-wrapper\fR options to specify an alternate preprocessor or +perform additional processing of the program source between +normal preprocessing and compilation. +.SS "Passing Options to the Assembler" +.IX Subsection "Passing Options to the Assembler" +You can pass options to the assembler. +.IP "\fB\-Wa,\fR\fIoption\fR" 4 +.IX Item "-Wa,option" +Pass \fIoption\fR as an option to the assembler. If \fIoption\fR +contains commas, it is split into multiple options at the commas. +.IP "\fB\-Xassembler\fR \fIoption\fR" 4 +.IX Item "-Xassembler option" +Pass \fIoption\fR as an option to the assembler. You can use this to +supply system-specific assembler options that \s-1GCC\s0 does not +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xassembler\fR twice, once for the option and once for the argument. +.SS "Options for Linking" +.IX Subsection "Options for Linking" +These options come into play when the compiler links object files into +an executable output file. They are meaningless if the compiler is +not doing a link step. +.IP "\fIobject-file-name\fR" 4 +.IX Item "object-file-name" +A file name that does not end in a special recognized suffix is +considered to name an object file or library. (Object files are +distinguished from libraries by the linker according to the file +contents.) If linking is done, these object files are used as input +to the linker. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.IP "\fB\-E\fR" 4 +.IX Item "-E" +.PD +If any of these options is used, then the linker is not run, and +object file names should not be used as arguments. +.IP "\fB\-flinker\-output=\fR\fItype\fR" 4 +.IX Item "-flinker-output=type" +This option controls the code generation of the link time optimizer. By +default the linker output is determined by the linker plugin automatically. For +debugging the compiler and in the case of incremental linking to non-lto object +file is desired, it may be useful to control the type manually. +.Sp +If \fItype\fR is \fBexec\fR the code generation is configured to produce static +binary. In this case \fB\-fpic\fR and \fB\-fpie\fR are both disabled. +.Sp +If \fItype\fR is \fBdyn\fR the code generation is configured to produce shared +library. In this case \fB\-fpic\fR or \fB\-fPIC\fR is preserved, but not +enabled automatically. This makes it possible to build shared libraries without +position independent code on architectures this is possible, i.e. on x86. +.Sp +If \fItype\fR is \fBpie\fR the code generation is configured to produce +\&\fB\-fpie\fR executable. This result in similar optimizations as \fBexec\fR +except that \fB\-fpie\fR is not disabled if specified at compilation time. +.Sp +If \fItype\fR is \fBrel\fR the compiler assumes that incremental linking is +done. The sections containing intermediate code for link-time optimization are +merged, pre-optimized, and output to the resulting object file. In addition, if +\&\fB\-ffat\-lto\-objects\fR is specified the binary code is produced for future +non-lto linking. The object file produced by incremental linking will be smaller +than a static library produced from the same object files. At link-time the +result of incremental linking will also load faster to compiler than a static +library assuming that majority of objects in the library are used. +.Sp +Finally \fBnolto-rel\fR configure compiler to for incremental linking where +code generation is forced, final binary is produced and the intermediate code +for later link-time optimization is stripped. When multiple object files are +linked together the resulting code will be optimized better than with link time +optimizations disabled (for example, the cross-module inlining will happen), +most of benefits of whole program optimizations are however lost. +.Sp +During the incremental link (by \fB\-r\fR) the linker plugin will default to +\&\fBrel\fR. With current interfaces to \s-1GNU\s0 Binutils it is however not +possible to link incrementally \s-1LTO\s0 objects and non-LTO objects into a single +mixed object file. In the case any of object files in incremental link cannot +be used for link-time optimization the linker plugin will output warning and +use \fBnolto-rel\fR. To maintain the whole program optimization it is +recommended to link such objects into static library instead. Alternatively it +is possible to use H.J. Lu's binutils with support for mixed objects. +.IP "\fB\-fuse\-ld=bfd\fR" 4 +.IX Item "-fuse-ld=bfd" +Use the \fBbfd\fR linker instead of the default linker. +.IP "\fB\-fuse\-ld=gold\fR" 4 +.IX Item "-fuse-ld=gold" +Use the \fBgold\fR linker instead of the default linker. +.IP "\fB\-fuse\-ld=lld\fR" 4 +.IX Item "-fuse-ld=lld" +Use the \s-1LLVM\s0 \fBlld\fR linker instead of the default linker. +.IP "\fB\-l\fR\fIlibrary\fR" 4 +.IX Item "-llibrary" +.PD 0 +.IP "\fB\-l\fR \fIlibrary\fR" 4 +.IX Item "-l library" +.PD +Search the library named \fIlibrary\fR when linking. (The second +alternative with the library as a separate argument is only for +\&\s-1POSIX\s0 compliance and is not recommended.) +.Sp +The \fB\-l\fR option is passed directly to the linker by \s-1GCC.\s0 Refer +to your linker documentation for exact details. The general +description below applies to the \s-1GNU\s0 linker. +.Sp +The linker searches a standard list of directories for the library. +The directories searched include several standard system directories +plus any that you specify with \fB\-L\fR. +.Sp +Static libraries are archives of object files, and have file names +like \fIlib\fIlibrary\fI.a\fR. Some targets also support shared +libraries, which typically have names like \fIlib\fIlibrary\fI.so\fR. +If both static and shared libraries are found, the linker gives +preference to linking with the shared library unless the +\&\fB\-static\fR option is used. +.Sp +It makes a difference where in the command you write this option; the +linker searches and processes libraries and object files in the order they +are specified. Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR +after file \fIfoo.o\fR but before \fIbar.o\fR. If \fIbar.o\fR refers +to functions in \fBz\fR, those functions may not be loaded. +.IP "\fB\-lobjc\fR" 4 +.IX Item "-lobjc" +You need this special case of the \fB\-l\fR option in order to +link an Objective-C or Objective\-\*(C+ program. +.IP "\fB\-nostartfiles\fR" 4 +.IX Item "-nostartfiles" +Do not use the standard system startup files when linking. +The standard system libraries are used normally, unless \fB\-nostdlib\fR, +\&\fB\-nolibc\fR, or \fB\-nodefaultlibs\fR is used. +.IP "\fB\-nodefaultlibs\fR" 4 +.IX Item "-nodefaultlibs" +Do not use the standard system libraries when linking. +Only the libraries you specify are passed to the linker, and options +specifying linkage of the system libraries, such as \fB\-static\-libgcc\fR +or \fB\-shared\-libgcc\fR, are ignored. +The standard startup files are used normally, unless \fB\-nostartfiles\fR +is used. +.Sp +The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, +\&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.IP "\fB\-nolibc\fR" 4 +.IX Item "-nolibc" +Do not use the C library or system libraries tightly coupled with it when +linking. Still link with the startup files, \fIlibgcc\fR or toolchain +provided language support libraries such as \fIlibgnat\fR, \fIlibgfortran\fR +or \fIlibstdc++\fR unless options preventing their inclusion are used as +well. This typically removes \fB\-lc\fR from the link command line, as well +as system libraries that normally go with it and become meaningless when +absence of a C library is assumed, for example \fB\-lpthread\fR or +\&\fB\-lm\fR in some configurations. This is intended for bare-board +targets when there is indeed no C library available. +.IP "\fB\-nostdlib\fR" 4 +.IX Item "-nostdlib" +Do not use the standard system startup files or libraries when linking. +No startup files and only the libraries you specify are passed to +the linker, and options specifying linkage of the system libraries, such as +\&\fB\-static\-libgcc\fR or \fB\-shared\-libgcc\fR, are ignored. +.Sp +The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR, +\&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.Sp +One of the standard libraries bypassed by \fB\-nostdlib\fR and +\&\fB\-nodefaultlibs\fR is \fIlibgcc.a\fR, a library of internal subroutines +which \s-1GCC\s0 uses to overcome shortcomings of particular machines, or special +needs for some languages. +.Sp +In most cases, you need \fIlibgcc.a\fR even when you want to avoid +other standard libraries. In other words, when you specify \fB\-nostdlib\fR +or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well. +This ensures that you have no unresolved references to internal \s-1GCC\s0 +library subroutines. +(An example of such an internal subroutine is \f(CW\*(C`_\|_main\*(C'\fR, used to ensure \*(C+ +constructors are called.) +.IP "\fB\-e\fR \fIentry\fR" 4 +.IX Item "-e entry" +.PD 0 +.IP "\fB\-\-entry=\fR\fIentry\fR" 4 +.IX Item "--entry=entry" +.PD +Specify that the program entry point is \fIentry\fR. The argument is +interpreted by the linker; the \s-1GNU\s0 linker accepts either a symbol name +or an address. +.IP "\fB\-pie\fR" 4 +.IX Item "-pie" +Produce a dynamically linked position independent executable on targets +that support it. For predictable results, you must also specify the same +set of options used for compilation (\fB\-fpie\fR, \fB\-fPIE\fR, +or model suboptions) when you specify this linker option. +.IP "\fB\-no\-pie\fR" 4 +.IX Item "-no-pie" +Don't produce a dynamically linked position independent executable. +.IP "\fB\-static\-pie\fR" 4 +.IX Item "-static-pie" +Produce a static position independent executable on targets that support +it. A static position independent executable is similar to a static +executable, but can be loaded at any address without a dynamic linker. +For predictable results, you must also specify the same set of options +used for compilation (\fB\-fpie\fR, \fB\-fPIE\fR, or model +suboptions) when you specify this linker option. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Link with the \s-1POSIX\s0 threads library. This option is supported on +GNU/Linux targets, most other Unix derivatives, and also on +x86 Cygwin and MinGW targets. On some targets this option also sets +flags for the preprocessor, so it should be used consistently for both +compilation and linking. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +Produce a relocatable object as output. This is also known as partial +linking. +.IP "\fB\-rdynamic\fR" 4 +.IX Item "-rdynamic" +Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets +that support it. This instructs the linker to add all symbols, not +only used ones, to the dynamic symbol table. This option is needed +for some uses of \f(CW\*(C`dlopen\*(C'\fR or to allow obtaining backtraces +from within a program. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +Remove all symbol table and relocation information from the executable. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +On systems that support dynamic linking, this overrides \fB\-pie\fR +and prevents linking with the shared libraries. On other systems, this +option has no effect. +.IP "\fB\-shared\fR" 4 +.IX Item "-shared" +Produce a shared object which can then be linked with other objects to +form an executable. Not all systems support this option. For predictable +results, you must also specify the same set of options used for compilation +(\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions) when +you specify this linker option.[1] +.IP "\fB\-shared\-libgcc\fR" 4 +.IX Item "-shared-libgcc" +.PD 0 +.IP "\fB\-static\-libgcc\fR" 4 +.IX Item "-static-libgcc" +.PD +On systems that provide \fIlibgcc\fR as a shared library, these options +force the use of either the shared or static version, respectively. +If no shared version of \fIlibgcc\fR was built when the compiler was +configured, these options have no effect. +.Sp +There are several situations in which an application should use the +shared \fIlibgcc\fR instead of the static version. The most common +of these is when the application wishes to throw and catch exceptions +across different shared libraries. In that case, each of the libraries +as well as the application itself should use the shared \fIlibgcc\fR. +.Sp +Therefore, the G++ driver automatically adds \fB\-shared\-libgcc\fR +whenever you build a shared library or a main executable, because \*(C+ +programs typically use exceptions, so this is the right thing to do. +.Sp +If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may +find that they are not always linked with the shared \fIlibgcc\fR. +If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker +or a \s-1GNU\s0 linker that does not support option \fB\-\-eh\-frame\-hdr\fR, +it links the shared version of \fIlibgcc\fR into shared libraries +by default. Otherwise, it takes advantage of the linker and optimizes +away the linking with the shared version of \fIlibgcc\fR, linking with +the static version of libgcc by default. This allows exceptions to +propagate through such shared libraries, without incurring relocation +costs at library load time. +.Sp +However, if a library or main executable is supposed to throw or catch +exceptions, you must link it using the G++ driver, or using the option +\&\fB\-shared\-libgcc\fR, such that it is linked with the shared +\&\fIlibgcc\fR. +.IP "\fB\-static\-libasan\fR" 4 +.IX Item "-static-libasan" +When the \fB\-fsanitize=address\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBlibasan\fR. If +\&\fIlibasan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIlibasan\fR. The \fB\-static\-libasan\fR option directs the \s-1GCC\s0 +driver to link \fIlibasan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-libtsan\fR" 4 +.IX Item "-static-libtsan" +When the \fB\-fsanitize=thread\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBlibtsan\fR. If +\&\fIlibtsan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIlibtsan\fR. The \fB\-static\-libtsan\fR option directs the \s-1GCC\s0 +driver to link \fIlibtsan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-liblsan\fR" 4 +.IX Item "-static-liblsan" +When the \fB\-fsanitize=leak\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBliblsan\fR. If +\&\fIliblsan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIliblsan\fR. The \fB\-static\-liblsan\fR option directs the \s-1GCC\s0 +driver to link \fIliblsan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-libubsan\fR" 4 +.IX Item "-static-libubsan" +When the \fB\-fsanitize=undefined\fR option is used to link a program, +the \s-1GCC\s0 driver automatically links against \fBlibubsan\fR. If +\&\fIlibubsan\fR is available as a shared library, and the \fB\-static\fR +option is not used, then this links against the shared version of +\&\fIlibubsan\fR. The \fB\-static\-libubsan\fR option directs the \s-1GCC\s0 +driver to link \fIlibubsan\fR statically, without necessarily linking +other libraries statically. +.IP "\fB\-static\-libstdc++\fR" 4 +.IX Item "-static-libstdc++" +When the \fBg++\fR program is used to link a \*(C+ program, it +normally automatically links against \fBlibstdc++\fR. If +\&\fIlibstdc++\fR is available as a shared library, and the +\&\fB\-static\fR option is not used, then this links against the +shared version of \fIlibstdc++\fR. That is normally fine. However, it +is sometimes useful to freeze the version of \fIlibstdc++\fR used by +the program without going all the way to a fully static link. The +\&\fB\-static\-libstdc++\fR option directs the \fBg++\fR driver to +link \fIlibstdc++\fR statically, without necessarily linking other +libraries statically. +.IP "\fB\-symbolic\fR" 4 +.IX Item "-symbolic" +Bind references to global symbols when building a shared object. Warn +about any unresolved references (unless overridden by the link editor +option \fB\-Xlinker \-z \-Xlinker defs\fR). Only a few systems support +this option. +.IP "\fB\-T\fR \fIscript\fR" 4 +.IX Item "-T script" +Use \fIscript\fR as the linker script. This option is supported by most +systems using the \s-1GNU\s0 linker. On some targets, such as bare-board +targets without an operating system, the \fB\-T\fR option may be required +when linking to avoid references to undefined symbols. +.IP "\fB\-Xlinker\fR \fIoption\fR" 4 +.IX Item "-Xlinker option" +Pass \fIoption\fR as an option to the linker. You can use this to +supply system-specific linker options that \s-1GCC\s0 does not recognize. +.Sp +If you want to pass an option that takes a separate argument, you must use +\&\fB\-Xlinker\fR twice, once for the option and once for the argument. +For example, to pass \fB\-assert definitions\fR, you must write +\&\fB\-Xlinker \-assert \-Xlinker definitions\fR. It does not work to write +\&\fB\-Xlinker \*(L"\-assert definitions\*(R"\fR, because this passes the entire +string as a single argument, which is not what the linker expects. +.Sp +When using the \s-1GNU\s0 linker, it is usually more convenient to pass +arguments to linker options using the \fIoption\fR\fB=\fR\fIvalue\fR +syntax than as separate arguments. For example, you can specify +\&\fB\-Xlinker \-Map=output.map\fR rather than +\&\fB\-Xlinker \-Map \-Xlinker output.map\fR. Other linkers may not support +this syntax for command-line options. +.IP "\fB\-Wl,\fR\fIoption\fR" 4 +.IX Item "-Wl,option" +Pass \fIoption\fR as an option to the linker. If \fIoption\fR contains +commas, it is split into multiple options at the commas. You can use this +syntax to pass an argument to the option. +For example, \fB\-Wl,\-Map,output.map\fR passes \fB\-Map output.map\fR to the +linker. When using the \s-1GNU\s0 linker, you can also get the same effect with +\&\fB\-Wl,\-Map=output.map\fR. +.IP "\fB\-u\fR \fIsymbol\fR" 4 +.IX Item "-u symbol" +Pretend the symbol \fIsymbol\fR is undefined, to force linking of +library modules to define it. You can use \fB\-u\fR multiple times with +different symbols to force loading of additional library modules. +.IP "\fB\-z\fR \fIkeyword\fR" 4 +.IX Item "-z keyword" +\&\fB\-z\fR is passed directly on to the linker along with the keyword +\&\fIkeyword\fR. See the section in the documentation of your linker for +permitted values and their meanings. +.SS "Options for Directory Search" +.IX Subsection "Options for Directory Search" +These options specify directories to search for header files, for +libraries and for parts of the compiler: +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +.PD 0 +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +.PD +Add the directory \fIdir\fR to the list of directories to be searched +for header files during preprocessing. +If \fIdir\fR begins with \fB=\fR or \f(CW$SYSROOT\fR, then the \fB=\fR +or \f(CW$SYSROOT\fR is replaced by the sysroot prefix; see +\&\fB\-\-sysroot\fR and \fB\-isysroot\fR. +.Sp +Directories specified with \fB\-iquote\fR apply only to the quote +form of the directive, \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. +Directories specified with \fB\-I\fR, \fB\-isystem\fR, +or \fB\-idirafter\fR apply to lookup for both the +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR and +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR directives. +.Sp +You can specify any number or combination of these options on the +command line to search for header files in several directories. +The lookup order is as follows: +.RS 4 +.IP "1." 4 +.IX Item "1." +For the quote form of the include directive, the directory of the current +file is searched first. +.IP "2." 4 +.IX Item "2." +For the quote form of the include directive, the directories specified +by \fB\-iquote\fR options are searched in left-to-right order, +as they appear on the command line. +.IP "3." 4 +.IX Item "3." +Directories specified with \fB\-I\fR options are scanned in +left-to-right order. +.IP "4." 4 +.IX Item "4." +Directories specified with \fB\-isystem\fR options are scanned in +left-to-right order. +.IP "5." 4 +.IX Item "5." +Standard system directories are scanned. +.IP "6." 4 +.IX Item "6." +Directories specified with \fB\-idirafter\fR options are scanned in +left-to-right order. +.RE +.RS 4 +.Sp +You can use \fB\-I\fR to override a system header +file, substituting your own version, since these directories are +searched before the standard system header file directories. +However, you should +not use this option to add directories that contain vendor-supplied +system header files; use \fB\-isystem\fR for that. +.Sp +The \fB\-isystem\fR and \fB\-idirafter\fR options also mark the directory +as a system directory, so that it gets the same special treatment that +is applied to the standard system directories. +.Sp +If a standard system include directory, or a directory specified with +\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR +option is ignored. The directory is still searched but as a +system directory at its normal position in the system include chain. +This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and +the ordering for the \f(CW\*(C`#include_next\*(C'\fR directive are not inadvertently +changed. +If you really need to change the search order for system directories, +use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options. +.RE +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +Split the include path. +This option has been deprecated. Please use \fB\-iquote\fR instead for +\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR +option. +.Sp +Any directories specified with \fB\-I\fR +options before \fB\-I\-\fR are searched only for headers requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are +specified with \fB\-I\fR options after the \fB\-I\-\fR, those +directories are searched for all \fB#include\fR directives. +.Sp +In addition, \fB\-I\-\fR inhibits the use of the directory of the current +file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. There is no way to override this effect of \fB\-I\-\fR. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the prefix represents a directory, you should include the +final \fB/\fR. +.IP "\fB\-iwithprefix\fR \fIdir\fR" 4 +.IX Item "-iwithprefix dir" +.PD 0 +.IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 +.IX Item "-iwithprefixbefore dir" +.PD +Append \fIdir\fR to the prefix specified previously with +\&\fB\-iprefix\fR, and add the resulting directory to the include search +path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR +would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files (except for Darwin targets, where it applies to both header +files and libraries). See the \fB\-\-sysroot\fR option for more +information. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing +target-specific \*(C+ headers. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. +Only the directories explicitly specified with \fB\-I\fR, +\&\fB\-iquote\fR, \fB\-isystem\fR, and/or \fB\-idirafter\fR +options (and the directory of the current file, if appropriate) +are searched. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the \*(C+\-specific standard directories, +but do still search the other standard directories. (This option is +used when building the \*(C+ library.) +.IP "\fB\-iplugindir=\fR\fIdir\fR" 4 +.IX Item "-iplugindir=dir" +Set the directory to search for plugins that are passed +by \fB\-fplugin=\fR\fIname\fR instead of +\&\fB\-fplugin=\fR\fIpath\fR\fB/\fR\fIname\fR\fB.so\fR. This option is not meant +to be used by the user, but only passed by the driver. +.IP "\fB\-L\fR\fIdir\fR" 4 +.IX Item "-Ldir" +Add directory \fIdir\fR to the list of directories to be searched +for \fB\-l\fR. +.IP "\fB\-B\fR\fIprefix\fR" 4 +.IX Item "-Bprefix" +This option specifies where to find the executables, libraries, +include files, and data files of the compiler itself. +.Sp +The compiler driver program runs one or more of the subprograms +\&\fBcpp\fR, \fBcc1\fR, \fBas\fR and \fBld\fR. It tries +\&\fIprefix\fR as a prefix for each program it tries to run, both with and +without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR for the corresponding target +machine and compiler version. +.Sp +For each subprogram to be run, the compiler driver first tries the +\&\fB\-B\fR prefix, if any. If that name is not found, or if \fB\-B\fR +is not specified, the driver tries two standard prefixes, +\&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR. If neither of +those results in a file name that is found, the unmodified program +name is searched for using the directories specified in your +\&\fB\s-1PATH\s0\fR environment variable. +.Sp +The compiler checks to see if the path provided by \fB\-B\fR +refers to a directory, and if necessary it adds a directory +separator character at the end of the path. +.Sp +\&\fB\-B\fR prefixes that effectively specify directory names also apply +to libraries in the linker, because the compiler translates these +options into \fB\-L\fR options for the linker. They also apply to +include files in the preprocessor, because the compiler translates these +options into \fB\-isystem\fR options for the preprocessor. In this case, +the compiler appends \fBinclude\fR to the prefix. +.Sp +The runtime support file \fIlibgcc.a\fR can also be searched for using +the \fB\-B\fR prefix, if needed. If it is not found there, the two +standard prefixes above are tried, and that is all. The file is left +out of the link if it is not found by those means. +.Sp +Another way to specify a prefix much like the \fB\-B\fR prefix is to use +the environment variable \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.Sp +As a special kludge, if the path provided by \fB\-B\fR is +\&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to +9, then it is replaced by \fI[dir/]include\fR. This is to help +with boot-strapping the compiler. +.IP "\fB\-no\-canonical\-prefixes\fR" 4 +.IX Item "-no-canonical-prefixes" +Do not expand any symbolic links, resolve references to \fB/../\fR +or \fB/./\fR, or make the path absolute when generating a relative +prefix. +.IP "\fB\-\-sysroot=\fR\fIdir\fR" 4 +.IX Item "--sysroot=dir" +Use \fIdir\fR as the logical root directory for headers and libraries. +For example, if the compiler normally searches for headers in +\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it instead +searches \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR. +.Sp +If you use both this option and the \fB\-isysroot\fR option, then +the \fB\-\-sysroot\fR option applies to libraries, but the +\&\fB\-isysroot\fR option applies to header files. +.Sp +The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support +for this option. If your linker does not support this option, the +header file aspect of \fB\-\-sysroot\fR still works, but the +library aspect does not. +.IP "\fB\-\-no\-sysroot\-suffix\fR" 4 +.IX Item "--no-sysroot-suffix" +For some targets, a suffix is added to the root directory specified +with \fB\-\-sysroot\fR, depending on the other options used, so that +headers may for example be found in +\&\fI\fIdir\fI/\fIsuffix\fI/usr/include\fR instead of +\&\fI\fIdir\fI/usr/include\fR. This option disables the addition of +such a suffix. +.SS "Options for Code Generation Conventions" +.IX Subsection "Options for Code Generation Conventions" +These machine-independent options control the interface conventions +used in code generation. +.PP +Most of them have both positive and negative forms; the negative form +of \fB\-ffoo\fR is \fB\-fno\-foo\fR. In the table below, only +one of the forms is listed\-\-\-the one that is not the default. You +can figure out the other form by either removing \fBno\-\fR or adding +it. +.IP "\fB\-fstack\-reuse=\fR\fIreuse-level\fR" 4 +.IX Item "-fstack-reuse=reuse-level" +This option controls stack space reuse for user declared local/auto variables +and compiler generated temporaries. \fIreuse_level\fR can be \fBall\fR, +\&\fBnamed_vars\fR, or \fBnone\fR. \fBall\fR enables stack reuse for all +local variables and temporaries, \fBnamed_vars\fR enables the reuse only for +user defined local variables with names, and \fBnone\fR disables stack reuse +completely. The default value is \fBall\fR. The option is needed when the +program extends the lifetime of a scoped local variable or a compiler generated +temporary beyond the end point defined by the language. When a lifetime of +a variable ends, and if the variable lives in memory, the optimizing compiler +has the freedom to reuse its stack space with other temporaries or scoped +local variables whose live range does not overlap with it. Legacy code extending +local lifetime is likely to break with the stack reuse optimization. +.Sp +For example, +.Sp +.Vb 3 +\& int *p; +\& { +\& int local1; +\& +\& p = &local1; +\& local1 = 10; +\& .... +\& } +\& { +\& int local2; +\& local2 = 20; +\& ... +\& } +\& +\& if (*p == 10) // out of scope use of local1 +\& { +\& +\& } +.Ve +.Sp +Another example: +.Sp +.Vb 6 +\& struct A +\& { +\& A(int k) : i(k), j(k) { } +\& int i; +\& int j; +\& }; +\& +\& A *ap; +\& +\& void foo(const A& ar) +\& { +\& ap = &ar; +\& } +\& +\& void bar() +\& { +\& foo(A(10)); // temp object\*(Aqs lifetime ends when foo returns +\& +\& { +\& A a(20); +\& .... +\& } +\& ap\->i+= 10; // ap references out of scope temp whose space +\& // is reused with a. What is the value of ap\->i? +\& } +.Ve +.Sp +The lifetime of a compiler generated temporary is well defined by the \*(C+ +standard. When a lifetime of a temporary ends, and if the temporary lives +in memory, the optimizing compiler has the freedom to reuse its stack +space with other temporaries or scoped local variables whose live range +does not overlap with it. However some of the legacy code relies on +the behavior of older compilers in which temporaries' stack space is +not reused, the aggressive stack reuse can lead to runtime errors. This +option is used to control the temporary stack reuse optimization. +.IP "\fB\-ftrapv\fR" 4 +.IX Item "-ftrapv" +This option generates traps for signed overflow on addition, subtraction, +multiplication operations. +The options \fB\-ftrapv\fR and \fB\-fwrapv\fR override each other, so using +\&\fB\-ftrapv\fR \fB\-fwrapv\fR on the command-line results in +\&\fB\-fwrapv\fR being effective. Note that only active options override, so +using \fB\-ftrapv\fR \fB\-fwrapv\fR \fB\-fno\-wrapv\fR on the command-line +results in \fB\-ftrapv\fR being effective. +.IP "\fB\-fwrapv\fR" 4 +.IX Item "-fwrapv" +This option instructs the compiler to assume that signed arithmetic +overflow of addition, subtraction and multiplication wraps around +using twos-complement representation. This flag enables some optimizations +and disables others. +The options \fB\-ftrapv\fR and \fB\-fwrapv\fR override each other, so using +\&\fB\-ftrapv\fR \fB\-fwrapv\fR on the command-line results in +\&\fB\-fwrapv\fR being effective. Note that only active options override, so +using \fB\-ftrapv\fR \fB\-fwrapv\fR \fB\-fno\-wrapv\fR on the command-line +results in \fB\-ftrapv\fR being effective. +.IP "\fB\-fwrapv\-pointer\fR" 4 +.IX Item "-fwrapv-pointer" +This option instructs the compiler to assume that pointer arithmetic +overflow on addition and subtraction wraps around using twos-complement +representation. This flag disables some optimizations which assume +pointer overflow is invalid. +.IP "\fB\-fstrict\-overflow\fR" 4 +.IX Item "-fstrict-overflow" +This option implies \fB\-fno\-wrapv\fR \fB\-fno\-wrapv\-pointer\fR and when +negated implies \fB\-fwrapv\fR \fB\-fwrapv\-pointer\fR. +.IP "\fB\-fexceptions\fR" 4 +.IX Item "-fexceptions" +Enable exception handling. Generates extra code needed to propagate +exceptions. For some targets, this implies \s-1GCC\s0 generates frame +unwind information for all functions, which can produce significant data +size overhead, although it does not affect execution. If you do not +specify this option, \s-1GCC\s0 enables it by default for languages like +\&\*(C+ that normally require exception handling, and disables it for +languages like C that do not normally require it. However, you may need +to enable this option when compiling C code that needs to interoperate +properly with exception handlers written in \*(C+. You may also wish to +disable this option if you are compiling older \*(C+ programs that don't +use exception handling. +.IP "\fB\-fnon\-call\-exceptions\fR" 4 +.IX Item "-fnon-call-exceptions" +Generate code that allows trapping instructions to throw exceptions. +Note that this requires platform-specific runtime support that does +not exist everywhere. Moreover, it only allows \fItrapping\fR +instructions to throw exceptions, i.e. memory references or floating-point +instructions. It does not allow exceptions to be thrown from +arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR. +.IP "\fB\-fdelete\-dead\-exceptions\fR" 4 +.IX Item "-fdelete-dead-exceptions" +Consider that instructions that may throw exceptions but don't otherwise +contribute to the execution of the program can be optimized away. +This option is enabled by default for the Ada front end, as permitted by +the Ada language specification. +Optimization passes that cause dead exceptions to be removed are enabled independently at different optimization levels. +.IP "\fB\-funwind\-tables\fR" 4 +.IX Item "-funwind-tables" +Similar to \fB\-fexceptions\fR, except that it just generates any needed +static data, but does not affect the generated code in any other way. +You normally do not need to enable this option; instead, a language processor +that needs this handling enables it on your behalf. +.IP "\fB\-fasynchronous\-unwind\-tables\fR" 4 +.IX Item "-fasynchronous-unwind-tables" +Generate unwind table in \s-1DWARF\s0 format, if supported by target machine. The +table is exact at each instruction boundary, so it can be used for stack +unwinding from asynchronous events (such as debugger or garbage collector). +.IP "\fB\-fno\-gnu\-unique\fR" 4 +.IX Item "-fno-gnu-unique" +On systems with recent \s-1GNU\s0 assembler and C library, the \*(C+ compiler +uses the \f(CW\*(C`STB_GNU_UNIQUE\*(C'\fR binding to make sure that definitions +of template static data members and static local variables in inline +functions are unique even in the presence of \f(CW\*(C`RTLD_LOCAL\*(C'\fR; this +is necessary to avoid problems with a library used by two different +\&\f(CW\*(C`RTLD_LOCAL\*(C'\fR plugins depending on a definition in one of them and +therefore disagreeing with the other one about the binding of the +symbol. But this causes \f(CW\*(C`dlclose\*(C'\fR to be ignored for affected +DSOs; if your program relies on reinitialization of a \s-1DSO\s0 via +\&\f(CW\*(C`dlclose\*(C'\fR and \f(CW\*(C`dlopen\*(C'\fR, you can use +\&\fB\-fno\-gnu\-unique\fR. +.IP "\fB\-fpcc\-struct\-return\fR" 4 +.IX Item "-fpcc-struct-return" +Return \*(L"short\*(R" \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like +longer ones, rather than in registers. This convention is less +efficient, but it has the advantage of allowing intercallability between +GCC-compiled files and files compiled with other compilers, particularly +the Portable C Compiler (pcc). +.Sp +The precise convention for returning structures in memory depends +on the target configuration macros. +.Sp +Short structures and unions are those whose size and alignment match +that of some integer type. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-fpcc\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-freg\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-freg\-struct\-return\fR" 4 +.IX Item "-freg-struct-return" +Return \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in registers when possible. +This is more efficient for small structures than +\&\fB\-fpcc\-struct\-return\fR. +.Sp +If you specify neither \fB\-fpcc\-struct\-return\fR nor +\&\fB\-freg\-struct\-return\fR, \s-1GCC\s0 defaults to whichever convention is +standard for the target. If there is no standard convention, \s-1GCC\s0 +defaults to \fB\-fpcc\-struct\-return\fR, except on targets where \s-1GCC\s0 is +the principal compiler. In those cases, we can choose the standard, and +we chose the more efficient register return alternative. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-freg\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-fpcc\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-enums\fR" 4 +.IX Item "-fshort-enums" +Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the +declared range of possible values. Specifically, the \f(CW\*(C`enum\*(C'\fR type +is equivalent to the smallest integer type that has enough room. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-enums\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-wchar\fR" 4 +.IX Item "-fshort-wchar" +Override the underlying type for \f(CW\*(C`wchar_t\*(C'\fR to be \f(CW\*(C`short +unsigned int\*(C'\fR instead of the default for the target. This option is +useful for building programs to run under \s-1WINE.\s0 +.Sp +\&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fno\-common\fR" 4 +.IX Item "-fno-common" +In C code, this option controls the placement of global variables +defined without an initializer, known as \fItentative definitions\fR +in the C standard. Tentative definitions are distinct from declarations +of a variable with the \f(CW\*(C`extern\*(C'\fR keyword, which do not allocate storage. +.Sp +Unix C compilers have traditionally allocated storage for +uninitialized global variables in a common block. This allows the +linker to resolve all tentative definitions of the same variable +in different compilation units to the same object, or to a non-tentative +definition. +This is the behavior specified by \fB\-fcommon\fR, and is the default for +\&\s-1GCC\s0 on most targets. +On the other hand, this behavior is not required by \s-1ISO +C,\s0 and on some targets may carry a speed or code size penalty on +variable references. +.Sp +The \fB\-fno\-common\fR option specifies that the compiler should instead +place uninitialized global variables in the \s-1BSS\s0 section of the object file. +This inhibits the merging of tentative definitions by the linker so +you get a multiple-definition error if the same +variable is defined in more than one compilation unit. +Compiling with \fB\-fno\-common\fR is useful on targets for which +it provides better performance, or if you wish to verify that the +program will work on other systems that always treat uninitialized +variable definitions this way. +.IP "\fB\-fno\-ident\fR" 4 +.IX Item "-fno-ident" +Ignore the \f(CW\*(C`#ident\*(C'\fR directive. +.IP "\fB\-finhibit\-size\-directive\fR" 4 +.IX Item "-finhibit-size-directive" +Don't output a \f(CW\*(C`.size\*(C'\fR assembler directive, or anything else that +would cause trouble if the function is split in the middle, and the +two halves are placed at locations far apart in memory. This option is +used when compiling \fIcrtstuff.c\fR; you should not need to use it +for anything else. +.IP "\fB\-fverbose\-asm\fR" 4 +.IX Item "-fverbose-asm" +Put extra commentary information in the generated assembly code to +make it more readable. This option is generally only of use to those +who actually need to read the generated assembly code (perhaps while +debugging the compiler itself). +.Sp +\&\fB\-fno\-verbose\-asm\fR, the default, causes the +extra information to be omitted and is useful when comparing two assembler +files. +.Sp +The added comments include: +.RS 4 +.IP "*" 4 +information on the compiler version and command-line options, +.IP "*" 4 +the source code lines associated with the assembly instructions, +in the form \s-1FILENAME:LINENUMBER:CONTENT OF LINE,\s0 +.IP "*" 4 +hints on which high-level expressions correspond to +the various assembly instruction operands. +.RE +.RS 4 +.Sp +For example, given this C source file: +.Sp +.Vb 4 +\& int test (int n) +\& { +\& int i; +\& int total = 0; +\& +\& for (i = 0; i < n; i++) +\& total += i * i; +\& +\& return total; +\& } +.Ve +.Sp +compiling to (x86_64) assembly via \fB\-S\fR and emitting the result +direct to stdout via \fB\-o\fR \fB\-\fR +.Sp +.Vb 1 +\& gcc \-S test.c \-fverbose\-asm \-Os \-o \- +.Ve +.Sp +gives output similar to this: +.Sp +.Vb 5 +\& .file "test.c" +\& # GNU C11 (GCC) version 7.0.0 20160809 (experimental) (x86_64\-pc\-linux\-gnu) +\& [...snip...] +\& # options passed: +\& [...snip...] +\& +\& .text +\& .globl test +\& .type test, @function +\& test: +\& .LFB0: +\& .cfi_startproc +\& # test.c:4: int total = 0; +\& xorl %eax, %eax # +\& # test.c:6: for (i = 0; i < n; i++) +\& xorl %edx, %edx # i +\& .L2: +\& # test.c:6: for (i = 0; i < n; i++) +\& cmpl %edi, %edx # n, i +\& jge .L5 #, +\& # test.c:7: total += i * i; +\& movl %edx, %ecx # i, tmp92 +\& imull %edx, %ecx # i, tmp92 +\& # test.c:6: for (i = 0; i < n; i++) +\& incl %edx # i +\& # test.c:7: total += i * i; +\& addl %ecx, %eax # tmp92, +\& jmp .L2 # +\& .L5: +\& # test.c:10: } +\& ret +\& .cfi_endproc +\& .LFE0: +\& .size test, .\-test +\& .ident "GCC: (GNU) 7.0.0 20160809 (experimental)" +\& .section .note.GNU\-stack,"",@progbits +.Ve +.Sp +The comments are intended for humans rather than machines and hence the +precise format of the comments is subject to change. +.RE +.IP "\fB\-frecord\-gcc\-switches\fR" 4 +.IX Item "-frecord-gcc-switches" +This switch causes the command line used to invoke the +compiler to be recorded into the object file that is being created. +This switch is only implemented on some targets and the exact format +of the recording is target and binary file format dependent, but it +usually takes the form of a section containing \s-1ASCII\s0 text. This +switch is related to the \fB\-fverbose\-asm\fR switch, but that +switch only records information in the assembler output file as +comments, so it never reaches the object file. +See also \fB\-grecord\-gcc\-switches\fR for another +way of storing compiler options into the object file. +.IP "\fB\-fpic\fR" 4 +.IX Item "-fpic" +Generate position-independent code (\s-1PIC\s0) suitable for use in a shared +library, if supported for the target machine. Such code accesses all +constant addresses through a global offset table (\s-1GOT\s0). The dynamic +loader resolves the \s-1GOT\s0 entries when the program starts (the dynamic +loader is not part of \s-1GCC\s0; it is part of the operating system). If +the \s-1GOT\s0 size for the linked executable exceeds a machine-specific +maximum size, you get an error message from the linker indicating that +\&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR +instead. (These maximums are 8k on the \s-1SPARC,\s0 28k on AArch64 and 32k +on the m68k and \s-1RS/6000.\s0 The x86 has no such limit.) +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. For the x86, \s-1GCC\s0 supports \s-1PIC\s0 for System V +but not for the Sun 386i. Code generated for the \s-1IBM RS/6000\s0 is always +position-independent. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 1. +.IP "\fB\-fPIC\fR" 4 +.IX Item "-fPIC" +If supported for the target machine, emit position-independent code, +suitable for dynamic linking and avoiding any limit on the size of the +global offset table. This option makes a difference on AArch64, m68k, +PowerPC and \s-1SPARC.\s0 +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 2. +.IP "\fB\-fpie\fR" 4 +.IX Item "-fpie" +.PD 0 +.IP "\fB\-fPIE\fR" 4 +.IX Item "-fPIE" +.PD +These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but the +generated position-independent code can be only linked into executables. +Usually these options are used to compile code that will be linked using +the \fB\-pie\fR \s-1GCC\s0 option. +.Sp +\&\fB\-fpie\fR and \fB\-fPIE\fR both define the macros +\&\f(CW\*(C`_\|_pie_\|_\*(C'\fR and \f(CW\*(C`_\|_PIE_\|_\*(C'\fR. The macros have the value 1 +for \fB\-fpie\fR and 2 for \fB\-fPIE\fR. +.IP "\fB\-fno\-plt\fR" 4 +.IX Item "-fno-plt" +Do not use the \s-1PLT\s0 for external function calls in position-independent code. +Instead, load the callee address at call sites from the \s-1GOT\s0 and branch to it. +This leads to more efficient code by eliminating \s-1PLT\s0 stubs and exposing +\&\s-1GOT\s0 loads to optimizations. On architectures such as 32\-bit x86 where +\&\s-1PLT\s0 stubs expect the \s-1GOT\s0 pointer in a specific register, this gives more +register allocation freedom to the compiler. +Lazy binding requires use of the \s-1PLT\s0; +with \fB\-fno\-plt\fR all external symbols are resolved at load time. +.Sp +Alternatively, the function attribute \f(CW\*(C`noplt\*(C'\fR can be used to avoid calls +through the \s-1PLT\s0 for specific external functions. +.Sp +In position-dependent code, a few targets also convert calls to +functions that are marked to not use the \s-1PLT\s0 to use the \s-1GOT\s0 instead. +.IP "\fB\-fno\-jump\-tables\fR" 4 +.IX Item "-fno-jump-tables" +Do not use jump tables for switch statements even where it would be +more efficient than other code generation strategies. This option is +of use in conjunction with \fB\-fpic\fR or \fB\-fPIC\fR for +building code that forms part of a dynamic linker and cannot +reference the address of a jump table. On some targets, jump tables +do not require a \s-1GOT\s0 and this option is not needed. +.IP "\fB\-ffixed\-\fR\fIreg\fR" 4 +.IX Item "-ffixed-reg" +Treat the register named \fIreg\fR as a fixed register; generated code +should never refer to it (except perhaps as a stack pointer, frame +pointer or in some other fixed role). +.Sp +\&\fIreg\fR must be the name of a register. The register names accepted +are machine-specific and are defined in the \f(CW\*(C`REGISTER_NAMES\*(C'\fR +macro in the machine description macro file. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-used\-\fR\fIreg\fR" 4 +.IX Item "-fcall-used-reg" +Treat the register named \fIreg\fR as an allocable register that is +clobbered by function calls. It may be allocated for temporaries or +variables that do not live across a call. Functions compiled this way +do not save and restore the register \fIreg\fR. +.Sp +It is an error to use this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model produces disastrous results. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-saved\-\fR\fIreg\fR" 4 +.IX Item "-fcall-saved-reg" +Treat the register named \fIreg\fR as an allocable register saved by +functions. It may be allocated even for temporaries or variables that +live across a call. Functions compiled this way save and restore +the register \fIreg\fR if they use it. +.Sp +It is an error to use this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model produces disastrous results. +.Sp +A different sort of disaster results from the use of this flag for +a register in which function values may be returned. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fpack\-struct[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-fpack-struct[=n]" +Without a value specified, pack all structure members together without +holes. When a value is specified (which must be a small power of two), pack +structure members according to this value, representing the maximum +alignment (that is, objects with default alignment requirements larger than +this are output potentially unaligned at the next fitting location. +.Sp +\&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Additionally, it makes the code suboptimal. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fleading\-underscore\fR" 4 +.IX Item "-fleading-underscore" +This option and its counterpart, \fB\-fno\-leading\-underscore\fR, forcibly +change the way C symbols are represented in the object file. One use +is to help link with legacy assembly code. +.Sp +\&\fBWarning:\fR the \fB\-fleading\-underscore\fR switch causes \s-1GCC\s0 to +generate code that is not binary compatible with code generated without that +switch. Use it to conform to a non-default application binary interface. +Not all targets provide complete support for this switch. +.IP "\fB\-ftls\-model=\fR\fImodel\fR" 4 +.IX Item "-ftls-model=model" +Alter the thread-local storage model to be used. +The \fImodel\fR argument should be one of \fBglobal-dynamic\fR, +\&\fBlocal-dynamic\fR, \fBinitial-exec\fR or \fBlocal-exec\fR. +Note that the choice is subject to optimization: the compiler may use +a more efficient model for symbols not visible outside of the translation +unit, or if \fB\-fpic\fR is not given on the command line. +.Sp +The default without \fB\-fpic\fR is \fBinitial-exec\fR; with +\&\fB\-fpic\fR the default is \fBglobal-dynamic\fR. +.IP "\fB\-ftrampolines\fR" 4 +.IX Item "-ftrampolines" +For targets that normally need trampolines for nested functions, always +generate them instead of using descriptors. Otherwise, for targets that +do not need them, like for example HP-PA or \s-1IA\-64,\s0 do nothing. +.Sp +A trampoline is a small piece of code that is created at run time on the +stack when the address of a nested function is taken, and is used to call +the nested function indirectly. Therefore, it requires the stack to be +made executable in order for the program to work properly. +.Sp +\&\fB\-fno\-trampolines\fR is enabled by default on a language by language +basis to let the compiler avoid generating them, if it computes that this +is safe, and replace them with descriptors. Descriptors are made up of data +only, but the generated code must be prepared to deal with them. As of this +writing, \fB\-fno\-trampolines\fR is enabled by default only for Ada. +.Sp +Moreover, code compiled with \fB\-ftrampolines\fR and code compiled with +\&\fB\-fno\-trampolines\fR are not binary compatible if nested functions are +present. This option must therefore be used on a program-wide basis and be +manipulated with extreme care. +.IP "\fB\-fvisibility=\fR[\fBdefault\fR|\fBinternal\fR|\fBhidden\fR|\fBprotected\fR]" 4 +.IX Item "-fvisibility=[default|internal|hidden|protected]" +Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all +symbols are marked with this unless overridden within the code. +Using this feature can very substantially improve linking and +load times of shared object libraries, produce more optimized +code, provide near-perfect \s-1API\s0 export and prevent symbol clashes. +It is \fBstrongly\fR recommended that you use this in any shared objects +you distribute. +.Sp +Despite the nomenclature, \fBdefault\fR always means public; i.e., +available to be linked against from outside the shared object. +\&\fBprotected\fR and \fBinternal\fR are pretty useless in real-world +usage so the only other commonly used option is \fBhidden\fR. +The default if \fB\-fvisibility\fR isn't specified is +\&\fBdefault\fR, i.e., make every symbol public. +.Sp +A good explanation of the benefits offered by ensuring \s-1ELF\s0 +symbols have the correct visibility is given by \*(L"How To Write +Shared Libraries\*(R" by Ulrich Drepper (which can be found at +<\fBhttps://www.akkadia.org/drepper/\fR>)\-\-\-however a superior +solution made possible by this option to marking things hidden when +the default is public is to make the default hidden and mark things +public. This is the norm with DLLs on Windows and with \fB\-fvisibility=hidden\fR +and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of +\&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with +identical syntax. This is a great boon to those working with +cross-platform projects. +.Sp +For those adding visibility support to existing code, you may find +\&\f(CW\*(C`#pragma GCC visibility\*(C'\fR of use. This works by you enclosing +the declarations you wish to set visibility for with (for example) +\&\f(CW\*(C`#pragma GCC visibility push(hidden)\*(C'\fR and +\&\f(CW\*(C`#pragma GCC visibility pop\*(C'\fR. +Bear in mind that symbol visibility should be viewed \fBas +part of the \s-1API\s0 interface contract\fR and thus all new code should +always specify visibility when it is not the default; i.e., declarations +only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly +as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this +abundantly clear also aids readability and self-documentation of the code. +Note that due to \s-1ISO \*(C+\s0 specification requirements, \f(CW\*(C`operator new\*(C'\fR and +\&\f(CW\*(C`operator delete\*(C'\fR must always be of default visibility. +.Sp +Be aware that headers from outside your project, in particular system +headers and headers from any other library you use, may not be +expecting to be compiled with visibility other than the default. You +may need to explicitly say \f(CW\*(C`#pragma GCC visibility push(default)\*(C'\fR +before including any such headers. +.Sp +\&\f(CW\*(C`extern\*(C'\fR declarations are not affected by \fB\-fvisibility\fR, so +a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with +no modifications. However, this means that calls to \f(CW\*(C`extern\*(C'\fR +functions with no explicit visibility use the \s-1PLT,\s0 so it is more +effective to use \f(CW\*(C`_\|_attribute ((visibility))\*(C'\fR and/or +\&\f(CW\*(C`#pragma GCC visibility\*(C'\fR to tell the compiler which \f(CW\*(C`extern\*(C'\fR +declarations should be treated as hidden. +.Sp +Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage +entities. This means that, for instance, an exception class that is +be thrown between DSOs must be explicitly marked with default +visibility so that the \fBtype_info\fR nodes are unified between +the DSOs. +.Sp +An overview of these techniques, their benefits and how to use them +is at <\fBhttp://gcc.gnu.org/wiki/Visibility\fR>. +.IP "\fB\-fstrict\-volatile\-bitfields\fR" 4 +.IX Item "-fstrict-volatile-bitfields" +This option should be used if accesses to volatile bit-fields (or other +structure fields, although the compiler usually honors those types +anyway) should use a single access of the width of the +field's type, aligned to a natural alignment if possible. For +example, targets with memory-mapped peripheral registers might require +all such accesses to be 16 bits wide; with this flag you can +declare all peripheral bit-fields as \f(CW\*(C`unsigned short\*(C'\fR (assuming short +is 16 bits on these targets) to force \s-1GCC\s0 to use 16\-bit accesses +instead of, perhaps, a more efficient 32\-bit access. +.Sp +If this option is disabled, the compiler uses the most efficient +instruction. In the previous example, that might be a 32\-bit load +instruction, even though that accesses bytes that do not contain +any portion of the bit-field, or memory-mapped registers unrelated to +the one being updated. +.Sp +In some cases, such as when the \f(CW\*(C`packed\*(C'\fR attribute is applied to a +structure field, it may not be possible to access the field with a single +read or write that is correctly aligned for the target machine. In this +case \s-1GCC\s0 falls back to generating multiple accesses rather than code that +will fault or truncate the result at run time. +.Sp +Note: Due to restrictions of the C/\*(C+11 memory model, write accesses are +not allowed to touch non bit-field members. It is therefore recommended +to define all bits of the field's type as bit-field members. +.Sp +The default value of this option is determined by the application binary +interface for the target processor. +.IP "\fB\-fsync\-libcalls\fR" 4 +.IX Item "-fsync-libcalls" +This option controls whether any out-of-line instance of the \f(CW\*(C`_\|_sync\*(C'\fR +family of functions may be used to implement the \*(C+11 \f(CW\*(C`_\|_atomic\*(C'\fR +family of functions. +.Sp +The default value of this option is enabled, thus the only useful form +of the option is \fB\-fno\-sync\-libcalls\fR. This option is used in +the implementation of the \fIlibatomic\fR runtime library. +.SS "\s-1GCC\s0 Developer Options" +.IX Subsection "GCC Developer Options" +This section describes command-line options that are primarily of +interest to \s-1GCC\s0 developers, including options to support compiler +testing and investigation of compiler bugs and compile-time +performance problems. This includes options that produce debug dumps +at various points in the compilation; that print statistics such as +memory use and execution time; and that print information about \s-1GCC\s0's +configuration, such as where it searches for libraries. You should +rarely need to use any of these options for ordinary compilation and +linking tasks. +.PP +Many developer options that cause \s-1GCC\s0 to dump output to a file take an +optional \fB=\fR\fIfilename\fR suffix. You can specify \fBstdout\fR +or \fB\-\fR to dump to standard output, and \fBstderr\fR for standard +error. +.PP +If \fB=\fR\fIfilename\fR is omitted, a default dump file name is +constructed by concatenating the base dump file name, a pass number, +phase letter, and pass name. The base dump file name is the name of +output file produced by the compiler if explicitly specified and not +an executable; otherwise it is the source file name. +The pass number is determined by the order passes are registered with +the compiler's pass manager. +This is generally the same as the order of execution, but passes +registered by plugins, target-specific passes, or passes that are +otherwise registered late are numbered higher than the pass named +\&\fBfinal\fR, even if they are executed earlier. The phase letter is +one of \fBi\fR (inter-procedural analysis), \fBl\fR +(language-specific), \fBr\fR (\s-1RTL\s0), or \fBt\fR (tree). +The files are created in the directory of the output file. +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +.PD 0 +.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fdump-rtl-pass" +.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fdump-rtl-pass=filename" +.PD +Says to make debugging dumps during compilation at times specified by +\&\fIletters\fR. This is used for debugging the RTL-based passes of the +compiler. +.Sp +Some \fB\-d\fR\fIletters\fR switches have different meaning when +\&\fB\-E\fR is used for preprocessing. +.Sp +Debug dumps can be enabled with a \fB\-fdump\-rtl\fR switch or some +\&\fB\-d\fR option \fIletters\fR. Here are the possible +letters for use in \fIpass\fR and \fIletters\fR, and their meanings: +.RS 4 +.IP "\fB\-fdump\-rtl\-alignments\fR" 4 +.IX Item "-fdump-rtl-alignments" +Dump after branch alignments have been computed. +.IP "\fB\-fdump\-rtl\-asmcons\fR" 4 +.IX Item "-fdump-rtl-asmcons" +Dump after fixing rtl statements that have unsatisfied in/out constraints. +.IP "\fB\-fdump\-rtl\-auto_inc_dec\fR" 4 +.IX Item "-fdump-rtl-auto_inc_dec" +Dump after auto-inc-dec discovery. This pass is only run on +architectures that have auto inc or auto dec instructions. +.IP "\fB\-fdump\-rtl\-barriers\fR" 4 +.IX Item "-fdump-rtl-barriers" +Dump after cleaning up the barrier instructions. +.IP "\fB\-fdump\-rtl\-bbpart\fR" 4 +.IX Item "-fdump-rtl-bbpart" +Dump after partitioning hot and cold basic blocks. +.IP "\fB\-fdump\-rtl\-bbro\fR" 4 +.IX Item "-fdump-rtl-bbro" +Dump after block reordering. +.IP "\fB\-fdump\-rtl\-btl1\fR" 4 +.IX Item "-fdump-rtl-btl1" +.PD 0 +.IP "\fB\-fdump\-rtl\-btl2\fR" 4 +.IX Item "-fdump-rtl-btl2" +.PD +\&\fB\-fdump\-rtl\-btl1\fR and \fB\-fdump\-rtl\-btl2\fR enable dumping +after the two branch +target load optimization passes. +.IP "\fB\-fdump\-rtl\-bypass\fR" 4 +.IX Item "-fdump-rtl-bypass" +Dump after jump bypassing and control flow optimizations. +.IP "\fB\-fdump\-rtl\-combine\fR" 4 +.IX Item "-fdump-rtl-combine" +Dump after the \s-1RTL\s0 instruction combination pass. +.IP "\fB\-fdump\-rtl\-compgotos\fR" 4 +.IX Item "-fdump-rtl-compgotos" +Dump after duplicating the computed gotos. +.IP "\fB\-fdump\-rtl\-ce1\fR" 4 +.IX Item "-fdump-rtl-ce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-ce2\fR" 4 +.IX Item "-fdump-rtl-ce2" +.IP "\fB\-fdump\-rtl\-ce3\fR" 4 +.IX Item "-fdump-rtl-ce3" +.PD +\&\fB\-fdump\-rtl\-ce1\fR, \fB\-fdump\-rtl\-ce2\fR, and +\&\fB\-fdump\-rtl\-ce3\fR enable dumping after the three +if conversion passes. +.IP "\fB\-fdump\-rtl\-cprop_hardreg\fR" 4 +.IX Item "-fdump-rtl-cprop_hardreg" +Dump after hard register copy propagation. +.IP "\fB\-fdump\-rtl\-csa\fR" 4 +.IX Item "-fdump-rtl-csa" +Dump after combining stack adjustments. +.IP "\fB\-fdump\-rtl\-cse1\fR" 4 +.IX Item "-fdump-rtl-cse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-cse2\fR" 4 +.IX Item "-fdump-rtl-cse2" +.PD +\&\fB\-fdump\-rtl\-cse1\fR and \fB\-fdump\-rtl\-cse2\fR enable dumping after +the two common subexpression elimination passes. +.IP "\fB\-fdump\-rtl\-dce\fR" 4 +.IX Item "-fdump-rtl-dce" +Dump after the standalone dead code elimination passes. +.IP "\fB\-fdump\-rtl\-dbr\fR" 4 +.IX Item "-fdump-rtl-dbr" +Dump after delayed branch scheduling. +.IP "\fB\-fdump\-rtl\-dce1\fR" 4 +.IX Item "-fdump-rtl-dce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-dce2\fR" 4 +.IX Item "-fdump-rtl-dce2" +.PD +\&\fB\-fdump\-rtl\-dce1\fR and \fB\-fdump\-rtl\-dce2\fR enable dumping after +the two dead store elimination passes. +.IP "\fB\-fdump\-rtl\-eh\fR" 4 +.IX Item "-fdump-rtl-eh" +Dump after finalization of \s-1EH\s0 handling code. +.IP "\fB\-fdump\-rtl\-eh_ranges\fR" 4 +.IX Item "-fdump-rtl-eh_ranges" +Dump after conversion of \s-1EH\s0 handling range regions. +.IP "\fB\-fdump\-rtl\-expand\fR" 4 +.IX Item "-fdump-rtl-expand" +Dump after \s-1RTL\s0 generation. +.IP "\fB\-fdump\-rtl\-fwprop1\fR" 4 +.IX Item "-fdump-rtl-fwprop1" +.PD 0 +.IP "\fB\-fdump\-rtl\-fwprop2\fR" 4 +.IX Item "-fdump-rtl-fwprop2" +.PD +\&\fB\-fdump\-rtl\-fwprop1\fR and \fB\-fdump\-rtl\-fwprop2\fR enable +dumping after the two forward propagation passes. +.IP "\fB\-fdump\-rtl\-gcse1\fR" 4 +.IX Item "-fdump-rtl-gcse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-gcse2\fR" 4 +.IX Item "-fdump-rtl-gcse2" +.PD +\&\fB\-fdump\-rtl\-gcse1\fR and \fB\-fdump\-rtl\-gcse2\fR enable dumping +after global common subexpression elimination. +.IP "\fB\-fdump\-rtl\-init\-regs\fR" 4 +.IX Item "-fdump-rtl-init-regs" +Dump after the initialization of the registers. +.IP "\fB\-fdump\-rtl\-initvals\fR" 4 +.IX Item "-fdump-rtl-initvals" +Dump after the computation of the initial value sets. +.IP "\fB\-fdump\-rtl\-into_cfglayout\fR" 4 +.IX Item "-fdump-rtl-into_cfglayout" +Dump after converting to cfglayout mode. +.IP "\fB\-fdump\-rtl\-ira\fR" 4 +.IX Item "-fdump-rtl-ira" +Dump after iterated register allocation. +.IP "\fB\-fdump\-rtl\-jump\fR" 4 +.IX Item "-fdump-rtl-jump" +Dump after the second jump optimization. +.IP "\fB\-fdump\-rtl\-loop2\fR" 4 +.IX Item "-fdump-rtl-loop2" +\&\fB\-fdump\-rtl\-loop2\fR enables dumping after the rtl +loop optimization passes. +.IP "\fB\-fdump\-rtl\-mach\fR" 4 +.IX Item "-fdump-rtl-mach" +Dump after performing the machine dependent reorganization pass, if that +pass exists. +.IP "\fB\-fdump\-rtl\-mode_sw\fR" 4 +.IX Item "-fdump-rtl-mode_sw" +Dump after removing redundant mode switches. +.IP "\fB\-fdump\-rtl\-rnreg\fR" 4 +.IX Item "-fdump-rtl-rnreg" +Dump after register renumbering. +.IP "\fB\-fdump\-rtl\-outof_cfglayout\fR" 4 +.IX Item "-fdump-rtl-outof_cfglayout" +Dump after converting from cfglayout mode. +.IP "\fB\-fdump\-rtl\-peephole2\fR" 4 +.IX Item "-fdump-rtl-peephole2" +Dump after the peephole pass. +.IP "\fB\-fdump\-rtl\-postreload\fR" 4 +.IX Item "-fdump-rtl-postreload" +Dump after post-reload optimizations. +.IP "\fB\-fdump\-rtl\-pro_and_epilogue\fR" 4 +.IX Item "-fdump-rtl-pro_and_epilogue" +Dump after generating the function prologues and epilogues. +.IP "\fB\-fdump\-rtl\-sched1\fR" 4 +.IX Item "-fdump-rtl-sched1" +.PD 0 +.IP "\fB\-fdump\-rtl\-sched2\fR" 4 +.IX Item "-fdump-rtl-sched2" +.PD +\&\fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR enable dumping +after the basic block scheduling passes. +.IP "\fB\-fdump\-rtl\-ree\fR" 4 +.IX Item "-fdump-rtl-ree" +Dump after sign/zero extension elimination. +.IP "\fB\-fdump\-rtl\-seqabstr\fR" 4 +.IX Item "-fdump-rtl-seqabstr" +Dump after common sequence discovery. +.IP "\fB\-fdump\-rtl\-shorten\fR" 4 +.IX Item "-fdump-rtl-shorten" +Dump after shortening branches. +.IP "\fB\-fdump\-rtl\-sibling\fR" 4 +.IX Item "-fdump-rtl-sibling" +Dump after sibling call optimizations. +.IP "\fB\-fdump\-rtl\-split1\fR" 4 +.IX Item "-fdump-rtl-split1" +.PD 0 +.IP "\fB\-fdump\-rtl\-split2\fR" 4 +.IX Item "-fdump-rtl-split2" +.IP "\fB\-fdump\-rtl\-split3\fR" 4 +.IX Item "-fdump-rtl-split3" +.IP "\fB\-fdump\-rtl\-split4\fR" 4 +.IX Item "-fdump-rtl-split4" +.IP "\fB\-fdump\-rtl\-split5\fR" 4 +.IX Item "-fdump-rtl-split5" +.PD +These options enable dumping after five rounds of +instruction splitting. +.IP "\fB\-fdump\-rtl\-sms\fR" 4 +.IX Item "-fdump-rtl-sms" +Dump after modulo scheduling. This pass is only run on some +architectures. +.IP "\fB\-fdump\-rtl\-stack\fR" 4 +.IX Item "-fdump-rtl-stack" +Dump after conversion from \s-1GCC\s0's \*(L"flat register file\*(R" registers to the +x87's stack-like registers. This pass is only run on x86 variants. +.IP "\fB\-fdump\-rtl\-subreg1\fR" 4 +.IX Item "-fdump-rtl-subreg1" +.PD 0 +.IP "\fB\-fdump\-rtl\-subreg2\fR" 4 +.IX Item "-fdump-rtl-subreg2" +.PD +\&\fB\-fdump\-rtl\-subreg1\fR and \fB\-fdump\-rtl\-subreg2\fR enable dumping after +the two subreg expansion passes. +.IP "\fB\-fdump\-rtl\-unshare\fR" 4 +.IX Item "-fdump-rtl-unshare" +Dump after all rtl has been unshared. +.IP "\fB\-fdump\-rtl\-vartrack\fR" 4 +.IX Item "-fdump-rtl-vartrack" +Dump after variable tracking. +.IP "\fB\-fdump\-rtl\-vregs\fR" 4 +.IX Item "-fdump-rtl-vregs" +Dump after converting virtual registers to hard registers. +.IP "\fB\-fdump\-rtl\-web\fR" 4 +.IX Item "-fdump-rtl-web" +Dump after live range splitting. +.IP "\fB\-fdump\-rtl\-regclass\fR" 4 +.IX Item "-fdump-rtl-regclass" +.PD 0 +.IP "\fB\-fdump\-rtl\-subregs_of_mode_init\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_init" +.IP "\fB\-fdump\-rtl\-subregs_of_mode_finish\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_finish" +.IP "\fB\-fdump\-rtl\-dfinit\fR" 4 +.IX Item "-fdump-rtl-dfinit" +.IP "\fB\-fdump\-rtl\-dfinish\fR" 4 +.IX Item "-fdump-rtl-dfinish" +.PD +These dumps are defined but always produce empty files. +.IP "\fB\-da\fR" 4 +.IX Item "-da" +.PD 0 +.IP "\fB\-fdump\-rtl\-all\fR" 4 +.IX Item "-fdump-rtl-all" +.PD +Produce all the dumps listed above. +.IP "\fB\-dA\fR" 4 +.IX Item "-dA" +Annotate the assembler output with miscellaneous debugging information. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Dump all macro definitions, at the end of preprocessing, in addition to +normal output. +.IP "\fB\-dH\fR" 4 +.IX Item "-dH" +Produce a core dump whenever an error occurs. +.IP "\fB\-dp\fR" 4 +.IX Item "-dp" +Annotate the assembler output with a comment indicating which +pattern and alternative is used. The length and cost of each instruction are +also printed. +.IP "\fB\-dP\fR" 4 +.IX Item "-dP" +Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction. +Also turns on \fB\-dp\fR annotation. +.IP "\fB\-dx\fR" 4 +.IX Item "-dx" +Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used +with \fB\-fdump\-rtl\-expand\fR. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-debug\fR" 4 +.IX Item "-fdump-debug" +Dump debugging information generated during the debug +generation phase. +.IP "\fB\-fdump\-earlydebug\fR" 4 +.IX Item "-fdump-earlydebug" +Dump debugging information generated during the early debug +generation phase. +.IP "\fB\-fdump\-noaddr\fR" 4 +.IX Item "-fdump-noaddr" +When doing debugging dumps, suppress address output. This makes it more +feasible to use diff on debugging dumps for compiler invocations with +different compiler binaries and/or different +text / bss / data / heap / stack / dso start locations. +.IP "\fB\-freport\-bug\fR" 4 +.IX Item "-freport-bug" +Collect and dump debug information into a temporary file if an +internal compiler error (\s-1ICE\s0) occurs. +.IP "\fB\-fdump\-unnumbered\fR" 4 +.IX Item "-fdump-unnumbered" +When doing debugging dumps, suppress instruction numbers and address output. +This makes it more feasible to use diff on debugging dumps for compiler +invocations with different options, in particular with and without +\&\fB\-g\fR. +.IP "\fB\-fdump\-unnumbered\-links\fR" 4 +.IX Item "-fdump-unnumbered-links" +When doing debugging dumps (see \fB\-d\fR option above), suppress +instruction numbers for the links to the previous and next instructions +in a sequence. +.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-ipa-switch" +.PD 0 +.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-ipa-switch-options" +.PD +Control the dumping at various stages of inter-procedural analysis +language tree to a file. The file name is generated by appending a +switch specific suffix to the source file name, and the file is created +in the same directory as the output file. The following dumps are +possible: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enables all inter-procedural analysis dumps. +.IP "\fBcgraph\fR" 4 +.IX Item "cgraph" +Dumps information about call-graph optimization, unused function removal, +and inlining decisions. +.IP "\fBinline\fR" 4 +.IX Item "inline" +Dump after function inlining. +.RE +.RS 4 +.Sp +Additionally, the options \fB\-optimized\fR, \fB\-missed\fR, +\&\fB\-note\fR, and \fB\-all\fR can be provided, with the same meaning +as for \fB\-fopt\-info\fR, defaulting to \fB\-optimized\fR. +.Sp +For example, \fB\-fdump\-ipa\-inline\-optimized\-missed\fR will emit +information on callsites that were inlined, along with callsites +that were not inlined. +.Sp +By default, the dump will contain messages about successful +optimizations (equivalent to \fB\-optimized\fR) together with +low-level details about the analysis. +.RE +.IP "\fB\-fdump\-lang\-all\fR" 4 +.IX Item "-fdump-lang-all" +.PD 0 +.IP "\fB\-fdump\-lang\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-lang-switch" +.IP "\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-lang-switch-options" +.IP "\fB\-fdump\-lang\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fdump-lang-switch-options=filename" +.PD +Control the dumping of language-specific information. The \fIoptions\fR +and \fIfilename\fR portions behave as described in the +\&\fB\-fdump\-tree\fR option. The following \fIswitch\fR values are +accepted: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all language-specific dumps. +.IP "\fBclass\fR" 4 +.IX Item "class" +Dump class hierarchy information. Virtual table information is emitted +unless '\fBslim\fR' is specified. This option is applicable to \*(C+ only. +.IP "\fBraw\fR" 4 +.IX Item "raw" +Dump the raw internal tree data. This option is applicable to \*(C+ only. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-passes\fR" 4 +.IX Item "-fdump-passes" +Print on \fIstderr\fR the list of optimization passes that are turned +on and off by the current command-line options. +.IP "\fB\-fdump\-statistics\-\fR\fIoption\fR" 4 +.IX Item "-fdump-statistics-option" +Enable and control dumping of pass statistics in a separate file. The +file name is generated by appending a suffix ending in +\&\fB.statistics\fR to the source file name, and the file is created in +the same directory as the output file. If the \fB\-\fR\fIoption\fR +form is used, \fB\-stats\fR causes counters to be summed over the +whole compilation unit while \fB\-details\fR dumps every event as +the passes generate them. The default with no option is to sum +counters for each function compiled. +.IP "\fB\-fdump\-tree\-all\fR" 4 +.IX Item "-fdump-tree-all" +.PD 0 +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-tree-switch" +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-tree-switch-options" +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fdump-tree-switch-options=filename" +.PD +Control the dumping at various stages of processing the intermediate +language tree to a file. If the \fB\-\fR\fIoptions\fR +form is used, \fIoptions\fR is a list of \fB\-\fR separated options +which control the details of the dump. Not all options are applicable +to all dumps; those that are not meaningful are ignored. The +following options are available +.RS 4 +.IP "\fBaddress\fR" 4 +.IX Item "address" +Print the address of each node. Usually this is not meaningful as it +changes according to the environment and source file. Its primary use +is for tying up a dump file with a debug environment. +.IP "\fBasmname\fR" 4 +.IX Item "asmname" +If \f(CW\*(C`DECL_ASSEMBLER_NAME\*(C'\fR has been set for a given decl, use that +in the dump instead of \f(CW\*(C`DECL_NAME\*(C'\fR. Its primary use is ease of +use working backward from mangled names in the assembly file. +.IP "\fBslim\fR" 4 +.IX Item "slim" +When dumping front-end intermediate representations, inhibit dumping +of members of a scope or body of a function merely because that scope +has been reached. Only dump such items when they are directly reachable +by some other path. +.Sp +When dumping pretty-printed trees, this option inhibits dumping the +bodies of control structures. +.Sp +When dumping \s-1RTL,\s0 print the \s-1RTL\s0 in slim (condensed) form instead of +the default LISP-like representation. +.IP "\fBraw\fR" 4 +.IX Item "raw" +Print a raw representation of the tree. By default, trees are +pretty-printed into a C\-like representation. +.IP "\fBdetails\fR" 4 +.IX Item "details" +Enable more detailed dumps (not honored by every dump option). Also +include information from the optimization passes. +.IP "\fBstats\fR" 4 +.IX Item "stats" +Enable dumping various statistics about the pass (not honored by every dump +option). +.IP "\fBblocks\fR" 4 +.IX Item "blocks" +Enable showing basic block boundaries (disabled in raw dumps). +.IP "\fBgraph\fR" 4 +.IX Item "graph" +For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR), +dump a representation of the control flow graph suitable for viewing with +GraphViz to \fI\fIfile\fI.\fIpassid\fI.\fIpass\fI.dot\fR. Each function in +the file is pretty-printed as a subgraph, so that GraphViz can render them +all in a single plot. +.Sp +This option currently only works for \s-1RTL\s0 dumps, and the \s-1RTL\s0 is always +dumped in slim form. +.IP "\fBvops\fR" 4 +.IX Item "vops" +Enable showing virtual operands for every statement. +.IP "\fBlineno\fR" 4 +.IX Item "lineno" +Enable showing line numbers for statements. +.IP "\fBuid\fR" 4 +.IX Item "uid" +Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +.IP "\fBverbose\fR" 4 +.IX Item "verbose" +Enable showing the tree dump for each statement. +.IP "\fBeh\fR" 4 +.IX Item "eh" +Enable showing the \s-1EH\s0 region number holding each statement. +.IP "\fBscev\fR" 4 +.IX Item "scev" +Enable showing scalar evolution analysis details. +.IP "\fBoptimized\fR" 4 +.IX Item "optimized" +Enable showing optimization information (only available in certain +passes). +.IP "\fBmissed\fR" 4 +.IX Item "missed" +Enable showing missed optimization information (only available in certain +passes). +.IP "\fBnote\fR" 4 +.IX Item "note" +Enable other detailed optimization information (only available in +certain passes). +.IP "\fBall\fR" 4 +.IX Item "all" +Turn on all options, except \fBraw\fR, \fBslim\fR, \fBverbose\fR +and \fBlineno\fR. +.IP "\fBoptall\fR" 4 +.IX Item "optall" +Turn on all optimization options, i.e., \fBoptimized\fR, +\&\fBmissed\fR, and \fBnote\fR. +.RE +.RS 4 +.Sp +To determine what tree dumps are available or find the dump for a pass +of interest follow the steps below. +.IP "1." 4 +.IX Item "1." +Invoke \s-1GCC\s0 with \fB\-fdump\-passes\fR and in the \fIstderr\fR output +look for a code that corresponds to the pass you are interested in. +For example, the codes \f(CW\*(C`tree\-evrp\*(C'\fR, \f(CW\*(C`tree\-vrp1\*(C'\fR, and +\&\f(CW\*(C`tree\-vrp2\*(C'\fR correspond to the three Value Range Propagation passes. +The number at the end distinguishes distinct invocations of the same pass. +.IP "2." 4 +.IX Item "2." +To enable the creation of the dump file, append the pass code to +the \fB\-fdump\-\fR option prefix and invoke \s-1GCC\s0 with it. For example, +to enable the dump from the Early Value Range Propagation pass, invoke +\&\s-1GCC\s0 with the \fB\-fdump\-tree\-evrp\fR option. Optionally, you may +specify the name of the dump file. If you don't specify one, \s-1GCC\s0 +creates as described below. +.IP "3." 4 +.IX Item "3." +Find the pass dump in a file whose name is composed of three components +separated by a period: the name of the source file \s-1GCC\s0 was invoked to +compile, a numeric suffix indicating the pass number followed by the +letter \fBt\fR for tree passes (and the letter \fBr\fR for \s-1RTL\s0 passes), +and finally the pass code. For example, the Early \s-1VRP\s0 pass dump might +be in a file named \fImyfile.c.038t.evrp\fR in the current working +directory. Note that the numeric codes are not stable and may change +from one version of \s-1GCC\s0 to another. +.RE +.RS 4 +.RE +.IP "\fB\-fopt\-info\fR" 4 +.IX Item "-fopt-info" +.PD 0 +.IP "\fB\-fopt\-info\-\fR\fIoptions\fR" 4 +.IX Item "-fopt-info-options" +.IP "\fB\-fopt\-info\-\fR\fIoptions\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "-fopt-info-options=filename" +.PD +Controls optimization dumps from various optimization passes. If the +\&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of +\&\fB\-\fR separated option keywords to select the dump details and +optimizations. +.Sp +The \fIoptions\fR can be divided into three groups: +.RS 4 +.IP "1." 4 +.IX Item "1." +options describing what kinds of messages should be emitted, +.IP "2." 4 +.IX Item "2." +options describing the verbosity of the dump, and +.IP "3." 4 +.IX Item "3." +options describing which optimizations should be included. +.RE +.RS 4 +.Sp +The options from each group can be freely mixed as they are +non-overlapping. However, in case of any conflicts, +the later options override the earlier options on the command +line. +.Sp +The following options control which kinds of messages should be emitted: +.IP "\fBoptimized\fR" 4 +.IX Item "optimized" +Print information when an optimization is successfully applied. It is +up to a pass to decide which information is relevant. For example, the +vectorizer passes print the source location of loops which are +successfully vectorized. +.IP "\fBmissed\fR" 4 +.IX Item "missed" +Print information about missed optimizations. Individual passes +control which information to include in the output. +.IP "\fBnote\fR" 4 +.IX Item "note" +Print verbose information about optimizations, such as certain +transformations, more detailed messages about decisions etc. +.IP "\fBall\fR" 4 +.IX Item "all" +Print detailed optimization information. This includes +\&\fBoptimized\fR, \fBmissed\fR, and \fBnote\fR. +.RE +.RS 4 +.Sp +The following option controls the dump verbosity: +.IP "\fBinternals\fR" 4 +.IX Item "internals" +By default, only \*(L"high-level\*(R" messages are emitted. This option enables +additional, more detailed, messages, which are likely to only be of interest +to \s-1GCC\s0 developers. +.RE +.RS 4 +.Sp +One or more of the following option keywords can be used to describe a +group of optimizations: +.IP "\fBipa\fR" 4 +.IX Item "ipa" +Enable dumps from all interprocedural optimizations. +.IP "\fBloop\fR" 4 +.IX Item "loop" +Enable dumps from all loop optimizations. +.IP "\fBinline\fR" 4 +.IX Item "inline" +Enable dumps from all inlining optimizations. +.IP "\fBomp\fR" 4 +.IX Item "omp" +Enable dumps from all \s-1OMP\s0 (Offloading and Multi Processing) optimizations. +.IP "\fBvec\fR" 4 +.IX Item "vec" +Enable dumps from all vectorization optimizations. +.IP "\fBoptall\fR" 4 +.IX Item "optall" +Enable dumps from all optimizations. This is a superset of +the optimization groups listed above. +.RE +.RS 4 +.Sp +If \fIoptions\fR is +omitted, it defaults to \fBoptimized-optall\fR, which means to dump messages +about successful optimizations from all the passes, omitting messages +that are treated as \*(L"internals\*(R". +.Sp +If the \fIfilename\fR is provided, then the dumps from all the +applicable optimizations are concatenated into the \fIfilename\fR. +Otherwise the dump is output onto \fIstderr\fR. Though multiple +\&\fB\-fopt\-info\fR options are accepted, only one of them can include +a \fIfilename\fR. If other filenames are provided then all but the +first such option are ignored. +.Sp +Note that the output \fIfilename\fR is overwritten +in case of multiple translation units. If a combined output from +multiple translation units is desired, \fIstderr\fR should be used +instead. +.Sp +In the following example, the optimization info is output to +\&\fIstderr\fR: +.Sp +.Vb 1 +\& gcc \-O3 \-fopt\-info +.Ve +.Sp +This example: +.Sp +.Vb 1 +\& gcc \-O3 \-fopt\-info\-missed=missed.all +.Ve +.Sp +outputs missed optimization report from all the passes into +\&\fImissed.all\fR, and this one: +.Sp +.Vb 1 +\& gcc \-O2 \-ftree\-vectorize \-fopt\-info\-vec\-missed +.Ve +.Sp +prints information about missed optimization opportunities from +vectorization passes on \fIstderr\fR. +Note that \fB\-fopt\-info\-vec\-missed\fR is equivalent to +\&\fB\-fopt\-info\-missed\-vec\fR. The order of the optimization group +names and message types listed after \fB\-fopt\-info\fR does not matter. +.Sp +As another example, +.Sp +.Vb 1 +\& gcc \-O3 \-fopt\-info\-inline\-optimized\-missed=inline.txt +.Ve +.Sp +outputs information about missed optimizations as well as +optimized locations from all the inlining passes into +\&\fIinline.txt\fR. +.Sp +Finally, consider: +.Sp +.Vb 1 +\& gcc \-fopt\-info\-vec\-missed=vec.miss \-fopt\-info\-loop\-optimized=loop.opt +.Ve +.Sp +Here the two output filenames \fIvec.miss\fR and \fIloop.opt\fR are +in conflict since only one output file is allowed. In this case, only +the first option takes effect and the subsequent options are +ignored. Thus only \fIvec.miss\fR is produced which contains +dumps from the vectorizer about missed opportunities. +.RE +.IP "\fB\-fsave\-optimization\-record\fR" 4 +.IX Item "-fsave-optimization-record" +Write a \s-1SRCFILE\s0.opt\-record.json.gz file detailing what optimizations +were performed, for those optimizations that support \fB\-fopt\-info\fR. +.Sp +This option is experimental and the format of the data within the +compressed \s-1JSON\s0 file is subject to change. +.Sp +It is roughly equivalent to a machine-readable version of +\&\fB\-fopt\-info\-all\fR, as a collection of messages with source file, +line number and column number, with the following additional data for +each message: +.RS 4 +.IP "*" 4 +the execution count of the code being optimized, along with metadata about +whether this was from actual profile data, or just an estimate, allowing +consumers to prioritize messages by code hotness, +.IP "*" 4 +the function name of the code being optimized, where applicable, +.IP "*" 4 +the \*(L"inlining chain\*(R" for the code being optimized, so that when +a function is inlined into several different places (which might +themselves be inlined), the reader can distinguish between the copies, +.IP "*" 4 +objects identifying those parts of the message that refer to expressions, +statements or symbol-table nodes, which of these categories they are, and, +when available, their source code location, +.IP "*" 4 +the \s-1GCC\s0 pass that emitted the message, and +.IP "*" 4 +the location in \s-1GCC\s0's own code from which the message was emitted +.RE +.RS 4 +.Sp +Additionally, some messages are logically nested within other +messages, reflecting implementation details of the optimization +passes. +.RE +.IP "\fB\-fsched\-verbose=\fR\fIn\fR" 4 +.IX Item "-fsched-verbose=n" +On targets that use instruction scheduling, this option controls the +amount of debugging output the scheduler prints to the dump files. +.Sp +For \fIn\fR greater than zero, \fB\-fsched\-verbose\fR outputs the +same information as \fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR. +For \fIn\fR greater than one, it also output basic block probabilities, +detailed ready list information and unit/insn info. For \fIn\fR greater +than two, it includes \s-1RTL\s0 at abort point, control-flow and regions info. +And for \fIn\fR over four, \fB\-fsched\-verbose\fR also includes +dependence info. +.IP "\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR" 4 +.IX Item "-fenable-kind-pass" +.PD 0 +.IP "\fB\-fdisable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-kind-pass=range-list" +.PD +This is a set of options that are used to explicitly disable/enable +optimization passes. These options are intended for use for debugging \s-1GCC.\s0 +Compiler users should use regular options for enabling/disabling +passes instead. +.RS 4 +.IP "\fB\-fdisable\-ipa\-\fR\fIpass\fR" 4 +.IX Item "-fdisable-ipa-pass" +Disable \s-1IPA\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "\fB\-fdisable\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fdisable-rtl-pass" +.PD 0 +.IP "\fB\-fdisable\-rtl\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-rtl-pass=range-list" +.PD +Disable \s-1RTL\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. \fIrange-list\fR is a +comma-separated list of function ranges or assembler names. Each range is a number +pair separated by a colon. The range is inclusive in both ends. If the range +is trivial, the number pair can be simplified as a single number. If the +function's call graph node's \fIuid\fR falls within one of the specified ranges, +the \fIpass\fR is disabled for that function. The \fIuid\fR is shown in the +function header of a dump file, and the pass names can be dumped by using +option \fB\-fdump\-passes\fR. +.IP "\fB\-fdisable\-tree\-\fR\fIpass\fR" 4 +.IX Item "-fdisable-tree-pass" +.PD 0 +.IP "\fB\-fdisable\-tree\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-tree-pass=range-list" +.PD +Disable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description of +option arguments. +.IP "\fB\-fenable\-ipa\-\fR\fIpass\fR" 4 +.IX Item "-fenable-ipa-pass" +Enable \s-1IPA\s0 pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "\fB\-fenable\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fenable-rtl-pass" +.PD 0 +.IP "\fB\-fenable\-rtl\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fenable-rtl-pass=range-list" +.PD +Enable \s-1RTL\s0 pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument +description and examples. +.IP "\fB\-fenable\-tree\-\fR\fIpass\fR" 4 +.IX Item "-fenable-tree-pass" +.PD 0 +.IP "\fB\-fenable\-tree\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fenable-tree-pass=range-list" +.PD +Enable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description +of option arguments. +.RE +.RS 4 +.Sp +Here are some examples showing uses of these options. +.Sp +.Vb 10 +\& # disable ccp1 for all functions +\& \-fdisable\-tree\-ccp1 +\& # disable complete unroll for function whose cgraph node uid is 1 +\& \-fenable\-tree\-cunroll=1 +\& # disable gcse2 for functions at the following ranges [1,1], +\& # [300,400], and [400,1000] +\& # disable gcse2 for functions foo and foo2 +\& \-fdisable\-rtl\-gcse2=foo,foo2 +\& # disable early inlining +\& \-fdisable\-tree\-einline +\& # disable ipa inlining +\& \-fdisable\-ipa\-inline +\& # enable tree full unroll +\& \-fenable\-tree\-unroll +.Ve +.RE +.IP "\fB\-fchecking\fR" 4 +.IX Item "-fchecking" +.PD 0 +.IP "\fB\-fchecking=\fR\fIn\fR" 4 +.IX Item "-fchecking=n" +.PD +Enable internal consistency checking. The default depends on +the compiler configuration. \fB\-fchecking=2\fR enables further +internal consistency checking that might affect code generation. +.IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4 +.IX Item "-frandom-seed=string" +This option provides a seed that \s-1GCC\s0 uses in place of +random numbers in generating certain symbol names +that have to be different in every compiled file. It is also used to +place unique stamps in coverage data files and the object files that +produce them. You can use the \fB\-frandom\-seed\fR option to produce +reproducibly identical object files. +.Sp +The \fIstring\fR can either be a number (decimal, octal or hex) or an +arbitrary string (in which case it's converted to a number by +computing \s-1CRC32\s0). +.Sp +The \fIstring\fR should be different for every file you compile. +.IP "\fB\-save\-temps\fR" 4 +.IX Item "-save-temps" +.PD 0 +.IP "\fB\-save\-temps=cwd\fR" 4 +.IX Item "-save-temps=cwd" +.PD +Store the usual \*(L"temporary\*(R" intermediate files permanently; place them +in the current directory and name them based on the source file. Thus, +compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR produces files +\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a +preprocessed \fIfoo.i\fR output file even though the compiler now +normally uses an integrated preprocessor. +.Sp +When used in combination with the \fB\-x\fR command-line option, +\&\fB\-save\-temps\fR is sensible enough to avoid over writing an +input source file with the same extension as an intermediate file. +The corresponding intermediate file may be obtained by renaming the +source file before using \fB\-save\-temps\fR. +.Sp +If you invoke \s-1GCC\s0 in parallel, compiling several different source +files that share a common base name in different subdirectories or the +same source file compiled for multiple output destinations, it is +likely that the different parallel compilers will interfere with each +other, and overwrite the temporary files. For instance: +.Sp +.Vb 2 +\& gcc \-save\-temps \-o outdir1/foo.o indir1/foo.c& +\& gcc \-save\-temps \-o outdir2/foo.o indir2/foo.c& +.Ve +.Sp +may result in \fIfoo.i\fR and \fIfoo.o\fR being written to +simultaneously by both compilers. +.IP "\fB\-save\-temps=obj\fR" 4 +.IX Item "-save-temps=obj" +Store the usual \*(L"temporary\*(R" intermediate files permanently. If the +\&\fB\-o\fR option is used, the temporary files are based on the +object file. If the \fB\-o\fR option is not used, the +\&\fB\-save\-temps=obj\fR switch behaves like \fB\-save\-temps\fR. +.Sp +For example: +.Sp +.Vb 3 +\& gcc \-save\-temps=obj \-c foo.c +\& gcc \-save\-temps=obj \-c bar.c \-o dir/xbar.o +\& gcc \-save\-temps=obj foobar.c \-o dir2/yfoobar +.Ve +.Sp +creates \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR, +\&\fIdir/xbar.s\fR, \fIdir2/yfoobar.i\fR, \fIdir2/yfoobar.s\fR, and +\&\fIdir2/yfoobar.o\fR. +.IP "\fB\-time\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-time[=file]" +Report the \s-1CPU\s0 time taken by each subprocess in the compilation +sequence. For C source files, this is the compiler proper and assembler +(plus the linker if linking is done). +.Sp +Without the specification of an output file, the output looks like this: +.Sp +.Vb 2 +\& # cc1 0.12 0.01 +\& # as 0.00 0.01 +.Ve +.Sp +The first number on each line is the \*(L"user time\*(R", that is time spent +executing the program itself. The second number is \*(L"system time\*(R", +time spent executing operating system routines on behalf of the program. +Both numbers are in seconds. +.Sp +With the specification of an output file, the output is appended to the +named file, and it looks like this: +.Sp +.Vb 2 +\& 0.12 0.01 cc1 +\& 0.00 0.01 as +.Ve +.Sp +The \*(L"user time\*(R" and the \*(L"system time\*(R" are moved before the program +name, and the options passed to the program are displayed, so that one +can later tell what file was being compiled, and with which options. +.IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-fdump-final-insns[=file]" +Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the +optional argument is omitted (or if \fIfile\fR is \f(CW\*(C`.\*(C'\fR), the name +of the dump file is determined by appending \f(CW\*(C`.gkd\*(C'\fR to the +compilation output file name. +.IP "\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR]" 4 +.IX Item "-fcompare-debug[=opts]" +If no error occurs during compilation, run the compiler a second time, +adding \fIopts\fR and \fB\-fcompare\-debug\-second\fR to the arguments +passed to the second compilation. Dump the final internal +representation in both compilations, and print an error if they differ. +.Sp +If the equal sign is omitted, the default \fB\-gtoggle\fR is used. +.Sp +The environment variable \fB\s-1GCC_COMPARE_DEBUG\s0\fR, if defined, non-empty +and nonzero, implicitly enables \fB\-fcompare\-debug\fR. If +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR is defined to a string starting with a dash, +then it is used for \fIopts\fR, otherwise the default \fB\-gtoggle\fR +is used. +.Sp +\&\fB\-fcompare\-debug=\fR, with the equal sign but without \fIopts\fR, +is equivalent to \fB\-fno\-compare\-debug\fR, which disables the dumping +of the final representation and the second compilation, preventing even +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR from taking effect. +.Sp +To verify full coverage during \fB\-fcompare\-debug\fR testing, set +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR to say \fB\-fcompare\-debug\-not\-overridden\fR, +which \s-1GCC\s0 rejects as an invalid option in any actual compilation +(rather than preprocessing, assembly or linking). To get just a +warning, setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR to \fB\-w%n\-fcompare\-debug +not overridden\fR will do. +.IP "\fB\-fcompare\-debug\-second\fR" 4 +.IX Item "-fcompare-debug-second" +This option is implicitly passed to the compiler for the second +compilation requested by \fB\-fcompare\-debug\fR, along with options to +silence warnings, and omitting other options that would cause the compiler +to produce output to files or to standard output as a side effect. Dump +files and preserved temporary files are renamed so as to contain the +\&\f(CW\*(C`.gk\*(C'\fR additional extension during the second compilation, to avoid +overwriting those generated by the first. +.Sp +When this option is passed to the compiler driver, it causes the +\&\fIfirst\fR compilation to be skipped, which makes it useful for little +other than debugging the compiler proper. +.IP "\fB\-gtoggle\fR" 4 +.IX Item "-gtoggle" +Turn off generation of debug info, if leaving out this option +generates it, or turn it on at level 2 otherwise. The position of this +argument in the command line does not matter; it takes effect after all +other options are processed, and it does so only once, no matter how +many times it is given. This is mainly intended to be used with +\&\fB\-fcompare\-debug\fR. +.IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4 +.IX Item "-fvar-tracking-assignments-toggle" +Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that +\&\fB\-gtoggle\fR toggles \fB\-g\fR. +.IP "\fB\-Q\fR" 4 +.IX Item "-Q" +Makes the compiler print out each function name as it is compiled, and +print some statistics about each pass when it finishes. +.IP "\fB\-ftime\-report\fR" 4 +.IX Item "-ftime-report" +Makes the compiler print some statistics about the time consumed by each +pass when it finishes. +.IP "\fB\-ftime\-report\-details\fR" 4 +.IX Item "-ftime-report-details" +Record the time consumed by infrastructure parts separately for each pass. +.IP "\fB\-fira\-verbose=\fR\fIn\fR" 4 +.IX Item "-fira-verbose=n" +Control the verbosity of the dump file for the integrated register allocator. +The default value is 5. If the value \fIn\fR is greater or equal to 10, +the dump output is sent to stderr using the same format as \fIn\fR minus 10. +.IP "\fB\-flto\-report\fR" 4 +.IX Item "-flto-report" +Prints a report with internal details on the workings of the link-time +optimizer. The contents of this report vary from version to version. +It is meant to be useful to \s-1GCC\s0 developers when processing object +files in \s-1LTO\s0 mode (via \fB\-flto\fR). +.Sp +Disabled by default. +.IP "\fB\-flto\-report\-wpa\fR" 4 +.IX Item "-flto-report-wpa" +Like \fB\-flto\-report\fR, but only print for the \s-1WPA\s0 phase of Link +Time Optimization. +.IP "\fB\-fmem\-report\fR" 4 +.IX Item "-fmem-report" +Makes the compiler print some statistics about permanent memory +allocation when it finishes. +.IP "\fB\-fmem\-report\-wpa\fR" 4 +.IX Item "-fmem-report-wpa" +Makes the compiler print some statistics about permanent memory +allocation for the \s-1WPA\s0 phase only. +.IP "\fB\-fpre\-ipa\-mem\-report\fR" 4 +.IX Item "-fpre-ipa-mem-report" +.PD 0 +.IP "\fB\-fpost\-ipa\-mem\-report\fR" 4 +.IX Item "-fpost-ipa-mem-report" +.PD +Makes the compiler print some statistics about permanent memory +allocation before or after interprocedural optimization. +.IP "\fB\-fprofile\-report\fR" 4 +.IX Item "-fprofile-report" +Makes the compiler print some statistics about consistency of the +(estimated) profile and effect of individual passes. +.IP "\fB\-fstack\-usage\fR" 4 +.IX Item "-fstack-usage" +Makes the compiler output stack usage information for the program, on a +per-function basis. The filename for the dump is made by appending +\&\fI.su\fR to the \fIauxname\fR. \fIauxname\fR is generated from the name of +the output file, if explicitly specified and it is not an executable, +otherwise it is the basename of the source file. An entry is made up +of three fields: +.RS 4 +.IP "*" 4 +The name of the function. +.IP "*" 4 +A number of bytes. +.IP "*" 4 +One or more qualifiers: \f(CW\*(C`static\*(C'\fR, \f(CW\*(C`dynamic\*(C'\fR, \f(CW\*(C`bounded\*(C'\fR. +.RE +.RS 4 +.Sp +The qualifier \f(CW\*(C`static\*(C'\fR means that the function manipulates the stack +statically: a fixed number of bytes are allocated for the frame on function +entry and released on function exit; no stack adjustments are otherwise made +in the function. The second field is this fixed number of bytes. +.Sp +The qualifier \f(CW\*(C`dynamic\*(C'\fR means that the function manipulates the stack +dynamically: in addition to the static allocation described above, stack +adjustments are made in the body of the function, for example to push/pop +arguments around function calls. If the qualifier \f(CW\*(C`bounded\*(C'\fR is also +present, the amount of these adjustments is bounded at compile time and +the second field is an upper bound of the total amount of stack used by +the function. If it is not present, the amount of these adjustments is +not bounded at compile time and the second field only represents the +bounded part. +.RE +.IP "\fB\-fstats\fR" 4 +.IX Item "-fstats" +Emit statistics about front-end processing at the end of the compilation. +This option is supported only by the \*(C+ front end, and +the information is generally only useful to the G++ development team. +.IP "\fB\-fdbg\-cnt\-list\fR" 4 +.IX Item "-fdbg-cnt-list" +Print the name and the counter upper bound for all debug counters. +.IP "\fB\-fdbg\-cnt=\fR\fIcounter-value-list\fR" 4 +.IX Item "-fdbg-cnt=counter-value-list" +Set the internal debug counter lower and upper bound. \fIcounter-value-list\fR +is a comma-separated list of \fIname\fR:\fIlower_bound\fR:\fIupper_bound\fR +tuples which sets the lower and the upper bound of each debug +counter \fIname\fR. The \fIlower_bound\fR is optional and is zero +initialized if not set. +All debug counters have the initial upper bound of \f(CW\*(C`UINT_MAX\*(C'\fR; +thus \f(CW\*(C`dbg_cnt\*(C'\fR returns true always unless the upper bound +is set by this option. +For example, with \fB\-fdbg\-cnt=dce:2:4,tail_call:10\fR, +\&\f(CW\*(C`dbg_cnt(dce)\*(C'\fR returns true only for third and fourth invocation. +For \f(CW\*(C`dbg_cnt(tail_call)\*(C'\fR true is returned for first 10 invocations. +.IP "\fB\-print\-file\-name=\fR\fIlibrary\fR" 4 +.IX Item "-print-file-name=library" +Print the full absolute name of the library file \fIlibrary\fR that +would be used when linking\-\-\-and don't do anything else. With this +option, \s-1GCC\s0 does not compile or link anything; it just prints the +file name. +.IP "\fB\-print\-multi\-directory\fR" 4 +.IX Item "-print-multi-directory" +Print the directory name corresponding to the multilib selected by any +other switches present in the command line. This directory is supposed +to exist in \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\-print\-multi\-lib\fR" 4 +.IX Item "-print-multi-lib" +Print the mapping from multilib directory names to compiler switches +that enable them. The directory name is separated from the switches by +\&\fB;\fR, and each switch starts with an \fB@\fR instead of the +\&\fB\-\fR, without spaces between multiple switches. This is supposed to +ease shell processing. +.IP "\fB\-print\-multi\-os\-directory\fR" 4 +.IX Item "-print-multi-os-directory" +Print the path to \s-1OS\s0 libraries for the selected +multilib, relative to some \fIlib\fR subdirectory. If \s-1OS\s0 libraries are +present in the \fIlib\fR subdirectory and no multilibs are used, this is +usually just \fI.\fR, if \s-1OS\s0 libraries are present in \fIlib\fIsuffix\fI\fR +sibling directories this prints e.g. \fI../lib64\fR, \fI../lib\fR or +\&\fI../lib32\fR, or if \s-1OS\s0 libraries are present in \fIlib/\fIsubdir\fI\fR +subdirectories it prints e.g. \fIamd64\fR, \fIsparcv9\fR or \fIev6\fR. +.IP "\fB\-print\-multiarch\fR" 4 +.IX Item "-print-multiarch" +Print the path to \s-1OS\s0 libraries for the selected multiarch, +relative to some \fIlib\fR subdirectory. +.IP "\fB\-print\-prog\-name=\fR\fIprogram\fR" 4 +.IX Item "-print-prog-name=program" +Like \fB\-print\-file\-name\fR, but searches for a program such as \fBcpp\fR. +.IP "\fB\-print\-libgcc\-file\-name\fR" 4 +.IX Item "-print-libgcc-file-name" +Same as \fB\-print\-file\-name=libgcc.a\fR. +.Sp +This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR +but you do want to link with \fIlibgcc.a\fR. You can do: +.Sp +.Vb 1 +\& gcc \-nostdlib ... \`gcc \-print\-libgcc\-file\-name\` +.Ve +.IP "\fB\-print\-search\-dirs\fR" 4 +.IX Item "-print-search-dirs" +Print the name of the configured installation directory and a list of +program and library directories \fBgcc\fR searches\-\-\-and don't do anything else. +.Sp +This is useful when \fBgcc\fR prints the error message +\&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR. +To resolve this you either need to put \fIcpp0\fR and the other compiler +components where \fBgcc\fR expects to find them, or you can set the environment +variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them. +Don't forget the trailing \fB/\fR. +.IP "\fB\-print\-sysroot\fR" 4 +.IX Item "-print-sysroot" +Print the target sysroot directory that is used during +compilation. This is the target sysroot specified either at configure +time or using the \fB\-\-sysroot\fR option, possibly with an extra +suffix that depends on compilation options. If no target sysroot is +specified, the option prints nothing. +.IP "\fB\-print\-sysroot\-headers\-suffix\fR" 4 +.IX Item "-print-sysroot-headers-suffix" +Print the suffix added to the target sysroot when searching for +headers, or give an error if the compiler is not configured with such +a suffix\-\-\-and don't do anything else. +.IP "\fB\-dumpmachine\fR" 4 +.IX Item "-dumpmachine" +Print the compiler's target machine (for example, +\&\fBi686\-pc\-linux\-gnu\fR)\-\-\-and don't do anything else. +.IP "\fB\-dumpversion\fR" 4 +.IX Item "-dumpversion" +Print the compiler version (for example, \f(CW3.0\fR, \f(CW6.3.0\fR or \f(CW7\fR)\-\-\-and don't do +anything else. This is the compiler version used in filesystem paths and +specs. Depending on how the compiler has been configured it can be just +a single number (major version), two numbers separated by a dot (major and +minor version) or three numbers separated by dots (major, minor and patchlevel +version). +.IP "\fB\-dumpfullversion\fR" 4 +.IX Item "-dumpfullversion" +Print the full compiler version\-\-\-and don't do anything else. The output is +always three numbers separated by dots, major, minor and patchlevel version. +.IP "\fB\-dumpspecs\fR" 4 +.IX Item "-dumpspecs" +Print the compiler's built-in specs\-\-\-and don't do anything else. (This +is used when \s-1GCC\s0 itself is being built.) +.SS "Machine-Dependent Options" +.IX Subsection "Machine-Dependent Options" +Each target machine supported by \s-1GCC\s0 can have its own options\-\-\-for +example, to allow you to compile for a particular processor variant or +\&\s-1ABI,\s0 or to control optimizations specific to that machine. By +convention, the names of machine-specific options start with +\&\fB\-m\fR. +.PP +Some configurations of the compiler also support additional target-specific +options, usually for compatibility with other compilers on the same +platform. +.PP +\fIAArch64 Options\fR +.IX Subsection "AArch64 Options" +.PP +These options are defined for AArch64 implementations: +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified data model. Permissible values +are \fBilp32\fR for SysV-like data model where int, long int and pointers +are 32 bits, and \fBlp64\fR for SysV-like data model where int is 32 bits, +but long int and pointers are 64 bits. +.Sp +The default depends on the specific target configuration. Note that +the \s-1LP64\s0 and \s-1ILP32\s0 ABIs are not link-compatible; you must compile your +entire program with the same \s-1ABI,\s0 and link with a compatible set of libraries. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate big-endian code. This is the default when \s-1GCC\s0 is configured for an +\&\fBaarch64_be\-*\-*\fR target. +.IP "\fB\-mgeneral\-regs\-only\fR" 4 +.IX Item "-mgeneral-regs-only" +Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced \s-1SIMD\s0 registers but will not +impose any restrictions on the assembler. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate little-endian code. This is the default when \s-1GCC\s0 is configured for an +\&\fBaarch64\-*\-*\fR but not an \fBaarch64_be\-*\-*\fR target. +.IP "\fB\-mcmodel=tiny\fR" 4 +.IX Item "-mcmodel=tiny" +Generate code for the tiny code model. The program and its statically defined +symbols must be within 1MB of each other. Programs can be statically or +dynamically linked. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model. The program and its statically defined +symbols must be within 4GB of each other. Programs can be statically or +dynamically linked. This is the default code model. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large code model. This makes no assumptions about +addresses and sizes of sections. Programs can be statically linked only. +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD 0 +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD +Avoid or allow generating memory accesses that may not be aligned on a natural +object boundary as described in the architecture specification. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +.PD 0 +.IP "\fB\-mno\-omit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-mno-omit-leaf-frame-pointer" +.PD +Omit or keep the frame pointer in leaf functions. The former behavior is the +default. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for a global canary or \fBsysreg\fR for a +canary in an appropriate system register. +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which system register to use as base register for reading the canary, +and from what offset from that base register. There is no default +register or offset as this is entirely for use within the Linux +kernel. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for a global canary or \fBsysreg\fR for a +canary in an appropriate system register. +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which system register to use as base register for reading the canary, +and from what offset from that base register. There is no default +register or offset as this is entirely for use within the Linux +kernel. +.IP "\fB\-mtls\-dialect=desc\fR" 4 +.IX Item "-mtls-dialect=desc" +Use \s-1TLS\s0 descriptors as the thread-local storage mechanism for dynamic accesses +of \s-1TLS\s0 variables. This is the default. +.IP "\fB\-mtls\-dialect=traditional\fR" 4 +.IX Item "-mtls-dialect=traditional" +Use traditional \s-1TLS\s0 as the thread-local storage mechanism for dynamic accesses +of \s-1TLS\s0 variables. +.IP "\fB\-mtls\-size=\fR\fIsize\fR" 4 +.IX Item "-mtls-size=size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 12, 24, 32, 48. +This option requires binutils 2.26 or newer. +.IP "\fB\-mfix\-cortex\-a53\-835769\fR" 4 +.IX Item "-mfix-cortex-a53-835769" +.PD 0 +.IP "\fB\-mno\-fix\-cortex\-a53\-835769\fR" 4 +.IX Item "-mno-fix-cortex-a53-835769" +.PD +Enable or disable the workaround for the \s-1ARM\s0 Cortex\-A53 erratum number 835769. +This involves inserting a \s-1NOP\s0 instruction between memory instructions and +64\-bit integer multiply-accumulate instructions. +.IP "\fB\-mfix\-cortex\-a53\-843419\fR" 4 +.IX Item "-mfix-cortex-a53-843419" +.PD 0 +.IP "\fB\-mno\-fix\-cortex\-a53\-843419\fR" 4 +.IX Item "-mno-fix-cortex-a53-843419" +.PD +Enable or disable the workaround for the \s-1ARM\s0 Cortex\-A53 erratum number 843419. +This erratum workaround is made at link time and this will only pass the +corresponding flag to the linker. +.IP "\fB\-mlow\-precision\-recip\-sqrt\fR" 4 +.IX Item "-mlow-precision-recip-sqrt" +.PD 0 +.IP "\fB\-mno\-low\-precision\-recip\-sqrt\fR" 4 +.IX Item "-mno-low-precision-recip-sqrt" +.PD +Enable or disable the reciprocal square root approximation. +This option only has an effect if \fB\-ffast\-math\fR or +\&\fB\-funsafe\-math\-optimizations\fR is used as well. Enabling this reduces +precision of reciprocal square root results to about 16 bits for +single precision and to 32 bits for double precision. +.IP "\fB\-mlow\-precision\-sqrt\fR" 4 +.IX Item "-mlow-precision-sqrt" +.PD 0 +.IP "\fB\-mno\-low\-precision\-sqrt\fR" 4 +.IX Item "-mno-low-precision-sqrt" +.PD +Enable or disable the square root approximation. +This option only has an effect if \fB\-ffast\-math\fR or +\&\fB\-funsafe\-math\-optimizations\fR is used as well. Enabling this reduces +precision of square root results to about 16 bits for +single precision and to 32 bits for double precision. +If enabled, it implies \fB\-mlow\-precision\-recip\-sqrt\fR. +.IP "\fB\-mlow\-precision\-div\fR" 4 +.IX Item "-mlow-precision-div" +.PD 0 +.IP "\fB\-mno\-low\-precision\-div\fR" 4 +.IX Item "-mno-low-precision-div" +.PD +Enable or disable the division approximation. +This option only has an effect if \fB\-ffast\-math\fR or +\&\fB\-funsafe\-math\-optimizations\fR is used as well. Enabling this reduces +precision of division results to about 16 bits for +single precision and to 32 bits for double precision. +.IP "\fB\-mtrack\-speculation\fR" 4 +.IX Item "-mtrack-speculation" +.PD 0 +.IP "\fB\-mno\-track\-speculation\fR" 4 +.IX Item "-mno-track-speculation" +.PD +Enable or disable generation of additional code to track speculative +execution through conditional branches. The tracking state can then +be used by the compiler when expanding calls to +\&\f(CW\*(C`_\|_builtin_speculation_safe_copy\*(C'\fR to permit a more efficient code +sequence to be generated. +.IP "\fB\-moutline\-atomics\fR" 4 +.IX Item "-moutline-atomics" +.PD 0 +.IP "\fB\-mno\-outline\-atomics\fR" 4 +.IX Item "-mno-outline-atomics" +.PD +Enable or disable calls to out-of-line helpers to implement atomic operations. +These helpers will, at runtime, determine if the \s-1LSE\s0 instructions from +ARMv8.1\-A can be used; if not, they will use the load/store\-exclusive +instructions that are present in the base ARMv8.0 \s-1ISA.\s0 +.Sp +This option is only applicable when compiling for the base ARMv8.0 +instruction set. If using a later revision, e.g. \fB\-march=armv8.1\-a\fR +or \fB\-march=armv8\-a+lse\fR, the ARMv8.1\-Atomics instructions will be +used directly. The same applies when using \fB\-mcpu=\fR when the +selected cpu supports the \fBlse\fR feature. +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +Specify the name of the target architecture and, optionally, one or +more feature modifiers. This option has the form +\&\fB\-march=\fR\fIarch\fR{\fB+\fR[\fBno\fR]\fIfeature\fR}*. +.Sp +The permissible values for \fIarch\fR are \fBarmv8\-a\fR, +\&\fBarmv8.1\-a\fR, \fBarmv8.2\-a\fR, \fBarmv8.3\-a\fR, \fBarmv8.4\-a\fR, +\&\fBarmv8.5\-a\fR or \fInative\fR. +.Sp +The value \fBarmv8.5\-a\fR implies \fBarmv8.4\-a\fR and enables compiler +support for the ARMv8.5\-A architecture extensions. +.Sp +The value \fBarmv8.4\-a\fR implies \fBarmv8.3\-a\fR and enables compiler +support for the ARMv8.4\-A architecture extensions. +.Sp +The value \fBarmv8.3\-a\fR implies \fBarmv8.2\-a\fR and enables compiler +support for the ARMv8.3\-A architecture extensions. +.Sp +The value \fBarmv8.2\-a\fR implies \fBarmv8.1\-a\fR and enables compiler +support for the ARMv8.2\-A architecture extensions. +.Sp +The value \fBarmv8.1\-a\fR implies \fBarmv8\-a\fR and enables compiler +support for the ARMv8.1\-A architecture extension. In particular, it +enables the \fB+crc\fR, \fB+lse\fR, and \fB+rdma\fR features. +.Sp +The value \fBnative\fR is available on native AArch64 GNU/Linux and +causes the compiler to pick the architecture of the host system. This +option has no effect if the compiler is unable to recognize the +architecture of the host system, +.Sp +The permissible values for \fIfeature\fR are listed in the sub-section +on \fBaarch64\-feature\-modifiers,,\fR\fB\-march\fR \fBand\fR \fB\-mcpu\fR +\&\fBFeature Modifiers\fR. Where conflicting feature modifiers are +specified, the right-most feature is used. +.Sp +\&\s-1GCC\s0 uses \fIname\fR to determine what kind of instructions it can emit +when generating assembly code. If \fB\-march\fR is specified +without either of \fB\-mtune\fR or \fB\-mcpu\fR also being +specified, the code is tuned to perform well across a range of target +processors implementing the target architecture. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +Specify the name of the target processor for which \s-1GCC\s0 should tune the +performance of the code. Permissible values for this option are: +\&\fBgeneric\fR, \fBcortex\-a35\fR, \fBcortex\-a53\fR, \fBcortex\-a55\fR, +\&\fBcortex\-a57\fR, \fBcortex\-a72\fR, \fBcortex\-a73\fR, \fBcortex\-a75\fR, +\&\fBcortex\-a76\fR, \fBares\fR, \fBexynos\-m1\fR, \fBemag\fR, \fBfalkor\fR, +\&\fBneoverse\-e1\fR, \fBneoverse\-n1\fR, \fBneoverse\-n2\fR, \fBneoverse\-v1\fR, +\&\fBneoverse\-512tvb\fR, +\&\fBqdf24xx\fR, \fBsaphira\fR, \fBphecda\fR, \fBxgene1\fR, \fBvulcan\fR, +\&\fBocteontx\fR, \fBocteontx81\fR, \fBocteontx83\fR, +\&\fBa64fx\fR, +\&\fBthunderx\fR, \fBthunderxt88\fR, +\&\fBthunderxt88p1\fR, \fBthunderxt81\fR, \fBtsv110\fR, +\&\fBthunderxt83\fR, \fBthunderx2t99\fR, \fBzeus\fR, +\&\fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a73.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR, +\&\fBcortex\-a75.cortex\-a55\fR, \fBcortex\-a76.cortex\-a55\fR +\&\fBnative\fR. +.Sp +The values \fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a73.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR, +\&\fBcortex\-a75.cortex\-a55\fR, \fBcortex\-a76.cortex\-a55\fR specify that \s-1GCC\s0 +should tune for a big.LITTLE system. +.Sp +The value \fBneoverse\-512tvb\fR specifies that \s-1GCC\s0 should tune +for Neoverse cores that (a) implement \s-1SVE\s0 and (b) have a total vector +bandwidth of 512 bits per cycle. In other words, the option tells \s-1GCC\s0 to +tune for Neoverse cores that can execute 4 128\-bit Advanced \s-1SIMD\s0 arithmetic +instructions a cycle and that can execute an equivalent number of \s-1SVE\s0 +arithmetic instructions per cycle (2 for 256\-bit \s-1SVE, 4\s0 for 128\-bit \s-1SVE\s0). +This is more general than tuning for a specific core like Neoverse V1 +but is more specific than the default tuning described below. +.Sp +Additionally on native AArch64 GNU/Linux systems the value +\&\fBnative\fR tunes performance to the host system. This option has no effect +if the compiler is unable to recognize the processor of the host system. +.Sp +Where none of \fB\-mtune=\fR, \fB\-mcpu=\fR or \fB\-march=\fR +are specified, the code is tuned to perform well across a range +of target processors. +.Sp +This option cannot be suffixed by feature modifiers. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Specify the name of the target processor, optionally suffixed by one +or more feature modifiers. This option has the form +\&\fB\-mcpu=\fR\fIcpu\fR{\fB+\fR[\fBno\fR]\fIfeature\fR}*, where +the permissible values for \fIcpu\fR are the same as those available +for \fB\-mtune\fR. The permissible values for \fIfeature\fR are +documented in the sub-section on +\&\fBaarch64\-feature\-modifiers,,\fR\fB\-march\fR \fBand\fR \fB\-mcpu\fR +\&\fBFeature Modifiers\fR. Where conflicting feature modifiers are +specified, the right-most feature is used. +.Sp +\&\s-1GCC\s0 uses \fIname\fR to determine what kind of instructions it can emit when +generating assembly code (as if by \fB\-march\fR) and to determine +the target processor for which to tune for performance (as if +by \fB\-mtune\fR). Where this option is used in conjunction +with \fB\-march\fR or \fB\-mtune\fR, those options take precedence +over the appropriate part of this option. +.Sp +\&\fB\-mcpu=neoverse\-512tvb\fR is special in that it does not refer +to a specific core, but instead refers to all Neoverse cores that +(a) implement \s-1SVE\s0 and (b) have a total vector bandwidth of 512 bits +a cycle. Unless overridden by \fB\-march\fR, +\&\fB\-mcpu=neoverse\-512tvb\fR generates code that can run on a +Neoverse V1 core, since Neoverse V1 is the first Neoverse core with +these properties. Unless overridden by \fB\-mtune\fR, +\&\fB\-mcpu=neoverse\-512tvb\fR tunes code in the same way as for +\&\fB\-mtune=neoverse\-512tvb\fR. +.IP "\fB\-moverride=\fR\fIstring\fR" 4 +.IX Item "-moverride=string" +Override tuning decisions made by the back-end in response to a +\&\fB\-mtune=\fR switch. The syntax, semantics, and accepted values +for \fIstring\fR in this option are not guaranteed to be consistent +across releases. +.Sp +This option is only intended to be useful when developing \s-1GCC.\s0 +.IP "\fB\-mverbose\-cost\-dump\fR" 4 +.IX Item "-mverbose-cost-dump" +Enable verbose cost model dumping in the debug dump files. This option is +provided for use in debugging the compiler. +.IP "\fB\-mpc\-relative\-literal\-loads\fR" 4 +.IX Item "-mpc-relative-literal-loads" +.PD 0 +.IP "\fB\-mno\-pc\-relative\-literal\-loads\fR" 4 +.IX Item "-mno-pc-relative-literal-loads" +.PD +Enable or disable PC-relative literal loads. With this option literal pools are +accessed using a single instruction and emitted after each function. This +limits the maximum size of functions to 1MB. This is enabled by default for +\&\fB\-mcmodel=tiny\fR. +.IP "\fB\-msign\-return\-address=\fR\fIscope\fR" 4 +.IX Item "-msign-return-address=scope" +Select the function scope on which return address signing will be applied. +Permissible values are \fBnone\fR, which disables return address signing, +\&\fBnon-leaf\fR, which enables pointer signing for functions which are not leaf +functions, and \fBall\fR, which enables pointer signing for all functions. The +default value is \fBnone\fR. This option has been deprecated by +\&\-mbranch\-protection. +.IP "\fB\-mbranch\-protection=\fR\fInone\fR\fB|\fR\fIstandard\fR\fB|\fR\fIpac-ret\fR\fB[+\fR\fIleaf\fR\fB]|\fR\fIbti\fR" 4 +.IX Item "-mbranch-protection=none|standard|pac-ret[+leaf]|bti" +Select the branch protection features to use. +\&\fBnone\fR is the default and turns off all types of branch protection. +\&\fBstandard\fR turns on all types of branch protection features. If a feature +has additional tuning options, then \fBstandard\fR sets it to its standard +level. +\&\fBpac\-ret[+\fR\fIleaf\fR\fB]\fR turns on return address signing to its standard +level: signing functions that save the return address to memory (non-leaf +functions will practically always do this) using the a\-key. The optional +argument \fBleaf\fR can be used to extend the signing to include leaf +functions. +\&\fBbti\fR turns on branch target identification mechanism. +.IP "\fB\-mharden\-sls=\fR\fIopts\fR" 4 +.IX Item "-mharden-sls=opts" +Enable compiler hardening against straight line speculation (\s-1SLS\s0). +\&\fIopts\fR is a comma-separated list of the following options: +.RS 4 +.IP "\fBretbr\fR" 4 +.IX Item "retbr" +.PD 0 +.IP "\fBblr\fR" 4 +.IX Item "blr" +.RE +.RS 4 +.PD +.Sp +In addition, \fB\-mharden\-sls=all\fR enables all \s-1SLS\s0 hardening while +\&\fB\-mharden\-sls=none\fR disables all \s-1SLS\s0 hardening. +.RE +.IP "\fB\-msve\-vector\-bits=\fR\fIbits\fR" 4 +.IX Item "-msve-vector-bits=bits" +Specify the number of bits in an \s-1SVE\s0 vector register. This option only has +an effect when \s-1SVE\s0 is enabled. +.Sp +\&\s-1GCC\s0 supports two forms of \s-1SVE\s0 code generation: \*(L"vector-length +agnostic\*(R" output that works with any size of vector register and +\&\*(L"vector-length specific\*(R" output that allows \s-1GCC\s0 to make assumptions +about the vector length when it is useful for optimization reasons. +The possible values of \fBbits\fR are: \fBscalable\fR, \fB128\fR, +\&\fB256\fR, \fB512\fR, \fB1024\fR and \fB2048\fR. +Specifying \fBscalable\fR selects vector-length agnostic +output. At present \fB\-msve\-vector\-bits=128\fR also generates vector-length +agnostic output. All other values generate vector-length specific code. +The behavior of these values may change in future releases and no value except +\&\fBscalable\fR should be relied on for producing code that is portable across +different hardware \s-1SVE\s0 vector lengths. +.Sp +The default is \fB\-msve\-vector\-bits=scalable\fR, which produces +vector-length agnostic code. +.PP +\fB\-march\fR and \fB\-mcpu\fR Feature Modifiers +.IX Subsection "-march and -mcpu Feature Modifiers" +.PP +Feature modifiers used with \fB\-march\fR and \fB\-mcpu\fR can be any of +the following and their inverses \fBno\fR\fIfeature\fR: +.IP "\fBcrc\fR" 4 +.IX Item "crc" +Enable \s-1CRC\s0 extension. This is on by default for +\&\fB\-march=armv8.1\-a\fR. +.IP "\fBcrypto\fR" 4 +.IX Item "crypto" +Enable Crypto extension. This also enables Advanced \s-1SIMD\s0 and floating-point +instructions. +.IP "\fBfp\fR" 4 +.IX Item "fp" +Enable floating-point instructions. This is on by default for all possible +values for options \fB\-march\fR and \fB\-mcpu\fR. +.IP "\fBsimd\fR" 4 +.IX Item "simd" +Enable Advanced \s-1SIMD\s0 instructions. This also enables floating-point +instructions. This is on by default for all possible values for options +\&\fB\-march\fR and \fB\-mcpu\fR. +.IP "\fBsve\fR" 4 +.IX Item "sve" +Enable Scalable Vector Extension instructions. This also enables Advanced +\&\s-1SIMD\s0 and floating-point instructions. +.IP "\fBlse\fR" 4 +.IX Item "lse" +Enable Large System Extension instructions. This is on by default for +\&\fB\-march=armv8.1\-a\fR. +.IP "\fBrdma\fR" 4 +.IX Item "rdma" +Enable Round Double Multiply Accumulate instructions. This is on by default +for \fB\-march=armv8.1\-a\fR. +.IP "\fBfp16\fR" 4 +.IX Item "fp16" +Enable \s-1FP16\s0 extension. This also enables floating-point instructions. +.IP "\fBfp16fml\fR" 4 +.IX Item "fp16fml" +Enable \s-1FP16\s0 fmla extension. This also enables \s-1FP16\s0 extensions and +floating-point instructions. This option is enabled by default for \fB\-march=armv8.4\-a\fR. Use of this option with architectures prior to Armv8.2\-A is not supported. +.IP "\fBrcpc\fR" 4 +.IX Item "rcpc" +Enable the RcPc extension. This does not change code generation from \s-1GCC,\s0 +but is passed on to the assembler, enabling inline asm statements to use +instructions from the RcPc extension. +.IP "\fBdotprod\fR" 4 +.IX Item "dotprod" +Enable the Dot Product extension. This also enables Advanced \s-1SIMD\s0 instructions. +.IP "\fBaes\fR" 4 +.IX Item "aes" +Enable the Armv8\-a aes and pmull crypto extension. This also enables Advanced +\&\s-1SIMD\s0 instructions. +.IP "\fBsha2\fR" 4 +.IX Item "sha2" +Enable the Armv8\-a sha2 crypto extension. This also enables Advanced \s-1SIMD\s0 instructions. +.IP "\fBsha3\fR" 4 +.IX Item "sha3" +Enable the sha512 and sha3 crypto extension. This also enables Advanced \s-1SIMD\s0 +instructions. Use of this option with architectures prior to Armv8.2\-A is not supported. +.IP "\fBsm4\fR" 4 +.IX Item "sm4" +Enable the sm3 and sm4 crypto extension. This also enables Advanced \s-1SIMD\s0 instructions. +Use of this option with architectures prior to Armv8.2\-A is not supported. +.IP "\fBprofile\fR" 4 +.IX Item "profile" +Enable the Statistical Profiling extension. This option is only to enable the +extension at the assembler level and does not affect code generation. +.IP "\fBrng\fR" 4 +.IX Item "rng" +Enable the Armv8.5\-a Random Number instructions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +.IP "\fBmemtag\fR" 4 +.IX Item "memtag" +Enable the Armv8.5\-a Memory Tagging Extensions. This option is only to +enable the extension at the assembler level and does not affect code +generation. +.IP "\fBsb\fR" 4 +.IX Item "sb" +Enable the Armv8\-a Speculation Barrier instruction. This option is only to +enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for \fB\-march=armv8.5\-a\fR. +.IP "\fBssbs\fR" 4 +.IX Item "ssbs" +Enable the Armv8\-a Speculative Store Bypass Safe instruction. This option +is only to enable the extension at the assembler level and does not affect code +generation. This option is enabled by default for \fB\-march=armv8.5\-a\fR. +.IP "\fBpredres\fR" 4 +.IX Item "predres" +Enable the Armv8\-a Execution and Data Prediction Restriction instructions. +This option is only to enable the extension at the assembler level and does +not affect code generation. This option is enabled by default for +\&\fB\-march=armv8.5\-a\fR. +.PP +Feature \fBcrypto\fR implies \fBaes\fR, \fBsha2\fR, and \fBsimd\fR, +which implies \fBfp\fR. +Conversely, \fBnofp\fR implies \fBnosimd\fR, which implies +\&\fBnocrypto\fR, \fBnoaes\fR and \fBnosha2\fR. +.PP +\fIAdapteva Epiphany Options\fR +.IX Subsection "Adapteva Epiphany Options" +.PP +These \fB\-m\fR options are defined for Adapteva Epiphany: +.IP "\fB\-mhalf\-reg\-file\fR" 4 +.IX Item "-mhalf-reg-file" +Don't allocate any register in the range \f(CW\*(C`r32\*(C'\fR...\f(CW\*(C`r63\*(C'\fR. +That allows code to run on hardware variants that lack these registers. +.IP "\fB\-mprefer\-short\-insn\-regs\fR" 4 +.IX Item "-mprefer-short-insn-regs" +Preferentially allocate registers that allow short instruction generation. +This can result in increased instruction count, so this may either reduce or +increase overall code size. +.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 +.IX Item "-mbranch-cost=num" +Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. +.IP "\fB\-mcmove\fR" 4 +.IX Item "-mcmove" +Enable the generation of conditional moves. +.IP "\fB\-mnops=\fR\fInum\fR" 4 +.IX Item "-mnops=num" +Emit \fInum\fR NOPs before every other generated instruction. +.IP "\fB\-mno\-soft\-cmpsf\fR" 4 +.IX Item "-mno-soft-cmpsf" +For single-precision floating-point comparisons, emit an \f(CW\*(C`fsub\*(C'\fR instruction +and test the flags. This is faster than a software comparison, but can +get incorrect results in the presence of NaNs, or when two different small +numbers are compared such that their difference is calculated as zero. +The default is \fB\-msoft\-cmpsf\fR, which uses slower, but IEEE-compliant, +software comparisons. +.IP "\fB\-mstack\-offset=\fR\fInum\fR" 4 +.IX Item "-mstack-offset=num" +Set the offset between the top of the stack and the stack pointer. +E.g., a value of 8 means that the eight bytes in the range \f(CW\*(C`sp+0...sp+7\*(C'\fR +can be used by leaf functions without stack allocation. +Values other than \fB8\fR or \fB16\fR are untested and unlikely to work. +Note also that this option changes the \s-1ABI\s0; compiling a program with a +different stack offset than the libraries have been compiled with +generally does not work. +This option can be useful if you want to evaluate if a different stack +offset would give you better code, but to actually use a different stack +offset to build working programs, it is recommended to configure the +toolchain with the appropriate \fB\-\-with\-stack\-offset=\fR\fInum\fR option. +.IP "\fB\-mno\-round\-nearest\fR" 4 +.IX Item "-mno-round-nearest" +Make the scheduler assume that the rounding mode has been set to +truncating. The default is \fB\-mround\-nearest\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +If not otherwise specified by an attribute, assume all calls might be beyond +the offset range of the \f(CW\*(C`b\*(C'\fR / \f(CW\*(C`bl\*(C'\fR instructions, and therefore load the +function address into a register before performing a (otherwise direct) call. +This is the default. +.IP "\fB\-mshort\-calls\fR" 4 +.IX Item "-mshort-calls" +If not otherwise specified by an attribute, assume all direct calls are +in the range of the \f(CW\*(C`b\*(C'\fR / \f(CW\*(C`bl\*(C'\fR instructions, so use these instructions +for direct calls. The default is \fB\-mlong\-calls\fR. +.IP "\fB\-msmall16\fR" 4 +.IX Item "-msmall16" +Assume addresses can be loaded as 16\-bit unsigned values. This does not +apply to function addresses for which \fB\-mlong\-calls\fR semantics +are in effect. +.IP "\fB\-mfp\-mode=\fR\fImode\fR" 4 +.IX Item "-mfp-mode=mode" +Set the prevailing mode of the floating-point unit. +This determines the floating-point mode that is provided and expected +at function call and return time. Making this mode match the mode you +predominantly need at function start can make your programs smaller and +faster by avoiding unnecessary mode switches. +.Sp +\&\fImode\fR can be set to one the following values: +.RS 4 +.IP "\fBcaller\fR" 4 +.IX Item "caller" +Any mode at function entry is valid, and retained or restored when +the function returns, and when it calls other functions. +This mode is useful for compiling libraries or other compilation units +you might want to incorporate into different programs with different +prevailing \s-1FPU\s0 modes, and the convenience of being able to use a single +object file outweighs the size and speed overhead for any extra +mode switching that might be needed, compared with what would be needed +with a more specific choice of prevailing \s-1FPU\s0 mode. +.IP "\fBtruncate\fR" 4 +.IX Item "truncate" +This is the mode used for floating-point calculations with +truncating (i.e. round towards zero) rounding mode. That includes +conversion from floating point to integer. +.IP "\fBround-nearest\fR" 4 +.IX Item "round-nearest" +This is the mode used for floating-point calculations with +round-to-nearest-or-even rounding mode. +.IP "\fBint\fR" 4 +.IX Item "int" +This is the mode used to perform integer calculations in the \s-1FPU,\s0 e.g. +integer multiply, or integer multiply-and-accumulate. +.RE +.RS 4 +.Sp +The default is \fB\-mfp\-mode=caller\fR +.RE +.IP "\fB\-mno\-split\-lohi\fR" 4 +.IX Item "-mno-split-lohi" +.PD 0 +.IP "\fB\-mno\-postinc\fR" 4 +.IX Item "-mno-postinc" +.IP "\fB\-mno\-postmodify\fR" 4 +.IX Item "-mno-postmodify" +.PD +Code generation tweaks that disable, respectively, splitting of 32\-bit +loads, generation of post-increment addresses, and generation of +post-modify addresses. The defaults are \fBmsplit-lohi\fR, +\&\fB\-mpost\-inc\fR, and \fB\-mpost\-modify\fR. +.IP "\fB\-mnovect\-double\fR" 4 +.IX Item "-mnovect-double" +Change the preferred \s-1SIMD\s0 mode to SImode. The default is +\&\fB\-mvect\-double\fR, which uses DImode as preferred \s-1SIMD\s0 mode. +.IP "\fB\-max\-vect\-align=\fR\fInum\fR" 4 +.IX Item "-max-vect-align=num" +The maximum alignment for \s-1SIMD\s0 vector mode types. +\&\fInum\fR may be 4 or 8. The default is 8. +Note that this is an \s-1ABI\s0 change, even though many library function +interfaces are unaffected if they don't use \s-1SIMD\s0 vector modes +in places that affect size and/or alignment of relevant types. +.IP "\fB\-msplit\-vecmove\-early\fR" 4 +.IX Item "-msplit-vecmove-early" +Split vector moves into single word moves before reload. In theory this +can give better register allocation, but so far the reverse seems to be +generally the case. +.IP "\fB\-m1reg\-\fR\fIreg\fR" 4 +.IX Item "-m1reg-reg" +Specify a register to hold the constant \-1, which makes loading small negative +constants and certain bitmasks faster. +Allowable values for \fIreg\fR are \fBr43\fR and \fBr63\fR, +which specify use of that register as a fixed register, +and \fBnone\fR, which means that no register is used for this +purpose. The default is \fB\-m1reg\-none\fR. +.PP +\fI\s-1AMD GCN\s0 Options\fR +.IX Subsection "AMD GCN Options" +.PP +These options are defined specifically for the \s-1AMD GCN\s0 port. +.IP "\fB\-march=\fR\fIgpu\fR" 4 +.IX Item "-march=gpu" +.PD 0 +.IP "\fB\-mtune=\fR\fIgpu\fR" 4 +.IX Item "-mtune=gpu" +.PD +Set architecture type or tuning for \fIgpu\fR. Supported values for \fIgpu\fR +are +.RS 4 +.IP "\fBfiji\fR" 4 +.IX Item "fiji" +Compile for \s-1GCN3\s0 Fiji devices (gfx803). +.IP "\fBgfx900\fR" 4 +.IX Item "gfx900" +Compile for \s-1GCN5\s0 Vega 10 devices (gfx900). +.RE +.RS 4 +.RE +.IP "\fB\-mstack\-size=\fR\fIbytes\fR" 4 +.IX Item "-mstack-size=bytes" +Specify how many \fIbytes\fR of stack space will be requested for each \s-1GPU\s0 +thread (wave-front). Beware that there may be many threads and limited memory +available. The size of the stack allocation may also have an impact on +run-time performance. The default is 32KB when using OpenACC or OpenMP, and +1MB otherwise. +.PP +\fI\s-1ARC\s0 Options\fR +.IX Subsection "ARC Options" +.PP +The following options control the architecture variant for which code +is being compiled: +.IP "\fB\-mbarrel\-shifter\fR" 4 +.IX Item "-mbarrel-shifter" +Generate instructions supported by barrel shifter. This is the default +unless \fB\-mcpu=ARC601\fR or \fB\-mcpu=ARCEM\fR is in effect. +.IP "\fB\-mjli\-always\fR" 4 +.IX Item "-mjli-always" +Force to call a function using jli_s instruction. This option is +valid only for ARCv2 architecture. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Set architecture type, register usage, and instruction scheduling +parameters for \fIcpu\fR. There are also shortcut alias options +available for backward compatibility and convenience. Supported +values for \fIcpu\fR are +.RS 4 +.IP "\fBarc600\fR" 4 +.IX Item "arc600" +Compile for \s-1ARC600.\s0 Aliases: \fB\-mA6\fR, \fB\-mARC600\fR. +.IP "\fBarc601\fR" 4 +.IX Item "arc601" +Compile for \s-1ARC601.\s0 Alias: \fB\-mARC601\fR. +.IP "\fBarc700\fR" 4 +.IX Item "arc700" +Compile for \s-1ARC700.\s0 Aliases: \fB\-mA7\fR, \fB\-mARC700\fR. +This is the default when configured with \fB\-\-with\-cpu=arc700\fR. +.IP "\fBarcem\fR" 4 +.IX Item "arcem" +Compile for \s-1ARC EM.\s0 +.IP "\fBarchs\fR" 4 +.IX Item "archs" +Compile for \s-1ARC HS.\s0 +.IP "\fBem\fR" 4 +.IX Item "em" +Compile for \s-1ARC EM CPU\s0 with no hardware extensions. +.IP "\fBem4\fR" 4 +.IX Item "em4" +Compile for \s-1ARC EM4 CPU.\s0 +.IP "\fBem4_dmips\fR" 4 +.IX Item "em4_dmips" +Compile for \s-1ARC EM4 DMIPS CPU.\s0 +.IP "\fBem4_fpus\fR" 4 +.IX Item "em4_fpus" +Compile for \s-1ARC EM4 DMIPS CPU\s0 with the single-precision floating-point +extension. +.IP "\fBem4_fpuda\fR" 4 +.IX Item "em4_fpuda" +Compile for \s-1ARC EM4 DMIPS CPU\s0 with single-precision floating-point and +double assist instructions. +.IP "\fBhs\fR" 4 +.IX Item "hs" +Compile for \s-1ARC HS CPU\s0 with no hardware extensions except the atomic +instructions. +.IP "\fBhs34\fR" 4 +.IX Item "hs34" +Compile for \s-1ARC HS34 CPU.\s0 +.IP "\fBhs38\fR" 4 +.IX Item "hs38" +Compile for \s-1ARC HS38 CPU.\s0 +.IP "\fBhs38_linux\fR" 4 +.IX Item "hs38_linux" +Compile for \s-1ARC HS38 CPU\s0 with all hardware extensions on. +.IP "\fBarc600_norm\fR" 4 +.IX Item "arc600_norm" +Compile for \s-1ARC 600 CPU\s0 with \f(CW\*(C`norm\*(C'\fR instructions enabled. +.IP "\fBarc600_mul32x16\fR" 4 +.IX Item "arc600_mul32x16" +Compile for \s-1ARC 600 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and 32x16\-bit multiply +instructions enabled. +.IP "\fBarc600_mul64\fR" 4 +.IX Item "arc600_mul64" +Compile for \s-1ARC 600 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and \f(CW\*(C`mul64\*(C'\fR\-family +instructions enabled. +.IP "\fBarc601_norm\fR" 4 +.IX Item "arc601_norm" +Compile for \s-1ARC 601 CPU\s0 with \f(CW\*(C`norm\*(C'\fR instructions enabled. +.IP "\fBarc601_mul32x16\fR" 4 +.IX Item "arc601_mul32x16" +Compile for \s-1ARC 601 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and 32x16\-bit multiply +instructions enabled. +.IP "\fBarc601_mul64\fR" 4 +.IX Item "arc601_mul64" +Compile for \s-1ARC 601 CPU\s0 with \f(CW\*(C`norm\*(C'\fR and \f(CW\*(C`mul64\*(C'\fR\-family +instructions enabled. +.IP "\fBnps400\fR" 4 +.IX Item "nps400" +Compile for \s-1ARC 700\s0 on \s-1NPS400\s0 chip. +.IP "\fBem_mini\fR" 4 +.IX Item "em_mini" +Compile for \s-1ARC EM\s0 minimalist configuration featuring reduced register +set. +.RE +.RS 4 +.RE +.IP "\fB\-mdpfp\fR" 4 +.IX Item "-mdpfp" +.PD 0 +.IP "\fB\-mdpfp\-compact\fR" 4 +.IX Item "-mdpfp-compact" +.PD +Generate double-precision \s-1FPX\s0 instructions, tuned for the compact +implementation. +.IP "\fB\-mdpfp\-fast\fR" 4 +.IX Item "-mdpfp-fast" +Generate double-precision \s-1FPX\s0 instructions, tuned for the fast +implementation. +.IP "\fB\-mno\-dpfp\-lrsr\fR" 4 +.IX Item "-mno-dpfp-lrsr" +Disable \f(CW\*(C`lr\*(C'\fR and \f(CW\*(C`sr\*(C'\fR instructions from using \s-1FPX\s0 extension +aux registers. +.IP "\fB\-mea\fR" 4 +.IX Item "-mea" +Generate extended arithmetic instructions. Currently only +\&\f(CW\*(C`divaw\*(C'\fR, \f(CW\*(C`adds\*(C'\fR, \f(CW\*(C`subs\*(C'\fR, and \f(CW\*(C`sat16\*(C'\fR are +supported. This is always enabled for \fB\-mcpu=ARC700\fR. +.IP "\fB\-mno\-mpy\fR" 4 +.IX Item "-mno-mpy" +Do not generate \f(CW\*(C`mpy\*(C'\fR\-family instructions for \s-1ARC700.\s0 This option is +deprecated. +.IP "\fB\-mmul32x16\fR" 4 +.IX Item "-mmul32x16" +Generate 32x16\-bit multiply and multiply-accumulate instructions. +.IP "\fB\-mmul64\fR" 4 +.IX Item "-mmul64" +Generate \f(CW\*(C`mul64\*(C'\fR and \f(CW\*(C`mulu64\*(C'\fR instructions. +Only valid for \fB\-mcpu=ARC600\fR. +.IP "\fB\-mnorm\fR" 4 +.IX Item "-mnorm" +Generate \f(CW\*(C`norm\*(C'\fR instructions. This is the default if \fB\-mcpu=ARC700\fR +is in effect. +.IP "\fB\-mspfp\fR" 4 +.IX Item "-mspfp" +.PD 0 +.IP "\fB\-mspfp\-compact\fR" 4 +.IX Item "-mspfp-compact" +.PD +Generate single-precision \s-1FPX\s0 instructions, tuned for the compact +implementation. +.IP "\fB\-mspfp\-fast\fR" 4 +.IX Item "-mspfp-fast" +Generate single-precision \s-1FPX\s0 instructions, tuned for the fast +implementation. +.IP "\fB\-msimd\fR" 4 +.IX Item "-msimd" +Enable generation of \s-1ARC SIMD\s0 instructions via target-specific +builtins. Only valid for \fB\-mcpu=ARC700\fR. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +This option ignored; it is provided for compatibility purposes only. +Software floating-point code is emitted by default, and this default +can overridden by \s-1FPX\s0 options; \fB\-mspfp\fR, \fB\-mspfp\-compact\fR, or +\&\fB\-mspfp\-fast\fR for single precision, and \fB\-mdpfp\fR, +\&\fB\-mdpfp\-compact\fR, or \fB\-mdpfp\-fast\fR for double precision. +.IP "\fB\-mswap\fR" 4 +.IX Item "-mswap" +Generate \f(CW\*(C`swap\*(C'\fR instructions. +.IP "\fB\-matomic\fR" 4 +.IX Item "-matomic" +This enables use of the locked load/store conditional extension to implement +atomic memory built-in functions. Not available for \s-1ARC\s0 6xx or \s-1ARC +EM\s0 cores. +.IP "\fB\-mdiv\-rem\fR" 4 +.IX Item "-mdiv-rem" +Enable \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`rem\*(C'\fR instructions for ARCv2 cores. +.IP "\fB\-mcode\-density\fR" 4 +.IX Item "-mcode-density" +Enable code density instructions for \s-1ARC EM.\s0 +This option is on by default for \s-1ARC HS.\s0 +.IP "\fB\-mll64\fR" 4 +.IX Item "-mll64" +Enable double load/store operations for \s-1ARC HS\s0 cores. +.IP "\fB\-mtp\-regno=\fR\fIregno\fR" 4 +.IX Item "-mtp-regno=regno" +Specify thread pointer register number. +.IP "\fB\-mmpy\-option=\fR\fImulto\fR" 4 +.IX Item "-mmpy-option=multo" +Compile ARCv2 code with a multiplier design option. You can specify +the option using either a string or numeric value for \fImulto\fR. +\&\fBwlh1\fR is the default value. The recognized values are: +.RS 4 +.IP "\fB0\fR" 4 +.IX Item "0" +.PD 0 +.IP "\fBnone\fR" 4 +.IX Item "none" +.PD +No multiplier available. +.IP "\fB1\fR" 4 +.IX Item "1" +.PD 0 +.IP "\fBw\fR" 4 +.IX Item "w" +.PD +16x16 multiplier, fully pipelined. +The following instructions are enabled: \f(CW\*(C`mpyw\*(C'\fR and \f(CW\*(C`mpyuw\*(C'\fR. +.IP "\fB2\fR" 4 +.IX Item "2" +.PD 0 +.IP "\fBwlh1\fR" 4 +.IX Item "wlh1" +.PD +32x32 multiplier, fully +pipelined (1 stage). The following instructions are additionally +enabled: \f(CW\*(C`mpy\*(C'\fR, \f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB3\fR" 4 +.IX Item "3" +.PD 0 +.IP "\fBwlh2\fR" 4 +.IX Item "wlh2" +.PD +32x32 multiplier, fully pipelined +(2 stages). The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB4\fR" 4 +.IX Item "4" +.PD 0 +.IP "\fBwlh3\fR" 4 +.IX Item "wlh3" +.PD +Two 16x16 multipliers, blocking, +sequential. The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB5\fR" 4 +.IX Item "5" +.PD 0 +.IP "\fBwlh4\fR" 4 +.IX Item "wlh4" +.PD +One 16x16 multiplier, blocking, +sequential. The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB6\fR" 4 +.IX Item "6" +.PD 0 +.IP "\fBwlh5\fR" 4 +.IX Item "wlh5" +.PD +One 32x4 multiplier, blocking, +sequential. The following instructions are additionally enabled: \f(CW\*(C`mpy\*(C'\fR, +\&\f(CW\*(C`mpyu\*(C'\fR, \f(CW\*(C`mpym\*(C'\fR, \f(CW\*(C`mpymu\*(C'\fR, and \f(CW\*(C`mpy_s\*(C'\fR. +.IP "\fB7\fR" 4 +.IX Item "7" +.PD 0 +.IP "\fBplus_dmpy\fR" 4 +.IX Item "plus_dmpy" +.PD +\&\s-1ARC HS SIMD\s0 support. +.IP "\fB8\fR" 4 +.IX Item "8" +.PD 0 +.IP "\fBplus_macd\fR" 4 +.IX Item "plus_macd" +.PD +\&\s-1ARC HS SIMD\s0 support. +.IP "\fB9\fR" 4 +.IX Item "9" +.PD 0 +.IP "\fBplus_qmacw\fR" 4 +.IX Item "plus_qmacw" +.PD +\&\s-1ARC HS SIMD\s0 support. +.RE +.RS 4 +.Sp +This option is only available for ARCv2 cores. +.RE +.IP "\fB\-mfpu=\fR\fIfpu\fR" 4 +.IX Item "-mfpu=fpu" +Enables support for specific floating-point hardware extensions for ARCv2 +cores. Supported values for \fIfpu\fR are: +.RS 4 +.IP "\fBfpus\fR" 4 +.IX Item "fpus" +Enables support for single-precision floating-point hardware +extensions. +.IP "\fBfpud\fR" 4 +.IX Item "fpud" +Enables support for double-precision floating-point hardware +extensions. The single-precision floating-point extension is also +enabled. Not available for \s-1ARC EM.\s0 +.IP "\fBfpuda\fR" 4 +.IX Item "fpuda" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. The single-precision +floating-point extension is also enabled. This option is +only available for \s-1ARC EM.\s0 +.IP "\fBfpuda_div\fR" 4 +.IX Item "fpuda_div" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. +The single-precision floating-point, square-root, and divide +extensions are also enabled. This option is +only available for \s-1ARC EM.\s0 +.IP "\fBfpuda_fma\fR" 4 +.IX Item "fpuda_fma" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. +The single-precision floating-point and fused multiply and add +hardware extensions are also enabled. This option is +only available for \s-1ARC EM.\s0 +.IP "\fBfpuda_all\fR" 4 +.IX Item "fpuda_all" +Enables support for double-precision floating-point hardware +extensions using double-precision assist instructions. +All single-precision floating-point hardware extensions are also +enabled. This option is only available for \s-1ARC EM.\s0 +.IP "\fBfpus_div\fR" 4 +.IX Item "fpus_div" +Enables support for single-precision floating-point, square-root and divide +hardware extensions. +.IP "\fBfpud_div\fR" 4 +.IX Item "fpud_div" +Enables support for double-precision floating-point, square-root and divide +hardware extensions. This option +includes option \fBfpus_div\fR. Not available for \s-1ARC EM.\s0 +.IP "\fBfpus_fma\fR" 4 +.IX Item "fpus_fma" +Enables support for single-precision floating-point and +fused multiply and add hardware extensions. +.IP "\fBfpud_fma\fR" 4 +.IX Item "fpud_fma" +Enables support for double-precision floating-point and +fused multiply and add hardware extensions. This option +includes option \fBfpus_fma\fR. Not available for \s-1ARC EM.\s0 +.IP "\fBfpus_all\fR" 4 +.IX Item "fpus_all" +Enables support for all single-precision floating-point hardware +extensions. +.IP "\fBfpud_all\fR" 4 +.IX Item "fpud_all" +Enables support for all single\- and double-precision floating-point +hardware extensions. Not available for \s-1ARC EM.\s0 +.RE +.RS 4 +.RE +.IP "\fB\-mirq\-ctrl\-saved=\fR\fIregister-range\fR\fB,\fR \fIblink\fR\fB,\fR \fIlp_count\fR" 4 +.IX Item "-mirq-ctrl-saved=register-range, blink, lp_count" +Specifies general-purposes registers that the processor automatically +saves/restores on interrupt entry and exit. \fIregister-range\fR is +specified as two registers separated by a dash. The register range +always starts with \f(CW\*(C`r0\*(C'\fR, the upper limit is \f(CW\*(C`fp\*(C'\fR register. +\&\fIblink\fR and \fIlp_count\fR are optional. This option is only +valid for \s-1ARC EM\s0 and \s-1ARC HS\s0 cores. +.IP "\fB\-mrgf\-banked\-regs=\fR\fInumber\fR" 4 +.IX Item "-mrgf-banked-regs=number" +Specifies the number of registers replicated in second register bank +on entry to fast interrupt. Fast interrupts are interrupts with the +highest priority level P0. These interrupts save only \s-1PC\s0 and \s-1STATUS32\s0 +registers to avoid memory transactions during interrupt entry and exit +sequences. Use this option when you are using fast interrupts in an +\&\s-1ARC V2\s0 family processor. Permitted values are 4, 8, 16, and 32. +.IP "\fB\-mlpc\-width=\fR\fIwidth\fR" 4 +.IX Item "-mlpc-width=width" +Specify the width of the \f(CW\*(C`lp_count\*(C'\fR register. Valid values for +\&\fIwidth\fR are 8, 16, 20, 24, 28 and 32 bits. The default width is +fixed to 32 bits. If the width is less than 32, the compiler does not +attempt to transform loops in your program to use the zero-delay loop +mechanism unless it is known that the \f(CW\*(C`lp_count\*(C'\fR register can +hold the required loop-counter value. Depending on the width +specified, the compiler and run-time library might continue to use the +loop mechanism for various needs. This option defines macro +\&\f(CW\*(C`_\|_ARC_LPC_WIDTH_\|_\*(C'\fR with the value of \fIwidth\fR. +.IP "\fB\-mrf16\fR" 4 +.IX Item "-mrf16" +This option instructs the compiler to generate code for a 16\-entry +register file. This option defines the \f(CW\*(C`_\|_ARC_RF16_\|_\*(C'\fR +preprocessor macro. +.IP "\fB\-mbranch\-index\fR" 4 +.IX Item "-mbranch-index" +Enable use of \f(CW\*(C`bi\*(C'\fR or \f(CW\*(C`bih\*(C'\fR instructions to implement jump +tables. +.PP +The following options are passed through to the assembler, and also +define preprocessor macro symbols. +.IP "\fB\-mdsp\-packa\fR" 4 +.IX Item "-mdsp-packa" +Passed down to the assembler to enable the \s-1DSP\s0 Pack A extensions. +Also sets the preprocessor symbol \f(CW\*(C`_\|_Xdsp_packa\*(C'\fR. This option is +deprecated. +.IP "\fB\-mdvbf\fR" 4 +.IX Item "-mdvbf" +Passed down to the assembler to enable the dual Viterbi butterfly +extension. Also sets the preprocessor symbol \f(CW\*(C`_\|_Xdvbf\*(C'\fR. This +option is deprecated. +.IP "\fB\-mlock\fR" 4 +.IX Item "-mlock" +Passed down to the assembler to enable the locked load/store +conditional extension. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xlock\*(C'\fR. +.IP "\fB\-mmac\-d16\fR" 4 +.IX Item "-mmac-d16" +Passed down to the assembler. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xxmac_d16\*(C'\fR. This option is deprecated. +.IP "\fB\-mmac\-24\fR" 4 +.IX Item "-mmac-24" +Passed down to the assembler. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xxmac_24\*(C'\fR. This option is deprecated. +.IP "\fB\-mrtsc\fR" 4 +.IX Item "-mrtsc" +Passed down to the assembler to enable the 64\-bit time-stamp counter +extension instruction. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xrtsc\*(C'\fR. This option is deprecated. +.IP "\fB\-mswape\fR" 4 +.IX Item "-mswape" +Passed down to the assembler to enable the swap byte ordering +extension instruction. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xswape\*(C'\fR. +.IP "\fB\-mtelephony\fR" 4 +.IX Item "-mtelephony" +Passed down to the assembler to enable dual\- and single-operand +instructions for telephony. Also sets the preprocessor symbol +\&\f(CW\*(C`_\|_Xtelephony\*(C'\fR. This option is deprecated. +.IP "\fB\-mxy\fR" 4 +.IX Item "-mxy" +Passed down to the assembler to enable the \s-1XY\s0 memory extension. Also +sets the preprocessor symbol \f(CW\*(C`_\|_Xxy\*(C'\fR. +.PP +The following options control how the assembly code is annotated: +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Annotate assembler instructions with estimated addresses. +.IP "\fB\-mannotate\-align\fR" 4 +.IX Item "-mannotate-align" +Explain what alignment considerations lead to the decision to make an +instruction short or long. +.PP +The following options are passed through to the linker: +.IP "\fB\-marclinux\fR" 4 +.IX Item "-marclinux" +Passed through to the linker, to specify use of the \f(CW\*(C`arclinux\*(C'\fR emulation. +This option is enabled by default in tool chains built for +\&\f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets +when profiling is not requested. +.IP "\fB\-marclinux_prof\fR" 4 +.IX Item "-marclinux_prof" +Passed through to the linker, to specify use of the +\&\f(CW\*(C`arclinux_prof\*(C'\fR emulation. This option is enabled by default in +tool chains built for \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and +\&\f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets when profiling is requested. +.PP +The following options control the semantics of generated code: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Generate calls as register indirect calls, thus providing access +to the full 32\-bit address range. +.IP "\fB\-mmedium\-calls\fR" 4 +.IX Item "-mmedium-calls" +Don't use less than 25\-bit addressing range for calls, which is the +offset available for an unconditional branch-and-link +instruction. Conditional execution of function calls is suppressed, to +allow use of the 25\-bit range, rather than the 21\-bit range with +conditional branch-and-link. This is the default for tool chains built +for \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put definitions of externally-visible data in a small data section if +that data is no bigger than \fInum\fR bytes. The default value of +\&\fInum\fR is 4 for any \s-1ARC\s0 configuration, or 8 when we have double +load/store operations. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +Do not generate sdata references. This is the default for tool chains +built for \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR +targets. +.IP "\fB\-mvolatile\-cache\fR" 4 +.IX Item "-mvolatile-cache" +Use ordinarily cached memory accesses for volatile references. This is the +default. +.IP "\fB\-mno\-volatile\-cache\fR" 4 +.IX Item "-mno-volatile-cache" +Enable cache bypass for volatile references. +.PP +The following options fine tune code generation: +.IP "\fB\-malign\-call\fR" 4 +.IX Item "-malign-call" +Do alignment optimizations for call instructions. +.IP "\fB\-mauto\-modify\-reg\fR" 4 +.IX Item "-mauto-modify-reg" +Enable the use of pre/post modify with register displacement. +.IP "\fB\-mbbit\-peephole\fR" 4 +.IX Item "-mbbit-peephole" +Enable bbit peephole2. +.IP "\fB\-mno\-brcc\fR" 4 +.IX Item "-mno-brcc" +This option disables a target-specific pass in \fIarc_reorg\fR to +generate compare-and-branch (\f(CW\*(C`br\f(CIcc\f(CW\*(C'\fR) instructions. +It has no effect on +generation of these instructions driven by the combiner pass. +.IP "\fB\-mcase\-vector\-pcrel\fR" 4 +.IX Item "-mcase-vector-pcrel" +Use PC-relative switch case tables to enable case table shortening. +This is the default for \fB\-Os\fR. +.IP "\fB\-mcompact\-casesi\fR" 4 +.IX Item "-mcompact-casesi" +Enable compact \f(CW\*(C`casesi\*(C'\fR pattern. This is the default for \fB\-Os\fR, +and only available for ARCv1 cores. This option is deprecated. +.IP "\fB\-mno\-cond\-exec\fR" 4 +.IX Item "-mno-cond-exec" +Disable the ARCompact-specific pass to generate conditional +execution instructions. +.Sp +Due to delay slot scheduling and interactions between operand numbers, +literal sizes, instruction lengths, and the support for conditional execution, +the target-independent pass to generate conditional execution is often lacking, +so the \s-1ARC\s0 port has kept a special pass around that tries to find more +conditional execution generation opportunities after register allocation, +branch shortening, and delay slot scheduling have been done. This pass +generally, but not always, improves performance and code size, at the cost of +extra compilation time, which is why there is an option to switch it off. +If you have a problem with call instructions exceeding their allowable +offset range because they are conditionalized, you should consider using +\&\fB\-mmedium\-calls\fR instead. +.IP "\fB\-mearly\-cbranchsi\fR" 4 +.IX Item "-mearly-cbranchsi" +Enable pre-reload use of the \f(CW\*(C`cbranchsi\*(C'\fR pattern. +.IP "\fB\-mexpand\-adddi\fR" 4 +.IX Item "-mexpand-adddi" +Expand \f(CW\*(C`adddi3\*(C'\fR and \f(CW\*(C`subdi3\*(C'\fR at \s-1RTL\s0 generation time into +\&\f(CW\*(C`add.f\*(C'\fR, \f(CW\*(C`adc\*(C'\fR etc. This option is deprecated. +.IP "\fB\-mindexed\-loads\fR" 4 +.IX Item "-mindexed-loads" +Enable the use of indexed loads. This can be problematic because some +optimizers then assume that indexed stores exist, which is not +the case. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Enable Local Register Allocation. This is still experimental for \s-1ARC,\s0 +so by default the compiler uses standard reload +(i.e. \fB\-mno\-lra\fR). +.IP "\fB\-mlra\-priority\-none\fR" 4 +.IX Item "-mlra-priority-none" +Don't indicate any priority for target registers. +.IP "\fB\-mlra\-priority\-compact\fR" 4 +.IX Item "-mlra-priority-compact" +Indicate target register priority for r0..r3 / r12..r15. +.IP "\fB\-mlra\-priority\-noncompact\fR" 4 +.IX Item "-mlra-priority-noncompact" +Reduce target register priority for r0..r3 / r12..r15. +.IP "\fB\-mmillicode\fR" 4 +.IX Item "-mmillicode" +When optimizing for size (using \fB\-Os\fR), prologues and epilogues +that have to save or restore a large number of registers are often +shortened by using call to a special function in libgcc; this is +referred to as a \fImillicode\fR call. As these calls can pose +performance issues, and/or cause linking issues when linking in a +nonstandard way, this option is provided to turn on or off millicode +call generation. +.IP "\fB\-mcode\-density\-frame\fR" 4 +.IX Item "-mcode-density-frame" +This option enable the compiler to emit \f(CW\*(C`enter\*(C'\fR and \f(CW\*(C`leave\*(C'\fR +instructions. These instructions are only valid for CPUs with +code-density feature. +.IP "\fB\-mmixed\-code\fR" 4 +.IX Item "-mmixed-code" +Tweak register allocation to help 16\-bit instruction generation. +This generally has the effect of decreasing the average instruction size +while increasing the instruction count. +.IP "\fB\-mq\-class\fR" 4 +.IX Item "-mq-class" +Enable \fBq\fR instruction alternatives. +This is the default for \fB\-Os\fR. +.IP "\fB\-mRcq\fR" 4 +.IX Item "-mRcq" +Enable \fBRcq\fR constraint handling. +Most short code generation depends on this. +This is the default. +.IP "\fB\-mRcw\fR" 4 +.IX Item "-mRcw" +Enable \fBRcw\fR constraint handling. +Most ccfsm condexec mostly depends on this. +This is the default. +.IP "\fB\-msize\-level=\fR\fIlevel\fR" 4 +.IX Item "-msize-level=level" +Fine-tune size optimization with regards to instruction lengths and alignment. +The recognized values for \fIlevel\fR are: +.RS 4 +.IP "\fB0\fR" 4 +.IX Item "0" +No size optimization. This level is deprecated and treated like \fB1\fR. +.IP "\fB1\fR" 4 +.IX Item "1" +Short instructions are used opportunistically. +.IP "\fB2\fR" 4 +.IX Item "2" +In addition, alignment of loops and of code after barriers are dropped. +.IP "\fB3\fR" 4 +.IX Item "3" +In addition, optional data alignment is dropped, and the option \fBOs\fR is enabled. +.RE +.RS 4 +.Sp +This defaults to \fB3\fR when \fB\-Os\fR is in effect. Otherwise, +the behavior when this is not set is equivalent to level \fB1\fR. +.RE +.IP "\fB\-mtune=\fR\fIcpu\fR" 4 +.IX Item "-mtune=cpu" +Set instruction scheduling parameters for \fIcpu\fR, overriding any implied +by \fB\-mcpu=\fR. +.Sp +Supported values for \fIcpu\fR are +.RS 4 +.IP "\fB\s-1ARC600\s0\fR" 4 +.IX Item "ARC600" +Tune for \s-1ARC600 CPU.\s0 +.IP "\fB\s-1ARC601\s0\fR" 4 +.IX Item "ARC601" +Tune for \s-1ARC601 CPU.\s0 +.IP "\fB\s-1ARC700\s0\fR" 4 +.IX Item "ARC700" +Tune for \s-1ARC700 CPU\s0 with standard multiplier block. +.IP "\fBARC700\-xmac\fR" 4 +.IX Item "ARC700-xmac" +Tune for \s-1ARC700 CPU\s0 with \s-1XMAC\s0 block. +.IP "\fB\s-1ARC725D\s0\fR" 4 +.IX Item "ARC725D" +Tune for \s-1ARC725D CPU.\s0 +.IP "\fB\s-1ARC750D\s0\fR" 4 +.IX Item "ARC750D" +Tune for \s-1ARC750D CPU.\s0 +.RE +.RS 4 +.RE +.IP "\fB\-mmultcost=\fR\fInum\fR" 4 +.IX Item "-mmultcost=num" +Cost to assume for a multiply instruction, with \fB4\fR being equal to a +normal instruction. +.IP "\fB\-munalign\-prob\-threshold=\fR\fIprobability\fR" 4 +.IX Item "-munalign-prob-threshold=probability" +Set probability threshold for unaligning branches. +When tuning for \fB\s-1ARC700\s0\fR and optimizing for speed, branches without +filled delay slot are preferably emitted unaligned and long, unless +profiling indicates that the probability for the branch to be taken +is below \fIprobability\fR. +The default is (\s-1REG_BR_PROB_BASE/2\s0), i.e. 5000. +.PP +The following options are maintained for backward compatibility, but +are now deprecated and will be removed in a future release: +.IP "\fB\-margonaut\fR" 4 +.IX Item "-margonaut" +Obsolete \s-1FPX.\s0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +.PD +Compile code for big-endian targets. Use of these options is now +deprecated. Big-endian code is supported by configuring \s-1GCC\s0 to build +\&\f(CW\*(C`arceb\-elf32\*(C'\fR and \f(CW\*(C`arceb\-linux\-uclibc\*(C'\fR targets, +for which big endian is the default. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD 0 +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +.PD +Compile code for little-endian targets. Use of these options is now +deprecated. Little-endian code is supported by configuring \s-1GCC\s0 to build +\&\f(CW\*(C`arc\-elf32\*(C'\fR and \f(CW\*(C`arc\-linux\-uclibc\*(C'\fR targets, +for which little endian is the default. +.IP "\fB\-mbarrel_shifter\fR" 4 +.IX Item "-mbarrel_shifter" +Replaced by \fB\-mbarrel\-shifter\fR. +.IP "\fB\-mdpfp_compact\fR" 4 +.IX Item "-mdpfp_compact" +Replaced by \fB\-mdpfp\-compact\fR. +.IP "\fB\-mdpfp_fast\fR" 4 +.IX Item "-mdpfp_fast" +Replaced by \fB\-mdpfp\-fast\fR. +.IP "\fB\-mdsp_packa\fR" 4 +.IX Item "-mdsp_packa" +Replaced by \fB\-mdsp\-packa\fR. +.IP "\fB\-mEA\fR" 4 +.IX Item "-mEA" +Replaced by \fB\-mea\fR. +.IP "\fB\-mmac_24\fR" 4 +.IX Item "-mmac_24" +Replaced by \fB\-mmac\-24\fR. +.IP "\fB\-mmac_d16\fR" 4 +.IX Item "-mmac_d16" +Replaced by \fB\-mmac\-d16\fR. +.IP "\fB\-mspfp_compact\fR" 4 +.IX Item "-mspfp_compact" +Replaced by \fB\-mspfp\-compact\fR. +.IP "\fB\-mspfp_fast\fR" 4 +.IX Item "-mspfp_fast" +Replaced by \fB\-mspfp\-fast\fR. +.IP "\fB\-mtune=\fR\fIcpu\fR" 4 +.IX Item "-mtune=cpu" +Values \fBarc600\fR, \fBarc601\fR, \fBarc700\fR and +\&\fBarc700\-xmac\fR for \fIcpu\fR are replaced by \fB\s-1ARC600\s0\fR, +\&\fB\s-1ARC601\s0\fR, \fB\s-1ARC700\s0\fR and \fBARC700\-xmac\fR respectively. +.IP "\fB\-multcost=\fR\fInum\fR" 4 +.IX Item "-multcost=num" +Replaced by \fB\-mmultcost\fR. +.PP +\fI\s-1ARM\s0 Options\fR +.IX Subsection "ARM Options" +.PP +These \fB\-m\fR options are defined for the \s-1ARM\s0 port: +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified \s-1ABI.\s0 Permissible values are: \fBapcs-gnu\fR, +\&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. +.IP "\fB\-mapcs\-frame\fR" 4 +.IX Item "-mapcs-frame" +Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call +Standard for all functions, even if this is not strictly necessary for +correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR +with this option causes the stack frames not to be generated for +leaf functions. The default is \fB\-mno\-apcs\-frame\fR. +This option is deprecated. +.IP "\fB\-mapcs\fR" 4 +.IX Item "-mapcs" +This is a synonym for \fB\-mapcs\-frame\fR and is deprecated. +.IP "\fB\-mthumb\-interwork\fR" 4 +.IX Item "-mthumb-interwork" +Generate code that supports calling between the \s-1ARM\s0 and Thumb +instruction sets. Without this option, on pre\-v5 architectures, the +two instruction sets cannot be reliably used inside one program. The +default is \fB\-mno\-thumb\-interwork\fR, since slightly larger code +is generated when \fB\-mthumb\-interwork\fR is specified. In \s-1AAPCS\s0 +configurations this option is meaningless. +.IP "\fB\-mno\-sched\-prolog\fR" 4 +.IX Item "-mno-sched-prolog" +Prevent the reordering of instructions in the function prologue, or the +merging of those instruction with the instructions in the function's +body. This means that all functions start with a recognizable set +of instructions (or in fact one of a choice from a small set of +different function prologues), and this information can be used to +locate the start of functions inside an executable piece of code. The +default is \fB\-msched\-prolog\fR. +.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4 +.IX Item "-mfloat-abi=name" +Specifies which floating-point \s-1ABI\s0 to use. Permissible values +are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR. +.Sp +Specifying \fBsoft\fR causes \s-1GCC\s0 to generate output containing +library calls for floating-point operations. +\&\fBsoftfp\fR allows the generation of code using hardware floating-point +instructions, but still uses the soft-float calling conventions. +\&\fBhard\fR allows generation of floating-point instructions +and uses FPU-specific calling conventions. +.Sp +The default depends on the specific target configuration. Note that +the hard-float and soft-float ABIs are not link-compatible; you must +compile your entire program with the same \s-1ABI,\s0 and link with a +compatible set of libraries. +.IP "\fB\-mgeneral\-regs\-only\fR" 4 +.IX Item "-mgeneral-regs-only" +Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced \s-1SIMD\s0 registers but will not +impose any restrictions on the assembler. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a processor running in little-endian mode. This is +the default for all standard configurations. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a processor running in big-endian mode; the default is +to compile code for a little-endian processor. +.IP "\fB\-mbe8\fR" 4 +.IX Item "-mbe8" +.PD 0 +.IP "\fB\-mbe32\fR" 4 +.IX Item "-mbe32" +.PD +When linking a big-endian image select between \s-1BE8\s0 and \s-1BE32\s0 formats. +The option has no effect for little-endian images and is ignored. The +default is dependent on the selected target architecture. For ARMv6 +and later architectures the default is \s-1BE8,\s0 for older architectures +the default is \s-1BE32.\s0 \s-1BE32\s0 format has been deprecated by \s-1ARM.\s0 +.IP "\fB\-march=\fR\fIname\fR[\fB+extension...\fR]" 4 +.IX Item "-march=name[+extension...]" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. +.Sp +Permissible names are: +\&\fBarmv4t\fR, +\&\fBarmv5t\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, \fBarmv6k\fR, \fBarmv6kz\fR, \fBarmv6t2\fR, +\&\fBarmv6z\fR, \fBarmv6zk\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7ve\fR, +\&\fBarmv8\-a\fR, \fBarmv8.1\-a\fR, \fBarmv8.2\-a\fR, \fBarmv8.3\-a\fR, +\&\fBarmv8.4\-a\fR, +\&\fBarmv8.5\-a\fR, +\&\fBarmv7\-r\fR, +\&\fBarmv8\-r\fR, +\&\fBarmv6\-m\fR, \fBarmv6s\-m\fR, +\&\fBarmv7\-m\fR, \fBarmv7e\-m\fR, +\&\fBarmv8\-m.base\fR, \fBarmv8\-m.main\fR, +\&\fBiwmmxt\fR and \fBiwmmxt2\fR. +.Sp +Additionally, the following architectures, which lack support for the +Thumb execution state, are recognized but support is deprecated: \fBarmv4\fR. +.Sp +Many of the architectures support extensions. These can be added by +appending \fB+\fR\fIextension\fR to the architecture name. Extension +options are processed in order and capabilities accumulate. An extension +will also enable any necessary base extensions +upon which it depends. For example, the \fB+crypto\fR extension +will always enable the \fB+simd\fR extension. The exception to the +additive construction is for extensions that are prefixed with +\&\fB+no...\fR: these extensions disable the specified option and +any other extensions that may depend on the presence of that +extension. +.Sp +For example, \fB\-march=armv7\-a+simd+nofp+vfpv4\fR is equivalent to +writing \fB\-march=armv7\-a+vfpv4\fR since the \fB+simd\fR option is +entirely disabled by the \fB+nofp\fR option that follows it. +.Sp +Most extension names are generically named, but have an effect that is +dependent upon the architecture to which it is applied. For example, +the \fB+simd\fR option can be applied to both \fBarmv7\-a\fR and +\&\fBarmv8\-a\fR architectures, but will enable the original ARMv7\-A +Advanced \s-1SIMD\s0 (Neon) extensions for \fBarmv7\-a\fR and the ARMv8\-A +variant for \fBarmv8\-a\fR. +.Sp +The table below lists the supported extensions for each architecture. +Architectures not mentioned do not support any extensions. +.RS 4 +.IP "\fBarmv5te\fR" 4 +.IX Item "armv5te" +.PD 0 +.IP "\fBarmv6\fR" 4 +.IX Item "armv6" +.IP "\fBarmv6j\fR" 4 +.IX Item "armv6j" +.IP "\fBarmv6k\fR" 4 +.IX Item "armv6k" +.IP "\fBarmv6kz\fR" 4 +.IX Item "armv6kz" +.IP "\fBarmv6t2\fR" 4 +.IX Item "armv6t2" +.IP "\fBarmv6z\fR" 4 +.IX Item "armv6z" +.IP "\fBarmv6zk\fR" 4 +.IX Item "armv6zk" +.RS 4 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +.PD +The VFPv2 floating-point instructions. The extension \fB+vfpv2\fR can be +used as an alias for this extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7\fR" 4 +.IX Item "armv7" +The common subset of the ARMv7\-A, ARMv7\-R and ARMv7\-M architectures. +.RS 4 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension \fB+vfpv3\-d16\fR can be used as an alias +for this extension. Note that floating-point is not supported by the +base ARMv7\-M architecture, but is compatible with both the ARMv7\-A and +ARMv7\-R architectures. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7\-a\fR" 4 +.IX Item "armv7-a" +.RS 4 +.PD 0 +.IP "\fB+mp\fR" 4 +.IX Item "+mp" +.PD +The multiprocessing extension. +.IP "\fB+sec\fR" 4 +.IX Item "+sec" +The security extension. +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension \fB+vfpv3\-d16\fR can be used as an alias +for this extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions. +The extensions \fB+neon\fR and \fB+neon\-vfpv3\fR can be used as aliases +for this extension. +.IP "\fB+vfpv3\fR" 4 +.IX Item "+vfpv3" +The VFPv3 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+vfpv3\-d16\-fp16\fR" 4 +.IX Item "+vfpv3-d16-fp16" +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv3\-fp16\fR" 4 +.IX Item "+vfpv3-fp16" +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv4\-d16\fR" 4 +.IX Item "+vfpv4-d16" +The VFPv4 floating-point instructions, with 16 double-precision +registers. +.IP "\fB+vfpv4\fR" 4 +.IX Item "+vfpv4" +The VFPv4 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+neon\-fp16\fR" 4 +.IX Item "+neon-fp16" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. +.IP "\fB+neon\-vfpv4\fR" 4 +.IX Item "+neon-vfpv4" +The Advanced \s-1SIMD\s0 (Neon) v2 and the VFPv4 floating-point instructions. +.IP "\fB+nosimd\fR" 4 +.IX Item "+nosimd" +Disable the Advanced \s-1SIMD\s0 instructions (does not disable floating point). +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point and Advanced \s-1SIMD\s0 instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7ve\fR" 4 +.IX Item "armv7ve" +The extended version of the ARMv7\-A architecture with support for +virtualization. +.RS 4 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv4 floating-point instructions, with 16 double-precision registers. +The extension \fB+vfpv4\-d16\fR can be used as an alias for this extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The Advanced \s-1SIMD\s0 (Neon) v2 and the VFPv4 floating-point instructions. The +extension \fB+neon\-vfpv4\fR can be used as an alias for this extension. +.IP "\fB+vfpv3\-d16\fR" 4 +.IX Item "+vfpv3-d16" +The VFPv3 floating-point instructions, with 16 double-precision +registers. +.IP "\fB+vfpv3\fR" 4 +.IX Item "+vfpv3" +The VFPv3 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+vfpv3\-d16\-fp16\fR" 4 +.IX Item "+vfpv3-d16-fp16" +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv3\-fp16\fR" 4 +.IX Item "+vfpv3-fp16" +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv4\-d16\fR" 4 +.IX Item "+vfpv4-d16" +The VFPv4 floating-point instructions, with 16 double-precision +registers. +.IP "\fB+vfpv4\fR" 4 +.IX Item "+vfpv4" +The VFPv4 floating-point instructions, with 32 double-precision +registers. +.IP "\fB+neon\fR" 4 +.IX Item "+neon" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions. +The extension \fB+neon\-vfpv3\fR can be used as an alias for this extension. +.IP "\fB+neon\-fp16\fR" 4 +.IX Item "+neon-fp16" +The Advanced \s-1SIMD\s0 (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. +.IP "\fB+nosimd\fR" 4 +.IX Item "+nosimd" +Disable the Advanced \s-1SIMD\s0 instructions (does not disable floating point). +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point and Advanced \s-1SIMD\s0 instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8\-a\fR" 4 +.IX Item "armv8-a" +.RS 4 +.PD 0 +.IP "\fB+crc\fR" 4 +.IX Item "+crc" +.PD +The Cyclic Redundancy Check (\s-1CRC\s0) instructions. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.1\-a\fR" 4 +.IX Item "armv8.1-a" +.RS 4 +.PD 0 +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +.PD +The ARMv8.1\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.2\-a\fR" 4 +.IX Item "armv8.2-a" +.PD 0 +.IP "\fBarmv8.3\-a\fR" 4 +.IX Item "armv8.3-a" +.RS 4 +.IP "\fB+fp16\fR" 4 +.IX Item "+fp16" +.PD +The half-precision floating-point data processing instructions. +This also enables the Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+fp16fml\fR" 4 +.IX Item "+fp16fml" +The half-precision floating-point fmla extension. This also enables +the half-precision floating-point extension and Advanced \s-1SIMD\s0 and +floating-point instructions. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8.1\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions. +.IP "\fB+dotprod\fR" 4 +.IX Item "+dotprod" +Enable the Dot Product extension. This also enables Advanced \s-1SIMD\s0 instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.4\-a\fR" 4 +.IX Item "armv8.4-a" +.RS 4 +.PD 0 +.IP "\fB+fp16\fR" 4 +.IX Item "+fp16" +.PD +The half-precision floating-point data processing instructions. +This also enables the Advanced \s-1SIMD\s0 and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8.3\-A Advanced \s-1SIMD\s0 and floating-point instructions as well as the +Dot Product extension. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions as well as the Dot Product extension. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.IP "\fB+sb\fR" 4 +.IX Item "+sb" +Speculation Barrier Instruction. +.IP "\fB+predres\fR" 4 +.IX Item "+predres" +Execution and Data Prediction Restriction Instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv8.5\-a\fR" 4 +.IX Item "armv8.5-a" +.RS 4 +.PD 0 +.IP "\fB+fp16\fR" 4 +.IX Item "+fp16" +.PD +The half-precision floating-point data processing instructions. +This also enables the Advanced \s-1SIMD\s0 and floating-point instructions as well +as the Dot Product extension and the half-precision floating-point fmla +extension. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8.3\-A Advanced \s-1SIMD\s0 and floating-point instructions as well as the +Dot Product extension. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. This also enables the Advanced \s-1SIMD\s0 and +floating-point instructions as well as the Dot Product extension. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic extension. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.RE +.RS 4 +.RE +.IP "\fBarmv7\-r\fR" 4 +.IX Item "armv7-r" +.RS 4 +.PD 0 +.IP "\fB+fp.sp\fR" 4 +.IX Item "+fp.sp" +.PD +The single-precision VFPv3 floating-point instructions. The extension +\&\fB+vfpv3xd\fR can be used as an alias for this extension. +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The VFPv3 floating-point instructions with 16 double-precision registers. +The extension +vfpv3\-d16 can be used as an alias for this extension. +.IP "\fB+vfpv3xd\-d16\-fp16\fR" 4 +.IX Item "+vfpv3xd-d16-fp16" +The single-precision VFPv3 floating-point instructions with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+vfpv3\-d16\-fp16\fR" 4 +.IX Item "+vfpv3-d16-fp16" +The VFPv3 floating-point instructions with 16 double-precision +registers and the half-precision floating-point conversion operations. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point extension. +.IP "\fB+idiv\fR" 4 +.IX Item "+idiv" +The ARM-state integer division instructions. +.IP "\fB+noidiv\fR" 4 +.IX Item "+noidiv" +Disable the ARM-state integer division extension. +.RE +.RS 4 +.RE +.IP "\fBarmv7e\-m\fR" 4 +.IX Item "armv7e-m" +.RS 4 +.PD 0 +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +.PD +The single-precision VFPv4 floating-point instructions. +.IP "\fB+fpv5\fR" 4 +.IX Item "+fpv5" +The single-precision FPv5 floating-point instructions. +.IP "\fB+fp.dp\fR" 4 +.IX Item "+fp.dp" +The single\- and double-precision FPv5 floating-point instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point extensions. +.RE +.RS 4 +.RE +.IP "\fBarmv8\-m.main\fR" 4 +.IX Item "armv8-m.main" +.RS 4 +.PD 0 +.IP "\fB+dsp\fR" 4 +.IX Item "+dsp" +.PD +The \s-1DSP\s0 instructions. +.IP "\fB+nodsp\fR" 4 +.IX Item "+nodsp" +Disable the \s-1DSP\s0 extension. +.IP "\fB+fp\fR" 4 +.IX Item "+fp" +The single-precision floating-point instructions. +.IP "\fB+fp.dp\fR" 4 +.IX Item "+fp.dp" +The single\- and double-precision floating-point instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point extension. +.RE +.RS 4 +.RE +.IP "\fBarmv8\-r\fR" 4 +.IX Item "armv8-r" +.RS 4 +.PD 0 +.IP "\fB+crc\fR" 4 +.IX Item "+crc" +.PD +The Cyclic Redundancy Check (\s-1CRC\s0) instructions. +.IP "\fB+fp.sp\fR" 4 +.IX Item "+fp.sp" +The single-precision FPv5 floating-point instructions. +.IP "\fB+simd\fR" 4 +.IX Item "+simd" +The ARMv8\-A Advanced \s-1SIMD\s0 and floating-point instructions. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +The cryptographic instructions. +.IP "\fB+nocrypto\fR" 4 +.IX Item "+nocrypto" +Disable the cryptographic instructions. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disable the floating-point, Advanced \s-1SIMD\s0 and cryptographic instructions. +.RE +.RS 4 +.RE +.RE +.RS 4 +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. +.RE +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR, \fBarm710t\fR, +\&\fBarm720t\fR, \fBarm740t\fR, \fBstrongarm\fR, \fBstrongarm110\fR, +\&\fBstrongarm1100\fR, 0\fBstrongarm1110\fR, \fBarm8\fR, \fBarm810\fR, +\&\fBarm9\fR, \fBarm9e\fR, \fBarm920\fR, \fBarm920t\fR, \fBarm922t\fR, +\&\fBarm946e\-s\fR, \fBarm966e\-s\fR, \fBarm968e\-s\fR, \fBarm926ej\-s\fR, +\&\fBarm940t\fR, \fBarm9tdmi\fR, \fBarm10tdmi\fR, \fBarm1020t\fR, +\&\fBarm1026ej\-s\fR, \fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR, +\&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR, +\&\fBarm1156t2\-s\fR, \fBarm1156t2f\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, +\&\fBgeneric\-armv7\-a\fR, \fBcortex\-a5\fR, \fBcortex\-a7\fR, \fBcortex\-a8\fR, +\&\fBcortex\-a9\fR, \fBcortex\-a12\fR, \fBcortex\-a15\fR, \fBcortex\-a17\fR, +\&\fBcortex\-a32\fR, \fBcortex\-a35\fR, \fBcortex\-a53\fR, \fBcortex\-a55\fR, +\&\fBcortex\-a57\fR, \fBcortex\-a72\fR, \fBcortex\-a73\fR, \fBcortex\-a75\fR, +\&\fBcortex\-a76\fR, \fBares\fR, \fBcortex\-r4\fR, \fBcortex\-r4f\fR, +\&\fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-r8\fR, \fBcortex\-r52\fR, +\&\fBcortex\-m0\fR, \fBcortex\-m0plus\fR, \fBcortex\-m1\fR, \fBcortex\-m3\fR, +\&\fBcortex\-m4\fR, \fBcortex\-m7\fR, \fBcortex\-m23\fR, \fBcortex\-m33\fR, +\&\fBcortex\-m1.small\-multiply\fR, \fBcortex\-m0.small\-multiply\fR, +\&\fBcortex\-m0plus.small\-multiply\fR, \fBexynos\-m1\fR, \fBmarvell\-pj4\fR, +\&\fBneoverse\-n1\fR, \fBneoverse\-n2\fR, \fBneoverse\-v1\fR, \fBxscale\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR, \fBfa526\fR, \fBfa626\fR, +\&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR, \fBxgene1\fR. +.Sp +Additionally, this option can specify that \s-1GCC\s0 should tune the performance +of the code for a big.LITTLE system. Permissible names are: +\&\fBcortex\-a15.cortex\-a7\fR, \fBcortex\-a17.cortex\-a7\fR, +\&\fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a72.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR, +\&\fBcortex\-a75.cortex\-a55\fR, \fBcortex\-a76.cortex\-a55\fR. +.Sp +\&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the +performance for a blend of processors within architecture \fIarch\fR. +The aim is to generate code that run well on the current most popular +processors, balancing between optimizations that benefit some CPUs in the +range, and avoiding performance pitfalls of other CPUs. The effects of +this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come and go. +.Sp +\&\fB\-mtune\fR permits the same extension options as \fB\-mcpu\fR, but +the extension options do not affect the tuning of the generated code. +.Sp +\&\fB\-mtune=native\fR causes the compiler to auto-detect the \s-1CPU\s0 +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mcpu=\fR\fIname\fR[\fB+extension...\fR]" 4 +.IX Item "-mcpu=name[+extension...]" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. +.Sp +Many of the supported CPUs implement optional architectural +extensions. Where this is so the architectural extensions are +normally enabled by default. If implementations that lack the +extension exist, then the extension syntax can be used to disable +those extensions that have been omitted. For floating-point and +Advanced \s-1SIMD\s0 (Neon) instructions, the settings of the options +\&\fB\-mfloat\-abi\fR and \fB\-mfpu\fR must also be considered: +floating-point and Advanced \s-1SIMD\s0 instructions will only be used if +\&\fB\-mfloat\-abi\fR is not set to \fBsoft\fR; and any setting of +\&\fB\-mfpu\fR other than \fBauto\fR will override the available +floating-point and \s-1SIMD\s0 extension instructions. +.Sp +For example, \fBcortex\-a9\fR can be found in three major +configurations: integer only, with just a floating-point unit or with +floating-point and Advanced \s-1SIMD.\s0 The default is to enable all the +instructions, but the extensions \fB+nosimd\fR and \fB+nofp\fR can +be used to disable just the \s-1SIMD\s0 or both the \s-1SIMD\s0 and floating-point +instructions respectively. +.Sp +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +The following extension options are common to the listed CPUs: +.RS 4 +.IP "\fB+nodsp\fR" 4 +.IX Item "+nodsp" +Disable the \s-1DSP\s0 instructions on \fBcortex\-m33\fR. +.IP "\fB+nofp\fR" 4 +.IX Item "+nofp" +Disables the floating-point instructions on \fBarm9e\fR, +\&\fBarm946e\-s\fR, \fBarm966e\-s\fR, \fBarm968e\-s\fR, \fBarm10e\fR, +\&\fBarm1020e\fR, \fBarm1022e\fR, \fBarm926ej\-s\fR, +\&\fBarm1026ej\-s\fR, \fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-r8\fR, +\&\fBcortex\-m4\fR, \fBcortex\-m7\fR and \fBcortex\-m33\fR. +Disables the floating-point and \s-1SIMD\s0 instructions on +\&\fBgeneric\-armv7\-a\fR, \fBcortex\-a5\fR, \fBcortex\-a7\fR, +\&\fBcortex\-a8\fR, \fBcortex\-a9\fR, \fBcortex\-a12\fR, +\&\fBcortex\-a15\fR, \fBcortex\-a17\fR, \fBcortex\-a15.cortex\-a7\fR, +\&\fBcortex\-a17.cortex\-a7\fR, \fBcortex\-a32\fR, \fBcortex\-a35\fR, +\&\fBcortex\-a53\fR and \fBcortex\-a55\fR. +.IP "\fB+nofp.dp\fR" 4 +.IX Item "+nofp.dp" +Disables the double-precision component of the floating-point instructions +on \fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-r8\fR, \fBcortex\-r52\fR and +\&\fBcortex\-m7\fR. +.IP "\fB+nosimd\fR" 4 +.IX Item "+nosimd" +Disables the \s-1SIMD\s0 (but not floating-point) instructions on +\&\fBgeneric\-armv7\-a\fR, \fBcortex\-a5\fR, \fBcortex\-a7\fR +and \fBcortex\-a9\fR. +.IP "\fB+crypto\fR" 4 +.IX Item "+crypto" +Enables the cryptographic instructions on \fBcortex\-a32\fR, +\&\fBcortex\-a35\fR, \fBcortex\-a53\fR, \fBcortex\-a55\fR, \fBcortex\-a57\fR, +\&\fBcortex\-a72\fR, \fBcortex\-a73\fR, \fBcortex\-a75\fR, \fBexynos\-m1\fR, +\&\fBxgene1\fR, \fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR, +\&\fBcortex\-a73.cortex\-a35\fR, \fBcortex\-a73.cortex\-a53\fR and +\&\fBcortex\-a75.cortex\-a55\fR. +.RE +.RS 4 +.Sp +Additionally the \fBgeneric\-armv7\-a\fR pseudo target defaults to +VFPv3 with 16 double-precision registers. It supports the following +extension options: \fBmp\fR, \fBsec\fR, \fBvfpv3\-d16\fR, +\&\fBvfpv3\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3\-fp16\fR, +\&\fBvfpv4\-d16\fR, \fBvfpv4\fR, \fBneon\fR, \fBneon\-vfpv3\fR, +\&\fBneon\-fp16\fR, \fBneon\-vfpv4\fR. The meanings are the same as for +the extensions to \fB\-march=armv7\-a\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 +of the build computer. At present, this feature is only supported on +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. +.RE +.IP "\fB\-mfpu=\fR\fIname\fR" 4 +.IX Item "-mfpu=name" +This specifies what floating-point hardware (or hardware emulation) is +available on the target. Permissible names are: \fBauto\fR, \fBvfpv2\fR, +\&\fBvfpv3\fR, +\&\fBvfpv3\-fp16\fR, \fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR, +\&\fBvfpv3xd\-fp16\fR, \fBneon\-vfpv3\fR, \fBneon\-fp16\fR, \fBvfpv4\fR, +\&\fBvfpv4\-d16\fR, \fBfpv4\-sp\-d16\fR, \fBneon\-vfpv4\fR, +\&\fBfpv5\-d16\fR, \fBfpv5\-sp\-d16\fR, +\&\fBfp\-armv8\fR, \fBneon\-fp\-armv8\fR and \fBcrypto\-neon\-fp\-armv8\fR. +Note that \fBneon\fR is an alias for \fBneon\-vfpv3\fR and \fBvfp\fR +is an alias for \fBvfpv2\fR. +.Sp +The setting \fBauto\fR is the default and is special. It causes the +compiler to select the floating-point and Advanced \s-1SIMD\s0 instructions +based on the settings of \fB\-mcpu\fR and \fB\-march\fR. +.Sp +If the selected floating-point hardware includes the \s-1NEON\s0 extension +(e.g. \fB\-mfpu=neon\fR), note that floating-point +operations are not generated by \s-1GCC\s0's auto-vectorization pass unless +\&\fB\-funsafe\-math\-optimizations\fR is also specified. This is +because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE 754\s0 standard for +floating-point arithmetic (in particular denormal values are treated as +zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. +.Sp +You can also set the fpu name at function level by using the \f(CW\*(C`target("fpu=")\*(C'\fR function attributes or pragmas. +.IP "\fB\-mfp16\-format=\fR\fIname\fR" 4 +.IX Item "-mfp16-format=name" +Specify the format of the \f(CW\*(C`_\|_fp16\*(C'\fR half-precision floating-point type. +Permissible names are \fBnone\fR, \fBieee\fR, and \fBalternative\fR; +the default is \fBnone\fR, in which case the \f(CW\*(C`_\|_fp16\*(C'\fR type is not +defined. +.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4 +.IX Item "-mstructure-size-boundary=n" +The sizes of all structures and unions are rounded up to a multiple +of the number of bits set by this option. Permissible values are 8, 32 +and 64. The default value varies for different toolchains. For the \s-1COFF\s0 +targeted toolchain the default value is 8. A value of 64 is only allowed +if the underlying \s-1ABI\s0 supports it. +.Sp +Specifying a larger number can produce faster, more efficient code, but +can also increase the size of the program. Different values are potentially +incompatible. Code compiled with one value cannot necessarily expect to +work with code or libraries compiled with another value, if they exchange +information using structures or unions. +.Sp +This option is deprecated. +.IP "\fB\-mabort\-on\-noreturn\fR" 4 +.IX Item "-mabort-on-noreturn" +Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a +\&\f(CW\*(C`noreturn\*(C'\fR function. It is executed if the function tries to +return. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +lies outside of the 64\-megabyte addressing range of the offset-based +version of subroutine call instruction. +.Sp +Even if this switch is enabled, not all function calls are turned +into long calls. The heuristic is that static functions, functions +that have the \f(CW\*(C`short_call\*(C'\fR attribute, functions that are inside +the scope of a \f(CW\*(C`#pragma no_long_calls\*(C'\fR directive, and functions whose +definitions have already been compiled within the current compilation +unit are not turned into long calls. The exceptions to this rule are +that weak function definitions, functions with the \f(CW\*(C`long_call\*(C'\fR +attribute or the \f(CW\*(C`section\*(C'\fR attribute, and functions that are within +the scope of a \f(CW\*(C`#pragma long_calls\*(C'\fR directive are always +turned into long calls. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR restores the default behavior, as does +placing the function calls within the scope of a \f(CW\*(C`#pragma +long_calls_off\*(C'\fR directive. Note these switches have no effect on how +the compiler generates code to handle function calls via function +pointers. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The runtime system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 +.IX Item "-mpic-register=reg" +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default is any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. +.IP "\fB\-mpic\-data\-is\-text\-relative\fR" 4 +.IX Item "-mpic-data-is-text-relative" +Assume that the displacement between the text and data segments is fixed +at static link time. This permits using PC-relative addressing +operations to access data known to be in the data segment. For +non-VxWorks \s-1RTP\s0 targets, this option is enabled by default. When +disabled on such targets, it will enable \fB\-msingle\-pic\-base\fR by +default. +.IP "\fB\-mpoke\-function\-name\fR" 4 +.IX Item "-mpoke-function-name" +Write the name of each function into the text section, directly +preceding the function prologue. The generated code is similar to this: +.Sp +.Vb 9 +\& t0 +\& .ascii "arm_poke_function_name", 0 +\& .align +\& t1 +\& .word 0xff000000 + (t1 \- t0) +\& arm_poke_function_name +\& mov ip, sp +\& stmfd sp!, {fp, ip, lr, pc} +\& sub fp, ip, #4 +.Ve +.Sp +When performing a stack backtrace, code can inspect the value of +\&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR. If the trace function then looks at +location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that +there is a function name embedded immediately preceding this location +and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR. +.IP "\fB\-mthumb\fR" 4 +.IX Item "-mthumb" +.PD 0 +.IP "\fB\-marm\fR" 4 +.IX Item "-marm" +.PD +Select between generating code that executes in \s-1ARM\s0 and Thumb +states. The default for most configurations is to generate code +that executes in \s-1ARM\s0 state, but the default can be changed by +configuring \s-1GCC\s0 with the \fB\-\-with\-mode=\fR\fIstate\fR +configure option. +.Sp +You can also override the \s-1ARM\s0 and Thumb mode for each function +by using the \f(CW\*(C`target("thumb")\*(C'\fR and \f(CW\*(C`target("arm")\*(C'\fR function attributes or pragmas. +.IP "\fB\-mflip\-thumb\fR" 4 +.IX Item "-mflip-thumb" +Switch ARM/Thumb modes on alternating functions. +This option is provided for regression testing of mixed Thumb/ARM code +generation, and is not intended for ordinary use in compiling code. +.IP "\fB\-mtpcs\-frame\fR" 4 +.IX Item "-mtpcs-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all non-leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-tpcs\-frame\fR. +.IP "\fB\-mtpcs\-leaf\-frame\fR" 4 +.IX Item "-mtpcs-leaf-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-apcs\-leaf\-frame\fR. +.IP "\fB\-mcallee\-super\-interworking\fR" 4 +.IX Item "-mcallee-super-interworking" +Gives all externally visible functions in the file being compiled an \s-1ARM\s0 +instruction set header which switches to Thumb mode before executing the +rest of the function. This allows these functions to be called from +non-interworking code. This option is not valid in \s-1AAPCS\s0 configurations +because interworking is enabled by default. +.IP "\fB\-mcaller\-super\-interworking\fR" 4 +.IX Item "-mcaller-super-interworking" +Allows calls via function pointers (including virtual functions) to +execute correctly regardless of whether the target code has been +compiled for interworking or not. There is a small overhead in the cost +of executing a function pointer if this option is enabled. This option +is not valid in \s-1AAPCS\s0 configurations because interworking is enabled +by default. +.IP "\fB\-mtp=\fR\fIname\fR" 4 +.IX Item "-mtp=name" +Specify the access model for the thread local storage pointer. The valid +models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR, +\&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly +(supported in the arm6k architecture), and \fBauto\fR, which uses the +best available method for the selected processor. The default setting is +\&\fBauto\fR. +.IP "\fB\-mtls\-dialect=\fR\fIdialect\fR" 4 +.IX Item "-mtls-dialect=dialect" +Specify the dialect to use for accessing thread local storage. Two +\&\fIdialect\fRs are supported\-\-\-\fBgnu\fR and \fBgnu2\fR. The +\&\fBgnu\fR dialect selects the original \s-1GNU\s0 scheme for supporting +local and global dynamic \s-1TLS\s0 models. The \fBgnu2\fR dialect +selects the \s-1GNU\s0 descriptor scheme, which provides better performance +for shared libraries. The \s-1GNU\s0 descriptor scheme is compatible with +the original scheme, but does require new assembler, linker and +library support. Initial and local exec \s-1TLS\s0 models are unaffected by +this option and always use the original scheme. +.IP "\fB\-mword\-relocations\fR" 4 +.IX Item "-mword-relocations" +Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). +This is enabled by default on targets (uClinux, SymbianOS) where the runtime +loader imposes this restriction, and when \fB\-fpic\fR or \fB\-fPIC\fR +is specified. This option conflicts with \fB\-mslow\-flash\-data\fR. +.IP "\fB\-mfix\-cortex\-m3\-ldrd\fR" 4 +.IX Item "-mfix-cortex-m3-ldrd" +Some Cortex\-M3 cores can cause data corruption when \f(CW\*(C`ldrd\*(C'\fR instructions +with overlapping destination and base registers are used. This option avoids +generating these instructions. This option is enabled by default when +\&\fB\-mcpu=cortex\-m3\fR is specified. +.IP "\fB\-munaligned\-access\fR" 4 +.IX Item "-munaligned-access" +.PD 0 +.IP "\fB\-mno\-unaligned\-access\fR" 4 +.IX Item "-mno-unaligned-access" +.PD +Enables (or disables) reading and writing of 16\- and 32\- bit values +from addresses that are not 16\- or 32\- bit aligned. By default +unaligned access is disabled for all pre\-ARMv6, all ARMv6\-M and for +ARMv8\-M Baseline architectures, and enabled for all other +architectures. If unaligned access is not enabled then words in packed +data structures are accessed a byte at a time. +.Sp +The \s-1ARM\s0 attribute \f(CW\*(C`Tag_CPU_unaligned_access\*(C'\fR is set in the +generated object file to either true or false, depending upon the +setting of this option. If unaligned access is enabled then the +preprocessor symbol \f(CW\*(C`_\|_ARM_FEATURE_UNALIGNED\*(C'\fR is also +defined. +.IP "\fB\-mneon\-for\-64bits\fR" 4 +.IX Item "-mneon-for-64bits" +Enables using Neon to handle scalar 64\-bits operations. This is +disabled by default since the cost of moving data from core registers +to Neon is high. +.IP "\fB\-mslow\-flash\-data\fR" 4 +.IX Item "-mslow-flash-data" +Assume loading data from flash is slower than fetching instruction. +Therefore literal load is minimized for better performance. +This option is only supported when compiling for ARMv7 M\-profile and +off by default. It conflicts with \fB\-mword\-relocations\fR. +.IP "\fB\-masm\-syntax\-unified\fR" 4 +.IX Item "-masm-syntax-unified" +Assume inline assembler is using unified asm syntax. The default is +currently off which implies divided syntax. This option has no impact +on Thumb2. However, this may change in future releases of \s-1GCC.\s0 +Divided syntax should be considered deprecated. +.IP "\fB\-mrestrict\-it\fR" 4 +.IX Item "-mrestrict-it" +Restricts generation of \s-1IT\s0 blocks to conform to the rules of ARMv8\-A. +\&\s-1IT\s0 blocks can only contain a single 16\-bit instruction from a select +set of instructions. This option is on by default for ARMv8\-A Thumb mode. +.IP "\fB\-mprint\-tune\-info\fR" 4 +.IX Item "-mprint-tune-info" +Print \s-1CPU\s0 tuning information as comment in assembler file. This is +an option used only for regression testing of the compiler and not +intended for ordinary use in compiling code. This option is disabled +by default. +.IP "\fB\-mverbose\-cost\-dump\fR" 4 +.IX Item "-mverbose-cost-dump" +Enable verbose cost model dumping in the debug dump files. This option is +provided for use in debugging the compiler. +.IP "\fB\-mpure\-code\fR" 4 +.IX Item "-mpure-code" +Do not allow constant data to be placed in code sections. +Additionally, when compiling for \s-1ELF\s0 object format give all text sections the +\&\s-1ELF\s0 processor-specific section attribute \f(CW\*(C`SHF_ARM_PURECODE\*(C'\fR. This option +is only available when generating non-pic code for M\-profile targets. +.IP "\fB\-mcmse\fR" 4 +.IX Item "-mcmse" +Generate secure code as per the \*(L"ARMv8\-M Security Extensions: Requirements on +Development Tools Engineering Specification\*(R", which can be found on +<\fBhttps://developer.arm.com/documentation/ecm0359818/latest/\fR>. +.PP +\fI\s-1AVR\s0 Options\fR +.IX Subsection "AVR Options" +.PP +These options are defined for \s-1AVR\s0 implementations: +.IP "\fB\-mmcu=\fR\fImcu\fR" 4 +.IX Item "-mmcu=mcu" +Specify Atmel \s-1AVR\s0 instruction set architectures (\s-1ISA\s0) or \s-1MCU\s0 type. +.Sp +The default for this option is \fBavr2\fR. +.Sp +\&\s-1GCC\s0 supports the following \s-1AVR\s0 devices and ISAs: +.RS 4 +.ie n .IP """avr2""" 4 +.el .IP "\f(CWavr2\fR" 4 +.IX Item "avr2" +\&\*(L"Classic\*(R" devices with up to 8 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`attiny22\*(C'\fR, \f(CW\*(C`attiny26\*(C'\fR, \f(CW\*(C`at90s2313\*(C'\fR, \f(CW\*(C`at90s2323\*(C'\fR, \f(CW\*(C`at90s2333\*(C'\fR, \f(CW\*(C`at90s2343\*(C'\fR, \f(CW\*(C`at90s4414\*(C'\fR, \f(CW\*(C`at90s4433\*(C'\fR, \f(CW\*(C`at90s4434\*(C'\fR, \f(CW\*(C`at90c8534\*(C'\fR, \f(CW\*(C`at90s8515\*(C'\fR, \f(CW\*(C`at90s8535\*(C'\fR. +.ie n .IP """avr25""" 4 +.el .IP "\f(CWavr25\fR" 4 +.IX Item "avr25" +\&\*(L"Classic\*(R" devices with up to 8 KiB of program memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction. +\&\fImcu\fR = \f(CW\*(C`attiny13\*(C'\fR, \f(CW\*(C`attiny13a\*(C'\fR, \f(CW\*(C`attiny24\*(C'\fR, \f(CW\*(C`attiny24a\*(C'\fR, \f(CW\*(C`attiny25\*(C'\fR, \f(CW\*(C`attiny261\*(C'\fR, \f(CW\*(C`attiny261a\*(C'\fR, \f(CW\*(C`attiny2313\*(C'\fR, \f(CW\*(C`attiny2313a\*(C'\fR, \f(CW\*(C`attiny43u\*(C'\fR, \f(CW\*(C`attiny44\*(C'\fR, \f(CW\*(C`attiny44a\*(C'\fR, \f(CW\*(C`attiny45\*(C'\fR, \f(CW\*(C`attiny48\*(C'\fR, \f(CW\*(C`attiny441\*(C'\fR, \f(CW\*(C`attiny461\*(C'\fR, \f(CW\*(C`attiny461a\*(C'\fR, \f(CW\*(C`attiny4313\*(C'\fR, \f(CW\*(C`attiny84\*(C'\fR, \f(CW\*(C`attiny84a\*(C'\fR, \f(CW\*(C`attiny85\*(C'\fR, \f(CW\*(C`attiny87\*(C'\fR, \f(CW\*(C`attiny88\*(C'\fR, \f(CW\*(C`attiny828\*(C'\fR, \f(CW\*(C`attiny841\*(C'\fR, \f(CW\*(C`attiny861\*(C'\fR, \f(CW\*(C`attiny861a\*(C'\fR, \f(CW\*(C`ata5272\*(C'\fR, \f(CW\*(C`ata6616c\*(C'\fR, \f(CW\*(C`at86rf401\*(C'\fR. +.ie n .IP """avr3""" 4 +.el .IP "\f(CWavr3\fR" 4 +.IX Item "avr3" +\&\*(L"Classic\*(R" devices with 16 KiB up to 64 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`at76c711\*(C'\fR, \f(CW\*(C`at43usb355\*(C'\fR. +.ie n .IP """avr31""" 4 +.el .IP "\f(CWavr31\fR" 4 +.IX Item "avr31" +\&\*(L"Classic\*(R" devices with 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega103\*(C'\fR, \f(CW\*(C`at43usb320\*(C'\fR. +.ie n .IP """avr35""" 4 +.el .IP "\f(CWavr35\fR" 4 +.IX Item "avr35" +\&\*(L"Classic\*(R" devices with 16 KiB up to 64 KiB of program memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction. +\&\fImcu\fR = \f(CW\*(C`attiny167\*(C'\fR, \f(CW\*(C`attiny1634\*(C'\fR, \f(CW\*(C`atmega8u2\*(C'\fR, \f(CW\*(C`atmega16u2\*(C'\fR, \f(CW\*(C`atmega32u2\*(C'\fR, \f(CW\*(C`ata5505\*(C'\fR, \f(CW\*(C`ata6617c\*(C'\fR, \f(CW\*(C`ata664251\*(C'\fR, \f(CW\*(C`at90usb82\*(C'\fR, \f(CW\*(C`at90usb162\*(C'\fR. +.ie n .IP """avr4""" 4 +.el .IP "\f(CWavr4\fR" 4 +.IX Item "avr4" +\&\*(L"Enhanced\*(R" devices with up to 8 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega48\*(C'\fR, \f(CW\*(C`atmega48a\*(C'\fR, \f(CW\*(C`atmega48p\*(C'\fR, \f(CW\*(C`atmega48pa\*(C'\fR, \f(CW\*(C`atmega48pb\*(C'\fR, \f(CW\*(C`atmega8\*(C'\fR, \f(CW\*(C`atmega8a\*(C'\fR, \f(CW\*(C`atmega8hva\*(C'\fR, \f(CW\*(C`atmega88\*(C'\fR, \f(CW\*(C`atmega88a\*(C'\fR, \f(CW\*(C`atmega88p\*(C'\fR, \f(CW\*(C`atmega88pa\*(C'\fR, \f(CW\*(C`atmega88pb\*(C'\fR, \f(CW\*(C`atmega8515\*(C'\fR, \f(CW\*(C`atmega8535\*(C'\fR, \f(CW\*(C`ata6285\*(C'\fR, \f(CW\*(C`ata6286\*(C'\fR, \f(CW\*(C`ata6289\*(C'\fR, \f(CW\*(C`ata6612c\*(C'\fR, \f(CW\*(C`at90pwm1\*(C'\fR, \f(CW\*(C`at90pwm2\*(C'\fR, \f(CW\*(C`at90pwm2b\*(C'\fR, \f(CW\*(C`at90pwm3\*(C'\fR, \f(CW\*(C`at90pwm3b\*(C'\fR, \f(CW\*(C`at90pwm81\*(C'\fR. +.ie n .IP """avr5""" 4 +.el .IP "\f(CWavr5\fR" 4 +.IX Item "avr5" +\&\*(L"Enhanced\*(R" devices with 16 KiB up to 64 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega168pb\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega325pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega328pb\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64hve2\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega644rfr2\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5791\*(C'\fR, \f(CW\*(C`ata6613c\*(C'\fR, \f(CW\*(C`ata6614q\*(C'\fR, \f(CW\*(C`ata5782\*(C'\fR, \f(CW\*(C`ata5831\*(C'\fR, \f(CW\*(C`ata8210\*(C'\fR, \f(CW\*(C`ata8510\*(C'\fR, \f(CW\*(C`ata5702m322\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +.ie n .IP """avr51""" 4 +.el .IP "\f(CWavr51\fR" 4 +.IX Item "avr51" +\&\*(L"Enhanced\*(R" devices with 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega128\*(C'\fR, \f(CW\*(C`atmega128a\*(C'\fR, \f(CW\*(C`atmega128rfa1\*(C'\fR, \f(CW\*(C`atmega128rfr2\*(C'\fR, \f(CW\*(C`atmega1280\*(C'\fR, \f(CW\*(C`atmega1281\*(C'\fR, \f(CW\*(C`atmega1284\*(C'\fR, \f(CW\*(C`atmega1284p\*(C'\fR, \f(CW\*(C`atmega1284rfr2\*(C'\fR, \f(CW\*(C`at90can128\*(C'\fR, \f(CW\*(C`at90usb1286\*(C'\fR, \f(CW\*(C`at90usb1287\*(C'\fR. +.ie n .IP """avr6""" 4 +.el .IP "\f(CWavr6\fR" 4 +.IX Item "avr6" +\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC,\s0 i.e. with more than 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atmega256rfr2\*(C'\fR, \f(CW\*(C`atmega2560\*(C'\fR, \f(CW\*(C`atmega2561\*(C'\fR, \f(CW\*(C`atmega2564rfr2\*(C'\fR. +.ie n .IP """avrxmega2""" 4 +.el .IP "\f(CWavrxmega2\fR" 4 +.IX Item "avrxmega2" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 8 KiB and up to 64 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atxmega8e5\*(C'\fR, \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16a4u\*(C'\fR, \f(CW\*(C`atxmega16c4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR, \f(CW\*(C`atxmega16e5\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32a4u\*(C'\fR, \f(CW\*(C`atxmega32c3\*(C'\fR, \f(CW\*(C`atxmega32c4\*(C'\fR, \f(CW\*(C`atxmega32d3\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR, \f(CW\*(C`atxmega32e5\*(C'\fR. +.ie n .IP """avrxmega3""" 4 +.el .IP "\f(CWavrxmega3\fR" 4 +.IX Item "avrxmega3" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with up to 64 KiB of combined program memory and \s-1RAM,\s0 and with program memory visible in the \s-1RAM\s0 address space. +\&\fImcu\fR = \f(CW\*(C`attiny202\*(C'\fR, \f(CW\*(C`attiny204\*(C'\fR, \f(CW\*(C`attiny212\*(C'\fR, \f(CW\*(C`attiny214\*(C'\fR, \f(CW\*(C`attiny402\*(C'\fR, \f(CW\*(C`attiny404\*(C'\fR, \f(CW\*(C`attiny406\*(C'\fR, \f(CW\*(C`attiny412\*(C'\fR, \f(CW\*(C`attiny414\*(C'\fR, \f(CW\*(C`attiny416\*(C'\fR, \f(CW\*(C`attiny417\*(C'\fR, \f(CW\*(C`attiny804\*(C'\fR, \f(CW\*(C`attiny806\*(C'\fR, \f(CW\*(C`attiny807\*(C'\fR, \f(CW\*(C`attiny814\*(C'\fR, \f(CW\*(C`attiny816\*(C'\fR, \f(CW\*(C`attiny817\*(C'\fR, \f(CW\*(C`attiny1604\*(C'\fR, \f(CW\*(C`attiny1606\*(C'\fR, \f(CW\*(C`attiny1607\*(C'\fR, \f(CW\*(C`attiny1614\*(C'\fR, \f(CW\*(C`attiny1616\*(C'\fR, \f(CW\*(C`attiny1617\*(C'\fR, \f(CW\*(C`attiny3214\*(C'\fR, \f(CW\*(C`attiny3216\*(C'\fR, \f(CW\*(C`attiny3217\*(C'\fR, \f(CW\*(C`atmega808\*(C'\fR, \f(CW\*(C`atmega809\*(C'\fR, \f(CW\*(C`atmega1608\*(C'\fR, \f(CW\*(C`atmega1609\*(C'\fR, \f(CW\*(C`atmega3208\*(C'\fR, \f(CW\*(C`atmega3209\*(C'\fR, \f(CW\*(C`atmega4808\*(C'\fR, \f(CW\*(C`atmega4809\*(C'\fR. +.ie n .IP """avrxmega4""" 4 +.el .IP "\f(CWavrxmega4\fR" 4 +.IX Item "avrxmega4" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64 KiB and up to 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64a3u\*(C'\fR, \f(CW\*(C`atxmega64a4u\*(C'\fR, \f(CW\*(C`atxmega64b1\*(C'\fR, \f(CW\*(C`atxmega64b3\*(C'\fR, \f(CW\*(C`atxmega64c3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR, \f(CW\*(C`atxmega64d4\*(C'\fR. +.ie n .IP """avrxmega5""" 4 +.el .IP "\f(CWavrxmega5\fR" 4 +.IX Item "avrxmega5" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of \s-1RAM.\s0 +\&\fImcu\fR = \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. +.ie n .IP """avrxmega6""" 4 +.el .IP "\f(CWavrxmega6\fR" 4 +.IX Item "avrxmega6" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128a3u\*(C'\fR, \f(CW\*(C`atxmega128b1\*(C'\fR, \f(CW\*(C`atxmega128b3\*(C'\fR, \f(CW\*(C`atxmega128c3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR, \f(CW\*(C`atxmega128d4\*(C'\fR, \f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192a3u\*(C'\fR, \f(CW\*(C`atxmega192c3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR, \f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256a3u\*(C'\fR, \f(CW\*(C`atxmega256c3\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR, \f(CW\*(C`atxmega384c3\*(C'\fR, \f(CW\*(C`atxmega384d3\*(C'\fR. +.ie n .IP """avrxmega7""" 4 +.el .IP "\f(CWavrxmega7\fR" 4 +.IX Item "avrxmega7" +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128 KiB of program memory and more than 64 KiB of \s-1RAM.\s0 +\&\fImcu\fR = \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. +.ie n .IP """avrtiny""" 4 +.el .IP "\f(CWavrtiny\fR" 4 +.IX Item "avrtiny" +\&\*(L"\s-1TINY\*(R"\s0 Tiny core devices with 512 B up to 4 KiB of program memory. +\&\fImcu\fR = \f(CW\*(C`attiny4\*(C'\fR, \f(CW\*(C`attiny5\*(C'\fR, \f(CW\*(C`attiny9\*(C'\fR, \f(CW\*(C`attiny10\*(C'\fR, \f(CW\*(C`attiny20\*(C'\fR, \f(CW\*(C`attiny40\*(C'\fR. +.ie n .IP """avr1""" 4 +.el .IP "\f(CWavr1\fR" 4 +.IX Item "avr1" +This \s-1ISA\s0 is implemented by the minimal \s-1AVR\s0 core and supported for assembler only. +\&\fImcu\fR = \f(CW\*(C`attiny11\*(C'\fR, \f(CW\*(C`attiny12\*(C'\fR, \f(CW\*(C`attiny15\*(C'\fR, \f(CW\*(C`attiny28\*(C'\fR, \f(CW\*(C`at90s1200\*(C'\fR. +.RE +.RS 4 +.RE +.IP "\fB\-mabsdata\fR" 4 +.IX Item "-mabsdata" +Assume that all data in static storage can be accessed by \s-1LDS / STS\s0 +instructions. This option has only an effect on reduced Tiny devices like +ATtiny40. See also the \f(CW\*(C`absdata\*(C'\fR +\&\fB\s-1AVR\s0 Variable Attributes,variable attribute\fR. +.IP "\fB\-maccumulate\-args\fR" 4 +.IX Item "-maccumulate-args" +Accumulate outgoing function arguments and acquire/release the needed +stack space for outgoing function arguments once in function +prologue/epilogue. Without this option, outgoing arguments are pushed +before calling a function and popped afterwards. +.Sp +Popping the arguments after the function call can be expensive on +\&\s-1AVR\s0 so that accumulating the stack space might lead to smaller +executables because arguments need not be removed from the +stack after such a function call. +.Sp +This option can lead to reduced code size for functions that perform +several calls to functions that get their arguments on the stack like +calls to printf-like functions. +.IP "\fB\-mbranch\-cost=\fR\fIcost\fR" 4 +.IX Item "-mbranch-cost=cost" +Set the branch costs for conditional branch instructions to +\&\fIcost\fR. Reasonable values for \fIcost\fR are small, non-negative +integers. The default branch cost is 0. +.IP "\fB\-mcall\-prologues\fR" 4 +.IX Item "-mcall-prologues" +Functions prologues/epilogues are expanded as calls to appropriate +subroutines. Code size is smaller. +.IP "\fB\-mgas\-isr\-prologues\fR" 4 +.IX Item "-mgas-isr-prologues" +Interrupt service routines (ISRs) may use the \f(CW\*(C`_\|_gcc_isr\*(C'\fR pseudo +instruction supported by \s-1GNU\s0 Binutils. +If this option is on, the feature can still be disabled for individual +ISRs by means of the \fB\s-1AVR\s0 Function Attributes,,\f(CB\*(C`no_gccisr\*(C'\fB\fR +function attribute. This feature is activated per default +if optimization is on (but not with \fB\-Og\fR, \f(CW@pxref\fR{Optimize Options}), +and if \s-1GNU\s0 Binutils support \s-1PR21683\s0 (\f(CW\*(C`https://sourceware.org/PR21683\*(C'\fR). +.IP "\fB\-mint8\fR" 4 +.IX Item "-mint8" +Assume \f(CW\*(C`int\*(C'\fR to be 8\-bit integer. This affects the sizes of all types: a +\&\f(CW\*(C`char\*(C'\fR is 1 byte, an \f(CW\*(C`int\*(C'\fR is 1 byte, a \f(CW\*(C`long\*(C'\fR is 2 bytes, +and \f(CW\*(C`long long\*(C'\fR is 4 bytes. Please note that this option does not +conform to the C standards, but it results in smaller code +size. +.IP "\fB\-mmain\-is\-OS_task\fR" 4 +.IX Item "-mmain-is-OS_task" +Do not save registers in \f(CW\*(C`main\*(C'\fR. The effect is the same like +attaching attribute \fB\s-1AVR\s0 Function Attributes,,\f(CB\*(C`OS_task\*(C'\fB\fR +to \f(CW\*(C`main\*(C'\fR. It is activated per default if optimization is on. +.IP "\fB\-mn\-flash=\fR\fInum\fR" 4 +.IX Item "-mn-flash=num" +Assume that the flash memory has a size of +\&\fInum\fR times 64 KiB. +.IP "\fB\-mno\-interrupts\fR" 4 +.IX Item "-mno-interrupts" +Generated code is not compatible with hardware interrupts. +Code size is smaller. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Try to replace \f(CW\*(C`CALL\*(C'\fR resp. \f(CW\*(C`JMP\*(C'\fR instruction by the shorter +\&\f(CW\*(C`RCALL\*(C'\fR resp. \f(CW\*(C`RJMP\*(C'\fR instruction if applicable. +Setting \fB\-mrelax\fR just adds the \fB\-\-mlink\-relax\fR option to +the assembler's command line and the \fB\-\-relax\fR option to the +linker's command line. +.Sp +Jump relaxing is performed by the linker because jump offsets are not +known before code is located. Therefore, the assembler code generated by the +compiler is the same, but the instructions in the executable may +differ from instructions in the assembler code. +.Sp +Relaxing must be turned on if linker stubs are needed, see the +section on \f(CW\*(C`EIND\*(C'\fR and linker stubs below. +.IP "\fB\-mrmw\fR" 4 +.IX Item "-mrmw" +Assume that the device supports the Read-Modify-Write +instructions \f(CW\*(C`XCH\*(C'\fR, \f(CW\*(C`LAC\*(C'\fR, \f(CW\*(C`LAS\*(C'\fR and \f(CW\*(C`LAT\*(C'\fR. +.IP "\fB\-mshort\-calls\fR" 4 +.IX Item "-mshort-calls" +Assume that \f(CW\*(C`RJMP\*(C'\fR and \f(CW\*(C`RCALL\*(C'\fR can target the whole +program memory. +.Sp +This option is used internally for multilib selection. It is +not an optimization option, and you don't need to set it by hand. +.IP "\fB\-msp8\fR" 4 +.IX Item "-msp8" +Treat the stack pointer register as an 8\-bit register, +i.e. assume the high byte of the stack pointer is zero. +In general, you don't need to set this option by hand. +.Sp +This option is used internally by the compiler to select and +build multilibs for architectures \f(CW\*(C`avr2\*(C'\fR and \f(CW\*(C`avr25\*(C'\fR. +These architectures mix devices with and without \f(CW\*(C`SPH\*(C'\fR. +For any setting other than \fB\-mmcu=avr2\fR or \fB\-mmcu=avr25\fR +the compiler driver adds or removes this option from the compiler +proper's command line, because the compiler then knows if the device +or architecture has an 8\-bit stack pointer and thus no \f(CW\*(C`SPH\*(C'\fR +register or not. +.IP "\fB\-mstrict\-X\fR" 4 +.IX Item "-mstrict-X" +Use address register \f(CW\*(C`X\*(C'\fR in a way proposed by the hardware. This means +that \f(CW\*(C`X\*(C'\fR is only used in indirect, post-increment or +pre-decrement addressing. +.Sp +Without this option, the \f(CW\*(C`X\*(C'\fR register may be used in the same way +as \f(CW\*(C`Y\*(C'\fR or \f(CW\*(C`Z\*(C'\fR which then is emulated by additional +instructions. +For example, loading a value with \f(CW\*(C`X+const\*(C'\fR addressing with a +small non-negative \f(CW\*(C`const < 64\*(C'\fR to a register \fIRn\fR is +performed as +.Sp +.Vb 3 +\& adiw r26, const ; X += const +\& ld , X ; = *X +\& sbiw r26, const ; X \-= const +.Ve +.IP "\fB\-mtiny\-stack\fR" 4 +.IX Item "-mtiny-stack" +Only change the lower 8 bits of the stack pointer. +.IP "\fB\-mfract\-convert\-truncate\fR" 4 +.IX Item "-mfract-convert-truncate" +Allow to use truncation instead of rounding towards zero for fractional fixed-point types. +.IP "\fB\-nodevicelib\fR" 4 +.IX Item "-nodevicelib" +Don't link against AVR-LibC's device specific library \f(CW\*(C`lib.a\*(C'\fR. +.IP "\fB\-nodevicespecs\fR" 4 +.IX Item "-nodevicespecs" +Don't add \fB\-specs=device\-specs/specs\-\fR to the compiler driver's +command line. The user takes responsibility for supplying the sub-processes +like compiler proper, assembler and linker with appropriate command line +options. +.IP "\fB\-Waddr\-space\-convert\fR" 4 +.IX Item "-Waddr-space-convert" +Warn about conversions between address spaces in the case where the +resulting address space is not contained in the incoming address space. +.IP "\fB\-Wmisspelled\-isr\fR" 4 +.IX Item "-Wmisspelled-isr" +Warn if the \s-1ISR\s0 is misspelled, i.e. without _\|_vector prefix. +Enabled by default. +.PP +\f(CW\*(C`EIND\*(C'\fR and Devices with More Than 128 Ki Bytes of Flash +.IX Subsection "EIND and Devices with More Than 128 Ki Bytes of Flash" +.PP +Pointers in the implementation are 16 bits wide. +The address of a function or label is represented as word address so +that indirect jumps and calls can target any code address in the +range of 64 Ki words. +.PP +In order to facilitate indirect jump on devices with more than 128 Ki +bytes of program memory space, there is a special function register called +\&\f(CW\*(C`EIND\*(C'\fR that serves as most significant part of the target address +when \f(CW\*(C`EICALL\*(C'\fR or \f(CW\*(C`EIJMP\*(C'\fR instructions are used. +.PP +Indirect jumps and calls on these devices are handled as follows by +the compiler and are subject to some limitations: +.IP "*" 4 +The compiler never sets \f(CW\*(C`EIND\*(C'\fR. +.IP "*" 4 +The compiler uses \f(CW\*(C`EIND\*(C'\fR implicitly in \f(CW\*(C`EICALL\*(C'\fR/\f(CW\*(C`EIJMP\*(C'\fR +instructions or might read \f(CW\*(C`EIND\*(C'\fR directly in order to emulate an +indirect call/jump by means of a \f(CW\*(C`RET\*(C'\fR instruction. +.IP "*" 4 +The compiler assumes that \f(CW\*(C`EIND\*(C'\fR never changes during the startup +code or during the application. In particular, \f(CW\*(C`EIND\*(C'\fR is not +saved/restored in function or interrupt service routine +prologue/epilogue. +.IP "*" 4 +For indirect calls to functions and computed goto, the linker +generates \fIstubs\fR. Stubs are jump pads sometimes also called +\&\fItrampolines\fR. Thus, the indirect call/jump jumps to such a stub. +The stub contains a direct jump to the desired address. +.IP "*" 4 +Linker relaxation must be turned on so that the linker generates +the stubs correctly in all situations. See the compiler option +\&\fB\-mrelax\fR and the linker option \fB\-\-relax\fR. +There are corner cases where the linker is supposed to generate stubs +but aborts without relaxation and without a helpful error message. +.IP "*" 4 +The default linker script is arranged for code with \f(CW\*(C`EIND = 0\*(C'\fR. +If code is supposed to work for a setup with \f(CW\*(C`EIND != 0\*(C'\fR, a custom +linker script has to be used in order to place the sections whose +name start with \f(CW\*(C`.trampolines\*(C'\fR into the segment where \f(CW\*(C`EIND\*(C'\fR +points to. +.IP "*" 4 +The startup code from libgcc never sets \f(CW\*(C`EIND\*(C'\fR. +Notice that startup code is a blend of code from libgcc and AVR-LibC. +For the impact of AVR-LibC on \f(CW\*(C`EIND\*(C'\fR, see the +AVR-LibC\ user\ manual (\f(CW\*(C`http://nongnu.org/avr\-libc/user\-manual/\*(C'\fR). +.IP "*" 4 +It is legitimate for user-specific startup code to set up \f(CW\*(C`EIND\*(C'\fR +early, for example by means of initialization code located in +section \f(CW\*(C`.init3\*(C'\fR. Such code runs prior to general startup code +that initializes \s-1RAM\s0 and calls constructors, but after the bit +of startup code from AVR-LibC that sets \f(CW\*(C`EIND\*(C'\fR to the segment +where the vector table is located. +.Sp +.Vb 1 +\& #include +\& +\& static void +\& _\|_attribute_\|_((section(".init3"),naked,used,no_instrument_function)) +\& init3_set_eind (void) +\& { +\& _\|_asm volatile ("ldi r24,pm_hh8(_\|_trampolines_start)\en\et" +\& "out %i0,r24" :: "n" (&EIND) : "r24","memory"); +\& } +.Ve +.Sp +The \f(CW\*(C`_\|_trampolines_start\*(C'\fR symbol is defined in the linker script. +.IP "*" 4 +Stubs are generated automatically by the linker if +the following two conditions are met: +.RS 4 +.ie n .IP "\-" 4 +.el .IP "\-" 4 +.IX Item "-" +(short for \fIgenerate stubs\fR) like so: +.Sp +.Vb 2 +\& LDI r24, lo8(gs()) +\& LDI r25, hi8(gs()) +.Ve +.IP "\-" 4 +.IX Item "-" +\&\fIoutside\fR the segment where the stubs are located. +.RE +.RS 4 +.RE +.IP "*" 4 +The compiler emits such \f(CW\*(C`gs\*(C'\fR modifiers for code labels in the +following situations: +.RS 4 +.IP "\-" 4 +.IX Item "-" +.PD 0 +.IP "\-" 4 +.IX Item "-" +.IP "\-" 4 +.IX Item "-" +.PD +command-line option. +.IP "\-" 4 +.IX Item "-" +tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. +.IP "\-" 4 +.IX Item "-" +.PD 0 +.ie n .IP "\-" 4 +.el .IP "\-" 4 +.IX Item "-" +.RE +.RS 4 +.RE +.IP "*" 4 +.PD +Jumping to non-symbolic addresses like so is \fInot\fR supported: +.Sp +.Vb 5 +\& int main (void) +\& { +\& /* Call function at word address 0x2 */ +\& return ((int(*)(void)) 0x2)(); +\& } +.Ve +.Sp +Instead, a stub has to be set up, i.e. the function has to be called +through a symbol (\f(CW\*(C`func_4\*(C'\fR in the example): +.Sp +.Vb 3 +\& int main (void) +\& { +\& extern int func_4 (void); +\& +\& /* Call function at byte address 0x4 */ +\& return func_4(); +\& } +.Ve +.Sp +and the application be linked with \fB\-Wl,\-\-defsym,func_4=0x4\fR. +Alternatively, \f(CW\*(C`func_4\*(C'\fR can be defined in the linker script. +.PP +Handling of the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR and \f(CW\*(C`RAMPZ\*(C'\fR Special Function Registers +.IX Subsection "Handling of the RAMPD, RAMPX, RAMPY and RAMPZ Special Function Registers" +.PP +Some \s-1AVR\s0 devices support memories larger than the 64 KiB range +that can be accessed with 16\-bit pointers. To access memory locations +outside this 64 KiB range, the content of a \f(CW\*(C`RAMP\*(C'\fR +register is used as high part of the address: +The \f(CW\*(C`X\*(C'\fR, \f(CW\*(C`Y\*(C'\fR, \f(CW\*(C`Z\*(C'\fR address register is concatenated +with the \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR, \f(CW\*(C`RAMPZ\*(C'\fR special function +register, respectively, to get a wide address. Similarly, +\&\f(CW\*(C`RAMPD\*(C'\fR is used together with direct addressing. +.IP "*" 4 +The startup code initializes the \f(CW\*(C`RAMP\*(C'\fR special function +registers with zero. +.IP "*" 4 +If a \fB\s-1AVR\s0 Named Address Spaces,named address space\fR other than +generic or \f(CW\*(C`_\|_flash\*(C'\fR is used, then \f(CW\*(C`RAMPZ\*(C'\fR is set +as needed before the operation. +.IP "*" 4 +If the device supports \s-1RAM\s0 larger than 64 KiB and the compiler +needs to change \f(CW\*(C`RAMPZ\*(C'\fR to accomplish an operation, \f(CW\*(C`RAMPZ\*(C'\fR +is reset to zero after the operation. +.IP "*" 4 +If the device comes with a specific \f(CW\*(C`RAMP\*(C'\fR register, the \s-1ISR\s0 +prologue/epilogue saves/restores that \s-1SFR\s0 and initializes it with +zero in case the \s-1ISR\s0 code might (implicitly) use it. +.IP "*" 4 +\&\s-1RAM\s0 larger than 64 KiB is not supported by \s-1GCC\s0 for \s-1AVR\s0 targets. +If you use inline assembler to read from locations outside the +16\-bit address range and change one of the \f(CW\*(C`RAMP\*(C'\fR registers, +you must reset it to zero after the access. +.PP +\s-1AVR\s0 Built-in Macros +.IX Subsection "AVR Built-in Macros" +.PP +\&\s-1GCC\s0 defines several built-in macros so that the user code can test +for the presence or absence of features. Almost any of the following +built-in macros are deduced from device capabilities and thus +triggered by the \fB\-mmcu=\fR command-line option. +.PP +For even more AVR-specific built-in macros see +\&\fB\s-1AVR\s0 Named Address Spaces\fR and \fB\s-1AVR\s0 Built-in Functions\fR. +.ie n .IP """_\|_AVR_ARCH_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ARCH_\|_\fR" 4 +.IX Item "__AVR_ARCH__" +Build-in macro that resolves to a decimal number that identifies the +architecture and depends on the \fB\-mmcu=\fR\fImcu\fR option. +Possible values are: +.Sp +\&\f(CW2\fR, \f(CW25\fR, \f(CW3\fR, \f(CW31\fR, \f(CW35\fR, +\&\f(CW4\fR, \f(CW5\fR, \f(CW51\fR, \f(CW6\fR +.Sp +for \fImcu\fR=\f(CW\*(C`avr2\*(C'\fR, \f(CW\*(C`avr25\*(C'\fR, \f(CW\*(C`avr3\*(C'\fR, \f(CW\*(C`avr31\*(C'\fR, +\&\f(CW\*(C`avr35\*(C'\fR, \f(CW\*(C`avr4\*(C'\fR, \f(CW\*(C`avr5\*(C'\fR, \f(CW\*(C`avr51\*(C'\fR, \f(CW\*(C`avr6\*(C'\fR, +.Sp +respectively and +.Sp +\&\f(CW100\fR, +\&\f(CW102\fR, \f(CW103\fR, \f(CW104\fR, +\&\f(CW105\fR, \f(CW106\fR, \f(CW107\fR +.Sp +for \fImcu\fR=\f(CW\*(C`avrtiny\*(C'\fR, +\&\f(CW\*(C`avrxmega2\*(C'\fR, \f(CW\*(C`avrxmega3\*(C'\fR, \f(CW\*(C`avrxmega4\*(C'\fR, +\&\f(CW\*(C`avrxmega5\*(C'\fR, \f(CW\*(C`avrxmega6\*(C'\fR, \f(CW\*(C`avrxmega7\*(C'\fR, respectively. +If \fImcu\fR specifies a device, this built-in macro is set +accordingly. For example, with \fB\-mmcu=atmega8\fR the macro is +defined to \f(CW4\fR. +.ie n .IP """_\|_AVR_\fIDevice\fP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_\f(CIDevice\f(CW_\|_\fR" 4 +.IX Item "__AVR_Device__" +Setting \fB\-mmcu=\fR\fIdevice\fR defines this built-in macro which reflects +the device's name. For example, \fB\-mmcu=atmega8\fR defines the +built-in macro \f(CW\*(C`_\|_AVR_ATmega8_\|_\*(C'\fR, \fB\-mmcu=attiny261a\fR defines +\&\f(CW\*(C`_\|_AVR_ATtiny261A_\|_\*(C'\fR, etc. +.Sp +The built-in macros' names follow +the scheme \f(CW\*(C`_\|_AVR_\f(CIDevice\f(CW_\|_\*(C'\fR where \fIDevice\fR is +the device name as from the \s-1AVR\s0 user manual. The difference between +\&\fIDevice\fR in the built-in macro and \fIdevice\fR in +\&\fB\-mmcu=\fR\fIdevice\fR is that the latter is always lowercase. +.Sp +If \fIdevice\fR is not a device but only a core architecture like +\&\fBavr51\fR, this macro is not defined. +.ie n .IP """_\|_AVR_DEVICE_NAME_\|_""" 4 +.el .IP "\f(CW_\|_AVR_DEVICE_NAME_\|_\fR" 4 +.IX Item "__AVR_DEVICE_NAME__" +Setting \fB\-mmcu=\fR\fIdevice\fR defines this built-in macro to +the device's name. For example, with \fB\-mmcu=atmega8\fR the macro +is defined to \f(CW\*(C`atmega8\*(C'\fR. +.Sp +If \fIdevice\fR is not a device but only a core architecture like +\&\fBavr51\fR, this macro is not defined. +.ie n .IP """_\|_AVR_XMEGA_\|_""" 4 +.el .IP "\f(CW_\|_AVR_XMEGA_\|_\fR" 4 +.IX Item "__AVR_XMEGA__" +The device / architecture belongs to the \s-1XMEGA\s0 family of devices. +.ie n .IP """_\|_AVR_HAVE_ELPM_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_ELPM_\|_\fR" 4 +.IX Item "__AVR_HAVE_ELPM__" +The device has the \f(CW\*(C`ELPM\*(C'\fR instruction. +.ie n .IP """_\|_AVR_HAVE_ELPMX_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_ELPMX_\|_\fR" 4 +.IX Item "__AVR_HAVE_ELPMX__" +The device has the \f(CW\*(C`ELPM R\f(CIn\f(CW,Z\*(C'\fR and \f(CW\*(C`ELPM +R\f(CIn\f(CW,Z+\*(C'\fR instructions. +.ie n .IP """_\|_AVR_HAVE_MOVW_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_MOVW_\|_\fR" 4 +.IX Item "__AVR_HAVE_MOVW__" +The device has the \f(CW\*(C`MOVW\*(C'\fR instruction to perform 16\-bit +register-register moves. +.ie n .IP """_\|_AVR_HAVE_LPMX_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_LPMX_\|_\fR" 4 +.IX Item "__AVR_HAVE_LPMX__" +The device has the \f(CW\*(C`LPM R\f(CIn\f(CW,Z\*(C'\fR and +\&\f(CW\*(C`LPM R\f(CIn\f(CW,Z+\*(C'\fR instructions. +.ie n .IP """_\|_AVR_HAVE_MUL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_MUL_\|_\fR" 4 +.IX Item "__AVR_HAVE_MUL__" +The device has a hardware multiplier. +.ie n .IP """_\|_AVR_HAVE_JMP_CALL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_JMP_CALL_\|_\fR" 4 +.IX Item "__AVR_HAVE_JMP_CALL__" +The device has the \f(CW\*(C`JMP\*(C'\fR and \f(CW\*(C`CALL\*(C'\fR instructions. +This is the case for devices with more than 8 KiB of program +memory. +.ie n .IP """_\|_AVR_HAVE_EIJMP_EICALL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_EIJMP_EICALL_\|_\fR" 4 +.IX Item "__AVR_HAVE_EIJMP_EICALL__" +.PD 0 +.ie n .IP """_\|_AVR_3_BYTE_PC_\|_""" 4 +.el .IP "\f(CW_\|_AVR_3_BYTE_PC_\|_\fR" 4 +.IX Item "__AVR_3_BYTE_PC__" +.PD +The device has the \f(CW\*(C`EIJMP\*(C'\fR and \f(CW\*(C`EICALL\*(C'\fR instructions. +This is the case for devices with more than 128 KiB of program memory. +This also means that the program counter +(\s-1PC\s0) is 3 bytes wide. +.ie n .IP """_\|_AVR_2_BYTE_PC_\|_""" 4 +.el .IP "\f(CW_\|_AVR_2_BYTE_PC_\|_\fR" 4 +.IX Item "__AVR_2_BYTE_PC__" +The program counter (\s-1PC\s0) is 2 bytes wide. This is the case for devices +with up to 128 KiB of program memory. +.ie n .IP """_\|_AVR_HAVE_8BIT_SP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_8BIT_SP_\|_\fR" 4 +.IX Item "__AVR_HAVE_8BIT_SP__" +.PD 0 +.ie n .IP """_\|_AVR_HAVE_16BIT_SP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_16BIT_SP_\|_\fR" 4 +.IX Item "__AVR_HAVE_16BIT_SP__" +.PD +The stack pointer (\s-1SP\s0) register is treated as 8\-bit respectively +16\-bit register by the compiler. +The definition of these macros is affected by \fB\-mtiny\-stack\fR. +.ie n .IP """_\|_AVR_HAVE_SPH_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_SPH_\|_\fR" 4 +.IX Item "__AVR_HAVE_SPH__" +.PD 0 +.ie n .IP """_\|_AVR_SP8_\|_""" 4 +.el .IP "\f(CW_\|_AVR_SP8_\|_\fR" 4 +.IX Item "__AVR_SP8__" +.PD +The device has the \s-1SPH\s0 (high part of stack pointer) special function +register or has an 8\-bit stack pointer, respectively. +The definition of these macros is affected by \fB\-mmcu=\fR and +in the cases of \fB\-mmcu=avr2\fR and \fB\-mmcu=avr25\fR also +by \fB\-msp8\fR. +.ie n .IP """_\|_AVR_HAVE_RAMPD_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPD_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPD__" +.PD 0 +.ie n .IP """_\|_AVR_HAVE_RAMPX_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPX_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPX__" +.ie n .IP """_\|_AVR_HAVE_RAMPY_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPY_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPY__" +.ie n .IP """_\|_AVR_HAVE_RAMPZ_\|_""" 4 +.el .IP "\f(CW_\|_AVR_HAVE_RAMPZ_\|_\fR" 4 +.IX Item "__AVR_HAVE_RAMPZ__" +.PD +The device has the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR, +\&\f(CW\*(C`RAMPZ\*(C'\fR special function register, respectively. +.ie n .IP """_\|_NO_INTERRUPTS_\|_""" 4 +.el .IP "\f(CW_\|_NO_INTERRUPTS_\|_\fR" 4 +.IX Item "__NO_INTERRUPTS__" +This macro reflects the \fB\-mno\-interrupts\fR command-line option. +.ie n .IP """_\|_AVR_ERRATA_SKIP_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ERRATA_SKIP_\|_\fR" 4 +.IX Item "__AVR_ERRATA_SKIP__" +.PD 0 +.ie n .IP """_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_\fR" 4 +.IX Item "__AVR_ERRATA_SKIP_JMP_CALL__" +.PD +Some \s-1AVR\s0 devices (\s-1AT90S8515,\s0 ATmega103) must not skip 32\-bit +instructions because of a hardware erratum. Skip instructions are +\&\f(CW\*(C`SBRS\*(C'\fR, \f(CW\*(C`SBRC\*(C'\fR, \f(CW\*(C`SBIS\*(C'\fR, \f(CW\*(C`SBIC\*(C'\fR and \f(CW\*(C`CPSE\*(C'\fR. +The second macro is only defined if \f(CW\*(C`_\|_AVR_HAVE_JMP_CALL_\|_\*(C'\fR is also +set. +.ie n .IP """_\|_AVR_ISA_RMW_\|_""" 4 +.el .IP "\f(CW_\|_AVR_ISA_RMW_\|_\fR" 4 +.IX Item "__AVR_ISA_RMW__" +The device has Read-Modify-Write instructions (\s-1XCH, LAC, LAS\s0 and \s-1LAT\s0). +.ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\fIoffset\fP""" 4 +.el .IP "\f(CW_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW\fR" 4 +.IX Item "__AVR_SFR_OFFSET__=offset" +Instructions that can address I/O special function registers directly +like \f(CW\*(C`IN\*(C'\fR, \f(CW\*(C`OUT\*(C'\fR, \f(CW\*(C`SBI\*(C'\fR, etc. may use a different +address as if addressed by an instruction to access \s-1RAM\s0 like \f(CW\*(C`LD\*(C'\fR +or \f(CW\*(C`STS\*(C'\fR. This offset depends on the device architecture and has +to be subtracted from the \s-1RAM\s0 address in order to get the +respective I/O address. +.ie n .IP """_\|_AVR_SHORT_CALLS_\|_""" 4 +.el .IP "\f(CW_\|_AVR_SHORT_CALLS_\|_\fR" 4 +.IX Item "__AVR_SHORT_CALLS__" +The \fB\-mshort\-calls\fR command line option is set. +.ie n .IP """_\|_AVR_PM_BASE_ADDRESS_\|_=\fIaddr\fP""" 4 +.el .IP "\f(CW_\|_AVR_PM_BASE_ADDRESS_\|_=\f(CIaddr\f(CW\fR" 4 +.IX Item "__AVR_PM_BASE_ADDRESS__=addr" +Some devices support reading from flash memory by means of \f(CW\*(C`LD*\*(C'\fR +instructions. The flash memory is seen in the data address space +at an offset of \f(CW\*(C`_\|_AVR_PM_BASE_ADDRESS_\|_\*(C'\fR. If this macro +is not defined, this feature is not available. If defined, +the address space is linear and there is no need to put +\&\f(CW\*(C`.rodata\*(C'\fR into \s-1RAM.\s0 This is handled by the default linker +description file, and is currently available for +\&\f(CW\*(C`avrtiny\*(C'\fR and \f(CW\*(C`avrxmega3\*(C'\fR. Even more convenient, +there is no need to use address spaces like \f(CW\*(C`_\|_flash\*(C'\fR or +features like attribute \f(CW\*(C`progmem\*(C'\fR and \f(CW\*(C`pgm_read_*\*(C'\fR. +.ie n .IP """_\|_WITH_AVRLIBC_\|_""" 4 +.el .IP "\f(CW_\|_WITH_AVRLIBC_\|_\fR" 4 +.IX Item "__WITH_AVRLIBC__" +The compiler is configured to be used together with AVR-Libc. +See the \fB\-\-with\-avrlibc\fR configure option. +.PP +\fIBlackfin Options\fR +.IX Subsection "Blackfin Options" +.IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4 +.IX Item "-mcpu=cpu[-sirevision]" +Specifies the name of the target Blackfin processor. Currently, \fIcpu\fR +can be one of \fBbf512\fR, \fBbf514\fR, \fBbf516\fR, \fBbf518\fR, +\&\fBbf522\fR, \fBbf523\fR, \fBbf524\fR, \fBbf525\fR, \fBbf526\fR, +\&\fBbf527\fR, \fBbf531\fR, \fBbf532\fR, \fBbf533\fR, +\&\fBbf534\fR, \fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR, +\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR, +\&\fBbf542m\fR, \fBbf544m\fR, \fBbf547m\fR, \fBbf548m\fR, \fBbf549m\fR, +\&\fBbf561\fR, \fBbf592\fR. +.Sp +The optional \fIsirevision\fR specifies the silicon revision of the target +Blackfin processor. Any workarounds available for the targeted silicon revision +are enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled. +If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor +are enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two +hexadecimal digits representing the major and minor numbers in the silicon +revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR +is not defined. If \fIsirevision\fR is \fBany\fR, the +\&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR. +If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known +silicon revision of the targeted Blackfin processor. +.Sp +\&\s-1GCC\s0 defines a preprocessor macro for the specified \fIcpu\fR. +For the \fBbfin-elf\fR toolchain, this option causes the hardware \s-1BSP\s0 +provided by libgloss to be linked in if \fB\-msim\fR is not given. +.Sp +Without this option, \fBbf532\fR is used as the processor by default. +.Sp +Note that support for \fBbf561\fR is incomplete. For \fBbf561\fR, +only the preprocessor macro is defined. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +the simulator \s-1BSP\s0 provided by libgloss to be linked in. This option +has effect only for \fBbfin-elf\fR toolchain. +Certain other options, such as \fB\-mid\-shared\-library\fR and +\&\fB\-mfdpic\fR, imply \fB\-msim\fR. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up and restore frame pointers and +makes an extra register available in leaf functions. +.IP "\fB\-mspecld\-anomaly\fR" 4 +.IX Item "-mspecld-anomaly" +When enabled, the compiler ensures that the generated code does not +contain speculative loads after jump instructions. If this option is used, +\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined. +.IP "\fB\-mno\-specld\-anomaly\fR" 4 +.IX Item "-mno-specld-anomaly" +Don't generate extra code to prevent speculative loads from occurring. +.IP "\fB\-mcsync\-anomaly\fR" 4 +.IX Item "-mcsync-anomaly" +When enabled, the compiler ensures that the generated code does not +contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches. +If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined. +.IP "\fB\-mno\-csync\-anomaly\fR" 4 +.IX Item "-mno-csync-anomaly" +Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from +occurring too soon after a conditional branch. +.IP "\fB\-mlow64k\fR" 4 +.IX Item "-mlow64k" +When enabled, the compiler is free to take advantage of the knowledge that +the entire program fits into the low 64k of memory. +.IP "\fB\-mno\-low64k\fR" 4 +.IX Item "-mno-low64k" +Assume that the program is arbitrarily large. This is the default. +.IP "\fB\-mstack\-check\-l1\fR" 4 +.IX Item "-mstack-check-l1" +Do stack checking using information placed into L1 scratchpad memory by the +uClinux kernel. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute in place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume ID-based shared libraries are being used. +This is the default. +.IP "\fB\-mleaf\-id\-shared\-library\fR" 4 +.IX Item "-mleaf-id-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method, +but assumes that this library or executable won't link against any other +\&\s-1ID\s0 shared libraries. That allows the compiler to use faster code for jumps +and calls. +.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4 +.IX Item "-mno-leaf-id-shared-library" +Do not assume that the code being compiled won't link against any \s-1ID\s0 shared +libraries. Slower code is generated for jump and call insns. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specifies the identification number of the ID-based shared library being +compiled. Specifying a value of 0 generates more compact code; specifying +other values forces the allocation of that number to the current +library but is no more space\- or time-efficient than omitting this option. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute in place in +an environment without virtual memory management by eliminating relocations +against the text section. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +lies outside of the 24\-bit addressing range of the offset-based +version of subroutine call instruction. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR restores the default behavior. Note these +switches have no effect on how the compiler generates code to handle +function calls via function pointers. +.IP "\fB\-mfast\-fp\fR" 4 +.IX Item "-mfast-fp" +Link with the fast floating-point library. This library relaxes some of +the \s-1IEEE\s0 floating-point standard's rules for checking inputs against +Not-a-Number (\s-1NAN\s0), in the interest of performance. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +.IP "\fB\-mmulticore\fR" 4 +.IX Item "-mmulticore" +Build a standalone application for multicore Blackfin processors. +This option causes proper start files and link scripts supporting +multicore to be used, and defines the macro \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. +It can only be used with \fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. +.Sp +This option can be used with \fB\-mcorea\fR or \fB\-mcoreb\fR, which +selects the one-application-per-core programming model. Without +\&\fB\-mcorea\fR or \fB\-mcoreb\fR, the single\-application/dual\-core +programming model is used. In this model, the main function of Core B +should be named as \f(CW\*(C`coreb_main\*(C'\fR. +.Sp +If this option is not used, the single-core application programming +model is used. +.IP "\fB\-mcorea\fR" 4 +.IX Item "-mcorea" +Build a standalone application for Core A of \s-1BF561\s0 when using +the one-application-per-core programming model. Proper start files +and link scripts are used to support Core A, and the macro +\&\f(CW\*(C`_\|_BFIN_COREA\*(C'\fR is defined. +This option can only be used in conjunction with \fB\-mmulticore\fR. +.IP "\fB\-mcoreb\fR" 4 +.IX Item "-mcoreb" +Build a standalone application for Core B of \s-1BF561\s0 when using +the one-application-per-core programming model. Proper start files +and link scripts are used to support Core B, and the macro +\&\f(CW\*(C`_\|_BFIN_COREB\*(C'\fR is defined. When this option is used, \f(CW\*(C`coreb_main\*(C'\fR +should be used instead of \f(CW\*(C`main\*(C'\fR. +This option can only be used in conjunction with \fB\-mmulticore\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Build a standalone application for \s-1SDRAM.\s0 Proper start files and +link scripts are used to put the application into \s-1SDRAM,\s0 and the macro +\&\f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR is defined. +The loader should initialize \s-1SDRAM\s0 before loading the application. +.IP "\fB\-micplb\fR" 4 +.IX Item "-micplb" +Assume that ICPLBs are enabled at run time. This has an effect on certain +anomaly workarounds. For Linux targets, the default is to assume ICPLBs +are enabled; for standalone applications the default is off. +.PP +\fIC6X Options\fR +.IX Subsection "C6X Options" +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. Permissible names are: \fBc62x\fR, +\&\fBc64x\fR, \fBc64x+\fR, \fBc67x\fR, \fBc67x+\fR, \fBc674x\fR. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. This is the default. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Choose startup files and linker script suitable for the simulator. +.IP "\fB\-msdata=default\fR" 4 +.IX Item "-msdata=default" +Put small global and static data in the \f(CW\*(C`.neardata\*(C'\fR section, +which is pointed to by register \f(CW\*(C`B14\*(C'\fR. Put small uninitialized +global and static data in the \f(CW\*(C`.bss\*(C'\fR section, which is adjacent +to the \f(CW\*(C`.neardata\*(C'\fR section. Put small read-only data into the +\&\f(CW\*(C`.rodata\*(C'\fR section. The corresponding sections used for large +pieces of data are \f(CW\*(C`.fardata\*(C'\fR, \f(CW\*(C`.far\*(C'\fR and \f(CW\*(C`.const\*(C'\fR. +.IP "\fB\-msdata=all\fR" 4 +.IX Item "-msdata=all" +Put all data, not just small objects, into the sections reserved for +small data, and use addressing relative to the \f(CW\*(C`B14\*(C'\fR register to +access them. +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +Make no use of the sections reserved for small data, and use absolute +addresses to access all data. Put all initialized global and static +data in the \f(CW\*(C`.fardata\*(C'\fR section, and all uninitialized data in the +\&\f(CW\*(C`.far\*(C'\fR section. Put all constant data into the \f(CW\*(C`.const\*(C'\fR +section. +.PP +\fI\s-1CRIS\s0 Options\fR +.IX Subsection "CRIS Options" +.PP +These options are defined specifically for the \s-1CRIS\s0 ports. +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +.PD 0 +.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mcpu=architecture-type" +.PD +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for +respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX.\s0 +Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is +\&\fBv10\fR. +.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mtune=architecture-type" +Tune to \fIarchitecture-type\fR everything applicable about the generated +code, except for the \s-1ABI\s0 and the set of available instructions. The +choices for \fIarchitecture-type\fR are the same as for +\&\fB\-march=\fR\fIarchitecture-type\fR. +.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4 +.IX Item "-mmax-stack-frame=n" +Warn when the stack frame of a function exceeds \fIn\fR bytes. +.IP "\fB\-metrax4\fR" 4 +.IX Item "-metrax4" +.PD 0 +.IP "\fB\-metrax100\fR" 4 +.IX Item "-metrax100" +.PD +The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for +\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively. +.IP "\fB\-mmul\-bug\-workaround\fR" 4 +.IX Item "-mmul-bug-workaround" +.PD 0 +.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4 +.IX Item "-mno-mul-bug-workaround" +.PD +Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0 +models where it applies. This option is active by default. +.IP "\fB\-mpdebug\fR" 4 +.IX Item "-mpdebug" +Enable CRIS-specific verbose debug-related information in the assembly +code. This option also has the effect of turning off the \fB#NO_APP\fR +formatted-code indicator to the assembler at the beginning of the +assembly file. +.IP "\fB\-mcc\-init\fR" 4 +.IX Item "-mcc-init" +Do not use condition-code results from previous instruction; always emit +compare and test instructions before use of condition codes. +.IP "\fB\-mno\-side\-effects\fR" 4 +.IX Item "-mno-side-effects" +Do not emit instructions with side effects in addressing modes other than +post-increment. +.IP "\fB\-mstack\-align\fR" 4 +.IX Item "-mstack-align" +.PD 0 +.IP "\fB\-mno\-stack\-align\fR" 4 +.IX Item "-mno-stack-align" +.IP "\fB\-mdata\-align\fR" 4 +.IX Item "-mdata-align" +.IP "\fB\-mno\-data\-align\fR" 4 +.IX Item "-mno-data-align" +.IP "\fB\-mconst\-align\fR" 4 +.IX Item "-mconst-align" +.IP "\fB\-mno\-const\-align\fR" 4 +.IX Item "-mno-const-align" +.PD +These options (\fBno\-\fR options) arrange (eliminate arrangements) for the +stack frame, individual data and constants to be aligned for the maximum +single data access size for the chosen \s-1CPU\s0 model. The default is to +arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are +not affected by these options. +.IP "\fB\-m32\-bit\fR" 4 +.IX Item "-m32-bit" +.PD 0 +.IP "\fB\-m16\-bit\fR" 4 +.IX Item "-m16-bit" +.IP "\fB\-m8\-bit\fR" 4 +.IX Item "-m8-bit" +.PD +Similar to the stack\- data\- and const-align options above, these options +arrange for stack frame, writable data and constants to all be 32\-bit, +16\-bit or 8\-bit aligned. The default is 32\-bit alignment. +.IP "\fB\-mno\-prologue\-epilogue\fR" 4 +.IX Item "-mno-prologue-epilogue" +.PD 0 +.IP "\fB\-mprologue\-epilogue\fR" 4 +.IX Item "-mprologue-epilogue" +.PD +With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and +epilogue which set up the stack frame are omitted and no return +instructions or return sequences are generated in the code. Use this +option only together with visual inspection of the compiled code: no +warnings or errors are generated when call-saved registers must be saved, +or storage for local variables needs to be allocated. +.IP "\fB\-mno\-gotplt\fR" 4 +.IX Item "-mno-gotplt" +.PD 0 +.IP "\fB\-mgotplt\fR" 4 +.IX Item "-mgotplt" +.PD +With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) +instruction sequences that load addresses for functions from the \s-1PLT\s0 part +of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the +\&\s-1PLT.\s0 The default is \fB\-mgotplt\fR. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Legacy no-op option only recognized with the cris-axis-elf and +cris-axis-linux-gnu targets. +.IP "\fB\-mlinux\fR" 4 +.IX Item "-mlinux" +Legacy no-op option only recognized with the cris-axis-linux-gnu target. +.IP "\fB\-sim\fR" 4 +.IX Item "-sim" +This option, recognized for the cris-axis-elf, arranges +to link with input-output functions from a simulator library. Code, +initialized data and zero-initialized data are allocated consecutively. +.IP "\fB\-sim2\fR" 4 +.IX Item "-sim2" +Like \fB\-sim\fR, but pass linker options to locate initialized data at +0x40000000 and zero-initialized data at 0x80000000. +.PP +\fI\s-1CR16\s0 Options\fR +.IX Subsection "CR16 Options" +.PP +These options are defined specifically for the \s-1CR16\s0 ports. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mcr16cplus\fR" 4 +.IX Item "-mcr16cplus" +.PD 0 +.IP "\fB\-mcr16c\fR" 4 +.IX Item "-mcr16c" +.PD +Generate code for \s-1CR16C\s0 or \s-1CR16C+\s0 architecture. \s-1CR16C+\s0 architecture +is default. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Links the library libsim.a which is in compatible with simulator. Applicable +to \s-1ELF\s0 compiler only. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +Choose integer type as 32\-bit wide. +.IP "\fB\-mbit\-ops\fR" 4 +.IX Item "-mbit-ops" +Generates \f(CW\*(C`sbit\*(C'\fR/\f(CW\*(C`cbit\*(C'\fR instructions for bit manipulations. +.IP "\fB\-mdata\-model=\fR\fImodel\fR" 4 +.IX Item "-mdata-model=model" +Choose a data model. The choices for \fImodel\fR are \fBnear\fR, +\&\fBfar\fR or \fBmedium\fR. \fBmedium\fR is default. +However, \fBfar\fR is not valid with \fB\-mcr16c\fR, as the +\&\s-1CR16C\s0 architecture does not support the far data model. +.PP +\fIC\-SKY Options\fR +.IX Subsection "C-SKY Options" +.PP +\&\s-1GCC\s0 supports these options when compiling for C\-SKY V2 processors. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Specify the C\-SKY target architecture. Valid values for \fIarch\fR are: +\&\fBck801\fR, \fBck802\fR, \fBck803\fR, \fBck807\fR, and \fBck810\fR. +The default is \fBck810\fR. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Specify the C\-SKY target processor. Valid values for \fIcpu\fR are: +\&\fBck801\fR, \fBck801t\fR, +\&\fBck802\fR, \fBck802t\fR, \fBck802j\fR, +\&\fBck803\fR, \fBck803h\fR, \fBck803t\fR, \fBck803ht\fR, +\&\fBck803f\fR, \fBck803fh\fR, \fBck803e\fR, \fBck803eh\fR, +\&\fBck803et\fR, \fBck803eht\fR, \fBck803ef\fR, \fBck803efh\fR, +\&\fBck803ft\fR, \fBck803eft\fR, \fBck803efht\fR, \fBck803r1\fR, +\&\fBck803hr1\fR, \fBck803tr1\fR, \fBck803htr1\fR, \fBck803fr1\fR, +\&\fBck803fhr1\fR, \fBck803er1\fR, \fBck803ehr1\fR, \fBck803etr1\fR, +\&\fBck803ehtr1\fR, \fBck803efr1\fR, \fBck803efhr1\fR, \fBck803ftr1\fR, +\&\fBck803eftr1\fR, \fBck803efhtr1\fR, +\&\fBck803s\fR, \fBck803st\fR, \fBck803se\fR, \fBck803sf\fR, +\&\fBck803sef\fR, \fBck803seft\fR, +\&\fBck807e\fR, \fBck807ef\fR, \fBck807\fR, \fBck807f\fR, +\&\fBck810e\fR, \fBck810et\fR, \fBck810ef\fR, \fBck810eft\fR, +\&\fBck810\fR, \fBck810v\fR, \fBck810f\fR, \fBck810t\fR, \fBck810fv\fR, +\&\fBck810tv\fR, \fBck810ft\fR, and \fBck810ftv\fR. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +.PD +Select big\- or little-endian code. The default is little-endian. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Select hardware or software floating-point implementations. +The default is soft float. +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +.PD 0 +.IP "\fB\-mno\-double\-float\fR" 4 +.IX Item "-mno-double-float" +.PD +When \fB\-mhard\-float\fR is in effect, enable generation of +double-precision float instructions. This is the default except +when compiling for \s-1CK803.\s0 +.IP "\fB\-mfdivdu\fR" 4 +.IX Item "-mfdivdu" +.PD 0 +.IP "\fB\-mno\-fdivdu\fR" 4 +.IX Item "-mno-fdivdu" +.PD +When \fB\-mhard\-float\fR is in effect, enable generation of +\&\f(CW\*(C`frecipd\*(C'\fR, \f(CW\*(C`fsqrtd\*(C'\fR, and \f(CW\*(C`fdivd\*(C'\fR instructions. +This is the default except when compiling for \s-1CK803.\s0 +.IP "\fB\-mfpu=\fR\fIfpu\fR" 4 +.IX Item "-mfpu=fpu" +Select the floating-point processor. This option can only be used with +\&\fB\-mhard\-float\fR. +Values for \fIfpu\fR are +\&\fBfpv2_sf\fR (equivalent to \fB\-mno\-double\-float \-mno\-fdivdu\fR), +\&\fBfpv2\fR (\fB\-mdouble\-float \-mno\-divdu\fR), and +\&\fBfpv2_divd\fR (\fB\-mdouble\-float \-mdivdu\fR). +.IP "\fB\-melrw\fR" 4 +.IX Item "-melrw" +.PD 0 +.IP "\fB\-mno\-elrw\fR" 4 +.IX Item "-mno-elrw" +.PD +Enable the extended \f(CW\*(C`lrw\*(C'\fR instruction. This option defaults to on +for \s-1CK801\s0 and off otherwise. +.IP "\fB\-mistack\fR" 4 +.IX Item "-mistack" +.PD 0 +.IP "\fB\-mno\-istack\fR" 4 +.IX Item "-mno-istack" +.PD +Enable interrupt stack instructions; the default is off. +.Sp +The \fB\-mistack\fR option is required to handle the +\&\f(CW\*(C`interrupt\*(C'\fR and \f(CW\*(C`isr\*(C'\fR function attributes. +.IP "\fB\-mmp\fR" 4 +.IX Item "-mmp" +Enable multiprocessor instructions; the default is off. +.IP "\fB\-mcp\fR" 4 +.IX Item "-mcp" +Enable coprocessor instructions; the default is off. +.IP "\fB\-mcache\fR" 4 +.IX Item "-mcache" +Enable coprocessor instructions; the default is off. +.IP "\fB\-msecurity\fR" 4 +.IX Item "-msecurity" +Enable C\-SKY security instructions; the default is off. +.IP "\fB\-mtrust\fR" 4 +.IX Item "-mtrust" +Enable C\-SKY trust instructions; the default is off. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-medsp\fR" 4 +.IX Item "-medsp" +.IP "\fB\-mvdsp\fR" 4 +.IX Item "-mvdsp" +.PD +Enable C\-SKY \s-1DSP,\s0 Enhanced \s-1DSP,\s0 or Vector \s-1DSP\s0 instructions, respectively. +All of these options default to off. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Generate divide instructions. Default is off. +.IP "\fB\-msmart\fR" 4 +.IX Item "-msmart" +.PD 0 +.IP "\fB\-mno\-smart\fR" 4 +.IX Item "-mno-smart" +.PD +Generate code for Smart Mode, using only registers numbered 0\-7 to allow +use of 16\-bit instructions. This option is ignored for \s-1CK801\s0 where this +is the required behavior, and it defaults to on for \s-1CK802.\s0 +For other targets, the default is off. +.IP "\fB\-mhigh\-registers\fR" 4 +.IX Item "-mhigh-registers" +.PD 0 +.IP "\fB\-mno\-high\-registers\fR" 4 +.IX Item "-mno-high-registers" +.PD +Generate code using the high registers numbered 16\-31. This option +is not supported on \s-1CK801, CK802,\s0 or \s-1CK803,\s0 and is enabled by default +for other processors. +.IP "\fB\-manchor\fR" 4 +.IX Item "-manchor" +.PD 0 +.IP "\fB\-mno\-anchor\fR" 4 +.IX Item "-mno-anchor" +.PD +Generate code using global anchor symbol addresses. +.IP "\fB\-mpushpop\fR" 4 +.IX Item "-mpushpop" +.PD 0 +.IP "\fB\-mno\-pushpop\fR" 4 +.IX Item "-mno-pushpop" +.PD +Generate code using \f(CW\*(C`push\*(C'\fR and \f(CW\*(C`pop\*(C'\fR instructions. This option +defaults to on. +.IP "\fB\-mmultiple\-stld\fR" 4 +.IX Item "-mmultiple-stld" +.PD 0 +.IP "\fB\-mstm\fR" 4 +.IX Item "-mstm" +.IP "\fB\-mno\-multiple\-stld\fR" 4 +.IX Item "-mno-multiple-stld" +.IP "\fB\-mno\-stm\fR" 4 +.IX Item "-mno-stm" +.PD +Generate code using \f(CW\*(C`stm\*(C'\fR and \f(CW\*(C`ldm\*(C'\fR instructions. This option +isn't supported on \s-1CK801\s0 but is enabled by default on other processors. +.IP "\fB\-mconstpool\fR" 4 +.IX Item "-mconstpool" +.PD 0 +.IP "\fB\-mno\-constpool\fR" 4 +.IX Item "-mno-constpool" +.PD +Create constant pools in the compiler instead of deferring it to the +assembler. This option is the default and required for correct code +generation on \s-1CK801\s0 and \s-1CK802,\s0 and is optional on other processors. +.IP "\fB\-mstack\-size\fR" 4 +.IX Item "-mstack-size" +.PD 0 +.IP "\fB\-mno\-stack\-size\fR" 4 +.IX Item "-mno-stack-size" +.PD +Emit \f(CW\*(C`.stack_size\*(C'\fR directives for each function in the assembly +output. This option defaults to off. +.IP "\fB\-mccrt\fR" 4 +.IX Item "-mccrt" +.PD 0 +.IP "\fB\-mno\-ccrt\fR" 4 +.IX Item "-mno-ccrt" +.PD +Generate code for the C\-SKY compiler runtime instead of libgcc. This +option defaults to off. +.IP "\fB\-mbranch\-cost=\fR\fIn\fR" 4 +.IX Item "-mbranch-cost=n" +Set the branch costs to roughly \f(CW\*(C`n\*(C'\fR instructions. The default is 1. +.IP "\fB\-msched\-prolog\fR" 4 +.IX Item "-msched-prolog" +.PD 0 +.IP "\fB\-mno\-sched\-prolog\fR" 4 +.IX Item "-mno-sched-prolog" +.PD +Permit scheduling of function prologue and epilogue sequences. Using +this option can result in code that is not compliant with the C\-SKY V2 \s-1ABI\s0 +prologue requirements and that cannot be debugged or backtraced. +It is disabled by default. +.PP +\fIDarwin Options\fR +.IX Subsection "Darwin Options" +.PP +These options are defined for all architectures running the Darwin operating +system. +.PP +\&\s-1FSF GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates +an object file for the single architecture that \s-1GCC\s0 was built to +target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple +\&\fB\-arch\fR options are used; it does so by running the compiler or +linker multiple times and joining the results together with +\&\fIlipo\fR. +.PP +The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or +\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0 +that \s-1GCC\s0 is targeting, like \fB\-mcpu\fR or \fB\-march\fR. The +\&\fB\-force_cpusubtype_ALL\fR option can be used to override this. +.PP +The Darwin tools vary in their behavior when presented with an \s-1ISA\s0 +mismatch. The assembler, \fIas\fR, only permits instructions to +be used that are valid for the subtype of the file it is generating, +so you cannot put 64\-bit instructions in a \fBppc750\fR object file. +The linker for shared libraries, \fI/usr/bin/libtool\fR, fails +and prints an error if asked to create a shared library with a less +restrictive subtype than its input files (for instance, trying to put +a \fBppc970\fR object file in a \fBppc7400\fR library). The linker +for executables, \fBld\fR, quietly gives the executable the most +restrictive subtype of any of its input files. +.IP "\fB\-F\fR\fIdir\fR" 4 +.IX Item "-Fdir" +Add the framework directory \fIdir\fR to the head of the list of +directories to be searched for header files. These directories are +interleaved with those specified by \fB\-I\fR options and are +scanned in a left-to-right order. +.Sp +A framework directory is a directory with frameworks in it. A +framework is a directory with a \fIHeaders\fR and/or +\&\fIPrivateHeaders\fR directory contained directly in it that ends +in \fI.framework\fR. The name of a framework is the name of this +directory excluding the \fI.framework\fR. Headers associated with +the framework are found in one of those two directories, with +\&\fIHeaders\fR being searched first. A subframework is a framework +directory that is in a framework's \fIFrameworks\fR directory. +Includes of subframework headers can only appear in a header of a +framework that contains the subframework, or in a sibling subframework +header. Two subframeworks are siblings if they occur in the same +framework. A subframework should not have the same name as a +framework; a warning is issued if this is violated. Currently a +subframework cannot have subframeworks; in the future, the mechanism +may be extended to support this. The standard frameworks can be found +in \fI/System/Library/Frameworks\fR and +\&\fI/Library/Frameworks\fR. An example include looks like +\&\f(CW\*(C`#include \*(C'\fR, where \fIFramework\fR denotes +the name of the framework and \fIheader.h\fR is found in the +\&\fIPrivateHeaders\fR or \fIHeaders\fR directory. +.IP "\fB\-iframework\fR\fIdir\fR" 4 +.IX Item "-iframeworkdir" +Like \fB\-F\fR except the directory is a treated as a system +directory. The main difference between this \fB\-iframework\fR and +\&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not +warn about constructs contained within header files found via +\&\fIdir\fR. This option is valid only for the C family of languages. +.IP "\fB\-gused\fR" 4 +.IX Item "-gused" +Emit debugging information for symbols that are used. For stabs +debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. +This is by default \s-1ON.\s0 +.IP "\fB\-gfull\fR" 4 +.IX Item "-gfull" +Emit debugging information for all symbols and types. +.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4 +.IX Item "-mmacosx-version-min=version" +The earliest version of MacOS X that this executable will run on +is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR, +\&\f(CW10.2\fR, and \f(CW10.3.9\fR. +.Sp +If the compiler was built to use the system's headers by default, +then the default for this option is the system version on which the +compiler is running, otherwise the default is to make choices that +are compatible with as many systems and code bases as possible. +.IP "\fB\-mkernel\fR" 4 +.IX Item "-mkernel" +Enable kernel development mode. The \fB\-mkernel\fR option sets +\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-use\-cxa\-atexit\fR, +\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR, +\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where +applicable. This mode also sets \fB\-mno\-altivec\fR, +\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and +\&\fB\-mlong\-branch\fR for PowerPC targets. +.IP "\fB\-mone\-byte\-bool\fR" 4 +.IX Item "-mone-byte-bool" +Override the defaults for \f(CW\*(C`bool\*(C'\fR so that \f(CW\*(C`sizeof(bool)==1\*(C'\fR. +By default \f(CW\*(C`sizeof(bool)\*(C'\fR is \f(CW4\fR when compiling for +Darwin/PowerPC and \f(CW1\fR when compiling for Darwin/x86, so this +option has no effect on x86. +.Sp +\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0 +to generate code that is not binary compatible with code generated +without that switch. Using this switch may require recompiling all +other modules in a program, including system libraries. Use this +switch to conform to a non-default data model. +.IP "\fB\-mfix\-and\-continue\fR" 4 +.IX Item "-mfix-and-continue" +.PD 0 +.IP "\fB\-ffix\-and\-continue\fR" 4 +.IX Item "-ffix-and-continue" +.IP "\fB\-findirect\-data\fR" 4 +.IX Item "-findirect-data" +.PD +Generate code suitable for fast turnaround development, such as to +allow \s-1GDB\s0 to dynamically load \fI.o\fR files into already-running +programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR +are provided for backwards compatibility. +.IP "\fB\-all_load\fR" 4 +.IX Item "-all_load" +Loads all members of static archive libraries. +See man \fBld\fR\|(1) for more information. +.IP "\fB\-arch_errors_fatal\fR" 4 +.IX Item "-arch_errors_fatal" +Cause the errors having to do with files that have the wrong architecture +to be fatal. +.IP "\fB\-bind_at_load\fR" 4 +.IX Item "-bind_at_load" +Causes the output file to be marked such that the dynamic linker will +bind all undefined references when the file is loaded or launched. +.IP "\fB\-bundle\fR" 4 +.IX Item "-bundle" +Produce a Mach-o bundle format file. +See man \fBld\fR\|(1) for more information. +.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4 +.IX Item "-bundle_loader executable" +This option specifies the \fIexecutable\fR that will load the build +output file being linked. See man \fBld\fR\|(1) for more information. +.IP "\fB\-dynamiclib\fR" 4 +.IX Item "-dynamiclib" +When passed this option, \s-1GCC\s0 produces a dynamic library instead of +an executable when linking, using the Darwin \fIlibtool\fR command. +.IP "\fB\-force_cpusubtype_ALL\fR" 4 +.IX Item "-force_cpusubtype_ALL" +This causes \s-1GCC\s0's output file to have the \fB\s-1ALL\s0\fR subtype, instead of +one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. +.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 +.IX Item "-allowable_client client_name" +.PD 0 +.IP "\fB\-client_name\fR" 4 +.IX Item "-client_name" +.IP "\fB\-compatibility_version\fR" 4 +.IX Item "-compatibility_version" +.IP "\fB\-current_version\fR" 4 +.IX Item "-current_version" +.IP "\fB\-dead_strip\fR" 4 +.IX Item "-dead_strip" +.IP "\fB\-dependency\-file\fR" 4 +.IX Item "-dependency-file" +.IP "\fB\-dylib_file\fR" 4 +.IX Item "-dylib_file" +.IP "\fB\-dylinker_install_name\fR" 4 +.IX Item "-dylinker_install_name" +.IP "\fB\-dynamic\fR" 4 +.IX Item "-dynamic" +.IP "\fB\-exported_symbols_list\fR" 4 +.IX Item "-exported_symbols_list" +.IP "\fB\-filelist\fR" 4 +.IX Item "-filelist" +.IP "\fB\-flat_namespace\fR" 4 +.IX Item "-flat_namespace" +.IP "\fB\-force_flat_namespace\fR" 4 +.IX Item "-force_flat_namespace" +.IP "\fB\-headerpad_max_install_names\fR" 4 +.IX Item "-headerpad_max_install_names" +.IP "\fB\-image_base\fR" 4 +.IX Item "-image_base" +.IP "\fB\-init\fR" 4 +.IX Item "-init" +.IP "\fB\-install_name\fR" 4 +.IX Item "-install_name" +.IP "\fB\-keep_private_externs\fR" 4 +.IX Item "-keep_private_externs" +.IP "\fB\-multi_module\fR" 4 +.IX Item "-multi_module" +.IP "\fB\-multiply_defined\fR" 4 +.IX Item "-multiply_defined" +.IP "\fB\-multiply_defined_unused\fR" 4 +.IX Item "-multiply_defined_unused" +.IP "\fB\-noall_load\fR" 4 +.IX Item "-noall_load" +.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4 +.IX Item "-no_dead_strip_inits_and_terms" +.IP "\fB\-nofixprebinding\fR" 4 +.IX Item "-nofixprebinding" +.IP "\fB\-nomultidefs\fR" 4 +.IX Item "-nomultidefs" +.IP "\fB\-noprebind\fR" 4 +.IX Item "-noprebind" +.IP "\fB\-noseglinkedit\fR" 4 +.IX Item "-noseglinkedit" +.IP "\fB\-pagezero_size\fR" 4 +.IX Item "-pagezero_size" +.IP "\fB\-prebind\fR" 4 +.IX Item "-prebind" +.IP "\fB\-prebind_all_twolevel_modules\fR" 4 +.IX Item "-prebind_all_twolevel_modules" +.IP "\fB\-private_bundle\fR" 4 +.IX Item "-private_bundle" +.IP "\fB\-read_only_relocs\fR" 4 +.IX Item "-read_only_relocs" +.IP "\fB\-sectalign\fR" 4 +.IX Item "-sectalign" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-whyload\fR" 4 +.IX Item "-whyload" +.IP "\fB\-seg1addr\fR" 4 +.IX Item "-seg1addr" +.IP "\fB\-sectcreate\fR" 4 +.IX Item "-sectcreate" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-sectorder\fR" 4 +.IX Item "-sectorder" +.IP "\fB\-segaddr\fR" 4 +.IX Item "-segaddr" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-seg_addr_table\fR" 4 +.IX Item "-seg_addr_table" +.IP "\fB\-seg_addr_table_filename\fR" 4 +.IX Item "-seg_addr_table_filename" +.IP "\fB\-seglinkedit\fR" 4 +.IX Item "-seglinkedit" +.IP "\fB\-segprot\fR" 4 +.IX Item "-segprot" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-single_module\fR" 4 +.IX Item "-single_module" +.IP "\fB\-static\fR" 4 +.IX Item "-static" +.IP "\fB\-sub_library\fR" 4 +.IX Item "-sub_library" +.IP "\fB\-sub_umbrella\fR" 4 +.IX Item "-sub_umbrella" +.IP "\fB\-twolevel_namespace\fR" 4 +.IX Item "-twolevel_namespace" +.IP "\fB\-umbrella\fR" 4 +.IX Item "-umbrella" +.IP "\fB\-undefined\fR" 4 +.IX Item "-undefined" +.IP "\fB\-unexported_symbols_list\fR" 4 +.IX Item "-unexported_symbols_list" +.IP "\fB\-weak_reference_mismatches\fR" 4 +.IX Item "-weak_reference_mismatches" +.IP "\fB\-whatsloaded\fR" 4 +.IX Item "-whatsloaded" +.PD +These options are passed to the Darwin linker. The Darwin linker man page +describes them in detail. +.PP +\fI\s-1DEC\s0 Alpha Options\fR +.IX Subsection "DEC Alpha Options" +.PP +These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations: +.IP "\fB\-mno\-soft\-float\fR" 4 +.IX Item "-mno-soft-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions for +floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR are used to perform floating-point +operations. Unless they are replaced by routines that emulate the +floating-point operations, or compiled in such a way as to call such +emulations routines, these routines issue floating-point +operations. If you are compiling for an Alpha without floating-point +operations, you must ensure that the library is built so as not to call +them. +.Sp +Note that Alpha implementations without floating-point operations are +required to have floating-point registers. +.IP "\fB\-mfp\-reg\fR" 4 +.IX Item "-mfp-reg" +.PD 0 +.IP "\fB\-mno\-fp\-regs\fR" 4 +.IX Item "-mno-fp-regs" +.PD +Generate code that uses (does not use) the floating-point register set. +\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point +register set is not used, floating-point operands are passed in integer +registers as if they were integers and floating-point results are passed +in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence, +so any function with a floating-point argument or return value called by code +compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that +option. +.Sp +A typical use of this option is building a kernel that does not use, +and hence need not save and restore, any floating-point registers. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +The Alpha architecture implements floating-point hardware optimized for +maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating-point +standard. However, for full compliance, software assistance is +required. This option generates code fully IEEE-compliant code +\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below). +If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is +defined during compilation. The resulting code is less efficient but is +able to correctly support denormalized numbers and exceptional \s-1IEEE\s0 +values such as not-a-number and plus/minus infinity. Other Alpha +compilers call this option \fB\-ieee_with_no_inexact\fR. +.IP "\fB\-mieee\-with\-inexact\fR" 4 +.IX Item "-mieee-with-inexact" +This is like \fB\-mieee\fR except the generated code also maintains +the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the +generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to +\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor +macro. On some Alpha implementations the resulting code may execute +significantly slower than the code generated by default. Since there is +very little code that depends on the \fIinexact-flag\fR, you should +normally not specify this option. Other Alpha compilers call this +option \fB\-ieee_with_inexact\fR. +.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4 +.IX Item "-mfp-trap-mode=trap-mode" +This option controls what floating-point related traps are enabled. +Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR. +The trap mode can be set to one of four values: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +This is the default (normal) setting. The only traps that are enabled +are the ones that cannot be disabled in software (e.g., division by zero +trap). +.IP "\fBu\fR" 4 +.IX Item "u" +In addition to the traps enabled by \fBn\fR, underflow traps are enabled +as well. +.IP "\fBsu\fR" 4 +.IX Item "su" +Like \fBu\fR, but the instructions are marked to be safe for software +completion (see Alpha architecture manual for details). +.IP "\fBsui\fR" 4 +.IX Item "sui" +Like \fBsu\fR, but inexact traps are enabled as well. +.RE +.RS 4 +.RE +.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4 +.IX Item "-mfp-rounding-mode=rounding-mode" +Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option +\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one +of: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +Normal \s-1IEEE\s0 rounding mode. Floating-point numbers are rounded towards +the nearest machine number or towards the even machine number in case +of a tie. +.IP "\fBm\fR" 4 +.IX Item "m" +Round towards minus infinity. +.IP "\fBc\fR" 4 +.IX Item "c" +Chopped rounding mode. Floating-point numbers are rounded towards zero. +.IP "\fBd\fR" 4 +.IX Item "d" +Dynamic rounding mode. A field in the floating-point control register +(\fIfpcr\fR, see Alpha architecture reference manual) controls the +rounding mode in effect. The C library initializes this register for +rounding towards plus infinity. Thus, unless your program modifies the +\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity. +.RE +.RS 4 +.RE +.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4 +.IX Item "-mtrap-precision=trap-precision" +In the Alpha architecture, floating-point traps are imprecise. This +means without software assistance it is impossible to recover from a +floating trap and program execution normally needs to be terminated. +\&\s-1GCC\s0 can generate code that can assist operating system trap handlers +in determining the exact location that caused a floating-point trap. +Depending on the requirements of an application, different levels of +precisions can be selected: +.RS 4 +.IP "\fBp\fR" 4 +.IX Item "p" +Program precision. This option is the default and means a trap handler +can only identify which program caused a floating-point exception. +.IP "\fBf\fR" 4 +.IX Item "f" +Function precision. The trap handler can determine the function that +caused a floating-point exception. +.IP "\fBi\fR" 4 +.IX Item "i" +Instruction precision. The trap handler can determine the exact +instruction that caused a floating-point exception. +.RE +.RS 4 +.Sp +Other Alpha compilers provide the equivalent options called +\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR. +.RE +.IP "\fB\-mieee\-conformant\fR" 4 +.IX Item "-mieee-conformant" +This option marks the generated code as \s-1IEEE\s0 conformant. You must not +use this option unless you also specify \fB\-mtrap\-precision=i\fR and either +\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect +is to emit the line \fB.eflag 48\fR in the function prologue of the +generated assembly file. +.IP "\fB\-mbuild\-constants\fR" 4 +.IX Item "-mbuild-constants" +Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to +see if it can construct it from smaller constants in two or three +instructions. If it cannot, it outputs the constant as a literal and +generates code to load it from the data segment at run time. +.Sp +Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants +using code, even if it takes more instructions (the maximum is six). +.Sp +You typically use this option to build a shared library dynamic +loader. Itself a shared library, it must relocate itself in memory +before it can find the variables and constants in its own data segment. +.IP "\fB\-mbwx\fR" 4 +.IX Item "-mbwx" +.PD 0 +.IP "\fB\-mno\-bwx\fR" 4 +.IX Item "-mno-bwx" +.IP "\fB\-mcix\fR" 4 +.IX Item "-mcix" +.IP "\fB\-mno\-cix\fR" 4 +.IX Item "-mno-cix" +.IP "\fB\-mfix\fR" 4 +.IX Item "-mfix" +.IP "\fB\-mno\-fix\fR" 4 +.IX Item "-mno-fix" +.IP "\fB\-mmax\fR" 4 +.IX Item "-mmax" +.IP "\fB\-mno\-max\fR" 4 +.IX Item "-mno-max" +.PD +Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX, +CIX, FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction +sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that +of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified. +.IP "\fB\-mfloat\-vax\fR" 4 +.IX Item "-mfloat-vax" +.PD 0 +.IP "\fB\-mfloat\-ieee\fR" 4 +.IX Item "-mfloat-ieee" +.PD +Generate code that uses (does not use) \s-1VAX F\s0 and G floating-point +arithmetic instead of \s-1IEEE\s0 single and double precision. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Older Alpha assemblers provided no way to generate symbol relocations +except via assembler macros. Use of these macros does not allow +optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12 +supports a new syntax that allows the compiler to explicitly mark +which relocations should apply to which instructions. This option +is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of +the assembler when it is built and sets the default accordingly. +.IP "\fB\-msmall\-data\fR" 4 +.IX Item "-msmall-data" +.PD 0 +.IP "\fB\-mlarge\-data\fR" 4 +.IX Item "-mlarge-data" +.PD +When \fB\-mexplicit\-relocs\fR is in effect, static data is +accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR +is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR +(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via +16\-bit relocations off of the \f(CW$gp\fR register. This limits the +size of the small data area to 64KB, but allows the variables to be +directly accessed via a single instruction. +.Sp +The default is \fB\-mlarge\-data\fR. With this option the data area +is limited to just below 2GB. Programs that require more than 2GB of +data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the +heap instead of in the program's data segment. +.Sp +When generating code for shared libraries, \fB\-fpic\fR implies +\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR. +.IP "\fB\-msmall\-text\fR" 4 +.IX Item "-msmall-text" +.PD 0 +.IP "\fB\-mlarge\-text\fR" 4 +.IX Item "-mlarge-text" +.PD +When \fB\-msmall\-text\fR is used, the compiler assumes that the +code of the entire program (or shared library) fits in 4MB, and is +thus reachable with a branch instruction. When \fB\-msmall\-data\fR +is used, the compiler can assume that all local symbols share the +same \f(CW$gp\fR value, and thus reduce the number of instructions +required for a function call from 4 to 1. +.Sp +The default is \fB\-mlarge\-text\fR. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set and instruction scheduling parameters for +machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR +style name or the corresponding chip number. \s-1GCC\s0 supports scheduling +parameters for the \s-1EV4, EV5\s0 and \s-1EV6\s0 family of processors and +chooses the default values for the instruction set from the processor +you specify. If you do not specify a processor type, \s-1GCC\s0 defaults +to the processor on which the compiler was built. +.Sp +Supported values for \fIcpu_type\fR are +.RS 4 +.IP "\fBev4\fR" 4 +.IX Item "ev4" +.PD 0 +.IP "\fBev45\fR" 4 +.IX Item "ev45" +.IP "\fB21064\fR" 4 +.IX Item "21064" +.PD +Schedules as an \s-1EV4\s0 and has no instruction set extensions. +.IP "\fBev5\fR" 4 +.IX Item "ev5" +.PD 0 +.IP "\fB21164\fR" 4 +.IX Item "21164" +.PD +Schedules as an \s-1EV5\s0 and has no instruction set extensions. +.IP "\fBev56\fR" 4 +.IX Item "ev56" +.PD 0 +.IP "\fB21164a\fR" 4 +.IX Item "21164a" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension. +.IP "\fBpca56\fR" 4 +.IX Item "pca56" +.PD 0 +.IP "\fB21164pc\fR" 4 +.IX Item "21164pc" +.IP "\fB21164PC\fR" 4 +.IX Item "21164PC" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions. +.IP "\fBev6\fR" 4 +.IX Item "ev6" +.PD 0 +.IP "\fB21264\fR" 4 +.IX Item "21264" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX, FIX,\s0 and \s-1MAX\s0 extensions. +.IP "\fBev67\fR" 4 +.IX Item "ev67" +.PD 0 +.IP "\fB21264a\fR" 4 +.IX Item "21264a" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX, CIX, FIX,\s0 and \s-1MAX\s0 extensions. +.RE +.RS 4 +.Sp +Native toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.RE +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set only the instruction scheduling parameters for machine type +\&\fIcpu_type\fR. The instruction set is not changed. +.Sp +Native toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mtune=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4 +.IX Item "-mmemory-latency=time" +Sets the latency the scheduler should assume for typical memory +references as seen by the application. This number is highly +dependent on the memory access patterns used by the application +and the size of the external cache on the machine. +.Sp +Valid options for \fItime\fR are +.RS 4 +.IP "\fInumber\fR" 4 +.IX Item "number" +A decimal number representing clock cycles. +.IP "\fBL1\fR" 4 +.IX Item "L1" +.PD 0 +.IP "\fBL2\fR" 4 +.IX Item "L2" +.IP "\fBL3\fR" 4 +.IX Item "L3" +.IP "\fBmain\fR" 4 +.IX Item "main" +.PD +The compiler contains estimates of the number of clock cycles for +\&\*(L"typical\*(R" \s-1EV4 & EV5\s0 hardware for the Level 1, 2 & 3 caches +(also called Dcache, Scache, and Bcache), as well as to main memory. +Note that L3 is only valid for \s-1EV5.\s0 +.RE +.RS 4 +.RE +.PP +\fI\s-1FR30\s0 Options\fR +.IX Subsection "FR30 Options" +.PP +These options are defined specifically for the \s-1FR30\s0 port. +.IP "\fB\-msmall\-model\fR" 4 +.IX Item "-msmall-model" +Use the small address space model. This can produce smaller code, but +it does assume that all symbolic values and addresses fit into a +20\-bit range. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that runtime support has been provided and so there is no need +to include the simulator library (\fIlibsim.a\fR) on the linker +command line. +.PP +\fI\s-1FT32\s0 Options\fR +.IX Subsection "FT32 Options" +.PP +These options are defined specifically for the \s-1FT32\s0 port. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +an alternate runtime startup and library to be linked. +You must not use this option when generating programs that will run on +real hardware; you must provide your own runtime library for whatever +I/O functions are needed. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Enable Local Register Allocation. This is still experimental for \s-1FT32,\s0 +so by default the compiler uses standard reload. +.IP "\fB\-mnodiv\fR" 4 +.IX Item "-mnodiv" +Do not use div and mod instructions. +.IP "\fB\-mft32b\fR" 4 +.IX Item "-mft32b" +Enable use of the extended instructions of the \s-1FT32B\s0 processor. +.IP "\fB\-mcompress\fR" 4 +.IX Item "-mcompress" +Compress all code using the Ft32B code compression scheme. +.IP "\fB\-mnopm\fR" 4 +.IX Item "-mnopm" +Do not generate code that reads program memory. +.PP +\fI\s-1FRV\s0 Options\fR +.IX Subsection "FRV Options" +.IP "\fB\-mgpr\-32\fR" 4 +.IX Item "-mgpr-32" +Only use the first 32 general-purpose registers. +.IP "\fB\-mgpr\-64\fR" 4 +.IX Item "-mgpr-64" +Use all 64 general-purpose registers. +.IP "\fB\-mfpr\-32\fR" 4 +.IX Item "-mfpr-32" +Use only the first 32 floating-point registers. +.IP "\fB\-mfpr\-64\fR" 4 +.IX Item "-mfpr-64" +Use all 64 floating-point registers. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware instructions for floating-point operations. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use library routines for floating-point operations. +.IP "\fB\-malloc\-cc\fR" 4 +.IX Item "-malloc-cc" +Dynamically allocate condition code registers. +.IP "\fB\-mfixed\-cc\fR" 4 +.IX Item "-mfixed-cc" +Do not try to dynamically allocate condition code registers, only +use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR. +.IP "\fB\-mdword\fR" 4 +.IX Item "-mdword" +Change \s-1ABI\s0 to use double word insns. +.IP "\fB\-mno\-dword\fR" 4 +.IX Item "-mno-dword" +Do not use double word instructions. +.IP "\fB\-mdouble\fR" 4 +.IX Item "-mdouble" +Use floating-point double instructions. +.IP "\fB\-mno\-double\fR" 4 +.IX Item "-mno-double" +Do not use floating-point double instructions. +.IP "\fB\-mmedia\fR" 4 +.IX Item "-mmedia" +Use media instructions. +.IP "\fB\-mno\-media\fR" 4 +.IX Item "-mno-media" +Do not use media instructions. +.IP "\fB\-mmuladd\fR" 4 +.IX Item "-mmuladd" +Use multiply and add/subtract instructions. +.IP "\fB\-mno\-muladd\fR" 4 +.IX Item "-mno-muladd" +Do not use multiply and add/subtract instructions. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Select the \s-1FDPIC ABI,\s0 which uses function descriptors to represent +pointers to functions. Without any PIC/PIE\-related options, it +implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it +assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the +\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets +are computed with 32 bits. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +It's enabled by default if optimizing for speed and compiling for +shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an +optimization option such as \fB\-O3\fR or above is present in the +command line. +.IP "\fB\-mTLS\fR" 4 +.IX Item "-mTLS" +Assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mtls\fR" 4 +.IX Item "-mtls" +Do not assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mgprel\-ro\fR" 4 +.IX Item "-mgprel-ro" +Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC ABI\s0 for data +that is known to be in read-only sections. It's enabled by default, +except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help +make the global offset table smaller, it trades 1 instruction for 4. +With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4, +one of which may be shared by multiple symbols, and it avoids the need +for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a +win. If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it. +.IP "\fB\-multilib\-library\-pic\fR" 4 +.IX Item "-multilib-library-pic" +Link with the (library, not \s-1FD\s0) pic libraries. It's implied by +\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and +\&\fB\-fpic\fR without \fB\-mfdpic\fR. You should never have to use +it explicitly. +.IP "\fB\-mlinked\-fp\fR" 4 +.IX Item "-mlinked-fp" +Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever +a stack frame is allocated. This option is enabled by default and can +be disabled with \fB\-mno\-linked\-fp\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Use indirect addressing to call functions outside the current +compilation unit. This allows the functions to be placed anywhere +within the 32\-bit address space. +.IP "\fB\-malign\-labels\fR" 4 +.IX Item "-malign-labels" +Try to align labels to an 8\-byte boundary by inserting NOPs into the +previous packet. This option only has an effect when \s-1VLIW\s0 packing +is enabled. It doesn't create new packets; it merely adds NOPs to +existing ones. +.IP "\fB\-mlibrary\-pic\fR" 4 +.IX Item "-mlibrary-pic" +Generate position-independent \s-1EABI\s0 code. +.IP "\fB\-macc\-4\fR" 4 +.IX Item "-macc-4" +Use only the first four media accumulator registers. +.IP "\fB\-macc\-8\fR" 4 +.IX Item "-macc-8" +Use all eight media accumulator registers. +.IP "\fB\-mpack\fR" 4 +.IX Item "-mpack" +Pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-pack\fR" 4 +.IX Item "-mno-pack" +Do not pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-eflags\fR" 4 +.IX Item "-mno-eflags" +Do not mark \s-1ABI\s0 switches in e_flags. +.IP "\fB\-mcond\-move\fR" 4 +.IX Item "-mcond-move" +Enable the use of conditional-move instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-move\fR" 4 +.IX Item "-mno-cond-move" +Disable the use of conditional-move instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mscc\fR" 4 +.IX Item "-mscc" +Enable the use of conditional set instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-scc\fR" 4 +.IX Item "-mno-scc" +Disable the use of conditional set instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mcond\-exec\fR" 4 +.IX Item "-mcond-exec" +Enable the use of conditional execution (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-exec\fR" 4 +.IX Item "-mno-cond-exec" +Disable the use of conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mvliw\-branch\fR" 4 +.IX Item "-mvliw-branch" +Run a pass to pack branches into \s-1VLIW\s0 instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-vliw\-branch\fR" 4 +.IX Item "-mno-vliw-branch" +Do not run a pass to pack branches into \s-1VLIW\s0 instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mmulti\-cond\-exec\fR" 4 +.IX Item "-mmulti-cond-exec" +Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution +(default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-multi\-cond\-exec\fR" 4 +.IX Item "-mno-multi-cond-exec" +Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mnested\-cond\-exec\fR" 4 +.IX Item "-mnested-cond-exec" +Enable nested conditional execution optimizations (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-nested\-cond\-exec\fR" 4 +.IX Item "-mno-nested-cond-exec" +Disable nested conditional execution optimizations. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-moptimize\-membar\fR" 4 +.IX Item "-moptimize-membar" +This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the +compiler-generated code. It is enabled by default. +.IP "\fB\-mno\-optimize\-membar\fR" 4 +.IX Item "-mno-optimize-membar" +This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR +instructions from the generated code. +.IP "\fB\-mtomcat\-stats\fR" 4 +.IX Item "-mtomcat-stats" +Cause gas to print out tomcat statistics. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Select the processor type for which to generate code. Possible values are +\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR, +\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR. +.PP +\fIGNU/Linux Options\fR +.IX Subsection "GNU/Linux Options" +.PP +These \fB\-m\fR options are defined for GNU/Linux targets: +.IP "\fB\-mglibc\fR" 4 +.IX Item "-mglibc" +Use the \s-1GNU C\s0 library. This is the default except +on \fB*\-*\-linux\-*uclibc*\fR, \fB*\-*\-linux\-*musl*\fR and +\&\fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-muclibc\fR" 4 +.IX Item "-muclibc" +Use uClibc C library. This is the default on +\&\fB*\-*\-linux\-*uclibc*\fR targets. +.IP "\fB\-mmusl\fR" 4 +.IX Item "-mmusl" +Use the musl C library. This is the default on +\&\fB*\-*\-linux\-*musl*\fR targets. +.IP "\fB\-mbionic\fR" 4 +.IX Item "-mbionic" +Use Bionic C library. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-mandroid\fR" 4 +.IX Item "-mandroid" +Compile code compatible with Android platform. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.Sp +When compiling, this option enables \fB\-mbionic\fR, \fB\-fPIC\fR, +\&\fB\-fno\-exceptions\fR and \fB\-fno\-rtti\fR by default. When linking, +this option makes the \s-1GCC\s0 driver pass Android-specific options to the linker. +Finally, this option causes the preprocessor macro \f(CW\*(C`_\|_ANDROID_\|_\*(C'\fR +to be defined. +.IP "\fB\-tno\-android\-cc\fR" 4 +.IX Item "-tno-android-cc" +Disable compilation effects of \fB\-mandroid\fR, i.e., do not enable +\&\fB\-mbionic\fR, \fB\-fPIC\fR, \fB\-fno\-exceptions\fR and +\&\fB\-fno\-rtti\fR by default. +.IP "\fB\-tno\-android\-ld\fR" 4 +.IX Item "-tno-android-ld" +Disable linking effects of \fB\-mandroid\fR, i.e., pass standard Linux +linking options to the linker. +.PP +\fIH8/300 Options\fR +.IX Subsection "H8/300 Options" +.PP +These \fB\-m\fR options are defined for the H8/300 implementations: +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mh\fR" 4 +.IX Item "-mh" +Generate code for the H8/300H. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Generate code for the H8S. +.IP "\fB\-mn\fR" 4 +.IX Item "-mn" +Generate code for the H8S and H8/300H in the normal mode. This switch +must be used either with \fB\-mh\fR or \fB\-ms\fR. +.IP "\fB\-ms2600\fR" 4 +.IX Item "-ms2600" +Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR. +.IP "\fB\-mexr\fR" 4 +.IX Item "-mexr" +Extended registers are stored on stack before execution of function +with monitor attribute. Default option is \fB\-mexr\fR. +This option is valid only for H8S targets. +.IP "\fB\-mno\-exr\fR" 4 +.IX Item "-mno-exr" +Extended registers are not stored on stack before execution of function +with monitor attribute. Default option is \fB\-mno\-exr\fR. +This option is valid only for H8S targets. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +Make \f(CW\*(C`int\*(C'\fR data 32 bits by default. +.IP "\fB\-malign\-300\fR" 4 +.IX Item "-malign-300" +On the H8/300H and H8S, use the same alignment rules as for the H8/300. +The default for the H8/300H and H8S is to align longs and floats on +4\-byte boundaries. +\&\fB\-malign\-300\fR causes them to be aligned on 2\-byte boundaries. +This option has no effect on the H8/300. +.PP +\fI\s-1HPPA\s0 Options\fR +.IX Subsection "HPPA Options" +.PP +These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA 1.0,\s0 \fB1.1\fR for \s-1PA +1.1,\s0 and \fB2.0\fR for \s-1PA 2.0\s0 processors. Refer to +\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper +architecture option for your machine. Code compiled for lower numbered +architectures runs on higher numbered architectures, but not the +other way around. +.IP "\fB\-mpa\-risc\-1\-0\fR" 4 +.IX Item "-mpa-risc-1-0" +.PD 0 +.IP "\fB\-mpa\-risc\-1\-1\fR" 4 +.IX Item "-mpa-risc-1-1" +.IP "\fB\-mpa\-risc\-2\-0\fR" 4 +.IX Item "-mpa-risc-2-0" +.PD +Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively. +.IP "\fB\-mcaller\-copies\fR" 4 +.IX Item "-mcaller-copies" +The caller copies function arguments passed by hidden reference. This +option should be used with care as it is not compatible with the default +32\-bit runtime. However, only aggregates larger than eight bytes are +passed by hidden reference and the option provides better compatibility +with OpenMP. +.IP "\fB\-mjump\-in\-delay\fR" 4 +.IX Item "-mjump-in-delay" +This option is ignored and provided for compatibility purposes only. +.IP "\fB\-mdisable\-fpregs\fR" 4 +.IX Item "-mdisable-fpregs" +Prevent floating-point registers from being used in any manner. This is +necessary for compiling kernels that perform lazy context switching of +floating-point registers. If you use this option and attempt to perform +floating-point operations, the compiler aborts. +.IP "\fB\-mdisable\-indexing\fR" 4 +.IX Item "-mdisable-indexing" +Prevent the compiler from using indexing address modes. This avoids some +rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH.\s0 +.IP "\fB\-mno\-space\-regs\fR" 4 +.IX Item "-mno-space-regs" +Generate code that assumes the target has no space registers. This allows +\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes. +.Sp +Such code is suitable for level 0 \s-1PA\s0 systems and kernels. +.IP "\fB\-mfast\-indirect\-calls\fR" 4 +.IX Item "-mfast-indirect-calls" +Generate code that assumes calls never cross space boundaries. This +allows \s-1GCC\s0 to emit code that performs faster indirect calls. +.Sp +This option does not work in the presence of shared libraries or nested +functions. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mlong\-load\-store\fR" 4 +.IX Item "-mlong-load-store" +Generate 3\-instruction load and store sequences as sometimes required by +the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to +the \s-1HP\s0 compilers. +.IP "\fB\-mportable\-runtime\fR" 4 +.IX Item "-mportable-runtime" +Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems. +.IP "\fB\-mgas\fR" 4 +.IX Item "-mgas" +Enable the use of assembler directives only \s-1GAS\s0 understands. +.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4 +.IX Item "-mschedule=cpu-type" +Schedule code according to the constraints for the machine type +\&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR +\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer +to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the +proper scheduling option for your machine. The default scheduling is +\&\fB8000\fR. +.IP "\fB\-mlinker\-opt\fR" 4 +.IX Item "-mlinker-opt" +Enable the optimization pass in the HP-UX linker. Note this makes symbolic +debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 +linkers in which they give bogus error messages when linking some programs. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-msio\fR" 4 +.IX Item "-msio" +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO.\s0 The default is +\&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO.\s0 These +options are available under HP-UX and HI-UX. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +Use options specific to \s-1GNU\s0 \fBld\fR. +This passes \fB\-shared\fR to \fBld\fR when +building a shared library. It is the default when \s-1GCC\s0 is configured, +explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not +affect which \fBld\fR is called; it only changes what parameters +are passed to that \fBld\fR. +The \fBld\fR that is called is determined by the +\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and +finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed +using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available +on the 64\-bit HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mhp\-ld\fR" 4 +.IX Item "-mhp-ld" +Use options specific to \s-1HP\s0 \fBld\fR. +This passes \fB\-b\fR to \fBld\fR when building +a shared library and passes \fB+Accept TypeMismatch\fR to \fBld\fR on all +links. It is the default when \s-1GCC\s0 is configured, explicitly or +implicitly, with the \s-1HP\s0 linker. This option does not affect +which \fBld\fR is called; it only changes what parameters are passed to that +\&\fBld\fR. +The \fBld\fR that is called is determined by the \fB\-\-with\-ld\fR +configure option, \s-1GCC\s0's program search path, and finally by the user's +\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich +`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit +HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Generate code that uses long call sequences. This ensures that a call +is always able to reach linker generated stubs. The default is to generate +long calls only when the distance from the call site to the beginning +of the function or translation unit, as the case may be, exceeds a +predefined limit set by the branch type being used. The limits for +normal calls are 7,600,000 and 240,000 bytes, respectively for the +\&\s-1PA 2.0\s0 and \s-1PA 1.X\s0 architectures. Sibcalls are always limited at +240,000 bytes. +.Sp +Distances are measured from the beginning of functions when using the +\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR +and \fB\-mno\-portable\-runtime\fR options together under HP-UX with +the \s-1SOM\s0 linker. +.Sp +It is normally not desirable to use this option as it degrades +performance. However, it may be useful in large applications, +particularly when partial linking is used to build the application. +.Sp +The types of long calls used depends on the capabilities of the +assembler and linker, and the type of code being generated. The +impact on systems that support long absolute calls, and long pic +symbol-difference or pc-relative calls should be relatively small. +However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code +and it is quite long. +.IP "\fB\-munix=\fR\fIunix-std\fR" 4 +.IX Item "-munix=unix-std" +Generate compiler predefines and select a startfile for the specified +\&\s-1UNIX\s0 standard. The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR +and \fB98\fR. \fB93\fR is supported on all HP-UX versions. \fB95\fR +is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX +11.11 and later. The default values are \fB93\fR for HP-UX 10.00, +\&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 +and later. +.Sp +\&\fB\-munix=93\fR provides the same predefines as \s-1GCC 3.3\s0 and 3.4. +\&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR +and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. +\&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, +\&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and +\&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR. +.Sp +It is \fIimportant\fR to note that this option changes the interfaces +for various library routines. It also affects the operational behavior +of the C library. Thus, \fIextreme\fR care is needed in using this +option. +.Sp +Library code that is intended to operate with more than one \s-1UNIX\s0 +standard must test, set and restore the variable \f(CW\*(C`_\|_xpg4_extended_mask\*(C'\fR +as appropriate. Most \s-1GNU\s0 software doesn't provide this capability. +.IP "\fB\-nolibdld\fR" 4 +.IX Item "-nolibdld" +Suppress the generation of link options to search libdld.sl when the +\&\fB\-static\fR option is specified on HP-UX 10 and later. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +The HP-UX implementation of setlocale in libc has a dependency on +libdld.sl. There isn't an archive version of libdld.sl. Thus, +when the \fB\-static\fR option is specified, special link options +are needed to resolve this dependency. +.Sp +On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to +link with libdld.sl when the \fB\-static\fR option is specified. +This causes the resulting binary to be dynamic. On the 64\-bit port, +the linkers generate dynamic binaries by default in any case. The +\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from +adding these link options. +.IP "\fB\-threads\fR" 4 +.IX Item "-threads" +Add support for multithreading with the \fIdce thread\fR library +under HP-UX. This option sets flags for both the preprocessor and +linker. +.PP +\fI\s-1IA\-64\s0 Options\fR +.IX Subsection "IA-64 Options" +.PP +These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. This is the default for HP-UX. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. This is the default for \s-1AIX5\s0 +and GNU/Linux. +.IP "\fB\-mgnu\-as\fR" 4 +.IX Item "-mgnu-as" +.PD 0 +.IP "\fB\-mno\-gnu\-as\fR" 4 +.IX Item "-mno-gnu-as" +.PD +Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +.PD 0 +.IP "\fB\-mno\-gnu\-ld\fR" 4 +.IX Item "-mno-gnu-ld" +.PD +Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. +.IP "\fB\-mno\-pic\fR" 4 +.IX Item "-mno-pic" +Generate code that does not use a global pointer register. The result +is not position independent code, and violates the \s-1IA\-64 ABI.\s0 +.IP "\fB\-mvolatile\-asm\-stop\fR" 4 +.IX Item "-mvolatile-asm-stop" +.PD 0 +.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 +.IX Item "-mno-volatile-asm-stop" +.PD +Generate (or don't) a stop bit immediately before and after volatile asm +statements. +.IP "\fB\-mregister\-names\fR" 4 +.IX Item "-mregister-names" +.PD 0 +.IP "\fB\-mno\-register\-names\fR" 4 +.IX Item "-mno-register-names" +.PD +Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for +the stacked registers. This may make assembler output more readable. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +Disable (or enable) optimizations that use the small data section. This may +be useful for working around optimizer bugs. +.IP "\fB\-mconstant\-gp\fR" 4 +.IX Item "-mconstant-gp" +Generate code that uses a single constant global pointer value. This is +useful when compiling kernel code. +.IP "\fB\-mauto\-pic\fR" 4 +.IX Item "-mauto-pic" +Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. +This is useful when compiling firmware code. +.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 +.IX Item "-minline-float-divide-min-latency" +Generate code for inline divides of floating-point values +using the minimum latency algorithm. +.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-float-divide-max-throughput" +Generate code for inline divides of floating-point values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-float\-divide\fR" 4 +.IX Item "-mno-inline-float-divide" +Do not generate inline code for divides of floating-point values. +.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 +.IX Item "-minline-int-divide-min-latency" +Generate code for inline divides of integer values +using the minimum latency algorithm. +.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-int-divide-max-throughput" +Generate code for inline divides of integer values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-int\-divide\fR" 4 +.IX Item "-mno-inline-int-divide" +Do not generate inline code for divides of integer values. +.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 +.IX Item "-minline-sqrt-min-latency" +Generate code for inline square roots +using the minimum latency algorithm. +.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 +.IX Item "-minline-sqrt-max-throughput" +Generate code for inline square roots +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-sqrt\fR" 4 +.IX Item "-mno-inline-sqrt" +Do not generate inline code for \f(CW\*(C`sqrt\*(C'\fR. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mno\-dwarf2\-asm\fR" 4 +.IX Item "-mno-dwarf2-asm" +.PD 0 +.IP "\fB\-mdwarf2\-asm\fR" 4 +.IX Item "-mdwarf2-asm" +.PD +Don't (or do) generate assembler code for the \s-1DWARF\s0 line number debugging +info. This may be useful when not using the \s-1GNU\s0 assembler. +.IP "\fB\-mearly\-stop\-bits\fR" 4 +.IX Item "-mearly-stop-bits" +.PD 0 +.IP "\fB\-mno\-early\-stop\-bits\fR" 4 +.IX Item "-mno-early-stop-bits" +.PD +Allow stop bits to be placed earlier than immediately preceding the +instruction that triggered the stop bit. This can improve instruction +scheduling, but does not always do so. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 +.IX Item "-mtls-size=tls-size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and +64. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune the instruction scheduling for a particular \s-1CPU,\s0 Valid values are +\&\fBitanium\fR, \fBitanium1\fR, \fBmerced\fR, \fBitanium2\fR, +and \fBmckinley\fR. +.IP "\fB\-milp32\fR" 4 +.IX Item "-milp32" +.PD 0 +.IP "\fB\-mlp64\fR" 4 +.IX Item "-mlp64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. These are HP-UX specific flags. +.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-data-spec" +.PD 0 +.IP "\fB\-msched\-br\-data\-spec\fR" 4 +.IX Item "-msched-br-data-spec" +.PD +(Dis/En)able data speculative scheduling before reload. +This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and +the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). +The default setting is disabled. +.IP "\fB\-msched\-ar\-data\-spec\fR" 4 +.IX Item "-msched-ar-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-data-spec" +.PD +(En/Dis)able data speculative scheduling after reload. +This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and +the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). +The default setting is enabled. +.IP "\fB\-mno\-sched\-control\-spec\fR" 4 +.IX Item "-mno-sched-control-spec" +.PD 0 +.IP "\fB\-msched\-control\-spec\fR" 4 +.IX Item "-msched-control-spec" +.PD +(Dis/En)able control speculative scheduling. This feature is +available only during region scheduling (i.e. before reload). +This results in generation of the \f(CW\*(C`ld.s\*(C'\fR instructions and +the corresponding check instructions \f(CW\*(C`chk.s\*(C'\fR. +The default setting is disabled. +.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 +.IX Item "-msched-br-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads before reload. +This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. +The default setting is enabled. +.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-msched-ar-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads after reload. +This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled. +The default setting is enabled. +.IP "\fB\-msched\-in\-control\-spec\fR" 4 +.IX Item "-msched-in-control-spec" +.PD 0 +.IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4 +.IX Item "-mno-sched-in-control-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the control speculative loads. +This is effective only with \fB\-msched\-control\-spec\fR enabled. +The default setting is enabled. +.IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-data-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-data-spec-insns" +.PD +If enabled, data-speculative instructions are chosen for schedule +only if there are no other choices at the moment. This makes +the use of the data speculation much more conservative. +The default setting is disabled. +.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-control-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-control-spec-insns" +.PD +If enabled, control-speculative instructions are chosen for schedule +only if there are no other choices at the moment. This makes +the use of the control speculation much more conservative. +The default setting is disabled. +.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-mno-sched-count-spec-in-critical-path" +.PD 0 +.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-msched-count-spec-in-critical-path" +.PD +If enabled, speculative dependencies are considered during +computation of the instructions priorities. This makes the use of the +speculation a bit more conservative. +The default setting is disabled. +.IP "\fB\-msched\-spec\-ldc\fR" 4 +.IX Item "-msched-spec-ldc" +Use a simple data speculation check. This option is on by default. +.IP "\fB\-msched\-control\-spec\-ldc\fR" 4 +.IX Item "-msched-control-spec-ldc" +Use a simple check for control speculation. This option is on by default. +.IP "\fB\-msched\-stop\-bits\-after\-every\-cycle\fR" 4 +.IX Item "-msched-stop-bits-after-every-cycle" +Place a stop bit after every cycle when scheduling. This option is on +by default. +.IP "\fB\-msched\-fp\-mem\-deps\-zero\-cost\fR" 4 +.IX Item "-msched-fp-mem-deps-zero-cost" +Assume that floating-point stores and loads are not likely to cause a conflict +when placed into the same instruction group. This option is disabled by +default. +.IP "\fB\-msel\-sched\-dont\-check\-control\-spec\fR" 4 +.IX Item "-msel-sched-dont-check-control-spec" +Generate checks for control speculation in selective scheduling. +This flag is disabled by default. +.IP "\fB\-msched\-max\-memory\-insns=\fR\fImax-insns\fR" 4 +.IX Item "-msched-max-memory-insns=max-insns" +Limit on the number of memory insns per instruction group, giving lower +priority to subsequent memory insns attempting to schedule in the same +instruction group. Frequently useful to prevent cache bank conflicts. +The default value is 1. +.IP "\fB\-msched\-max\-memory\-insns\-hard\-limit\fR" 4 +.IX Item "-msched-max-memory-insns-hard-limit" +Makes the limit specified by \fBmsched-max-memory-insns\fR a hard limit, +disallowing more than that number in an instruction group. +Otherwise, the limit is \*(L"soft\*(R", meaning that non-memory operations +are preferred when the limit is reached, but memory operations may still +be scheduled. +.PP +\fI\s-1LM32\s0 Options\fR +.IX Subsection "LM32 Options" +.PP +These \fB\-m\fR options are defined for the LatticeMico32 architecture: +.IP "\fB\-mbarrel\-shift\-enabled\fR" 4 +.IX Item "-mbarrel-shift-enabled" +Enable barrel-shift instructions. +.IP "\fB\-mdivide\-enabled\fR" 4 +.IX Item "-mdivide-enabled" +Enable divide and modulus instructions. +.IP "\fB\-mmultiply\-enabled\fR" 4 +.IX Item "-mmultiply-enabled" +Enable multiply instructions. +.IP "\fB\-msign\-extend\-enabled\fR" 4 +.IX Item "-msign-extend-enabled" +Enable sign extend instructions. +.IP "\fB\-muser\-enabled\fR" 4 +.IX Item "-muser-enabled" +Enable user-defined instructions. +.PP +\fIM32C Options\fR +.IX Subsection "M32C Options" +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Select the \s-1CPU\s0 for which code is generated. \fIname\fR may be one of +\&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to +/60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for +the M32C/80 series. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +an alternate runtime library to be linked in which supports, for +example, file I/O. You must not use this option when generating +programs that will run on real hardware; you must provide your own +runtime library for whatever I/O functions are needed. +.IP "\fB\-memregs=\fR\fInumber\fR" 4 +.IX Item "-memregs=number" +Specifies the number of memory-based pseudo-registers \s-1GCC\s0 uses +during code generation. These pseudo-registers are used like real +registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the +code into available registers, and the performance penalty of using +memory instead of registers. Note that all modules in a program must +be compiled with the same value for this option. Because of that, you +must not use this option with \s-1GCC\s0's default runtime libraries. +.PP +\fIM32R/D Options\fR +.IX Subsection "M32R/D Options" +.PP +These \fB\-m\fR options are defined for Renesas M32R/D architectures: +.IP "\fB\-m32r2\fR" 4 +.IX Item "-m32r2" +Generate code for the M32R/2. +.IP "\fB\-m32rx\fR" 4 +.IX Item "-m32rx" +Generate code for the M32R/X. +.IP "\fB\-m32r\fR" 4 +.IX Item "-m32r" +Generate code for the M32R. This is the default. +.IP "\fB\-mmodel=small\fR" 4 +.IX Item "-mmodel=small" +Assume all objects live in the lower 16MB of memory (so that their addresses +can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines +are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +This is the default. +.Sp +The addressability of a particular object can be set with the +\&\f(CW\*(C`model\*(C'\fR attribute. +.IP "\fB\-mmodel=medium\fR" 4 +.IX Item "-mmodel=medium" +Assume objects may be anywhere in the 32\-bit address space (the compiler +generates \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +.IP "\fB\-mmodel=large\fR" 4 +.IX Item "-mmodel=large" +Assume objects may be anywhere in the 32\-bit address space (the compiler +generates \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction +(the compiler generates the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR +instruction sequence). +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +Disable use of the small data area. Variables are put into +one of \f(CW\*(C`.data\*(C'\fR, \f(CW\*(C`.bss\*(C'\fR, or \f(CW\*(C`.rodata\*(C'\fR (unless the +\&\f(CW\*(C`section\*(C'\fR attribute has been specified). +This is the default. +.Sp +The small data area consists of sections \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR. +Objects may be explicitly put in the small data area with the +\&\f(CW\*(C`section\*(C'\fR attribute using one of these sections. +.IP "\fB\-msdata=sdata\fR" 4 +.IX Item "-msdata=sdata" +Put small global and static data in the small data area, but do not +generate special code to reference them. +.IP "\fB\-msdata=use\fR" 4 +.IX Item "-msdata=use" +Put small global and static data in the small data area, and generate +special instructions to reference them. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put global and static objects less than or equal to \fInum\fR bytes +into the small data or \s-1BSS\s0 sections instead of the normal data or \s-1BSS\s0 +sections. The default value of \fInum\fR is 8. +The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR +for this option to have any effect. +.Sp +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +Compiling with different values of \fInum\fR may or may not work; if it +doesn't the linker gives an error message\-\-\-incorrect code is not +generated. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +Makes the M32R\-specific code in the compiler display some statistics +that might help in debugging programs. +.IP "\fB\-malign\-loops\fR" 4 +.IX Item "-malign-loops" +Align all loops to a 32\-byte boundary. +.IP "\fB\-mno\-align\-loops\fR" 4 +.IX Item "-mno-align-loops" +Do not enforce a 32\-byte alignment for loops. This is the default. +.IP "\fB\-missue\-rate=\fR\fInumber\fR" 4 +.IX Item "-missue-rate=number" +Issue \fInumber\fR instructions per cycle. \fInumber\fR can only be 1 +or 2. +.IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4 +.IX Item "-mbranch-cost=number" +\&\fInumber\fR can only be 1 or 2. If it is 1 then branches are +preferred over conditional code, if it is 2, then the opposite applies. +.IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4 +.IX Item "-mflush-trap=number" +Specifies the trap number to use to flush the cache. The default is +12. Valid numbers are between 0 and 15 inclusive. +.IP "\fB\-mno\-flush\-trap\fR" 4 +.IX Item "-mno-flush-trap" +Specifies that the cache cannot be flushed by using a trap. +.IP "\fB\-mflush\-func=\fR\fIname\fR" 4 +.IX Item "-mflush-func=name" +Specifies the name of the operating system function to call to flush +the cache. The default is \fB_flush_cache\fR, but a function call +is only used if a trap is not available. +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +Indicates that there is no \s-1OS\s0 function for flushing the cache. +.PP +\fIM680x0 Options\fR +.IX Subsection "M680x0 Options" +.PP +These are the \fB\-m\fR options defined for M680x0 and ColdFire processors. +The default settings depend on which architecture was selected when +the compiler was configured; the defaults for the most common choices +are given below. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code for a specific M680x0 or ColdFire instruction set +architecture. Permissible values of \fIarch\fR for M680x0 +architectures are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR and \fBcpu32\fR. ColdFire +architectures are selected according to Freescale's \s-1ISA\s0 classification +and the permissible values are: \fBisaa\fR, \fBisaaplus\fR, +\&\fBisab\fR and \fBisac\fR. +.Sp +\&\s-1GCC\s0 defines a macro \f(CW\*(C`_\|_mcf\f(CIarch\f(CW_\|_\*(C'\fR whenever it is generating +code for a ColdFire target. The \fIarch\fR in this macro is one of the +\&\fB\-march\fR arguments given above. +.Sp +When used together, \fB\-march\fR and \fB\-mtune\fR select code +that runs on a family of similar processors but that is optimized +for a particular microarchitecture. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Generate code for a specific M680x0 or ColdFire processor. +The M680x0 \fIcpu\fRs are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR, \fB68302\fR, \fB68332\fR +and \fBcpu32\fR. The ColdFire \fIcpu\fRs are given by the table +below, which also classifies the CPUs into families: +.RS 4 +.IP "Family : \fB\-mcpu\fR arguments" 4 +.IX Item "Family : -mcpu arguments" +.PD 0 +.IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51ag\fR \fB51cn\fR \fB51em\fR \fB51je\fR \fB51jf\fR \fB51jg\fR \fB51jm\fR \fB51mm\fR \fB51qe\fR \fB51qm\fR" 4 +.IX Item "51 : 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm" +.IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4 +.IX Item "5206 : 5202 5204 5206" +.IP "\fB5206e\fR : \fB5206e\fR" 4 +.IX Item "5206e : 5206e" +.IP "\fB5208\fR : \fB5207\fR \fB5208\fR" 4 +.IX Item "5208 : 5207 5208" +.IP "\fB5211a\fR : \fB5210a\fR \fB5211a\fR" 4 +.IX Item "5211a : 5210a 5211a" +.IP "\fB5213\fR : \fB5211\fR \fB5212\fR \fB5213\fR" 4 +.IX Item "5213 : 5211 5212 5213" +.IP "\fB5216\fR : \fB5214\fR \fB5216\fR" 4 +.IX Item "5216 : 5214 5216" +.IP "\fB52235\fR : \fB52230\fR \fB52231\fR \fB52232\fR \fB52233\fR \fB52234\fR \fB52235\fR" 4 +.IX Item "52235 : 52230 52231 52232 52233 52234 52235" +.IP "\fB5225\fR : \fB5224\fR \fB5225\fR" 4 +.IX Item "5225 : 5224 5225" +.IP "\fB52259\fR : \fB52252\fR \fB52254\fR \fB52255\fR \fB52256\fR \fB52258\fR \fB52259\fR" 4 +.IX Item "52259 : 52252 52254 52255 52256 52258 52259" +.IP "\fB5235\fR : \fB5232\fR \fB5233\fR \fB5234\fR \fB5235\fR \fB523x\fR" 4 +.IX Item "5235 : 5232 5233 5234 5235 523x" +.IP "\fB5249\fR : \fB5249\fR" 4 +.IX Item "5249 : 5249" +.IP "\fB5250\fR : \fB5250\fR" 4 +.IX Item "5250 : 5250" +.IP "\fB5271\fR : \fB5270\fR \fB5271\fR" 4 +.IX Item "5271 : 5270 5271" +.IP "\fB5272\fR : \fB5272\fR" 4 +.IX Item "5272 : 5272" +.IP "\fB5275\fR : \fB5274\fR \fB5275\fR" 4 +.IX Item "5275 : 5274 5275" +.IP "\fB5282\fR : \fB5280\fR \fB5281\fR \fB5282\fR \fB528x\fR" 4 +.IX Item "5282 : 5280 5281 5282 528x" +.IP "\fB53017\fR : \fB53011\fR \fB53012\fR \fB53013\fR \fB53014\fR \fB53015\fR \fB53016\fR \fB53017\fR" 4 +.IX Item "53017 : 53011 53012 53013 53014 53015 53016 53017" +.IP "\fB5307\fR : \fB5307\fR" 4 +.IX Item "5307 : 5307" +.IP "\fB5329\fR : \fB5327\fR \fB5328\fR \fB5329\fR \fB532x\fR" 4 +.IX Item "5329 : 5327 5328 5329 532x" +.IP "\fB5373\fR : \fB5372\fR \fB5373\fR \fB537x\fR" 4 +.IX Item "5373 : 5372 5373 537x" +.IP "\fB5407\fR : \fB5407\fR" 4 +.IX Item "5407 : 5407" +.IP "\fB5475\fR : \fB5470\fR \fB5471\fR \fB5472\fR \fB5473\fR \fB5474\fR \fB5475\fR \fB547x\fR \fB5480\fR \fB5481\fR \fB5482\fR \fB5483\fR \fB5484\fR \fB5485\fR" 4 +.IX Item "5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485" +.RE +.RS 4 +.PD +.Sp +\&\fB\-mcpu=\fR\fIcpu\fR overrides \fB\-march=\fR\fIarch\fR if +\&\fIarch\fR is compatible with \fIcpu\fR. Other combinations of +\&\fB\-mcpu\fR and \fB\-march\fR are rejected. +.Sp +\&\s-1GCC\s0 defines the macro \f(CW\*(C`_\|_mcf_cpu_\f(CIcpu\f(CW\*(C'\fR when ColdFire target +\&\fIcpu\fR is selected. It also defines \f(CW\*(C`_\|_mcf_family_\f(CIfamily\f(CW\*(C'\fR, +where the value of \fIfamily\fR is given by the table above. +.RE +.IP "\fB\-mtune=\fR\fItune\fR" 4 +.IX Item "-mtune=tune" +Tune the code for a particular microarchitecture within the +constraints set by \fB\-march\fR and \fB\-mcpu\fR. +The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR, +\&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR +and \fBcpu32\fR. The ColdFire microarchitectures +are: \fBcfv1\fR, \fBcfv2\fR, \fBcfv3\fR, \fBcfv4\fR and \fBcfv4e\fR. +.Sp +You can also use \fB\-mtune=68020\-40\fR for code that needs +to run relatively well on 68020, 68030 and 68040 targets. +\&\fB\-mtune=68020\-60\fR is similar but includes 68060 targets +as well. These two options select the same tuning decisions as +\&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively. +.Sp +\&\s-1GCC\s0 defines the macros \f(CW\*(C`_\|_mc\f(CIarch\f(CW\*(C'\fR and \f(CW\*(C`_\|_mc\f(CIarch\f(CW_\|_\*(C'\fR +when tuning for 680x0 architecture \fIarch\fR. It also defines +\&\f(CW\*(C`mc\f(CIarch\f(CW\*(C'\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR +option is used. If \s-1GCC\s0 is tuning for a range of architectures, +as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR, +it defines the macros for every architecture in the range. +.Sp +\&\s-1GCC\s0 also defines the macro \f(CW\*(C`_\|_m\f(CIuarch\f(CW_\|_\*(C'\fR when tuning for +ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one +of the arguments given above. +.IP "\fB\-m68000\fR" 4 +.IX Item "-m68000" +.PD 0 +.IP "\fB\-mc68000\fR" 4 +.IX Item "-mc68000" +.PD +Generate output for a 68000. This is the default +when the compiler is configured for 68000\-based systems. +It is equivalent to \fB\-march=68000\fR. +.Sp +Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core, +including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. +.IP "\fB\-m68010\fR" 4 +.IX Item "-m68010" +Generate output for a 68010. This is the default +when the compiler is configured for 68010\-based systems. +It is equivalent to \fB\-march=68010\fR. +.IP "\fB\-m68020\fR" 4 +.IX Item "-m68020" +.PD 0 +.IP "\fB\-mc68020\fR" 4 +.IX Item "-mc68020" +.PD +Generate output for a 68020. This is the default +when the compiler is configured for 68020\-based systems. +It is equivalent to \fB\-march=68020\fR. +.IP "\fB\-m68030\fR" 4 +.IX Item "-m68030" +Generate output for a 68030. This is the default when the compiler is +configured for 68030\-based systems. It is equivalent to +\&\fB\-march=68030\fR. +.IP "\fB\-m68040\fR" 4 +.IX Item "-m68040" +Generate output for a 68040. This is the default when the compiler is +configured for 68040\-based systems. It is equivalent to +\&\fB\-march=68040\fR. +.Sp +This option inhibits the use of 68881/68882 instructions that have to be +emulated by software on the 68040. Use this option if your 68040 does not +have code to emulate those instructions. +.IP "\fB\-m68060\fR" 4 +.IX Item "-m68060" +Generate output for a 68060. This is the default when the compiler is +configured for 68060\-based systems. It is equivalent to +\&\fB\-march=68060\fR. +.Sp +This option inhibits the use of 68020 and 68881/68882 instructions that +have to be emulated by software on the 68060. Use this option if your 68060 +does not have code to emulate those instructions. +.IP "\fB\-mcpu32\fR" 4 +.IX Item "-mcpu32" +Generate output for a \s-1CPU32.\s0 This is the default +when the compiler is configured for CPU32\-based systems. +It is equivalent to \fB\-march=cpu32\fR. +.Sp +Use this option for microcontrollers with a +\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334, +68336, 68340, 68341, 68349 and 68360. +.IP "\fB\-m5200\fR" 4 +.IX Item "-m5200" +Generate output for a 520X ColdFire \s-1CPU.\s0 This is the default +when the compiler is configured for 520X\-based systems. +It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated +in favor of that option. +.Sp +Use this option for microcontroller with a 5200 core, including +the \s-1MCF5202, MCF5203, MCF5204\s0 and \s-1MCF5206.\s0 +.IP "\fB\-m5206e\fR" 4 +.IX Item "-m5206e" +Generate output for a 5206e ColdFire \s-1CPU.\s0 The option is now +deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. +.IP "\fB\-m528x\fR" 4 +.IX Item "-m528x" +Generate output for a member of the ColdFire 528X family. +The option is now deprecated in favor of the equivalent +\&\fB\-mcpu=528x\fR. +.IP "\fB\-m5307\fR" 4 +.IX Item "-m5307" +Generate output for a ColdFire 5307 \s-1CPU.\s0 The option is now deprecated +in favor of the equivalent \fB\-mcpu=5307\fR. +.IP "\fB\-m5407\fR" 4 +.IX Item "-m5407" +Generate output for a ColdFire 5407 \s-1CPU.\s0 The option is now deprecated +in favor of the equivalent \fB\-mcpu=5407\fR. +.IP "\fB\-mcfv4e\fR" 4 +.IX Item "-mcfv4e" +Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). +This includes use of hardware floating-point instructions. +The option is equivalent to \fB\-mcpu=547x\fR, and is now +deprecated in favor of that option. +.IP "\fB\-m68020\-40\fR" 4 +.IX Item "-m68020-40" +Generate output for a 68040, without using any of the new instructions. +This results in code that can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68040. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-40\fR. +.IP "\fB\-m68020\-60\fR" 4 +.IX Item "-m68020-60" +Generate output for a 68060, without using any of the new instructions. +This results in code that can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68060. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-m68881\fR" 4 +.IX Item "-m68881" +.PD +Generate floating-point instructions. This is the default for 68020 +and above, and for ColdFire devices that have an \s-1FPU.\s0 It defines the +macro \f(CW\*(C`_\|_HAVE_68881_\|_\*(C'\fR on M680x0 targets and \f(CW\*(C`_\|_mcffpu_\|_\*(C'\fR +on ColdFire targets. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not generate floating-point instructions; use library calls instead. +This is the default for 68000, 68010, and 68832 targets. It is also +the default for ColdFire devices that have no \s-1FPU.\s0 +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Generate (do not generate) ColdFire hardware divide and remainder +instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, +the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 +architectures. Otherwise, the default is taken from the target \s-1CPU\s0 +(either the default \s-1CPU,\s0 or the one specified by \fB\-mcpu\fR). For +example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for +\&\fB\-mcpu=5206e\fR. +.Sp +\&\s-1GCC\s0 defines the macro \f(CW\*(C`_\|_mcfhwdiv_\|_\*(C'\fR when this option is enabled. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. +Additionally, parameters passed on the stack are also aligned to a +16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit. +.IP "\fB\-mno\-short\fR" 4 +.IX Item "-mno-short" +Do not consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide. This is the default. +.IP "\fB\-mnobitfield\fR" 4 +.IX Item "-mnobitfield" +.PD 0 +.IP "\fB\-mno\-bitfield\fR" 4 +.IX Item "-mno-bitfield" +.PD +Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR +and \fB\-m5200\fR options imply \fB\-mnobitfield\fR. +.IP "\fB\-mbitfield\fR" 4 +.IX Item "-mbitfield" +Do use the bit-field instructions. The \fB\-m68020\fR option implies +\&\fB\-mbitfield\fR. This is the default if you use a configuration +designed for a 68020. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions +that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR +instruction, which pops their arguments while returning. This +saves one instruction in the caller since there is no need to pop +the arguments there. +.Sp +This calling convention is incompatible with the one normally +used on Unix, so you cannot use it if you need to call libraries +compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code is generated for calls to those +functions. +.Sp +In addition, seriously incorrect code results if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.Sp +The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030, +68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200. +.Sp +The default is \fB\-mno\-rtd\fR. +.IP "\fB\-malign\-int\fR" 4 +.IX Item "-malign-int" +.PD 0 +.IP "\fB\-mno\-align\-int\fR" 4 +.IX Item "-mno-align-int" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR, +\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit +boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR). +Aligning variables on 32\-bit boundaries produces code that runs somewhat +faster on processors with 32\-bit busses at the expense of more memory. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 +aligns structures containing the above types differently than +most published application binary interface specifications for the m68k. +.IP "\fB\-mpcrel\fR" 4 +.IX Item "-mpcrel" +Use the pc-relative addressing mode of the 68000 directly, instead of +using a global offset table. At present, this option implies \fB\-fpic\fR, +allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is +not presently supported with \fB\-mpcrel\fR, though this could be supported for +68020 and higher processors. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +Do not (do) assume that unaligned memory references are handled by +the system. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute-in-place in +an environment without virtual memory management. This option implies +\&\fB\-fPIC\fR. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute-in-place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume ID-based shared libraries are being used. +This is the default. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specifies the identification number of the ID-based shared library being +compiled. Specifying a value of 0 generates more compact code; specifying +other values forces the allocation of that number to the current +library, but is no more space\- or time-efficient than omitting this option. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +When generating position-independent code for ColdFire, generate code +that works if the \s-1GOT\s0 has more than 8192 entries. This code is +larger and slower than code generated without this option. On M680x0 +processors, this option is not needed; \fB\-fPIC\fR suffices. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 +While this is relatively efficient, it only works if the \s-1GOT\s0 +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_68K_GOT16O foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +It should then work with very large GOTs. However, code generated with +\&\fB\-mxgot\fR is less efficient, since it takes 4 instructions to fetch +the value of a global symbol. +.Sp +Note that some linkers, including newer versions of the \s-1GNU\s0 linker, +can create multiple GOTs and sort \s-1GOT\s0 entries. If you have such a linker, +you should only need to use \fB\-mxgot\fR when compiling a single +object file that accesses more than 8192 \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating +position-independent code. +.IP "\fB\-mlong\-jump\-table\-offsets\fR" 4 +.IX Item "-mlong-jump-table-offsets" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.PP +\fIMCore Options\fR +.IX Subsection "MCore Options" +.PP +These are the \fB\-m\fR options defined for the Motorola M*Core +processors. +.IP "\fB\-mhardlit\fR" 4 +.IX Item "-mhardlit" +.PD 0 +.IP "\fB\-mno\-hardlit\fR" 4 +.IX Item "-mno-hardlit" +.PD +Inline constants into the code stream if it can be done in two +instructions or less. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Use the divide instruction. (Enabled by default). +.IP "\fB\-mrelax\-immediate\fR" 4 +.IX Item "-mrelax-immediate" +.PD 0 +.IP "\fB\-mno\-relax\-immediate\fR" 4 +.IX Item "-mno-relax-immediate" +.PD +Allow arbitrary-sized immediates in bit operations. +.IP "\fB\-mwide\-bitfields\fR" 4 +.IX Item "-mwide-bitfields" +.PD 0 +.IP "\fB\-mno\-wide\-bitfields\fR" 4 +.IX Item "-mno-wide-bitfields" +.PD +Always treat bit-fields as \f(CW\*(C`int\*(C'\fR\-sized. +.IP "\fB\-m4byte\-functions\fR" 4 +.IX Item "-m4byte-functions" +.PD 0 +.IP "\fB\-mno\-4byte\-functions\fR" 4 +.IX Item "-mno-4byte-functions" +.PD +Force all functions to be aligned to a 4\-byte boundary. +.IP "\fB\-mcallgraph\-data\fR" 4 +.IX Item "-mcallgraph-data" +.PD 0 +.IP "\fB\-mno\-callgraph\-data\fR" 4 +.IX Item "-mno-callgraph-data" +.PD +Emit callgraph information. +.IP "\fB\-mslow\-bytes\fR" 4 +.IX Item "-mslow-bytes" +.PD 0 +.IP "\fB\-mno\-slow\-bytes\fR" 4 +.IX Item "-mno-slow-bytes" +.PD +Prefer word access when reading byte quantities. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +Generate code for a little-endian target. +.IP "\fB\-m210\fR" 4 +.IX Item "-m210" +.PD 0 +.IP "\fB\-m340\fR" 4 +.IX Item "-m340" +.PD +Generate code for the 210 processor. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that runtime support has been provided and so omit the +simulator library (\fIlibsim.a)\fR from the linker command line. +.IP "\fB\-mstack\-increment=\fR\fIsize\fR" 4 +.IX Item "-mstack-increment=size" +Set the maximum amount for a single stack increment operation. Large +values can increase the speed of programs that contain functions +that need a large amount of stack space, but they can also trigger a +segmentation fault if the stack is extended too much. The default +value is 0x1000. +.PP +\fIMeP Options\fR +.IX Subsection "MeP Options" +.IP "\fB\-mabsdiff\fR" 4 +.IX Item "-mabsdiff" +Enables the \f(CW\*(C`abs\*(C'\fR instruction, which is the absolute difference +between two registers. +.IP "\fB\-mall\-opts\fR" 4 +.IX Item "-mall-opts" +Enables all the optional instructions\-\-\-average, multiply, divide, bit +operations, leading zero, absolute difference, min/max, clip, and +saturation. +.IP "\fB\-maverage\fR" 4 +.IX Item "-maverage" +Enables the \f(CW\*(C`ave\*(C'\fR instruction, which computes the average of two +registers. +.IP "\fB\-mbased=\fR\fIn\fR" 4 +.IX Item "-mbased=n" +Variables of size \fIn\fR bytes or smaller are placed in the +\&\f(CW\*(C`.based\*(C'\fR section by default. Based variables use the \f(CW$tp\fR +register as a base register, and there is a 128\-byte limit to the +\&\f(CW\*(C`.based\*(C'\fR section. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enables the bit operation instructions\-\-\-bit test (\f(CW\*(C`btstm\*(C'\fR), set +(\f(CW\*(C`bsetm\*(C'\fR), clear (\f(CW\*(C`bclrm\*(C'\fR), invert (\f(CW\*(C`bnotm\*(C'\fR), and +test-and-set (\f(CW\*(C`tas\*(C'\fR). +.IP "\fB\-mc=\fR\fIname\fR" 4 +.IX Item "-mc=name" +Selects which section constant data is placed in. \fIname\fR may +be \fBtiny\fR, \fBnear\fR, or \fBfar\fR. +.IP "\fB\-mclip\fR" 4 +.IX Item "-mclip" +Enables the \f(CW\*(C`clip\*(C'\fR instruction. Note that \fB\-mclip\fR is not +useful unless you also provide \fB\-mminmax\fR. +.IP "\fB\-mconfig=\fR\fIname\fR" 4 +.IX Item "-mconfig=name" +Selects one of the built-in core configurations. Each MeP chip has +one or more modules in it; each module has a core \s-1CPU\s0 and a variety of +coprocessors, optional instructions, and peripherals. The +\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC,\s0 provides these +configurations through this option; using this option is the same as +using all the corresponding command-line options. The default +configuration is \fBdefault\fR. +.IP "\fB\-mcop\fR" 4 +.IX Item "-mcop" +Enables the coprocessor instructions. By default, this is a 32\-bit +coprocessor. Note that the coprocessor is normally enabled via the +\&\fB\-mconfig=\fR option. +.IP "\fB\-mcop32\fR" 4 +.IX Item "-mcop32" +Enables the 32\-bit coprocessor's instructions. +.IP "\fB\-mcop64\fR" 4 +.IX Item "-mcop64" +Enables the 64\-bit coprocessor's instructions. +.IP "\fB\-mivc2\fR" 4 +.IX Item "-mivc2" +Enables \s-1IVC2\s0 scheduling. \s-1IVC2\s0 is a 64\-bit \s-1VLIW\s0 coprocessor. +.IP "\fB\-mdc\fR" 4 +.IX Item "-mdc" +Causes constant variables to be placed in the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +Enables the \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions. +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Generate big-endian code. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Generate little-endian code. +.IP "\fB\-mio\-volatile\fR" 4 +.IX Item "-mio-volatile" +Tells the compiler that any variable marked with the \f(CW\*(C`io\*(C'\fR +attribute is to be considered volatile. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Causes variables to be assigned to the \f(CW\*(C`.far\*(C'\fR section by default. +.IP "\fB\-mleadz\fR" 4 +.IX Item "-mleadz" +Enables the \f(CW\*(C`leadz\*(C'\fR (leading zero) instruction. +.IP "\fB\-mm\fR" 4 +.IX Item "-mm" +Causes variables to be assigned to the \f(CW\*(C`.near\*(C'\fR section by default. +.IP "\fB\-mminmax\fR" 4 +.IX Item "-mminmax" +Enables the \f(CW\*(C`min\*(C'\fR and \f(CW\*(C`max\*(C'\fR instructions. +.IP "\fB\-mmult\fR" 4 +.IX Item "-mmult" +Enables the multiplication and multiply-accumulate instructions. +.IP "\fB\-mno\-opts\fR" 4 +.IX Item "-mno-opts" +Disables all the optional instructions enabled by \fB\-mall\-opts\fR. +.IP "\fB\-mrepeat\fR" 4 +.IX Item "-mrepeat" +Enables the \f(CW\*(C`repeat\*(C'\fR and \f(CW\*(C`erepeat\*(C'\fR instructions, used for +low-overhead looping. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Causes all variables to default to the \f(CW\*(C`.tiny\*(C'\fR section. Note +that there is a 65536\-byte limit to this section. Accesses to these +variables use the \f(CW%gp\fR base register. +.IP "\fB\-msatur\fR" 4 +.IX Item "-msatur" +Enables the saturation instructions. Note that the compiler does not +currently generate these itself, but this option is included for +compatibility with other tools, like \f(CW\*(C`as\*(C'\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Link the SDRAM-based runtime instead of the default ROM-based runtime. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Link the simulator run-time libraries. +.IP "\fB\-msimnovec\fR" 4 +.IX Item "-msimnovec" +Link the simulator runtime libraries, excluding built-in support +for reset and exception vectors and tables. +.IP "\fB\-mtf\fR" 4 +.IX Item "-mtf" +Causes all functions to default to the \f(CW\*(C`.far\*(C'\fR section. Without +this option, functions default to the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mtiny=\fR\fIn\fR" 4 +.IX Item "-mtiny=n" +Variables that are \fIn\fR bytes or smaller are allocated to the +\&\f(CW\*(C`.tiny\*(C'\fR section. These variables use the \f(CW$gp\fR base +register. The default for this option is 4, but note that there's a +65536\-byte limit to the \f(CW\*(C`.tiny\*(C'\fR section. +.PP +\fIMicroBlaze Options\fR +.IX Subsection "MicroBlaze Options" +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use software emulation for floating point (default). +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware floating-point instructions. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. +.IP "\fB\-mno\-clearbss\fR" 4 +.IX Item "-mno-clearbss" +This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +Use features of, and schedule code for, the given \s-1CPU.\s0 +Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, +where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and +\&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, +\&\fBv4.00.b\fR, \fBv5.00.a\fR, \fBv5.00.b\fR, \fBv6.00.a\fR. +.IP "\fB\-mxl\-soft\-mul\fR" 4 +.IX Item "-mxl-soft-mul" +Use software multiply emulation (default). +.IP "\fB\-mxl\-soft\-div\fR" 4 +.IX Item "-mxl-soft-div" +Use software emulation for divides (default). +.IP "\fB\-mxl\-barrel\-shift\fR" 4 +.IX Item "-mxl-barrel-shift" +Use the hardware barrel shifter. +.IP "\fB\-mxl\-pattern\-compare\fR" 4 +.IX Item "-mxl-pattern-compare" +Use pattern compare instructions. +.IP "\fB\-msmall\-divides\fR" 4 +.IX Item "-msmall-divides" +Use table lookup optimization for small signed integer divisions. +.IP "\fB\-mxl\-stack\-check\fR" 4 +.IX Item "-mxl-stack-check" +This option is deprecated. Use \fB\-fstack\-check\fR instead. +.IP "\fB\-mxl\-gp\-opt\fR" 4 +.IX Item "-mxl-gp-opt" +Use GP-relative \f(CW\*(C`.sdata\*(C'\fR/\f(CW\*(C`.sbss\*(C'\fR sections. +.IP "\fB\-mxl\-multiply\-high\fR" 4 +.IX Item "-mxl-multiply-high" +Use multiply high instructions for high part of 32x32 multiply. +.IP "\fB\-mxl\-float\-convert\fR" 4 +.IX Item "-mxl-float-convert" +Use hardware floating-point conversion instructions. +.IP "\fB\-mxl\-float\-sqrt\fR" 4 +.IX Item "-mxl-float-sqrt" +Use hardware floating-point square root instruction. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. +.IP "\fB\-mxl\-reorder\fR" 4 +.IX Item "-mxl-reorder" +Use reorder instructions (swap and byte reversed load/store). +.IP "\fB\-mxl\-mode\-\fR\fIapp-model\fR" 4 +.IX Item "-mxl-mode-app-model" +Select application model \fIapp-model\fR. Valid models are +.RS 4 +.IP "\fBexecutable\fR" 4 +.IX Item "executable" +normal executable (default), uses startup code \fIcrt0.o\fR. +.IP "\fB\-mpic\-data\-is\-text\-relative\fR" 4 +.IX Item "-mpic-data-is-text-relative" +Assume that the displacement between the text and data segments is fixed +at static link time. This allows data to be referenced by offset from start of +text address instead of \s-1GOT\s0 since PC-relative addressing is not supported. +.IP "\fBxmdstub\fR" 4 +.IX Item "xmdstub" +for use with Xilinx Microprocessor Debugger (\s-1XMD\s0) based +software intrusive debug agent called xmdstub. This uses startup file +\&\fIcrt1.o\fR and sets the start address of the program to 0x800. +.IP "\fBbootstrap\fR" 4 +.IX Item "bootstrap" +for applications that are loaded using a bootloader. +This model uses startup file \fIcrt2.o\fR which does not contain a processor +reset vector handler. This is suitable for transferring control on a +processor reset to the bootloader rather than the application. +.IP "\fBnovectors\fR" 4 +.IX Item "novectors" +for applications that do not require any of the +MicroBlaze vectors. This option may be useful for applications running +within a monitoring application. This model uses \fIcrt3.o\fR as a startup file. +.RE +.RS 4 +.Sp +Option \fB\-xl\-mode\-\fR\fIapp-model\fR is a deprecated alias for +\&\fB\-mxl\-mode\-\fR\fIapp-model\fR. +.RE +.PP +\fI\s-1MIPS\s0 Options\fR +.IX Subsection "MIPS Options" +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Generate big-endian code. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR +configurations. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code that runs on \fIarch\fR, which can be the name of a +generic \s-1MIPS ISA,\s0 or the name of a particular processor. +The \s-1ISA\s0 names are: +\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, +\&\fBmips32\fR, \fBmips32r2\fR, \fBmips32r3\fR, \fBmips32r5\fR, +\&\fBmips32r6\fR, \fBmips64\fR, \fBmips64r2\fR, \fBmips64r3\fR, +\&\fBmips64r5\fR and \fBmips64r6\fR. +The processor names are: +\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR, +\&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR, +\&\fB5kc\fR, \fB5kf\fR, +\&\fB20kc\fR, +\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR, +\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR, +\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR, \fB34kn\fR, +\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR, +\&\fB1004kc\fR, \fB1004kf2_1\fR, \fB1004kf1_1\fR, +\&\fBi6400\fR, \fBi6500\fR, +\&\fBinteraptiv\fR, +\&\fBloongson2e\fR, \fBloongson2f\fR, \fBloongson3a\fR, \fBgs464\fR, +\&\fBgs464e\fR, \fBgs264e\fR, +\&\fBm4k\fR, +\&\fBm14k\fR, \fBm14kc\fR, \fBm14ke\fR, \fBm14kec\fR, +\&\fBm5100\fR, \fBm5101\fR, +\&\fBocteon\fR, \fBocteon+\fR, \fBocteon2\fR, \fBocteon3\fR, +\&\fBorion\fR, +\&\fBp5600\fR, \fBp6600\fR, +\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR, +\&\fBr4600\fR, \fBr4650\fR, \fBr4700\fR, \fBr5900\fR, +\&\fBr6000\fR, \fBr8000\fR, +\&\fBrm7000\fR, \fBrm9000\fR, +\&\fBr10000\fR, \fBr12000\fR, \fBr14000\fR, \fBr16000\fR, +\&\fBsb1\fR, +\&\fBsr71000\fR, +\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR, +\&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR, +\&\fBxlr\fR and \fBxlp\fR. +The special value \fBfrom-abi\fR selects the +most compatible architecture for the selected \s-1ABI\s0 (that is, +\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). +.Sp +The native Linux/GNU toolchain also supports the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +In processor names, a final \fB000\fR can be abbreviated as \fBk\fR +(for example, \fB\-march=r2k\fR). Prefixes are optional, and +\&\fBvr\fR may be written \fBr\fR. +.Sp +Names of the form \fIn\fR\fBf2_1\fR refer to processors with +FPUs clocked at half the rate of the core, names of the form +\&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same +rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to +processors with FPUs clocked a ratio of 3:2 with respect to the core. +For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym +for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are +accepted as synonyms for \fIn\fR\fBf1_1\fR. +.Sp +\&\s-1GCC\s0 defines two macros based on the value of this option. The first +is \f(CW\*(C`_MIPS_ARCH\*(C'\fR, which gives the name of target architecture, as +a string. The second has the form \f(CW\*(C`_MIPS_ARCH_\f(CIfoo\f(CW\*(C'\fR, +where \fIfoo\fR is the capitalized value of \f(CW\*(C`_MIPS_ARCH\*(C'\fR. +For example, \fB\-march=r2000\fR sets \f(CW\*(C`_MIPS_ARCH\*(C'\fR +to \f(CW"r2000"\fR and defines the macro \f(CW\*(C`_MIPS_ARCH_R2000\*(C'\fR. +.Sp +Note that the \f(CW\*(C`_MIPS_ARCH\*(C'\fR macro uses the processor names given +above. In other words, it has the full prefix and does not +abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR, +the macro names the resolved architecture (either \f(CW"mips1"\fR or +\&\f(CW"mips3"\fR). It names the default architecture when no +\&\fB\-march\fR option is given. +.IP "\fB\-mtune=\fR\fIarch\fR" 4 +.IX Item "-mtune=arch" +Optimize for \fIarch\fR. Among other things, this option controls +the way instructions are scheduled, and the perceived cost of arithmetic +operations. The list of \fIarch\fR values is the same as for +\&\fB\-march\fR. +.Sp +When this option is not used, \s-1GCC\s0 optimizes for the processor +specified by \fB\-march\fR. By using \fB\-march\fR and +\&\fB\-mtune\fR together, it is possible to generate code that +runs on a family of processors, but optimize the code for one +particular member of that family. +.Sp +\&\fB\-mtune\fR defines the macros \f(CW\*(C`_MIPS_TUNE\*(C'\fR and +\&\f(CW\*(C`_MIPS_TUNE_\f(CIfoo\f(CW\*(C'\fR, which work in the same way as the +\&\fB\-march\fR ones described above. +.IP "\fB\-mips1\fR" 4 +.IX Item "-mips1" +Equivalent to \fB\-march=mips1\fR. +.IP "\fB\-mips2\fR" 4 +.IX Item "-mips2" +Equivalent to \fB\-march=mips2\fR. +.IP "\fB\-mips3\fR" 4 +.IX Item "-mips3" +Equivalent to \fB\-march=mips3\fR. +.IP "\fB\-mips4\fR" 4 +.IX Item "-mips4" +Equivalent to \fB\-march=mips4\fR. +.IP "\fB\-mips32\fR" 4 +.IX Item "-mips32" +Equivalent to \fB\-march=mips32\fR. +.IP "\fB\-mips32r3\fR" 4 +.IX Item "-mips32r3" +Equivalent to \fB\-march=mips32r3\fR. +.IP "\fB\-mips32r5\fR" 4 +.IX Item "-mips32r5" +Equivalent to \fB\-march=mips32r5\fR. +.IP "\fB\-mips32r6\fR" 4 +.IX Item "-mips32r6" +Equivalent to \fB\-march=mips32r6\fR. +.IP "\fB\-mips64\fR" 4 +.IX Item "-mips64" +Equivalent to \fB\-march=mips64\fR. +.IP "\fB\-mips64r2\fR" 4 +.IX Item "-mips64r2" +Equivalent to \fB\-march=mips64r2\fR. +.IP "\fB\-mips64r3\fR" 4 +.IX Item "-mips64r3" +Equivalent to \fB\-march=mips64r3\fR. +.IP "\fB\-mips64r5\fR" 4 +.IX Item "-mips64r5" +Equivalent to \fB\-march=mips64r5\fR. +.IP "\fB\-mips64r6\fR" 4 +.IX Item "-mips64r6" +Equivalent to \fB\-march=mips64r6\fR. +.IP "\fB\-mips16\fR" 4 +.IX Item "-mips16" +.PD 0 +.IP "\fB\-mno\-mips16\fR" 4 +.IX Item "-mno-mips16" +.PD +Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targeting a +\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE.\s0 +.Sp +\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis +by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. +.IP "\fB\-mflip\-mips16\fR" 4 +.IX Item "-mflip-mips16" +Generate \s-1MIPS16\s0 code on alternating functions. This option is provided +for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is +not intended for ordinary use in compiling user code. +.IP "\fB\-minterlink\-compressed\fR" 4 +.IX Item "-minterlink-compressed" +.PD 0 +.IP "\fB\-mno\-interlink\-compressed\fR" 4 +.IX Item "-mno-interlink-compressed" +.PD +Require (do not require) that code using the standard (uncompressed) \s-1MIPS ISA\s0 +be link-compatible with \s-1MIPS16\s0 and microMIPS code, and vice versa. +.Sp +For example, code using the standard \s-1ISA\s0 encoding cannot jump directly +to \s-1MIPS16\s0 or microMIPS code; it must either use a call or an indirect jump. +\&\fB\-minterlink\-compressed\fR therefore disables direct jumps unless \s-1GCC\s0 +knows that the target of the jump is not compressed. +.IP "\fB\-minterlink\-mips16\fR" 4 +.IX Item "-minterlink-mips16" +.PD 0 +.IP "\fB\-mno\-interlink\-mips16\fR" 4 +.IX Item "-mno-interlink-mips16" +.PD +Aliases of \fB\-minterlink\-compressed\fR and +\&\fB\-mno\-interlink\-compressed\fR. These options predate the microMIPS \s-1ASE\s0 +and are retained for backwards compatibility. +.IP "\fB\-mabi=32\fR" 4 +.IX Item "-mabi=32" +.PD 0 +.IP "\fB\-mabi=o64\fR" 4 +.IX Item "-mabi=o64" +.IP "\fB\-mabi=n32\fR" 4 +.IX Item "-mabi=n32" +.IP "\fB\-mabi=64\fR" 4 +.IX Item "-mabi=64" +.IP "\fB\-mabi=eabi\fR" 4 +.IX Item "-mabi=eabi" +.PD +Generate code for the given \s-1ABI.\s0 +.Sp +Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally +generates 64\-bit code when you select a 64\-bit architecture, but you +can use \fB\-mgp32\fR to get 32\-bit code instead. +.Sp +For information about the O64 \s-1ABI,\s0 see +<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. +.Sp +\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers +are 64 rather than 32 bits wide. You can select this combination with +\&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \f(CW\*(C`mthc1\*(C'\fR +and \f(CW\*(C`mfhc1\*(C'\fR instructions and is therefore only supported for +\&\s-1MIPS32R2, MIPS32R3\s0 and \s-1MIPS32R5\s0 processors. +.Sp +The register assignments for arguments and return values remain the +same, but each scalar value is passed in a single 64\-bit register +rather than a pair of 32\-bit registers. For example, scalar +floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a +\&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair. The set of call-saved registers also +remains the same in that the even-numbered double-precision registers +are saved. +.Sp +Two additional variants of the o32 \s-1ABI\s0 are supported to enable +a transition from 32\-bit to 64\-bit registers. These are \s-1FPXX\s0 +(\fB\-mfpxx\fR) and \s-1FP64A\s0 (\fB\-mfp64\fR \fB\-mno\-odd\-spreg\fR). +The \s-1FPXX\s0 extension mandates that all code must execute correctly +when run using 32\-bit or 64\-bit registers. The code can be interlinked +with either \s-1FP32\s0 or \s-1FP64,\s0 but not both. +The \s-1FP64A\s0 extension is similar to the \s-1FP64\s0 extension but forbids the +use of odd-numbered single-precision registers. This can be used +in conjunction with the \f(CW\*(C`FRE\*(C'\fR mode of FPUs in \s-1MIPS32R5\s0 +processors and allows both \s-1FP32\s0 and \s-1FP64A\s0 code to interlink and +run in the same process without changing \s-1FPU\s0 modes. +.IP "\fB\-mabicalls\fR" 4 +.IX Item "-mabicalls" +.PD 0 +.IP "\fB\-mno\-abicalls\fR" 4 +.IX Item "-mno-abicalls" +.PD +Generate (do not generate) code that is suitable for SVR4\-style +dynamic objects. \fB\-mabicalls\fR is the default for SVR4\-based +systems. +.IP "\fB\-mshared\fR" 4 +.IX Item "-mshared" +.PD 0 +.IP "\fB\-mno\-shared\fR" 4 +.IX Item "-mno-shared" +.PD +Generate (do not generate) code that is fully position-independent, +and that can therefore be linked into shared libraries. This option +only affects \fB\-mabicalls\fR. +.Sp +All \fB\-mabicalls\fR code has traditionally been position-independent, +regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR. However, +as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute +accesses for locally-binding symbols. It can also use shorter \s-1GP\s0 +initialization sequences and generate direct calls to locally-defined +functions. This mode is selected by \fB\-mno\-shared\fR. +.Sp +\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates +objects that can only be linked by the \s-1GNU\s0 linker. However, the option +does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0 +of relocatable objects. Using \fB\-mno\-shared\fR generally makes +executables both smaller and quicker. +.Sp +\&\fB\-mshared\fR is the default. +.IP "\fB\-mplt\fR" 4 +.IX Item "-mplt" +.PD 0 +.IP "\fB\-mno\-plt\fR" 4 +.IX Item "-mno-plt" +.PD +Assume (do not assume) that the static and dynamic linkers +support PLTs and copy relocations. This option only affects +\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI,\s0 this option +has no effect without \fB\-msym32\fR. +.Sp +You can make \fB\-mplt\fR the default by configuring +\&\s-1GCC\s0 with \fB\-\-with\-mips\-plt\fR. The default is +\&\fB\-mno\-plt\fR otherwise. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +Lift (do not lift) the usual restrictions on the size of the global +offset table. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 +While this is relatively efficient, it only works if the \s-1GOT\s0 +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_MIPS_GOT16 foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +This works with very large GOTs, although the code is also +less efficient, since it takes three instructions to fetch the +value of a global symbol. +.Sp +Note that some linkers can create multiple GOTs. If you have such a +linker, you should only need to use \fB\-mxgot\fR when a single object +file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating position +independent code. +.IP "\fB\-mgp32\fR" 4 +.IX Item "-mgp32" +Assume that general-purpose registers are 32 bits wide. +.IP "\fB\-mgp64\fR" 4 +.IX Item "-mgp64" +Assume that general-purpose registers are 64 bits wide. +.IP "\fB\-mfp32\fR" 4 +.IX Item "-mfp32" +Assume that floating-point registers are 32 bits wide. +.IP "\fB\-mfp64\fR" 4 +.IX Item "-mfp64" +Assume that floating-point registers are 64 bits wide. +.IP "\fB\-mfpxx\fR" 4 +.IX Item "-mfpxx" +Do not assume the width of floating-point registers. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use floating-point coprocessor instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use floating-point coprocessor instructions. Implement +floating-point calculations using library calls instead. +.IP "\fB\-mno\-float\fR" 4 +.IX Item "-mno-float" +Equivalent to \fB\-msoft\-float\fR, but additionally asserts that the +program being compiled does not perform any floating-point operations. +This option is presently supported only by some bare-metal \s-1MIPS\s0 +configurations, where it may select a special set of libraries +that lack all floating-point support (including, for example, the +floating-point \f(CW\*(C`printf\*(C'\fR formats). +If code compiled with \fB\-mno\-float\fR accidentally contains +floating-point operations, it is likely to suffer a link-time +or run-time failure. +.IP "\fB\-msingle\-float\fR" 4 +.IX Item "-msingle-float" +Assume that the floating-point coprocessor only supports single-precision +operations. +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +Assume that the floating-point coprocessor supports double-precision +operations. This is the default. +.IP "\fB\-modd\-spreg\fR" 4 +.IX Item "-modd-spreg" +.PD 0 +.IP "\fB\-mno\-odd\-spreg\fR" 4 +.IX Item "-mno-odd-spreg" +.PD +Enable the use of odd-numbered single-precision floating-point registers +for the o32 \s-1ABI.\s0 This is the default for processors that are known to +support these registers. When using the o32 \s-1FPXX ABI,\s0 \fB\-mno\-odd\-spreg\fR +is set by default. +.IP "\fB\-mabs=2008\fR" 4 +.IX Item "-mabs=2008" +.PD 0 +.IP "\fB\-mabs=legacy\fR" 4 +.IX Item "-mabs=legacy" +.PD +These options control the treatment of the special not-a-number (NaN) +\&\s-1IEEE 754\s0 floating-point data with the \f(CW\*(C`abs.\f(CIfmt\f(CW\*(C'\fR and +\&\f(CW\*(C`neg.\f(CIfmt\f(CW\*(C'\fR machine instructions. +.Sp +By default or when \fB\-mabs=legacy\fR is used the legacy +treatment is selected. In this case these instructions are considered +arithmetic and avoided where correct operation is required and the +input operand might be a NaN. A longer sequence of instructions that +manipulate the sign bit of floating-point datum manually is used +instead unless the \fB\-ffinite\-math\-only\fR option has also been +specified. +.Sp +The \fB\-mabs=2008\fR option selects the \s-1IEEE 754\-2008\s0 treatment. In +this case these instructions are considered non-arithmetic and therefore +operating correctly in all cases, including in particular where the +input operand is a NaN. These instructions are therefore always used +for the respective operations. +.IP "\fB\-mnan=2008\fR" 4 +.IX Item "-mnan=2008" +.PD 0 +.IP "\fB\-mnan=legacy\fR" 4 +.IX Item "-mnan=legacy" +.PD +These options control the encoding of the special not-a-number (NaN) +\&\s-1IEEE 754\s0 floating-point data. +.Sp +The \fB\-mnan=legacy\fR option selects the legacy encoding. In this +case quiet NaNs (qNaNs) are denoted by the first bit of their trailing +significand field being 0, whereas signaling NaNs (sNaNs) are denoted +by the first bit of their trailing significand field being 1. +.Sp +The \fB\-mnan=2008\fR option selects the \s-1IEEE 754\-2008\s0 encoding. In +this case qNaNs are denoted by the first bit of their trailing +significand field being 1, whereas sNaNs are denoted by the first bit of +their trailing significand field being 0. +.Sp +The default is \fB\-mnan=legacy\fR unless \s-1GCC\s0 has been configured with +\&\fB\-\-with\-nan=2008\fR. +.IP "\fB\-mllsc\fR" 4 +.IX Item "-mllsc" +.PD 0 +.IP "\fB\-mno\-llsc\fR" 4 +.IX Item "-mno-llsc" +.PD +Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to +implement atomic memory built-in functions. When neither option is +specified, \s-1GCC\s0 uses the instructions if the target architecture +supports them. +.Sp +\&\fB\-mllsc\fR is useful if the runtime environment can emulate the +instructions and \fB\-mno\-llsc\fR can be useful when compiling for +nonstandard ISAs. You can make either option the default by +configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR +respectively. \fB\-\-with\-llsc\fR is the default for some +configurations; see the installation documentation for details. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-mno\-dsp\fR" 4 +.IX Item "-mno-dsp" +.PD +Use (do not use) revision 1 of the \s-1MIPS DSP ASE.\s0 + This option defines the +preprocessor macro \f(CW\*(C`_\|_mips_dsp\*(C'\fR. It also defines +\&\f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 1. +.IP "\fB\-mdspr2\fR" 4 +.IX Item "-mdspr2" +.PD 0 +.IP "\fB\-mno\-dspr2\fR" 4 +.IX Item "-mno-dspr2" +.PD +Use (do not use) revision 2 of the \s-1MIPS DSP ASE.\s0 + This option defines the +preprocessor macros \f(CW\*(C`_\|_mips_dsp\*(C'\fR and \f(CW\*(C`_\|_mips_dspr2\*(C'\fR. +It also defines \f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 2. +.IP "\fB\-msmartmips\fR" 4 +.IX Item "-msmartmips" +.PD 0 +.IP "\fB\-mno\-smartmips\fR" 4 +.IX Item "-mno-smartmips" +.PD +Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE.\s0 +.IP "\fB\-mpaired\-single\fR" 4 +.IX Item "-mpaired-single" +.PD 0 +.IP "\fB\-mno\-paired\-single\fR" 4 +.IX Item "-mno-paired-single" +.PD +Use (do not use) paired-single floating-point instructions. + This option requires +hardware floating-point support to be enabled. +.IP "\fB\-mdmx\fR" 4 +.IX Item "-mdmx" +.PD 0 +.IP "\fB\-mno\-mdmx\fR" 4 +.IX Item "-mno-mdmx" +.PD +Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions. +This option can only be used when generating 64\-bit code and requires +hardware floating-point support to be enabled. +.IP "\fB\-mips3d\fR" 4 +.IX Item "-mips3d" +.PD 0 +.IP "\fB\-mno\-mips3d\fR" 4 +.IX Item "-mno-mips3d" +.PD +Use (do not use) the \s-1MIPS\-3D ASE.\s0 +The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. +.IP "\fB\-mmicromips\fR" 4 +.IX Item "-mmicromips" +.PD 0 +.IP "\fB\-mno\-micromips\fR" 4 +.IX Item "-mno-micromips" +.PD +Generate (do not generate) microMIPS code. +.Sp +MicroMIPS code generation can also be controlled on a per-function basis +by means of \f(CW\*(C`micromips\*(C'\fR and \f(CW\*(C`nomicromips\*(C'\fR attributes. +.IP "\fB\-mmt\fR" 4 +.IX Item "-mmt" +.PD 0 +.IP "\fB\-mno\-mt\fR" 4 +.IX Item "-mno-mt" +.PD +Use (do not use) \s-1MT\s0 Multithreading instructions. +.IP "\fB\-mmcu\fR" 4 +.IX Item "-mmcu" +.PD 0 +.IP "\fB\-mno\-mcu\fR" 4 +.IX Item "-mno-mcu" +.PD +Use (do not use) the \s-1MIPS MCU ASE\s0 instructions. +.IP "\fB\-meva\fR" 4 +.IX Item "-meva" +.PD 0 +.IP "\fB\-mno\-eva\fR" 4 +.IX Item "-mno-eva" +.PD +Use (do not use) the \s-1MIPS\s0 Enhanced Virtual Addressing instructions. +.IP "\fB\-mvirt\fR" 4 +.IX Item "-mvirt" +.PD 0 +.IP "\fB\-mno\-virt\fR" 4 +.IX Item "-mno-virt" +.PD +Use (do not use) the \s-1MIPS\s0 Virtualization (\s-1VZ\s0) instructions. +.IP "\fB\-mxpa\fR" 4 +.IX Item "-mxpa" +.PD 0 +.IP "\fB\-mno\-xpa\fR" 4 +.IX Item "-mno-xpa" +.PD +Use (do not use) the \s-1MIPS\s0 eXtended Physical Address (\s-1XPA\s0) instructions. +.IP "\fB\-mcrc\fR" 4 +.IX Item "-mcrc" +.PD 0 +.IP "\fB\-mno\-crc\fR" 4 +.IX Item "-mno-crc" +.PD +Use (do not use) the \s-1MIPS\s0 Cyclic Redundancy Check (\s-1CRC\s0) instructions. +.IP "\fB\-mginv\fR" 4 +.IX Item "-mginv" +.PD 0 +.IP "\fB\-mno\-ginv\fR" 4 +.IX Item "-mno-ginv" +.PD +Use (do not use) the \s-1MIPS\s0 Global INValidate (\s-1GINV\s0) instructions. +.IP "\fB\-mloongson\-mmi\fR" 4 +.IX Item "-mloongson-mmi" +.PD 0 +.IP "\fB\-mno\-loongson\-mmi\fR" 4 +.IX Item "-mno-loongson-mmi" +.PD +Use (do not use) the \s-1MIPS\s0 Loongson MultiMedia extensions Instructions (\s-1MMI\s0). +.IP "\fB\-mloongson\-ext\fR" 4 +.IX Item "-mloongson-ext" +.PD 0 +.IP "\fB\-mno\-loongson\-ext\fR" 4 +.IX Item "-mno-loongson-ext" +.PD +Use (do not use) the \s-1MIPS\s0 Loongson EXTensions (\s-1EXT\s0) instructions. +.IP "\fB\-mloongson\-ext2\fR" 4 +.IX Item "-mloongson-ext2" +.PD 0 +.IP "\fB\-mno\-loongson\-ext2\fR" 4 +.IX Item "-mno-loongson-ext2" +.PD +Use (do not use) the \s-1MIPS\s0 Loongson EXTensions r2 (\s-1EXT2\s0) instructions. +.IP "\fB\-mlong64\fR" 4 +.IX Item "-mlong64" +Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for +an explanation of the default and the way that the pointer size is +determined. +.IP "\fB\-mlong32\fR" 4 +.IX Item "-mlong32" +Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. +.Sp +The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on +the \s-1ABI.\s0 All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use +32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, +or the same size as integer registers, whichever is smaller. +.IP "\fB\-msym32\fR" 4 +.IX Item "-msym32" +.PD 0 +.IP "\fB\-mno\-sym32\fR" 4 +.IX Item "-mno-sym32" +.PD +Assume (do not assume) that all symbols have 32\-bit values, regardless +of the selected \s-1ABI.\s0 This option is useful in combination with +\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 +to generate shorter and faster references to symbolic addresses. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put definitions of externally-visible data in a small data section +if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then generate +more efficient accesses to the data; see \fB\-mgpopt\fR for details. +.Sp +The default \fB\-G\fR option depends on the configuration. +.IP "\fB\-mlocal\-sdata\fR" 4 +.IX Item "-mlocal-sdata" +.PD 0 +.IP "\fB\-mno\-local\-sdata\fR" 4 +.IX Item "-mno-local-sdata" +.PD +Extend (do not extend) the \fB\-G\fR behavior to local data too, +such as to static variables in C. \fB\-mlocal\-sdata\fR is the +default for all configurations. +.Sp +If the linker complains that an application is using too much small data, +you might want to try rebuilding the less performance-critical parts with +\&\fB\-mno\-local\-sdata\fR. You might also want to build large +libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave +more room for the main program. +.IP "\fB\-mextern\-sdata\fR" 4 +.IX Item "-mextern-sdata" +.PD 0 +.IP "\fB\-mno\-extern\-sdata\fR" 4 +.IX Item "-mno-extern-sdata" +.PD +Assume (do not assume) that externally-defined data is in +a small data section if the size of that data is within the \fB\-G\fR limit. +\&\fB\-mextern\-sdata\fR is the default for all configurations. +.Sp +If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR +\&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR +that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR +is placed in a small data section. If \fIVar\fR is defined by another +module, you must either compile that module with a high-enough +\&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's +definition. If \fIVar\fR is common, you must link the application +with a high-enough \fB\-G\fR setting. +.Sp +The easiest way of satisfying these restrictions is to compile +and link every module with the same \fB\-G\fR option. However, +you may wish to build a library that supports several different +small data limits. You can do this by compiling the library with +the highest supported \fB\-G\fR setting and additionally using +\&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions +about externally-defined data. +.IP "\fB\-mgpopt\fR" 4 +.IX Item "-mgpopt" +.PD 0 +.IP "\fB\-mno\-gpopt\fR" 4 +.IX Item "-mno-gpopt" +.PD +Use (do not use) GP-relative accesses for symbols that are known to be +in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and +\&\fB\-mextern\-sdata\fR. \fB\-mgpopt\fR is the default for all +configurations. +.Sp +\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register +might not hold the value of \f(CW\*(C`_gp\*(C'\fR. For example, if the code is +part of a library that might be used in a boot monitor, programs that +call boot monitor routines pass an unknown value in \f(CW$gp\fR. +(In such situations, the boot monitor itself is usually compiled +with \fB\-G0\fR.) +.Sp +\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and +\&\fB\-mno\-extern\-sdata\fR. +.IP "\fB\-membedded\-data\fR" 4 +.IX Item "-membedded-data" +.PD 0 +.IP "\fB\-mno\-embedded\-data\fR" 4 +.IX Item "-mno-embedded-data" +.PD +Allocate variables to the read-only data section first if possible, then +next in the small data section if possible, otherwise in data. This gives +slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required +when executing, and thus may be preferred for some embedded systems. +.IP "\fB\-muninit\-const\-in\-rodata\fR" 4 +.IX Item "-muninit-const-in-rodata" +.PD 0 +.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4 +.IX Item "-mno-uninit-const-in-rodata" +.PD +Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section. +This option is only meaningful in conjunction with \fB\-membedded\-data\fR. +.IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4 +.IX Item "-mcode-readable=setting" +Specify whether \s-1GCC\s0 may generate code that reads from executable sections. +There are three possible settings: +.RS 4 +.IP "\fB\-mcode\-readable=yes\fR" 4 +.IX Item "-mcode-readable=yes" +Instructions may freely access executable sections. This is the +default setting. +.IP "\fB\-mcode\-readable=pcrel\fR" 4 +.IX Item "-mcode-readable=pcrel" +\&\s-1MIPS16\s0 PC-relative load instructions can access executable sections, +but other instructions must not do so. This option is useful on 4KSc +and 4KSd processors when the code TLBs have the Read Inhibit bit set. +It is also useful on processors that can be configured to have a dual +instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically +redirect PC-relative loads to the instruction \s-1RAM.\s0 +.IP "\fB\-mcode\-readable=no\fR" 4 +.IX Item "-mcode-readable=no" +Instructions must not access executable sections. This option can be +useful on targets that are configured to have a dual instruction/data +\&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect +PC-relative loads to the instruction \s-1RAM.\s0 +.RE +.RS 4 +.RE +.IP "\fB\-msplit\-addresses\fR" 4 +.IX Item "-msplit-addresses" +.PD 0 +.IP "\fB\-mno\-split\-addresses\fR" 4 +.IX Item "-mno-split-addresses" +.PD +Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler +relocation operators. This option has been superseded by +\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Use (do not use) assembler relocation operators when dealing with symbolic +addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR, +is to use assembler macros instead. +.Sp +\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured +to use an assembler that supports relocation operators. +.IP "\fB\-mcheck\-zero\-division\fR" 4 +.IX Item "-mcheck-zero-division" +.PD 0 +.IP "\fB\-mno\-check\-zero\-division\fR" 4 +.IX Item "-mno-check-zero-division" +.PD +Trap (do not trap) on integer division by zero. +.Sp +The default is \fB\-mcheck\-zero\-division\fR. +.IP "\fB\-mdivide\-traps\fR" 4 +.IX Item "-mdivide-traps" +.PD 0 +.IP "\fB\-mdivide\-breaks\fR" 4 +.IX Item "-mdivide-breaks" +.PD +\&\s-1MIPS\s0 systems check for division by zero by generating either a +conditional trap or a break instruction. Using traps results in +smaller code, but is only supported on \s-1MIPS II\s0 and later. Also, some +versions of the Linux kernel have a bug that prevents trap from +generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to +allow conditional traps on architectures that support them and +\&\fB\-mdivide\-breaks\fR to force the use of breaks. +.Sp +The default is usually \fB\-mdivide\-traps\fR, but this can be +overridden at configure time using \fB\-\-with\-divide=breaks\fR. +Divide-by-zero checks can be completely disabled using +\&\fB\-mno\-check\-zero\-division\fR. +.IP "\fB\-mload\-store\-pairs\fR" 4 +.IX Item "-mload-store-pairs" +.PD 0 +.IP "\fB\-mno\-load\-store\-pairs\fR" 4 +.IX Item "-mno-load-store-pairs" +.PD +Enable (disable) an optimization that pairs consecutive load or store +instructions to enable load/store bonding. This option is enabled by +default but only takes effect when the selected architecture is known +to support bonding. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +.PD 0 +.IP "\fB\-mno\-memcpy\fR" 4 +.IX Item "-mno-memcpy" +.PD +Force (do not force) the use of \f(CW\*(C`memcpy\*(C'\fR for non-trivial block +moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline +most constant-sized copies. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling +functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller +and callee to be in the same 256 megabyte segment. +.Sp +This option has no effect on abicalls code. The default is +\&\fB\-mno\-long\-calls\fR. +.IP "\fB\-mmad\fR" 4 +.IX Item "-mmad" +.PD 0 +.IP "\fB\-mno\-mad\fR" 4 +.IX Item "-mno-mad" +.PD +Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR +instructions, as provided by the R4650 \s-1ISA.\s0 +.IP "\fB\-mimadd\fR" 4 +.IX Item "-mimadd" +.PD 0 +.IP "\fB\-mno\-imadd\fR" 4 +.IX Item "-mno-imadd" +.PD +Enable (disable) use of the \f(CW\*(C`madd\*(C'\fR and \f(CW\*(C`msub\*(C'\fR integer +instructions. The default is \fB\-mimadd\fR on architectures +that support \f(CW\*(C`madd\*(C'\fR and \f(CW\*(C`msub\*(C'\fR except for the 74k +architecture where it was found to generate slower code. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable (disable) use of the floating-point multiply-accumulate +instructions, when they are available. The default is +\&\fB\-mfused\-madd\fR. +.Sp +On the R8000 \s-1CPU\s0 when multiply-accumulate instructions are used, +the intermediate product is calculated to infinite precision +and is not subject to the \s-1FCSR\s0 Flush to Zero bit. This may be +undesirable in some circumstances. On other processors the result +is numerically identical to the equivalent computation using +separate multiply, add, subtract and negate instructions. +.IP "\fB\-nocpp\fR" 4 +.IX Item "-nocpp" +Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user +assembler files (with a \fB.s\fR suffix) when assembling them. +.IP "\fB\-mfix\-24k\fR" 4 +.IX Item "-mfix-24k" +.PD 0 +.IP "\fB\-mno\-fix\-24k\fR" 4 +.IX Item "-mno-fix-24k" +.PD +Work around the 24K E48 (lost data on stores during refill) errata. +The workarounds are implemented by the assembler rather than by \s-1GCC.\s0 +.IP "\fB\-mfix\-r4000\fR" 4 +.IX Item "-mfix-r4000" +.PD 0 +.IP "\fB\-mno\-fix\-r4000\fR" 4 +.IX Item "-mno-fix-r4000" +.PD +Work around certain R4000 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +while an integer multiplication is in progress. +.IP "\-" 4 +An integer division may give an incorrect result if started in a delay slot +of a taken branch or a jump. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r4400\fR" 4 +.IX Item "-mfix-r4400" +.PD 0 +.IP "\fB\-mno\-fix\-r4400\fR" 4 +.IX Item "-mno-fix-r4400" +.PD +Work around certain R4400 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r10000\fR" 4 +.IX Item "-mfix-r10000" +.PD 0 +.IP "\fB\-mno\-fix\-r10000\fR" 4 +.IX Item "-mno-fix-r10000" +.PD +Work around certain R10000 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`ll\*(C'\fR/\f(CW\*(C`sc\*(C'\fR sequences may not behave atomically on revisions +prior to 3.0. They may deadlock on revisions 2.6 and earlier. +.RE +.RS 4 +.Sp +This option can only be used if the target architecture supports +branch-likely instructions. \fB\-mfix\-r10000\fR is the default when +\&\fB\-march=r10000\fR is used; \fB\-mno\-fix\-r10000\fR is the default +otherwise. +.RE +.IP "\fB\-mfix\-r5900\fR" 4 +.IX Item "-mfix-r5900" +.PD 0 +.IP "\fB\-mno\-fix\-r5900\fR" 4 +.IX Item "-mno-fix-r5900" +.PD +Do not attempt to schedule the preceding instruction into the delay slot +of a branch instruction placed at the end of a short loop of six +instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction there +instead. The short loop bug under certain conditions causes loops to +execute only once or twice, due to a hardware bug in the R5900 chip. The +workaround is implemented by the assembler rather than by \s-1GCC.\s0 +.IP "\fB\-mfix\-rm7000\fR" 4 +.IX Item "-mfix-rm7000" +.PD 0 +.IP "\fB\-mno\-fix\-rm7000\fR" 4 +.IX Item "-mno-fix-rm7000" +.PD +Work around the \s-1RM7000\s0 \f(CW\*(C`dmult\*(C'\fR/\f(CW\*(C`dmultu\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC.\s0 +.IP "\fB\-mfix\-vr4120\fR" 4 +.IX Item "-mfix-vr4120" +.PD 0 +.IP "\fB\-mno\-fix\-vr4120\fR" 4 +.IX Item "-mno-fix-vr4120" +.PD +Work around certain \s-1VR4120\s0 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result. +.IP "\-" 4 +\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one +of the operands is negative. +.RE +.RS 4 +.Sp +The workarounds for the division errata rely on special functions in +\&\fIlibgcc.a\fR. At present, these functions are only provided by +the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations. +.Sp +Other \s-1VR4120\s0 errata require a \s-1NOP\s0 to be inserted between certain pairs of +instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself. +.RE +.IP "\fB\-mfix\-vr4130\fR" 4 +.IX Item "-mfix-vr4130" +Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC,\s0 +although \s-1GCC\s0 avoids using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the +\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +instructions are available instead. +.IP "\fB\-mfix\-sb1\fR" 4 +.IX Item "-mfix-sb1" +.PD 0 +.IP "\fB\-mno\-fix\-sb1\fR" 4 +.IX Item "-mno-fix-sb1" +.PD +Work around certain \s-1SB\-1 CPU\s0 core errata. +(This flag currently works around the \s-1SB\-1\s0 revision 2 +\&\*(L"F1\*(R" and \*(L"F2\*(R" floating-point errata.) +.IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 +.IX Item "-mr10k-cache-barrier=setting" +Specify whether \s-1GCC\s0 should insert cache barriers to avoid the +side effects of speculation on R10K processors. +.Sp +In common with many processors, the R10K tries to predict the outcome +of a conditional branch and speculatively executes instructions from +the \*(L"taken\*(R" branch. It later aborts these instructions if the +predicted outcome is wrong. However, on the R10K, even aborted +instructions can have side effects. +.Sp +This problem only affects kernel stores and, depending on the system, +kernel loads. As an example, a speculatively-executed store may load +the target memory into cache and mark the cache line as dirty, even if +the store itself is later aborted. If a \s-1DMA\s0 operation writes to the +same area of memory before the \*(L"dirty\*(R" line is flushed, the cached +data overwrites the DMA-ed data. See the R10K processor manual +for a full description, including other potential problems. +.Sp +One workaround is to insert cache barrier instructions before every memory +access that might be speculatively executed and that might have side +effects even if aborted. \fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR +controls \s-1GCC\s0's implementation of this workaround. It assumes that +aborted accesses to any byte in the following regions does not have +side effects: +.RS 4 +.IP "1." 4 +.IX Item "1." +the memory occupied by the current function's stack frame; +.IP "2." 4 +.IX Item "2." +the memory occupied by an incoming stack argument; +.IP "3." 4 +.IX Item "3." +the memory occupied by an object with a link-time-constant address. +.RE +.RS 4 +.Sp +It is the kernel's responsibility to ensure that speculative +accesses to these regions are indeed safe. +.Sp +If the input program contains a function declaration such as: +.Sp +.Vb 1 +\& void foo (void); +.Ve +.Sp +then the implementation of \f(CW\*(C`foo\*(C'\fR must allow \f(CW\*(C`j foo\*(C'\fR and +\&\f(CW\*(C`jal foo\*(C'\fR to be executed speculatively. \s-1GCC\s0 honors this +restriction for functions it compiles itself. It expects non-GCC +functions (such as hand-written assembly code) to do the same. +.Sp +The option has three forms: +.IP "\fB\-mr10k\-cache\-barrier=load\-store\fR" 4 +.IX Item "-mr10k-cache-barrier=load-store" +Insert a cache barrier before a load or store that might be +speculatively executed and that might have side effects even +if aborted. +.IP "\fB\-mr10k\-cache\-barrier=store\fR" 4 +.IX Item "-mr10k-cache-barrier=store" +Insert a cache barrier before a store that might be speculatively +executed and that might have side effects even if aborted. +.IP "\fB\-mr10k\-cache\-barrier=none\fR" 4 +.IX Item "-mr10k-cache-barrier=none" +Disable the insertion of cache barriers. This is the default setting. +.RE +.RS 4 +.RE +.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4 +.IX Item "-mflush-func=func" +.PD 0 +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +.PD +Specifies the function to call to flush the I and D caches, or to not +call any such function. If called, the function must take the same +arguments as the common \f(CW\*(C`_flush_func\*(C'\fR, that is, the address of the +memory range for which the cache is being flushed, the size of the +memory range, and the number 3 (to flush both caches). The default +depends on the target \s-1GCC\s0 was configured for, but commonly is either +\&\f(CW\*(C`_flush_func\*(C'\fR or \f(CW\*(C`_\|_cpu_flush\*(C'\fR. +.IP "\fBmbranch\-cost=\fR\fInum\fR" 4 +.IX Item "mbranch-cost=num" +Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. A zero cost redundantly selects +the default, which is based on the \fB\-mtune\fR setting. +.IP "\fB\-mbranch\-likely\fR" 4 +.IX Item "-mbranch-likely" +.PD 0 +.IP "\fB\-mno\-branch\-likely\fR" 4 +.IX Item "-mno-branch-likely" +.PD +Enable or disable use of Branch Likely instructions, regardless of the +default for the selected architecture. By default, Branch Likely +instructions may be generated if they are supported by the selected +architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures +and processors that implement those architectures; for those, Branch +Likely instructions are not be generated by default because the \s-1MIPS32\s0 +and \s-1MIPS64\s0 architectures specifically deprecate their use. +.IP "\fB\-mcompact\-branches=never\fR" 4 +.IX Item "-mcompact-branches=never" +.PD 0 +.IP "\fB\-mcompact\-branches=optimal\fR" 4 +.IX Item "-mcompact-branches=optimal" +.IP "\fB\-mcompact\-branches=always\fR" 4 +.IX Item "-mcompact-branches=always" +.PD +These options control which form of branches will be generated. The +default is \fB\-mcompact\-branches=optimal\fR. +.Sp +The \fB\-mcompact\-branches=never\fR option ensures that compact branch +instructions will never be generated. +.Sp +The \fB\-mcompact\-branches=always\fR option ensures that a compact +branch instruction will be generated if available. If a compact branch +instruction is not available, a delay slot form of the branch will be +used instead. +.Sp +This option is supported from \s-1MIPS\s0 Release 6 onwards. +.Sp +The \fB\-mcompact\-branches=optimal\fR option will cause a delay slot +branch to be used if one is available in the current \s-1ISA\s0 and the delay +slot is successfully filled. If the delay slot is not filled, a compact +branch will be chosen if one is available. +.IP "\fB\-mfp\-exceptions\fR" 4 +.IX Item "-mfp-exceptions" +.PD 0 +.IP "\fB\-mno\-fp\-exceptions\fR" 4 +.IX Item "-mno-fp-exceptions" +.PD +Specifies whether \s-1FP\s0 exceptions are enabled. This affects how +\&\s-1FP\s0 instructions are scheduled for some processors. +The default is that \s-1FP\s0 exceptions are +enabled. +.Sp +For instance, on the \s-1SB\-1,\s0 if \s-1FP\s0 exceptions are disabled, and we are emitting +64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one +\&\s-1FP\s0 pipe. +.IP "\fB\-mvr4130\-align\fR" 4 +.IX Item "-mvr4130-align" +.PD 0 +.IP "\fB\-mno\-vr4130\-align\fR" 4 +.IX Item "-mno-vr4130-align" +.PD +The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two +instructions together if the first one is 8\-byte aligned. When this +option is enabled, \s-1GCC\s0 aligns pairs of instructions that it +thinks should execute in parallel. +.Sp +This option only has an effect when optimizing for the \s-1VR4130.\s0 +It normally makes code faster, but at the expense of making it bigger. +It is enabled by default at optimization level \fB\-O3\fR. +.IP "\fB\-msynci\fR" 4 +.IX Item "-msynci" +.PD 0 +.IP "\fB\-mno\-synci\fR" 4 +.IX Item "-mno-synci" +.PD +Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on +architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if +enabled) are generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache\*(C'\fR is +compiled. +.Sp +This option defaults to \fB\-mno\-synci\fR, but the default can be +overridden by configuring \s-1GCC\s0 with \fB\-\-with\-synci\fR. +.Sp +When compiling code for single processor systems, it is generally safe +to use \f(CW\*(C`synci\*(C'\fR. However, on many multi-core (\s-1SMP\s0) systems, it +does not invalidate the instruction caches on all cores and may lead +to undefined behavior. +.IP "\fB\-mrelax\-pic\-calls\fR" 4 +.IX Item "-mrelax-pic-calls" +.PD 0 +.IP "\fB\-mno\-relax\-pic\-calls\fR" 4 +.IX Item "-mno-relax-pic-calls" +.PD +Try to turn \s-1PIC\s0 calls that are normally dispatched via register +\&\f(CW$25\fR into direct calls. This is only possible if the linker can +resolve the destination at link time and if the destination is within +range for a direct call. +.Sp +\&\fB\-mrelax\-pic\-calls\fR is the default if \s-1GCC\s0 was configured to use +an assembler and a linker that support the \f(CW\*(C`.reloc\*(C'\fR assembly +directive and \fB\-mexplicit\-relocs\fR is in effect. With +\&\fB\-mno\-explicit\-relocs\fR, this optimization can be performed by the +assembler and the linker alone without help from the compiler. +.IP "\fB\-mmcount\-ra\-address\fR" 4 +.IX Item "-mmcount-ra-address" +.PD 0 +.IP "\fB\-mno\-mcount\-ra\-address\fR" 4 +.IX Item "-mno-mcount-ra-address" +.PD +Emit (do not emit) code that allows \f(CW\*(C`_mcount\*(C'\fR to modify the +calling function's return address. When enabled, this option extends +the usual \f(CW\*(C`_mcount\*(C'\fR interface with a new \fIra-address\fR +parameter, which has type \f(CW\*(C`intptr_t *\*(C'\fR and is passed in register +\&\f(CW$12\fR. \f(CW\*(C`_mcount\*(C'\fR can then modify the return address by +doing both of the following: +.RS 4 +.IP "*" 4 +Returning the new address in register \f(CW$31\fR. +.IP "*" 4 +Storing the new address in \f(CW\*(C`*\f(CIra\-address\f(CW\*(C'\fR, +if \fIra-address\fR is nonnull. +.RE +.RS 4 +.Sp +The default is \fB\-mno\-mcount\-ra\-address\fR. +.RE +.IP "\fB\-mframe\-header\-opt\fR" 4 +.IX Item "-mframe-header-opt" +.PD 0 +.IP "\fB\-mno\-frame\-header\-opt\fR" 4 +.IX Item "-mno-frame-header-opt" +.PD +Enable (disable) frame header optimization in the o32 \s-1ABI.\s0 When using the +o32 \s-1ABI,\s0 calling functions will allocate 16 bytes on the stack for the called +function to write out register arguments. When enabled, this optimization +will suppress the allocation of the frame header if it can be determined that +it is unused. +.Sp +This optimization is off by default at all optimization levels. +.IP "\fB\-mlxc1\-sxc1\fR" 4 +.IX Item "-mlxc1-sxc1" +.PD 0 +.IP "\fB\-mno\-lxc1\-sxc1\fR" 4 +.IX Item "-mno-lxc1-sxc1" +.PD +When applicable, enable (disable) the generation of \f(CW\*(C`lwxc1\*(C'\fR, +\&\f(CW\*(C`swxc1\*(C'\fR, \f(CW\*(C`ldxc1\*(C'\fR, \f(CW\*(C`sdxc1\*(C'\fR instructions. Enabled by default. +.IP "\fB\-mmadd4\fR" 4 +.IX Item "-mmadd4" +.PD 0 +.IP "\fB\-mno\-madd4\fR" 4 +.IX Item "-mno-madd4" +.PD +When applicable, enable (disable) the generation of 4\-operand \f(CW\*(C`madd.s\*(C'\fR, +\&\f(CW\*(C`madd.d\*(C'\fR and related instructions. Enabled by default. +.PP +\fI\s-1MMIX\s0 Options\fR +.IX Subsection "MMIX Options" +.PP +These options are defined for the \s-1MMIX:\s0 +.IP "\fB\-mlibfuncs\fR" 4 +.IX Item "-mlibfuncs" +.PD 0 +.IP "\fB\-mno\-libfuncs\fR" 4 +.IX Item "-mno-libfuncs" +.PD +Specify that intrinsic library functions are being compiled, passing all +values in registers, no matter the size. +.IP "\fB\-mepsilon\fR" 4 +.IX Item "-mepsilon" +.PD 0 +.IP "\fB\-mno\-epsilon\fR" 4 +.IX Item "-mno-epsilon" +.PD +Generate floating-point comparison instructions that compare with respect +to the \f(CW\*(C`rE\*(C'\fR epsilon register. +.IP "\fB\-mabi=mmixware\fR" 4 +.IX Item "-mabi=mmixware" +.PD 0 +.IP "\fB\-mabi=gnu\fR" 4 +.IX Item "-mabi=gnu" +.PD +Generate code that passes function parameters and return values that (in +the called function) are seen as registers \f(CW$0\fR and up, as opposed to +the \s-1GNU ABI\s0 which uses global registers \f(CW$231\fR and up. +.IP "\fB\-mzero\-extend\fR" 4 +.IX Item "-mzero-extend" +.PD 0 +.IP "\fB\-mno\-zero\-extend\fR" 4 +.IX Item "-mno-zero-extend" +.PD +When reading data from memory in sizes shorter than 64 bits, use (do not +use) zero-extending load instructions by default, rather than +sign-extending ones. +.IP "\fB\-mknuthdiv\fR" 4 +.IX Item "-mknuthdiv" +.PD 0 +.IP "\fB\-mno\-knuthdiv\fR" 4 +.IX Item "-mno-knuthdiv" +.PD +Make the result of a division yielding a remainder have the same sign as +the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the +remainder follows the sign of the dividend. Both methods are +arithmetically valid, the latter being almost exclusively used. +.IP "\fB\-mtoplevel\-symbols\fR" 4 +.IX Item "-mtoplevel-symbols" +.PD 0 +.IP "\fB\-mno\-toplevel\-symbols\fR" 4 +.IX Item "-mno-toplevel-symbols" +.PD +Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly +code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Generate an executable in the \s-1ELF\s0 format, rather than the default +\&\fBmmo\fR format used by the \fBmmix\fR simulator. +.IP "\fB\-mbranch\-predict\fR" 4 +.IX Item "-mbranch-predict" +.PD 0 +.IP "\fB\-mno\-branch\-predict\fR" 4 +.IX Item "-mno-branch-predict" +.PD +Use (do not use) the probable-branch instructions, when static branch +prediction indicates a probable branch. +.IP "\fB\-mbase\-addresses\fR" 4 +.IX Item "-mbase-addresses" +.PD 0 +.IP "\fB\-mno\-base\-addresses\fR" 4 +.IX Item "-mno-base-addresses" +.PD +Generate (do not generate) code that uses \fIbase addresses\fR. Using a +base address automatically generates a request (handled by the assembler +and the linker) for a constant to be set up in a global register. The +register is used for one or more base address requests within the range 0 +to 255 from the value held in the register. The generally leads to short +and fast code, but the number of different data items that can be +addressed is limited. This means that a program that uses lots of static +data may require \fB\-mno\-base\-addresses\fR. +.IP "\fB\-msingle\-exit\fR" 4 +.IX Item "-msingle-exit" +.PD 0 +.IP "\fB\-mno\-single\-exit\fR" 4 +.IX Item "-mno-single-exit" +.PD +Force (do not force) generated code to have a single exit point in each +function. +.PP +\fI\s-1MN10300\s0 Options\fR +.IX Subsection "MN10300 Options" +.PP +These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures: +.IP "\fB\-mmult\-bug\fR" 4 +.IX Item "-mmult-bug" +Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0 +processors. This is the default. +.IP "\fB\-mno\-mult\-bug\fR" 4 +.IX Item "-mno-mult-bug" +Do not generate code to avoid bugs in the multiply instructions for the +\&\s-1MN10300\s0 processors. +.IP "\fB\-mam33\fR" 4 +.IX Item "-mam33" +Generate code using features specific to the \s-1AM33\s0 processor. +.IP "\fB\-mno\-am33\fR" 4 +.IX Item "-mno-am33" +Do not generate code using features specific to the \s-1AM33\s0 processor. This +is the default. +.IP "\fB\-mam33\-2\fR" 4 +.IX Item "-mam33-2" +Generate code using features specific to the \s-1AM33/2.0\s0 processor. +.IP "\fB\-mam34\fR" 4 +.IX Item "-mam34" +Generate code using features specific to the \s-1AM34\s0 processor. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Use the timing characteristics of the indicated \s-1CPU\s0 type when +scheduling instructions. This does not change the targeted processor +type. The \s-1CPU\s0 type must be one of \fBmn10300\fR, \fBam33\fR, +\&\fBam33\-2\fR or \fBam34\fR. +.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4 +.IX Item "-mreturn-pointer-on-d0" +When generating a function that returns a pointer, return the pointer +in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned +only in \f(CW\*(C`a0\*(C'\fR, and attempts to call such functions without a prototype +result in errors. Note that this option is on by default; use +\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it. +.IP "\fB\-mno\-crt0\fR" 4 +.IX Item "-mno-crt0" +Do not link in the C run-time initialization object file. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Indicate to the linker that it should perform a relaxation optimization pass +to shorten branches, calls and absolute memory addresses. This option only +has an effect when used on the command line for the final link step. +.Sp +This option makes symbolic debugging impossible. +.IP "\fB\-mliw\fR" 4 +.IX Item "-mliw" +Allow the compiler to generate \fILong Instruction Word\fR +instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the +default. This option defines the preprocessor macro \f(CW\*(C`_\|_LIW_\|_\*(C'\fR. +.IP "\fB\-mno\-liw\fR" 4 +.IX Item "-mno-liw" +Do not allow the compiler to generate \fILong Instruction Word\fR +instructions. This option defines the preprocessor macro +\&\f(CW\*(C`_\|_NO_LIW_\|_\*(C'\fR. +.IP "\fB\-msetlb\fR" 4 +.IX Item "-msetlb" +Allow the compiler to generate the \fI\s-1SETLB\s0\fR and \fILcc\fR +instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the +default. This option defines the preprocessor macro \f(CW\*(C`_\|_SETLB_\|_\*(C'\fR. +.IP "\fB\-mno\-setlb\fR" 4 +.IX Item "-mno-setlb" +Do not allow the compiler to generate \fI\s-1SETLB\s0\fR or \fILcc\fR +instructions. This option defines the preprocessor macro +\&\f(CW\*(C`_\|_NO_SETLB_\|_\*(C'\fR. +.PP +\fIMoxie Options\fR +.IX Subsection "Moxie Options" +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Generate big-endian code. This is the default for \fBmoxie\-*\-*\fR +configurations. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Generate little-endian code. +.IP "\fB\-mmul.x\fR" 4 +.IX Item "-mmul.x" +Generate mul.x and umul.x instructions. This is the default for +\&\fBmoxiebox\-*\-*\fR configurations. +.IP "\fB\-mno\-crt0\fR" 4 +.IX Item "-mno-crt0" +Do not link in the C run-time initialization object file. +.PP +\fI\s-1MSP430\s0 Options\fR +.IX Subsection "MSP430 Options" +.PP +These options are defined for the \s-1MSP430:\s0 +.IP "\fB\-masm\-hex\fR" 4 +.IX Item "-masm-hex" +Force assembly output to always use hex constants. Normally such +constants are signed decimals, but this option is available for +testsuite and/or aesthetic purposes. +.IP "\fB\-mmcu=\fR" 4 +.IX Item "-mmcu=" +Select the \s-1MCU\s0 to target. This is used to create a C preprocessor +symbol based upon the \s-1MCU\s0 name, converted to upper case and pre\- and +post-fixed with \fB_\|_\fR. This in turn is used by the +\&\fImsp430.h\fR header file to select an MCU-specific supplementary +header file. +.Sp +The option also sets the \s-1ISA\s0 to use. If the \s-1MCU\s0 name is one that is +known to only support the 430 \s-1ISA\s0 then that is selected, otherwise the +430X \s-1ISA\s0 is selected. A generic \s-1MCU\s0 name of \fBmsp430\fR can also be +used to select the 430 \s-1ISA.\s0 Similarly the generic \fBmsp430x\fR \s-1MCU\s0 +name selects the 430X \s-1ISA.\s0 +.Sp +In addition an MCU-specific linker script is added to the linker +command line. The script's name is the name of the \s-1MCU\s0 with +\&\fI.ld\fR appended. Thus specifying \fB\-mmcu=xxx\fR on the \fBgcc\fR +command line defines the C preprocessor symbol \f(CW\*(C`_\|_XXX_\|_\*(C'\fR and +cause the linker to search for a script called \fIxxx.ld\fR. +.Sp +This option is also passed on to the assembler. +.IP "\fB\-mwarn\-mcu\fR" 4 +.IX Item "-mwarn-mcu" +.PD 0 +.IP "\fB\-mno\-warn\-mcu\fR" 4 +.IX Item "-mno-warn-mcu" +.PD +This option enables or disables warnings about conflicts between the +\&\s-1MCU\s0 name specified by the \fB\-mmcu\fR option and the \s-1ISA\s0 set by the +\&\fB\-mcpu\fR option and/or the hardware multiply support set by the +\&\fB\-mhwmult\fR option. It also toggles warnings about unrecognized +\&\s-1MCU\s0 names. This option is on by default. +.IP "\fB\-mcpu=\fR" 4 +.IX Item "-mcpu=" +Specifies the \s-1ISA\s0 to use. Accepted values are \fBmsp430\fR, +\&\fBmsp430x\fR and \fBmsp430xv2\fR. This option is deprecated. The +\&\fB\-mmcu=\fR option should be used to select the \s-1ISA.\s0 +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Link to the simulator runtime libraries and linker script. Overrides +any scripts that would be selected by the \fB\-mmcu=\fR option. +.IP "\fB\-mlarge\fR" 4 +.IX Item "-mlarge" +Use large-model addressing (20\-bit pointers, 32\-bit \f(CW\*(C`size_t\*(C'\fR). +.IP "\fB\-msmall\fR" 4 +.IX Item "-msmall" +Use small-model addressing (16\-bit pointers, 16\-bit \f(CW\*(C`size_t\*(C'\fR). +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +This option is passed to the assembler and linker, and allows the +linker to perform certain optimizations that cannot be done until +the final link. +.IP "\fBmhwmult=\fR" 4 +.IX Item "mhwmult=" +Describes the type of hardware multiply supported by the target. +Accepted values are \fBnone\fR for no hardware multiply, \fB16bit\fR +for the original 16\-bit\-only multiply supported by early MCUs. +\&\fB32bit\fR for the 16/32\-bit multiply supported by later MCUs and +\&\fBf5series\fR for the 16/32\-bit multiply supported by F5\-series MCUs. +A value of \fBauto\fR can also be given. This tells \s-1GCC\s0 to deduce +the hardware multiply support based upon the \s-1MCU\s0 name provided by the +\&\fB\-mmcu\fR option. If no \fB\-mmcu\fR option is specified or if +the \s-1MCU\s0 name is not recognized then no hardware multiply support is +assumed. \f(CW\*(C`auto\*(C'\fR is the default setting. +.Sp +Hardware multiplies are normally performed by calling a library +routine. This saves space in the generated code. When compiling at +\&\fB\-O3\fR or higher however the hardware multiplier is invoked +inline. This makes for bigger, but faster code. +.Sp +The hardware multiply routines disable interrupts whilst running and +restore the previous interrupt state when they finish. This makes +them safe to use inside interrupt handlers as well as in normal code. +.IP "\fB\-minrt\fR" 4 +.IX Item "-minrt" +Enable the use of a minimum runtime environment \- no static +initializers or constructors. This is intended for memory-constrained +devices. The compiler includes special symbols in some objects +that tell the linker and runtime which code fragments are required. +.IP "\fB\-mcode\-region=\fR" 4 +.IX Item "-mcode-region=" +.PD 0 +.IP "\fB\-mdata\-region=\fR" 4 +.IX Item "-mdata-region=" +.PD +These options tell the compiler where to place functions and data that +do not have one of the \f(CW\*(C`lower\*(C'\fR, \f(CW\*(C`upper\*(C'\fR, \f(CW\*(C`either\*(C'\fR or +\&\f(CW\*(C`section\*(C'\fR attributes. Possible values are \f(CW\*(C`lower\*(C'\fR, +\&\f(CW\*(C`upper\*(C'\fR, \f(CW\*(C`either\*(C'\fR or \f(CW\*(C`any\*(C'\fR. The first three behave +like the corresponding attribute. The fourth possible value \- +\&\f(CW\*(C`any\*(C'\fR \- is the default. It leaves placement entirely up to the +linker script and how it assigns the standard sections +(\f(CW\*(C`.text\*(C'\fR, \f(CW\*(C`.data\*(C'\fR, etc) to the memory regions. +.IP "\fB\-msilicon\-errata=\fR" 4 +.IX Item "-msilicon-errata=" +This option passes on a request to assembler to enable the fixes for +the named silicon errata. +.IP "\fB\-msilicon\-errata\-warn=\fR" 4 +.IX Item "-msilicon-errata-warn=" +This option passes on a request to the assembler to enable warning +messages when a silicon errata might need to be applied. +.PP +\fI\s-1NDS32\s0 Options\fR +.IX Subsection "NDS32 Options" +.PP +These options are defined for \s-1NDS32\s0 implementations: +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code in big-endian mode. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code in little-endian mode. +.IP "\fB\-mreduced\-regs\fR" 4 +.IX Item "-mreduced-regs" +Use reduced-set registers for register allocation. +.IP "\fB\-mfull\-regs\fR" 4 +.IX Item "-mfull-regs" +Use full-set registers for register allocation. +.IP "\fB\-mcmov\fR" 4 +.IX Item "-mcmov" +Generate conditional move instructions. +.IP "\fB\-mno\-cmov\fR" 4 +.IX Item "-mno-cmov" +Do not generate conditional move instructions. +.IP "\fB\-mext\-perf\fR" 4 +.IX Item "-mext-perf" +Generate performance extension instructions. +.IP "\fB\-mno\-ext\-perf\fR" 4 +.IX Item "-mno-ext-perf" +Do not generate performance extension instructions. +.IP "\fB\-mext\-perf2\fR" 4 +.IX Item "-mext-perf2" +Generate performance extension 2 instructions. +.IP "\fB\-mno\-ext\-perf2\fR" 4 +.IX Item "-mno-ext-perf2" +Do not generate performance extension 2 instructions. +.IP "\fB\-mext\-string\fR" 4 +.IX Item "-mext-string" +Generate string extension instructions. +.IP "\fB\-mno\-ext\-string\fR" 4 +.IX Item "-mno-ext-string" +Do not generate string extension instructions. +.IP "\fB\-mv3push\fR" 4 +.IX Item "-mv3push" +Generate v3 push25/pop25 instructions. +.IP "\fB\-mno\-v3push\fR" 4 +.IX Item "-mno-v3push" +Do not generate v3 push25/pop25 instructions. +.IP "\fB\-m16\-bit\fR" 4 +.IX Item "-m16-bit" +Generate 16\-bit instructions. +.IP "\fB\-mno\-16\-bit\fR" 4 +.IX Item "-mno-16-bit" +Do not generate 16\-bit instructions. +.IP "\fB\-misr\-vector\-size=\fR\fInum\fR" 4 +.IX Item "-misr-vector-size=num" +Specify the size of each interrupt vector, which must be 4 or 16. +.IP "\fB\-mcache\-block\-size=\fR\fInum\fR" 4 +.IX Item "-mcache-block-size=num" +Specify the size of each cache block, +which must be a power of 2 between 4 and 512. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Specify the name of the target architecture. +.IP "\fB\-mcmodel=\fR\fIcode-model\fR" 4 +.IX Item "-mcmodel=code-model" +Set the code model to one of +.RS 4 +.IP "\fBsmall\fR" 4 +.IX Item "small" +All the data and read-only data segments must be within 512KB addressing space. +The text segment must be within 16MB addressing space. +.IP "\fBmedium\fR" 4 +.IX Item "medium" +The data segment must be within 512KB while the read-only data segment can be +within 4GB addressing space. The text segment should be still within 16MB +addressing space. +.IP "\fBlarge\fR" 4 +.IX Item "large" +All the text and data segments can be within 4GB addressing space. +.RE +.RS 4 +.RE +.IP "\fB\-mctor\-dtor\fR" 4 +.IX Item "-mctor-dtor" +Enable constructor/destructor feature. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Guide linker to relax instructions. +.PP +\fINios \s-1II\s0 Options\fR +.IX Subsection "Nios II Options" +.PP +These are the options defined for the Altera Nios \s-1II\s0 processor. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put global and static objects less than or equal to \fInum\fR bytes +into the small data or \s-1BSS\s0 sections instead of the normal data or \s-1BSS\s0 +sections. The default value of \fInum\fR is 8. +.IP "\fB\-mgpopt=\fR\fIoption\fR" 4 +.IX Item "-mgpopt=option" +.PD 0 +.IP "\fB\-mgpopt\fR" 4 +.IX Item "-mgpopt" +.IP "\fB\-mno\-gpopt\fR" 4 +.IX Item "-mno-gpopt" +.PD +Generate (do not generate) GP-relative accesses. The following +\&\fIoption\fR names are recognized: +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +Do not generate GP-relative accesses. +.IP "\fBlocal\fR" 4 +.IX Item "local" +Generate GP-relative accesses for small data objects that are not +external, weak, or uninitialized common symbols. +Also use GP-relative addressing for objects that +have been explicitly placed in a small data section via a \f(CW\*(C`section\*(C'\fR +attribute. +.IP "\fBglobal\fR" 4 +.IX Item "global" +As for \fBlocal\fR, but also generate GP-relative accesses for +small data objects that are external, weak, or common. If you use this option, +you must ensure that all parts of your program (including libraries) are +compiled with the same \fB\-G\fR setting. +.IP "\fBdata\fR" 4 +.IX Item "data" +Generate GP-relative accesses for all data objects in the program. If you +use this option, the entire data and \s-1BSS\s0 segments +of your program must fit in 64K of memory and you must use an appropriate +linker script to allocate them within the addressable range of the +global pointer. +.IP "\fBall\fR" 4 +.IX Item "all" +Generate GP-relative addresses for function pointers as well as data +pointers. If you use this option, the entire text, data, and \s-1BSS\s0 segments +of your program must fit in 64K of memory and you must use an appropriate +linker script to allocate them within the addressable range of the +global pointer. +.RE +.RS 4 +.Sp +\&\fB\-mgpopt\fR is equivalent to \fB\-mgpopt=local\fR, and +\&\fB\-mno\-gpopt\fR is equivalent to \fB\-mgpopt=none\fR. +.Sp +The default is \fB\-mgpopt\fR except when \fB\-fpic\fR or +\&\fB\-fPIC\fR is specified to generate position-independent code. +Note that the Nios \s-1II ABI\s0 does not permit GP-relative accesses from +shared libraries. +.Sp +You may need to specify \fB\-mno\-gpopt\fR explicitly when building +programs that include large amounts of small data, including large +\&\s-1GOT\s0 data sections. In this case, the 16\-bit offset for GP-relative +addressing may not be large enough to allow access to the entire +small data section. +.RE +.IP "\fB\-mgprel\-sec=\fR\fIregexp\fR" 4 +.IX Item "-mgprel-sec=regexp" +This option specifies additional section names that can be accessed via +GP-relative addressing. It is most useful in conjunction with +\&\f(CW\*(C`section\*(C'\fR attributes on variable declarations and a custom linker script. +The \fIregexp\fR is a \s-1POSIX\s0 Extended Regular Expression. +.Sp +This option does not affect the behavior of the \fB\-G\fR option, and +the specified sections are in addition to the standard \f(CW\*(C`.sdata\*(C'\fR +and \f(CW\*(C`.sbss\*(C'\fR small-data sections that are recognized by \fB\-mgpopt\fR. +.IP "\fB\-mr0rel\-sec=\fR\fIregexp\fR" 4 +.IX Item "-mr0rel-sec=regexp" +This option specifies names of sections that can be accessed via a +16\-bit offset from \f(CW\*(C`r0\*(C'\fR; that is, in the low 32K or high 32K +of the 32\-bit address space. It is most useful in conjunction with +\&\f(CW\*(C`section\*(C'\fR attributes on variable declarations and a custom linker script. +The \fIregexp\fR is a \s-1POSIX\s0 Extended Regular Expression. +.Sp +In contrast to the use of GP-relative addressing for small data, +zero-based addressing is never generated by default and there are no +conventional section names used in standard linker scripts for sections +in the low or high areas of memory. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +.PD 0 +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +.PD +Generate little-endian (default) or big-endian (experimental) code, +respectively. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +This specifies the name of the target Nios \s-1II\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. Permissible names are: \fBr1\fR, \fBr2\fR. +.Sp +The preprocessor macro \f(CW\*(C`_\|_nios2_arch_\|_\*(C'\fR is available to programs, +with value 1 or 2, indicating the targeted \s-1ISA\s0 level. +.IP "\fB\-mbypass\-cache\fR" 4 +.IX Item "-mbypass-cache" +.PD 0 +.IP "\fB\-mno\-bypass\-cache\fR" 4 +.IX Item "-mno-bypass-cache" +.PD +Force all load and store instructions to always bypass cache by +using I/O variants of the instructions. The default is not to +bypass the cache. +.IP "\fB\-mno\-cache\-volatile\fR" 4 +.IX Item "-mno-cache-volatile" +.PD 0 +.IP "\fB\-mcache\-volatile\fR" 4 +.IX Item "-mcache-volatile" +.PD +Volatile memory access bypass the cache using the I/O variants of +the load and store instructions. The default is not to bypass the cache. +.IP "\fB\-mno\-fast\-sw\-div\fR" 4 +.IX Item "-mno-fast-sw-div" +.PD 0 +.IP "\fB\-mfast\-sw\-div\fR" 4 +.IX Item "-mfast-sw-div" +.PD +Do not use table-based fast divide for small numbers. The default +is to use the fast divide at \fB\-O3\fR and above. +.IP "\fB\-mno\-hw\-mul\fR" 4 +.IX Item "-mno-hw-mul" +.PD 0 +.IP "\fB\-mhw\-mul\fR" 4 +.IX Item "-mhw-mul" +.IP "\fB\-mno\-hw\-mulx\fR" 4 +.IX Item "-mno-hw-mulx" +.IP "\fB\-mhw\-mulx\fR" 4 +.IX Item "-mhw-mulx" +.IP "\fB\-mno\-hw\-div\fR" 4 +.IX Item "-mno-hw-div" +.IP "\fB\-mhw\-div\fR" 4 +.IX Item "-mhw-div" +.PD +Enable or disable emitting \f(CW\*(C`mul\*(C'\fR, \f(CW\*(C`mulx\*(C'\fR and \f(CW\*(C`div\*(C'\fR family of +instructions by the compiler. The default is to emit \f(CW\*(C`mul\*(C'\fR +and not emit \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`mulx\*(C'\fR. +.IP "\fB\-mbmx\fR" 4 +.IX Item "-mbmx" +.PD 0 +.IP "\fB\-mno\-bmx\fR" 4 +.IX Item "-mno-bmx" +.IP "\fB\-mcdx\fR" 4 +.IX Item "-mcdx" +.IP "\fB\-mno\-cdx\fR" 4 +.IX Item "-mno-cdx" +.PD +Enable or disable generation of Nios \s-1II R2 BMX\s0 (bit manipulation) and +\&\s-1CDX\s0 (code density) instructions. Enabling these instructions also +requires \fB\-march=r2\fR. Since these instructions are optional +extensions to the R2 architecture, the default is not to emit them. +.IP "\fB\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR" 4 +.IX Item "-mcustom-insn=N" +.PD 0 +.IP "\fB\-mno\-custom\-\fR\fIinsn\fR" 4 +.IX Item "-mno-custom-insn" +.PD +Each \fB\-mcustom\-\fR\fIinsn\fR\fB=\fR\fIN\fR option enables use of a +custom instruction with encoding \fIN\fR when generating code that uses +\&\fIinsn\fR. For example, \fB\-mcustom\-fadds=253\fR generates custom +instruction 253 for single-precision floating-point add operations instead +of the default behavior of using a library call. +.Sp +The following values of \fIinsn\fR are supported. Except as otherwise +noted, floating-point operations are expected to be implemented with +normal \s-1IEEE 754\s0 semantics and correspond directly to the C operators or the +equivalent \s-1GCC\s0 built-in functions. +.Sp +Single-precision floating point: +.RS 4 +.IP "\fBfadds\fR, \fBfsubs\fR, \fBfdivs\fR, \fBfmuls\fR" 4 +.IX Item "fadds, fsubs, fdivs, fmuls" +Binary arithmetic operations. +.IP "\fBfnegs\fR" 4 +.IX Item "fnegs" +Unary negation. +.IP "\fBfabss\fR" 4 +.IX Item "fabss" +Unary absolute value. +.IP "\fBfcmpeqs\fR, \fBfcmpges\fR, \fBfcmpgts\fR, \fBfcmples\fR, \fBfcmplts\fR, \fBfcmpnes\fR" 4 +.IX Item "fcmpeqs, fcmpges, fcmpgts, fcmples, fcmplts, fcmpnes" +Comparison operations. +.IP "\fBfmins\fR, \fBfmaxs\fR" 4 +.IX Item "fmins, fmaxs" +Floating-point minimum and maximum. These instructions are only +generated if \fB\-ffinite\-math\-only\fR is specified. +.IP "\fBfsqrts\fR" 4 +.IX Item "fsqrts" +Unary square root operation. +.IP "\fBfcoss\fR, \fBfsins\fR, \fBftans\fR, \fBfatans\fR, \fBfexps\fR, \fBflogs\fR" 4 +.IX Item "fcoss, fsins, ftans, fatans, fexps, flogs" +Floating-point trigonometric and exponential functions. These instructions +are only generated if \fB\-funsafe\-math\-optimizations\fR is also specified. +.RE +.RS 4 +.Sp +Double-precision floating point: +.IP "\fBfaddd\fR, \fBfsubd\fR, \fBfdivd\fR, \fBfmuld\fR" 4 +.IX Item "faddd, fsubd, fdivd, fmuld" +Binary arithmetic operations. +.IP "\fBfnegd\fR" 4 +.IX Item "fnegd" +Unary negation. +.IP "\fBfabsd\fR" 4 +.IX Item "fabsd" +Unary absolute value. +.IP "\fBfcmpeqd\fR, \fBfcmpged\fR, \fBfcmpgtd\fR, \fBfcmpled\fR, \fBfcmpltd\fR, \fBfcmpned\fR" 4 +.IX Item "fcmpeqd, fcmpged, fcmpgtd, fcmpled, fcmpltd, fcmpned" +Comparison operations. +.IP "\fBfmind\fR, \fBfmaxd\fR" 4 +.IX Item "fmind, fmaxd" +Double-precision minimum and maximum. These instructions are only +generated if \fB\-ffinite\-math\-only\fR is specified. +.IP "\fBfsqrtd\fR" 4 +.IX Item "fsqrtd" +Unary square root operation. +.IP "\fBfcosd\fR, \fBfsind\fR, \fBftand\fR, \fBfatand\fR, \fBfexpd\fR, \fBflogd\fR" 4 +.IX Item "fcosd, fsind, ftand, fatand, fexpd, flogd" +Double-precision trigonometric and exponential functions. These instructions +are only generated if \fB\-funsafe\-math\-optimizations\fR is also specified. +.RE +.RS 4 +.Sp +Conversions: +.IP "\fBfextsd\fR" 4 +.IX Item "fextsd" +Conversion from single precision to double precision. +.IP "\fBftruncds\fR" 4 +.IX Item "ftruncds" +Conversion from double precision to single precision. +.IP "\fBfixsi\fR, \fBfixsu\fR, \fBfixdi\fR, \fBfixdu\fR" 4 +.IX Item "fixsi, fixsu, fixdi, fixdu" +Conversion from floating point to signed or unsigned integer types, with +truncation towards zero. +.IP "\fBround\fR" 4 +.IX Item "round" +Conversion from single-precision floating point to signed integer, +rounding to the nearest integer and ties away from zero. +This corresponds to the \f(CW\*(C`_\|_builtin_lroundf\*(C'\fR function when +\&\fB\-fno\-math\-errno\fR is used. +.IP "\fBfloatis\fR, \fBfloatus\fR, \fBfloatid\fR, \fBfloatud\fR" 4 +.IX Item "floatis, floatus, floatid, floatud" +Conversion from signed or unsigned integer types to floating-point types. +.RE +.RS 4 +.Sp +In addition, all of the following transfer instructions for internal +registers X and Y must be provided to use any of the double-precision +floating-point instructions. Custom instructions taking two +double-precision source operands expect the first operand in the +64\-bit register X. The other operand (or only operand of a unary +operation) is given to the custom arithmetic instruction with the +least significant half in source register \fIsrc1\fR and the most +significant half in \fIsrc2\fR. A custom instruction that returns a +double-precision result returns the most significant 32 bits in the +destination register and the other half in 32\-bit register Y. +\&\s-1GCC\s0 automatically generates the necessary code sequences to write +register X and/or read register Y when double-precision floating-point +instructions are used. +.IP "\fBfwrx\fR" 4 +.IX Item "fwrx" +Write \fIsrc1\fR into the least significant half of X and \fIsrc2\fR into +the most significant half of X. +.IP "\fBfwry\fR" 4 +.IX Item "fwry" +Write \fIsrc1\fR into Y. +.IP "\fBfrdxhi\fR, \fBfrdxlo\fR" 4 +.IX Item "frdxhi, frdxlo" +Read the most or least (respectively) significant half of X and store it in +\&\fIdest\fR. +.IP "\fBfrdy\fR" 4 +.IX Item "frdy" +Read the value of Y and store it into \fIdest\fR. +.RE +.RS 4 +.Sp +Note that you can gain more local control over generation of Nios \s-1II\s0 custom +instructions by using the \f(CW\*(C`target("custom\-\f(CIinsn\f(CW=\f(CIN\f(CW")\*(C'\fR +and \f(CW\*(C`target("no\-custom\-\f(CIinsn\f(CW")\*(C'\fR function attributes +or pragmas. +.RE +.IP "\fB\-mcustom\-fpu\-cfg=\fR\fIname\fR" 4 +.IX Item "-mcustom-fpu-cfg=name" +This option enables a predefined, named set of custom instruction encodings +(see \fB\-mcustom\-\fR\fIinsn\fR above). +Currently, the following sets are defined: +.Sp +\&\fB\-mcustom\-fpu\-cfg=60\-1\fR is equivalent to: +\&\fB\-mcustom\-fmuls=252 +\&\-mcustom\-fadds=253 +\&\-mcustom\-fsubs=254 +\&\-fsingle\-precision\-constant\fR +.Sp +\&\fB\-mcustom\-fpu\-cfg=60\-2\fR is equivalent to: +\&\fB\-mcustom\-fmuls=252 +\&\-mcustom\-fadds=253 +\&\-mcustom\-fsubs=254 +\&\-mcustom\-fdivs=255 +\&\-fsingle\-precision\-constant\fR +.Sp +\&\fB\-mcustom\-fpu\-cfg=72\-3\fR is equivalent to: +\&\fB\-mcustom\-floatus=243 +\&\-mcustom\-fixsi=244 +\&\-mcustom\-floatis=245 +\&\-mcustom\-fcmpgts=246 +\&\-mcustom\-fcmples=249 +\&\-mcustom\-fcmpeqs=250 +\&\-mcustom\-fcmpnes=251 +\&\-mcustom\-fmuls=252 +\&\-mcustom\-fadds=253 +\&\-mcustom\-fsubs=254 +\&\-mcustom\-fdivs=255 +\&\-fsingle\-precision\-constant\fR +.Sp +Custom instruction assignments given by individual +\&\fB\-mcustom\-\fR\fIinsn\fR\fB=\fR options override those given by +\&\fB\-mcustom\-fpu\-cfg=\fR, regardless of the +order of the options on the command line. +.Sp +Note that you can gain more local control over selection of a \s-1FPU\s0 +configuration by using the \f(CW\*(C`target("custom\-fpu\-cfg=\f(CIname\f(CW")\*(C'\fR +function attribute +or pragma. +.PP +These additional \fB\-m\fR options are available for the Altera Nios \s-1II +ELF\s0 (bare-metal) target: +.IP "\fB\-mhal\fR" 4 +.IX Item "-mhal" +Link with \s-1HAL BSP.\s0 This suppresses linking with the GCC-provided C runtime +startup and termination code, and is typically used in conjunction with +\&\fB\-msys\-crt0=\fR to specify the location of the alternate startup code +provided by the \s-1HAL BSP.\s0 +.IP "\fB\-msmallc\fR" 4 +.IX Item "-msmallc" +Link with a limited version of the C library, \fB\-lsmallc\fR, rather than +Newlib. +.IP "\fB\-msys\-crt0=\fR\fIstartfile\fR" 4 +.IX Item "-msys-crt0=startfile" +\&\fIstartfile\fR is the file name of the startfile (crt0) to use +when linking. This option is only useful in conjunction with \fB\-mhal\fR. +.IP "\fB\-msys\-lib=\fR\fIsystemlib\fR" 4 +.IX Item "-msys-lib=systemlib" +\&\fIsystemlib\fR is the library name of the library that provides +low-level system calls required by the C library, +e.g. \f(CW\*(C`read\*(C'\fR and \f(CW\*(C`write\*(C'\fR. +This option is typically used to link with a library provided by a \s-1HAL BSP.\s0 +.PP +\fINvidia \s-1PTX\s0 Options\fR +.IX Subsection "Nvidia PTX Options" +.PP +These options are defined for Nvidia \s-1PTX:\s0 +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit \s-1ABI.\s0 +.IP "\fB\-misa=\fR\fIISA-string\fR" 4 +.IX Item "-misa=ISA-string" +Generate code for given the specified \s-1PTX ISA\s0 (e.g. \fBsm_35\fR). \s-1ISA\s0 +strings must be lower-case. Valid \s-1ISA\s0 strings include \fBsm_30\fR and +\&\fBsm_35\fR. The default \s-1ISA\s0 is sm_30. +.IP "\fB\-mmainkernel\fR" 4 +.IX Item "-mmainkernel" +Link in code for a _\|_main kernel. This is for stand-alone instead of +offloading execution. +.IP "\fB\-moptimize\fR" 4 +.IX Item "-moptimize" +Apply partitioned execution optimizations. This is the default when any +level of optimization is selected. +.IP "\fB\-msoft\-stack\fR" 4 +.IX Item "-msoft-stack" +Generate code that does not use \f(CW\*(C`.local\*(C'\fR memory +directly for stack storage. Instead, a per-warp stack pointer is +maintained explicitly. This enables variable-length stack allocation (with +variable-length arrays or \f(CW\*(C`alloca\*(C'\fR), and when global memory is used for +underlying storage, makes it possible to access automatic variables from other +threads, or with atomic instructions. This code generation variant is used +for OpenMP offloading, but the option is exposed on its own for the purpose +of testing the compiler; to generate code suitable for linking into programs +using OpenMP offloading, use option \fB\-mgomp\fR. +.IP "\fB\-muniform\-simt\fR" 4 +.IX Item "-muniform-simt" +Switch to code generation variant that allows to execute all threads in each +warp, while maintaining memory state and side effects as if only one thread +in each warp was active outside of OpenMP \s-1SIMD\s0 regions. All atomic operations +and calls to runtime (malloc, free, vprintf) are conditionally executed (iff +current lane index equals the master lane index), and the register being +assigned is copied via a shuffle instruction from the master lane. Outside of +\&\s-1SIMD\s0 regions lane 0 is the master; inside, each thread sees itself as the +master. Shared memory array \f(CW\*(C`int _\|_nvptx_uni[]\*(C'\fR stores all-zeros or +all-ones bitmasks for each warp, indicating current mode (0 outside of \s-1SIMD\s0 +regions). Each thread can bitwise-and the bitmask at position \f(CW\*(C`tid.y\*(C'\fR +with current lane index to compute the master lane index. +.IP "\fB\-mgomp\fR" 4 +.IX Item "-mgomp" +Generate code for use in OpenMP offloading: enables \fB\-msoft\-stack\fR and +\&\fB\-muniform\-simt\fR options, and selects corresponding multilib variant. +.PP +\fIOpenRISC Options\fR +.IX Subsection "OpenRISC Options" +.PP +These options are defined for OpenRISC: +.IP "\fB\-mboard=\fR\fIname\fR" 4 +.IX Item "-mboard=name" +Configure a board specific runtime. This will be passed to the linker for +newlib board library linking. The default is \f(CW\*(C`or1ksim\*(C'\fR. +.IP "\fB\-mnewlib\fR" 4 +.IX Item "-mnewlib" +For compatibility, it's always newlib for elf now. +.IP "\fB\-mhard\-div\fR" 4 +.IX Item "-mhard-div" +Generate code for hardware which supports divide instructions. This is the +default. +.IP "\fB\-mhard\-mul\fR" 4 +.IX Item "-mhard-mul" +Generate code for hardware which supports multiply instructions. This is the +default. +.IP "\fB\-mcmov\fR" 4 +.IX Item "-mcmov" +Generate code for hardware which supports the conditional move (\f(CW\*(C`l.cmov\*(C'\fR) +instruction. +.IP "\fB\-mror\fR" 4 +.IX Item "-mror" +Generate code for hardware which supports rotate right instructions. +.IP "\fB\-msext\fR" 4 +.IX Item "-msext" +Generate code for hardware which supports sign-extension instructions. +.IP "\fB\-msfimm\fR" 4 +.IX Item "-msfimm" +Generate code for hardware which supports set flag immediate (\f(CW\*(C`l.sf*i\*(C'\fR) +instructions. +.IP "\fB\-mshftimm\fR" 4 +.IX Item "-mshftimm" +Generate code for hardware which supports shift immediate related instructions +(i.e. \f(CW\*(C`l.srai\*(C'\fR, \f(CW\*(C`l.srli\*(C'\fR, \f(CW\*(C`l.slli\*(C'\fR, \f(CW\*(C`1.rori\*(C'\fR). Note, to +enable generation of the \f(CW\*(C`l.rori\*(C'\fR instruction the \fB\-mror\fR flag must +also be specified. +.IP "\fB\-msoft\-div\fR" 4 +.IX Item "-msoft-div" +Generate code for hardware which requires divide instruction emulation. +.IP "\fB\-msoft\-mul\fR" 4 +.IX Item "-msoft-mul" +Generate code for hardware which requires multiply instruction emulation. +.PP +\fI\s-1PDP\-11\s0 Options\fR +.IX Subsection "PDP-11 Options" +.PP +These options are defined for the \s-1PDP\-11:\s0 +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating +point on the \s-1PDP\-11/40\s0 is not supported.) Implies \-m45. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use hardware floating point. +.IP "\fB\-mac0\fR" 4 +.IX Item "-mac0" +Return floating-point results in ac0 (fr0 in Unix assembler syntax). +.IP "\fB\-mno\-ac0\fR" 4 +.IX Item "-mno-ac0" +Return floating-point results in memory. This is the default. +.IP "\fB\-m40\fR" 4 +.IX Item "-m40" +Generate code for a \s-1PDP\-11/40.\s0 Implies \-msoft\-float \-mno\-split. +.IP "\fB\-m45\fR" 4 +.IX Item "-m45" +Generate code for a \s-1PDP\-11/45.\s0 This is the default. +.IP "\fB\-m10\fR" 4 +.IX Item "-m10" +Generate code for a \s-1PDP\-11/10.\s0 Implies \-msoft\-float \-mno\-split. +.IP "\fB\-mint16\fR" 4 +.IX Item "-mint16" +.PD 0 +.IP "\fB\-mno\-int32\fR" 4 +.IX Item "-mno-int32" +.PD +Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +.PD 0 +.IP "\fB\-mno\-int16\fR" 4 +.IX Item "-mno-int16" +.PD +Use 32\-bit \f(CW\*(C`int\*(C'\fR. +.IP "\fB\-msplit\fR" 4 +.IX Item "-msplit" +Target has split instruction and data space. Implies \-m45. +.IP "\fB\-munix\-asm\fR" 4 +.IX Item "-munix-asm" +Use Unix assembler syntax. +.IP "\fB\-mdec\-asm\fR" 4 +.IX Item "-mdec-asm" +Use \s-1DEC\s0 assembler syntax. +.IP "\fB\-mgnu\-asm\fR" 4 +.IX Item "-mgnu-asm" +Use \s-1GNU\s0 assembler syntax. This is the default. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +Use the new \s-1LRA\s0 register allocator. By default, the old \*(L"reload\*(R" +allocator is used. +.PP +\fIpicoChip Options\fR +.IX Subsection "picoChip Options" +.PP +These \fB\-m\fR options are defined for picoChip implementations: +.IP "\fB\-mae=\fR\fIae_type\fR" 4 +.IX Item "-mae=ae_type" +Set the instruction set, register set, and instruction scheduling +parameters for array element type \fIae_type\fR. Supported values +for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. +.Sp +\&\fB\-mae=ANY\fR selects a completely generic \s-1AE\s0 type. Code +generated with this option runs on any of the other \s-1AE\s0 types. The +code is not as efficient as it would be if compiled for a specific +\&\s-1AE\s0 type, and some types of operation (e.g., multiplication) do not +work properly on all types of \s-1AE.\s0 +.Sp +\&\fB\-mae=MUL\fR selects a \s-1MUL AE\s0 type. This is the most useful \s-1AE\s0 type +for compiled code, and is the default. +.Sp +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC AE.\s0 Code compiled with this +option may suffer from poor performance of byte (char) manipulation, +since the \s-1DSP AE\s0 does not provide hardware support for byte load/stores. +.IP "\fB\-msymbol\-as\-address\fR" 4 +.IX Item "-msymbol-as-address" +Enable the compiler to directly use a symbol name as an address in a +load/store instruction, without first loading it into a +register. Typically, the use of this option generates larger +programs, which run faster than when the option isn't used. However, the +results vary from program to program, so it is left as a user option, +rather than being permanently enabled. +.IP "\fB\-mno\-inefficient\-warnings\fR" 4 +.IX Item "-mno-inefficient-warnings" +Disables warnings about the generation of inefficient code. These +warnings can be generated, for example, when compiling code that +performs byte-level memory operations on the \s-1MAC AE\s0 type. The \s-1MAC AE\s0 has +no hardware support for byte-level memory operations, so all byte +load/stores must be synthesized from word load/store operations. This is +inefficient and a warning is generated to indicate +that you should rewrite the code to avoid byte operations, or to target +an \s-1AE\s0 type that has the necessary hardware support. This option disables +these warnings. +.PP +\fIPowerPC Options\fR +.IX Subsection "PowerPC Options" +.PP +These are listed under +.PP +\fIRISC-V Options\fR +.IX Subsection "RISC-V Options" +.PP +These command-line options are defined for RISC-V targets: +.IP "\fB\-mbranch\-cost=\fR\fIn\fR" 4 +.IX Item "-mbranch-cost=n" +Set the cost of branches to roughly \fIn\fR instructions. +.IP "\fB\-mplt\fR" 4 +.IX Item "-mplt" +.PD 0 +.IP "\fB\-mno\-plt\fR" 4 +.IX Item "-mno-plt" +.PD +When generating \s-1PIC\s0 code, do or don't allow the use of PLTs. Ignored for +non-PIC. The default is \fB\-mplt\fR. +.IP "\fB\-mabi=\fR\fIABI-string\fR" 4 +.IX Item "-mabi=ABI-string" +Specify integer and floating-point calling convention. \fIABI-string\fR +contains two parts: the size of integer types and the registers used for +floating-point types. For example \fB\-march=rv64ifd \-mabi=lp64d\fR means that +\&\fBlong\fR and pointers are 64\-bit (implicitly defining \fBint\fR to be +32\-bit), and that floating-point values up to 64 bits wide are passed in F +registers. Contrast this with \fB\-march=rv64ifd \-mabi=lp64f\fR, which still +allows the compiler to generate code that uses the F and D extensions but only +allows floating-point values up to 32 bits long to be passed in registers; or +\&\fB\-march=rv64ifd \-mabi=lp64\fR, in which no floating-point arguments will be +passed in registers. +.Sp +The default for this argument is system dependent, users who want a specific +calling convention should specify one explicitly. The valid calling +conventions are: \fBilp32\fR, \fBilp32f\fR, \fBilp32d\fR, \fBlp64\fR, +\&\fBlp64f\fR, and \fBlp64d\fR. Some calling conventions are impossible to +implement on some ISAs: for example, \fB\-march=rv32if \-mabi=ilp32d\fR is +invalid because the \s-1ABI\s0 requires 64\-bit values be passed in F registers, but F +registers are only 32 bits wide. There is also the \fBilp32e\fR \s-1ABI\s0 that can +only be used with the \fBrv32e\fR architecture. This \s-1ABI\s0 is not well +specified at present, and is subject to change. +.IP "\fB\-mfdiv\fR" 4 +.IX Item "-mfdiv" +.PD 0 +.IP "\fB\-mno\-fdiv\fR" 4 +.IX Item "-mno-fdiv" +.PD +Do or don't use hardware floating-point divide and square root instructions. +This requires the F or D extensions for floating-point registers. The default +is to use them if the specified architecture has these instructions. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Do or don't use hardware instructions for integer division. This requires the +M extension. The default is to use them if the specified architecture has +these instructions. +.IP "\fB\-march=\fR\fIISA-string\fR" 4 +.IX Item "-march=ISA-string" +Generate code for given RISC-V \s-1ISA\s0 (e.g. \fBrv64im\fR). \s-1ISA\s0 strings must be +lower-case. Examples include \fBrv64i\fR, \fBrv32g\fR, \fBrv32e\fR, and +\&\fBrv32imaf\fR. +.IP "\fB\-mtune=\fR\fIprocessor-string\fR" 4 +.IX Item "-mtune=processor-string" +Optimize the output for the given processor, specified by microarchitecture +name. Permissible values for this option are: \fBrocket\fR, +\&\fBsifive\-3\-series\fR, \fBsifive\-5\-series\fR, \fBsifive\-7\-series\fR, +and \fBsize\fR. +.Sp +When \fB\-mtune=\fR is not specified, the default is \fBrocket\fR. +.Sp +The \fBsize\fR choice is not intended for use by end-users. This is used +when \fB\-Os\fR is specified. It overrides the instruction cost info +provided by \fB\-mtune=\fR, but does not override the pipeline info. This +helps reduce code size while still giving good performance. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128\-bits). +.Sp +\&\fBWarning:\fR If you use this switch, then you must build all modules with +the same value, including any libraries. This includes the system libraries +and startup modules. +.IP "\fB\-msmall\-data\-limit=\fR\fIn\fR" 4 +.IX Item "-msmall-data-limit=n" +Put global and static data smaller than \fIn\fR bytes into a special section +(on some targets). +.IP "\fB\-msave\-restore\fR" 4 +.IX Item "-msave-restore" +.PD 0 +.IP "\fB\-mno\-save\-restore\fR" 4 +.IX Item "-mno-save-restore" +.PD +Do or don't use smaller but slower prologue and epilogue code that uses +library function calls. The default is to use fast inline prologues and +epilogues. +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD 0 +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD +Do not or do generate unaligned memory accesses. The default is set depending +on whether the processor we are optimizing for supports fast unaligned access +or not. +.IP "\fB\-mcmodel=medlow\fR" 4 +.IX Item "-mcmodel=medlow" +Generate code for the medium-low code model. The program and its statically +defined symbols must lie within a single 2 GiB address range and must lie +between absolute addresses \-2 GiB and +2 GiB. Programs can be +statically or dynamically linked. This is the default code model. +.IP "\fB\-mcmodel=medany\fR" 4 +.IX Item "-mcmodel=medany" +Generate code for the medium-any code model. The program and its statically +defined symbols must be within any single 2 GiB address range. Programs can be +statically or dynamically linked. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-exlicit\-relocs\fR" 4 +.IX Item "-mno-exlicit-relocs" +.PD +Use or do not use assembler relocation operators when dealing with symbolic +addresses. The alternative is to use assembler macros instead, which may +limit optimization. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +.PD 0 +.IP "\fB\-mno\-relax\fR" 4 +.IX Item "-mno-relax" +.PD +Take advantage of linker relaxations to reduce the number of instructions +required to materialize symbol addresses. The default is to take advantage of +linker relaxations. +.IP "\fB\-memit\-attribute\fR" 4 +.IX Item "-memit-attribute" +.PD 0 +.IP "\fB\-mno\-emit\-attribute\fR" 4 +.IX Item "-mno-emit-attribute" +.PD +Emit (do not emit) RISC-V attribute to record extra information into \s-1ELF\s0 +objects. This feature requires at least binutils 2.32. +.PP +\fI\s-1RL78\s0 Options\fR +.IX Subsection "RL78 Options" +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Links in additional target libraries to support operation within a +simulator. +.IP "\fB\-mmul=none\fR" 4 +.IX Item "-mmul=none" +.PD 0 +.IP "\fB\-mmul=g10\fR" 4 +.IX Item "-mmul=g10" +.IP "\fB\-mmul=g13\fR" 4 +.IX Item "-mmul=g13" +.IP "\fB\-mmul=g14\fR" 4 +.IX Item "-mmul=g14" +.IP "\fB\-mmul=rl78\fR" 4 +.IX Item "-mmul=rl78" +.PD +Specifies the type of hardware multiplication and division support to +be used. The simplest is \f(CW\*(C`none\*(C'\fR, which uses software for both +multiplication and division. This is the default. The \f(CW\*(C`g13\*(C'\fR +value is for the hardware multiply/divide peripheral found on the +\&\s-1RL78/G13\s0 (S2 core) targets. The \f(CW\*(C`g14\*(C'\fR value selects the use of +the multiplication and division instructions supported by the \s-1RL78/G14\s0 +(S3 core) parts. The value \f(CW\*(C`rl78\*(C'\fR is an alias for \f(CW\*(C`g14\*(C'\fR and +the value \f(CW\*(C`mg10\*(C'\fR is an alias for \f(CW\*(C`none\*(C'\fR. +.Sp +In addition a C preprocessor macro is defined, based upon the setting +of this option. Possible values are: \f(CW\*(C`_\|_RL78_MUL_NONE_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_RL78_MUL_G13_\|_\*(C'\fR or \f(CW\*(C`_\|_RL78_MUL_G14_\|_\*(C'\fR. +.IP "\fB\-mcpu=g10\fR" 4 +.IX Item "-mcpu=g10" +.PD 0 +.IP "\fB\-mcpu=g13\fR" 4 +.IX Item "-mcpu=g13" +.IP "\fB\-mcpu=g14\fR" 4 +.IX Item "-mcpu=g14" +.IP "\fB\-mcpu=rl78\fR" 4 +.IX Item "-mcpu=rl78" +.PD +Specifies the \s-1RL78\s0 core to target. The default is the G14 core, also +known as an S3 core or just \s-1RL78.\s0 The G13 or S2 core does not have +multiply or divide instructions, instead it uses a hardware peripheral +for these operations. The G10 or S1 core does not have register +banks, so it uses a different calling convention. +.Sp +If this option is set it also selects the type of hardware multiply +support to use, unless this is overridden by an explicit +\&\fB\-mmul=none\fR option on the command line. Thus specifying +\&\fB\-mcpu=g13\fR enables the use of the G13 hardware multiply +peripheral and specifying \fB\-mcpu=g10\fR disables the use of +hardware multiplications altogether. +.Sp +Note, although the \s-1RL78/G14\s0 core is the default target, specifying +\&\fB\-mcpu=g14\fR or \fB\-mcpu=rl78\fR on the command line does +change the behavior of the toolchain since it also enables G14 +hardware multiply support. If these options are not specified on the +command line then software multiplication routines will be used even +though the code targets the \s-1RL78\s0 core. This is for backwards +compatibility with older toolchains which did not have hardware +multiply and divide support. +.Sp +In addition a C preprocessor macro is defined, based upon the setting +of this option. Possible values are: \f(CW\*(C`_\|_RL78_G10_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_RL78_G13_\|_\*(C'\fR or \f(CW\*(C`_\|_RL78_G14_\|_\*(C'\fR. +.IP "\fB\-mg10\fR" 4 +.IX Item "-mg10" +.PD 0 +.IP "\fB\-mg13\fR" 4 +.IX Item "-mg13" +.IP "\fB\-mg14\fR" 4 +.IX Item "-mg14" +.IP "\fB\-mrl78\fR" 4 +.IX Item "-mrl78" +.PD +These are aliases for the corresponding \fB\-mcpu=\fR option. They +are provided for backwards compatibility. +.IP "\fB\-mallregs\fR" 4 +.IX Item "-mallregs" +Allow the compiler to use all of the available registers. By default +registers \f(CW\*(C`r24..r31\*(C'\fR are reserved for use in interrupt handlers. +With this option enabled these registers can be used in ordinary +functions as well. +.IP "\fB\-m64bit\-doubles\fR" 4 +.IX Item "-m64bit-doubles" +.PD 0 +.IP "\fB\-m32bit\-doubles\fR" 4 +.IX Item "-m32bit-doubles" +.PD +Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) +or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is +\&\fB\-m32bit\-doubles\fR. +.IP "\fB\-msave\-mduc\-in\-interrupts\fR" 4 +.IX Item "-msave-mduc-in-interrupts" +.PD 0 +.IP "\fB\-mno\-save\-mduc\-in\-interrupts\fR" 4 +.IX Item "-mno-save-mduc-in-interrupts" +.PD +Specifies that interrupt handler functions should preserve the +\&\s-1MDUC\s0 registers. This is only necessary if normal code might use +the \s-1MDUC\s0 registers, for example because it performs multiplication +and division operations. The default is to ignore the \s-1MDUC\s0 registers +as this makes the interrupt handlers faster. The target option \-mg13 +needs to be passed for this to work as this feature is only available +on the G13 target (S2 core). The \s-1MDUC\s0 registers will only be saved +if the interrupt handler performs a multiplication or division +operation or it calls another function. +.PP +\fI\s-1IBM RS/6000\s0 and PowerPC Options\fR +.IX Subsection "IBM RS/6000 and PowerPC Options" +.PP +These \fB\-m\fR options are defined for the \s-1IBM RS/6000\s0 and PowerPC: +.IP "\fB\-mpowerpc\-gpopt\fR" 4 +.IX Item "-mpowerpc-gpopt" +.PD 0 +.IP "\fB\-mno\-powerpc\-gpopt\fR" 4 +.IX Item "-mno-powerpc-gpopt" +.IP "\fB\-mpowerpc\-gfxopt\fR" 4 +.IX Item "-mpowerpc-gfxopt" +.IP "\fB\-mno\-powerpc\-gfxopt\fR" 4 +.IX Item "-mno-powerpc-gfxopt" +.IP "\fB\-mpowerpc64\fR" 4 +.IX Item "-mpowerpc64" +.IP "\fB\-mno\-powerpc64\fR" 4 +.IX Item "-mno-powerpc64" +.IP "\fB\-mmfcrf\fR" 4 +.IX Item "-mmfcrf" +.IP "\fB\-mno\-mfcrf\fR" 4 +.IX Item "-mno-mfcrf" +.IP "\fB\-mpopcntb\fR" 4 +.IX Item "-mpopcntb" +.IP "\fB\-mno\-popcntb\fR" 4 +.IX Item "-mno-popcntb" +.IP "\fB\-mpopcntd\fR" 4 +.IX Item "-mpopcntd" +.IP "\fB\-mno\-popcntd\fR" 4 +.IX Item "-mno-popcntd" +.IP "\fB\-mfprnd\fR" 4 +.IX Item "-mfprnd" +.IP "\fB\-mno\-fprnd\fR" 4 +.IX Item "-mno-fprnd" +.IP "\fB\-mcmpb\fR" 4 +.IX Item "-mcmpb" +.IP "\fB\-mno\-cmpb\fR" 4 +.IX Item "-mno-cmpb" +.IP "\fB\-mmfpgpr\fR" 4 +.IX Item "-mmfpgpr" +.IP "\fB\-mno\-mfpgpr\fR" 4 +.IX Item "-mno-mfpgpr" +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +You use these options to specify which instructions are available on the +processor you are using. The default value of these options is +determined when configuring \s-1GCC.\s0 Specifying the +\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these +options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option +rather than the options listed above. +.Sp +Specifying \fB\-mpowerpc\-gpopt\fR allows +\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the +General Purpose group, including floating-point square root. Specifying +\&\fB\-mpowerpc\-gfxopt\fR allows \s-1GCC\s0 to +use the optional PowerPC architecture instructions in the Graphics +group, including floating-point select. +.Sp +The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from +condition register field instruction implemented on the \s-1POWER4\s0 +processor and other processors that support the PowerPC V2.01 +architecture. +The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and +double-precision \s-1FP\s0 reciprocal estimate instruction implemented on the +\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02 +architecture. +The \fB\-mpopcntd\fR option allows \s-1GCC\s0 to generate the popcount +instruction implemented on the \s-1POWER7\s0 processor and other processors +that support the PowerPC V2.06 architecture. +The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to +integer instructions implemented on the \s-1POWER5+\s0 processor and other +processors that support the PowerPC V2.03 architecture. +The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes +instruction implemented on the \s-1POWER6\s0 processor and other processors +that support the PowerPC V2.05 architecture. +The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from +general-purpose register instructions implemented on the \s-1POWER6X\s0 +processor and other processors that support the extended PowerPC V2.05 +architecture. +The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal +floating-point instructions implemented on some \s-1POWER\s0 processors. +.Sp +The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional +64\-bit instructions that are found in the full PowerPC64 architecture +and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to +\&\fB\-mno\-powerpc64\fR. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set architecture type, register usage, and +instruction scheduling parameters for machine type \fIcpu_type\fR. +Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR, +\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB464\fR, \fB464fp\fR, +\&\fB476\fR, \fB476fp\fR, \fB505\fR, \fB601\fR, \fB602\fR, \fB603\fR, +\&\fB603e\fR, \fB604\fR, \fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, +\&\fB7400\fR, \fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR, +\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBa2\fR, \fBe300c2\fR, +\&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBe5500\fR, +\&\fBe6500\fR, \fBec603e\fR, \fBG3\fR, \fBG4\fR, \fBG5\fR, +\&\fBtitan\fR, \fBpower3\fR, \fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, +\&\fBpower6\fR, \fBpower6x\fR, \fBpower7\fR, \fBpower8\fR, +\&\fBpower9\fR, \fBpowerpc\fR, \fBpowerpc64\fR, \fBpowerpc64le\fR, +\&\fBrs64\fR, and \fBnative\fR. +.Sp +\&\fB\-mcpu=powerpc\fR, \fB\-mcpu=powerpc64\fR, and +\&\fB\-mcpu=powerpc64le\fR specify pure 32\-bit PowerPC (either +endian), 64\-bit big endian PowerPC and 64\-bit little endian PowerPC +architecture machine types, with an appropriate, generic processor +model assumed for scheduling purposes. +.Sp +Specifying \fBnative\fR as cpu type detects and selects the +architecture option that corresponds to the host processor of the +system performing the compilation. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize the +processor. +.Sp +The other options specify a specific processor. Code generated under +those options runs best on that processor, and may not run at all on +others. +.Sp +The \fB\-mcpu\fR options automatically enable or disable the +following options: +.Sp +\&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple +\&\-mpopcntb \-mpopcntd \-mpowerpc64 +\&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt +\&\-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mhtm \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic \-mfloat128 \-mfloat128\-hardware\fR +.Sp +The particular options set for any particular \s-1CPU\s0 varies between +compiler versions, depending on what setting seems to produce optimal +code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's +capabilities. If you wish to set an individual option to a particular +value, you may specify it after the \fB\-mcpu\fR option, like +\&\fB\-mcpu=970 \-mno\-altivec\fR. +.Sp +On \s-1AIX,\s0 the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are +not enabled or disabled by the \fB\-mcpu\fR option at present because +\&\s-1AIX\s0 does not have full support for these options. You may still +enable or disable them individually if you're sure it'll work in your +environment. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the architecture type or register usage, +as \fB\-mcpu=\fR\fIcpu_type\fR does. The same +values for \fIcpu_type\fR are used for \fB\-mtune\fR as for +\&\fB\-mcpu\fR. If both are specified, the code generated uses the +architecture and registers set by \fB\-mcpu\fR, but the +scheduling parameters set by \fB\-mtune\fR. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate PowerPC64 code for the small model: The \s-1TOC\s0 is limited to +64k. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate PowerPC64 code for the medium model: The \s-1TOC\s0 and other static +data may be up to a total of 4G in size. This is the default for 64\-bit +Linux. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate PowerPC64 code for the large model: The \s-1TOC\s0 may be up to 4G +in size. Other data and code is only limited by the 64\-bit address +space. +.IP "\fB\-maltivec\fR" 4 +.IX Item "-maltivec" +.PD 0 +.IP "\fB\-mno\-altivec\fR" 4 +.IX Item "-mno-altivec" +.PD +Generate code that uses (does not use) AltiVec instructions, and also +enable the use of built-in functions that allow more direct access to +the AltiVec instruction set. You may also need to set +\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 +enhancements. +.Sp +When \fB\-maltivec\fR is used, the element order for AltiVec intrinsics +such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-mvrsave\fR" 4 +.IX Item "-mvrsave" +.PD 0 +.IP "\fB\-mno\-vrsave\fR" 4 +.IX Item "-mno-vrsave" +.PD +Generate \s-1VRSAVE\s0 instructions when generating AltiVec code. +.IP "\fB\-msecure\-plt\fR" 4 +.IX Item "-msecure-plt" +Generate code that allows \fBld\fR and \fBld.so\fR +to build executables and shared +libraries with non-executable \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections. +This is a PowerPC +32\-bit \s-1SYSV ABI\s0 option. +.IP "\fB\-mbss\-plt\fR" 4 +.IX Item "-mbss-plt" +Generate code that uses a \s-1BSS\s0 \f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR +fills in, and +requires \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR +sections that are both writable and executable. +This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. +.IP "\fB\-misel\fR" 4 +.IX Item "-misel" +.PD 0 +.IP "\fB\-mno\-isel\fR" 4 +.IX Item "-mno-isel" +.PD +This switch enables or disables the generation of \s-1ISEL\s0 instructions. +.IP "\fB\-mvsx\fR" 4 +.IX Item "-mvsx" +.PD 0 +.IP "\fB\-mno\-vsx\fR" 4 +.IX Item "-mno-vsx" +.PD +Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) +instructions, and also enable the use of built-in functions that allow +more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA.\s0 +.IP "\fB\-mhtm\fR" 4 +.IX Item "-mhtm" +.PD 0 +.IP "\fB\-mno\-htm\fR" 4 +.IX Item "-mno-htm" +.PD +Enable (disable) the use of the built-in functions that allow direct +access to the Hardware Transactional Memory (\s-1HTM\s0) instructions that +were added in version 2.07 of the PowerPC \s-1ISA.\s0 +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA.\s0 Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. +.IP "\fB\-mfloat128\fR" 4 +.IX Item "-mfloat128" +.PD 0 +.IP "\fB\-mno\-float128\fR" 4 +.IX Item "-mno-float128" +.PD +Enable/disable the \fI_\|_float128\fR keyword for \s-1IEEE\s0 128\-bit floating point +and use either software emulation for \s-1IEEE\s0 128\-bit floating point or +hardware instructions. +.Sp +The \s-1VSX\s0 instruction set (\fB\-mvsx\fR, \fB\-mcpu=power7\fR, +\&\fB\-mcpu=power8\fR), or \fB\-mcpu=power9\fR must be enabled to +use the \s-1IEEE\s0 128\-bit floating point support. The \s-1IEEE\s0 128\-bit +floating point support only works on PowerPC Linux systems. +.Sp +The default for \fB\-mfloat128\fR is enabled on PowerPC Linux +systems using the \s-1VSX\s0 instruction set, and disabled on other systems. +.Sp +If you use the \s-1ISA 3.0\s0 instruction set (\fB\-mpower9\-vector\fR or +\&\fB\-mcpu=power9\fR) on a 64\-bit system, the \s-1IEEE\s0 128\-bit floating +point support will also enable the generation of \s-1ISA 3.0 IEEE\s0 128\-bit +floating point instructions. Otherwise, if you do not specify to +generate \s-1ISA 3.0\s0 instructions or you are targeting a 32\-bit big endian +system, \s-1IEEE\s0 128\-bit floating point will be done with software +emulation. +.IP "\fB\-mfloat128\-hardware\fR" 4 +.IX Item "-mfloat128-hardware" +.PD 0 +.IP "\fB\-mno\-float128\-hardware\fR" 4 +.IX Item "-mno-float128-hardware" +.PD +Enable/disable using \s-1ISA 3.0\s0 hardware instructions to support the +\&\fI_\|_float128\fR data type. +.Sp +The default for \fB\-mfloat128\-hardware\fR is enabled on PowerPC +Linux systems using the \s-1ISA 3.0\s0 instruction set, and disabled on other +systems. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0 +targets (including GNU/Linux). The 32\-bit environment sets int, long +and pointer to 32 bits and generates code that runs on any PowerPC +variant. The 64\-bit environment sets int to 32 bits and long and +pointer to 64 bits, and generates code for PowerPC64, as for +\&\fB\-mpowerpc64\fR. +.IP "\fB\-mfull\-toc\fR" 4 +.IX Item "-mfull-toc" +.PD 0 +.IP "\fB\-mno\-fp\-in\-toc\fR" 4 +.IX Item "-mno-fp-in-toc" +.IP "\fB\-mno\-sum\-in\-toc\fR" 4 +.IX Item "-mno-sum-in-toc" +.IP "\fB\-mminimal\-toc\fR" 4 +.IX Item "-mminimal-toc" +.PD +Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for +every executable file. The \fB\-mfull\-toc\fR option is selected by +default. In that case, \s-1GCC\s0 allocates at least one \s-1TOC\s0 entry for +each unique non-automatic variable reference in your program. \s-1GCC\s0 +also places floating-point constants in the \s-1TOC.\s0 However, only +16,384 entries are available in the \s-1TOC.\s0 +.Sp +If you receive a linker error message that saying you have overflowed +the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used +with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. +\&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point +constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to +generate code to calculate the sum of an address and a constant at +run time instead of putting that sum into the \s-1TOC.\s0 You may specify one +or both of these options. Each causes \s-1GCC\s0 to produce very slightly +slower and larger code at the expense of conserving \s-1TOC\s0 space. +.Sp +If you still run out of space in the \s-1TOC\s0 even when you specify both of +these options, specify \fB\-mminimal\-toc\fR instead. This option causes +\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file. When you specify this +option, \s-1GCC\s0 produces code that is slower and larger but which +uses extremely little \s-1TOC\s0 space. You may wish to use this option +only on files that contain less frequently-executed code. +.IP "\fB\-maix64\fR" 4 +.IX Item "-maix64" +.PD 0 +.IP "\fB\-maix32\fR" 4 +.IX Item "-maix32" +.PD +Enable 64\-bit \s-1AIX ABI\s0 and calling convention: 64\-bit pointers, 64\-bit +\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. +Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR, +while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and +implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. +.IP "\fB\-mxl\-compat\fR" 4 +.IX Item "-mxl-compat" +.PD 0 +.IP "\fB\-mno\-xl\-compat\fR" 4 +.IX Item "-mno-xl-compat" +.PD +Produce code that conforms more closely to \s-1IBM XL\s0 compiler semantics +when using AIX-compatible \s-1ABI.\s0 Pass floating-point arguments to +prototyped functions beyond the register save area (\s-1RSA\s0) on the stack +in addition to argument FPRs. Do not assume that most significant +double in 128\-bit long double value is properly rounded when comparing +values and converting to double. Use \s-1XL\s0 symbol names for long double +support routines. +.Sp +The \s-1AIX\s0 calling convention was extended but not initially documented to +handle an obscure K&R C case of calling a function that takes the +address of its arguments with fewer arguments than declared. \s-1IBM XL\s0 +compilers access floating-point arguments that do not fit in the +\&\s-1RSA\s0 from the stack when a subroutine is compiled without +optimization. Because always storing floating-point arguments on the +stack is inefficient and rarely needed, this option is not enabled by +default and only is necessary when calling subroutines compiled by \s-1IBM +XL\s0 compilers without optimization. +.IP "\fB\-mpe\fR" 4 +.IX Item "-mpe" +Support \fI\s-1IBM RS/6000 SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an +application written to use message passing with special startup code to +enable the application to run. The system must have \s-1PE\s0 installed in the +standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file +must be overridden with the \fB\-specs=\fR option to specify the +appropriate directory location. The Parallel Environment does not +support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR +option are incompatible. +.IP "\fB\-malign\-natural\fR" 4 +.IX Item "-malign-natural" +.PD 0 +.IP "\fB\-malign\-power\fR" 4 +.IX Item "-malign-power" +.PD +On \s-1AIX,\s0 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option +\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger +types, such as floating-point doubles, on their natural size-based boundary. +The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified +alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI.\s0 +.Sp +On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR +is not supported. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code that does not use (uses) the floating-point register set. +Software floating-point emulation is provided if you use the +\&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking. +.IP "\fB\-mmultiple\fR" 4 +.IX Item "-mmultiple" +.PD 0 +.IP "\fB\-mno\-multiple\fR" 4 +.IX Item "-mno-multiple" +.PD +Generate code that uses (does not use) the load multiple word +instructions and the store multiple word instructions. These +instructions are generated by default on \s-1POWER\s0 systems, and not +generated on PowerPC systems. Do not use \fB\-mmultiple\fR on little-endian +PowerPC systems, since those instructions do not work when the +processor is in little-endian mode. The exceptions are \s-1PPC740\s0 and +\&\s-1PPC750\s0 which permit these instructions in little-endian mode. +.IP "\fB\-mupdate\fR" 4 +.IX Item "-mupdate" +.PD 0 +.IP "\fB\-mno\-update\fR" 4 +.IX Item "-mno-update" +.PD +Generate code that uses (does not use) the load or store instructions +that update the base register to the address of the calculated memory +location. These instructions are generated by default. If you use +\&\fB\-mno\-update\fR, there is a small window between the time that the +stack pointer is updated and the address of the previous frame is +stored, which means code that walks the stack frame across interrupts or +signals may get corrupted data. +.IP "\fB\-mavoid\-indexed\-addresses\fR" 4 +.IX Item "-mavoid-indexed-addresses" +.PD 0 +.IP "\fB\-mno\-avoid\-indexed\-addresses\fR" 4 +.IX Item "-mno-avoid-indexed-addresses" +.PD +Generate code that tries to avoid (not avoid) the use of indexed load +or store instructions. These instructions can incur a performance +penalty on Power6 processors in certain situations, such as when +stepping through large arrays that cross a 16M boundary. This option +is enabled by default when targeting Power6 and disabled otherwise. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine-dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mmulhw\fR" 4 +.IX Item "-mmulhw" +.PD 0 +.IP "\fB\-mno\-mulhw\fR" 4 +.IX Item "-mno-mulhw" +.PD +Generate code that uses (does not use) the half-word multiply and +multiply-accumulate instructions on the \s-1IBM 405, 440, 464\s0 and 476 processors. +These instructions are generated by default when targeting those +processors. +.IP "\fB\-mdlmzb\fR" 4 +.IX Item "-mdlmzb" +.PD 0 +.IP "\fB\-mno\-dlmzb\fR" 4 +.IX Item "-mno-dlmzb" +.PD +Generate code that uses (does not use) the string-search \fBdlmzb\fR +instruction on the \s-1IBM 405, 440, 464\s0 and 476 processors. This instruction is +generated by default when targeting those processors. +.IP "\fB\-mno\-bit\-align\fR" 4 +.IX Item "-mno-bit-align" +.PD 0 +.IP "\fB\-mbit\-align\fR" 4 +.IX Item "-mbit-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) force structures +and unions that contain bit-fields to be aligned to the base type of the +bit-field. +.Sp +For example, by default a structure containing nothing but 8 +\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 is aligned to a 4\-byte +boundary and has a size of 4 bytes. By using \fB\-mno\-bit\-align\fR, +the structure is aligned to a 1\-byte boundary and is 1 byte in +size. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +unaligned memory references are handled by the system. +.IP "\fB\-mrelocatable\fR" 4 +.IX Item "-mrelocatable" +.PD 0 +.IP "\fB\-mno\-relocatable\fR" 4 +.IX Item "-mno-relocatable" +.PD +Generate code that allows (does not allow) a static executable to be +relocated to a different address at run time. A simple embedded +PowerPC system loader should relocate the entire contents of +\&\f(CW\*(C`.got2\*(C'\fR and 4\-byte locations listed in the \f(CW\*(C`.fixup\*(C'\fR section, +a table of 32\-bit addresses generated by this option. For this to +work, all objects linked together must be compiled with +\&\fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR. +\&\fB\-mrelocatable\fR code aligns the stack to an 8\-byte boundary. +.IP "\fB\-mrelocatable\-lib\fR" 4 +.IX Item "-mrelocatable-lib" +.PD 0 +.IP "\fB\-mno\-relocatable\-lib\fR" 4 +.IX Item "-mno-relocatable-lib" +.PD +Like \fB\-mrelocatable\fR, \fB\-mrelocatable\-lib\fR generates a +\&\f(CW\*(C`.fixup\*(C'\fR section to allow static executables to be relocated at +run time, but \fB\-mrelocatable\-lib\fR does not use the smaller stack +alignment of \fB\-mrelocatable\fR. Objects compiled with +\&\fB\-mrelocatable\-lib\fR may be linked with objects compiled with +any combination of the \fB\-mrelocatable\fR options. +.IP "\fB\-mno\-toc\fR" 4 +.IX Item "-mno-toc" +.PD 0 +.IP "\fB\-mtoc\fR" 4 +.IX Item "-mtoc" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +register 2 contains a pointer to a global area pointing to the addresses +used in the program. +.IP "\fB\-mlittle\fR" 4 +.IX Item "-mlittle" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in little-endian mode. The \fB\-mlittle\-endian\fR option is +the same as \fB\-mlittle\fR. +.IP "\fB\-mbig\fR" 4 +.IX Item "-mbig" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in big-endian mode. The \fB\-mbig\-endian\fR option is +the same as \fB\-mbig\fR. +.IP "\fB\-mdynamic\-no\-pic\fR" 4 +.IX Item "-mdynamic-no-pic" +On Darwin and Mac \s-1OS X\s0 systems, compile code so that it is not +relocatable, but that its external references are relocatable. The +resulting code is suitable for applications, but not shared +libraries. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The runtime system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mprioritize\-restricted\-insns=\fR\fIpriority\fR" 4 +.IX Item "-mprioritize-restricted-insns=priority" +This option controls the priority that is assigned to +dispatch-slot restricted instructions during the second scheduling +pass. The argument \fIpriority\fR takes the value \fB0\fR, \fB1\fR, +or \fB2\fR to assign no, highest, or second-highest (respectively) +priority to dispatch-slot restricted +instructions. +.IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4 +.IX Item "-msched-costly-dep=dependence_type" +This option controls which dependences are considered costly +by the target during instruction scheduling. The argument +\&\fIdependence_type\fR takes one of the following values: +.RS 4 +.IP "\fBno\fR" 4 +.IX Item "no" +No dependence is costly. +.IP "\fBall\fR" 4 +.IX Item "all" +All dependences are costly. +.IP "\fBtrue_store_to_load\fR" 4 +.IX Item "true_store_to_load" +A true dependence from store to load is costly. +.IP "\fBstore_to_load\fR" 4 +.IX Item "store_to_load" +Any dependence from store to load is costly. +.IP "\fInumber\fR" 4 +.IX Item "number" +Any dependence for which the latency is greater than or equal to +\&\fInumber\fR is costly. +.RE +.RS 4 +.RE +.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4 +.IX Item "-minsert-sched-nops=scheme" +This option controls which \s-1NOP\s0 insertion scheme is used during +the second scheduling pass. The argument \fIscheme\fR takes one of the +following values: +.RS 4 +.IP "\fBno\fR" 4 +.IX Item "no" +Don't insert NOPs. +.IP "\fBpad\fR" 4 +.IX Item "pad" +Pad with NOPs any dispatch group that has vacant issue slots, +according to the scheduler's grouping. +.IP "\fBregroup_exact\fR" 4 +.IX Item "regroup_exact" +Insert NOPs to force costly dependent insns into +separate groups. Insert exactly as many NOPs as needed to force an insn +to a new group, according to the estimated processor grouping. +.IP "\fInumber\fR" 4 +.IX Item "number" +Insert NOPs to force costly dependent insns into +separate groups. Insert \fInumber\fR NOPs to force an insn to a new group. +.RE +.RS 4 +.RE +.IP "\fB\-mcall\-sysv\fR" 4 +.IX Item "-mcall-sysv" +On System V.4 and embedded PowerPC systems compile code using calling +conventions that adhere to the March 1995 draft of the System V +Application Binary Interface, PowerPC processor supplement. This is the +default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR. +.IP "\fB\-mcall\-sysv\-eabi\fR" 4 +.IX Item "-mcall-sysv-eabi" +.PD 0 +.IP "\fB\-mcall\-eabi\fR" 4 +.IX Item "-mcall-eabi" +.PD +Specify both \fB\-mcall\-sysv\fR and \fB\-meabi\fR options. +.IP "\fB\-mcall\-sysv\-noeabi\fR" 4 +.IX Item "-mcall-sysv-noeabi" +Specify both \fB\-mcall\-sysv\fR and \fB\-mno\-eabi\fR options. +.IP "\fB\-mcall\-aixdesc\fR" 4 +.IX Item "-mcall-aixdesc" +On System V.4 and embedded PowerPC systems compile code for the \s-1AIX\s0 +operating system. +.IP "\fB\-mcall\-linux\fR" 4 +.IX Item "-mcall-linux" +On System V.4 and embedded PowerPC systems compile code for the +Linux-based \s-1GNU\s0 system. +.IP "\fB\-mcall\-freebsd\fR" 4 +.IX Item "-mcall-freebsd" +On System V.4 and embedded PowerPC systems compile code for the +FreeBSD operating system. +.IP "\fB\-mcall\-netbsd\fR" 4 +.IX Item "-mcall-netbsd" +On System V.4 and embedded PowerPC systems compile code for the +NetBSD operating system. +.IP "\fB\-mcall\-openbsd\fR" 4 +.IX Item "-mcall-openbsd" +On System V.4 and embedded PowerPC systems compile code for the +OpenBSD operating system. +.IP "\fB\-mtraceback=\fR\fItraceback_type\fR" 4 +.IX Item "-mtraceback=traceback_type" +Select the type of traceback table. Valid values for \fItraceback_type\fR +are \fBfull\fR, \fBpart\fR, and \fBno\fR. +.IP "\fB\-maix\-struct\-return\fR" 4 +.IX Item "-maix-struct-return" +Return all structures in memory (as specified by the \s-1AIX ABI\s0). +.IP "\fB\-msvr4\-struct\-return\fR" 4 +.IX Item "-msvr4-struct-return" +Return structures smaller than 8 bytes in registers (as specified by the +\&\s-1SVR4 ABI\s0). +.IP "\fB\-mabi=\fR\fIabi-type\fR" 4 +.IX Item "-mabi=abi-type" +Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. +Valid values are \fBaltivec\fR, \fBno-altivec\fR, +\&\fBibmlongdouble\fR, \fBieeelongdouble\fR, +\&\fBelfv1\fR, \fBelfv2\fR. +.IP "\fB\-mabi=ibmlongdouble\fR" 4 +.IX Item "-mabi=ibmlongdouble" +Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended-precision long double. +This is not likely to work if your system defaults to using \s-1IEEE\s0 +extended-precision long double. If you change the long double type +from \s-1IEEE\s0 extended-precision, the compiler will issue a warning unless +you use the \fB\-Wno\-psabi\fR option. Requires \fB\-mlong\-double\-128\fR +to be enabled. +.IP "\fB\-mabi=ieeelongdouble\fR" 4 +.IX Item "-mabi=ieeelongdouble" +Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. +This is not likely to work if your system defaults to using \s-1IBM\s0 +extended-precision long double. If you change the long double type +from \s-1IBM\s0 extended-precision, the compiler will issue a warning unless +you use the \fB\-Wno\-psabi\fR option. Requires \fB\-mlong\-double\-128\fR +to be enabled. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI.\s0 +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI.\s0 +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mgnu\-attribute\fR" 4 +.IX Item "-mgnu-attribute" +.PD 0 +.IP "\fB\-mno\-gnu\-attribute\fR" 4 +.IX Item "-mno-gnu-attribute" +.PD +Emit .gnu_attribute assembly directives to set tag/value pairs in a +\&.gnu.attributes section that specify \s-1ABI\s0 variations in function +parameters or return values. +.IP "\fB\-mprototype\fR" 4 +.IX Item "-mprototype" +.PD 0 +.IP "\fB\-mno\-prototype\fR" 4 +.IX Item "-mno-prototype" +.PD +On System V.4 and embedded PowerPC systems assume that all calls to +variable argument functions are properly prototyped. Otherwise, the +compiler must insert an instruction before every non-prototyped call to +set or clear bit 6 of the condition code register (\f(CW\*(C`CR\*(C'\fR) to +indicate whether floating-point values are passed in the floating-point +registers in case the function takes variable arguments. With +\&\fB\-mprototype\fR, only calls to prototyped variable argument functions +set or clear the bit. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +On embedded PowerPC systems, assume that the startup module is called +\&\fIsim\-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and +\&\fIlibc.a\fR. This is the default for \fBpowerpc\-*\-eabisim\fR +configurations. +.IP "\fB\-mmvme\fR" 4 +.IX Item "-mmvme" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mads\fR" 4 +.IX Item "-mads" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-myellowknife\fR" 4 +.IX Item "-myellowknife" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mvxworks\fR" 4 +.IX Item "-mvxworks" +On System V.4 and embedded PowerPC systems, specify that you are +compiling for a VxWorks system. +.IP "\fB\-memb\fR" 4 +.IX Item "-memb" +On embedded PowerPC systems, set the \f(CW\*(C`PPC_EMB\*(C'\fR bit in the \s-1ELF\s0 flags +header to indicate that \fBeabi\fR extended relocations are used. +.IP "\fB\-meabi\fR" 4 +.IX Item "-meabi" +.PD 0 +.IP "\fB\-mno\-eabi\fR" 4 +.IX Item "-mno-eabi" +.PD +On System V.4 and embedded PowerPC systems do (do not) adhere to the +Embedded Applications Binary Interface (\s-1EABI\s0), which is a set of +modifications to the System V.4 specifications. Selecting \fB\-meabi\fR +means that the stack is aligned to an 8\-byte boundary, a function +\&\f(CW\*(C`_\|_eabi\*(C'\fR is called from \f(CW\*(C`main\*(C'\fR to set up the \s-1EABI\s0 +environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and +\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas. Selecting +\&\fB\-mno\-eabi\fR means that the stack is aligned to a 16\-byte boundary, +no \s-1EABI\s0 initialization function is called from \f(CW\*(C`main\*(C'\fR, and the +\&\fB\-msdata\fR option only uses \f(CW\*(C`r13\*(C'\fR to point to a single +small data area. The \fB\-meabi\fR option is on by default if you +configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options. +.IP "\fB\-msdata=eabi\fR" 4 +.IX Item "-msdata=eabi" +On System V.4 and embedded PowerPC systems, put small initialized +\&\f(CW\*(C`const\*(C'\fR global and static data in the \f(CW\*(C`.sdata2\*(C'\fR section, which +is pointed to by register \f(CW\*(C`r2\*(C'\fR. Put small initialized +non\-\f(CW\*(C`const\*(C'\fR global and static data in the \f(CW\*(C`.sdata\*(C'\fR section, +which is pointed to by register \f(CW\*(C`r13\*(C'\fR. Put small uninitialized +global and static data in the \f(CW\*(C`.sbss\*(C'\fR section, which is adjacent to +the \f(CW\*(C`.sdata\*(C'\fR section. The \fB\-msdata=eabi\fR option is +incompatible with the \fB\-mrelocatable\fR option. The +\&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option. +.IP "\fB\-msdata=sysv\fR" 4 +.IX Item "-msdata=sysv" +On System V.4 and embedded PowerPC systems, put small global and static +data in the \f(CW\*(C`.sdata\*(C'\fR section, which is pointed to by register +\&\f(CW\*(C`r13\*(C'\fR. Put small uninitialized global and static data in the +\&\f(CW\*(C`.sbss\*(C'\fR section, which is adjacent to the \f(CW\*(C`.sdata\*(C'\fR section. +The \fB\-msdata=sysv\fR option is incompatible with the +\&\fB\-mrelocatable\fR option. +.IP "\fB\-msdata=default\fR" 4 +.IX Item "-msdata=default" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used, +compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the +same as \fB\-msdata=sysv\fR. +.IP "\fB\-msdata=data\fR" 4 +.IX Item "-msdata=data" +On System V.4 and embedded PowerPC systems, put small global +data in the \f(CW\*(C`.sdata\*(C'\fR section. Put small uninitialized global +data in the \f(CW\*(C`.sbss\*(C'\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR +to address small data however. This is the default behavior unless +other \fB\-msdata\fR options are used. +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +.PD 0 +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD +On embedded PowerPC systems, put all initialized global and static data +in the \f(CW\*(C`.data\*(C'\fR section, and all uninitialized data in the +\&\f(CW\*(C`.bss\*(C'\fR section. +.IP "\fB\-mreadonly\-in\-sdata\fR" 4 +.IX Item "-mreadonly-in-sdata" +Put read-only objects in the \f(CW\*(C`.sdata\*(C'\fR section as well. This is the +default. +.IP "\fB\-mblock\-move\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-move-inline-limit=num" +Inline all block moves (such as calls to \f(CW\*(C`memcpy\*(C'\fR or structure +copies) less than or equal to \fInum\fR bytes. The minimum value for +\&\fInum\fR is 32 bytes on 32\-bit targets and 64 bytes on 64\-bit +targets. The default value is target-specific. +.IP "\fB\-mblock\-compare\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-compare-inline-limit=num" +Generate non-looping inline code for all block compares (such as calls +to \f(CW\*(C`memcmp\*(C'\fR or structure compares) less than or equal to \fInum\fR +bytes. If \fInum\fR is 0, all inline expansion (non-loop and loop) of +block compare is disabled. The default value is target-specific. +.IP "\fB\-mblock\-compare\-inline\-loop\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-compare-inline-loop-limit=num" +Generate an inline expansion using loop code for all block compares that +are less than or equal to \fInum\fR bytes, but greater than the limit +for non-loop inline block compare expansion. If the block length is not +constant, at most \fInum\fR bytes will be compared before \f(CW\*(C`memcmp\*(C'\fR +is called to compare the remainder of the block. The default value is +target-specific. +.IP "\fB\-mstring\-compare\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mstring-compare-inline-limit=num" +Compare at most \fInum\fR string bytes with inline code. +If the difference or end of string is not found at the +end of the inline compare a call to \f(CW\*(C`strcmp\*(C'\fR or \f(CW\*(C`strncmp\*(C'\fR will +take care of the rest of the comparison. The default is 64 bytes. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +On embedded PowerPC systems, put global and static items less than or +equal to \fInum\fR bytes into the small data or \s-1BSS\s0 sections instead of +the normal data or \s-1BSS\s0 section. By default, \fInum\fR is 8. The +\&\fB\-G\fR \fInum\fR switch is also passed to the linker. +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +.IP "\fB\-mregnames\fR" 4 +.IX Item "-mregnames" +.PD 0 +.IP "\fB\-mno\-regnames\fR" 4 +.IX Item "-mno-regnames" +.PD +On System V.4 and embedded PowerPC systems do (do not) emit register +names in the assembly language output using symbolic forms. +.IP "\fB\-mlongcall\fR" 4 +.IX Item "-mlongcall" +.PD 0 +.IP "\fB\-mno\-longcall\fR" 4 +.IX Item "-mno-longcall" +.PD +By default assume that all calls are far away so that a longer and more +expensive calling sequence is required. This is required for calls +farther than 32 megabytes (33,554,432 bytes) from the current location. +A short call is generated if the compiler knows +the call cannot be that far away. This setting can be overridden by +the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma +longcall(0)\*(C'\fR. +.Sp +Some linkers are capable of detecting out-of-range calls and generating +glue code on the fly. On these systems, long calls are unnecessary and +generate slower code. As of this writing, the \s-1AIX\s0 linker can do this, +as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature +to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well. +.Sp +On PowerPC64 ELFv2 and 32\-bit PowerPC systems with newer \s-1GNU\s0 linkers, +\&\s-1GCC\s0 can generate long calls using an inline \s-1PLT\s0 call sequence (see +\&\fB\-mpltseq\fR). PowerPC with \fB\-mbss\-plt\fR and PowerPC64 +ELFv1 (big-endian) do not support inline \s-1PLT\s0 calls. +.Sp +On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR generates \f(CW\*(C`jbsr +callee, L42\*(C'\fR, plus a \fIbranch island\fR (glue code). The two target +addresses represent the callee and the branch island. The +Darwin/PPC linker prefers the first address and generates a \f(CW\*(C`bl +callee\*(C'\fR if the \s-1PPC\s0 \f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; +otherwise, the linker generates \f(CW\*(C`bl L42\*(C'\fR to call the branch +island. The branch island is appended to the body of the +calling function; it computes the full 32\-bit address of the callee +and jumps to it. +.Sp +On Mach-O (Darwin) systems, this option directs the compiler emit to +the glue for every direct call, and the Darwin linker decides whether +to use or discard it. +.Sp +In the future, \s-1GCC\s0 may ignore all longcall specifications +when the linker is known to generate glue. +.IP "\fB\-mpltseq\fR" 4 +.IX Item "-mpltseq" +.PD 0 +.IP "\fB\-mno\-pltseq\fR" 4 +.IX Item "-mno-pltseq" +.PD +Implement (do not implement) \-fno\-plt and long calls using an inline +\&\s-1PLT\s0 call sequence that supports lazy linking and long calls to +functions in dlopen'd shared libraries. Inline \s-1PLT\s0 calls are only +supported on PowerPC64 ELFv2 and 32\-bit PowerPC systems with newer \s-1GNU\s0 +linkers, and are enabled by default if the support is detected when +configuring \s-1GCC,\s0 and, in the case of 32\-bit PowerPC, if \s-1GCC\s0 is +configured with \fB\-\-enable\-secureplt\fR. \fB\-mpltseq\fR code +and \fB\-mbss\-plt\fR 32\-bit PowerPC relocatable objects may not be +linked together. +.IP "\fB\-mtls\-markers\fR" 4 +.IX Item "-mtls-markers" +.PD 0 +.IP "\fB\-mno\-tls\-markers\fR" 4 +.IX Item "-mno-tls-markers" +.PD +Mark (do not mark) calls to \f(CW\*(C`_\|_tls_get_addr\*(C'\fR with a relocation +specifying the function argument. The relocation allows the linker to +reliably associate function call with argument setup instructions for +\&\s-1TLS\s0 optimization, which in turn allows \s-1GCC\s0 to better schedule the +sequence. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +.PD 0 +.IP "\fB\-mno\-recip\fR" 4 +.IX Item "-mno-recip" +.PD +This option enables use of the reciprocal estimate and +reciprocal square root estimate instructions with additional +Newton-Raphson steps to increase precision instead of doing a divide or +square root and divide for floating-point arguments. You should use +the \fB\-ffast\-math\fR option when using \fB\-mrecip\fR (or at +least \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-ffinite\-math\-only\fR, \fB\-freciprocal\-math\fR and +\&\fB\-fno\-trapping\-math\fR). Note that while the throughput of the +sequence is generally higher than the throughput of the non-reciprocal +instruction, the precision of the sequence can be decreased by up to 2 +ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square +roots. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option controls which reciprocal estimate instructions +may be used. \fIopt\fR is a comma-separated list of options, which may +be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all estimate instructions. +.IP "\fBdefault\fR" 4 +.IX Item "default" +Enable the default instructions, equivalent to \fB\-mrecip\fR. +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR. +.IP "\fBdiv\fR" 4 +.IX Item "div" +Enable the reciprocal approximation instructions for both +single and double precision. +.IP "\fBdivf\fR" 4 +.IX Item "divf" +Enable the single-precision reciprocal approximation instructions. +.IP "\fBdivd\fR" 4 +.IX Item "divd" +Enable the double-precision reciprocal approximation instructions. +.IP "\fBrsqrt\fR" 4 +.IX Item "rsqrt" +Enable the reciprocal square root approximation instructions for both +single and double precision. +.IP "\fBrsqrtf\fR" 4 +.IX Item "rsqrtf" +Enable the single-precision reciprocal square root approximation instructions. +.IP "\fBrsqrtd\fR" 4 +.IX Item "rsqrtd" +Enable the double-precision reciprocal square root approximation instructions. +.RE +.RS 4 +.Sp +So, for example, \fB\-mrecip=all,!rsqrtd\fR enables +all of the reciprocal estimate instructions, except for the +\&\f(CW\*(C`FRSQRTE\*(C'\fR, \f(CW\*(C`XSRSQRTEDP\*(C'\fR, and \f(CW\*(C`XVRSQRTEDP\*(C'\fR instructions +which handle the double-precision reciprocal square root calculations. +.RE +.IP "\fB\-mrecip\-precision\fR" 4 +.IX Item "-mrecip-precision" +.PD 0 +.IP "\fB\-mno\-recip\-precision\fR" 4 +.IX Item "-mno-recip-precision" +.PD +Assume (do not assume) that the reciprocal estimate instructions +provide higher-precision estimates than is mandated by the PowerPC +\&\s-1ABI.\s0 Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or +\&\fB\-mcpu=power8\fR automatically selects \fB\-mrecip\-precision\fR. +The double-precision square root estimate instructions are not generated by +default on low-precision machines, since they do not provide an +estimate that converges after three steps. +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. The only type supported at present is \fBmass\fR, +which specifies to use \s-1IBM\s0's Mathematical Acceleration Subsystem +(\s-1MASS\s0) libraries for vectorizing intrinsics using external libraries. +\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR, +\&\f(CW\*(C`acoshd2\*(C'\fR, \f(CW\*(C`acoshf4\*(C'\fR, \f(CW\*(C`asind2\*(C'\fR, \f(CW\*(C`asinf4\*(C'\fR, +\&\f(CW\*(C`asinhd2\*(C'\fR, \f(CW\*(C`asinhf4\*(C'\fR, \f(CW\*(C`atan2d2\*(C'\fR, \f(CW\*(C`atan2f4\*(C'\fR, +\&\f(CW\*(C`atand2\*(C'\fR, \f(CW\*(C`atanf4\*(C'\fR, \f(CW\*(C`atanhd2\*(C'\fR, \f(CW\*(C`atanhf4\*(C'\fR, +\&\f(CW\*(C`cbrtd2\*(C'\fR, \f(CW\*(C`cbrtf4\*(C'\fR, \f(CW\*(C`cosd2\*(C'\fR, \f(CW\*(C`cosf4\*(C'\fR, +\&\f(CW\*(C`coshd2\*(C'\fR, \f(CW\*(C`coshf4\*(C'\fR, \f(CW\*(C`erfcd2\*(C'\fR, \f(CW\*(C`erfcf4\*(C'\fR, +\&\f(CW\*(C`erfd2\*(C'\fR, \f(CW\*(C`erff4\*(C'\fR, \f(CW\*(C`exp2d2\*(C'\fR, \f(CW\*(C`exp2f4\*(C'\fR, +\&\f(CW\*(C`expd2\*(C'\fR, \f(CW\*(C`expf4\*(C'\fR, \f(CW\*(C`expm1d2\*(C'\fR, \f(CW\*(C`expm1f4\*(C'\fR, +\&\f(CW\*(C`hypotd2\*(C'\fR, \f(CW\*(C`hypotf4\*(C'\fR, \f(CW\*(C`lgammad2\*(C'\fR, \f(CW\*(C`lgammaf4\*(C'\fR, +\&\f(CW\*(C`log10d2\*(C'\fR, \f(CW\*(C`log10f4\*(C'\fR, \f(CW\*(C`log1pd2\*(C'\fR, \f(CW\*(C`log1pf4\*(C'\fR, +\&\f(CW\*(C`log2d2\*(C'\fR, \f(CW\*(C`log2f4\*(C'\fR, \f(CW\*(C`logd2\*(C'\fR, \f(CW\*(C`logf4\*(C'\fR, +\&\f(CW\*(C`powd2\*(C'\fR, \f(CW\*(C`powf4\*(C'\fR, \f(CW\*(C`sind2\*(C'\fR, \f(CW\*(C`sinf4\*(C'\fR, \f(CW\*(C`sinhd2\*(C'\fR, +\&\f(CW\*(C`sinhf4\*(C'\fR, \f(CW\*(C`sqrtd2\*(C'\fR, \f(CW\*(C`sqrtf4\*(C'\fR, \f(CW\*(C`tand2\*(C'\fR, +\&\f(CW\*(C`tanf4\*(C'\fR, \f(CW\*(C`tanhd2\*(C'\fR, and \f(CW\*(C`tanhf4\*(C'\fR when generating code +for power7. Both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR must also be enabled. The \s-1MASS\s0 +libraries must be specified at link time. +.IP "\fB\-mfriz\fR" 4 +.IX Item "-mfriz" +.PD 0 +.IP "\fB\-mno\-friz\fR" 4 +.IX Item "-mno-friz" +.PD +Generate (do not generate) the \f(CW\*(C`friz\*(C'\fR instruction when the +\&\fB\-funsafe\-math\-optimizations\fR option is used to optimize +rounding of floating-point values to 64\-bit integer and back to floating +point. The \f(CW\*(C`friz\*(C'\fR instruction does not return the same value if +the floating-point number is too large to fit in an integer. +.IP "\fB\-mpointers\-to\-nested\-functions\fR" 4 +.IX Item "-mpointers-to-nested-functions" +.PD 0 +.IP "\fB\-mno\-pointers\-to\-nested\-functions\fR" 4 +.IX Item "-mno-pointers-to-nested-functions" +.PD +Generate (do not generate) code to load up the static chain register +(\f(CW\*(C`r11\*(C'\fR) when calling through a pointer on \s-1AIX\s0 and 64\-bit Linux +systems where a function pointer points to a 3\-word descriptor giving +the function address, \s-1TOC\s0 value to be loaded in register \f(CW\*(C`r2\*(C'\fR, and +static chain value to be loaded in register \f(CW\*(C`r11\*(C'\fR. The +\&\fB\-mpointers\-to\-nested\-functions\fR is on by default. You cannot +call through pointers to nested functions or pointers +to functions compiled in other languages that use the static chain if +you use \fB\-mno\-pointers\-to\-nested\-functions\fR. +.IP "\fB\-msave\-toc\-indirect\fR" 4 +.IX Item "-msave-toc-indirect" +.PD 0 +.IP "\fB\-mno\-save\-toc\-indirect\fR" 4 +.IX Item "-mno-save-toc-indirect" +.PD +Generate (do not generate) code to save the \s-1TOC\s0 value in the reserved +stack location in the function prologue if the function calls through +a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not +saved in the prologue, it is saved just before the call through the +pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC.\s0 +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC.\s0 This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC.\s0 +.Sp +The \fB\-mno\-compat\-align\-parm\fR option is the default. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.IP "\fB\-mstack\-protector\-guard\-symbol=\fR\fIsymbol\fR" 4 +.IX Item "-mstack-protector-guard-symbol=symbol" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for global canary or \fBtls\fR for per-thread +canary in the \s-1TLS\s0 block (the default with \s-1GNU\s0 libc version 2.4 or later). +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which register to use as base register for reading the canary, and from what +offset from that base register. The default for those is as specified in the +relevant \s-1ABI.\s0 \fB\-mstack\-protector\-guard\-symbol=\fR\fIsymbol\fR overrides +the offset with a symbol reference to a canary in the \s-1TLS\s0 block. +.PP +\fI\s-1RX\s0 Options\fR +.IX Subsection "RX Options" +.PP +These command-line options are defined for \s-1RX\s0 targets: +.IP "\fB\-m64bit\-doubles\fR" 4 +.IX Item "-m64bit-doubles" +.PD 0 +.IP "\fB\-m32bit\-doubles\fR" 4 +.IX Item "-m32bit-doubles" +.PD +Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) +or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is +\&\fB\-m32bit\-doubles\fR. \fINote\fR \s-1RX\s0 floating-point hardware only +works on 32\-bit values, which is why the default is +\&\fB\-m32bit\-doubles\fR. +.IP "\fB\-fpu\fR" 4 +.IX Item "-fpu" +.PD 0 +.IP "\fB\-nofpu\fR" 4 +.IX Item "-nofpu" +.PD +Enables (\fB\-fpu\fR) or disables (\fB\-nofpu\fR) the use of \s-1RX\s0 +floating-point hardware. The default is enabled for the \s-1RX600\s0 +series and disabled for the \s-1RX200\s0 series. +.Sp +Floating-point instructions are only generated for 32\-bit floating-point +values, however, so the \s-1FPU\s0 hardware is not used for doubles if the +\&\fB\-m64bit\-doubles\fR option is used. +.Sp +\&\fINote\fR If the \fB\-fpu\fR option is enabled then +\&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. +This is because the \s-1RX FPU\s0 instructions are themselves unsafe. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1RX CPU\s0 to be targeted. Currently three types are +supported, the generic \fB\s-1RX600\s0\fR and \fB\s-1RX200\s0\fR series hardware and +the specific \fB\s-1RX610\s0\fR \s-1CPU.\s0 The default is \fB\s-1RX600\s0\fR. +.Sp +The only difference between \fB\s-1RX600\s0\fR and \fB\s-1RX610\s0\fR is that the +\&\fB\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. +.Sp +The \fB\s-1RX200\s0\fR series does not have a hardware floating-point unit +and so \fB\-nofpu\fR is enabled by default when this type is +selected. +.IP "\fB\-mbig\-endian\-data\fR" 4 +.IX Item "-mbig-endian-data" +.PD 0 +.IP "\fB\-mlittle\-endian\-data\fR" 4 +.IX Item "-mlittle-endian-data" +.PD +Store data (but not code) in the big-endian format. The default is +\&\fB\-mlittle\-endian\-data\fR, i.e. to store data in the little-endian +format. +.IP "\fB\-msmall\-data\-limit=\fR\fIN\fR" 4 +.IX Item "-msmall-data-limit=N" +Specifies the maximum size in bytes of global and static variables +which can be placed into the small data area. Using the small data +area can lead to smaller and faster code, but the size of area is +limited and it is up to the programmer to ensure that the area does +not overflow. Also when the small data area is used one of the \s-1RX\s0's +registers (usually \f(CW\*(C`r13\*(C'\fR) is reserved for use pointing to this +area, so it is no longer available for use by the compiler. This +could result in slower and/or larger code if variables are pushed onto +the stack instead of being held in this register. +.Sp +Note, common variables (variables that have not been initialized) and +constants are not placed into the small data area as they are assigned +to other sections in the output executable. +.Sp +The default value is zero, which disables this feature. Note, this +feature is not enabled by default with higher optimization levels +(\fB\-O2\fR etc) because of the potentially detrimental effects of +reserving a register. It is up to the programmer to experiment and +discover whether this feature is of benefit to their program. See the +description of the \fB\-mpid\fR option for a description of how the +actual register to hold the small data area pointer is chosen. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +.PD 0 +.IP "\fB\-mno\-sim\fR" 4 +.IX Item "-mno-sim" +.PD +Use the simulator runtime. The default is to use the libgloss +board-specific runtime. +.IP "\fB\-mas100\-syntax\fR" 4 +.IX Item "-mas100-syntax" +.PD 0 +.IP "\fB\-mno\-as100\-syntax\fR" 4 +.IX Item "-mno-as100-syntax" +.PD +When generating assembler output use a syntax that is compatible with +Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 +assembler, but it has some restrictions so it is not generated by default. +.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 +.IX Item "-mmax-constant-size=N" +Specifies the maximum size, in bytes, of a constant that can be used as +an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does +allow constants of up to 4 bytes in length to be used in instructions, +a longer value equates to a longer instruction. Thus in some +circumstances it can be beneficial to restrict the size of constants +that are used in instructions. Constants that are too big are instead +placed into a constant pool and referenced via register indirection. +.Sp +The value \fIN\fR can be between 0 and 4. A value of 0 (the default) +or 4 means that constants of any size are allowed. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Enable linker relaxation. Linker relaxation is a process whereby the +linker attempts to reduce the size of a program by finding shorter +versions of various instructions. Disabled by default. +.IP "\fB\-mint\-register=\fR\fIN\fR" 4 +.IX Item "-mint-register=N" +Specify the number of registers to reserve for fast interrupt handler +functions. The value \fIN\fR can be between 0 and 4. A value of 1 +means that register \f(CW\*(C`r13\*(C'\fR is reserved for the exclusive use +of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and +\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and +\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. +A value of 0, the default, does not reserve any registers. +.IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 +.IX Item "-msave-acc-in-interrupts" +Specifies that interrupt handler functions should preserve the +accumulator register. This is only necessary if normal code might use +the accumulator register, for example because it performs 64\-bit +multiplications. The default is to ignore the accumulator as this +makes the interrupt handlers faster. +.IP "\fB\-mpid\fR" 4 +.IX Item "-mpid" +.PD 0 +.IP "\fB\-mno\-pid\fR" 4 +.IX Item "-mno-pid" +.PD +Enables the generation of position independent data. When enabled any +access to constant data is done via an offset from a base address +held in a register. This allows the location of constant data to be +determined at run time without requiring the executable to be +relocated, which is a benefit to embedded applications with tight +memory constraints. Data that can be modified is not affected by this +option. +.Sp +Note, using this feature reserves a register, usually \f(CW\*(C`r13\*(C'\fR, for +the constant data base address. This can result in slower and/or +larger code, especially in complicated functions. +.Sp +The actual register chosen to hold the constant data base address +depends upon whether the \fB\-msmall\-data\-limit\fR and/or the +\&\fB\-mint\-register\fR command-line options are enabled. Starting +with register \f(CW\*(C`r13\*(C'\fR and proceeding downwards, registers are +allocated first to satisfy the requirements of \fB\-mint\-register\fR, +then \fB\-mpid\fR and finally \fB\-msmall\-data\-limit\fR. Thus it +is possible for the small data area register to be \f(CW\*(C`r8\*(C'\fR if both +\&\fB\-mint\-register=4\fR and \fB\-mpid\fR are specified on the +command line. +.Sp +By default this feature is not enabled. The default can be restored +via the \fB\-mno\-pid\fR command-line option. +.IP "\fB\-mno\-warn\-multiple\-fast\-interrupts\fR" 4 +.IX Item "-mno-warn-multiple-fast-interrupts" +.PD 0 +.IP "\fB\-mwarn\-multiple\-fast\-interrupts\fR" 4 +.IX Item "-mwarn-multiple-fast-interrupts" +.PD +Prevents \s-1GCC\s0 from issuing a warning message if it finds more than one +fast interrupt handler when it is compiling a file. The default is to +issue a warning for each extra fast interrupt handler found, as the \s-1RX\s0 +only supports one such interrupt. +.IP "\fB\-mallow\-string\-insns\fR" 4 +.IX Item "-mallow-string-insns" +.PD 0 +.IP "\fB\-mno\-allow\-string\-insns\fR" 4 +.IX Item "-mno-allow-string-insns" +.PD +Enables or disables the use of the string manipulation instructions +\&\f(CW\*(C`SMOVF\*(C'\fR, \f(CW\*(C`SCMPU\*(C'\fR, \f(CW\*(C`SMOVB\*(C'\fR, \f(CW\*(C`SMOVU\*(C'\fR, \f(CW\*(C`SUNTIL\*(C'\fR +\&\f(CW\*(C`SWHILE\*(C'\fR and also the \f(CW\*(C`RMPA\*(C'\fR instruction. These +instructions may prefetch data, which is not safe to do if accessing +an I/O register. (See section 12.2.7 of the \s-1RX62N\s0 Group User's Manual +for more information). +.Sp +The default is to allow these instructions, but it is not possible for +\&\s-1GCC\s0 to reliably detect all circumstances where a string instruction +might be used to access an I/O register, so their use cannot be +disabled automatically. Instead it is reliant upon the programmer to +use the \fB\-mno\-allow\-string\-insns\fR option if their program +accesses I/O space. +.Sp +When the instructions are enabled \s-1GCC\s0 defines the C preprocessor +symbol \f(CW\*(C`_\|_RX_ALLOW_STRING_INSNS_\|_\*(C'\fR, otherwise it defines the +symbol \f(CW\*(C`_\|_RX_DISALLOW_STRING_INSNS_\|_\*(C'\fR. +.IP "\fB\-mjsr\fR" 4 +.IX Item "-mjsr" +.PD 0 +.IP "\fB\-mno\-jsr\fR" 4 +.IX Item "-mno-jsr" +.PD +Use only (or not only) \f(CW\*(C`JSR\*(C'\fR instructions to access functions. +This option can be used when code size exceeds the range of \f(CW\*(C`BSR\*(C'\fR +instructions. Note that \fB\-mno\-jsr\fR does not mean to not use +\&\f(CW\*(C`JSR\*(C'\fR but instead means that any type of branch may be used. +.PP +\&\fINote:\fR The generic \s-1GCC\s0 command-line option \fB\-ffixed\-\fR\fIreg\fR +has special significance to the \s-1RX\s0 port when used with the +\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a +function intended to process fast interrupts. \s-1GCC\s0 ensures +that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR +and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the +corresponding registers have been restricted via the +\&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command-line +options. +.PP +\fIS/390 and zSeries Options\fR +.IX Subsection "S/390 and zSeries Options" +.PP +These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions and registers +for floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR are used to perform floating-point +operations. When \fB\-mhard\-float\fR is specified, the compiler +generates \s-1IEEE\s0 floating-point instructions. This is the default. +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.PD 0 +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +Use (do not use) the hardware decimal-floating-point instructions for +decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is +specified, functions in \fIlibgcc.a\fR are used to perform +decimal-floating-point operations. When \fB\-mhard\-dfp\fR is +specified, the compiler generates decimal-floating-point hardware +instructions. This is the default for \fB\-march=z9\-ec\fR or higher. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default. +.IP "\fB\-mbackchain\fR" 4 +.IX Item "-mbackchain" +.PD 0 +.IP "\fB\-mno\-backchain\fR" 4 +.IX Item "-mno-backchain" +.PD +Store (do not store) the address of the caller's frame as backchain pointer +into the callee's stack frame. +A backchain may be needed to allow debugging using tools that do not understand +\&\s-1DWARF\s0 call frame information. +When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored +at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, +the backchain is placed into the topmost word of the 96/160 byte register +save area. +.Sp +In general, code compiled with \fB\-mbackchain\fR is call-compatible with +code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain +for debugging purposes usually requires that the whole binary is built with +\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not maintain the backchain. +.IP "\fB\-mpacked\-stack\fR" 4 +.IX Item "-mpacked-stack" +.PD 0 +.IP "\fB\-mno\-packed\-stack\fR" 4 +.IX Item "-mno-packed-stack" +.PD +Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is +specified, the compiler uses the all fields of the 96/160 byte register save +area only for their default purpose; unused fields still take up stack space. +When \fB\-mpacked\-stack\fR is specified, register save slots are densely +packed at the top of the register save area; unused space is reused for other +purposes, allowing for more efficient use of the available stack space. +However, when \fB\-mbackchain\fR is also in effect, the topmost word of +the save area is always used to store the backchain, and the return address +register is always saved two words below the backchain. +.Sp +As long as the stack frame backchain is not used, code generated with +\&\fB\-mpacked\-stack\fR is call-compatible with code generated with +\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC 2.95\s0 for +S/390 or zSeries generated code that uses the stack frame backchain at run +time, not just for debugging purposes. Such code is not call-compatible +with code compiled with \fB\-mpacked\-stack\fR. Also, note that the +combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not use the packed stack layout. +.IP "\fB\-msmall\-exec\fR" 4 +.IX Item "-msmall-exec" +.PD 0 +.IP "\fB\-mno\-small\-exec\fR" 4 +.IX Item "-mno-small-exec" +.PD +Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction +to do subroutine calls. +This only works reliably if the total executable size does not +exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, +which does not have this limitation. +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD 0 +.IP "\fB\-m31\fR" 4 +.IX Item "-m31" +.PD +When \fB\-m31\fR is specified, generate code compliant to the +GNU/Linux for S/390 \s-1ABI.\s0 When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI.\s0 This allows \s-1GCC\s0 in +particular to generate 64\-bit instructions. For the \fBs390\fR +targets, the default is \fB\-m31\fR, while the \fBs390x\fR +targets default to \fB\-m64\fR. +.IP "\fB\-mzarch\fR" 4 +.IX Item "-mzarch" +.PD 0 +.IP "\fB\-mesa\fR" 4 +.IX Item "-mesa" +.PD +When \fB\-mzarch\fR is specified, generate code using the +instructions available on z/Architecture. +When \fB\-mesa\fR is specified, generate code using the +instructions available on \s-1ESA/390.\s0 Note that \fB\-mesa\fR is +not possible with \fB\-m64\fR. +When generating code compliant to the GNU/Linux for S/390 \s-1ABI,\s0 +the default is \fB\-mesa\fR. When generating code compliant +to the GNU/Linux for zSeries \s-1ABI,\s0 the default is \fB\-mzarch\fR. +.IP "\fB\-mhtm\fR" 4 +.IX Item "-mhtm" +.PD 0 +.IP "\fB\-mno\-htm\fR" 4 +.IX Item "-mno-htm" +.PD +The \fB\-mhtm\fR option enables a set of builtins making use of +instructions available with the transactional execution facility +introduced with the \s-1IBM\s0 zEnterprise \s-1EC12\s0 machine generation +\&\fBS/390 System z Built-in Functions\fR. +\&\fB\-mhtm\fR is enabled by default when using \fB\-march=zEC12\fR. +.IP "\fB\-mvx\fR" 4 +.IX Item "-mvx" +.PD 0 +.IP "\fB\-mno\-vx\fR" 4 +.IX Item "-mno-vx" +.PD +When \fB\-mvx\fR is specified, generate code using the instructions +available with the vector extension facility introduced with the \s-1IBM\s0 +z13 machine generation. +This option changes the \s-1ABI\s0 for some vector type values with regard to +alignment and calling conventions. In case vector type values are +being used in an ABI-relevant context a \s-1GAS\s0 \fB.gnu_attribute\fR +command will be added to mark the resulting binary with the \s-1ABI\s0 used. +\&\fB\-mvx\fR is enabled by default when using \fB\-march=z13\fR. +.IP "\fB\-mzvector\fR" 4 +.IX Item "-mzvector" +.PD 0 +.IP "\fB\-mno\-zvector\fR" 4 +.IX Item "-mno-zvector" +.PD +The \fB\-mzvector\fR option enables vector language extensions and +builtins using instructions available with the vector extension +facility introduced with the \s-1IBM\s0 z13 machine generation. +This option adds support for \fBvector\fR to be used as a keyword to +define vector type variables and arguments. \fBvector\fR is only +available when \s-1GNU\s0 extensions are enabled. It will not be expanded +when requesting strict standard compliance e.g. with \fB\-std=c99\fR. +In addition to the \s-1GCC\s0 low-level builtins \fB\-mzvector\fR enables +a set of builtins added for compatibility with AltiVec-style +implementations like Power and Cell. In order to make use of these +builtins the header file \fIvecintrin.h\fR needs to be included. +\&\fB\-mzvector\fR is disabled by default. +.IP "\fB\-mmvcle\fR" 4 +.IX Item "-mmvcle" +.PD 0 +.IP "\fB\-mno\-mvcle\fR" 4 +.IX Item "-mno-mvcle" +.PD +Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction +to perform block moves. When \fB\-mno\-mvcle\fR is specified, +use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for +size. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +.PD 0 +.IP "\fB\-mno\-debug\fR" 4 +.IX Item "-mno-debug" +.PD +Print (or do not print) additional debug information when compiling. +The default is to not print debug information. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate code that runs on \fIcpu-type\fR, which is the name of a +system representing a certain processor type. Possible values for +\&\fIcpu-type\fR are \fBz900\fR/\fBarch5\fR, \fBz990\fR/\fBarch6\fR, +\&\fBz9\-109\fR, \fBz9\-ec\fR/\fBarch7\fR, \fBz10\fR/\fBarch8\fR, +\&\fBz196\fR/\fBarch9\fR, \fBzEC12\fR, \fBz13\fR/\fBarch11\fR, +\&\fBz14\fR/\fBarch12\fR, and \fBnative\fR. +.Sp +The default is \fB\-march=z900\fR. +.Sp +Specifying \fBnative\fR as cpu type can be used to select the best +architecture option for the host processor. +\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize the +processor. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, +except for the \s-1ABI\s0 and the set of available instructions. +The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. +The default is the value used for \fB\-march\fR. +.IP "\fB\-mtpf\-trace\fR" 4 +.IX Item "-mtpf-trace" +.PD 0 +.IP "\fB\-mno\-tpf\-trace\fR" 4 +.IX Item "-mno-tpf-trace" +.PD +Generate code that adds (does not add) in \s-1TPF OS\s0 specific branches to trace +routines in the operating system. This option is off by default, even +when compiling for the \s-1TPF OS.\s0 +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default if +hardware floating point is used. +.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 +.IX Item "-mwarn-framesize=framesize" +Emit a warning if the current function exceeds the given frame size. Because +this is a compile-time check it doesn't need to be a real problem when the program +runs. It is intended to identify functions that most probably cause +a stack overflow. It is useful to be used in an environment with limited stack +size e.g. the linux kernel. +.IP "\fB\-mwarn\-dynamicstack\fR" 4 +.IX Item "-mwarn-dynamicstack" +Emit a warning if the function calls \f(CW\*(C`alloca\*(C'\fR or uses dynamically-sized +arrays. This is generally a bad idea with a limited stack size. +.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 +.IX Item "-mstack-guard=stack-guard" +.PD 0 +.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 +.IX Item "-mstack-size=stack-size" +.PD +If these options are provided the S/390 back end emits additional instructions in +the function prologue that trigger a trap if the stack size is \fIstack-guard\fR +bytes above the \fIstack-size\fR (remember that the stack on S/390 grows downward). +If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than +the frame size of the compiled function is chosen. +These options are intended to be used to help debugging stack overflow problems. +The additionally emitted code causes only little overhead and hence can also be +used in production-like systems without greater performance degradation. The given +values have to be exact powers of 2 and \fIstack-size\fR has to be greater than +\&\fIstack-guard\fR without exceeding 64k. +In order to be efficient the extra code makes the assumption that the stack starts +at an address aligned to the value given by \fIstack-size\fR. +The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch=\fR\fIpre-halfwords\fR\fB,\fR\fIpost-halfwords\fR" 4 +.IX Item "-mhotpatch=pre-halfwords,post-halfwords" +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +\&\s-1NOP\s0 instructions (\fIpre-halfwords\fR, maximum 1000000). After +the label, 2 * \fIpost-halfwords\fR bytes are appended, using the +largest \s-1NOP\s0 like instructions the architecture allows (maximum +1000000). +.Sp +If both arguments are zero, hotpatching is disabled. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. +.PP +\fIScore Options\fR +.IX Subsection "Score Options" +.PP +These options are defined for Score implementations: +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Compile code for big-endian mode. This is the default. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Compile code for little-endian mode. +.IP "\fB\-mnhwloop\fR" 4 +.IX Item "-mnhwloop" +Disable generation of \f(CW\*(C`bcnz\*(C'\fR instructions. +.IP "\fB\-muls\fR" 4 +.IX Item "-muls" +Enable generation of unaligned load and store instructions. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mscore5\fR" 4 +.IX Item "-mscore5" +Specify the \s-1SCORE5\s0 as the target architecture. +.IP "\fB\-mscore5u\fR" 4 +.IX Item "-mscore5u" +Specify the \s-1SCORE5U\s0 of the target architecture. +.IP "\fB\-mscore7\fR" 4 +.IX Item "-mscore7" +Specify the \s-1SCORE7\s0 as the target architecture. This is the default. +.IP "\fB\-mscore7d\fR" 4 +.IX Item "-mscore7d" +Specify the \s-1SCORE7D\s0 as the target architecture. +.PP +\fI\s-1SH\s0 Options\fR +.IX Subsection "SH Options" +.PP +These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: +.IP "\fB\-m1\fR" 4 +.IX Item "-m1" +Generate code for the \s-1SH1.\s0 +.IP "\fB\-m2\fR" 4 +.IX Item "-m2" +Generate code for the \s-1SH2.\s0 +.IP "\fB\-m2e\fR" 4 +.IX Item "-m2e" +Generate code for the SH2e. +.IP "\fB\-m2a\-nofpu\fR" 4 +.IX Item "-m2a-nofpu" +Generate code for the SH2a without \s-1FPU,\s0 or for a SH2a\-FPU in such a way +that the floating-point unit is not used. +.IP "\fB\-m2a\-single\-only\fR" 4 +.IX Item "-m2a-single-only" +Generate code for the SH2a\-FPU, in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m2a\-single\fR" 4 +.IX Item "-m2a-single" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m2a\fR" 4 +.IX Item "-m2a" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +double-precision mode by default. +.IP "\fB\-m3\fR" 4 +.IX Item "-m3" +Generate code for the \s-1SH3.\s0 +.IP "\fB\-m3e\fR" 4 +.IX Item "-m3e" +Generate code for the SH3e. +.IP "\fB\-m4\-nofpu\fR" 4 +.IX Item "-m4-nofpu" +Generate code for the \s-1SH4\s0 without a floating-point unit. +.IP "\fB\-m4\-single\-only\fR" 4 +.IX Item "-m4-single-only" +Generate code for the \s-1SH4\s0 with a floating-point unit that only +supports single-precision arithmetic. +.IP "\fB\-m4\-single\fR" 4 +.IX Item "-m4-single" +Generate code for the \s-1SH4\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\fR" 4 +.IX Item "-m4" +Generate code for the \s-1SH4.\s0 +.IP "\fB\-m4\-100\fR" 4 +.IX Item "-m4-100" +Generate code for \s-1SH4\-100.\s0 +.IP "\fB\-m4\-100\-nofpu\fR" 4 +.IX Item "-m4-100-nofpu" +Generate code for \s-1SH4\-100\s0 in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-100\-single\fR" 4 +.IX Item "-m4-100-single" +Generate code for \s-1SH4\-100\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\-100\-single\-only\fR" 4 +.IX Item "-m4-100-single-only" +Generate code for \s-1SH4\-100\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-200\fR" 4 +.IX Item "-m4-200" +Generate code for \s-1SH4\-200.\s0 +.IP "\fB\-m4\-200\-nofpu\fR" 4 +.IX Item "-m4-200-nofpu" +Generate code for \s-1SH4\-200\s0 without in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-200\-single\fR" 4 +.IX Item "-m4-200-single" +Generate code for \s-1SH4\-200\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\-200\-single\-only\fR" 4 +.IX Item "-m4-200-single-only" +Generate code for \s-1SH4\-200\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-300\fR" 4 +.IX Item "-m4-300" +Generate code for \s-1SH4\-300.\s0 +.IP "\fB\-m4\-300\-nofpu\fR" 4 +.IX Item "-m4-300-nofpu" +Generate code for \s-1SH4\-300\s0 without in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-300\-single\fR" 4 +.IX Item "-m4-300-single" +Generate code for \s-1SH4\-300\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-300\-single\-only\fR" 4 +.IX Item "-m4-300-single-only" +Generate code for \s-1SH4\-300\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-340\fR" 4 +.IX Item "-m4-340" +Generate code for \s-1SH4\-340\s0 (no \s-1MMU,\s0 no \s-1FPU\s0). +.IP "\fB\-m4\-500\fR" 4 +.IX Item "-m4-500" +Generate code for \s-1SH4\-500\s0 (no \s-1FPU\s0). Passes \fB\-isa=sh4\-nofpu\fR to the +assembler. +.IP "\fB\-m4a\-nofpu\fR" 4 +.IX Item "-m4a-nofpu" +Generate code for the SH4al\-dsp, or for a SH4a in such a way that the +floating-point unit is not used. +.IP "\fB\-m4a\-single\-only\fR" 4 +.IX Item "-m4a-single-only" +Generate code for the SH4a, in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4a\-single\fR" 4 +.IX Item "-m4a-single" +Generate code for the SH4a assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4a\fR" 4 +.IX Item "-m4a" +Generate code for the SH4a. +.IP "\fB\-m4al\fR" 4 +.IX Item "-m4al" +Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes +\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 +instructions at the moment. +.IP "\fB\-mb\fR" 4 +.IX Item "-mb" +Compile code for the processor in big-endian mode. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Compile code for the processor in little-endian mode. +.IP "\fB\-mdalign\fR" 4 +.IX Item "-mdalign" +Align doubles at 64\-bit boundaries. Note that this changes the calling +conventions, and thus some functions from the standard C library do +not work unless you recompile it first with \fB\-mdalign\fR. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mbigtable\fR" 4 +.IX Item "-mbigtable" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enable the use of bit manipulation instructions on \s-1SH2A.\s0 +.IP "\fB\-mfmovd\fR" 4 +.IX Item "-mfmovd" +Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for +alignment constraints. +.IP "\fB\-mrenesas\fR" 4 +.IX Item "-mrenesas" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mno\-renesas\fR" 4 +.IX Item "-mno-renesas" +Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas +conventions were available. This option is the default for all +targets of the \s-1SH\s0 toolchain. +.IP "\fB\-mnomacsave\fR" 4 +.IX Item "-mnomacsave" +Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if +\&\fB\-mrenesas\fR is given. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +.PD 0 +.IP "\fB\-mno\-ieee\fR" 4 +.IX Item "-mno-ieee" +.PD +Control the \s-1IEEE\s0 compliance of floating-point comparisons, which affects the +handling of cases where the result of a comparison is unordered. By default +\&\fB\-mieee\fR is implicitly enabled. If \fB\-ffinite\-math\-only\fR is +enabled \fB\-mno\-ieee\fR is implicitly set, which results in faster +floating-point greater-equal and less-equal comparisons. The implicit settings +can be overridden by specifying either \fB\-mieee\fR or \fB\-mno\-ieee\fR. +.IP "\fB\-minline\-ic_invalidate\fR" 4 +.IX Item "-minline-ic_invalidate" +Inline code to invalidate instruction cache entries after setting up +nested function trampolines. +This option has no effect if \fB\-musermode\fR is in effect and the selected +code generation option (e.g. \fB\-m4\fR) does not allow the use of the \f(CW\*(C`icbi\*(C'\fR +instruction. +If the selected code generation option does not allow the use of the \f(CW\*(C`icbi\*(C'\fR +instruction, and \fB\-musermode\fR is not in effect, the inlined code +manipulates the instruction cache address array directly with an associative +write. This not only requires privileged mode at run time, but it also +fails if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Dump instruction size and location in the assembly code. +.IP "\fB\-mpadstruct\fR" 4 +.IX Item "-mpadstruct" +This option is deprecated. It pads structures to multiple of 4 bytes, +which is incompatible with the \s-1SH ABI.\s0 +.IP "\fB\-matomic\-model=\fR\fImodel\fR" 4 +.IX Item "-matomic-model=model" +Sets the model of atomic operations and additional parameters as a comma +separated list. For details on the atomic built-in functions see +\&\fB_\|_atomic Builtins\fR. The following models and parameters are supported: +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable compiler generated atomic sequences and emit library calls for atomic +operations. This is the default if the target is not \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. +.IP "\fBsoft-gusa\fR" 4 +.IX Item "soft-gusa" +Generate GNU/Linux compatible gUSA software atomic sequences for the atomic +built-in functions. The generated atomic sequences require additional support +from the interrupt/exception handling code of the system and are only suitable +for SH3* and SH4* single-core systems. This option is enabled by default when +the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A,\s0 +this option also partially utilizes the hardware atomic instructions +\&\f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR to create more efficient code, unless +\&\fBstrict\fR is specified. +.IP "\fBsoft-tcb\fR" 4 +.IX Item "soft-tcb" +Generate software atomic sequences that use a variable in the thread control +block. This is a variation of the gUSA sequences which can also be used on +SH1* and SH2* targets. The generated atomic sequences require additional +support from the interrupt/exception handling code of the system and are only +suitable for single-core systems. When using this model, the \fBgbr\-offset=\fR +parameter has to be specified as well. +.IP "\fBsoft-imask\fR" 4 +.IX Item "soft-imask" +Generate software atomic sequences that temporarily disable interrupts by +setting \f(CW\*(C`SR.IMASK = 1111\*(C'\fR. This model works only when the program runs +in privileged mode and is only suitable for single-core systems. Additional +support from the interrupt/exception handling code of the system is not +required. This model is enabled by default when the target is +\&\f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH1* or SH2*. +.IP "\fBhard-llcs\fR" 4 +.IX Item "hard-llcs" +Generate hardware atomic sequences using the \f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR +instructions only. This is only available on \s-1SH4A\s0 and is suitable for +multi-core systems. Since the hardware instructions support only 32 bit atomic +variables access to 8 or 16 bit variables is emulated with 32 bit accesses. +Code compiled with this option is also compatible with other software +atomic model interrupt/exception handling systems if executed on an \s-1SH4A\s0 +system. Additional support from the interrupt/exception handling code of the +system is not required for this model. +.IP "\fBgbr\-offset=\fR" 4 +.IX Item "gbr-offset=" +This parameter specifies the offset in bytes of the variable in the thread +control block structure that should be used by the generated atomic sequences +when the \fBsoft-tcb\fR model has been selected. For other models this +parameter is ignored. The specified value must be an integer multiple of four +and in the range 0\-1020. +.IP "\fBstrict\fR" 4 +.IX Item "strict" +This parameter prevents mixed usage of multiple atomic models, even if they +are compatible, and makes the compiler generate atomic sequences of the +specified model only. +.RE +.RS 4 +.RE +.IP "\fB\-mtas\fR" 4 +.IX Item "-mtas" +Generate the \f(CW\*(C`tas.b\*(C'\fR opcode for \f(CW\*(C`_\|_atomic_test_and_set\*(C'\fR. +Notice that depending on the particular hardware and software configuration +this can degrade overall performance due to the operand cache line flushes +that are implied by the \f(CW\*(C`tas.b\*(C'\fR instruction. On multi-core \s-1SH4A\s0 +processors the \f(CW\*(C`tas.b\*(C'\fR instruction must be used with caution since it +can result in data corruption for certain cache configurations. +.IP "\fB\-mprefergot\fR" 4 +.IX Item "-mprefergot" +When generating position-independent code, emit function calls using +the Global Offset Table instead of the Procedure Linkage Table. +.IP "\fB\-musermode\fR" 4 +.IX Item "-musermode" +.PD 0 +.IP "\fB\-mno\-usermode\fR" 4 +.IX Item "-mno-usermode" +.PD +Don't allow (allow) the compiler generating privileged mode code. Specifying +\&\fB\-musermode\fR also implies \fB\-mno\-inline\-ic_invalidate\fR if the +inlined code would not work in user mode. \fB\-musermode\fR is the default +when the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. If the target is SH1* or SH2* +\&\fB\-musermode\fR has no effect, since there is no user mode. +.IP "\fB\-multcost=\fR\fInumber\fR" 4 +.IX Item "-multcost=number" +Set the cost to assume for a multiply insn. +.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 +.IX Item "-mdiv=strategy" +Set the division strategy to be used for integer division operations. +\&\fIstrategy\fR can be one of: +.RS 4 +.IP "\fBcall\-div1\fR" 4 +.IX Item "call-div1" +Calls a library function that uses the single-step division instruction +\&\f(CW\*(C`div1\*(C'\fR to perform the operation. Division by zero calculates an +unspecified result and does not trap. This is the default except for \s-1SH4, +SH2A\s0 and SHcompact. +.IP "\fBcall-fp\fR" 4 +.IX Item "call-fp" +Calls a library function that performs the operation in double precision +floating point. Division by zero causes a floating-point exception. This is +the default for SHcompact with \s-1FPU.\s0 Specifying this for targets that do not +have a double precision \s-1FPU\s0 defaults to \f(CW\*(C`call\-div1\*(C'\fR. +.IP "\fBcall-table\fR" 4 +.IX Item "call-table" +Calls a library function that uses a lookup table for small divisors and +the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division +by zero calculates an unspecified result and does not trap. This is the default +for \s-1SH4.\s0 Specifying this for targets that do not have dynamic shift +instructions defaults to \f(CW\*(C`call\-div1\*(C'\fR. +.RE +.RS 4 +.Sp +When a division strategy has not been specified the default strategy is +selected based on the current target. For \s-1SH2A\s0 the default strategy is to +use the \f(CW\*(C`divs\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions instead of library function +calls. +.RE +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +Reserve space once for outgoing arguments in the function prologue rather +than around each call. Generally beneficial for performance and size. Also +needed for unwinding to avoid changing the stack frame around conditional code. +.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 +.IX Item "-mdivsi3_libfunc=name" +Set the name of the library function used for 32\-bit signed division to +\&\fIname\fR. +This only affects the name used in the \fBcall\fR division strategies, and +the compiler still expects the same sets of input/output/clobbered registers as +if this option were not present. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 +.IX Item "-mbranch-cost=num" +Assume \fInum\fR to be the cost for a branch instruction. Higher numbers +make the compiler try to generate more branch-free code if possible. +If not specified the value is selected depending on the processor type that +is being compiled for. +.IP "\fB\-mzdcbranch\fR" 4 +.IX Item "-mzdcbranch" +.PD 0 +.IP "\fB\-mno\-zdcbranch\fR" 4 +.IX Item "-mno-zdcbranch" +.PD +Assume (do not assume) that zero displacement conditional branch instructions +\&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the +compiler prefers zero displacement branch code sequences. This is +enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A.\s0 It can be explicitly +disabled by specifying \fB\-mno\-zdcbranch\fR. +.IP "\fB\-mcbranch\-force\-delay\-slot\fR" 4 +.IX Item "-mcbranch-force-delay-slot" +Force the usage of delay slots for conditional branches, which stuffs the delay +slot with a \f(CW\*(C`nop\*(C'\fR if a suitable instruction cannot be found. By default +this option is disabled. It can be enabled to work around hardware bugs as +found in the original \s-1SH7055.\s0 +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine-dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mfsca\fR" 4 +.IX Item "-mfsca" +.PD 0 +.IP "\fB\-mno\-fsca\fR" 4 +.IX Item "-mno-fsca" +.PD +Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine +and cosine approximations. The option \fB\-mfsca\fR must be used in +combination with \fB\-funsafe\-math\-optimizations\fR. It is enabled by default +when generating code for \s-1SH4A.\s0 Using \fB\-mno\-fsca\fR disables sine and cosine +approximations even if \fB\-funsafe\-math\-optimizations\fR is in effect. +.IP "\fB\-mfsrra\fR" 4 +.IX Item "-mfsrra" +.PD 0 +.IP "\fB\-mno\-fsrra\fR" 4 +.IX Item "-mno-fsrra" +.PD +Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction for +reciprocal square root approximations. The option \fB\-mfsrra\fR must be used +in combination with \fB\-funsafe\-math\-optimizations\fR and +\&\fB\-ffinite\-math\-only\fR. It is enabled by default when generating code for +\&\s-1SH4A.\s0 Using \fB\-mno\-fsrra\fR disables reciprocal square root approximations +even if \fB\-funsafe\-math\-optimizations\fR and \fB\-ffinite\-math\-only\fR are +in effect. +.IP "\fB\-mpretend\-cmove\fR" 4 +.IX Item "-mpretend-cmove" +Prefer zero-displacement conditional branches for conditional move instruction +patterns. This can result in faster code on the \s-1SH4\s0 processor. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Generate code using the \s-1FDPIC ABI.\s0 +.PP +\fISolaris 2 Options\fR +.IX Subsection "Solaris 2 Options" +.PP +These \fB\-m\fR options are supported on Solaris 2: +.IP "\fB\-mclear\-hwcap\fR" 4 +.IX Item "-mclear-hwcap" +\&\fB\-mclear\-hwcap\fR tells the compiler to remove the hardware +capabilities generated by the Solaris assembler. This is only necessary +when object files use \s-1ISA\s0 extensions not supported by the current +machine, but check at runtime whether or not to use them. +.IP "\fB\-mimpure\-text\fR" 4 +.IX Item "-mimpure-text" +\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells +the compiler to not pass \fB\-z text\fR to the linker when linking a +shared object. Using this option, you can link position-dependent +code into a shared object. +.Sp +\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against +allocatable but non-writable sections\*(R" linker error message. +However, the necessary relocations trigger copy-on-write, and the +shared object is not actually shared across processes. Instead of +using \fB\-mimpure\-text\fR, you should compile all source code with +\&\fB\-fpic\fR or \fB\-fPIC\fR. +.PP +These switches are supported in addition to the above on Solaris 2: +.IP "\fB\-pthreads\fR" 4 +.IX Item "-pthreads" +This is a synonym for \fB\-pthread\fR. +.PP +\fI\s-1SPARC\s0 Options\fR +.IX Subsection "SPARC Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPARC:\s0 +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +.PD 0 +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +.PD +Specify \fB\-mapp\-regs\fR to generate output using the global registers +2 through 4, which the \s-1SPARC SVR4 ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. +.Sp +To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, +specify \fB\-mno\-app\-regs\fR. You should compile libraries and system +software with this option. +.IP "\fB\-mflat\fR" 4 +.IX Item "-mflat" +.PD 0 +.IP "\fB\-mno\-flat\fR" 4 +.IX Item "-mno-flat" +.PD +With \fB\-mflat\fR, the compiler does not generate save/restore instructions +and uses a \*(L"flat\*(R" or single register window model. This model is compatible +with the regular register window model. The local registers and the input +registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and are +saved on the stack as needed. +.Sp +With \fB\-mno\-flat\fR (the default), the compiler generates save/restore +instructions (except for leaf functions). This is the normal operating mode. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing floating-point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and +\&\fBsparclite\-*\-*\fR do provide software floating-point support. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mhard\-quad\-float\fR" 4 +.IX Item "-mhard-quad-float" +Generate output containing quad-word (long double) floating-point +instructions. +.IP "\fB\-msoft\-quad\-float\fR" 4 +.IX Item "-msoft-quad-float" +Generate output containing library calls for quad-word (long double) +floating-point instructions. The functions called are those specified +in the \s-1SPARC ABI.\s0 This is the default. +.Sp +As of this writing, there are no \s-1SPARC\s0 implementations that have hardware +support for the quad-word floating-point instructions. They all invoke +a trap handler for one of these instructions, and then the trap handler +emulates the effect of the instruction. Because of the trap handler overhead, +this is much slower than calling the \s-1ABI\s0 library routines. Thus the +\&\fB\-msoft\-quad\-float\fR option is the default. +.IP "\fB\-mno\-unaligned\-doubles\fR" 4 +.IX Item "-mno-unaligned-doubles" +.PD 0 +.IP "\fB\-munaligned\-doubles\fR" 4 +.IX Item "-munaligned-doubles" +.PD +Assume that doubles have 8\-byte alignment. This is the default. +.Sp +With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8\-byte +alignment only if they are contained in another type, or if they have an +absolute address. Otherwise, it assumes they have 4\-byte alignment. +Specifying this option avoids some rare compatibility problems with code +generated by other compilers. It is not the default because it results +in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. This +is the default. +.IP "\fB\-mfaster\-structs\fR" 4 +.IX Item "-mfaster-structs" +.PD 0 +.IP "\fB\-mno\-faster\-structs\fR" 4 +.IX Item "-mno-faster-structs" +.PD +With \fB\-mfaster\-structs\fR, the compiler assumes that structures +should have 8\-byte alignment. This enables the use of pairs of +\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure +assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. +However, the use of this changed alignment directly violates the \s-1SPARC +ABI.\s0 Thus, it's intended only for use on targets where the developer +acknowledges that their resulting code is not directly in line with +the rules of the \s-1ABI.\s0 +.IP "\fB\-mstd\-struct\-return\fR" 4 +.IX Item "-mstd-struct-return" +.PD 0 +.IP "\fB\-mno\-std\-struct\-return\fR" 4 +.IX Item "-mno-std-struct-return" +.PD +With \fB\-mstd\-struct\-return\fR, the compiler generates checking code +in functions returning structures or unions to detect size mismatches +between the two sides of function calls, as per the 32\-bit \s-1ABI.\s0 +.Sp +The default is \fB\-mno\-std\-struct\-return\fR. This option has no effect +in 64\-bit mode. +.IP "\fB\-mlra\fR" 4 +.IX Item "-mlra" +.PD 0 +.IP "\fB\-mno\-lra\fR" 4 +.IX Item "-mno-lra" +.PD +Enable Local Register Allocation. This is the default for \s-1SPARC\s0 since \s-1GCC 7\s0 +so \fB\-mno\-lra\fR needs to be passed to get old Reload. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, +\&\fBleon\fR, \fBleon3\fR, \fBleon3v7\fR, \fBsparclite\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR, \fBniagara4\fR, \fBniagara7\fR and \fBm8\fR. +.Sp +Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +Default instruction scheduling parameters are used for values that select +an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, +\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. +.Sp +Here is a list of each supported architecture and their supported +implementations. +.RS 4 +.IP "v7" 4 +.IX Item "v7" +cypress, leon3v7 +.IP "v8" 4 +.IX Item "v8" +supersparc, hypersparc, leon, leon3 +.IP "sparclite" 4 +.IX Item "sparclite" +f930, f934, sparclite86x +.IP "sparclet" 4 +.IX Item "sparclet" +tsc701 +.IP "v9" 4 +.IX Item "v9" +ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, +niagara7, m8 +.RE +.RS 4 +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 +variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler +additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the +SPARCStation/SPARCServer 3xx series. This is also appropriate for the older +SPARCStation 1, 2, \s-1IPX\s0 etc. +.Sp +With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 +architecture. The only difference from V7 code is that the compiler emits +the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 +but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=supersparc\fR, the compiler additionally +optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and +2000 series. +.Sp +With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step +and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7.\s0 +With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU.\s0 With +\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu +\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU.\s0 +.Sp +With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, +integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet +but not in \s-1SPARC\-V7.\s0 With \fB\-mcpu=tsc701\fR, the compiler additionally +optimizes it for the \s-1TEMIC\s0 SPARClet chip. +.Sp +With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 +architecture. This adds 64\-bit integer and floating-point move instructions, +3 additional floating-point condition code registers and conditional move +instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally +optimizes it for the Sun UltraSPARC I/II/IIi chips. With +\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the +Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With +\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for +Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler +additionally optimizes it for Sun UltraSPARC T2 chips. With +\&\fB\-mcpu=niagara3\fR, the compiler additionally optimizes it for Sun +UltraSPARC T3 chips. With \fB\-mcpu=niagara4\fR, the compiler +additionally optimizes it for Sun UltraSPARC T4 chips. With +\&\fB\-mcpu=niagara7\fR, the compiler additionally optimizes it for +Oracle \s-1SPARC M7\s0 chips. With \fB\-mcpu=m8\fR, the compiler +additionally optimizes it for Oracle M8 chips. +.RE +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the instruction set or register set that the +option \fB\-mcpu=\fR\fIcpu_type\fR does. +.Sp +The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for +\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those +that select a particular \s-1CPU\s0 implementation. Those are +\&\fBcypress\fR, \fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, +\&\fBleon3\fR, \fBleon3v7\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, +\&\fBniagara4\fR, \fBniagara7\fR and \fBm8\fR. With native Solaris +and GNU/Linux toolchains, \fBnative\fR can also be used. +.IP "\fB\-mv8plus\fR" 4 +.IX Item "-mv8plus" +.PD 0 +.IP "\fB\-mno\-v8plus\fR" 4 +.IX Item "-mno-v8plus" +.PD +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+ ABI.\s0 The +difference from the V8 \s-1ABI\s0 is that the global and out registers are +considered 64 bits wide. This is enabled by default on Solaris in 32\-bit +mode for all \s-1SPARC\-V9\s0 processors. +.IP "\fB\-mvis\fR" 4 +.IX Item "-mvis" +.PD 0 +.IP "\fB\-mno\-vis\fR" 4 +.IX Item "-mno-vis" +.PD +With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. +.IP "\fB\-mvis2\fR" 4 +.IX Item "-mvis2" +.PD 0 +.IP "\fB\-mno\-vis2\fR" 4 +.IX Item "-mno-vis2" +.PD +With \fB\-mvis2\fR, \s-1GCC\s0 generates code that takes advantage of +version 2.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis2\fR when targeting a cpu that supports such +instructions, such as UltraSPARC-III and later. Setting \fB\-mvis2\fR +also sets \fB\-mvis\fR. +.IP "\fB\-mvis3\fR" 4 +.IX Item "-mvis3" +.PD 0 +.IP "\fB\-mno\-vis3\fR" 4 +.IX Item "-mno-vis3" +.PD +With \fB\-mvis3\fR, \s-1GCC\s0 generates code that takes advantage of +version 3.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis3\fR when targeting a cpu that supports such +instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR +also sets \fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mvis4\fR" 4 +.IX Item "-mvis4" +.PD 0 +.IP "\fB\-mno\-vis4\fR" 4 +.IX Item "-mno-vis4" +.PD +With \fB\-mvis4\fR, \s-1GCC\s0 generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis4\fR when targeting a cpu that supports such +instructions, such as niagara\-7 and later. Setting \fB\-mvis4\fR +also sets \fB\-mvis3\fR, \fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mvis4b\fR" 4 +.IX Item "-mvis4b" +.PD 0 +.IP "\fB\-mno\-vis4b\fR" 4 +.IX Item "-mno-vis4b" +.PD +With \fB\-mvis4b\fR, \s-1GCC\s0 generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus +the additional \s-1VIS\s0 instructions introduced in the Oracle \s-1SPARC\s0 +Architecture 2017. The default is \fB\-mvis4b\fR when targeting a +cpu that supports such instructions, such as m8 and later. Setting +\&\fB\-mvis4b\fR also sets \fB\-mvis4\fR, \fB\-mvis3\fR, +\&\fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mcbcond\fR" 4 +.IX Item "-mcbcond" +.PD 0 +.IP "\fB\-mno\-cbcond\fR" 4 +.IX Item "-mno-cbcond" +.PD +With \fB\-mcbcond\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Compare-and-Branch-on-Condition instructions. The default is \fB\-mcbcond\fR +when targeting a \s-1CPU\s0 that supports such instructions, such as Niagara\-4 and +later. +.IP "\fB\-mfmaf\fR" 4 +.IX Item "-mfmaf" +.PD 0 +.IP "\fB\-mno\-fmaf\fR" 4 +.IX Item "-mno-fmaf" +.PD +With \fB\-mfmaf\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Fused Multiply-Add Floating-point instructions. The default is \fB\-mfmaf\fR +when targeting a \s-1CPU\s0 that supports such instructions, such as Niagara\-3 and +later. +.IP "\fB\-mfsmuld\fR" 4 +.IX Item "-mfsmuld" +.PD 0 +.IP "\fB\-mno\-fsmuld\fR" 4 +.IX Item "-mno-fsmuld" +.PD +With \fB\-mfsmuld\fR, \s-1GCC\s0 generates code that takes advantage of the +Floating-point Multiply Single to Double (FsMULd) instruction. The default is +\&\fB\-mfsmuld\fR when targeting a \s-1CPU\s0 supporting the architecture versions V8 +or V9 with \s-1FPU\s0 except \fB\-mcpu=leon\fR. +.IP "\fB\-mpopc\fR" 4 +.IX Item "-mpopc" +.PD 0 +.IP "\fB\-mno\-popc\fR" 4 +.IX Item "-mno-popc" +.PD +With \fB\-mpopc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Population Count instruction. The default is \fB\-mpopc\fR +when targeting a \s-1CPU\s0 that supports such an instruction, such as Niagara\-2 and +later. +.IP "\fB\-msubxc\fR" 4 +.IX Item "-msubxc" +.PD 0 +.IP "\fB\-mno\-subxc\fR" 4 +.IX Item "-mno-subxc" +.PD +With \fB\-msubxc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Subtract-Extended-with-Carry instruction. The default is \fB\-msubxc\fR +when targeting a \s-1CPU\s0 that supports such an instruction, such as Niagara\-7 and +later. +.IP "\fB\-mfix\-at697f\fR" 4 +.IX Item "-mfix-at697f" +Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 +processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. +.IP "\fB\-mfix\-ut700\fR" 4 +.IX Item "-mfix-ut700" +Enable the documented workaround for the back-to-back store errata of +the \s-1UT699E/UT700\s0 processor. +.IP "\fB\-mfix\-gr712rc\fR" 4 +.IX Item "-mfix-gr712rc" +Enable the documented workaround for the back-to-back store errata of +the \s-1GR712RC\s0 processor. +.PP +These \fB\-m\fR options are supported in addition to the above +on \s-1SPARC\-V9\s0 processors in 64\-bit environments: +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. +.IP "\fB\-mcmodel=\fR\fIwhich\fR" 4 +.IX Item "-mcmodel=which" +Set the code model to one of +.RS 4 +.IP "\fBmedlow\fR" 4 +.IX Item "medlow" +The Medium/Low code model: 64\-bit addresses, programs +must be linked in the low 32 bits of memory. Programs can be statically +or dynamically linked. +.IP "\fBmedmid\fR" 4 +.IX Item "medmid" +The Medium/Middle code model: 64\-bit addresses, programs +must be linked in the low 44 bits of memory, the text and data segments must +be less than 2GB in size and the data segment must be located within 2GB of +the text segment. +.IP "\fBmedany\fR" 4 +.IX Item "medany" +The Medium/Anywhere code model: 64\-bit addresses, programs +may be linked anywhere in memory, the text and data segments must be less +than 2GB in size and the data segment must be located within 2GB of the +text segment. +.IP "\fBembmedany\fR" 4 +.IX Item "embmedany" +The Medium/Anywhere code model for embedded systems: +64\-bit addresses, the text and data segments must be less than 2GB in +size, both starting anywhere in memory (determined at link time). The +global register \f(CW%g4\fR points to the base of the data segment. Programs +are statically linked and \s-1PIC\s0 is not supported. +.RE +.RS 4 +.RE +.IP "\fB\-mmemory\-model=\fR\fImem-model\fR" 4 +.IX Item "-mmemory-model=mem-model" +Set the memory model in force on the processor to one of +.RS 4 +.IP "\fBdefault\fR" 4 +.IX Item "default" +The default memory model for the processor and operating system. +.IP "\fBrmo\fR" 4 +.IX Item "rmo" +Relaxed Memory Order +.IP "\fBpso\fR" 4 +.IX Item "pso" +Partial Store Order +.IP "\fBtso\fR" 4 +.IX Item "tso" +Total Store Order +.IP "\fBsc\fR" 4 +.IX Item "sc" +Sequential Consistency +.RE +.RS 4 +.Sp +These memory models are formally defined in Appendix D of the \s-1SPARC\-V9\s0 +architecture manual, as set in the processor's \f(CW\*(C`PSTATE.MM\*(C'\fR field. +.RE +.IP "\fB\-mstack\-bias\fR" 4 +.IX Item "-mstack-bias" +.PD 0 +.IP "\fB\-mno\-stack\-bias\fR" 4 +.IX Item "-mno-stack-bias" +.PD +With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and +frame pointer if present, are offset by \-2047 which must be added back +when making stack frame references. This is the default in 64\-bit mode. +Otherwise, assume no such offset is present. +.PP +\fI\s-1SPU\s0 Options\fR +.IX Subsection "SPU Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPU:\s0 +.IP "\fB\-mwarn\-reloc\fR" 4 +.IX Item "-mwarn-reloc" +.PD 0 +.IP "\fB\-merror\-reloc\fR" 4 +.IX Item "-merror-reloc" +.PD +The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 +gives an error when it generates code that requires a dynamic +relocation. \fB\-mno\-error\-reloc\fR disables the error, +\&\fB\-mwarn\-reloc\fR generates a warning instead. +.IP "\fB\-msafe\-dma\fR" 4 +.IX Item "-msafe-dma" +.PD 0 +.IP "\fB\-munsafe\-dma\fR" 4 +.IX Item "-munsafe-dma" +.PD +Instructions that initiate or test completion of \s-1DMA\s0 must not be +reordered with respect to loads and stores of the memory that is being +accessed. +With \fB\-munsafe\-dma\fR you must use the \f(CW\*(C`volatile\*(C'\fR keyword to protect +memory accesses, but that can lead to inefficient code in places where the +memory is known to not change. Rather than mark the memory as volatile, +you can use \fB\-msafe\-dma\fR to tell the compiler to treat +the \s-1DMA\s0 instructions as potentially affecting all memory. +.IP "\fB\-mbranch\-hints\fR" 4 +.IX Item "-mbranch-hints" +By default, \s-1GCC\s0 generates a branch hint instruction to avoid +pipeline stalls for always-taken or probably-taken branches. A hint +is not generated closer than 8 instructions away from its branch. +There is little reason to disable them, except for debugging purposes, +or to make an object a little bit smaller. +.IP "\fB\-msmall\-mem\fR" 4 +.IX Item "-msmall-mem" +.PD 0 +.IP "\fB\-mlarge\-mem\fR" 4 +.IX Item "-mlarge-mem" +.PD +By default, \s-1GCC\s0 generates code assuming that addresses are never larger +than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes +a full 32\-bit address. +.IP "\fB\-mstdmain\fR" 4 +.IX Item "-mstdmain" +By default, \s-1GCC\s0 links against startup code that assumes the SPU-style +main function interface (which has an unconventional parameter list). +With \fB\-mstdmain\fR, \s-1GCC\s0 links your program against startup +code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a +local copy of \f(CW\*(C`argv\*(C'\fR strings. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mea32\fR" 4 +.IX Item "-mea32" +.PD 0 +.IP "\fB\-mea64\fR" 4 +.IX Item "-mea64" +.PD +Compile code assuming that pointers to the \s-1PPU\s0 address space accessed +via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 +bits wide. The default is 32 bits. As this is an ABI-changing option, +all object code in an executable must be compiled with the same setting. +.IP "\fB\-maddress\-space\-conversion\fR" 4 +.IX Item "-maddress-space-conversion" +.PD 0 +.IP "\fB\-mno\-address\-space\-conversion\fR" 4 +.IX Item "-mno-address-space-conversion" +.PD +Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset +of the generic address space. This enables explicit type casts +between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit +conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The +default is to allow address space pointer conversions. +.IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 +.IX Item "-mcache-size=cache-size" +This option controls the version of libgcc that the compiler links to an +executable and selects a software-managed cache for accessing variables +in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible +options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR +and \fB128\fR. The default cache size is 64KB. +.IP "\fB\-matomic\-updates\fR" 4 +.IX Item "-matomic-updates" +.PD 0 +.IP "\fB\-mno\-atomic\-updates\fR" 4 +.IX Item "-mno-atomic-updates" +.PD +This option controls the version of libgcc that the compiler links to an +executable and selects whether atomic updates to the software-managed +cache of PPU-side variables are used. If you use atomic updates, changes +to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space +qualifier do not interfere with changes to other \s-1PPU\s0 variables residing +in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, +such interference may occur; however, writing back cache lines is +more efficient. The default behavior is to use atomic updates. +.IP "\fB\-mdual\-nops\fR" 4 +.IX Item "-mdual-nops" +.PD 0 +.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 +.IX Item "-mdual-nops=n" +.PD +By default, \s-1GCC\s0 inserts NOPs to increase dual issue when it expects +it to increase performance. \fIn\fR can be a value from 0 to 10. A +smaller \fIn\fR inserts fewer NOPs. 10 is the default, 0 is the +same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. +.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 +.IX Item "-mhint-max-nops=n" +Maximum number of NOPs to insert for a branch hint. A branch hint must +be at least 8 instructions away from the branch it is affecting. \s-1GCC\s0 +inserts up to \fIn\fR NOPs to enforce this, otherwise it does not +generate the branch hint. +.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 +.IX Item "-mhint-max-distance=n" +The encoding of the branch hint instruction limits the hint to be within +256 instructions of the branch it is affecting. By default, \s-1GCC\s0 makes +sure it is within 125. +.IP "\fB\-msafe\-hints\fR" 4 +.IX Item "-msafe-hints" +Work around a hardware bug that causes the \s-1SPU\s0 to stall indefinitely. +By default, \s-1GCC\s0 inserts the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure +this stall won't happen. +.PP +\fIOptions for System V\fR +.IX Subsection "Options for System V" +.PP +These additional options are available on System V Release 4 for +compatibility with other compilers on those systems: +.IP "\fB\-G\fR" 4 +.IX Item "-G" +Create a shared object. +It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. +.IP "\fB\-Qy\fR" 4 +.IX Item "-Qy" +Identify the versions of each tool used by the compiler, in a +\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. +.IP "\fB\-Qn\fR" 4 +.IX Item "-Qn" +Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is +the default). +.IP "\fB\-YP,\fR\fIdirs\fR" 4 +.IX Item "-YP,dirs" +Search the directories \fIdirs\fR, and no others, for libraries +specified with \fB\-l\fR. +.IP "\fB\-Ym,\fR\fIdir\fR" 4 +.IX Item "-Ym,dir" +Look in the directory \fIdir\fR to find the M4 preprocessor. +The assembler uses this option. +.PP +\fITILE-Gx Options\fR +.IX Subsection "TILE-Gx Options" +.PP +These \fB\-m\fR options are supported on the TILE-Gx: +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small model. The distance for direct calls is +limited to 500M in either direction. PC-relative addresses are 32 +bits. Absolute addresses support the full address range. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model. There is no limitation on call +distance, pc-relative addresses, or absolute addresses. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported +type is \fBtilegx\fR. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. The 32\-bit +environment sets int, long, and pointer to 32 bits. The 64\-bit +environment sets int to 32 bits and long and pointer to 64 bits. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +Generate code in big/little endian mode, respectively. +.PP +\fITILEPro Options\fR +.IX Subsection "TILEPro Options" +.PP +These \fB\-m\fR options are supported on the TILEPro: +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported +type is \fBtilepro\fR. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +Generate code for a 32\-bit environment, which sets int, long, and +pointer to 32 bits. This is the only supported behavior so the flag +is essentially ignored. +.PP +\fIV850 Options\fR +.IX Subsection "V850 Options" +.PP +These \fB\-m\fR options are defined for V850 implementations: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler always loads the function's address into a +register, and calls indirect through the pointer. +.IP "\fB\-mno\-ep\fR" 4 +.IX Item "-mno-ep" +.PD 0 +.IP "\fB\-mep\fR" 4 +.IX Item "-mep" +.PD +Do not optimize (do optimize) basic blocks that use the same index +pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and +use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR +option is on by default if you optimize. +.IP "\fB\-mno\-prolog\-function\fR" 4 +.IX Item "-mno-prolog-function" +.PD 0 +.IP "\fB\-mprolog\-function\fR" 4 +.IX Item "-mprolog-function" +.PD +Do not use (do use) external functions to save and restore registers +at the prologue and epilogue of a function. The external functions +are slower, but use less code space if more than one function saves +the same number of registers. The \fB\-mprolog\-function\fR option +is on by default if you optimize. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Try to make the code as small as possible. At present, this just turns +on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. +.IP "\fB\-mtda=\fR\fIn\fR" 4 +.IX Item "-mtda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data +area can hold up to 256 bytes in total (128 bytes for byte references). +.IP "\fB\-msda=\fR\fIn\fR" 4 +.IX Item "-msda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data +area can hold up to 64 kilobytes. +.IP "\fB\-mzda=\fR\fIn\fR" 4 +.IX Item "-mzda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the first 32 kilobytes of memory. +.IP "\fB\-mv850\fR" 4 +.IX Item "-mv850" +Specify that the target processor is the V850. +.IP "\fB\-mv850e3v5\fR" 4 +.IX Item "-mv850e3v5" +Specify that the target processor is the V850E3V5. The preprocessor +constant \f(CW\*(C`_\|_v850e3v5_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e2v4\fR" 4 +.IX Item "-mv850e2v4" +Specify that the target processor is the V850E3V5. This is an alias for +the \fB\-mv850e3v5\fR option. +.IP "\fB\-mv850e2v3\fR" 4 +.IX Item "-mv850e2v3" +Specify that the target processor is the V850E2V3. The preprocessor +constant \f(CW\*(C`_\|_v850e2v3_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e2\fR" 4 +.IX Item "-mv850e2" +Specify that the target processor is the V850E2. The preprocessor +constant \f(CW\*(C`_\|_v850e2_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e1\fR" 4 +.IX Item "-mv850e1" +Specify that the target processor is the V850E1. The preprocessor +constants \f(CW\*(C`_\|_v850e1_\|_\*(C'\fR and \f(CW\*(C`_\|_v850e_\|_\*(C'\fR are defined if +this option is used. +.IP "\fB\-mv850es\fR" 4 +.IX Item "-mv850es" +Specify that the target processor is the V850ES. This is an alias for +the \fB\-mv850e1\fR option. +.IP "\fB\-mv850e\fR" 4 +.IX Item "-mv850e" +Specify that the target processor is the V850E. The preprocessor +constant \f(CW\*(C`_\|_v850e_\|_\*(C'\fR is defined if this option is used. +.Sp +If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR +nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR nor \fB\-mv850e3v5\fR +are defined then a default target processor is chosen and the +relevant \fB_\|_v850*_\|_\fR preprocessor constant is defined. +.Sp +The preprocessor constants \f(CW\*(C`_\|_v850\*(C'\fR and \f(CW\*(C`_\|_v851_\|_\*(C'\fR are always +defined, regardless of which processor variant is the target. +.IP "\fB\-mdisable\-callt\fR" 4 +.IX Item "-mdisable-callt" +.PD 0 +.IP "\fB\-mno\-disable\-callt\fR" 4 +.IX Item "-mno-disable-callt" +.PD +This option suppresses generation of the \f(CW\*(C`CALLT\*(C'\fR instruction for the +v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 +architecture. +.Sp +This option is enabled by default when the \s-1RH850 ABI\s0 is +in use (see \fB\-mrh850\-abi\fR), and disabled by default when the +\&\s-1GCC ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated +then the C preprocessor symbol \f(CW\*(C`_\|_V850_CALLT_\|_\*(C'\fR is defined. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +.PD 0 +.IP "\fB\-mno\-relax\fR" 4 +.IX Item "-mno-relax" +.PD +Pass on (or do not pass on) the \fB\-mrelax\fR command-line option +to the assembler. +.IP "\fB\-mlong\-jumps\fR" 4 +.IX Item "-mlong-jumps" +.PD 0 +.IP "\fB\-mno\-long\-jumps\fR" 4 +.IX Item "-mno-long-jumps" +.PD +Disable (or re-enable) the generation of PC-relative jump instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Disable (or re-enable) the generation of hardware floating point +instructions. This option is only significant when the target +architecture is \fBV850E2V3\fR or higher. If hardware floating point +instructions are being generated then the C preprocessor symbol +\&\f(CW\*(C`_\|_FPU_OK_\|_\*(C'\fR is defined, otherwise the symbol +\&\f(CW\*(C`_\|_NO_FPU_\|_\*(C'\fR is defined. +.IP "\fB\-mloop\fR" 4 +.IX Item "-mloop" +Enables the use of the e3v5 \s-1LOOP\s0 instruction. The use of this +instruction is not enabled by default when the e3v5 architecture is +selected because its use is still experimental. +.IP "\fB\-mrh850\-abi\fR" 4 +.IX Item "-mrh850-abi" +.PD 0 +.IP "\fB\-mghs\fR" 4 +.IX Item "-mghs" +.PD +Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI.\s0 This is the +default. With this version of the \s-1ABI\s0 the following rules apply: +.RS 4 +.IP "*" 4 +Integer sized structures and unions are returned via a memory pointer +rather than a register. +.IP "*" 4 +Large structures and unions (more than 8 bytes in size) are passed by +value. +.IP "*" 4 +Functions are aligned to 16\-bit boundaries. +.IP "*" 4 +The \fB\-m8byte\-align\fR command-line option is supported. +.IP "*" 4 +The \fB\-mdisable\-callt\fR command-line option is enabled by +default. The \fB\-mno\-disable\-callt\fR command-line option is not +supported. +.RE +.RS 4 +.Sp +When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_RH850_ABI_\|_\*(C'\fR is defined. +.RE +.IP "\fB\-mgcc\-abi\fR" 4 +.IX Item "-mgcc-abi" +Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI.\s0 With this +version of the \s-1ABI\s0 the following rules apply: +.RS 4 +.IP "*" 4 +Integer sized structures and unions are returned in register \f(CW\*(C`r10\*(C'\fR. +.IP "*" 4 +Large structures and unions (more than 8 bytes in size) are passed by +reference. +.IP "*" 4 +Functions are aligned to 32\-bit boundaries, unless optimizing for +size. +.IP "*" 4 +The \fB\-m8byte\-align\fR command-line option is not supported. +.IP "*" 4 +The \fB\-mdisable\-callt\fR command-line option is supported but not +enabled by default. +.RE +.RS 4 +.Sp +When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_GCC_ABI_\|_\*(C'\fR is defined. +.RE +.IP "\fB\-m8byte\-align\fR" 4 +.IX Item "-m8byte-align" +.PD 0 +.IP "\fB\-mno\-8byte\-align\fR" 4 +.IX Item "-mno-8byte-align" +.PD +Enables support for \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long long\*(C'\fR types to be +aligned on 8\-byte boundaries. The default is to restrict the +alignment of all objects to at most 4\-bytes. When +\&\fB\-m8byte\-align\fR is in effect the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_8BYTE_ALIGN_\|_\*(C'\fR is defined. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +This option causes r2 and r5 to be used in the code generated by +the compiler. This setting is the default. +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +This option causes r2 and r5 to be treated as fixed registers. +.PP +\fI\s-1VAX\s0 Options\fR +.IX Subsection "VAX Options" +.PP +These \fB\-m\fR options are defined for the \s-1VAX:\s0 +.IP "\fB\-munix\fR" 4 +.IX Item "-munix" +Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) +that the Unix assembler for the \s-1VAX\s0 cannot handle across long +ranges. +.IP "\fB\-mgnu\fR" 4 +.IX Item "-mgnu" +Do output those jump instructions, on the assumption that the +\&\s-1GNU\s0 assembler is being used. +.IP "\fB\-mg\fR" 4 +.IX Item "-mg" +Output code for G\-format floating-point numbers instead of D\-format. +.PP +\fIVisium Options\fR +.IX Subsection "Visium Options" +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +A program which performs file I/O and is destined to run on an \s-1MCM\s0 target +should be linked with this option. It causes the libraries libc.a and +libdebug.a to be linked. The program should be run on the target under +the control of the \s-1GDB\s0 remote debugging stub. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +A program which performs file I/O and is destined to run on the simulator +should be linked with option. This causes libraries libc.a and libsim.a to +be linked. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code containing floating-point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate code containing library calls for floating-point. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBmcm\fR, \fBgr5\fR and \fBgr6\fR. +.Sp +\&\fBmcm\fR is a synonym of \fBgr5\fR present for backward compatibility. +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the \s-1GR5\s0 +variant of the Visium architecture. +.Sp +With \fB\-mcpu=gr6\fR, \s-1GCC\s0 generates code for the \s-1GR6\s0 variant of the Visium +architecture. The only difference from \s-1GR5\s0 code is that the compiler will +generate block move instructions. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type \fIcpu_type\fR, +but do not set the instruction set or register set that the option +\&\fB\-mcpu=\fR\fIcpu_type\fR would. +.IP "\fB\-msv\-mode\fR" 4 +.IX Item "-msv-mode" +Generate code for the supervisor mode, where there are no restrictions on +the access to general registers. This is the default. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +Generate code for the user mode, where the access to some general registers +is forbidden: on the \s-1GR5,\s0 registers r24 to r31 cannot be accessed in this +mode; on the \s-1GR6,\s0 only registers r29 to r31 are affected. +.PP +\fI\s-1VMS\s0 Options\fR +.IX Subsection "VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1VMS\s0 implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from \f(CW\*(C`main\*(C'\fR. The default is to return POSIX-style +condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64\-bit memory allocation routines. +.IP "\fB\-mpointer\-size=\fR\fIsize\fR" 4 +.IX Item "-mpointer-size=size" +Set the default size of pointers. Possible options for \fIsize\fR are +\&\fB32\fR or \fBshort\fR for 32 bit pointers, \fB64\fR or \fBlong\fR +for 64 bit pointers, and \fBno\fR for supporting only 32 bit pointers. +The later option disables \f(CW\*(C`pragma pointer_size\*(C'\fR. +.PP +\fIVxWorks Options\fR +.IX Subsection "VxWorks Options" +.PP +The options in this section are defined for all VxWorks targets. +Options specific to the target hardware are listed with the other +options for that target. +.IP "\fB\-mrtp\fR" 4 +.IX Item "-mrtp" +\&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes +(RTPs). This option switches from the former to the latter. It also +defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. +.IP "\fB\-non\-static\fR" 4 +.IX Item "-non-static" +Link an \s-1RTP\s0 executable against shared libraries rather than static +libraries. The options \fB\-static\fR and \fB\-shared\fR can +also be used for RTPs; \fB\-static\fR +is the default. +.IP "\fB\-Bstatic\fR" 4 +.IX Item "-Bstatic" +.PD 0 +.IP "\fB\-Bdynamic\fR" 4 +.IX Item "-Bdynamic" +.PD +These options are passed down to the linker. They are defined for +compatibility with Diab. +.IP "\fB\-Xbind\-lazy\fR" 4 +.IX Item "-Xbind-lazy" +Enable lazy binding of function calls. This option is equivalent to +\&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. +.IP "\fB\-Xbind\-now\fR" 4 +.IX Item "-Xbind-now" +Disable lazy binding of function calls. This option is the default and +is defined for compatibility with Diab. +.PP +\fIx86 Options\fR +.IX Subsection "x86 Options" +.PP +These \fB\-m\fR options are defined for the x86 family of computers. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate instructions for the machine type \fIcpu-type\fR. In contrast to +\&\fB\-mtune=\fR\fIcpu-type\fR, which merely tunes the generated code +for the specified \fIcpu-type\fR, \fB\-march=\fR\fIcpu-type\fR allows \s-1GCC\s0 +to generate code that may not run at all on processors other than the one +indicated. Specifying \fB\-march=\fR\fIcpu-type\fR implies +\&\fB\-mtune=\fR\fIcpu-type\fR. +.Sp +The choices for \fIcpu-type\fR are: +.RS 4 +.IP "\fBnative\fR" 4 +.IX Item "native" +This selects the \s-1CPU\s0 to generate code for at compilation time by determining +the processor type of the compiling machine. Using \fB\-march=native\fR +enables all instruction subsets supported by the local machine (hence +the result might not run on different machines). Using \fB\-mtune=native\fR +produces code optimized for the local machine under the constraints +of the selected instruction set. +.IP "\fBx86\-64\fR" 4 +.IX Item "x86-64" +A generic \s-1CPU\s0 with 64\-bit extensions. +.IP "\fBi386\fR" 4 +.IX Item "i386" +Original Intel i386 \s-1CPU.\s0 +.IP "\fBi486\fR" 4 +.IX Item "i486" +Intel i486 \s-1CPU.\s0 (No scheduling is implemented for this chip.) +.IP "\fBi586\fR" 4 +.IX Item "i586" +.PD 0 +.IP "\fBpentium\fR" 4 +.IX Item "pentium" +.PD +Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. +.IP "\fBlakemont\fR" 4 +.IX Item "lakemont" +Intel Lakemont \s-1MCU,\s0 based on Intel Pentium \s-1CPU.\s0 +.IP "\fBpentium-mmx\fR" 4 +.IX Item "pentium-mmx" +Intel Pentium \s-1MMX CPU,\s0 based on Pentium core with \s-1MMX\s0 instruction set support. +.IP "\fBpentiumpro\fR" 4 +.IX Item "pentiumpro" +Intel Pentium Pro \s-1CPU.\s0 +.IP "\fBi686\fR" 4 +.IX Item "i686" +When used with \fB\-march\fR, the Pentium Pro +instruction set is used, so the code runs on all i686 family chips. +When used with \fB\-mtune\fR, it has the same meaning as \fBgeneric\fR. +.IP "\fBpentium2\fR" 4 +.IX Item "pentium2" +Intel Pentium \s-1II CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 instruction set +support. +.IP "\fBpentium3\fR" 4 +.IX Item "pentium3" +.PD 0 +.IP "\fBpentium3m\fR" 4 +.IX Item "pentium3m" +.PD +Intel Pentium \s-1III CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction +set support. +.IP "\fBpentium-m\fR" 4 +.IX Item "pentium-m" +Intel Pentium M; low-power version of Intel Pentium \s-1III CPU\s0 +with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks. +.IP "\fBpentium4\fR" 4 +.IX Item "pentium4" +.PD 0 +.IP "\fBpentium4m\fR" 4 +.IX Item "pentium4m" +.PD +Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. +.IP "\fBprescott\fR" 4 +.IX Item "prescott" +Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction +set support. +.IP "\fBnocona\fR" 4 +.IX Item "nocona" +Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, +SSE2\s0 and \s-1SSE3\s0 instruction set support. +.IP "\fBcore2\fR" 4 +.IX Item "core2" +Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fBnehalem\fR" 4 +.IX Item "nehalem" +Intel Nehalem \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2\s0 and \s-1POPCNT\s0 instruction set support. +.IP "\fBwestmere\fR" 4 +.IX Item "westmere" +Intel Westmere \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fBsandybridge\fR" 4 +.IX Item "sandybridge" +Intel Sandy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fBivybridge\fR" 4 +.IX Item "ivybridge" +Intel Ivy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND\s0 and F16C +instruction set support. +.IP "\fBhaswell\fR" 4 +.IX Item "haswell" +Intel Haswell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2\s0 and F16C instruction set support. +.IP "\fBbroadwell\fR" 4 +.IX Item "broadwell" +Intel Broadwell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, +F16C, RDSEED ADCX\s0 and \s-1PREFETCHW\s0 instruction set support. +.IP "\fBskylake\fR" 4 +.IX Item "skylake" +Intel Skylake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC\s0 and \s-1XSAVES\s0 +instruction set support. +.IP "\fBbonnell\fR" 4 +.IX Item "bonnell" +Intel Bonnell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fBsilvermont\fR" 4 +.IX Item "silvermont" +Intel Silvermont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL\s0 and \s-1RDRND\s0 instruction set support. +.IP "\fBgoldmont\fR" 4 +.IX Item "goldmont" +Intel Goldmont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, +XSAVEOPT\s0 and \s-1FSGSBASE\s0 instruction set support. +.IP "\fBgoldmont-plus\fR" 4 +.IX Item "goldmont-plus" +Intel Goldmont Plus \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX\s0 and \s-1UMIP\s0 instruction set support. +.IP "\fBtremont\fR" 4 +.IX Item "tremont" +Intel Tremont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, +XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP,\s0 GFNI-SSE, \s-1CLWB, MOVDIRI, +MOVDIR64B, CLDEMOTE\s0 and \s-1WAITPKG\s0 instruction set support. +.IP "\fBknl\fR" 4 +.IX Item "knl" +Intel Knight's Landing \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF, +AVX512ER\s0 and \s-1AVX512CD\s0 instruction set support. +.IP "\fBknm\fR" 4 +.IX Item "knm" +Intel Knights Mill \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF, +AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS\s0 and \s-1AVX512VPOPCNTDQ\s0 instruction +set support. +.IP "\fBskylake\-avx512\fR" 4 +.IX Item "skylake-avx512" +Intel Skylake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, +CLWB, AVX512VL, AVX512BW, AVX512DQ\s0 and \s-1AVX512CD\s0 instruction set support. +.IP "\fBcannonlake\fR" 4 +.IX Item "cannonlake" +Intel Cannonlake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA\s0 and \s-1UMIP\s0 instruction set support. +.IP "\fBicelake-client\fR" 4 +.IX Item "icelake-client" +Intel Icelake Client \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES\s0 instruction set support. +.IP "\fBicelake-server\fR" 4 +.IX Item "icelake-server" +Intel Icelake Server \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG\s0 and \s-1WBNOINVD\s0 instruction +set support. +.IP "\fBcascadelake\fR" 4 +.IX Item "cascadelake" +Intel Cascadelake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB, +AVX512VL, AVX512BW, AVX512DQ, AVX512CD\s0 and \s-1AVX512VNNI\s0 instruction set support. +.IP "\fBtigerlake\fR" 4 +.IX Item "tigerlake" +Intel Tigerlake \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, +AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, +RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, +VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B\s0 and \s-1CLWB\s0 instruction set support. +.IP "\fBk6\fR" 4 +.IX Item "k6" +\&\s-1AMD K6 CPU\s0 with \s-1MMX\s0 instruction set support. +.IP "\fBk6\-2\fR" 4 +.IX Item "k6-2" +.PD 0 +.IP "\fBk6\-3\fR" 4 +.IX Item "k6-3" +.PD +Improved versions of \s-1AMD K6 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.IP "\fBathlon\fR" 4 +.IX Item "athlon" +.PD 0 +.IP "\fBathlon-tbird\fR" 4 +.IX Item "athlon-tbird" +.PD +\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions +support. +.IP "\fBathlon\-4\fR" 4 +.IX Item "athlon-4" +.PD 0 +.IP "\fBathlon-xp\fR" 4 +.IX Item "athlon-xp" +.IP "\fBathlon-mp\fR" 4 +.IX Item "athlon-mp" +.PD +Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 +instruction set support. +.IP "\fBk8\fR" 4 +.IX Item "k8" +.PD 0 +.IP "\fBopteron\fR" 4 +.IX Item "opteron" +.IP "\fBathlon64\fR" 4 +.IX Item "athlon64" +.IP "\fBathlon-fx\fR" 4 +.IX Item "athlon-fx" +.PD +Processors based on the \s-1AMD K8\s0 core with x86\-64 instruction set support, +including the \s-1AMD\s0 Opteron, Athlon 64, and Athlon 64 \s-1FX\s0 processors. +(This supersets \s-1MMX, SSE, SSE2,\s0 3DNow!, enhanced 3DNow! and 64\-bit +instruction set extensions.) +.IP "\fBk8\-sse3\fR" 4 +.IX Item "k8-sse3" +.PD 0 +.IP "\fBopteron\-sse3\fR" 4 +.IX Item "opteron-sse3" +.IP "\fBathlon64\-sse3\fR" 4 +.IX Item "athlon64-sse3" +.PD +Improved versions of \s-1AMD K8\s0 cores with \s-1SSE3\s0 instruction set support. +.IP "\fBamdfam10\fR" 4 +.IX Item "amdfam10" +.PD 0 +.IP "\fBbarcelona\fR" 4 +.IX Item "barcelona" +.PD +CPUs based on \s-1AMD\s0 Family 10h cores with x86\-64 instruction set support. (This +supersets \s-1MMX, SSE, SSE2, SSE3, SSE4A,\s0 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbdver1\fR" 4 +.IX Item "bdver1" +CPUs based on \s-1AMD\s0 Family 15h cores with x86\-64 instruction set support. (This +supersets \s-1FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set extensions.) +.IP "\fBbdver2\fR" 4 +.IX Item "bdver2" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, +SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set +extensions.) +.IP "\fBbdver3\fR" 4 +.IX Item "bdver3" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,\s0 +\&\s-1PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and +64\-bit instruction set extensions. +.IP "\fBbdver4\fR" 4 +.IX Item "bdver4" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,\s0 +\&\s-1AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,\s0 +\&\s-1SSE4.2, ABM\s0 and 64\-bit instruction set extensions. +.IP "\fBznver1\fR" 4 +.IX Item "znver1" +\&\s-1AMD\s0 Family 17h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, +SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, +SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT,\s0 and 64\-bit +instruction set extensions. +.IP "\fBznver2\fR" 4 +.IX Item "znver2" +\&\s-1AMD\s0 Family 17h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, +MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT,\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbtver1\fR" 4 +.IX Item "btver1" +CPUs based on \s-1AMD\s0 Family 14h cores with x86\-64 instruction set support. (This +supersets \s-1MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbtver2\fR" 4 +.IX Item "btver2" +CPUs based on \s-1AMD\s0 Family 16h cores with x86\-64 instruction set support. This +includes \s-1MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, +SSE4A, SSSE3, SSE3, SSE2, SSE, MMX\s0 and 64\-bit instruction set extensions. +.IP "\fBwinchip\-c6\fR" 4 +.IX Item "winchip-c6" +\&\s-1IDT\s0 WinChip C6 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 instruction +set support. +.IP "\fBwinchip2\fR" 4 +.IX Item "winchip2" +\&\s-1IDT\s0 WinChip 2 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! +instruction set support. +.IP "\fBc3\fR" 4 +.IX Item "c3" +\&\s-1VIA C3 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBc3\-2\fR" 4 +.IX Item "c3-2" +\&\s-1VIA C3\-2\s0 (Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBc7\fR" 4 +.IX Item "c7" +\&\s-1VIA C7\s0 (Esther) \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBsamuel\-2\fR" 4 +.IX Item "samuel-2" +\&\s-1VIA\s0 Eden Samuel 2 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnehemiah\fR" 4 +.IX Item "nehemiah" +\&\s-1VIA\s0 Eden Nehemiah \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBesther\fR" 4 +.IX Item "esther" +\&\s-1VIA\s0 Eden Esther \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBeden\-x2\fR" 4 +.IX Item "eden-x2" +\&\s-1VIA\s0 Eden X2 \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBeden\-x4\fR" 4 +.IX Item "eden-x4" +\&\s-1VIA\s0 Eden X4 \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, +AVX\s0 and \s-1AVX2\s0 instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\fR" 4 +.IX Item "nano" +Generic \s-1VIA\s0 Nano \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-1000\fR" 4 +.IX Item "nano-1000" +\&\s-1VIA\s0 Nano 1xxx \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-2000\fR" 4 +.IX Item "nano-2000" +\&\s-1VIA\s0 Nano 2xxx \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-3000\fR" 4 +.IX Item "nano-3000" +\&\s-1VIA\s0 Nano 3xxx \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3\s0 and \s-1SSE4.1\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-x2\fR" 4 +.IX Item "nano-x2" +\&\s-1VIA\s0 Nano Dual Core \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3\s0 and \s-1SSE4.1\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBnano\-x4\fR" 4 +.IX Item "nano-x4" +\&\s-1VIA\s0 Nano Quad Core \s-1CPU\s0 with x86\-64, \s-1MMX, SSE, SSE2, SSE3, SSSE3\s0 and \s-1SSE4.1\s0 +instruction set support. +(No scheduling is implemented for this chip.) +.IP "\fBgeode\fR" 4 +.IX Item "geode" +\&\s-1AMD\s0 Geode embedded processor with \s-1MMX\s0 and 3DNow! instruction set support. +.RE +.RS 4 +.RE +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, except +for the \s-1ABI\s0 and the set of available instructions. +While picking a specific \fIcpu-type\fR schedules things appropriately +for that particular chip, the compiler does not generate any code that +cannot run on the default machine type unless you use a +\&\fB\-march=\fR\fIcpu-type\fR option. +For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu +then \fB\-mtune=pentium4\fR generates code that is tuned for Pentium 4 +but still runs on i686 machines. +.Sp +The choices for \fIcpu-type\fR are the same as for \fB\-march\fR. +In addition, \fB\-mtune\fR supports 2 extra choices for \fIcpu-type\fR: +.RS 4 +.IP "\fBgeneric\fR" 4 +.IX Item "generic" +Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. +If you know the \s-1CPU\s0 on which your code will run, then you should use +the corresponding \fB\-mtune\fR or \fB\-march\fR option instead of +\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users +of your application will have, then you should use this option. +.Sp +As new processors are deployed in the marketplace, the behavior of this +option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +the processors +that are most common at the time that version of \s-1GCC\s0 is released. +.Sp +There is no \fB\-march=generic\fR option because \fB\-march\fR +indicates the instruction set the compiler can use, and there is no +generic instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.IP "\fBintel\fR" 4 +.IX Item "intel" +Produce code optimized for the most current Intel processors, which are +Haswell and Silvermont for this version of \s-1GCC.\s0 If you know the \s-1CPU\s0 +on which your code will run, then you should use the corresponding +\&\fB\-mtune\fR or \fB\-march\fR option instead of \fB\-mtune=intel\fR. +But, if you want your application performs better on both Haswell and +Silvermont, then you should use this option. +.Sp +As new Intel processors are deployed in the marketplace, the behavior of +this option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +the most current Intel processors at the time that version of \s-1GCC\s0 is +released. +.Sp +There is no \fB\-march=intel\fR option because \fB\-march\fR indicates +the instruction set the compiler can use, and there is no common +instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.RE +.RS 4 +.RE +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +A deprecated synonym for \fB\-mtune\fR. +.IP "\fB\-mfpmath=\fR\fIunit\fR" 4 +.IX Item "-mfpmath=unit" +Generate floating-point arithmetic for selected unit \fIunit\fR. The choices +for \fIunit\fR are: +.RS 4 +.IP "\fB387\fR" 4 +.IX Item "387" +Use the standard 387 floating-point coprocessor present on the majority of chips and +emulated otherwise. Code compiled with this option runs almost everywhere. +The temporary results are computed in 80\-bit precision instead of the precision +specified by the type, resulting in slightly different results compared to most +of other chips. See \fB\-ffloat\-store\fR for more detailed description. +.Sp +This is the default choice for non-Darwin x86\-32 targets. +.IP "\fBsse\fR" 4 +.IX Item "sse" +Use scalar floating-point instructions present in the \s-1SSE\s0 instruction set. +This instruction set is supported by Pentium \s-1III\s0 and newer chips, +and in the \s-1AMD\s0 line +by Athlon\-4, Athlon \s-1XP\s0 and Athlon \s-1MP\s0 chips. The earlier version of the \s-1SSE\s0 +instruction set supports only single-precision arithmetic, thus the double and +extended-precision arithmetic are still done using 387. A later version, present +only in Pentium 4 and \s-1AMD\s0 x86\-64 chips, supports double-precision +arithmetic too. +.Sp +For the x86\-32 compiler, you must use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR +or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option +effective. For the x86\-64 compiler, these extensions are enabled by default. +.Sp +The resulting code should be considerably faster in the majority of cases and avoid +the numerical instability problems of 387 code, but may break some existing +code that expects temporaries to be 80 bits. +.Sp +This is the default choice for the x86\-64 compiler, Darwin x86\-32 targets, +and the default choice for x86\-32 targets with the \s-1SSE2\s0 instruction set +when \fB\-ffast\-math\fR is enabled. +.IP "\fBsse,387\fR" 4 +.IX Item "sse,387" +.PD 0 +.IP "\fBsse+387\fR" 4 +.IX Item "sse+387" +.IP "\fBboth\fR" 4 +.IX Item "both" +.PD +Attempt to utilize both instruction sets at once. This effectively doubles the +amount of available registers, and on chips with separate execution units for +387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is +still experimental, because the \s-1GCC\s0 register allocator does not model separate +functional units well, resulting in unstable performance. +.RE +.RS 4 +.RE +.IP "\fB\-masm=\fR\fIdialect\fR" 4 +.IX Item "-masm=dialect" +Output assembly instructions using selected \fIdialect\fR. Also affects +which dialect is used for basic \f(CW\*(C`asm\*(C'\fR and +extended \f(CW\*(C`asm\*(C'\fR. Supported choices (in dialect +order) are \fBatt\fR or \fBintel\fR. The default is \fBatt\fR. Darwin does +not support \fBintel\fR. +.IP "\fB\-mieee\-fp\fR" 4 +.IX Item "-mieee-fp" +.PD 0 +.IP "\fB\-mno\-ieee\-fp\fR" 4 +.IX Item "-mno-ieee-fp" +.PD +Control whether or not the compiler uses \s-1IEEE\s0 floating-point +comparisons. These correctly handle the case where the result of a +comparison is unordered. +.IP "\fB\-m80387\fR" 4 +.IX Item "-m80387" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing 80387 instructions for floating point. +.IP "\fB\-mno\-80387\fR" 4 +.IX Item "-mno-80387" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +.Sp +\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC.\s0 +Normally the facilities of the machine's usual C compiler are used, but +this cannot be done directly in cross-compilation. You must make your +own arrangements to provide suitable library functions for +cross-compilation. +.Sp +On machines where a function returns floating-point results in the 80387 +register stack, some floating-point opcodes may be emitted even if +\&\fB\-msoft\-float\fR is used. +.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 +.IX Item "-mno-fp-ret-in-387" +Do not use the \s-1FPU\s0 registers for return values of functions. +.Sp +The usual calling convention has functions return values of types +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there +is no \s-1FPU.\s0 The idea is that the operating system should emulate +an \s-1FPU.\s0 +.Sp +The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned +in ordinary \s-1CPU\s0 registers instead. +.IP "\fB\-mno\-fancy\-math\-387\fR" 4 +.IX Item "-mno-fancy-math-387" +Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and +\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid +generating those instructions. +This option is overridden when \fB\-march\fR +indicates that the target \s-1CPU\s0 always has an \s-1FPU\s0 and so the +instruction does not need emulation. These +instructions are not generated unless you also use the +\&\fB\-funsafe\-math\-optimizations\fR switch. +.IP "\fB\-malign\-double\fR" 4 +.IX Item "-malign-double" +.PD 0 +.IP "\fB\-mno\-align\-double\fR" 4 +.IX Item "-mno-align-double" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and +\&\f(CW\*(C`long long\*(C'\fR variables on a two-word boundary or a one-word +boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two-word boundary +produces code that runs somewhat faster on a Pentium at the +expense of more memory. +.Sp +On x86\-64, \fB\-malign\-double\fR is enabled by default. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, +structures containing the above types are aligned differently than +the published application binary interface specifications for the x86\-32 +and are not binary compatible with structures in code compiled +without that switch. +.IP "\fB\-m96bit\-long\-double\fR" 4 +.IX Item "-m96bit-long-double" +.PD 0 +.IP "\fB\-m128bit\-long\-double\fR" 4 +.IX Item "-m128bit-long-double" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The x86\-32 +application binary interface specifies the size to be 96 bits, +so \fB\-m96bit\-long\-double\fR is the default in 32\-bit mode. +.Sp +Modern architectures (Pentium and newer) prefer \f(CW\*(C`long double\*(C'\fR +to be aligned to an 8\- or 16\-byte boundary. In arrays or structures +conforming to the \s-1ABI,\s0 this is not possible. So specifying +\&\fB\-m128bit\-long\-double\fR aligns \f(CW\*(C`long double\*(C'\fR +to a 16\-byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional +32\-bit zero. +.Sp +In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as +its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is aligned on 16\-byte boundary. +.Sp +Notice that neither of these options enable any extra precision over the x87 +standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +changes the size of +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, +as well as modifying the function calling convention for functions taking +\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible +with code compiled without that switch. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-80\fR" 4 +.IX Item "-mlong-double-80" +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default for 32\-bit Bionic C library. A size +of 128 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the +\&\f(CW\*(C`_\|_float128\*(C'\fR type. This is the default for 64\-bit Bionic C library. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +changes the size of +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, +as well as modifying the function calling convention for functions taking +\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible +with code compiled without that switch. +.IP "\fB\-malign\-data=\fR\fItype\fR" 4 +.IX Item "-malign-data=type" +Control how \s-1GCC\s0 aligns variables. Supported values for \fItype\fR are +\&\fBcompat\fR uses increased alignment value compatible uses \s-1GCC 4.8\s0 +and earlier, \fBabi\fR uses alignment value as specified by the +psABI, and \fBcacheline\fR uses increased alignment value to match +the cache line size. \fBcompat\fR is the default. +.IP "\fB\-mlarge\-data\-threshold=\fR\fIthreshold\fR" 4 +.IX Item "-mlarge-data-threshold=threshold" +When \fB\-mcmodel=medium\fR is specified, data objects larger than +\&\fIthreshold\fR are placed in the large data section. This value must be the +same across all objects linked into the binary, and defaults to 65535. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions that +take a fixed number of arguments return with the \f(CW\*(C`ret \f(CInum\f(CW\*(C'\fR +instruction, which pops their arguments while returning. This saves one +instruction in the caller since there is no need to pop the arguments +there. +.Sp +You can specify that an individual function is called with this calling +sequence with the function attribute \f(CW\*(C`stdcall\*(C'\fR. You can also +override the \fB\-mrtd\fR option by using the function attribute +\&\f(CW\*(C`cdecl\*(C'\fR. +.Sp +\&\fBWarning:\fR this calling convention is incompatible with the one +normally used on Unix, so you cannot use it if you need to call +libraries compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code is generated for calls to those +functions. +.Sp +In addition, seriously incorrect code results if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.IP "\fB\-mregparm=\fR\fInum\fR" 4 +.IX Item "-mregparm=num" +Control how many registers are used to pass integer arguments. By +default, no registers are used to pass arguments, and at most 3 +registers can be used. You can control this behavior for a specific +function by using the function attribute \f(CW\*(C`regparm\*(C'\fR. +.Sp +\&\fBWarning:\fR if you use this switch, and +\&\fInum\fR is nonzero, then you must build all modules with the same +value, including any libraries. This includes the system libraries and +startup modules. +.IP "\fB\-msseregparm\fR" 4 +.IX Item "-msseregparm" +Use \s-1SSE\s0 register passing conventions for float and double arguments +and return values. You can control this behavior for a specific +function by using the function attribute \f(CW\*(C`sseregparm\*(C'\fR. +.Sp +\&\fBWarning:\fR if you use this switch then you must build all +modules with the same value, including any libraries. This includes +the system libraries and startup modules. +.IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 +.IX Item "-mvect8-ret-in-mem" +Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the +default on Solaris 8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun +Studio compilers until version 12. Later compiler versions (starting +with Studio 12 Update 1) follow the \s-1ABI\s0 used by other x86 targets, which +is the default on Solaris 10 and later. \fIOnly\fR use this option if +you need to remain compatible with existing code produced by those +previous compiler versions or older versions of \s-1GCC.\s0 +.IP "\fB\-mpc32\fR" 4 +.IX Item "-mpc32" +.PD 0 +.IP "\fB\-mpc64\fR" 4 +.IX Item "-mpc64" +.IP "\fB\-mpc80\fR" 4 +.IX Item "-mpc80" +.PD +Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR +is specified, the significands of results of floating-point operations are +rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the +significands of results of floating-point operations to 53 bits (double +precision) and \fB\-mpc80\fR rounds the significands of results of +floating-point operations to 64 bits (extended double precision), which is +the default. When this option is used, floating-point operations in higher +precisions are not available to the programmer without setting the \s-1FPU\s0 +control word explicitly. +.Sp +Setting the rounding of floating-point operations to less than the default +80 bits can speed some programs by 2% or more. Note that some mathematical +libraries assume that extended-precision (80\-bit) floating-point operations +are enabled by default; routines in such libraries could suffer significant +loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", +when this option is used to set the precision to less than extended precision. +.IP "\fB\-mstackrealign\fR" 4 +.IX Item "-mstackrealign" +Realign the stack at entry. On the x86, the \fB\-mstackrealign\fR +option generates an alternate prologue and epilogue that realigns the +run-time stack if necessary. This supports mixing legacy codes that keep +4\-byte stack alignment with modern codes that keep 16\-byte stack alignment for +\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, +applicable to individual functions. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128 bits). +.Sp +\&\fBWarning:\fR When generating code for the x86\-64 architecture with +\&\s-1SSE\s0 extensions disabled, \fB\-mpreferred\-stack\-boundary=3\fR can be +used to keep the stack boundary aligned to 8 byte boundary. Since +x86\-64 \s-1ABI\s0 require 16 byte stack alignment, this is \s-1ABI\s0 incompatible and +intended to be used in controlled environment where stack space is +important limitation. This option leads to wrong code when functions +compiled with 16 byte stack alignment (such as functions from a standard +library) are called with misaligned stack. In this case, \s-1SSE\s0 +instructions may lead to misaligned memory access traps. In addition, +variable arguments are handled incorrectly for 16 byte aligned +objects (including x87 long double and _\|_int128), leading to wrong +results. You must build all modules with +\&\fB\-mpreferred\-stack\-boundary=3\fR, including any libraries. This +includes the system libraries and startup modules. +.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mincoming-stack-boundary=num" +Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte +boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, +the one specified by \fB\-mpreferred\-stack\-boundary\fR is used. +.Sp +On Pentium and Pentium Pro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values +should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or +suffer significant run time performance penalties. On Pentium \s-1III,\s0 the +Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work +properly if it is not 16\-byte aligned. +.Sp +To ensure proper alignment of this values on the stack, the stack boundary +must be as aligned as that required by any value stored on the stack. +Further, every function must be generated such that it keeps the stack +aligned. Thus calling a function compiled with a higher preferred +stack boundary from a function compiled with a lower preferred stack +boundary most likely misaligns the stack. It is recommended that +libraries that use callbacks always use the default setting. +.Sp +This extra alignment does consume extra stack space, and generally +increases code size. Code that is sensitive to stack space usage, such +as embedded systems and operating system kernels, may want to reduce the +preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. +.IP "\fB\-mmmx\fR" 4 +.IX Item "-mmmx" +.PD 0 +.IP "\fB\-msse\fR" 4 +.IX Item "-msse" +.IP "\fB\-msse2\fR" 4 +.IX Item "-msse2" +.IP "\fB\-msse3\fR" 4 +.IX Item "-msse3" +.IP "\fB\-mssse3\fR" 4 +.IX Item "-mssse3" +.IP "\fB\-msse4\fR" 4 +.IX Item "-msse4" +.IP "\fB\-msse4a\fR" 4 +.IX Item "-msse4a" +.IP "\fB\-msse4.1\fR" 4 +.IX Item "-msse4.1" +.IP "\fB\-msse4.2\fR" 4 +.IX Item "-msse4.2" +.IP "\fB\-mavx\fR" 4 +.IX Item "-mavx" +.IP "\fB\-mavx2\fR" 4 +.IX Item "-mavx2" +.IP "\fB\-mavx512f\fR" 4 +.IX Item "-mavx512f" +.IP "\fB\-mavx512pf\fR" 4 +.IX Item "-mavx512pf" +.IP "\fB\-mavx512er\fR" 4 +.IX Item "-mavx512er" +.IP "\fB\-mavx512cd\fR" 4 +.IX Item "-mavx512cd" +.IP "\fB\-mavx512vl\fR" 4 +.IX Item "-mavx512vl" +.IP "\fB\-mavx512bw\fR" 4 +.IX Item "-mavx512bw" +.IP "\fB\-mavx512dq\fR" 4 +.IX Item "-mavx512dq" +.IP "\fB\-mavx512ifma\fR" 4 +.IX Item "-mavx512ifma" +.IP "\fB\-mavx512vbmi\fR" 4 +.IX Item "-mavx512vbmi" +.IP "\fB\-msha\fR" 4 +.IX Item "-msha" +.IP "\fB\-maes\fR" 4 +.IX Item "-maes" +.IP "\fB\-mpclmul\fR" 4 +.IX Item "-mpclmul" +.IP "\fB\-mclflushopt\fR" 4 +.IX Item "-mclflushopt" +.IP "\fB\-mclwb\fR" 4 +.IX Item "-mclwb" +.IP "\fB\-mfsgsbase\fR" 4 +.IX Item "-mfsgsbase" +.IP "\fB\-mptwrite\fR" 4 +.IX Item "-mptwrite" +.IP "\fB\-mrdrnd\fR" 4 +.IX Item "-mrdrnd" +.IP "\fB\-mf16c\fR" 4 +.IX Item "-mf16c" +.IP "\fB\-mfma\fR" 4 +.IX Item "-mfma" +.IP "\fB\-mpconfig\fR" 4 +.IX Item "-mpconfig" +.IP "\fB\-mwbnoinvd\fR" 4 +.IX Item "-mwbnoinvd" +.IP "\fB\-mfma4\fR" 4 +.IX Item "-mfma4" +.IP "\fB\-mprfchw\fR" 4 +.IX Item "-mprfchw" +.IP "\fB\-mrdpid\fR" 4 +.IX Item "-mrdpid" +.IP "\fB\-mprefetchwt1\fR" 4 +.IX Item "-mprefetchwt1" +.IP "\fB\-mrdseed\fR" 4 +.IX Item "-mrdseed" +.IP "\fB\-msgx\fR" 4 +.IX Item "-msgx" +.IP "\fB\-mxop\fR" 4 +.IX Item "-mxop" +.IP "\fB\-mlwp\fR" 4 +.IX Item "-mlwp" +.IP "\fB\-m3dnow\fR" 4 +.IX Item "-m3dnow" +.IP "\fB\-m3dnowa\fR" 4 +.IX Item "-m3dnowa" +.IP "\fB\-mpopcnt\fR" 4 +.IX Item "-mpopcnt" +.IP "\fB\-mabm\fR" 4 +.IX Item "-mabm" +.IP "\fB\-madx\fR" 4 +.IX Item "-madx" +.IP "\fB\-mbmi\fR" 4 +.IX Item "-mbmi" +.IP "\fB\-mbmi2\fR" 4 +.IX Item "-mbmi2" +.IP "\fB\-mlzcnt\fR" 4 +.IX Item "-mlzcnt" +.IP "\fB\-mfxsr\fR" 4 +.IX Item "-mfxsr" +.IP "\fB\-mxsave\fR" 4 +.IX Item "-mxsave" +.IP "\fB\-mxsaveopt\fR" 4 +.IX Item "-mxsaveopt" +.IP "\fB\-mxsavec\fR" 4 +.IX Item "-mxsavec" +.IP "\fB\-mxsaves\fR" 4 +.IX Item "-mxsaves" +.IP "\fB\-mrtm\fR" 4 +.IX Item "-mrtm" +.IP "\fB\-mhle\fR" 4 +.IX Item "-mhle" +.IP "\fB\-mtbm\fR" 4 +.IX Item "-mtbm" +.IP "\fB\-mmwaitx\fR" 4 +.IX Item "-mmwaitx" +.IP "\fB\-mclzero\fR" 4 +.IX Item "-mclzero" +.IP "\fB\-mpku\fR" 4 +.IX Item "-mpku" +.IP "\fB\-mavx512vbmi2\fR" 4 +.IX Item "-mavx512vbmi2" +.IP "\fB\-mgfni\fR" 4 +.IX Item "-mgfni" +.IP "\fB\-mvaes\fR" 4 +.IX Item "-mvaes" +.IP "\fB\-mwaitpkg\fR" 4 +.IX Item "-mwaitpkg" +.IP "\fB\-mvpclmulqdq\fR" 4 +.IX Item "-mvpclmulqdq" +.IP "\fB\-mavx512bitalg\fR" 4 +.IX Item "-mavx512bitalg" +.IP "\fB\-mmovdiri\fR" 4 +.IX Item "-mmovdiri" +.IP "\fB\-mmovdir64b\fR" 4 +.IX Item "-mmovdir64b" +.IP "\fB\-mavx512vpopcntdq\fR" 4 +.IX Item "-mavx512vpopcntdq" +.IP "\fB\-mavx5124fmaps\fR" 4 +.IX Item "-mavx5124fmaps" +.IP "\fB\-mavx512vnni\fR" 4 +.IX Item "-mavx512vnni" +.IP "\fB\-mavx5124vnniw\fR" 4 +.IX Item "-mavx5124vnniw" +.IP "\fB\-mcldemote\fR" 4 +.IX Item "-mcldemote" +.PD +These switches enable the use of instructions in the \s-1MMX, SSE, +SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, +AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, +AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, +WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,\s0 +3DNow!, enhanced 3DNow!, \s-1POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE, +XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2, +GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, +AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW,\s0 or \s-1CLDEMOTE\s0 +extended instruction sets. Each has a corresponding \fB\-mno\-\fR option to +disable use of these instructions. +.Sp +These extensions are also available as built-in functions: see +\&\fBx86 Built-in Functions\fR, for details of the functions enabled and +disabled by these switches. +.Sp +To generate \s-1SSE/SSE2\s0 instructions automatically from floating-point +code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. +.Sp +\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it +generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions +when needed. +.Sp +These options enable \s-1GCC\s0 to use these extended instructions in +generated code, even without \fB\-mfpmath=sse\fR. Applications that +perform run-time \s-1CPU\s0 detection must compile separate files for each +supported architecture, using the appropriate flags. In particular, +the file containing the \s-1CPU\s0 detection code should be compiled without +these options. +.IP "\fB\-mdump\-tune\-features\fR" 4 +.IX Item "-mdump-tune-features" +This option instructs \s-1GCC\s0 to dump the names of the x86 performance +tuning features and default settings. The names can be used in +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR. +.IP "\fB\-mtune\-ctrl=\fR\fIfeature-list\fR" 4 +.IX Item "-mtune-ctrl=feature-list" +This option is used to do fine grain control of x86 code generation features. +\&\fIfeature-list\fR is a comma separated list of \fIfeature\fR names. See also +\&\fB\-mdump\-tune\-features\fR. When specified, the \fIfeature\fR is turned +on if it is not preceded with \fB^\fR, otherwise, it is turned off. +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR is intended to be used by \s-1GCC\s0 +developers. Using it may lead to code paths not covered by testing and can +potentially result in compiler ICEs or runtime errors. +.IP "\fB\-mno\-default\fR" 4 +.IX Item "-mno-default" +This option instructs \s-1GCC\s0 to turn off all tunable features. See also +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR and \fB\-mdump\-tune\-features\fR. +.IP "\fB\-mcld\fR" 4 +.IX Item "-mcld" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue +of functions that use string instructions. String instructions depend on +the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the +\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating +systems violate this specification by not clearing the \s-1DF\s0 flag in their +exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag +set, which leads to wrong direction mode when string instructions are used. +This option can be enabled by default on 32\-bit x86 targets by configuring +\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR +instructions can be suppressed with the \fB\-mno\-cld\fR compiler option +in this case. +.IP "\fB\-mvzeroupper\fR" 4 +.IX Item "-mvzeroupper" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction +before a transfer of control flow out of the function to minimize +the \s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary \f(CW\*(C`zeroupper\*(C'\fR +intrinsics. +.IP "\fB\-mprefer\-avx128\fR" 4 +.IX Item "-mprefer-avx128" +This option instructs \s-1GCC\s0 to use 128\-bit \s-1AVX\s0 instructions instead of +256\-bit \s-1AVX\s0 instructions in the auto-vectorizer. +.IP "\fB\-mprefer\-vector\-width=\fR\fIopt\fR" 4 +.IX Item "-mprefer-vector-width=opt" +This option instructs \s-1GCC\s0 to use \fIopt\fR\-bit vector width in instructions +instead of default on the selected platform. +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +No extra limitations applied to \s-1GCC\s0 other than defined by the selected platform. +.IP "\fB128\fR" 4 +.IX Item "128" +Prefer 128\-bit vector width for instructions. +.IP "\fB256\fR" 4 +.IX Item "256" +Prefer 256\-bit vector width for instructions. +.IP "\fB512\fR" 4 +.IX Item "512" +Prefer 512\-bit vector width for instructions. +.RE +.RS 4 +.RE +.IP "\fB\-mcx16\fR" 4 +.IX Item "-mcx16" +This option enables \s-1GCC\s0 to generate \f(CW\*(C`CMPXCHG16B\*(C'\fR instructions in 64\-bit +code to implement compare-and-exchange operations on 16\-byte aligned 128\-bit +objects. This is useful for atomic updates of data structures exceeding one +machine word in size. The compiler uses this instruction to implement +\&\fB_\|_sync Builtins\fR. However, for \fB_\|_atomic Builtins\fR operating on +128\-bit integers, a library call is always used. +.IP "\fB\-msahf\fR" 4 +.IX Item "-msahf" +This option enables generation of \f(CW\*(C`SAHF\*(C'\fR instructions in 64\-bit code. +Early Intel Pentium 4 CPUs with Intel 64 support, +prior to the introduction of Pentium 4 G1 step in December 2005, +lacked the \f(CW\*(C`LAHF\*(C'\fR and \f(CW\*(C`SAHF\*(C'\fR instructions +which are supported by \s-1AMD64.\s0 +These are load and store instructions, respectively, for certain status flags. +In 64\-bit mode, the \f(CW\*(C`SAHF\*(C'\fR instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, +\&\f(CW\*(C`drem\*(C'\fR, and \f(CW\*(C`remainder\*(C'\fR built-in functions; +see \fBOther Builtins\fR for details. +.IP "\fB\-mmovbe\fR" 4 +.IX Item "-mmovbe" +This option enables use of the \f(CW\*(C`movbe\*(C'\fR instruction to implement +\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. +.IP "\fB\-mshstk\fR" 4 +.IX Item "-mshstk" +The \fB\-mshstk\fR option enables shadow stack built-in functions +from x86 Control-flow Enforcement Technology (\s-1CET\s0). +.IP "\fB\-mcrc32\fR" 4 +.IX Item "-mcrc32" +This option enables built-in functions \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, +\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR, \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and +\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the \f(CW\*(C`crc32\*(C'\fR machine instruction. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +This option enables use of \f(CW\*(C`RCPSS\*(C'\fR and \f(CW\*(C`RSQRTSS\*(C'\fR instructions +(and their vectorized variants \f(CW\*(C`RCPPS\*(C'\fR and \f(CW\*(C`RSQRTPS\*(C'\fR) +with an additional Newton-Raphson step +to increase precision instead of \f(CW\*(C`DIVSS\*(C'\fR and \f(CW\*(C`SQRTSS\*(C'\fR +(and their vectorized +variants) for single-precision floating-point arguments. These instructions +are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled +together with \fB\-ffinite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. +Note that while the throughput of the sequence is higher than the throughput +of the non-reciprocal instruction, the precision of the sequence can be +decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). +.Sp +Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \f(CW\*(C`RSQRTSS\*(C'\fR +(or \f(CW\*(C`RSQRTPS\*(C'\fR) already with \fB\-ffast\-math\fR (or the above option +combination), and doesn't need \fB\-mrecip\fR. +.Sp +Also note that \s-1GCC\s0 emits the above sequence with additional Newton-Raphson step +for vectorized single-float division and vectorized \f(CW\*(C`sqrtf(\f(CIx\f(CW)\*(C'\fR +already with \fB\-ffast\-math\fR (or the above option combination), and +doesn't need \fB\-mrecip\fR. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option controls which reciprocal estimate instructions +may be used. \fIopt\fR is a comma-separated list of options, which may +be preceded by a \fB!\fR to invert the option: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all estimate instructions. +.IP "\fBdefault\fR" 4 +.IX Item "default" +Enable the default instructions, equivalent to \fB\-mrecip\fR. +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR. +.IP "\fBdiv\fR" 4 +.IX Item "div" +Enable the approximation for scalar division. +.IP "\fBvec-div\fR" 4 +.IX Item "vec-div" +Enable the approximation for vectorized division. +.IP "\fBsqrt\fR" 4 +.IX Item "sqrt" +Enable the approximation for scalar square root. +.IP "\fBvec-sqrt\fR" 4 +.IX Item "vec-sqrt" +Enable the approximation for vectorized square root. +.RE +.RS 4 +.Sp +So, for example, \fB\-mrecip=all,!sqrt\fR enables +all of the reciprocal approximations, except for square root. +.RE +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. Supported values for \fItype\fR are \fBsvml\fR +for the Intel short +vector math library and \fBacml\fR for the \s-1AMD\s0 math core library. +To use this option, both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML\s0 +ABI-compatible library must be specified at link time. +.Sp +\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR, +\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, +\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, +\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, +\&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, +\&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, +\&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, +\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, +\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, +\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding +function type when \fB\-mveclibabi=svml\fR is used, and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for the corresponding function type +when \fB\-mveclibabi=acml\fR is used. +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified calling convention. Permissible values +are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and +\&\fBms\fR for the Microsoft \s-1ABI.\s0 The default is to use the Microsoft +\&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems. +You can control this behavior for specific functions by +using the function attributes \f(CW\*(C`ms_abi\*(C'\fR and \f(CW\*(C`sysv_abi\*(C'\fR. +.IP "\fB\-mforce\-indirect\-call\fR" 4 +.IX Item "-mforce-indirect-call" +Force all calls to functions to be indirect. This is useful +when using Intel Processor Trace where it generates more precise timing +information for function calls. +.IP "\fB\-mmanual\-endbr\fR" 4 +.IX Item "-mmanual-endbr" +Insert \s-1ENDBR\s0 instruction at function entry only via the \f(CW\*(C`cf_check\*(C'\fR +function attribute. This is useful when used with the option +\&\fB\-fcf\-protection=branch\fR to control \s-1ENDBR\s0 insertion at the +function entry. +.IP "\fB\-mcall\-ms2sysv\-xlogues\fR" 4 +.IX Item "-mcall-ms2sysv-xlogues" +Due to differences in 64\-bit ABIs, any Microsoft \s-1ABI\s0 function that calls a +System V \s-1ABI\s0 function must consider \s-1RSI, RDI\s0 and \s-1XMM6\-15\s0 as clobbered. By +default, the code for saving and restoring these registers is emitted inline, +resulting in fairly lengthy prologues and epilogues. Using +\&\fB\-mcall\-ms2sysv\-xlogues\fR emits prologues and epilogues that +use stubs in the static portion of libgcc to perform these saves and restores, +thus reducing function size at the cost of a few extra instructions. +.IP "\fB\-mtls\-dialect=\fR\fItype\fR" 4 +.IX Item "-mtls-dialect=type" +Generate code to access thread-local storage using the \fBgnu\fR or +\&\fBgnu2\fR conventions. \fBgnu\fR is the conservative default; +\&\fBgnu2\fR is more efficient, but it may add compile\- and run-time +requirements that cannot be satisfied on all systems. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" +.PD 0 +.IP "\fB\-mno\-push\-args\fR" 4 +.IX Item "-mno-push-args" +.PD +Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter +and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled +by default. In some cases disabling it may improve performance because of +improved scheduling and reduced dependencies. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +If enabled, the maximum amount of space required for outgoing arguments is +computed in the function prologue. This is faster on most modern CPUs +because of reduced dependencies, improved scheduling and reduced stack usage +when the preferred stack boundary is not equal to 2. The drawback is a notable +increase in code size. This switch implies \fB\-mno\-push\-args\fR. +.IP "\fB\-mthreads\fR" 4 +.IX Item "-mthreads" +Support thread-safe exception handling on MinGW. Programs that rely +on thread-safe exception handling must compile and link all code with the +\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines +\&\fB\-D_MT\fR; when linking, it links in a special thread helper library +\&\fB\-lmingwthrd\fR which cleans up per-thread exception-handling data. +.IP "\fB\-mms\-bitfields\fR" 4 +.IX Item "-mms-bitfields" +.PD 0 +.IP "\fB\-mno\-ms\-bitfields\fR" 4 +.IX Item "-mno-ms-bitfields" +.PD +Enable/disable bit-field layout compatible with the native Microsoft +Windows compiler. +.Sp +If \f(CW\*(C`packed\*(C'\fR is used on a structure, or if bit-fields are used, +it may be that the Microsoft \s-1ABI\s0 lays out the structure differently +than the way \s-1GCC\s0 normally does. Particularly when moving packed +data between functions compiled with \s-1GCC\s0 and the native Microsoft compiler +(either via function call or as data in a file), it may be necessary to access +either format. +.Sp +This option is enabled by default for Microsoft Windows +targets. This behavior can also be controlled locally by use of variable +or type attributes. For more information, see \fBx86 Variable Attributes\fR +and \fBx86 Type Attributes\fR. +.Sp +The Microsoft structure layout algorithm is fairly simple with the exception +of the bit-field packing. +The padding and alignment of members of structures and whether a bit-field +can straddle a storage-unit boundary are determine by these rules: +.RS 4 +.IP "1. Structure members are stored sequentially in the order in which they are" 4 +.IX Item "1. Structure members are stored sequentially in the order in which they are" +declared: the first member has the lowest memory address and the last member +the highest. +.IP "2. Every data object has an alignment requirement. The alignment requirement" 4 +.IX Item "2. Every data object has an alignment requirement. The alignment requirement" +for all data except structures, unions, and arrays is either the size of the +object or the current packing size (specified with either the +\&\f(CW\*(C`aligned\*(C'\fR attribute or the \f(CW\*(C`pack\*(C'\fR pragma), +whichever is less. For structures, unions, and arrays, +the alignment requirement is the largest alignment requirement of its members. +Every object is allocated an offset so that: +.Sp +.Vb 1 +\& offset % alignment_requirement == 0 +.Ve +.IP "3. Adjacent bit-fields are packed into the same 1\-, 2\-, or 4\-byte allocation" 4 +.IX Item "3. Adjacent bit-fields are packed into the same 1-, 2-, or 4-byte allocation" +unit if the integral types are the same size and if the next bit-field fits +into the current allocation unit without crossing the boundary imposed by the +common alignment requirements of the bit-fields. +.RE +.RS 4 +.Sp +\&\s-1MSVC\s0 interprets zero-length bit-fields in the following ways: +.IP "1. If a zero-length bit-field is inserted between two bit-fields that" 4 +.IX Item "1. If a zero-length bit-field is inserted between two bit-fields that" +are normally coalesced, the bit-fields are not coalesced. +.Sp +For example: +.Sp +.Vb 6 +\& struct +\& { +\& unsigned long bf_1 : 12; +\& unsigned long : 0; +\& unsigned long bf_2 : 12; +\& } t1; +.Ve +.Sp +The size of \f(CW\*(C`t1\*(C'\fR is 8 bytes with the zero-length bit-field. If the +zero-length bit-field were removed, \f(CW\*(C`t1\*(C'\fR's size would be 4 bytes. +.ie n .IP "2. If a zero-length bit-field is inserted after a bit-field, ""foo"", and the" 4 +.el .IP "2. If a zero-length bit-field is inserted after a bit-field, \f(CWfoo\fR, and the" 4 +.IX Item "2. If a zero-length bit-field is inserted after a bit-field, foo, and the" +alignment of the zero-length bit-field is greater than the member that follows it, +\&\f(CW\*(C`bar\*(C'\fR, \f(CW\*(C`bar\*(C'\fR is aligned as the type of the zero-length bit-field. +.Sp +For example: +.Sp +.Vb 6 +\& struct +\& { +\& char foo : 4; +\& short : 0; +\& char bar; +\& } t2; +\& +\& struct +\& { +\& char foo : 4; +\& short : 0; +\& double bar; +\& } t3; +.Ve +.Sp +For \f(CW\*(C`t2\*(C'\fR, \f(CW\*(C`bar\*(C'\fR is placed at offset 2, rather than offset 1. +Accordingly, the size of \f(CW\*(C`t2\*(C'\fR is 4. For \f(CW\*(C`t3\*(C'\fR, the zero-length +bit-field does not affect the alignment of \f(CW\*(C`bar\*(C'\fR or, as a result, the size +of the structure. +.Sp +Taking this into account, it is important to note the following: +.RS 4 +.IP "1. If a zero-length bit-field follows a normal bit-field, the type of the" 4 +.IX Item "1. If a zero-length bit-field follows a normal bit-field, the type of the" +zero-length bit-field may affect the alignment of the structure as whole. For +example, \f(CW\*(C`t2\*(C'\fR has a size of 4 bytes, since the zero-length bit-field follows a +normal bit-field, and is of type short. +.IP "2. Even if a zero-length bit-field is not followed by a normal bit-field, it may" 4 +.IX Item "2. Even if a zero-length bit-field is not followed by a normal bit-field, it may" +still affect the alignment of the structure: +.Sp +.Vb 5 +\& struct +\& { +\& char foo : 6; +\& long : 0; +\& } t4; +.Ve +.Sp +Here, \f(CW\*(C`t4\*(C'\fR takes up 4 bytes. +.RE +.RS 4 +.RE +.IP "3. Zero-length bit-fields following non-bit-field members are ignored:" 4 +.IX Item "3. Zero-length bit-fields following non-bit-field members are ignored:" +.Vb 6 +\& struct +\& { +\& char foo; +\& long : 0; +\& char bar; +\& } t5; +.Ve +.Sp +Here, \f(CW\*(C`t5\*(C'\fR takes up 2 bytes. +.RE +.RS 4 +.RE +.IP "\fB\-mno\-align\-stringops\fR" 4 +.IX Item "-mno-align-stringops" +Do not align the destination of inlined string operations. This switch reduces +code size and improves performance in case the destination is already aligned, +but \s-1GCC\s0 doesn't know about it. +.IP "\fB\-minline\-all\-stringops\fR" 4 +.IX Item "-minline-all-stringops" +By default \s-1GCC\s0 inlines string operations only when the destination is +known to be aligned to least a 4\-byte boundary. +This enables more inlining and increases code +size, but may improve performance of code that depends on fast +\&\f(CW\*(C`memcpy\*(C'\fR, \f(CW\*(C`strlen\*(C'\fR, +and \f(CW\*(C`memset\*(C'\fR for short lengths. +.IP "\fB\-minline\-stringops\-dynamically\fR" 4 +.IX Item "-minline-stringops-dynamically" +For string operations of unknown size, use run-time checks with +inline code for small blocks and a library call for large blocks. +.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 +.IX Item "-mstringop-strategy=alg" +Override the internal decision heuristic for the particular algorithm to use +for inlining string operations. The allowed values for \fIalg\fR are: +.RS 4 +.IP "\fBrep_byte\fR" 4 +.IX Item "rep_byte" +.PD 0 +.IP "\fBrep_4byte\fR" 4 +.IX Item "rep_4byte" +.IP "\fBrep_8byte\fR" 4 +.IX Item "rep_8byte" +.PD +Expand using i386 \f(CW\*(C`rep\*(C'\fR prefix of the specified size. +.IP "\fBbyte_loop\fR" 4 +.IX Item "byte_loop" +.PD 0 +.IP "\fBloop\fR" 4 +.IX Item "loop" +.IP "\fBunrolled_loop\fR" 4 +.IX Item "unrolled_loop" +.PD +Expand into an inline loop. +.IP "\fBlibcall\fR" 4 +.IX Item "libcall" +Always use a library call. +.RE +.RS 4 +.RE +.IP "\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR" 4 +.IX Item "-mmemcpy-strategy=strategy" +Override the internal decision heuristic to decide if \f(CW\*(C`_\|_builtin_memcpy\*(C'\fR +should be inlined and what inline algorithm to use when the expected size +of the copy operation is known. \fIstrategy\fR +is a comma-separated list of \fIalg\fR:\fImax_size\fR:\fIdest_align\fR triplets. +\&\fIalg\fR is specified in \fB\-mstringop\-strategy\fR, \fImax_size\fR specifies +the max byte size with which inline algorithm \fIalg\fR is allowed. For the last +triplet, the \fImax_size\fR must be \f(CW\*(C`\-1\*(C'\fR. The \fImax_size\fR of the triplets +in the list must be specified in increasing order. The minimal byte size for +\&\fIalg\fR is \f(CW0\fR for the first triplet and \f(CW\*(C`\f(CImax_size\f(CW + 1\*(C'\fR of the +preceding range. +.IP "\fB\-mmemset\-strategy=\fR\fIstrategy\fR" 4 +.IX Item "-mmemset-strategy=strategy" +The option is similar to \fB\-mmemcpy\-strategy=\fR except that it is to control +\&\f(CW\*(C`_\|_builtin_memset\*(C'\fR expansion. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up, and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-leaf\-frame\-pointer\fR removes the frame pointer for leaf functions, +which might make debugging harder. +.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 +.IX Item "-mtls-direct-seg-refs" +.PD 0 +.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 +.IX Item "-mno-tls-direct-seg-refs" +.PD +Controls whether \s-1TLS\s0 variables may be accessed with offsets from the +\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), +or whether the thread base pointer must be added. Whether or not this +is valid depends on the operating system, and whether it maps the +segment to cover the entire \s-1TLS\s0 area. +.Sp +For systems that use the \s-1GNU C\s0 Library, the default is on. +.IP "\fB\-msse2avx\fR" 4 +.IX Item "-msse2avx" +.PD 0 +.IP "\fB\-mno\-sse2avx\fR" 4 +.IX Item "-mno-sse2avx" +.PD +Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 +prefix. The option \fB\-mavx\fR turns this on by default. +.IP "\fB\-mfentry\fR" 4 +.IX Item "-mfentry" +.PD 0 +.IP "\fB\-mno\-fentry\fR" 4 +.IX Item "-mno-fentry" +.PD +If profiling is active (\fB\-pg\fR), put the profiling +counter call before the prologue. +Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR +isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. +.IP "\fB\-mrecord\-mcount\fR" 4 +.IX Item "-mrecord-mcount" +.PD 0 +.IP "\fB\-mno\-record\-mcount\fR" 4 +.IX Item "-mno-record-mcount" +.PD +If profiling is active (\fB\-pg\fR), generate a _\|_mcount_loc section +that contains pointers to each profiling call. This is useful for +automatically patching and out calls. +.IP "\fB\-mnop\-mcount\fR" 4 +.IX Item "-mnop-mcount" +.PD 0 +.IP "\fB\-mno\-nop\-mcount\fR" 4 +.IX Item "-mno-nop-mcount" +.PD +If profiling is active (\fB\-pg\fR), generate the calls to +the profiling functions as NOPs. This is useful when they +should be patched in later dynamically. This is likely only +useful together with \fB\-mrecord\-mcount\fR. +.IP "\fB\-minstrument\-return=\fR\fItype\fR" 4 +.IX Item "-minstrument-return=type" +Instrument function exit in \-pg \-mfentry instrumented functions with +call to specified function. This only instruments true returns ending +with ret, but not sibling calls ending with jump. Valid types +are \fInone\fR to not instrument, \fIcall\fR to generate a call to _\|_return_\|_, +or \fInop5\fR to generate a 5 byte nop. +.IP "\fB\-mrecord\-return\fR" 4 +.IX Item "-mrecord-return" +.PD 0 +.IP "\fB\-mno\-record\-return\fR" 4 +.IX Item "-mno-record-return" +.PD +Generate a _\|_return_loc section pointing to all return instrumentation code. +.IP "\fB\-mfentry\-name=\fR\fIname\fR" 4 +.IX Item "-mfentry-name=name" +Set name of _\|_fentry_\|_ symbol called at function entry for \-pg \-mfentry functions. +.IP "\fB\-mfentry\-section=\fR\fIname\fR" 4 +.IX Item "-mfentry-section=name" +Set name of section to record \-mrecord\-mcount calls (default _\|_mcount_loc). +.IP "\fB\-mskip\-rax\-setup\fR" 4 +.IX Item "-mskip-rax-setup" +.PD 0 +.IP "\fB\-mno\-skip\-rax\-setup\fR" 4 +.IX Item "-mno-skip-rax-setup" +.PD +When generating code for the x86\-64 architecture with \s-1SSE\s0 extensions +disabled, \fB\-mskip\-rax\-setup\fR can be used to skip setting up \s-1RAX\s0 +register when there are no variable arguments passed in vector registers. +.Sp +\&\fBWarning:\fR Since \s-1RAX\s0 register is used to avoid unnecessarily +saving vector registers on stack when passing variable arguments, the +impacts of this option are callees may waste some stack space, +misbehave or jump to a random location. \s-1GCC 4.4\s0 or newer don't have +those issues, regardless the \s-1RAX\s0 register value. +.IP "\fB\-m8bit\-idiv\fR" 4 +.IX Item "-m8bit-idiv" +.PD 0 +.IP "\fB\-mno\-8bit\-idiv\fR" 4 +.IX Item "-mno-8bit-idiv" +.PD +On some processors, like Intel Atom, 8\-bit unsigned integer divide is +much faster than 32\-bit/64\-bit integer divide. This option generates a +run-time check. If both dividend and divisor are within range of 0 +to 255, 8\-bit unsigned integer divide is used instead of +32\-bit/64\-bit integer divide. +.IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 +.IX Item "-mavx256-split-unaligned-load" +.PD 0 +.IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 +.IX Item "-mavx256-split-unaligned-store" +.PD +Split 32\-byte \s-1AVX\s0 unaligned load and store. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +.PD 0 +.IP "\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR" 4 +.IX Item "-mstack-protector-guard-reg=reg" +.IP "\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR" 4 +.IX Item "-mstack-protector-guard-offset=offset" +.PD +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for global canary or \fBtls\fR for per-thread +canary in the \s-1TLS\s0 block (the default). This option has effect only when +\&\fB\-fstack\-protector\fR or \fB\-fstack\-protector\-all\fR is specified. +.Sp +With the latter choice the options +\&\fB\-mstack\-protector\-guard\-reg=\fR\fIreg\fR and +\&\fB\-mstack\-protector\-guard\-offset=\fR\fIoffset\fR furthermore specify +which segment register (\f(CW%fs\fR or \f(CW%gs\fR) to use as base register +for reading the canary, and from what offset from that base register. +The default for those is as specified in the relevant \s-1ABI.\s0 +.IP "\fB\-mgeneral\-regs\-only\fR" 4 +.IX Item "-mgeneral-regs-only" +Generate code that uses only the general-purpose registers. This +prevents the compiler from using floating-point, vector, mask and bound +registers. +.IP "\fB\-mindirect\-branch=\fR\fIchoice\fR" 4 +.IX Item "-mindirect-branch=choice" +Convert indirect call and jump with \fIchoice\fR. The default is +\&\fBkeep\fR, which keeps indirect call and jump unmodified. +\&\fBthunk\fR converts indirect call and jump to call and return thunk. +\&\fBthunk-inline\fR converts indirect call and jump to inlined call +and return thunk. \fBthunk-extern\fR converts indirect call and jump +to external call and return thunk provided in a separate object file. +You can control this behavior for a specific function by using the +function attribute \f(CW\*(C`indirect_branch\*(C'\fR. +.Sp +Note that \fB\-mcmodel=large\fR is incompatible with +\&\fB\-mindirect\-branch=thunk\fR and +\&\fB\-mindirect\-branch=thunk\-extern\fR since the thunk function may +not be reachable in the large code model. +.Sp +Note that \fB\-mindirect\-branch=thunk\-extern\fR is compatible with +\&\fB\-fcf\-protection=branch\fR since the external thunk can be made +to enable control-flow check. +.IP "\fB\-mfunction\-return=\fR\fIchoice\fR" 4 +.IX Item "-mfunction-return=choice" +Convert function return with \fIchoice\fR. The default is \fBkeep\fR, +which keeps function return unmodified. \fBthunk\fR converts function +return to call and return thunk. \fBthunk-inline\fR converts function +return to inlined call and return thunk. \fBthunk-extern\fR converts +function return to external call and return thunk provided in a separate +object file. You can control this behavior for a specific function by +using the function attribute \f(CW\*(C`function_return\*(C'\fR. +.Sp +Note that \fB\-mindirect\-return=thunk\-extern\fR is compatible with +\&\fB\-fcf\-protection=branch\fR since the external thunk can be made +to enable control-flow check. +.Sp +Note that \fB\-mcmodel=large\fR is incompatible with +\&\fB\-mfunction\-return=thunk\fR and +\&\fB\-mfunction\-return=thunk\-extern\fR since the thunk function may +not be reachable in the large code model. +.IP "\fB\-mindirect\-branch\-register\fR" 4 +.IX Item "-mindirect-branch-register" +Force indirect call and jump via register. +.PP +These \fB\-m\fR switches are supported in addition to the above +on x86\-64 processors in 64\-bit environments. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.IP "\fB\-mx32\fR" 4 +.IX Item "-mx32" +.IP "\fB\-m16\fR" 4 +.IX Item "-m16" +.IP "\fB\-miamcu\fR" 4 +.IX Item "-miamcu" +.PD +Generate code for a 16\-bit, 32\-bit or 64\-bit environment. +The \fB\-m32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types +to 32 bits, and +generates code that runs on any i386 system. +.Sp +The \fB\-m64\fR option sets \f(CW\*(C`int\*(C'\fR to 32 bits and \f(CW\*(C`long\*(C'\fR and pointer +types to 64 bits, and generates code for the x86\-64 architecture. +For Darwin only the \fB\-m64\fR option also turns off the \fB\-fno\-pic\fR +and \fB\-mdynamic\-no\-pic\fR options. +.Sp +The \fB\-mx32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types +to 32 bits, and +generates code for the x86\-64 architecture. +.Sp +The \fB\-m16\fR option is the same as \fB\-m32\fR, except for that +it outputs the \f(CW\*(C`.code16gcc\*(C'\fR assembly directive at the beginning of +the assembly output so that the binary can run in 16\-bit mode. +.Sp +The \fB\-miamcu\fR option generates code which conforms to Intel \s-1MCU\s0 +psABI. It requires the \fB\-m32\fR option to be turned on. +.IP "\fB\-mno\-red\-zone\fR" 4 +.IX Item "-mno-red-zone" +Do not use a so-called \*(L"red zone\*(R" for x86\-64 code. The red zone is mandated +by the x86\-64 \s-1ABI\s0; it is a 128\-byte area beyond the location of the +stack pointer that is not modified by signal or interrupt handlers +and therefore can be used for temporary data without adjusting the stack +pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model: the program and its symbols must +be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. +Programs can be statically or dynamically linked. This is the default +code model. +.IP "\fB\-mcmodel=kernel\fR" 4 +.IX Item "-mcmodel=kernel" +Generate code for the kernel code model. The kernel runs in the +negative 2 \s-1GB\s0 of the address space. +This model has to be used for Linux kernel code. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate code for the medium model: the program is linked in the lower 2 +\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols +with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into +large data or \s-1BSS\s0 sections and can be located above 2GB. Programs can +be statically or dynamically linked. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model. This model makes no assumptions +about addresses and sizes of sections. +.IP "\fB\-maddress\-mode=long\fR" 4 +.IX Item "-maddress-mode=long" +Generate code for long address mode. This is only supported for 64\-bit +and x32 environments. It is the default address mode for 64\-bit +environments. +.IP "\fB\-maddress\-mode=short\fR" 4 +.IX Item "-maddress-mode=short" +Generate code for short address mode. This is only supported for 32\-bit +and x32 environments. It is the default address mode for 32\-bit and +x32 environments. +.PP +\fIx86 Windows Options\fR +.IX Subsection "x86 Windows Options" +.PP +These additional options are available for Microsoft Windows targets: +.IP "\fB\-mconsole\fR" 4 +.IX Item "-mconsole" +This option +specifies that a console application is to be generated, by +instructing the linker to set the \s-1PE\s0 header subsystem type +required for console applications. +This option is available for Cygwin and MinGW targets and is +enabled by default on those targets. +.IP "\fB\-mdll\fR" 4 +.IX Item "-mdll" +This option is available for Cygwin and MinGW targets. It +specifies that a DLL\-\-\-a dynamic link library\-\-\-is to be +generated, enabling the selection of the required runtime +startup object and entry point. +.IP "\fB\-mnop\-fun\-dllimport\fR" 4 +.IX Item "-mnop-fun-dllimport" +This option is available for Cygwin and MinGW targets. It +specifies that the \f(CW\*(C`dllimport\*(C'\fR attribute should be ignored. +.IP "\fB\-mthread\fR" 4 +.IX Item "-mthread" +This option is available for MinGW targets. It specifies +that MinGW-specific thread support is to be used. +.IP "\fB\-municode\fR" 4 +.IX Item "-municode" +This option is available for MinGW\-w64 targets. It causes +the \f(CW\*(C`UNICODE\*(C'\fR preprocessor macro to be predefined, and +chooses Unicode-capable runtime startup code. +.IP "\fB\-mwin32\fR" 4 +.IX Item "-mwin32" +This option is available for Cygwin and MinGW targets. It +specifies that the typical Microsoft Windows predefined macros are to +be set in the pre-processor, but does not influence the choice +of runtime library/startup code. +.IP "\fB\-mwindows\fR" 4 +.IX Item "-mwindows" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1GUI\s0 application is to be generated by +instructing the linker to set the \s-1PE\s0 header subsystem type +appropriately. +.IP "\fB\-fno\-set\-stack\-executable\fR" 4 +.IX Item "-fno-set-stack-executable" +This option is available for MinGW targets. It specifies that +the executable flag for the stack used by nested functions isn't +set. This is necessary for binaries running in kernel mode of +Microsoft Windows, as there the User32 \s-1API,\s0 which is used to set executable +privileges, isn't available. +.IP "\fB\-fwritable\-relocated\-rdata\fR" 4 +.IX Item "-fwritable-relocated-rdata" +This option is available for MinGW and Cygwin targets. It specifies +that relocated-data in read-only section is put into the \f(CW\*(C`.data\*(C'\fR +section. This is a necessary for older runtimes not supporting +modification of \f(CW\*(C`.rdata\*(C'\fR sections for pseudo-relocation. +.IP "\fB\-mpe\-aligned\-commons\fR" 4 +.IX Item "-mpe-aligned-commons" +This option is available for Cygwin and MinGW targets. It +specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that +permits the correct alignment of \s-1COMMON\s0 variables should be +used when generating code. It is enabled by default if +\&\s-1GCC\s0 detects that the target assembler found during configuration +supports the feature. +.PP +See also under \fBx86 Options\fR for standard options. +.PP +\fIXstormy16 Options\fR +.IX Subsection "Xstormy16 Options" +.PP +These options are defined for Xstormy16: +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Choose startup files and linker script suitable for the simulator. +.PP +\fIXtensa Options\fR +.IX Subsection "Xtensa Options" +.PP +These options are supported for Xtensa targets: +.IP "\fB\-mconst16\fR" 4 +.IX Item "-mconst16" +.PD 0 +.IP "\fB\-mno\-const16\fR" 4 +.IX Item "-mno-const16" +.PD +Enable or disable use of \f(CW\*(C`CONST16\*(C'\fR instructions for loading +constant values. The \f(CW\*(C`CONST16\*(C'\fR instruction is currently not a +standard option from Tensilica. When enabled, \f(CW\*(C`CONST16\*(C'\fR +instructions are always used in place of the standard \f(CW\*(C`L32R\*(C'\fR +instructions. The use of \f(CW\*(C`CONST16\*(C'\fR is enabled by default only if +the \f(CW\*(C`L32R\*(C'\fR instruction is not available. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable or disable use of fused multiply/add and multiply/subtract +instructions in the floating-point option. This has no effect if the +floating-point option is not also enabled. Disabling fused multiply/add +and multiply/subtract instructions forces the compiler to use separate +instructions for the multiply and add/subtract operations. This may be +desirable in some cases where strict \s-1IEEE\s0 754\-compliant results are +required: the fused multiply add/subtract instructions do not round the +intermediate result, thereby producing results with \fImore\fR bits of +precision than specified by the \s-1IEEE\s0 standard. Disabling fused multiply +add/subtract instructions also ensures that the program output is not +sensitive to the compiler's ability to combine multiply and add/subtract +operations. +.IP "\fB\-mserialize\-volatile\fR" 4 +.IX Item "-mserialize-volatile" +.PD 0 +.IP "\fB\-mno\-serialize\-volatile\fR" 4 +.IX Item "-mno-serialize-volatile" +.PD +When this option is enabled, \s-1GCC\s0 inserts \f(CW\*(C`MEMW\*(C'\fR instructions before +\&\f(CW\*(C`volatile\*(C'\fR memory references to guarantee sequential consistency. +The default is \fB\-mserialize\-volatile\fR. Use +\&\fB\-mno\-serialize\-volatile\fR to omit the \f(CW\*(C`MEMW\*(C'\fR instructions. +.IP "\fB\-mforce\-no\-pic\fR" 4 +.IX Item "-mforce-no-pic" +For targets, like GNU/Linux, where all user-mode Xtensa code must be +position-independent code (\s-1PIC\s0), this option disables \s-1PIC\s0 for compiling +kernel code. +.IP "\fB\-mtext\-section\-literals\fR" 4 +.IX Item "-mtext-section-literals" +.PD 0 +.IP "\fB\-mno\-text\-section\-literals\fR" 4 +.IX Item "-mno-text-section-literals" +.PD +These options control the treatment of literal pools. The default is +\&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate +section in the output file. This allows the literal pool to be placed +in a data \s-1RAM/ROM,\s0 and it also allows the linker to combine literal +pools from separate object files to remove redundant literals and +improve code size. With \fB\-mtext\-section\-literals\fR, the literals +are interspersed in the text section in order to keep them as close as +possible to their references. This may be necessary for large assembly +files. Literals for each function are placed right before that function. +.IP "\fB\-mauto\-litpools\fR" 4 +.IX Item "-mauto-litpools" +.PD 0 +.IP "\fB\-mno\-auto\-litpools\fR" 4 +.IX Item "-mno-auto-litpools" +.PD +These options control the treatment of literal pools. The default is +\&\fB\-mno\-auto\-litpools\fR, which places literals in a separate +section in the output file unless \fB\-mtext\-section\-literals\fR is +used. With \fB\-mauto\-litpools\fR the literals are interspersed in +the text section by the assembler. Compiler does not produce explicit +\&\f(CW\*(C`.literal\*(C'\fR directives and loads literals into registers with +\&\f(CW\*(C`MOVI\*(C'\fR instructions instead of \f(CW\*(C`L32R\*(C'\fR to let the assembler +do relaxation and place literals as necessary. This option allows +assembler to create several literal pools per function and assemble +very big functions, which may not be possible with +\&\fB\-mtext\-section\-literals\fR. +.IP "\fB\-mtarget\-align\fR" 4 +.IX Item "-mtarget-align" +.PD 0 +.IP "\fB\-mno\-target\-align\fR" 4 +.IX Item "-mno-target-align" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to +automatically align instructions to reduce branch penalties at the +expense of some code density. The assembler attempts to widen density +instructions to align branch targets and the instructions following call +instructions. If there are not enough preceding safe density +instructions to align a target, no widening is performed. The +default is \fB\-mtarget\-align\fR. These options do not affect the +treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the +assembler always aligns, either by widening density instructions or +by inserting \s-1NOP\s0 instructions. +.IP "\fB\-mlongcalls\fR" 4 +.IX Item "-mlongcalls" +.PD 0 +.IP "\fB\-mno\-longcalls\fR" 4 +.IX Item "-mno-longcalls" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to translate +direct calls to indirect calls unless it can determine that the target +of a direct call is in the range allowed by the call instruction. This +translation typically occurs for calls to functions in other source +files. Specifically, the assembler translates a direct \f(CW\*(C`CALL\*(C'\fR +instruction into an \f(CW\*(C`L32R\*(C'\fR followed by a \f(CW\*(C`CALLX\*(C'\fR instruction. +The default is \fB\-mno\-longcalls\fR. This option should be used in +programs where the call target can potentially be out of range. This +option is implemented in the assembler, not the compiler, so the +assembly code generated by \s-1GCC\s0 still shows direct call +instructions\-\-\-look at the disassembled object code to see the actual +instructions. Note that the assembler uses an indirect call for +every cross-file call, not just those that really are out of range. +.PP +\fIzSeries Options\fR +.IX Subsection "zSeries Options" +.PP +These are listed under +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +This section describes several environment variables that affect how \s-1GCC\s0 +operates. Some of them work by specifying directories or prefixes to use +when searching for various kinds of files. Some are used to specify other +aspects of the compilation environment. +.PP +Note that you can also specify places to search using options such as +\&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These +take precedence over places specified using environment variables, which +in turn take precedence over those specified by the configuration of \s-1GCC.\s0 +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +.PD 0 +.IP "\fB\s-1LC_CTYPE\s0\fR" 4 +.IX Item "LC_CTYPE" +.IP "\fB\s-1LC_MESSAGES\s0\fR" 4 +.IX Item "LC_MESSAGES" +.IP "\fB\s-1LC_ALL\s0\fR" 4 +.IX Item "LC_ALL" +.PD +These environment variables control the way that \s-1GCC\s0 uses +localization information which allows \s-1GCC\s0 to work with different +national conventions. \s-1GCC\s0 inspects the locale categories +\&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do +so. These locale categories can be set to any value supported by your +installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United +Kingdom encoded in \s-1UTF\-8.\s0 +.Sp +The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character +classification. \s-1GCC\s0 uses it to determine the character boundaries in +a string; this is needed for some multibyte encodings that contain quote +and escape characters that are otherwise interpreted as a string +end or escape. +.Sp +The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to +use in diagnostic messages. +.Sp +If the \fB\s-1LC_ALL\s0\fR environment variable is set, it overrides the value +of \fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR; otherwise, \fB\s-1LC_CTYPE\s0\fR +and \fB\s-1LC_MESSAGES\s0\fR default to the value of the \fB\s-1LANG\s0\fR +environment variable. If none of these variables are set, \s-1GCC\s0 +defaults to traditional C English behavior. +.IP "\fB\s-1TMPDIR\s0\fR" 4 +.IX Item "TMPDIR" +If \fB\s-1TMPDIR\s0\fR is set, it specifies the directory to use for temporary +files. \s-1GCC\s0 uses temporary files to hold the output of one stage of +compilation which is to be used as input to the next stage: for example, +the output of the preprocessor, which is the input to the compiler +proper. +.IP "\fB\s-1GCC_COMPARE_DEBUG\s0\fR" 4 +.IX Item "GCC_COMPARE_DEBUG" +Setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR is nearly equivalent to passing +\&\fB\-fcompare\-debug\fR to the compiler driver. See the documentation +of this option for more details. +.IP "\fB\s-1GCC_EXEC_PREFIX\s0\fR" 4 +.IX Item "GCC_EXEC_PREFIX" +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is set, it specifies a prefix to use in the +names of the subprograms executed by the compiler. No slash is added +when this prefix is combined with the name of a subprogram, but you can +specify a prefix that ends with a slash if you wish. +.Sp +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 attempts to figure out +an appropriate prefix to use based on the pathname it is invoked with. +.Sp +If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it +tries looking in the usual places for the subprogram. +.Sp +The default value of \fB\s-1GCC_EXEC_PREFIX\s0\fR is +\&\fI\fIprefix\fI/lib/gcc/\fR where \fIprefix\fR is the prefix to +the installed compiler. In many cases \fIprefix\fR is the value +of \f(CW\*(C`prefix\*(C'\fR when you ran the \fIconfigure\fR script. +.Sp +Other prefixes specified with \fB\-B\fR take precedence over this prefix. +.Sp +This prefix is also used for finding files such as \fIcrt0.o\fR that are +used for linking. +.Sp +In addition, the prefix is used in an unusual way in finding the +directories to search for header files. For each of the standard +directories whose name normally begins with \fB/usr/local/lib/gcc\fR +(more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries +replacing that beginning with the specified prefix to produce an +alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 searches +\&\fIfoo/bar\fR just before it searches the standard directory +\&\fI/usr/local/lib/bar\fR. +If a standard directory begins with the configured +\&\fIprefix\fR then the value of \fIprefix\fR is replaced by +\&\fB\s-1GCC_EXEC_PREFIX\s0\fR when looking for header files. +.IP "\fB\s-1COMPILER_PATH\s0\fR" 4 +.IX Item "COMPILER_PATH" +The value of \fB\s-1COMPILER_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. \s-1GCC\s0 tries the directories thus +specified when searching for subprograms, if it cannot find the +subprograms using \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\s-1LIBRARY_PATH\s0\fR" 4 +.IX Item "LIBRARY_PATH" +The value of \fB\s-1LIBRARY_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. When configured as a native compiler, +\&\s-1GCC\s0 tries the directories thus specified when searching for special +linker files, if it cannot find them using \fB\s-1GCC_EXEC_PREFIX\s0\fR. Linking +using \s-1GCC\s0 also uses these directories when searching for ordinary +libraries for the \fB\-l\fR option (but directories specified with +\&\fB\-L\fR come first). +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +This variable is used to pass locale information to the compiler. One way in +which this information is used is to determine the character set to be used +when character literals, string literals and comments are parsed in C and \*(C+. +When the compiler is configured to allow multibyte characters, +the following values for \fB\s-1LANG\s0\fR are recognized: +.RS 4 +.IP "\fBC\-JIS\fR" 4 +.IX Item "C-JIS" +Recognize \s-1JIS\s0 characters. +.IP "\fBC\-SJIS\fR" 4 +.IX Item "C-SJIS" +Recognize \s-1SJIS\s0 characters. +.IP "\fBC\-EUCJP\fR" 4 +.IX Item "C-EUCJP" +Recognize \s-1EUCJP\s0 characters. +.RE +.RS 4 +.Sp +If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the +compiler uses \f(CW\*(C`mblen\*(C'\fR and \f(CW\*(C`mbtowc\*(C'\fR as defined by the default locale to +recognize and translate multibyte characters. +.RE +.PP +Some additional environment variables affect the behavior of the +preprocessor. +.IP "\fB\s-1CPATH\s0\fR" 4 +.IX Item "CPATH" +.PD 0 +.IP "\fBC_INCLUDE_PATH\fR" 4 +.IX Item "C_INCLUDE_PATH" +.IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 +.IX Item "CPLUS_INCLUDE_PATH" +.IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 +.IX Item "OBJC_INCLUDE_PATH" +.PD +Each variable's value is a list of directories separated by a special +character, much like \fB\s-1PATH\s0\fR, in which to look for header files. +The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and +determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a +semicolon, and for almost all other targets it is a colon. +.Sp +\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if +specified with \fB\-I\fR, but after any paths given with \fB\-I\fR +options on the command line. This environment variable is used +regardless of which language is being preprocessed. +.Sp +The remaining environment variables apply only when preprocessing the +particular language indicated. Each specifies a list of directories +to be searched as if specified with \fB\-isystem\fR, but after any +paths given with \fB\-isystem\fR options on the command line. +.Sp +In all these variables, an empty element instructs the compiler to +search its current working directory. Empty elements can appear at the +beginning or end of a path. For instance, if the value of +\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same +effect as \fB\-I.\ \-I/special/include\fR. +.IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 +.IX Item "DEPENDENCIES_OUTPUT" +If this variable is set, its value specifies how to output +dependencies for Make based on the non-system header files processed +by the compiler. System header files are ignored in the dependency +output. +.Sp +The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in +which case the Make rules are written to that file, guessing the target +name from the source file name. Or the value can have the form +\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to +file \fIfile\fR using \fItarget\fR as the target name. +.Sp +In other words, this environment variable is equivalent to combining +the options \fB\-MM\fR and \fB\-MF\fR, +with an optional \fB\-MT\fR switch too. +.IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 +.IX Item "SUNPRO_DEPENDENCIES" +This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), +except that system header files are not ignored, so it implies +\&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the +main input file is omitted. +.IP "\fB\s-1SOURCE_DATE_EPOCH\s0\fR" 4 +.IX Item "SOURCE_DATE_EPOCH" +If this variable is set, its value specifies a \s-1UNIX\s0 timestamp to be +used in replacement of the current date and time in the \f(CW\*(C`_\|_DATE_\|_\*(C'\fR +and \f(CW\*(C`_\|_TIME_\|_\*(C'\fR macros, so that the embedded timestamps become +reproducible. +.Sp +The value of \fB\s-1SOURCE_DATE_EPOCH\s0\fR must be a \s-1UNIX\s0 timestamp, +defined as the number of seconds (excluding leap seconds) since +01 Jan 1970 00:00:00 represented in \s-1ASCII\s0; identical to the output of +\&\fB\f(CB@command\fB{date +%s\fR} on GNU/Linux and other systems that support the +\&\f(CW%s\fR extension in the \f(CW\*(C`date\*(C'\fR command. +.Sp +The value should be a known timestamp such as the last modification +time of the source or package and it should be set by the build +process. +.SH "BUGS" +.IX Header "BUGS" +For instructions on reporting bugs, see +<\fBhttps://github.com/conda\-forge/ctng\-compilers\-feedstock/issues/new/choose\fR>. +.SH "FOOTNOTES" +.IX Header "FOOTNOTES" +.IP "1." 4 +On some systems, \fBgcc \-shared\fR +needs to build supplementary stub code for constructors to work. On +multi-libbed systems, \fBgcc \-shared\fR must select the correct support +libraries to link against. Failing to supply the correct flags may lead +to subtle defects. Supplying them in cases where they are not necessary +is innocuous. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fBgpl\fR\|(7), \fBgfdl\fR\|(7), \fBfsf\-funding\fR\|(7), +\&\fBcpp\fR\|(1), \fBgcov\fR\|(1), \fBas\fR\|(1), \fBld\fR\|(1), \fBgdb\fR\|(1), \fBdbx\fR\|(1) +and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, +\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. +.SH "AUTHOR" +.IX Header "AUTHOR" +See the Info entry for \fBgcc\fR, or +<\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, +for contributors to \s-1GCC.\s0 +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1988\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fBgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man1/gcov-dump.1 b/man/man1/gcov-dump.1 new file mode 100644 index 0000000000000000000000000000000000000000..0a9252c367454f2dfdfb9be60602e0de97dfdb68 --- /dev/null +++ b/man/man1/gcov-dump.1 @@ -0,0 +1,206 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.if !\nF .nr F 0 +.if \nF>0 \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCOV-DUMP 1" +.TH GCOV-DUMP 1 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcov\-dump \- offline gcda and gcno profile dump tool +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcov-dump [\fB\-v\fR|\fB\-\-version\fR] + [\fB\-h\fR|\fB\-\-help\fR] + [\fB\-l\fR|\fB\-\-long\fR] + [\fB\-p\fR|\fB\-\-positions\fR] + \fIgcovfiles\fR +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBgcov-dump\fR is a tool you can use in conjunction with \s-1GCC\s0 to +dump content of gcda and gcno profile files offline. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Display help about using \fBgcov-dump\fR (on the standard output), and +exit without doing any further processing. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +.PD 0 +.IP "\fB\-\-long\fR" 4 +.IX Item "--long" +.PD +Dump content of records. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-positions\fR" 4 +.IX Item "--positions" +.PD +Dump positions of records. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the \fBgcov-dump\fR version number (on the standard output), +and exit without doing any further processing. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2017\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fIgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man1/gcov-tool.1 b/man/man1/gcov-tool.1 new file mode 100644 index 0000000000000000000000000000000000000000..890e93430dc78c05dd484aed3a7eff2ab6d4b2d6 --- /dev/null +++ b/man/man1/gcov-tool.1 @@ -0,0 +1,369 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.if !\nF .nr F 0 +.if \nF>0 \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCOV-TOOL 1" +.TH GCOV-TOOL 1 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcov\-tool \- offline gcda profile processing tool +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcov-tool [\fB\-v\fR|\fB\-\-version\fR] [\fB\-h\fR|\fB\-\-help\fR] +.PP +gcov-tool merge [merge\-options] \fIdirectory1\fR \fIdirectory2\fR + [\fB\-o\fR|\fB\-\-output\fR \fIdirectory\fR] + [\fB\-v\fR|\fB\-\-verbose\fR] + [\fB\-w\fR|\fB\-\-weight\fR \fIw1,w2\fR] +.PP +gcov-tool rewrite [rewrite\-options] \fIdirectory\fR + [\fB\-n\fR|\fB\-\-normalize\fR \fIlong_long_value\fR] + [\fB\-o\fR|\fB\-\-output\fR \fIdirectory\fR] + [\fB\-s\fR|\fB\-\-scale\fR \fIfloat_or_simple\-frac_value\fR] + [\fB\-v\fR|\fB\-\-verbose\fR] +.PP +gcov-tool overlap [overlap\-options] \fIdirectory1\fR \fIdirectory2\fR + [\fB\-f\fR|\fB\-\-function\fR] + [\fB\-F\fR|\fB\-\-fullname\fR] + [\fB\-h\fR|\fB\-\-hotonly\fR] + [\fB\-o\fR|\fB\-\-object\fR] + [\fB\-t\fR|\fB\-\-hot_threshold\fR] \fIfloat\fR + [\fB\-v\fR|\fB\-\-verbose\fR] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBgcov-tool\fR is an offline tool to process gcc's gcda profile files. +.PP +Current gcov-tool supports the following functionalities: +.IP "*" 4 +merge two sets of profiles with weights. +.IP "*" 4 +read one set of profile and rewrite profile contents. One can scale or +normalize the count values. +.PP +Examples of the use cases for this tool are: +.IP "*" 4 +Collect the profiles for different set of inputs, and use this tool to merge +them. One can specify the weight to factor in the relative importance of +each input. +.IP "*" 4 +Rewrite the profile after removing a subset of the gcda files, while maintaining +the consistency of the summary and the histogram. +.IP "*" 4 +It can also be used to debug or libgcov code as the tools shares the majority +code as the runtime library. +.PP +Note that for the merging operation, this profile generated offline may +contain slight different values from the online merged profile. Here are +a list of typical differences: +.IP "*" 4 +histogram difference: This offline tool recomputes the histogram after merging +the counters. The resulting histogram, therefore, is precise. The online +merging does not have this capability \*(-- the histogram is merged from two +histograms and the result is an approximation. +.IP "*" 4 +summary checksum difference: Summary checksum uses a \s-1CRC32\s0 operation. The value +depends on the link list order of gcov-info objects. This order is different in +gcov-tool from that in the online merge. It's expected to have different +summary checksums. It does not really matter as the compiler does not use this +checksum anywhere. +.IP "*" 4 +value profile counter values difference: Some counter values for value profile +are runtime dependent, like heap addresses. It's normal to see some difference +in these kind of counters. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Display help about using \fBgcov-tool\fR (on the standard output), and +exit without doing any further processing. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the \fBgcov-tool\fR version number (on the standard output), +and exit without doing any further processing. +.IP "\fBmerge\fR" 4 +.IX Item "merge" +Merge two profile directories. +.RS 4 +.IP "\fB\-o\fR \fIdirectory\fR" 4 +.IX Item "-o directory" +.PD 0 +.IP "\fB\-\-output\fR \fIdirectory\fR" 4 +.IX Item "--output directory" +.PD +Set the output profile directory. Default output directory name is +\&\fImerged_profile\fR. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Set the verbose mode. +.IP "\fB\-w\fR \fIw1\fR\fB,\fR\fIw2\fR" 4 +.IX Item "-w w1,w2" +.PD 0 +.IP "\fB\-\-weight\fR \fIw1\fR\fB,\fR\fIw2\fR" 4 +.IX Item "--weight w1,w2" +.PD +Set the merge weights of the \fIdirectory1\fR and \fIdirectory2\fR, +respectively. The default weights are 1 for both. +.RE +.RS 4 +.RE +.IP "\fBrewrite\fR" 4 +.IX Item "rewrite" +Read the specified profile directory and rewrite to a new directory. +.RS 4 +.IP "\fB\-n\fR \fIlong_long_value\fR" 4 +.IX Item "-n long_long_value" +.PD 0 +.IP "\fB\-\-normalize \fR" 4 +.IX Item "--normalize " +.PD +Normalize the profile. The specified value is the max counter value +in the new profile. +.IP "\fB\-o\fR \fIdirectory\fR" 4 +.IX Item "-o directory" +.PD 0 +.IP "\fB\-\-output\fR \fIdirectory\fR" 4 +.IX Item "--output directory" +.PD +Set the output profile directory. Default output name is \fIrewrite_profile\fR. +.IP "\fB\-s\fR \fIfloat_or_simple\-frac_value\fR" 4 +.IX Item "-s float_or_simple-frac_value" +.PD 0 +.IP "\fB\-\-scale\fR \fIfloat_or_simple\-frac_value\fR" 4 +.IX Item "--scale float_or_simple-frac_value" +.PD +Scale the profile counters. The specified value can be in floating point value, +or simple fraction value form, such 1, 2, 2/3, and 5/3. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Set the verbose mode. +.RE +.RS 4 +.RE +.IP "\fBoverlap\fR" 4 +.IX Item "overlap" +Compute the overlap score between the two specified profile directories. +The overlap score is computed based on the arc profiles. It is defined as +the sum of min (p1_counter[i] / p1_sum_all, p2_counter[i] / p2_sum_all), +for all arc counter i, where p1_counter[i] and p2_counter[i] are two +matched counters and p1_sum_all and p2_sum_all are the sum of counter +values in profile 1 and profile 2, respectively. +.RS 4 +.IP "\fB\-f\fR" 4 +.IX Item "-f" +.PD 0 +.IP "\fB\-\-function\fR" 4 +.IX Item "--function" +.PD +Print function level overlap score. +.IP "\fB\-F\fR" 4 +.IX Item "-F" +.PD 0 +.IP "\fB\-\-fullname\fR" 4 +.IX Item "--fullname" +.PD +Print full gcda filename. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-hotonly\fR" 4 +.IX Item "--hotonly" +.PD +Only print info for hot objects/functions. +.IP "\fB\-o\fR" 4 +.IX Item "-o" +.PD 0 +.IP "\fB\-\-object\fR" 4 +.IX Item "--object" +.PD +Print object level overlap score. +.IP "\fB\-t\fR \fIfloat\fR" 4 +.IX Item "-t float" +.PD 0 +.IP "\fB\-\-hot_threshold \fR" 4 +.IX Item "--hot_threshold " +.PD +Set the threshold for hot counter value. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Set the verbose mode. +.RE +.RS 4 +.RE +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), \fIgcc\fR\|(1), \fIgcov\fR\|(1) and the Info entry for +\&\fIgcc\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2014\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fIgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man1/gcov.1 b/man/man1/gcov.1 new file mode 100644 index 0000000000000000000000000000000000000000..f02713520072e78fa818d3ce536f6102e21279ae --- /dev/null +++ b/man/man1/gcov.1 @@ -0,0 +1,1039 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.if !\nF .nr F 0 +.if \nF>0 \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCOV 1" +.TH GCOV 1 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcov \- coverage testing tool +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcov [\fB\-v\fR|\fB\-\-version\fR] [\fB\-h\fR|\fB\-\-help\fR] + [\fB\-a\fR|\fB\-\-all\-blocks\fR] + [\fB\-b\fR|\fB\-\-branch\-probabilities\fR] + [\fB\-c\fR|\fB\-\-branch\-counts\fR] + [\fB\-d\fR|\fB\-\-display\-progress\fR] + [\fB\-f\fR|\fB\-\-function\-summaries\fR] + [\fB\-i\fR|\fB\-\-json\-format\fR] + [\fB\-j\fR|\fB\-\-human\-readable\fR] + [\fB\-k\fR|\fB\-\-use\-colors\fR] + [\fB\-l\fR|\fB\-\-long\-file\-names\fR] + [\fB\-m\fR|\fB\-\-demangled\-names\fR] + [\fB\-n\fR|\fB\-\-no\-output\fR] + [\fB\-o\fR|\fB\-\-object\-directory\fR \fIdirectory|file\fR] + [\fB\-p\fR|\fB\-\-preserve\-paths\fR] + [\fB\-q\fR|\fB\-\-use\-hotness\-colors\fR] + [\fB\-r\fR|\fB\-\-relative\-only\fR] + [\fB\-s\fR|\fB\-\-source\-prefix\fR \fIdirectory\fR] + [\fB\-t\fR|\fB\-\-stdout\fR] + [\fB\-u\fR|\fB\-\-unconditional\-branches\fR] + [\fB\-x\fR|\fB\-\-hash\-filenames\fR] + \fIfiles\fR +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBgcov\fR is a test coverage program. Use it in concert with \s-1GCC\s0 +to analyze your programs to help create more efficient, faster running +code and to discover untested parts of your program. You can use +\&\fBgcov\fR as a profiling tool to help discover where your +optimization efforts will best affect your code. You can also use +\&\fBgcov\fR along with the other profiling tool, \fBgprof\fR, to +assess which parts of your code use the greatest amount of computing +time. +.PP +Profiling tools help you analyze your code's performance. Using a +profiler such as \fBgcov\fR or \fBgprof\fR, you can find out some +basic performance statistics, such as: +.IP "*" 4 +how often each line of code executes +.IP "*" 4 +what lines of code are actually executed +.IP "*" 4 +how much computing time each section of code uses +.PP +Once you know these things about how your code works when compiled, you +can look at each module to see which modules should be optimized. +\&\fBgcov\fR helps you determine where to work on optimization. +.PP +Software developers also use coverage testing in concert with +testsuites, to make sure software is actually good enough for a release. +Testsuites can verify that a program works as expected; a coverage +program tests to see how much of the program is exercised by the +testsuite. Developers can then determine what kinds of test cases need +to be added to the testsuites to create both better testing and a better +final product. +.PP +You should compile your code without optimization if you plan to use +\&\fBgcov\fR because the optimization, by combining some lines of code +into one function, may not give you as much information as you need to +look for `hot spots' where the code is using a great deal of computer +time. Likewise, because \fBgcov\fR accumulates statistics by line (at +the lowest resolution), it works best with a programming style that +places only one statement on each line. If you use complicated macros +that expand to loops or to other control structures, the statistics are +less helpful\-\-\-they only report on the line where the macro call +appears. If your complex macros behave like functions, you can replace +them with inline functions to solve this problem. +.PP +\&\fBgcov\fR creates a logfile called \fI\fIsourcefile\fI.gcov\fR which +indicates how many times each line of a source file \fI\fIsourcefile\fI.c\fR +has executed. You can use these logfiles along with \fBgprof\fR to aid +in fine-tuning the performance of your programs. \fBgprof\fR gives +timing information you can use along with the information you get from +\&\fBgcov\fR. +.PP +\&\fBgcov\fR works only on code compiled with \s-1GCC.\s0 It is not +compatible with any other profiling or test coverage mechanism. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-all\-blocks\fR" 4 +.IX Item "--all-blocks" +.PD +Write individual execution counts for every basic block. Normally gcov +outputs execution counts only for the main blocks of a line. With this +option you can determine if blocks within a single line are not being +executed. +.IP "\fB\-b\fR" 4 +.IX Item "-b" +.PD 0 +.IP "\fB\-\-branch\-probabilities\fR" 4 +.IX Item "--branch-probabilities" +.PD +Write branch frequencies to the output file, and write branch summary +info to the standard output. This option allows you to see how often +each branch in your program was taken. Unconditional branches will not +be shown, unless the \fB\-u\fR option is given. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-\-branch\-counts\fR" 4 +.IX Item "--branch-counts" +.PD +Write branch frequencies as the number of branches taken, rather than +the percentage of branches taken. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-\-display\-progress\fR" 4 +.IX Item "--display-progress" +.PD +Display the progress on the standard output. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +.PD 0 +.IP "\fB\-\-function\-summaries\fR" 4 +.IX Item "--function-summaries" +.PD +Output summaries for each function in addition to the file level summary. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Display help about using \fBgcov\fR (on the standard output), and +exit without doing any further processing. +.IP "\fB\-i\fR" 4 +.IX Item "-i" +.PD 0 +.IP "\fB\-\-json\-format\fR" 4 +.IX Item "--json-format" +.PD +Output gcov file in an easy-to-parse \s-1JSON\s0 intermediate format +which does not require source code for generation. The \s-1JSON\s0 +file is compressed with gzip compression algorithm +and the files have \fI.gcov.json.gz\fR extension. +.Sp +Structure of the \s-1JSON\s0 is following: +.Sp +.Vb 7 +\& { +\& "current_working_directory": , +\& "data_file": , +\& "format_version": , +\& "gcc_version": +\& "files": [] +\& } +.Ve +.Sp +Fields of the root element have following semantics: +.RS 4 +.IP "*" 4 +\&\fIcurrent_working_directory\fR: working directory where +a compilation unit was compiled +.IP "*" 4 +\&\fIdata_file\fR: name of the data file (\s-1GCDA\s0) +.IP "*" 4 +\&\fIformat_version\fR: semantic version of the format +.IP "*" 4 +\&\fIgcc_version\fR: version of the \s-1GCC\s0 compiler +.RE +.RS 4 +.Sp +Each \fIfile\fR has the following form: +.Sp +.Vb 5 +\& { +\& "file": , +\& "functions": [], +\& "lines": [] +\& } +.Ve +.Sp +Fields of the \fIfile\fR element have following semantics: +.IP "*" 4 +\&\fIfile_name\fR: name of the source file +.RE +.RS 4 +.Sp +Each \fIfunction\fR has the following form: +.Sp +.Vb 11 +\& { +\& "blocks": , +\& "blocks_executed": , +\& "demangled_name": ", +\& "end_column": , +\& "end_line": , +\& "execution_count": , +\& "name": , +\& "start_column": +\& "start_line": +\& } +.Ve +.Sp +Fields of the \fIfunction\fR element have following semantics: +.IP "*" 4 +\&\fIblocks\fR: number of blocks that are in the function +.IP "*" 4 +\&\fIblocks_executed\fR: number of executed blocks of the function +.IP "*" 4 +\&\fIdemangled_name\fR: demangled name of the function +.IP "*" 4 +\&\fIend_column\fR: column in the source file where the function ends +.IP "*" 4 +\&\fIend_line\fR: line in the source file where the function ends +.IP "*" 4 +\&\fIexecution_count\fR: number of executions of the function +.IP "*" 4 +\&\fIname\fR: name of the function +.IP "*" 4 +\&\fIstart_column\fR: column in the source file where the function begins +.IP "*" 4 +\&\fIstart_line\fR: line in the source file where the function begins +.RE +.RS 4 +.Sp +Note that line numbers and column numbers number from 1. In the current +implementation, \fIstart_line\fR and \fIstart_column\fR do not include +any template parameters and the leading return type but that +this is likely to be fixed in the future. +.Sp +Each \fIline\fR has the following form: +.Sp +.Vb 7 +\& { +\& "branches": [], +\& "count": , +\& "line_number": , +\& "unexecuted_block": +\& "function_name": , +\& } +.Ve +.Sp +Branches are present only with \fI\-b\fR option. +Fields of the \fIline\fR element have following semantics: +.IP "*" 4 +\&\fIcount\fR: number of executions of the line +.IP "*" 4 +\&\fIline_number\fR: line number +.IP "*" 4 +\&\fIunexecuted_block\fR: flag whether the line contains an unexecuted block +(not all statements on the line are executed) +.IP "*" 4 +\&\fIfunction_name\fR: a name of a function this \fIline\fR belongs to +(for a line with an inlined statements can be not set) +.RE +.RS 4 +.Sp +Each \fIbranch\fR has the following form: +.Sp +.Vb 5 +\& { +\& "count": , +\& "fallthrough": , +\& "throw": +\& } +.Ve +.Sp +Fields of the \fIbranch\fR element have following semantics: +.IP "*" 4 +\&\fIcount\fR: number of executions of the branch +.IP "*" 4 +\&\fIfallthrough\fR: true when the branch is a fall through branch +.IP "*" 4 +\&\fIthrow\fR: true when the branch is an exceptional branch +.RE +.RS 4 +.RE +.IP "\fB\-j\fR" 4 +.IX Item "-j" +.PD 0 +.IP "\fB\-\-human\-readable\fR" 4 +.IX Item "--human-readable" +.PD +Write counts in human readable format (like 24.6k). +.IP "\fB\-k\fR" 4 +.IX Item "-k" +.PD 0 +.IP "\fB\-\-use\-colors\fR" 4 +.IX Item "--use-colors" +.PD +Use colors for lines of code that have zero coverage. We use red color for +non-exceptional lines and cyan for exceptional. Same colors are used for +basic blocks with \fB\-a\fR option. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +.PD 0 +.IP "\fB\-\-long\-file\-names\fR" 4 +.IX Item "--long-file-names" +.PD +Create long file names for included source files. For example, if the +header file \fIx.h\fR contains code, and was included in the file +\&\fIa.c\fR, then running \fBgcov\fR on the file \fIa.c\fR will +produce an output file called \fIa.c##x.h.gcov\fR instead of +\&\fIx.h.gcov\fR. This can be useful if \fIx.h\fR is included in +multiple source files and you want to see the individual +contributions. If you use the \fB\-p\fR option, both the including +and included file names will be complete path names. +.IP "\fB\-m\fR" 4 +.IX Item "-m" +.PD 0 +.IP "\fB\-\-demangled\-names\fR" 4 +.IX Item "--demangled-names" +.PD +Display demangled function names in output. The default is to show +mangled function names. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-no\-output\fR" 4 +.IX Item "--no-output" +.PD +Do not create the \fBgcov\fR output file. +.IP "\fB\-o\fR \fIdirectory|file\fR" 4 +.IX Item "-o directory|file" +.PD 0 +.IP "\fB\-\-object\-directory\fR \fIdirectory\fR" 4 +.IX Item "--object-directory directory" +.IP "\fB\-\-object\-file\fR \fIfile\fR" 4 +.IX Item "--object-file file" +.PD +Specify either the directory containing the gcov data files, or the +object path name. The \fI.gcno\fR, and +\&\fI.gcda\fR data files are searched for using this option. If a directory +is specified, the data files are in that directory and named after the +input file name, without its extension. If a file is specified here, +the data files are named after that file, without its extension. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-preserve\-paths\fR" 4 +.IX Item "--preserve-paths" +.PD +Preserve complete path information in the names of generated +\&\fI.gcov\fR files. Without this option, just the filename component is +used. With this option, all directories are used, with \fB/\fR characters +translated to \fB#\fR characters, \fI.\fR directory components +removed and unremoveable \fI..\fR +components renamed to \fB^\fR. This is useful if sourcefiles are in several +different directories. +.IP "\fB\-q\fR" 4 +.IX Item "-q" +.PD 0 +.IP "\fB\-\-use\-hotness\-colors\fR" 4 +.IX Item "--use-hotness-colors" +.PD +Emit perf-like colored output for hot lines. Legend of the color scale +is printed at the very beginning of the output file. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +.PD 0 +.IP "\fB\-\-relative\-only\fR" 4 +.IX Item "--relative-only" +.PD +Only output information about source files with a relative pathname +(after source prefix elision). Absolute paths are usually system +header files and coverage of any inline functions therein is normally +uninteresting. +.IP "\fB\-s\fR \fIdirectory\fR" 4 +.IX Item "-s directory" +.PD 0 +.IP "\fB\-\-source\-prefix\fR \fIdirectory\fR" 4 +.IX Item "--source-prefix directory" +.PD +A prefix for source file names to remove when generating the output +coverage files. This option is useful when building in a separate +directory, and the pathname to the source directory is not wanted when +determining the output file names. Note that this prefix detection is +applied before determining whether the source file is absolute. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +.PD 0 +.IP "\fB\-\-stdout\fR" 4 +.IX Item "--stdout" +.PD +Output to standard output instead of output files. +.IP "\fB\-u\fR" 4 +.IX Item "-u" +.PD 0 +.IP "\fB\-\-unconditional\-branches\fR" 4 +.IX Item "--unconditional-branches" +.PD +When branch probabilities are given, include those of unconditional branches. +Unconditional branches are normally not interesting. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the \fBgcov\fR version number (on the standard output), +and exit without doing any further processing. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Print verbose informations related to basic blocks and arcs. +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.PD 0 +.IP "\fB\-\-hash\-filenames\fR" 4 +.IX Item "--hash-filenames" +.PD +When using \fI\-\-preserve\-paths\fR, +gcov uses the full pathname of the source files to create +an output filename. This can lead to long filenames that can overflow +filesystem limits. This option creates names of the form +\&\fI\fIsource-file\fI##\fImd5\fI.gcov\fR, +where the \fIsource-file\fR component is the final filename part and +the \fImd5\fR component is calculated from the full mangled name that +would have been used otherwise. The option is an alternative +to the \fI\-\-preserve\-paths\fR on systems which have a filesystem limit. +.PP +\&\fBgcov\fR should be run with the current directory the same as that +when you invoked the compiler. Otherwise it will not be able to locate +the source files. \fBgcov\fR produces files called +\&\fI\fImangledname\fI.gcov\fR in the current directory. These contain +the coverage information of the source file they correspond to. +One \fI.gcov\fR file is produced for each source (or header) file +containing code, +which was compiled to produce the data files. The \fImangledname\fR part +of the output file name is usually simply the source file name, but can +be something more complicated if the \fB\-l\fR or \fB\-p\fR options are +given. Refer to those options for details. +.PP +If you invoke \fBgcov\fR with multiple input files, the +contributions from each input file are summed. Typically you would +invoke it with the same list of files as the final link of your executable. +.PP +The \fI.gcov\fR files contain the \fB:\fR separated fields along with +program source code. The format is +.PP +.Vb 1 +\& :: +.Ve +.PP +Additional block information may succeed each line, when requested by +command line option. The \fIexecution_count\fR is \fB\-\fR for lines +containing no code. Unexecuted lines are marked \fB#####\fR or +\&\fB=====\fR, depending on whether they are reachable by +non-exceptional paths or only exceptional paths such as \*(C+ exception +handlers, respectively. Given the \fB\-a\fR option, unexecuted blocks are +marked \fB$$$$$\fR or \fB%%%%%\fR, depending on whether a basic block +is reachable via non-exceptional or exceptional paths. +Executed basic blocks having a statement with zero \fIexecution_count\fR +end with \fB*\fR character and are colored with magenta color with +the \fB\-k\fR option. This functionality is not supported in Ada. +.PP +Note that \s-1GCC\s0 can completely remove the bodies of functions that are +not needed \*(-- for instance if they are inlined everywhere. Such functions +are marked with \fB\-\fR, which can be confusing. +Use the \fB\-fkeep\-inline\-functions\fR and \fB\-fkeep\-static\-functions\fR +options to retain these functions and +allow gcov to properly show their \fIexecution_count\fR. +.PP +Some lines of information at the start have \fIline_number\fR of zero. +These preamble lines are of the form +.PP +.Vb 1 +\& \-:0:: +.Ve +.PP +The ordering and number of these preamble lines will be augmented as +\&\fBgcov\fR development progresses \-\-\- do not rely on them remaining +unchanged. Use \fItag\fR to locate a particular preamble line. +.PP +The additional block information is of the form +.PP +.Vb 1 +\& +.Ve +.PP +The \fIinformation\fR is human readable, but designed to be simple +enough for machine parsing too. +.PP +When printing percentages, 0% and 100% are only printed when the values +are \fIexactly\fR 0% and 100% respectively. Other values which would +conventionally be rounded to 0% or 100% are instead printed as the +nearest non-boundary value. +.PP +When using \fBgcov\fR, you must first compile your program +with a special \s-1GCC\s0 option \fB\-\-coverage\fR. +This tells the compiler to generate additional information needed by +gcov (basically a flow graph of the program) and also includes +additional code in the object files for generating the extra profiling +information needed by gcov. These additional files are placed in the +directory where the object file is located. +.PP +Running the program will cause profile output to be generated. For each +source file compiled with \fB\-fprofile\-arcs\fR, an accompanying +\&\fI.gcda\fR file will be placed in the object file directory. +.PP +Running \fBgcov\fR with your program's source file names as arguments +will now produce a listing of the code along with frequency of execution +for each line. For example, if your program is called \fItmp.cpp\fR, this +is what you see when you use the basic \fBgcov\fR facility: +.PP +.Vb 6 +\& $ g++ \-\-coverage tmp.cpp +\& $ a.out +\& $ gcov tmp.cpp \-m +\& File \*(Aqtmp.cpp\*(Aq +\& Lines executed:92.86% of 14 +\& Creating \*(Aqtmp.cpp.gcov\*(Aq +.Ve +.PP +The file \fItmp.cpp.gcov\fR contains output from \fBgcov\fR. +Here is a sample: +.PP +.Vb 10 +\& \-: 0:Source:tmp.cpp +\& \-: 0:Working directory:/home/gcc/testcase +\& \-: 0:Graph:tmp.gcno +\& \-: 0:Data:tmp.gcda +\& \-: 0:Runs:1 +\& \-: 0:Programs:1 +\& \-: 1:#include +\& \-: 2: +\& \-: 3:template +\& \-: 4:class Foo +\& \-: 5:{ +\& \-: 6: public: +\& 1*: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::Foo(): +\& #####: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::Foo(): +\& 1: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& 2*: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::inc(): +\& #####: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::inc(): +\& 2: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& \-: 9: +\& \-: 10: private: +\& \-: 11: int b; +\& \-: 12:}; +\& \-: 13: +\& \-: 14:template class Foo; +\& \-: 15:template class Foo; +\& \-: 16: +\& \-: 17:int +\& 1: 18:main (void) +\& \-: 19:{ +\& \-: 20: int i, total; +\& 1: 21: Foo counter; +\& \-: 22: +\& 1: 23: counter.inc(); +\& 1: 24: counter.inc(); +\& 1: 25: total = 0; +\& \-: 26: +\& 11: 27: for (i = 0; i < 10; i++) +\& 10: 28: total += i; +\& \-: 29: +\& 1*: 30: int v = total > 100 ? 1 : 2; +\& \-: 31: +\& 1: 32: if (total != 45) +\& #####: 33: printf ("Failure\en"); +\& \-: 34: else +\& 1: 35: printf ("Success\en"); +\& 1: 36: return 0; +\& \-: 37:} +.Ve +.PP +Note that line 7 is shown in the report multiple times. First occurrence +presents total number of execution of the line and the next two belong +to instances of class Foo constructors. As you can also see, line 30 contains +some unexecuted basic blocks and thus execution count has asterisk symbol. +.PP +When you use the \fB\-a\fR option, you will get individual block +counts, and the output looks like this: +.PP +.Vb 10 +\& \-: 0:Source:tmp.cpp +\& \-: 0:Working directory:/home/gcc/testcase +\& \-: 0:Graph:tmp.gcno +\& \-: 0:Data:tmp.gcda +\& \-: 0:Runs:1 +\& \-: 0:Programs:1 +\& \-: 1:#include +\& \-: 2: +\& \-: 3:template +\& \-: 4:class Foo +\& \-: 5:{ +\& \-: 6: public: +\& 1*: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::Foo(): +\& #####: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::Foo(): +\& 1: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& 2*: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::inc(): +\& #####: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::inc(): +\& 2: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& \-: 9: +\& \-: 10: private: +\& \-: 11: int b; +\& \-: 12:}; +\& \-: 13: +\& \-: 14:template class Foo; +\& \-: 15:template class Foo; +\& \-: 16: +\& \-: 17:int +\& 1: 18:main (void) +\& \-: 19:{ +\& \-: 20: int i, total; +\& 1: 21: Foo counter; +\& 1: 21\-block 0 +\& \-: 22: +\& 1: 23: counter.inc(); +\& 1: 23\-block 0 +\& 1: 24: counter.inc(); +\& 1: 24\-block 0 +\& 1: 25: total = 0; +\& \-: 26: +\& 11: 27: for (i = 0; i < 10; i++) +\& 1: 27\-block 0 +\& 11: 27\-block 1 +\& 10: 28: total += i; +\& 10: 28\-block 0 +\& \-: 29: +\& 1*: 30: int v = total > 100 ? 1 : 2; +\& 1: 30\-block 0 +\& %%%%%: 30\-block 1 +\& 1: 30\-block 2 +\& \-: 31: +\& 1: 32: if (total != 45) +\& 1: 32\-block 0 +\& #####: 33: printf ("Failure\en"); +\& %%%%%: 33\-block 0 +\& \-: 34: else +\& 1: 35: printf ("Success\en"); +\& 1: 35\-block 0 +\& 1: 36: return 0; +\& 1: 36\-block 0 +\& \-: 37:} +.Ve +.PP +In this mode, each basic block is only shown on one line \*(-- the last +line of the block. A multi-line block will only contribute to the +execution count of that last line, and other lines will not be shown +to contain code, unless previous blocks end on those lines. +The total execution count of a line is shown and subsequent lines show +the execution counts for individual blocks that end on that line. After each +block, the branch and call counts of the block will be shown, if the +\&\fB\-b\fR option is given. +.PP +Because of the way \s-1GCC\s0 instruments calls, a call count can be shown +after a line with no individual blocks. +As you can see, line 33 contains a basic block that was not executed. +.PP +When you use the \fB\-b\fR option, your output looks like this: +.PP +.Vb 10 +\& \-: 0:Source:tmp.cpp +\& \-: 0:Working directory:/home/gcc/testcase +\& \-: 0:Graph:tmp.gcno +\& \-: 0:Data:tmp.gcda +\& \-: 0:Runs:1 +\& \-: 0:Programs:1 +\& \-: 1:#include +\& \-: 2: +\& \-: 3:template +\& \-: 4:class Foo +\& \-: 5:{ +\& \-: 6: public: +\& 1*: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::Foo(): +\& function Foo::Foo() called 0 returned 0% blocks executed 0% +\& #####: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::Foo(): +\& function Foo::Foo() called 1 returned 100% blocks executed 100% +\& 1: 7: Foo(): b (1000) {} +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& 2*: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::inc(): +\& function Foo::inc() called 0 returned 0% blocks executed 0% +\& #####: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& Foo::inc(): +\& function Foo::inc() called 2 returned 100% blocks executed 100% +\& 2: 8: void inc () { b++; } +\& \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\- +\& \-: 9: +\& \-: 10: private: +\& \-: 11: int b; +\& \-: 12:}; +\& \-: 13: +\& \-: 14:template class Foo; +\& \-: 15:template class Foo; +\& \-: 16: +\& \-: 17:int +\& function main called 1 returned 100% blocks executed 81% +\& 1: 18:main (void) +\& \-: 19:{ +\& \-: 20: int i, total; +\& 1: 21: Foo counter; +\& call 0 returned 100% +\& branch 1 taken 100% (fallthrough) +\& branch 2 taken 0% (throw) +\& \-: 22: +\& 1: 23: counter.inc(); +\& call 0 returned 100% +\& branch 1 taken 100% (fallthrough) +\& branch 2 taken 0% (throw) +\& 1: 24: counter.inc(); +\& call 0 returned 100% +\& branch 1 taken 100% (fallthrough) +\& branch 2 taken 0% (throw) +\& 1: 25: total = 0; +\& \-: 26: +\& 11: 27: for (i = 0; i < 10; i++) +\& branch 0 taken 91% (fallthrough) +\& branch 1 taken 9% +\& 10: 28: total += i; +\& \-: 29: +\& 1*: 30: int v = total > 100 ? 1 : 2; +\& branch 0 taken 0% (fallthrough) +\& branch 1 taken 100% +\& \-: 31: +\& 1: 32: if (total != 45) +\& branch 0 taken 0% (fallthrough) +\& branch 1 taken 100% +\& #####: 33: printf ("Failure\en"); +\& call 0 never executed +\& branch 1 never executed +\& branch 2 never executed +\& \-: 34: else +\& 1: 35: printf ("Success\en"); +\& call 0 returned 100% +\& branch 1 taken 100% (fallthrough) +\& branch 2 taken 0% (throw) +\& 1: 36: return 0; +\& \-: 37:} +.Ve +.PP +For each function, a line is printed showing how many times the function +is called, how many times it returns and what percentage of the +function's blocks were executed. +.PP +For each basic block, a line is printed after the last line of the basic +block describing the branch or call that ends the basic block. There can +be multiple branches and calls listed for a single source line if there +are multiple basic blocks that end on that line. In this case, the +branches and calls are each given a number. There is no simple way to map +these branches and calls back to source constructs. In general, though, +the lowest numbered branch or call will correspond to the leftmost construct +on the source line. +.PP +For a branch, if it was executed at least once, then a percentage +indicating the number of times the branch was taken divided by the +number of times the branch was executed will be printed. Otherwise, the +message \*(L"never executed\*(R" is printed. +.PP +For a call, if it was executed at least once, then a percentage +indicating the number of times the call returned divided by the number +of times the call was executed will be printed. This will usually be +100%, but may be less for functions that call \f(CW\*(C`exit\*(C'\fR or \f(CW\*(C`longjmp\*(C'\fR, +and thus may not return every time they are called. +.PP +The execution counts are cumulative. If the example program were +executed again without removing the \fI.gcda\fR file, the count for the +number of times each line in the source was executed would be added to +the results of the previous run(s). This is potentially useful in +several ways. For example, it could be used to accumulate data over a +number of program runs as part of a test verification suite, or to +provide more accurate long-term information over a large number of +program runs. +.PP +The data in the \fI.gcda\fR files is saved immediately before the program +exits. For each source file compiled with \fB\-fprofile\-arcs\fR, the +profiling code first attempts to read in an existing \fI.gcda\fR file; if +the file doesn't match the executable (differing number of basic block +counts) it will ignore the contents of the file. It then adds in the +new execution counts and finally writes the data to the file. +.SS "Using \fBgcov\fP with \s-1GCC\s0 Optimization" +.IX Subsection "Using gcov with GCC Optimization" +If you plan to use \fBgcov\fR to help optimize your code, you must +first compile your program with a special \s-1GCC\s0 option +\&\fB\-\-coverage\fR. Aside from that, you can use any +other \s-1GCC\s0 options; but if you want to prove that every single line +in your program was executed, you should not compile with optimization +at the same time. On some machines the optimizer can eliminate some +simple code lines by combining them with other lines. For example, code +like this: +.PP +.Vb 4 +\& if (a != b) +\& c = 1; +\& else +\& c = 0; +.Ve +.PP +can be compiled into one instruction on some machines. In this case, +there is no way for \fBgcov\fR to calculate separate execution counts +for each line because there isn't separate code for each line. Hence +the \fBgcov\fR output looks like this if you compiled the program with +optimization: +.PP +.Vb 4 +\& 100: 12:if (a != b) +\& 100: 13: c = 1; +\& 100: 14:else +\& 100: 15: c = 0; +.Ve +.PP +The output shows that this block of code, combined by optimization, +executed 100 times. In one sense this result is correct, because there +was only one instruction representing all four of these lines. However, +the output does not indicate how many times the result was 0 and how +many times the result was 1. +.PP +Inlineable functions can create unexpected line counts. Line counts are +shown for the source code of the inlineable function, but what is shown +depends on where the function is inlined, or if it is not inlined at all. +.PP +If the function is not inlined, the compiler must emit an out of line +copy of the function, in any object file that needs it. If +\&\fIfileA.o\fR and \fIfileB.o\fR both contain out of line bodies of a +particular inlineable function, they will also both contain coverage +counts for that function. When \fIfileA.o\fR and \fIfileB.o\fR are +linked together, the linker will, on many systems, select one of those +out of line bodies for all calls to that function, and remove or ignore +the other. Unfortunately, it will not remove the coverage counters for +the unused function body. Hence when instrumented, all but one use of +that function will show zero counts. +.PP +If the function is inlined in several places, the block structure in +each location might not be the same. For instance, a condition might +now be calculable at compile time in some instances. Because the +coverage of all the uses of the inline function will be shown for the +same source lines, the line counts themselves might seem inconsistent. +.PP +Long-running applications can use the \f(CW\*(C`_\|_gcov_reset\*(C'\fR and \f(CW\*(C`_\|_gcov_dump\*(C'\fR +facilities to restrict profile collection to the program region of +interest. Calling \f(CW\*(C`_\|_gcov_reset(void)\*(C'\fR will clear all profile counters +to zero, and calling \f(CW\*(C`_\|_gcov_dump(void)\*(C'\fR will cause the profile information +collected at that point to be dumped to \fI.gcda\fR output files. +Instrumented applications use a static destructor with priority 99 +to invoke the \f(CW\*(C`_\|_gcov_dump\*(C'\fR function. Thus \f(CW\*(C`_\|_gcov_dump\*(C'\fR +is executed after all user defined static destructors, +as well as handlers registered with \f(CW\*(C`atexit\*(C'\fR. +If an executable loads a dynamic shared object via dlopen functionality, +\&\fB\-Wl,\-\-dynamic\-list\-data\fR is needed to dump all profile data. +.PP +Profiling run-time library reports various errors related to profile +manipulation and profile saving. Errors are printed into standard error output +or \fB\s-1GCOV_ERROR_FILE\s0\fR file, if environment variable is used. +In order to terminate immediately after an errors occurs +set \fB\s-1GCOV_EXIT_AT_ERROR\s0\fR environment variable. +That can help users to find profile clashing which leads +to a misleading profile. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), \fIgcc\fR\|(1) and the Info entry for \fIgcc\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1996\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fIgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man1/gfortran.1 b/man/man1/gfortran.1 new file mode 100644 index 0000000000000000000000000000000000000000..3cdefb326cd92938ea2f5b8f11e7eaa5fb3a7e77 --- /dev/null +++ b/man/man1/gfortran.1 @@ -0,0 +1,1683 @@ +.\" Automatically generated by Pod::Man 4.14 (Pod::Simple 3.40) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. 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Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gfortran \- GNU Fortran compiler +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gfortran [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] + [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] + [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] + [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-f\fR\fIoption\fR...] + [\fB\-m\fR\fImachine-option\fR...] + [\fB\-o\fR \fIoutfile\fR] \fIinfile\fR... +.PP +Only the most useful options are listed here; see below for the +remainder. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The \fBgfortran\fR command supports all the options supported by the +\&\fBgcc\fR command. Only options specific to \s-1GNU\s0 Fortran are documented +here. +.PP +All \s-1GCC\s0 and \s-1GNU\s0 Fortran options +are accepted both by \fBgfortran\fR and by \fBgcc\fR +(as well as any other drivers built at the same time, +such as \fBg++\fR), +since adding \s-1GNU\s0 Fortran to the \s-1GCC\s0 distribution +enables acceptance of \s-1GNU\s0 Fortran options +by all of the relevant drivers. +.PP +In some cases, options have positive and negative forms; +the negative form of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. +This manual documents only one of these two forms, whichever +one is not the default. +.SH "OPTIONS" +.IX Header "OPTIONS" +Here is a summary of all the options specific to \s-1GNU\s0 Fortran, grouped +by type. Explanations are in the following sections. +.IP "\fIFortran Language Options\fR" 4 +.IX Item "Fortran Language Options" +\&\fB\-fall\-intrinsics \-fbackslash \-fcray\-pointer \-fd\-lines\-as\-code +\&\-fd\-lines\-as\-comments +\&\-fdec \-fdec\-structure \-fdec\-intrinsic\-ints \-fdec\-static \-fdec\-math +\&\-fdec\-include \-fdefault\-double\-8 \-fdefault\-integer\-8 \-fdefault\-real\-8 +\&\-fdefault\-real\-10 \-fdefault\-real\-16 \-fdollar\-ok \-ffixed\-line\-length\-\fR\fIn\fR +\&\fB\-ffixed\-line\-length\-none \-fpad\-source \-ffree\-form \-ffree\-line\-length\-\fR\fIn\fR +\&\fB\-ffree\-line\-length\-none \-fimplicit\-none \-finteger\-4\-integer\-8 +\&\-fmax\-identifier\-length \-fmodule\-private \-ffixed\-form \-fno\-range\-check +\&\-fopenacc \-fopenmp \-freal\-4\-real\-10 \-freal\-4\-real\-16 \-freal\-4\-real\-8 +\&\-freal\-8\-real\-10 \-freal\-8\-real\-16 \-freal\-8\-real\-4 \-std=\fR\fIstd\fR +\&\fB\-ftest\-forall\-temp\fR +.IP "\fIPreprocessing Options\fR" 4 +.IX Item "Preprocessing Options" +\&\fB\-A\-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] +\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR \fB\-C \-CC \-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR] +\&\fB\-H \-P +\&\-U\fR\fImacro\fR \fB\-cpp \-dD \-dI \-dM \-dN \-dU \-fworking\-directory +\&\-imultilib\fR \fIdir\fR +\&\fB\-iprefix\fR \fIfile\fR \fB\-iquote \-isysroot\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR \fB\-nocpp +\&\-nostdinc +\&\-undef\fR +.IP "\fIError and Warning Options\fR" 4 +.IX Item "Error and Warning Options" +\&\fB\-Waliasing \-Wall \-Wampersand \-Wargument\-mismatch \-Warray\-bounds +\&\-Wc\-binding\-type \-Wcharacter\-truncation \-Wconversion +\&\-Wdo\-subscript \-Wfunction\-elimination \-Wimplicit\-interface +\&\-Wimplicit\-procedure \-Wintrinsic\-shadow \-Wuse\-without\-only \-Wintrinsics\-std +\&\-Wline\-truncation \-Wno\-align\-commons \-Wno\-tabs \-Wreal\-q\-constant +\&\-Wsurprising \-Wunderflow \-Wunused\-parameter \-Wrealloc\-lhs +\&\-Wrealloc\-lhs\-all \-Wfrontend\-loop\-interchange \-Wtarget\-lifetime +\&\-fmax\-errors=\fR\fIn\fR \fB\-fsyntax\-only \-pedantic \-pedantic\-errors\fR +.IP "\fIDebugging Options\fR" 4 +.IX Item "Debugging Options" +\&\fB\-fbacktrace \-fdump\-fortran\-optimized \-fdump\-fortran\-original +\&\-fdump\-fortran\-global \-fdump\-parse\-tree \-ffpe\-trap=\fR\fIlist\fR +\&\fB\-ffpe\-summary=\fR\fIlist\fR\fB \fR +.IP "\fIDirectory Options\fR" 4 +.IX Item "Directory Options" +\&\fB\-I\fR\fIdir\fR \fB\-J\fR\fIdir\fR \fB\-fintrinsic\-modules\-path\fR \fIdir\fR +.IP "\fILink Options\fR" 4 +.IX Item "Link Options" +\&\fB\-static\-libgfortran\fR +.IP "\fIRuntime Options\fR" 4 +.IX Item "Runtime Options" +\&\fB\-fconvert=\fR\fIconversion\fR \fB\-fmax\-subrecord\-length=\fR\fIlength\fR +\&\fB\-frecord\-marker=\fR\fIlength\fR \fB\-fsign\-zero\fR +.IP "\fIInteroperability Options\fR" 4 +.IX Item "Interoperability Options" +\&\fB\-fc\-prototypes \-fc\-prototypes\-external\fR +.IP "\fICode Generation Options\fR" 4 +.IX Item "Code Generation Options" +\&\fB\-faggressive\-function\-elimination \-fblas\-matmul\-limit=\fR\fIn\fR +\&\fB\-fbounds\-check \-ftail\-call\-workaround \-ftail\-call\-workaround=\fR\fIn\fR +\&\fB\-fcheck\-array\-temporaries +\&\-fcheck=\fR\fI\fR +\&\fB\-fcoarray=\fR\fI\fR \fB\-fexternal\-blas \-ff2c +\&\-ffrontend\-loop\-interchange +\&\-ffrontend\-optimize +\&\-finit\-character=\fR\fIn\fR \fB\-finit\-integer=\fR\fIn\fR \fB\-finit\-local\-zero +\&\-finit\-derived +\&\-finit\-logical=\fR\fI\fR +\&\fB\-finit\-real=\fR\fI\fR +\&\fB\-finline\-matmul\-limit=\fR\fIn\fR +\&\fB\-fmax\-array\-constructor=\fR\fIn\fR \fB\-fmax\-stack\-var\-size=\fR\fIn\fR +\&\fB\-fno\-align\-commons +\&\-fno\-automatic \-fno\-protect\-parens \-fno\-underscoring +\&\-fsecond\-underscore \-fpack\-derived \-frealloc\-lhs \-frecursive +\&\-frepack\-arrays \-fshort\-enums \-fstack\-arrays\fR +.SS "Options controlling Fortran dialect" +.IX Subsection "Options controlling Fortran dialect" +The following options control the details of the Fortran dialect +accepted by the compiler: +.IP "\fB\-ffree\-form\fR" 4 +.IX Item "-ffree-form" +.PD 0 +.IP "\fB\-ffixed\-form\fR" 4 +.IX Item "-ffixed-form" +.PD +Specify the layout used by the source file. The free form layout +was introduced in Fortran 90. Fixed form was traditionally used in +older Fortran programs. When neither option is specified, the source +form is determined by the file extension. +.IP "\fB\-fall\-intrinsics\fR" 4 +.IX Item "-fall-intrinsics" +This option causes all intrinsic procedures (including the GNU-specific +extensions) to be accepted. This can be useful with \fB\-std=f95\fR to +force standard-compliance but get access to the full range of intrinsics +available with \fBgfortran\fR. As a consequence, \fB\-Wintrinsics\-std\fR +will be ignored and no user-defined procedure with the same name as any +intrinsic will be called except when it is explicitly declared \f(CW\*(C`EXTERNAL\*(C'\fR. +.IP "\fB\-fd\-lines\-as\-code\fR" 4 +.IX Item "-fd-lines-as-code" +.PD 0 +.IP "\fB\-fd\-lines\-as\-comments\fR" 4 +.IX Item "-fd-lines-as-comments" +.PD +Enable special treatment for lines beginning with \f(CW\*(C`d\*(C'\fR or \f(CW\*(C`D\*(C'\fR +in fixed form sources. If the \fB\-fd\-lines\-as\-code\fR option is +given they are treated as if the first column contained a blank. If the +\&\fB\-fd\-lines\-as\-comments\fR option is given, they are treated as +comment lines. +.IP "\fB\-fdec\fR" 4 +.IX Item "-fdec" +\&\s-1DEC\s0 compatibility mode. Enables extensions and other features that mimic +the default behavior of older compilers (such as \s-1DEC\s0). +These features are non-standard and should be avoided at all costs. +For details on \s-1GNU\s0 Fortran's implementation of these extensions see the +full documentation. +.Sp +Other flags enabled by this switch are: +\&\fB\-fdollar\-ok\fR \fB\-fcray\-pointer\fR \fB\-fdec\-structure\fR +\&\fB\-fdec\-intrinsic\-ints\fR \fB\-fdec\-static\fR \fB\-fdec\-math\fR +.Sp +If \fB\-fd\-lines\-as\-code\fR/\fB\-fd\-lines\-as\-comments\fR are unset, then +\&\fB\-fdec\fR also sets \fB\-fd\-lines\-as\-comments\fR. +.IP "\fB\-fdec\-structure\fR" 4 +.IX Item "-fdec-structure" +Enable \s-1DEC\s0 \f(CW\*(C`STRUCTURE\*(C'\fR and \f(CW\*(C`RECORD\*(C'\fR as well as \f(CW\*(C`UNION\*(C'\fR, +\&\f(CW\*(C`MAP\*(C'\fR, and dot ('.') as a member separator (in addition to '%'). This is +provided for compatibility only; Fortran 90 derived types should be used +instead where possible. +.IP "\fB\-fdec\-intrinsic\-ints\fR" 4 +.IX Item "-fdec-intrinsic-ints" +Enable B/I/J/K kind variants of existing integer functions (e.g. \s-1BIAND, IIAND, +JIAND,\s0 etc...). For a complete list of intrinsics see the full documentation. +.IP "\fB\-fdec\-math\fR" 4 +.IX Item "-fdec-math" +Enable legacy math intrinsics such as \s-1COTAN\s0 and degree-valued trigonometric +functions (e.g. \s-1TAND, ATAND,\s0 etc...) for compatability with older code. +.IP "\fB\-fdec\-static\fR" 4 +.IX Item "-fdec-static" +Enable DEC-style \s-1STATIC\s0 and \s-1AUTOMATIC\s0 attributes to explicitly specify +the storage of variables and other objects. +.IP "\fB\-fdec\-include\fR" 4 +.IX Item "-fdec-include" +Enable parsing of \s-1INCLUDE\s0 as a statement in addition to parsing it as +\&\s-1INCLUDE\s0 line. When parsed as \s-1INCLUDE\s0 statement, \s-1INCLUDE\s0 does not have to +be on a single line and can use line continuations. +.IP "\fB\-fdollar\-ok\fR" 4 +.IX Item "-fdollar-ok" +Allow \fB$\fR as a valid non-first character in a symbol name. Symbols +that start with \fB$\fR are rejected since it is unclear which rules to +apply to implicit typing as different vendors implement different rules. +Using \fB$\fR in \f(CW\*(C`IMPLICIT\*(C'\fR statements is also rejected. +.IP "\fB\-fbackslash\fR" 4 +.IX Item "-fbackslash" +Change the interpretation of backslashes in string literals from a single +backslash character to \*(L"C\-style\*(R" escape characters. The following +combinations are expanded \f(CW\*(C`\ea\*(C'\fR, \f(CW\*(C`\eb\*(C'\fR, \f(CW\*(C`\ef\*(C'\fR, \f(CW\*(C`\en\*(C'\fR, +\&\f(CW\*(C`\er\*(C'\fR, \f(CW\*(C`\et\*(C'\fR, \f(CW\*(C`\ev\*(C'\fR, \f(CW\*(C`\e\e\*(C'\fR, and \f(CW\*(C`\e0\*(C'\fR to the \s-1ASCII\s0 +characters alert, backspace, form feed, newline, carriage return, +horizontal tab, vertical tab, backslash, and \s-1NUL,\s0 respectively. +Additionally, \f(CW\*(C`\ex\*(C'\fR\fInn\fR, \f(CW\*(C`\eu\*(C'\fR\fInnnn\fR and +\&\f(CW\*(C`\eU\*(C'\fR\fInnnnnnnn\fR (where each \fIn\fR is a hexadecimal digit) are +translated into the Unicode characters corresponding to the specified code +points. All other combinations of a character preceded by \e are +unexpanded. +.IP "\fB\-fmodule\-private\fR" 4 +.IX Item "-fmodule-private" +Set the default accessibility of module entities to \f(CW\*(C`PRIVATE\*(C'\fR. +Use-associated entities will not be accessible unless they are explicitly +declared as \f(CW\*(C`PUBLIC\*(C'\fR. +.IP "\fB\-ffixed\-line\-length\-\fR\fIn\fR" 4 +.IX Item "-ffixed-line-length-n" +Set column after which characters are ignored in typical fixed-form +lines in the source file, and, unless \f(CW\*(C`\-fno\-pad\-source\*(C'\fR, through which +spaces are assumed (as if padded to that length) after the ends of short +fixed-form lines. +.Sp +Popular values for \fIn\fR include 72 (the +standard and the default), 80 (card image), and 132 (corresponding +to \*(L"extended-source\*(R" options in some popular compilers). +\&\fIn\fR may also be \fBnone\fR, meaning that the entire line is meaningful +and that continued character constants never have implicit spaces appended +to them to fill out the line. +\&\fB\-ffixed\-line\-length\-0\fR means the same thing as +\&\fB\-ffixed\-line\-length\-none\fR. +.IP "\fB\-fno\-pad\-source\fR" 4 +.IX Item "-fno-pad-source" +By default fixed-form lines have spaces assumed (as if padded to that length) +after the ends of short fixed-form lines. This is not done either if +\&\fB\-ffixed\-line\-length\-0\fR, \fB\-ffixed\-line\-length\-none\fR or +if \fB\-fno\-pad\-source\fR option is used. With any of those options +continued character constants never have implicit spaces appended +to them to fill out the line. +.IP "\fB\-ffree\-line\-length\-\fR\fIn\fR" 4 +.IX Item "-ffree-line-length-n" +Set column after which characters are ignored in typical free-form +lines in the source file. The default value is 132. +\&\fIn\fR may be \fBnone\fR, meaning that the entire line is meaningful. +\&\fB\-ffree\-line\-length\-0\fR means the same thing as +\&\fB\-ffree\-line\-length\-none\fR. +.IP "\fB\-fmax\-identifier\-length=\fR\fIn\fR" 4 +.IX Item "-fmax-identifier-length=n" +Specify the maximum allowed identifier length. Typical values are +31 (Fortran 95) and 63 (Fortran 2003 and Fortran 2008). +.IP "\fB\-fimplicit\-none\fR" 4 +.IX Item "-fimplicit-none" +Specify that no implicit typing is allowed, unless overridden by explicit +\&\f(CW\*(C`IMPLICIT\*(C'\fR statements. This is the equivalent of adding +\&\f(CW\*(C`implicit none\*(C'\fR to the start of every procedure. +.IP "\fB\-fcray\-pointer\fR" 4 +.IX Item "-fcray-pointer" +Enable the Cray pointer extension, which provides C\-like pointer +functionality. +.IP "\fB\-fopenacc\fR" 4 +.IX Item "-fopenacc" +Enable the OpenACC extensions. This includes OpenACC \f(CW\*(C`!$acc\*(C'\fR +directives in free form and \f(CW\*(C`c$acc\*(C'\fR, \f(CW*$acc\fR and +\&\f(CW\*(C`!$acc\*(C'\fR directives in fixed form, \f(CW\*(C`!$\*(C'\fR conditional +compilation sentinels in free form and \f(CW\*(C`c$\*(C'\fR, \f(CW\*(C`*$\*(C'\fR and +\&\f(CW\*(C`!$\*(C'\fR sentinels in fixed form, and when linking arranges for the +OpenACC runtime library to be linked in. +.Sp +Note that this is an experimental feature, incomplete, and subject to +change in future versions of \s-1GCC.\s0 See +<\fBhttps://gcc.gnu.org/wiki/OpenACC\fR> for more information. +.IP "\fB\-fopenmp\fR" 4 +.IX Item "-fopenmp" +Enable the OpenMP extensions. This includes OpenMP \f(CW\*(C`!$omp\*(C'\fR directives +in free form +and \f(CW\*(C`c$omp\*(C'\fR, \f(CW*$omp\fR and \f(CW\*(C`!$omp\*(C'\fR directives in fixed form, +\&\f(CW\*(C`!$\*(C'\fR conditional compilation sentinels in free form +and \f(CW\*(C`c$\*(C'\fR, \f(CW\*(C`*$\*(C'\fR and \f(CW\*(C`!$\*(C'\fR sentinels in fixed form, +and when linking arranges for the OpenMP runtime library to be linked +in. The option \fB\-fopenmp\fR implies \fB\-frecursive\fR. +.IP "\fB\-fno\-range\-check\fR" 4 +.IX Item "-fno-range-check" +Disable range checking on results of simplification of constant +expressions during compilation. For example, \s-1GNU\s0 Fortran will give +an error at compile time when simplifying \f(CW\*(C`a = 1. / 0\*(C'\fR. +With this option, no error will be given and \f(CW\*(C`a\*(C'\fR will be assigned +the value \f(CW\*(C`+Infinity\*(C'\fR. If an expression evaluates to a value +outside of the relevant range of [\f(CW\*(C`\-HUGE()\*(C'\fR:\f(CW\*(C`HUGE()\*(C'\fR], +then the expression will be replaced by \f(CW\*(C`\-Inf\*(C'\fR or \f(CW\*(C`+Inf\*(C'\fR +as appropriate. +Similarly, \f(CW\*(C`DATA i/Z\*(AqFFFFFFFF\*(Aq/\*(C'\fR will result in an integer overflow +on most systems, but with \fB\-fno\-range\-check\fR the value will +\&\*(L"wrap around\*(R" and \f(CW\*(C`i\*(C'\fR will be initialized to \-1 instead. +.IP "\fB\-fdefault\-integer\-8\fR" 4 +.IX Item "-fdefault-integer-8" +Set the default integer and logical types to an 8 byte wide type. This option +also affects the kind of integer constants like \f(CW42\fR. Unlike +\&\fB\-finteger\-4\-integer\-8\fR, it does not promote variables with explicit +kind declaration. +.IP "\fB\-fdefault\-real\-8\fR" 4 +.IX Item "-fdefault-real-8" +Set the default real type to an 8 byte wide type. This option also affects +the kind of non-double real constants like \f(CW1.0\fR. This option promotes +the default width of \f(CW\*(C`DOUBLE PRECISION\*(C'\fR and double real constants +like \f(CW\*(C`1.d0\*(C'\fR to 16 bytes if possible. If \f(CW\*(C`\-fdefault\-double\-8\*(C'\fR +is given along with \f(CW\*(C`fdefault\-real\-8\*(C'\fR, \f(CW\*(C`DOUBLE PRECISION\*(C'\fR +and double real constants are not promoted. Unlike \fB\-freal\-4\-real\-8\fR, +\&\f(CW\*(C`fdefault\-real\-8\*(C'\fR does not promote variables with explicit kind +declarations. +.IP "\fB\-fdefault\-real\-10\fR" 4 +.IX Item "-fdefault-real-10" +Set the default real type to an 10 byte wide type. This option also affects +the kind of non-double real constants like \f(CW1.0\fR. This option promotes +the default width of \f(CW\*(C`DOUBLE PRECISION\*(C'\fR and double real constants +like \f(CW\*(C`1.d0\*(C'\fR to 16 bytes if possible. If \f(CW\*(C`\-fdefault\-double\-8\*(C'\fR +is given along with \f(CW\*(C`fdefault\-real\-10\*(C'\fR, \f(CW\*(C`DOUBLE PRECISION\*(C'\fR +and double real constants are not promoted. Unlike \fB\-freal\-4\-real\-10\fR, +\&\f(CW\*(C`fdefault\-real\-10\*(C'\fR does not promote variables with explicit kind +declarations. +.IP "\fB\-fdefault\-real\-16\fR" 4 +.IX Item "-fdefault-real-16" +Set the default real type to an 16 byte wide type. This option also affects +the kind of non-double real constants like \f(CW1.0\fR. This option promotes +the default width of \f(CW\*(C`DOUBLE PRECISION\*(C'\fR and double real constants +like \f(CW\*(C`1.d0\*(C'\fR to 16 bytes if possible. If \f(CW\*(C`\-fdefault\-double\-8\*(C'\fR +is given along with \f(CW\*(C`fdefault\-real\-16\*(C'\fR, \f(CW\*(C`DOUBLE PRECISION\*(C'\fR +and double real constants are not promoted. Unlike \fB\-freal\-4\-real\-16\fR, +\&\f(CW\*(C`fdefault\-real\-16\*(C'\fR does not promote variables with explicit kind +declarations. +.IP "\fB\-fdefault\-double\-8\fR" 4 +.IX Item "-fdefault-double-8" +Set the \f(CW\*(C`DOUBLE PRECISION\*(C'\fR type and double real constants +like \f(CW\*(C`1.d0\*(C'\fR to an 8 byte wide type. Do nothing if this +is already the default. This option prevents \fB\-fdefault\-real\-8\fR, +\&\fB\-fdefault\-real\-10\fR, and \fB\-fdefault\-real\-16\fR, +from promoting \f(CW\*(C`DOUBLE PRECISION\*(C'\fR and double real constants like +\&\f(CW\*(C`1.d0\*(C'\fR to 16 bytes. +.IP "\fB\-finteger\-4\-integer\-8\fR" 4 +.IX Item "-finteger-4-integer-8" +Promote all \f(CW\*(C`INTEGER(KIND=4)\*(C'\fR entities to an \f(CW\*(C`INTEGER(KIND=8)\*(C'\fR +entities. If \f(CW\*(C`KIND=8\*(C'\fR is unavailable, then an error will be issued. +This option should be used with care and may not be suitable for your codes. +Areas of possible concern include calls to external procedures, +alignment in \f(CW\*(C`EQUIVALENCE\*(C'\fR and/or \f(CW\*(C`COMMON\*(C'\fR, generic interfaces, +\&\s-1BOZ\s0 literal constant conversion, and I/O. Inspection of the intermediate +representation of the translated Fortran code, produced by +\&\fB\-fdump\-tree\-original\fR, is suggested. +.IP "\fB\-freal\-4\-real\-8\fR" 4 +.IX Item "-freal-4-real-8" +.PD 0 +.IP "\fB\-freal\-4\-real\-10\fR" 4 +.IX Item "-freal-4-real-10" +.IP "\fB\-freal\-4\-real\-16\fR" 4 +.IX Item "-freal-4-real-16" +.IP "\fB\-freal\-8\-real\-4\fR" 4 +.IX Item "-freal-8-real-4" +.IP "\fB\-freal\-8\-real\-10\fR" 4 +.IX Item "-freal-8-real-10" +.IP "\fB\-freal\-8\-real\-16\fR" 4 +.IX Item "-freal-8-real-16" +.PD +Promote all \f(CW\*(C`REAL(KIND=M)\*(C'\fR entities to \f(CW\*(C`REAL(KIND=N)\*(C'\fR entities. +If \f(CW\*(C`REAL(KIND=N)\*(C'\fR is unavailable, then an error will be issued. +All other real kind types are unaffected by this option. +These options should be used with care and may not be suitable for your +codes. Areas of possible concern include calls to external procedures, +alignment in \f(CW\*(C`EQUIVALENCE\*(C'\fR and/or \f(CW\*(C`COMMON\*(C'\fR, generic interfaces, +\&\s-1BOZ\s0 literal constant conversion, and I/O. Inspection of the intermediate +representation of the translated Fortran code, produced by +\&\fB\-fdump\-tree\-original\fR, is suggested. +.IP "\fB\-std=\fR\fIstd\fR" 4 +.IX Item "-std=std" +Specify the standard to which the program is expected to conform, +which may be one of \fBf95\fR, \fBf2003\fR, \fBf2008\fR, +\&\fBf2018\fR, \fBgnu\fR, or \fBlegacy\fR. The default value for +\&\fIstd\fR is \fBgnu\fR, which specifies a superset of the latest +Fortran standard that includes all of the extensions supported by \s-1GNU\s0 +Fortran, although warnings will be given for obsolete extensions not +recommended for use in new code. The \fBlegacy\fR value is +equivalent but without the warnings for obsolete extensions, and may +be useful for old non-standard programs. The \fBf95\fR, +\&\fBf2003\fR, \fBf2008\fR, and \fBf2018\fR values specify strict +conformance to the Fortran 95, Fortran 2003, Fortran 2008 and Fortran +2018 standards, respectively; errors are given for all extensions +beyond the relevant language standard, and warnings are given for the +Fortran 77 features that are permitted but obsolescent in later +standards. The deprecated option \fB\-std=f2008ts\fR acts as an alias for +\&\fB\-std=f2018\fR. It is only present for backwards compatibility with +earlier gfortran versions and should not be used any more. +.IP "\fB\-ftest\-forall\-temp\fR" 4 +.IX Item "-ftest-forall-temp" +Enhance test coverage by forcing most forall assignments to use temporary. +.SS "Enable and customize preprocessing" +.IX Subsection "Enable and customize preprocessing" +Preprocessor related options. See section +\&\fBPreprocessing and conditional compilation\fR for more detailed +information on preprocessing in \fBgfortran\fR. +.IP "\fB\-cpp\fR" 4 +.IX Item "-cpp" +.PD 0 +.IP "\fB\-nocpp\fR" 4 +.IX Item "-nocpp" +.PD +Enable preprocessing. The preprocessor is automatically invoked if +the file extension is \fI.fpp\fR, \fI.FPP\fR, \fI.F\fR, \fI.FOR\fR, +\&\fI.FTN\fR, \fI.F90\fR, \fI.F95\fR, \fI.F03\fR or \fI.F08\fR. Use +this option to manually enable preprocessing of any kind of Fortran file. +.Sp +To disable preprocessing of files with any of the above listed extensions, +use the negative form: \fB\-nocpp\fR. +.Sp +The preprocessor is run in traditional mode. Any restrictions of the +file-format, especially the limits on line length, apply for +preprocessed output as well, so it might be advisable to use the +\&\fB\-ffree\-line\-length\-none\fR or \fB\-ffixed\-line\-length\-none\fR +options. +.IP "\fB\-dM\fR" 4 +.IX Item "-dM" +Instead of the normal output, generate a list of \f(CW\*(Aq#define\*(Aq\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way +of finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.f90\fR, the command +.Sp +.Vb 1 +\& touch foo.f90; gfortran \-cpp \-E \-dM foo.f90 +.Ve +.Sp +will show all the predefined macros. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Like \fB\-dM\fR except in two respects: it does not include the +predefined macros, and it outputs both the \f(CW\*(C`#define\*(C'\fR directives +and the result of preprocessing. Both kinds of output go to the +standard output file. +.IP "\fB\-dN\fR" 4 +.IX Item "-dN" +Like \fB\-dD\fR, but emit only the macro names, not their expansions. +.IP "\fB\-dU\fR" 4 +.IX Item "-dU" +Like \fBdD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and \f(CW\*(Aq#undef\*(Aq\fR +directives are also output for macros tested but undefined at the time. +.IP "\fB\-dI\fR" 4 +.IX Item "-dI" +Output \f(CW\*(Aq#include\*(Aq\fR directives in addition to the result +of preprocessing. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that will +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor will emit, +after the initial linemarker, a second linemarker with the current +working directory followed by two slashes. \s-1GCC\s0 will use this directory, +when it is present in the preprocessed input, as the directory emitted +as the current working directory in some debugging information formats. +This option is implicitly enabled if debugging information is enabled, +but this can be inhibited with the negated form +\&\fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is present +in the command line, this option has no effect, since no \f(CW\*(C`#line\*(C'\fR +directives are emitted whatsoever. +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +Search \fIdir\fR for include files, but do it after all directories +specified with \fB\-I\fR and the standard system directories have +been exhausted. \fIdir\fR is treated as a system include directory. +If dir begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced by +the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing target-specific +\&\*(C+ headers. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the \fIprefix\fR represents a directory, you should include +the final \f(CW\*(Aq/\*(Aq\fR. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files. See the \fB\-\-sysroot\fR option for more information. +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +Search \fIdir\fR only for header files requested with \f(CW\*(C`#include "file"\*(C'\fR; +they are not searched for \f(CW\*(C`#include \*(C'\fR, before all directories +specified by \fB\-I\fR and before the standard system directories. If +\&\fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced by the +sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +Search \fIdir\fR for header files, after all directories specified by +\&\fB\-I\fR but before the standard system directories. Mark it as a +system directory, so that it gets the same special treatment as is +applied to the standard system directories. If \fIdir\fR begins with +\&\f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced by the sysroot prefix; +see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. Only +the directories you have specified with \fB\-I\fR options (and the +directory of the current file, if appropriate) are searched. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. +The standard predefined macros remain defined. +.IP "\fB\-A\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-Apredicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer \fIanswer\fR. +This form is preferred to the older form \-A predicate(answer), which is still +supported, because it does not use shell special characters. +.IP "\fB\-A\-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A-predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer \fIanswer\fR. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it causes +the preprocessor to treat comments as tokens in their own right. For example, +comments appearing at the start of what would be a directive line have the +effect of turning that line into an ordinary source line, since the first +token on the line is no longer a \f(CW\*(Aq#\*(Aq\fR. +.Sp +Warning: this currently handles C\-Style comments only. The preprocessor +does not yet recognize Fortran-style comments. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is like +\&\fB\-C\fR, except that comments contained within macros are also passed +through to the output file where the macro is expanded. +.Sp +In addition to the side-effects of the \fB\-C\fR option, the \fB\-CC\fR +option causes all \*(C+\-style comments inside a macro to be converted to C\-style +comments. This is to prevent later use of that macro from inadvertently +commenting out the remainder of the source line. The \fB\-CC\fR option +is generally used to support lint comments. +.Sp +Warning: this currently handles C\- and \*(C+\-Style comments only. The +preprocessor does not yet recognize Fortran-style comments. +.IP "\fB\-D\fR\fIname\fR" 4 +.IX Item "-Dname" +Predefine name as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR\fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-Dname=definition" +The contents of \fIdefinition\fR are tokenized and processed as if they +appeared during translation phase three in a \f(CW\*(Aq#define\*(Aq\fR directive. +In particular, the definition will be truncated by embedded newline +characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like program +you may need to use the shell's quoting syntax to protect characters such +as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you will need +to quote the option. With sh and csh, \f(CW\*(C`\-D\*(Aqname(args...)=definition\*(Aq\*(C'\fR +works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they are +given on the command line. All \-imacros file and \-include file options +are processed after all \-D and \-U options. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the \f(CW\*(Aq#include\*(Aq\fR +stack it is. +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that +is not C code, and will be sent to a program which might be confused +by the linemarkers. +.IP "\fB\-U\fR\fIname\fR" 4 +.IX Item "-Uname" +Cancel any previous definition of \fIname\fR, either built in or provided +with a \fB\-D\fR option. +.SS "Options to request or suppress errors and warnings" +.IX Subsection "Options to request or suppress errors and warnings" +Errors are diagnostic messages that report that the \s-1GNU\s0 Fortran compiler +cannot compile the relevant piece of source code. The compiler will +continue to process the program in an attempt to report further errors +to aid in debugging, but will not produce any compiled output. +.PP +Warnings are diagnostic messages that report constructions which +are not inherently erroneous but which are risky or suggest there is +likely to be a bug in the program. Unless \fB\-Werror\fR is specified, +they do not prevent compilation of the program. +.PP +You can request many specific warnings with options beginning \fB\-W\fR, +for example \fB\-Wimplicit\fR to request warnings on implicit +declarations. Each of these specific warning options also has a +negative form beginning \fB\-Wno\-\fR to turn off warnings; +for example, \fB\-Wno\-implicit\fR. This manual lists only one of the +two forms, whichever is not the default. +.PP +These options control the amount and kinds of errors and warnings produced +by \s-1GNU\s0 Fortran: +.IP "\fB\-fmax\-errors=\fR\fIn\fR" 4 +.IX Item "-fmax-errors=n" +Limits the maximum number of error messages to \fIn\fR, at which point +\&\s-1GNU\s0 Fortran bails out rather than attempting to continue processing the +source code. If \fIn\fR is 0, there is no limit on the number of error +messages produced. +.IP "\fB\-fsyntax\-only\fR" 4 +.IX Item "-fsyntax-only" +Check the code for syntax errors, but do not actually compile it. This +will generate module files for each module present in the code, but no +other output file. +.IP "\fB\-Wpedantic\fR" 4 +.IX Item "-Wpedantic" +.PD 0 +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +.PD +Issue warnings for uses of extensions to Fortran. +\&\fB\-pedantic\fR also applies to C\-language constructs where they +occur in \s-1GNU\s0 Fortran source files, such as use of \fB\ee\fR in a +character constant within a directive like \f(CW\*(C`#include\*(C'\fR. +.Sp +Valid Fortran programs should compile properly with or without +this option. +However, without this option, certain \s-1GNU\s0 extensions and traditional +Fortran features are supported as well. +With this option, many of them are rejected. +.Sp +Some users try to use \fB\-pedantic\fR to check programs for conformance. +They soon find that it does not do quite what they want\-\-\-it finds some +nonstandard practices, but not all. +However, improvements to \s-1GNU\s0 Fortran in this area are welcome. +.Sp +This should be used in conjunction with \fB\-std=f95\fR, +\&\fB\-std=f2003\fR, \fB\-std=f2008\fR or \fB\-std=f2018\fR. +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Like \fB\-pedantic\fR, except that errors are produced rather than +warnings. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +Enables commonly used warning options pertaining to usage that +we recommend avoiding and that we believe are easy to avoid. +This currently includes \fB\-Waliasing\fR, \fB\-Wampersand\fR, +\&\fB\-Wconversion\fR, \fB\-Wsurprising\fR, \fB\-Wc\-binding\-type\fR, +\&\fB\-Wintrinsics\-std\fR, \fB\-Wtabs\fR, \fB\-Wintrinsic\-shadow\fR, +\&\fB\-Wline\-truncation\fR, \fB\-Wtarget\-lifetime\fR, +\&\fB\-Winteger\-division\fR, \fB\-Wreal\-q\-constant\fR, \fB\-Wunused\fR +and \fB\-Wundefined\-do\-loop\fR. +.IP "\fB\-Waliasing\fR" 4 +.IX Item "-Waliasing" +Warn about possible aliasing of dummy arguments. Specifically, it warns +if the same actual argument is associated with a dummy argument with +\&\f(CW\*(C`INTENT(IN)\*(C'\fR and a dummy argument with \f(CW\*(C`INTENT(OUT)\*(C'\fR in a call +with an explicit interface. +.Sp +The following example will trigger the warning. +.Sp +.Vb 7 +\& interface +\& subroutine bar(a,b) +\& integer, intent(in) :: a +\& integer, intent(out) :: b +\& end subroutine +\& end interface +\& integer :: a +\& +\& call bar(a,a) +.Ve +.IP "\fB\-Wampersand\fR" 4 +.IX Item "-Wampersand" +Warn about missing ampersand in continued character constants. The +warning is given with \fB\-Wampersand\fR, \fB\-pedantic\fR, +\&\fB\-std=f95\fR, \fB\-std=f2003\fR, \fB\-std=f2008\fR and +\&\fB\-std=f2018\fR. Note: With no ampersand given in a continued +character constant, \s-1GNU\s0 Fortran assumes continuation at the first +non-comment, non-whitespace character after the ampersand that +initiated the continuation. +.IP "\fB\-Wargument\-mismatch\fR" 4 +.IX Item "-Wargument-mismatch" +Warn about type, rank, and other mismatches between formal parameters and actual +arguments to functions and subroutines. These warnings are recommended and +thus enabled by default. +.IP "\fB\-Warray\-temporaries\fR" 4 +.IX Item "-Warray-temporaries" +Warn about array temporaries generated by the compiler. The information +generated by this warning is sometimes useful in optimization, in order to +avoid such temporaries. +.IP "\fB\-Wc\-binding\-type\fR" 4 +.IX Item "-Wc-binding-type" +Warn if the a variable might not be C interoperable. In particular, warn if +the variable has been declared using an intrinsic type with default kind +instead of using a kind parameter defined for C interoperability in the +intrinsic \f(CW\*(C`ISO_C_Binding\*(C'\fR module. This option is implied by +\&\fB\-Wall\fR. +.IP "\fB\-Wcharacter\-truncation\fR" 4 +.IX Item "-Wcharacter-truncation" +Warn when a character assignment will truncate the assigned string. +.IP "\fB\-Wline\-truncation\fR" 4 +.IX Item "-Wline-truncation" +Warn when a source code line will be truncated. This option is +implied by \fB\-Wall\fR. For free-form source code, the default is +\&\fB\-Werror=line\-truncation\fR such that truncations are reported as +error. +.IP "\fB\-Wconversion\fR" 4 +.IX Item "-Wconversion" +Warn about implicit conversions that are likely to change the value of +the expression after conversion. Implied by \fB\-Wall\fR. +.IP "\fB\-Wconversion\-extra\fR" 4 +.IX Item "-Wconversion-extra" +Warn about implicit conversions between different types and kinds. This +option does \fInot\fR imply \fB\-Wconversion\fR. +.IP "\fB\-Wextra\fR" 4 +.IX Item "-Wextra" +Enables some warning options for usages of language features which +may be problematic. This currently includes \fB\-Wcompare\-reals\fR, +\&\fB\-Wunused\-parameter\fR and \fB\-Wdo\-subscript\fR. +.IP "\fB\-Wfrontend\-loop\-interchange\fR" 4 +.IX Item "-Wfrontend-loop-interchange" +Enable warning for loop interchanges performed by the +\&\fB\-ffrontend\-loop\-interchange\fR option. +.IP "\fB\-Wimplicit\-interface\fR" 4 +.IX Item "-Wimplicit-interface" +Warn if a procedure is called without an explicit interface. +Note this only checks that an explicit interface is present. It does not +check that the declared interfaces are consistent across program units. +.IP "\fB\-Wimplicit\-procedure\fR" 4 +.IX Item "-Wimplicit-procedure" +Warn if a procedure is called that has neither an explicit interface +nor has been declared as \f(CW\*(C`EXTERNAL\*(C'\fR. +.IP "\fB\-Winteger\-division\fR" 4 +.IX Item "-Winteger-division" +Warn if a constant integer division truncates it result. +As an example, 3/5 evaluates to 0. +.IP "\fB\-Wintrinsics\-std\fR" 4 +.IX Item "-Wintrinsics-std" +Warn if \fBgfortran\fR finds a procedure named like an intrinsic not +available in the currently selected standard (with \fB\-std\fR) and treats +it as \f(CW\*(C`EXTERNAL\*(C'\fR procedure because of this. \fB\-fall\-intrinsics\fR can +be used to never trigger this behavior and always link to the intrinsic +regardless of the selected standard. +.IP "\fB\-Wreal\-q\-constant\fR" 4 +.IX Item "-Wreal-q-constant" +Produce a warning if a real-literal-constant contains a \f(CW\*(C`q\*(C'\fR +exponent-letter. +.IP "\fB\-Wsurprising\fR" 4 +.IX Item "-Wsurprising" +Produce a warning when \*(L"suspicious\*(R" code constructs are encountered. +While technically legal these usually indicate that an error has been made. +.Sp +This currently produces a warning under the following circumstances: +.RS 4 +.IP "*" 4 +An \s-1INTEGER SELECT\s0 construct has a \s-1CASE\s0 that can never be matched as its +lower value is greater than its upper value. +.IP "*" 4 +A \s-1LOGICAL SELECT\s0 construct has three \s-1CASE\s0 statements. +.IP "*" 4 +A \s-1TRANSFER\s0 specifies a source that is shorter than the destination. +.IP "*" 4 +The type of a function result is declared more than once with the same type. If +\&\fB\-pedantic\fR or standard-conforming mode is enabled, this is an error. +.IP "*" 4 +A \f(CW\*(C`CHARACTER\*(C'\fR variable is declared with negative length. +.RE +.RS 4 +.RE +.IP "\fB\-Wtabs\fR" 4 +.IX Item "-Wtabs" +By default, tabs are accepted as whitespace, but tabs are not members +of the Fortran Character Set. For continuation lines, a tab followed +by a digit between 1 and 9 is supported. \fB\-Wtabs\fR will cause a +warning to be issued if a tab is encountered. Note, \fB\-Wtabs\fR is +active for \fB\-pedantic\fR, \fB\-std=f95\fR, \fB\-std=f2003\fR, +\&\fB\-std=f2008\fR, \fB\-std=f2018\fR and +\&\fB\-Wall\fR. +.IP "\fB\-Wundefined\-do\-loop\fR" 4 +.IX Item "-Wundefined-do-loop" +Warn if a \s-1DO\s0 loop with step either 1 or \-1 yields an underflow or an overflow +during iteration of an induction variable of the loop. +This option is implied by \fB\-Wall\fR. +.IP "\fB\-Wunderflow\fR" 4 +.IX Item "-Wunderflow" +Produce a warning when numerical constant expressions are +encountered, which yield an \s-1UNDERFLOW\s0 during compilation. Enabled by default. +.IP "\fB\-Wintrinsic\-shadow\fR" 4 +.IX Item "-Wintrinsic-shadow" +Warn if a user-defined procedure or module procedure has the same name as an +intrinsic; in this case, an explicit interface or \f(CW\*(C`EXTERNAL\*(C'\fR or +\&\f(CW\*(C`INTRINSIC\*(C'\fR declaration might be needed to get calls later resolved to +the desired intrinsic/procedure. This option is implied by \fB\-Wall\fR. +.IP "\fB\-Wuse\-without\-only\fR" 4 +.IX Item "-Wuse-without-only" +Warn if a \f(CW\*(C`USE\*(C'\fR statement has no \f(CW\*(C`ONLY\*(C'\fR qualifier and +thus implicitly imports all public entities of the used module. +.IP "\fB\-Wunused\-dummy\-argument\fR" 4 +.IX Item "-Wunused-dummy-argument" +Warn about unused dummy arguments. This option is implied by \fB\-Wall\fR. +.IP "\fB\-Wunused\-parameter\fR" 4 +.IX Item "-Wunused-parameter" +Contrary to \fBgcc\fR's meaning of \fB\-Wunused\-parameter\fR, +\&\fBgfortran\fR's implementation of this option does not warn +about unused dummy arguments (see \fB\-Wunused\-dummy\-argument\fR), +but about unused \f(CW\*(C`PARAMETER\*(C'\fR values. \fB\-Wunused\-parameter\fR +is implied by \fB\-Wextra\fR if also \fB\-Wunused\fR or +\&\fB\-Wall\fR is used. +.IP "\fB\-Walign\-commons\fR" 4 +.IX Item "-Walign-commons" +By default, \fBgfortran\fR warns about any occasion of variables being +padded for proper alignment inside a \f(CW\*(C`COMMON\*(C'\fR block. This warning can be turned +off via \fB\-Wno\-align\-commons\fR. See also \fB\-falign\-commons\fR. +.IP "\fB\-Wfunction\-elimination\fR" 4 +.IX Item "-Wfunction-elimination" +Warn if any calls to impure functions are eliminated by the optimizations +enabled by the \fB\-ffrontend\-optimize\fR option. +This option is implied by \fB\-Wextra\fR. +.IP "\fB\-Wrealloc\-lhs\fR" 4 +.IX Item "-Wrealloc-lhs" +Warn when the compiler might insert code to for allocation or reallocation of +an allocatable array variable of intrinsic type in intrinsic assignments. In +hot loops, the Fortran 2003 reallocation feature may reduce the performance. +If the array is already allocated with the correct shape, consider using a +whole-array array-spec (e.g. \f(CW\*(C`(:,:,:)\*(C'\fR) for the variable on the left-hand +side to prevent the reallocation check. Note that in some cases the warning +is shown, even if the compiler will optimize reallocation checks away. For +instance, when the right-hand side contains the same variable multiplied by +a scalar. See also \fB\-frealloc\-lhs\fR. +.IP "\fB\-Wrealloc\-lhs\-all\fR" 4 +.IX Item "-Wrealloc-lhs-all" +Warn when the compiler inserts code to for allocation or reallocation of an +allocatable variable; this includes scalars and derived types. +.IP "\fB\-Wcompare\-reals\fR" 4 +.IX Item "-Wcompare-reals" +Warn when comparing real or complex types for equality or inequality. +This option is implied by \fB\-Wextra\fR. +.IP "\fB\-Wtarget\-lifetime\fR" 4 +.IX Item "-Wtarget-lifetime" +Warn if the pointer in a pointer assignment might be longer than the its +target. This option is implied by \fB\-Wall\fR. +.IP "\fB\-Wzerotrip\fR" 4 +.IX Item "-Wzerotrip" +Warn if a \f(CW\*(C`DO\*(C'\fR loop is known to execute zero times at compile +time. This option is implied by \fB\-Wall\fR. +.IP "\fB\-Wdo\-subscript\fR" 4 +.IX Item "-Wdo-subscript" +Warn if an array subscript inside a \s-1DO\s0 loop could lead to an +out-of-bounds access even if the compiler cannot prove that the +statement is actually executed, in cases like +.Sp +.Vb 6 +\& real a(3) +\& do i=1,4 +\& if (condition(i)) then +\& a(i) = 1.2 +\& end if +\& end do +.Ve +.Sp +This option is implied by \fB\-Wextra\fR. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Turns all warnings into errors. +.PP +Some of these have no effect when compiling programs written in Fortran. +.SS "Options for debugging your program or \s-1GNU\s0 Fortran" +.IX Subsection "Options for debugging your program or GNU Fortran" +\&\s-1GNU\s0 Fortran has various special options that are used for debugging +either your program or the \s-1GNU\s0 Fortran compiler. +.IP "\fB\-fdump\-fortran\-original\fR" 4 +.IX Item "-fdump-fortran-original" +Output the internal parse tree after translating the source program +into internal representation. This option is mostly useful for +debugging the \s-1GNU\s0 Fortran compiler itself. The output generated by +this option might change between releases. This option may also +generate internal compiler errors for features which have only +recently been added. +.IP "\fB\-fdump\-fortran\-optimized\fR" 4 +.IX Item "-fdump-fortran-optimized" +Output the parse tree after front-end optimization. Mostly useful for +debugging the \s-1GNU\s0 Fortran compiler itself. The output generated by +this option might change between releases. This option may also +generate internal compiler errors for features which have only +recently been added. +.IP "\fB\-fdump\-parse\-tree\fR" 4 +.IX Item "-fdump-parse-tree" +Output the internal parse tree after translating the source program +into internal representation. Mostly useful for debugging the \s-1GNU\s0 +Fortran compiler itself. The output generated by this option might +change between releases. This option may also generate internal +compiler errors for features which have only recently been added. This +option is deprecated; use \f(CW\*(C`\-fdump\-fortran\-original\*(C'\fR instead. +.IP "\fB\-fdump\-fortran\-global\fR" 4 +.IX Item "-fdump-fortran-global" +Output a list of the global identifiers after translating into +middle-end representation. Mostly useful for debugging the \s-1GNU\s0 Fortran +compiler itself. The output generated by this option might change +between releases. This option may also generate internal compiler +errors for features which have only recently been added. +.IP "\fB\-ffpe\-trap=\fR\fIlist\fR" 4 +.IX Item "-ffpe-trap=list" +Specify a list of floating point exception traps to enable. On most +systems, if a floating point exception occurs and the trap for that +exception is enabled, a \s-1SIGFPE\s0 signal will be sent and the program +being aborted, producing a core file useful for debugging. \fIlist\fR +is a (possibly empty) comma-separated list of the following +exceptions: \fBinvalid\fR (invalid floating point operation, such as +\&\f(CW\*(C`SQRT(\-1.0)\*(C'\fR), \fBzero\fR (division by zero), \fBoverflow\fR +(overflow in a floating point operation), \fBunderflow\fR (underflow +in a floating point operation), \fBinexact\fR (loss of precision +during operation), and \fBdenormal\fR (operation performed on a +denormal value). The first five exceptions correspond to the five +\&\s-1IEEE 754\s0 exceptions, whereas the last one (\fBdenormal\fR) is not +part of the \s-1IEEE 754\s0 standard but is available on some common +architectures such as x86. +.Sp +The first three exceptions (\fBinvalid\fR, \fBzero\fR, and +\&\fBoverflow\fR) often indicate serious errors, and unless the program +has provisions for dealing with these exceptions, enabling traps for +these three exceptions is probably a good idea. +.Sp +If the option is used more than once in the command line, the lists will +be joined: '\f(CW\*(C`ffpe\-trap=\*(C'\fR\fIlist1\fR \f(CW\*(C`ffpe\-trap=\*(C'\fR\fIlist2\fR' +is equivalent to \f(CW\*(C`ffpe\-trap=\*(C'\fR\fIlist1\fR,\fIlist2\fR. +.Sp +Note that once enabled an exception cannot be disabled (no negative form). +.Sp +Many, if not most, floating point operations incur loss of precision +due to rounding, and hence the \f(CW\*(C`ffpe\-trap=inexact\*(C'\fR is likely to +be uninteresting in practice. +.Sp +By default no exception traps are enabled. +.IP "\fB\-ffpe\-summary=\fR\fIlist\fR" 4 +.IX Item "-ffpe-summary=list" +Specify a list of floating-point exceptions, whose flag status is printed +to \f(CW\*(C`ERROR_UNIT\*(C'\fR when invoking \f(CW\*(C`STOP\*(C'\fR and \f(CW\*(C`ERROR STOP\*(C'\fR. +\&\fIlist\fR can be either \fBnone\fR, \fBall\fR or a comma-separated list +of the following exceptions: \fBinvalid\fR, \fBzero\fR, \fBoverflow\fR, +\&\fBunderflow\fR, \fBinexact\fR and \fBdenormal\fR. (See +\&\fB\-ffpe\-trap\fR for a description of the exceptions.) +.Sp +If the option is used more than once in the command line, only the +last one will be used. +.Sp +By default, a summary for all exceptions but \fBinexact\fR is shown. +.IP "\fB\-fno\-backtrace\fR" 4 +.IX Item "-fno-backtrace" +When a serious runtime error is encountered or a deadly signal is +emitted (segmentation fault, illegal instruction, bus error, +floating-point exception, and the other \s-1POSIX\s0 signals that have the +action \fBcore\fR), the Fortran runtime library tries to output a +backtrace of the error. \f(CW\*(C`\-fno\-backtrace\*(C'\fR disables the backtrace +generation. This option only has influence for compilation of the +Fortran main program. +.SS "Options for directory search" +.IX Subsection "Options for directory search" +These options affect how \s-1GNU\s0 Fortran searches +for files specified by the \f(CW\*(C`INCLUDE\*(C'\fR directive and where it searches +for previously compiled modules. +.PP +It also affects the search paths used by \fBcpp\fR when used to preprocess +Fortran source. +.IP "\fB\-I\fR\fIdir\fR" 4 +.IX Item "-Idir" +These affect interpretation of the \f(CW\*(C`INCLUDE\*(C'\fR directive +(as well as of the \f(CW\*(C`#include\*(C'\fR directive of the \fBcpp\fR +preprocessor). +.Sp +Also note that the general behavior of \fB\-I\fR and +\&\f(CW\*(C`INCLUDE\*(C'\fR is pretty much the same as of \fB\-I\fR with +\&\f(CW\*(C`#include\*(C'\fR in the \fBcpp\fR preprocessor, with regard to +looking for \fIheader.gcc\fR files and other such things. +.Sp +This path is also used to search for \fI.mod\fR files when previously +compiled modules are required by a \f(CW\*(C`USE\*(C'\fR statement. +.IP "\fB\-J\fR\fIdir\fR" 4 +.IX Item "-Jdir" +This option specifies where to put \fI.mod\fR files for compiled modules. +It is also added to the list of directories to searched by an \f(CW\*(C`USE\*(C'\fR +statement. +.Sp +The default is the current directory. +.IP "\fB\-fintrinsic\-modules\-path\fR \fIdir\fR" 4 +.IX Item "-fintrinsic-modules-path dir" +This option specifies the location of pre-compiled intrinsic modules, if +they are not in the default location expected by the compiler. +.SS "Influencing the linking step" +.IX Subsection "Influencing the linking step" +These options come into play when the compiler links object files into an +executable output file. They are meaningless if the compiler is not doing +a link step. +.IP "\fB\-static\-libgfortran\fR" 4 +.IX Item "-static-libgfortran" +On systems that provide \fIlibgfortran\fR as a shared and a static +library, this option forces the use of the static version. If no +shared version of \fIlibgfortran\fR was built when the compiler was +configured, this option has no effect. +.SS "Influencing runtime behavior" +.IX Subsection "Influencing runtime behavior" +These options affect the runtime behavior of programs compiled with \s-1GNU\s0 Fortran. +.IP "\fB\-fconvert=\fR\fIconversion\fR" 4 +.IX Item "-fconvert=conversion" +Specify the representation of data for unformatted files. Valid +values for conversion are: \fBnative\fR, the default; \fBswap\fR, +swap between big\- and little-endian; \fBbig-endian\fR, use big-endian +representation for unformatted files; \fBlittle-endian\fR, use little-endian +representation for unformatted files. +.Sp +\&\fIThis option has an effect only when used in the main program. +The \f(CI\*(C`CONVERT\*(C'\fI specifier and the \s-1GFORTRAN_CONVERT_UNIT\s0 environment +variable override the default specified by \f(BI\-fconvert\fI.\fR +.IP "\fB\-frecord\-marker=\fR\fIlength\fR" 4 +.IX Item "-frecord-marker=length" +Specify the length of record markers for unformatted files. +Valid values for \fIlength\fR are 4 and 8. Default is 4. +\&\fIThis is different from previous versions of\fR \fBgfortran\fR, +which specified a default record marker length of 8 on most +systems. If you want to read or write files compatible +with earlier versions of \fBgfortran\fR, use \fB\-frecord\-marker=8\fR. +.IP "\fB\-fmax\-subrecord\-length=\fR\fIlength\fR" 4 +.IX Item "-fmax-subrecord-length=length" +Specify the maximum length for a subrecord. The maximum permitted +value for length is 2147483639, which is also the default. Only +really useful for use by the gfortran testsuite. +.IP "\fB\-fsign\-zero\fR" 4 +.IX Item "-fsign-zero" +When enabled, floating point numbers of value zero with the sign bit set +are written as negative number in formatted output and treated as +negative in the \f(CW\*(C`SIGN\*(C'\fR intrinsic. \fB\-fno\-sign\-zero\fR does not +print the negative sign of zero values (or values rounded to zero for I/O) +and regards zero as positive number in the \f(CW\*(C`SIGN\*(C'\fR intrinsic for +compatibility with Fortran 77. The default is \fB\-fsign\-zero\fR. +.SS "Options for code generation conventions" +.IX Subsection "Options for code generation conventions" +These machine-independent options control the interface conventions +used in code generation. +.PP +Most of them have both positive and negative forms; the negative form +of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table below, only +one of the forms is listed\-\-\-the one which is not the default. You +can figure out the other form by either removing \fBno\-\fR or adding +it. +.IP "\fB\-fno\-automatic\fR" 4 +.IX Item "-fno-automatic" +Treat each program unit (except those marked as \s-1RECURSIVE\s0) as if the +\&\f(CW\*(C`SAVE\*(C'\fR statement were specified for every local variable and array +referenced in it. Does not affect common blocks. (Some Fortran compilers +provide this option under the name \fB\-static\fR or \fB\-save\fR.) +The default, which is \fB\-fautomatic\fR, uses the stack for local +variables smaller than the value given by \fB\-fmax\-stack\-var\-size\fR. +Use the option \fB\-frecursive\fR to use no static memory. +.Sp +Local variables or arrays having an explicit \f(CW\*(C`SAVE\*(C'\fR attribute are +silently ignored unless the \fB\-pedantic\fR option is added. +.IP "\fB\-ff2c\fR" 4 +.IX Item "-ff2c" +Generate code designed to be compatible with code generated +by \fBg77\fR and \fBf2c\fR. +.Sp +The calling conventions used by \fBg77\fR (originally implemented +in \fBf2c\fR) require functions that return type +default \f(CW\*(C`REAL\*(C'\fR to actually return the C type \f(CW\*(C`double\*(C'\fR, and +functions that return type \f(CW\*(C`COMPLEX\*(C'\fR to return the values via an +extra argument in the calling sequence that points to where to +store the return value. Under the default \s-1GNU\s0 calling conventions, such +functions simply return their results as they would in \s-1GNU\s0 +C\-\-\-default \f(CW\*(C`REAL\*(C'\fR functions return the C type \f(CW\*(C`float\*(C'\fR, and +\&\f(CW\*(C`COMPLEX\*(C'\fR functions return the \s-1GNU C\s0 type \f(CW\*(C`complex\*(C'\fR. +Additionally, this option implies the \fB\-fsecond\-underscore\fR +option, unless \fB\-fno\-second\-underscore\fR is explicitly requested. +.Sp +This does not affect the generation of code that interfaces with +the \fBlibgfortran\fR library. +.Sp +\&\fICaution:\fR It is not a good idea to mix Fortran code compiled with +\&\fB\-ff2c\fR with code compiled with the default \fB\-fno\-f2c\fR +calling conventions as, calling \f(CW\*(C`COMPLEX\*(C'\fR or default \f(CW\*(C`REAL\*(C'\fR +functions between program parts which were compiled with different +calling conventions will break at execution time. +.Sp +\&\fICaution:\fR This will break code which passes intrinsic functions +of type default \f(CW\*(C`REAL\*(C'\fR or \f(CW\*(C`COMPLEX\*(C'\fR as actual arguments, as +the library implementations use the \fB\-fno\-f2c\fR calling conventions. +.IP "\fB\-fno\-underscoring\fR" 4 +.IX Item "-fno-underscoring" +Do not transform names of entities specified in the Fortran +source file by appending underscores to them. +.Sp +With \fB\-funderscoring\fR in effect, \s-1GNU\s0 Fortran appends one +underscore to external names with no underscores. This is done to ensure +compatibility with code produced by many \s-1UNIX\s0 Fortran compilers. +.Sp +\&\fICaution\fR: The default behavior of \s-1GNU\s0 Fortran is +incompatible with \fBf2c\fR and \fBg77\fR, please use the +\&\fB\-ff2c\fR option if you want object files compiled with +\&\s-1GNU\s0 Fortran to be compatible with object code created with these +tools. +.Sp +Use of \fB\-fno\-underscoring\fR is not recommended unless you are +experimenting with issues such as integration of \s-1GNU\s0 Fortran into +existing system environments (vis\-a\*`\-vis existing libraries, tools, +and so on). +.Sp +For example, with \fB\-funderscoring\fR, and assuming that \f(CW\*(C`j()\*(C'\fR and +\&\f(CW\*(C`max_count()\*(C'\fR are external functions while \f(CW\*(C`my_var\*(C'\fR and +\&\f(CW\*(C`lvar\*(C'\fR are local variables, a statement like +.Sp +.Vb 1 +\& I = J() + MAX_COUNT (MY_VAR, LVAR) +.Ve +.Sp +is implemented as something akin to: +.Sp +.Vb 1 +\& i = j_() + max_count_\|_(&my_var_\|_, &lvar); +.Ve +.Sp +With \fB\-fno\-underscoring\fR, the same statement is implemented as: +.Sp +.Vb 1 +\& i = j() + max_count(&my_var, &lvar); +.Ve +.Sp +Use of \fB\-fno\-underscoring\fR allows direct specification of +user-defined names while debugging and when interfacing \s-1GNU\s0 Fortran +code with other languages. +.Sp +Note that just because the names match does \fInot\fR mean that the +interface implemented by \s-1GNU\s0 Fortran for an external name matches the +interface implemented by some other language for that same name. +That is, getting code produced by \s-1GNU\s0 Fortran to link to code produced +by some other compiler using this or any other method can be only a +small part of the overall solution\-\-\-getting the code generated by +both compilers to agree on issues other than naming can require +significant effort, and, unlike naming disagreements, linkers normally +cannot detect disagreements in these other areas. +.Sp +Also, note that with \fB\-fno\-underscoring\fR, the lack of appended +underscores introduces the very real possibility that a user-defined +external name will conflict with a name in a system library, which +could make finding unresolved-reference bugs quite difficult in some +cases\-\-\-they might occur at program run time, and show up only as +buggy behavior at run time. +.Sp +In future versions of \s-1GNU\s0 Fortran we hope to improve naming and linking +issues so that debugging always involves using the names as they appear +in the source, even if the names as seen by the linker are mangled to +prevent accidental linking between procedures with incompatible +interfaces. +.IP "\fB\-fsecond\-underscore\fR" 4 +.IX Item "-fsecond-underscore" +By default, \s-1GNU\s0 Fortran appends an underscore to external +names. If this option is used \s-1GNU\s0 Fortran appends two +underscores to names with underscores and one underscore to external names +with no underscores. \s-1GNU\s0 Fortran also appends two underscores to +internal names with underscores to avoid naming collisions with external +names. +.Sp +This option has no effect if \fB\-fno\-underscoring\fR is +in effect. It is implied by the \fB\-ff2c\fR option. +.Sp +Otherwise, with this option, an external name such as \f(CW\*(C`MAX_COUNT\*(C'\fR +is implemented as a reference to the link-time external symbol +\&\f(CW\*(C`max_count_\|_\*(C'\fR, instead of \f(CW\*(C`max_count_\*(C'\fR. This is required +for compatibility with \fBg77\fR and \fBf2c\fR, and is implied +by use of the \fB\-ff2c\fR option. +.IP "\fB\-fcoarray=\fR\fI\fR" 4 +.IX Item "-fcoarray=" +.RS 4 +.PD 0 +.IP "\fBnone\fR" 4 +.IX Item "none" +.PD +Disable coarray support; using coarray declarations and image-control +statements will produce a compile-time error. (Default) +.IP "\fBsingle\fR" 4 +.IX Item "single" +Single-image mode, i.e. \f(CW\*(C`num_images()\*(C'\fR is always one. +.IP "\fBlib\fR" 4 +.IX Item "lib" +Library-based coarray parallelization; a suitable \s-1GNU\s0 Fortran coarray +library needs to be linked. +.RE +.RS 4 +.RE +.IP "\fB\-fcheck=\fR\fI\fR" 4 +.IX Item "-fcheck=" +Enable the generation of run-time checks; the argument shall be +a comma-delimited list of the following keywords. Prefixing a check with +\&\fBno\-\fR disables it if it was activated by a previous specification. +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all run-time test of \fB\-fcheck\fR. +.IP "\fBarray-temps\fR" 4 +.IX Item "array-temps" +Warns at run time when for passing an actual argument a temporary array +had to be generated. The information generated by this warning is +sometimes useful in optimization, in order to avoid such temporaries. +.Sp +Note: The warning is only printed once per location. +.IP "\fBbounds\fR" 4 +.IX Item "bounds" +Enable generation of run-time checks for array subscripts +and against the declared minimum and maximum values. It also +checks array indices for assumed and deferred +shape arrays against the actual allocated bounds and ensures that all string +lengths are equal for character array constructors without an explicit +typespec. +.Sp +Some checks require that \fB\-fcheck=bounds\fR is set for +the compilation of the main program. +.Sp +Note: In the future this may also include other forms of checking, e.g., +checking substring references. +.IP "\fBdo\fR" 4 +.IX Item "do" +Enable generation of run-time checks for invalid modification of loop +iteration variables. +.IP "\fBmem\fR" 4 +.IX Item "mem" +Enable generation of run-time checks for memory allocation. +Note: This option does not affect explicit allocations using the +\&\f(CW\*(C`ALLOCATE\*(C'\fR statement, which will be always checked. +.IP "\fBpointer\fR" 4 +.IX Item "pointer" +Enable generation of run-time checks for pointers and allocatables. +.IP "\fBrecursion\fR" 4 +.IX Item "recursion" +Enable generation of run-time checks for recursively called subroutines and +functions which are not marked as recursive. See also \fB\-frecursive\fR. +Note: This check does not work for OpenMP programs and is disabled if used +together with \fB\-frecursive\fR and \fB\-fopenmp\fR. +.RE +.RS 4 +.Sp +Example: Assuming you have a file \fIfoo.f90\fR, the command +.Sp +.Vb 1 +\& gfortran \-fcheck=all,no\-array\-temps foo.f90 +.Ve +.Sp +will compile the file with all checks enabled as specified above except +warnings for generated array temporaries. +.RE +.IP "\fB\-fbounds\-check\fR" 4 +.IX Item "-fbounds-check" +Deprecated alias for \fB\-fcheck=bounds\fR. +.IP "\fB\-ftail\-call\-workaround\fR" 4 +.IX Item "-ftail-call-workaround" +.PD 0 +.IP "\fB\-ftail\-call\-workaround=\fR\fIn\fR" 4 +.IX Item "-ftail-call-workaround=n" +.PD +Some C interfaces to Fortran codes violate the gfortran \s-1ABI\s0 by +omitting the hidden character length arguments as described in + This can lead to crashes +because pushing arguments for tail calls can overflow the stack. +.Sp +To provide a workaround for existing binary packages, this option +disables tail call optimization for gfortran procedures with character +arguments. With \fB\-ftail\-call\-workaround=2\fR tail call optimization +is disabled in all gfortran procedures with character arguments, +with \fB\-ftail\-call\-workaround=1\fR or equivalent +\&\fB\-ftail\-call\-workaround\fR only in gfortran procedures with character +arguments that call implicitly prototyped procedures. +.Sp +Using this option can lead to problems including crashes due to +insufficient stack space. +.Sp +It is \fIvery strongly\fR recommended to fix the code in question. +The \fB\-fc\-prototypes\-external\fR option can be used to generate +prototypes which conform to gfortran's \s-1ABI,\s0 for inclusion in the +source code. +.Sp +Support for this option will likely be withdrawn in a future release +of gfortran. +.Sp +The negative form, \fB\-fno\-tail\-call\-workaround\fR or equivalent +\&\fB\-ftail\-call\-workaround=0\fR, can be used to disable this option. +.Sp +Default is currently \fB\-ftail\-call\-workaround\fR, this will change +in future releases. +.IP "\fB\-fcheck\-array\-temporaries\fR" 4 +.IX Item "-fcheck-array-temporaries" +Deprecated alias for \fB\-fcheck=array\-temps\fR. +.IP "\fB\-fmax\-array\-constructor=\fR\fIn\fR" 4 +.IX Item "-fmax-array-constructor=n" +This option can be used to increase the upper limit permitted in +array constructors. The code below requires this option to expand +the array at compile time. +.Sp +.Vb 7 +\& program test +\& implicit none +\& integer j +\& integer, parameter :: n = 100000 +\& integer, parameter :: i(n) = (/ (2*j, j = 1, n) /) +\& print \*(Aq(10(I0,1X))\*(Aq, i +\& end program test +.Ve +.Sp +\&\fICaution: This option can lead to long compile times and excessively +large object files.\fR +.Sp +The default value for \fIn\fR is 65535. +.IP "\fB\-fmax\-stack\-var\-size=\fR\fIn\fR" 4 +.IX Item "-fmax-stack-var-size=n" +This option specifies the size in bytes of the largest array that will be put +on the stack; if the size is exceeded static memory is used (except in +procedures marked as \s-1RECURSIVE\s0). Use the option \fB\-frecursive\fR to +allow for recursive procedures which do not have a \s-1RECURSIVE\s0 attribute or +for parallel programs. Use \fB\-fno\-automatic\fR to never use the stack. +.Sp +This option currently only affects local arrays declared with constant +bounds, and may not apply to all character variables. +Future versions of \s-1GNU\s0 Fortran may improve this behavior. +.Sp +The default value for \fIn\fR is 32768. +.IP "\fB\-fstack\-arrays\fR" 4 +.IX Item "-fstack-arrays" +Adding this option will make the Fortran compiler put all arrays of +unknown size and array temporaries onto stack memory. If your program uses very +large local arrays it is possible that you will have to extend your runtime +limits for stack memory on some operating systems. This flag is enabled +by default at optimization level \fB\-Ofast\fR unless +\&\fB\-fmax\-stack\-var\-size\fR is specified. +.IP "\fB\-fpack\-derived\fR" 4 +.IX Item "-fpack-derived" +This option tells \s-1GNU\s0 Fortran to pack derived type members as closely as +possible. Code compiled with this option is likely to be incompatible +with code compiled without this option, and may execute slower. +.IP "\fB\-frepack\-arrays\fR" 4 +.IX Item "-frepack-arrays" +In some circumstances \s-1GNU\s0 Fortran may pass assumed shape array +sections via a descriptor describing a noncontiguous area of memory. +This option adds code to the function prologue to repack the data into +a contiguous block at runtime. +.Sp +This should result in faster accesses to the array. However it can introduce +significant overhead to the function call, especially when the passed data +is noncontiguous. +.IP "\fB\-fshort\-enums\fR" 4 +.IX Item "-fshort-enums" +This option is provided for interoperability with C code that was +compiled with the \fB\-fshort\-enums\fR option. It will make +\&\s-1GNU\s0 Fortran choose the smallest \f(CW\*(C`INTEGER\*(C'\fR kind a given +enumerator set will fit in, and give all its enumerators this kind. +.IP "\fB\-fexternal\-blas\fR" 4 +.IX Item "-fexternal-blas" +This option will make \fBgfortran\fR generate calls to \s-1BLAS\s0 functions +for some matrix operations like \f(CW\*(C`MATMUL\*(C'\fR, instead of using our own +algorithms, if the size of the matrices involved is larger than a given +limit (see \fB\-fblas\-matmul\-limit\fR). This may be profitable if an +optimized vendor \s-1BLAS\s0 library is available. The \s-1BLAS\s0 library will have +to be specified at link time. +.IP "\fB\-fblas\-matmul\-limit=\fR\fIn\fR" 4 +.IX Item "-fblas-matmul-limit=n" +Only significant when \fB\-fexternal\-blas\fR is in effect. +Matrix multiplication of matrices with size larger than (or equal to) \fIn\fR +will be performed by calls to \s-1BLAS\s0 functions, while others will be +handled by \fBgfortran\fR internal algorithms. If the matrices +involved are not square, the size comparison is performed using the +geometric mean of the dimensions of the argument and result matrices. +.Sp +The default value for \fIn\fR is 30. +.IP "\fB\-finline\-matmul\-limit=\fR\fIn\fR" 4 +.IX Item "-finline-matmul-limit=n" +When front-end optimiztion is active, some calls to the \f(CW\*(C`MATMUL\*(C'\fR +intrinsic function will be inlined. This may result in code size +increase if the size of the matrix cannot be determined at compile +time, as code for both cases is generated. Setting +\&\f(CW\*(C`\-finline\-matmul\-limit=0\*(C'\fR will disable inlining in all cases. +Setting this option with a value of \fIn\fR will produce inline code +for matrices with size up to \fIn\fR. If the matrices involved are not +square, the size comparison is performed using the geometric mean of +the dimensions of the argument and result matrices. +.Sp +The default value for \fIn\fR is 30. The \f(CW\*(C`\-fblas\-matmul\-limit\*(C'\fR +can be used to change this value. +.IP "\fB\-frecursive\fR" 4 +.IX Item "-frecursive" +Allow indirect recursion by forcing all local arrays to be allocated +on the stack. This flag cannot be used together with +\&\fB\-fmax\-stack\-var\-size=\fR or \fB\-fno\-automatic\fR. +.IP "\fB\-finit\-local\-zero\fR" 4 +.IX Item "-finit-local-zero" +.PD 0 +.IP "\fB\-finit\-derived\fR" 4 +.IX Item "-finit-derived" +.IP "\fB\-finit\-integer=\fR\fIn\fR" 4 +.IX Item "-finit-integer=n" +.IP "\fB\-finit\-real=\fR\fI\fR" 4 +.IX Item "-finit-real=" +.IP "\fB\-finit\-logical=\fR\fI\fR" 4 +.IX Item "-finit-logical=" +.IP "\fB\-finit\-character=\fR\fIn\fR" 4 +.IX Item "-finit-character=n" +.PD +The \fB\-finit\-local\-zero\fR option instructs the compiler to +initialize local \f(CW\*(C`INTEGER\*(C'\fR, \f(CW\*(C`REAL\*(C'\fR, and \f(CW\*(C`COMPLEX\*(C'\fR +variables to zero, \f(CW\*(C`LOGICAL\*(C'\fR variables to false, and +\&\f(CW\*(C`CHARACTER\*(C'\fR variables to a string of null bytes. Finer-grained +initialization options are provided by the +\&\fB\-finit\-integer=\fR\fIn\fR, +\&\fB\-finit\-real=\fR\fI\fR (which also initializes +the real and imaginary parts of local \f(CW\*(C`COMPLEX\*(C'\fR variables), +\&\fB\-finit\-logical=\fR\fI\fR, and +\&\fB\-finit\-character=\fR\fIn\fR (where \fIn\fR is an \s-1ASCII\s0 character +value) options. +.Sp +With \fB\-finit\-derived\fR, components of derived type variables will be +initialized according to these flags. Components whose type is not covered by +an explicit \fB\-finit\-*\fR flag will be treated as described above with +\&\fB\-finit\-local\-zero\fR. +.Sp +These options do not initialize +.RS 4 +.IP "*" 4 +objects with the \s-1POINTER\s0 attribute +.IP "*" 4 +allocatable arrays +.IP "*" 4 +variables that appear in an \f(CW\*(C`EQUIVALENCE\*(C'\fR statement. +.RE +.RS 4 +.Sp +(These limitations may be removed in future releases). +.Sp +Note that the \fB\-finit\-real=nan\fR option initializes \f(CW\*(C`REAL\*(C'\fR +and \f(CW\*(C`COMPLEX\*(C'\fR variables with a quiet NaN. For a signalling NaN +use \fB\-finit\-real=snan\fR; note, however, that compile-time +optimizations may convert them into quiet NaN and that trapping +needs to be enabled (e.g. via \fB\-ffpe\-trap\fR). +.Sp +The \fB\-finit\-integer\fR option will parse the value into an +integer of type \f(CW\*(C`INTEGER(kind=C_LONG)\*(C'\fR on the host. Said value +is then assigned to the integer variables in the Fortran code, which +might result in wraparound if the value is too large for the kind. +.Sp +Finally, note that enabling any of the \fB\-finit\-*\fR options will +silence warnings that would have been emitted by \fB\-Wuninitialized\fR +for the affected local variables. +.RE +.IP "\fB\-falign\-commons\fR" 4 +.IX Item "-falign-commons" +By default, \fBgfortran\fR enforces proper alignment of all variables in a +\&\f(CW\*(C`COMMON\*(C'\fR block by padding them as needed. On certain platforms this is mandatory, +on others it increases performance. If a \f(CW\*(C`COMMON\*(C'\fR block is not declared with +consistent data types everywhere, this padding can cause trouble, and +\&\fB\-fno\-align\-commons\fR can be used to disable automatic alignment. The +same form of this option should be used for all files that share a \f(CW\*(C`COMMON\*(C'\fR block. +To avoid potential alignment issues in \f(CW\*(C`COMMON\*(C'\fR blocks, it is recommended to order +objects from largest to smallest. +.IP "\fB\-fno\-protect\-parens\fR" 4 +.IX Item "-fno-protect-parens" +By default the parentheses in expression are honored for all optimization +levels such that the compiler does not do any re-association. Using +\&\fB\-fno\-protect\-parens\fR allows the compiler to reorder \f(CW\*(C`REAL\*(C'\fR and +\&\f(CW\*(C`COMPLEX\*(C'\fR expressions to produce faster code. Note that for the re-association +optimization \fB\-fno\-signed\-zeros\fR and \fB\-fno\-trapping\-math\fR +need to be in effect. The parentheses protection is enabled by default, unless +\&\fB\-Ofast\fR is given. +.IP "\fB\-frealloc\-lhs\fR" 4 +.IX Item "-frealloc-lhs" +An allocatable left-hand side of an intrinsic assignment is automatically +(re)allocated if it is either unallocated or has a different shape. The +option is enabled by default except when \fB\-std=f95\fR is given. See +also \fB\-Wrealloc\-lhs\fR. +.IP "\fB\-faggressive\-function\-elimination\fR" 4 +.IX Item "-faggressive-function-elimination" +Functions with identical argument lists are eliminated within +statements, regardless of whether these functions are marked +\&\f(CW\*(C`PURE\*(C'\fR or not. For example, in +.Sp +.Vb 1 +\& a = f(b,c) + f(b,c) +.Ve +.Sp +there will only be a single call to \f(CW\*(C`f\*(C'\fR. This option only works +if \fB\-ffrontend\-optimize\fR is in effect. +.IP "\fB\-ffrontend\-optimize\fR" 4 +.IX Item "-ffrontend-optimize" +This option performs front-end optimization, based on manipulating +parts the Fortran parse tree. Enabled by default by any \fB\-O\fR option +except \fB\-O0\fR and \fB\-Og\fR. Optimizations enabled by this option +include: +.RS 4 +.ie n .IP "*" 4 +.el .IP "*" 4 +.IX Item "*" +.PD 0 +.IP "*" 4 +.IX Item "*" +.ie n .IP "*" 4 +.el .IP "*" 4 +.IX Item "*" +.ie n .IP "*" 4 +.el .IP "*" 4 +.IX Item "*" +.ie n .IP "*" 4 +.el .IP "*" 4 +.IX Item "*" +.RE +.RS 4 +.PD +.Sp +It can be deselected by specifying \fB\-fno\-frontend\-optimize\fR. +.RE +.IP "\fB\-ffrontend\-loop\-interchange\fR" 4 +.IX Item "-ffrontend-loop-interchange" +Attempt to interchange loops in the Fortran front end where +profitable. Enabled by default by any \fB\-O\fR option. +At the moment, this option only affects \f(CW\*(C`FORALL\*(C'\fR and +\&\f(CW\*(C`DO CONCURRENT\*(C'\fR statements with several forall triplets. +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +The \fBgfortran\fR compiler currently does not make use of any environment +variables to control its operation above and beyond those +that affect the operation of \fBgcc\fR. +.SH "BUGS" +.IX Header "BUGS" +For instructions on reporting bugs, see +<\fBhttps://github.com/conda\-forge/ctng\-compilers\-feedstock/issues/new/choose\fR>. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fBgpl\fR\|(7), \fBgfdl\fR\|(7), \fBfsf\-funding\fR\|(7), +\&\fBcpp\fR\|(1), \fBgcov\fR\|(1), \fBgcc\fR\|(1), \fBas\fR\|(1), \fBld\fR\|(1), \fBgdb\fR\|(1), \fBdbx\fR\|(1) +and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIgfortran\fR, \fIas\fR, +\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. +.SH "AUTHOR" +.IX Header "AUTHOR" +See the Info entry for \fBgfortran\fR for contributors to \s-1GCC\s0 and +\&\s-1GNU\s0 Fortran. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2004\-2019 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"Funding Free Software\*(R", the Front-Cover +Texts being (a) (see below), and with the Back-Cover Texts being (b) +(see below). A copy of the license is included in the \fBgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/man/man3/io_uring_clone_buffers.3 b/man/man3/io_uring_clone_buffers.3 new file mode 100644 index 0000000000000000000000000000000000000000..3f0a881bf5b0365fabf6fdef68f73c15c94b2b11 --- /dev/null +++ b/man/man3/io_uring_clone_buffers.3 @@ -0,0 +1,168 @@ +.\" Copyright (C) 2024 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_clone_buffers 3 "September 12, 2024" "liburing-2.9" "liburing Manual" +.SH NAME +io_uring_clone_buffers \- Clones registered buffers between rings +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_clone_buffers(struct io_uring *" dst "," +.BI " struct io_uring * " src ");" +.PP +.BI "int __io_uring_clone_buffers(struct io_uring *" dst "," +.BI " struct io_uring * " src "," +.BI " unsigned int " flags ");" +.PP +.BI "int io_uring_clone_buffers_offset(struct io_uring *" dst "," +.BI " struct io_uring * " src "," +.BI " unsigned int " dst_off "," +.BI " unsigned int " src_off "," +.BI " unsigned int " nr "," +.BI " unsigned int " flags ");" +.PP +.BI "int __io_uring_clone_buffers_offset(struct io_uring *" dst "," +.BI " struct io_uring * " src "," +.BI " unsigned int " dst_off "," +.BI " unsigned int " src_off "," +.BI " unsigned int " nr "," +.BI " unsigned int " flags ");" +.PP +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_clone_buffers (3) +function clones registered buffers from the ring indicated by +.IR src +to the ring indicated by +.IR dst . +Upon successful completion of this operation, +.IR src +and +.IR dst +will have the same set of registered buffers. This operation is identical to +performing a +.BR io_uring_register_buffers (3) +operation on the +.IR dst +ring, if the +.IR src +ring previously had that same buffer registration operating done. + +The +.IR dst +ring must not have any buffers currently registered. If buffers are currently +registered on the destination ring, they must be unregistered with +.BR io_uring_unregister_buffers (3) +first. + +For +.BR __io_uring_clone_buffers (3) , +the only difference is that it takes a +.IR flags +argument. By default, if the destination ring has a registered file descriptor +through +.BR io_uring_register_ring_fd (3) +AND the calling application is not the thread that registered that ring, then +the kernel doesn't know how to look up the destination. This is problematic +as +.BR io_uring_clone_buffers (3) +defaults to using the registered index if the destination is setup as such. +Use +.BR __io_uring_clone_buffers (3) +which doesn't set +.B IORING_REGISTER_SRC_REGISTERED +by default. This requires the application to still have the original ring file +descriptor open. See below for the flag definition. + +Available since kernel 6.12. + +The +.BR io_uring_clone_buffers_offset (3) +function also clones buffers from the +.IR src +ring to the +.IR dst +ring, however it supports cloning only a subset of the buffers, where +.BR io_uring_clone_buffers (3) +always clones all of them. +.IR dst_off +indicates at what offset cloning should start in the destination, +.IR src_off +indicates at what offset cloning should start in the source, and +.IR nr +indicates how many buffers to clone at the given offset. If both +.IR dst_off , +.IR src_off , +and +.IR nr +are given as +.B 0 , +then +.BR io_uring_clone_buffers_offset (3) +performs the same action as +.BR io_uring_clone_buffers (3) . + +While +.BR io_uring_clone_buffers_offset (3) +sets +.B IORING_REGISTER_SRC_REGISTERED +by default, the +.BR __io_uring_clone_buffers_offset (3) +does not. See the explanation for +.BR __io_uring_clone_buffers (3) +for details. + +.IR flags +may be set to the following value: +.TP +.B IORING_REGISTER_SRC_REGISTERED +If the source ring is registered AND the calling thread is the one that +originally registered its ring fd, then this flag may be set to lookup the +registered index rather than use the normal file descriptor. If the normal +file descriptor wasn't closed after registering it, there's no need to set +this flag. +.TP +.B IORING_REGISTER_DST_REPLACE +If set, cloning may happen for a destination ring that already has a buffer +table assigned. In that case, existing nodes that overlap with the specified +range will be released and replaced.IORING_REGISTER_DST_REPLACE +If set, cloning may happen for a destination ring that already has a buffer +table assigned. In that case, existing nodes that overlap with the specified +range will be released and replaced. +.PP + +Available since kernel 6.13. + +.SH NOTES +The source and target ring must shared address spaces, and hence internal +kernel accounting. +.SH RETURN VALUE +On success +.BR io_uring_clone_buffers (3) +and +.BR io_uring_clone_buffers_offset (3) +return 0. +On failure, they returns +.BR -errno , +specifically +.TP +.B -EBUSY +The destination ring already has buffers registered, and +.B IORING_REGISTER_DST_REPLACE +wasn't set. +.TP +.B -ENOMEM +The kernel ran out of memory. +.TP +.B -ENXIO +The source ring doesn't have any buffers registered. +.SH SEE ALSO +.BR io_uring_register (2), +.BR io_uring_unregister_buffers (3), +.BR io_uring_register_buffers (3), +.BR io_uring_prep_read_fixed (3), +.BR io_uring_prep_write_fixed (3) diff --git a/man/man3/io_uring_clone_buffers_offset.3 b/man/man3/io_uring_clone_buffers_offset.3 new file mode 100644 index 0000000000000000000000000000000000000000..3f0a881bf5b0365fabf6fdef68f73c15c94b2b11 --- /dev/null +++ b/man/man3/io_uring_clone_buffers_offset.3 @@ -0,0 +1,168 @@ +.\" Copyright (C) 2024 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_clone_buffers 3 "September 12, 2024" "liburing-2.9" "liburing Manual" +.SH NAME +io_uring_clone_buffers \- Clones registered buffers between rings +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_clone_buffers(struct io_uring *" dst "," +.BI " struct io_uring * " src ");" +.PP +.BI "int __io_uring_clone_buffers(struct io_uring *" dst "," +.BI " struct io_uring * " src "," +.BI " unsigned int " flags ");" +.PP +.BI "int io_uring_clone_buffers_offset(struct io_uring *" dst "," +.BI " struct io_uring * " src "," +.BI " unsigned int " dst_off "," +.BI " unsigned int " src_off "," +.BI " unsigned int " nr "," +.BI " unsigned int " flags ");" +.PP +.BI "int __io_uring_clone_buffers_offset(struct io_uring *" dst "," +.BI " struct io_uring * " src "," +.BI " unsigned int " dst_off "," +.BI " unsigned int " src_off "," +.BI " unsigned int " nr "," +.BI " unsigned int " flags ");" +.PP +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_clone_buffers (3) +function clones registered buffers from the ring indicated by +.IR src +to the ring indicated by +.IR dst . +Upon successful completion of this operation, +.IR src +and +.IR dst +will have the same set of registered buffers. This operation is identical to +performing a +.BR io_uring_register_buffers (3) +operation on the +.IR dst +ring, if the +.IR src +ring previously had that same buffer registration operating done. + +The +.IR dst +ring must not have any buffers currently registered. If buffers are currently +registered on the destination ring, they must be unregistered with +.BR io_uring_unregister_buffers (3) +first. + +For +.BR __io_uring_clone_buffers (3) , +the only difference is that it takes a +.IR flags +argument. By default, if the destination ring has a registered file descriptor +through +.BR io_uring_register_ring_fd (3) +AND the calling application is not the thread that registered that ring, then +the kernel doesn't know how to look up the destination. This is problematic +as +.BR io_uring_clone_buffers (3) +defaults to using the registered index if the destination is setup as such. +Use +.BR __io_uring_clone_buffers (3) +which doesn't set +.B IORING_REGISTER_SRC_REGISTERED +by default. This requires the application to still have the original ring file +descriptor open. See below for the flag definition. + +Available since kernel 6.12. + +The +.BR io_uring_clone_buffers_offset (3) +function also clones buffers from the +.IR src +ring to the +.IR dst +ring, however it supports cloning only a subset of the buffers, where +.BR io_uring_clone_buffers (3) +always clones all of them. +.IR dst_off +indicates at what offset cloning should start in the destination, +.IR src_off +indicates at what offset cloning should start in the source, and +.IR nr +indicates how many buffers to clone at the given offset. If both +.IR dst_off , +.IR src_off , +and +.IR nr +are given as +.B 0 , +then +.BR io_uring_clone_buffers_offset (3) +performs the same action as +.BR io_uring_clone_buffers (3) . + +While +.BR io_uring_clone_buffers_offset (3) +sets +.B IORING_REGISTER_SRC_REGISTERED +by default, the +.BR __io_uring_clone_buffers_offset (3) +does not. See the explanation for +.BR __io_uring_clone_buffers (3) +for details. + +.IR flags +may be set to the following value: +.TP +.B IORING_REGISTER_SRC_REGISTERED +If the source ring is registered AND the calling thread is the one that +originally registered its ring fd, then this flag may be set to lookup the +registered index rather than use the normal file descriptor. If the normal +file descriptor wasn't closed after registering it, there's no need to set +this flag. +.TP +.B IORING_REGISTER_DST_REPLACE +If set, cloning may happen for a destination ring that already has a buffer +table assigned. In that case, existing nodes that overlap with the specified +range will be released and replaced.IORING_REGISTER_DST_REPLACE +If set, cloning may happen for a destination ring that already has a buffer +table assigned. In that case, existing nodes that overlap with the specified +range will be released and replaced. +.PP + +Available since kernel 6.13. + +.SH NOTES +The source and target ring must shared address spaces, and hence internal +kernel accounting. +.SH RETURN VALUE +On success +.BR io_uring_clone_buffers (3) +and +.BR io_uring_clone_buffers_offset (3) +return 0. +On failure, they returns +.BR -errno , +specifically +.TP +.B -EBUSY +The destination ring already has buffers registered, and +.B IORING_REGISTER_DST_REPLACE +wasn't set. +.TP +.B -ENOMEM +The kernel ran out of memory. +.TP +.B -ENXIO +The source ring doesn't have any buffers registered. +.SH SEE ALSO +.BR io_uring_register (2), +.BR io_uring_unregister_buffers (3), +.BR io_uring_register_buffers (3), +.BR io_uring_prep_read_fixed (3), +.BR io_uring_prep_write_fixed (3) diff --git a/man/man3/io_uring_cq_has_overflow.3 b/man/man3/io_uring_cq_has_overflow.3 new file mode 100644 index 0000000000000000000000000000000000000000..8ca0ba86571ea8c59c36e368661d556b40501228 --- /dev/null +++ b/man/man3/io_uring_cq_has_overflow.3 @@ -0,0 +1,31 @@ +.\" Copyright (C) 2022 Dylan Yudaken +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_cq_has_overflow 3 "September 5, 2022" "liburing-2.3" "liburing Manual" +.SH NAME +io_uring_cq_has_overflow \- returns if there are overflow entries waiting to move to the CQ ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "bool io_uring_cq_has_overflow(const struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_cq_has_overflow (3) +function informs the application if CQ entries have overflowed and are waiting to be flushed to +the CQ ring. For example using +.BR io_uring_get_events (3) +.SH NOTES +Using this function is only valid if the ring has +.B IORING_FEAT_NODROP +set, as it's checking for a flag set by kernels supporting that feature. For +really old kernels that don't support this feature, if CQE overflow is +experienced the CQEs are lost. If that happens, the CQ ring overflow offset +will get incremented. +.SH RETURN VALUE +True if there are CQ entries waiting to be flushed to the CQ ring. +.SH SEE ALSO +.BR io_uring_get_events (3) diff --git a/man/man3/io_uring_cqe_get_data.3 b/man/man3/io_uring_cqe_get_data.3 new file mode 100644 index 0000000000000000000000000000000000000000..a4d2988a49d92aa89f3b650c77c4a00ca0df0d20 --- /dev/null +++ b/man/man3/io_uring_cqe_get_data.3 @@ -0,0 +1,53 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_cqe_get_data 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_cqe_get_data \- get user data for completion event +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void *io_uring_cqe_get_data(struct io_uring_cqe *" cqe ");" +.BI " +.BI "__u64 io_uring_cqe_get_data64(struct io_uring_cqe *" cqe ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_cqe_get_data (3) +function returns the user_data with the completion queue entry +.IR cqe +as a data pointer. + +The +.BR io_uring_cqe_get_data64 (3) +function returns the user_data with the completion queue entry +.IR cqe +as a 64-bit data value. + +After the caller has received a completion queue entry (CQE) with +.BR io_uring_wait_cqe (3), +the application can call +.BR io_uring_cqe_get_data (3) +or +.BR io_uring_cqe_get_data64 (3) +function to retrieve the +.I user_data +value. This requires that +.I user_data +has been set earlier with the function +.BR io_uring_sqe_set_data (3) +or +.BR io_uring_sqe_set_data64 (3). + +.SH RETURN VALUE +If the +.I user_data +value has been set before submitting the request, it will be returned. +Otherwise, the return value is undefined. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_sqe_set_data (3), +.BR io_uring_sqe_submit (3) diff --git a/man/man3/io_uring_cqe_get_data64.3 b/man/man3/io_uring_cqe_get_data64.3 new file mode 100644 index 0000000000000000000000000000000000000000..a4d2988a49d92aa89f3b650c77c4a00ca0df0d20 --- /dev/null +++ b/man/man3/io_uring_cqe_get_data64.3 @@ -0,0 +1,53 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_cqe_get_data 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_cqe_get_data \- get user data for completion event +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void *io_uring_cqe_get_data(struct io_uring_cqe *" cqe ");" +.BI " +.BI "__u64 io_uring_cqe_get_data64(struct io_uring_cqe *" cqe ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_cqe_get_data (3) +function returns the user_data with the completion queue entry +.IR cqe +as a data pointer. + +The +.BR io_uring_cqe_get_data64 (3) +function returns the user_data with the completion queue entry +.IR cqe +as a 64-bit data value. + +After the caller has received a completion queue entry (CQE) with +.BR io_uring_wait_cqe (3), +the application can call +.BR io_uring_cqe_get_data (3) +or +.BR io_uring_cqe_get_data64 (3) +function to retrieve the +.I user_data +value. This requires that +.I user_data +has been set earlier with the function +.BR io_uring_sqe_set_data (3) +or +.BR io_uring_sqe_set_data64 (3). + +.SH RETURN VALUE +If the +.I user_data +value has been set before submitting the request, it will be returned. +Otherwise, the return value is undefined. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_sqe_set_data (3), +.BR io_uring_sqe_submit (3) diff --git a/man/man3/io_uring_cqe_seen.3 b/man/man3/io_uring_cqe_seen.3 new file mode 100644 index 0000000000000000000000000000000000000000..5c9cd4e5ff40fb2e408d8ef4fabc5542e235551b --- /dev/null +++ b/man/man3/io_uring_cqe_seen.3 @@ -0,0 +1,41 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_cqe_seen 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_cqe_seen \- mark io_uring completion event as consumed +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_cqe_seen(struct io_uring *" ring "," +.BI " struct io_uring_cqe *" cqe ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_cqe_seen (3) +function marks the IO completion +.I cqe +belonging to the +.I ring +param as consumed. + +After the caller has submitted a request with +.BR io_uring_submit (3), +the application can retrieve the completion with +.BR io_uring_wait_cqe (3), +.BR io_uring_peek_cqe (3), +or any of the other CQE retrieval helpers, and mark it as consumed with +.BR io_uring_cqe_seen (3). + +Completions must be marked as completed so their slot can get reused. +.SH RETURN VALUE +None +.SH SEE ALSO +.BR io_uring_submit (3), +.BR io_uring_peek_cqe (3), +.BR io_uring_wait_cqe (3), +.BR io_uring_wait_cqes (3), +.BR io_uring_wait_cqe_timeout (3) diff --git a/man/man3/io_uring_free_buf_ring.3 b/man/man3/io_uring_free_buf_ring.3 new file mode 100644 index 0000000000000000000000000000000000000000..649cabb3d16c523f6a2874f79a47b6de4ac4ede5 --- /dev/null +++ b/man/man3/io_uring_free_buf_ring.3 @@ -0,0 +1,53 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_free_buf_ring 3 "Mar 07, 2023" "liburing-2.4" "liburing Manual" +.SH NAME +io_uring_free_buf_ring \- register and free a buffer ring for provided buffers +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_free_buf_ring(struct io_uring *" ring ", +.BI " struct io_uring_buf_ring *" br ", +.BI " unsigned int " nentries ", +.BI " int " bgid ");" +.BI " +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_free_buf_ring (3) +function unregisters a previously registered shared buffer ring. The ring must +have heen previously returned from +.BR io_uring_setup_buf_ring (3) . + +The +.I ring +argument must pointer to the ring for which the provided buffer ring is being +registered, +.I br +must point to a buffer ring previously returned by +.BR io_uring_setup_buf_ring (3) , +.I nentries +is the number of entries requested in the buffer ring, and +.I bgid +is the buffer group ID that +.I br +was setup with. + +Under the covers, this function uses +.BR io_uring_unregister_buf_ring (3) +to unregister the ring, and handles the freeing of the ring rather than +letting the application open code it. + +Available since 5.19. + +.SH RETURN VALUE +On success +.BR io_uring_free_buf_ring (3) +returns zero. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_setup_buf_ring (3) diff --git a/man/man3/io_uring_get_events.3 b/man/man3/io_uring_get_events.3 new file mode 100644 index 0000000000000000000000000000000000000000..f2415423953c3c55781e4be8fabe02a0ba4abb6b --- /dev/null +++ b/man/man3/io_uring_get_events.3 @@ -0,0 +1,33 @@ +.\" Copyright (C) 2022 Dylan Yudaken +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_get_events 3 "September 5, 2022" "liburing-2.3" "liburing Manual" +.SH NAME +io_uring_get_events \- Flush outstanding requests to CQE ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_get_events(struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_get_events (3) +function runs outstanding work and flushes completion events to the CQE ring. + +There can be events needing to be flushed if the ring was full and had overflowed. +Alternatively if the ring was setup with the +.BR IORING_SETUP_DEFER_TASKRUN +flag then this will process outstanding tasks, possibly resulting in more CQEs. + +.SH RETURN VALUE +On success +.BR io_uring_get_events (3) +returns 0. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit_and_get_events (3), +.BR io_uring_cq_has_overflow (3) diff --git a/man/man3/io_uring_opcode_supported.3 b/man/man3/io_uring_opcode_supported.3 new file mode 100644 index 0000000000000000000000000000000000000000..b981ed7d7dc6ca98c8ad80e715973e1dc2723174 --- /dev/null +++ b/man/man3/io_uring_opcode_supported.3 @@ -0,0 +1,30 @@ +.\" Copyright (C) 2022 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_opcode_supported 3 "January 25, 2022" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_opcode_supported \- is op code supported? +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_opcode_supported(struct io_uring_probe *" probe "," +.BI " int " opcode ");" +.fi +.SH DESCRIPTION +.PP +The function +.BR io_uring_opcode_supported (3) +allows the caller to determine if the passed in +.I opcode +belonging to the +.I probe +param is supported. An instance of the io_uring_probe instance can be +obtained by calling the function +.BR io_uring_get_probe (3). + +.SH RETURN VALUE +On success it returns 1, otherwise it returns 0. +.SH SEE ALSO +.BR io_uring_get_probe (3) diff --git a/man/man3/io_uring_prep_accept.3 b/man/man3/io_uring_prep_accept.3 new file mode 100644 index 0000000000000000000000000000000000000000..950ab7d40b83a6cc085c4380ed1d83a1d112f0c8 --- /dev/null +++ b/man/man3/io_uring_prep_accept.3 @@ -0,0 +1,203 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_accept 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_accept \- prepare an accept request +.SH SYNOPSIS +.nf +.B #include +.B #include +.PP +.BI "void io_uring_prep_accept(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_accept_direct(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags "," +.BI " unsigned int " file_index ");" +.PP +.BI "void io_uring_prep_multishot_accept(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_multishot_accept_direct(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_accept (3) +function and its three variants prepare an accept request similar to +.BR accept4 (2). +The submission queue entry +.I sqe +is setup to use the file descriptor +.I sockfd +to start accepting a connection request described by the socket address at +.I addr +and of structure length +.I addrlen +and using modifier flags in +.IR flags . + +The three variants allow combining the direct file table and multishot features. + +Direct descriptors are io_uring private file descriptors. They +avoid some of the overhead associated with thread shared file tables and +can be used in any io_uring request that takes a file descriptor. +The two direct variants here create such direct descriptors. +Subsequent to their creation, they can be used by setting +.B IOSQE_FIXED_FILE +in the SQE +.I flags +member, and setting the SQE +.I fd +field to the direct descriptor value rather than the regular file +descriptor. Direct descriptors are managed like registered files. + +To use an accept direct variant, the application must first have registered +a file table of a desired size using +.BR io_uring_register_files (3) +or +.BR io_uring_register_files_sparse (3). +Once registered, +.BR io_uring_prep_accept_direct (3) +allows an entry in that table to be specifically selected through the +.I file_index +argument. +If the specified entry already contains a file, the file will first be removed +from the table and closed, consistent with the behavior of updating an +existing file with +.BR io_uring_register_files_update (3). +.I file_index +can also be set to +.B IORING_FILE_INDEX_ALLOC +for this variant and +an unused table index will be dynamically chosen and returned. +Likewise, +.B io_uring_prep_multishot_accept_direct +will have an unused table index dynamically chosen and returned for each connection accepted. +If both forms of direct selection will be employed, specific and dynamic, see +.BR io_uring_register_file_alloc_range (3) +for setting up the table so dynamically chosen entries are made against +a different range than that targeted by specific requests. + +Note that old kernels don't check the SQE +.I file_index +field meaning +applications cannot rely on a +.B -EINVAL +CQE +.I res +being returned when the kernel is too old because older kernels +may not recognize they are being asked to use a direct table slot. + +When a direct descriptor accept request asks for a table slot to be +dynamically chosen but there are no free entries, +.B -ENFILE +is returned as the CQE +.IR res . + +The multishot variants allow an application to issue +a single accept request, which will repeatedly trigger a CQE when a connection +request comes in. Like other multishot type requests, the application should +look at the CQE +.I flags +and see if +.B IORING_CQE_F_MORE +is set on completion as an indication of whether or not the accept request +will generate further CQEs. Note that for the multishot variants, setting +.B addr +and +.B addrlen +may not make a lot of sense, as the same value would be used for every +accepted connection. This means that the data written to +.B addr +may be overwritten by a new connection before the application has had time +to process a past connection. If the application knows that a new connection +cannot come in before a previous one has been processed, it may be used as +expected. The multishot variants are available since 5.19. + +See the man page +.BR accept4 (2) +for details of the accept function itself. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. + +.BR io_uring_prep_accept (3) +generates the installed file descriptor as its result. + +.BR io_uring_prep_accept_direct (3) +and +.I file_index +set to a specific direct descriptor +generates +.B 0 +on success. +The caller must remember which direct descriptor was picked for this request. + +.BR io_uring_prep_accept_direct (3) +and +.I file_index +set to +.B IORING_FILE_INDEX_ALLOC +generates the dynamically chosen direct descriptor. + +.BR io_uring_prep_multishot_accept (3) +generates the installed file descriptor in each result. + +.BR io_uring_prep_multishot_accept_direct (3), +generates the dynamically chosen direct descriptor in each result. + +Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it generates the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.P +Note that the direct versions of accept do not accept +.B SOCK_CLOEXEC , +and setting that flag will result in an +.B -EINVAL +error in the CQE. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_register_files (3), +.BR io_uring_register_files_sparse (3), +.BR io_uring_register_file_alloc_range (3), +.BR io_uring_register (2), +.BR accept4 (2) diff --git a/man/man3/io_uring_prep_cancel64.3 b/man/man3/io_uring_prep_cancel64.3 new file mode 100644 index 0000000000000000000000000000000000000000..75d4fb55deec8dd5e6a8882358f6873216001382 --- /dev/null +++ b/man/man3/io_uring_prep_cancel64.3 @@ -0,0 +1,136 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_cancel 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_cancel \- prepare a cancelation request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_cancel64(struct io_uring_sqe *" sqe "," +.BI " __u64 " user_data "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_cancel(struct io_uring_sqe *" sqe "," +.BI " void *" user_data "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_cancel_fd(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " unsigned int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_cancel (3) +function prepares a cancelation request. The submission queue entry +.I sqe +is prepared to cancel an existing request identified by +.IR user_data . +For the +.I flags +argument, see below. + +.BR io_uring_prep_cancel64 (3) +is identical to +.BR io_uring_prep_cancel (3) , +except it takes a 64-bit integer rather than a pointer type. + +The cancelation request will attempt to find the previously issued request +identified by +.I user_data +and cancel it. The identifier is what the previously issued request has in +their +.I user_data +field in the SQE. + +The +.BR io_uring_prep_cancel_fd (3) +function prepares a cancelation request. The submission queue entry +.I sqe +is prepared to cancel an existing request that used the file descriptor +.IR fd . +For the +.I flags +argument, see below. + +The cancelation request will attempt to find the previously issued request +that used +.I fd +as the file descriptor and cancel it. + +By default, the first request matching the criteria given will be canceled. +This can be modified with any of the following flags passed in: +.TP +.B IORING_ASYNC_CANCEL_ALL +Cancel all requests that match the given criteria, rather than just canceling +the first one found. Available since 5.19. +.TP +.B IORING_ASYNC_CANCEL_FD +Match based on the file descriptor used in the original request rather than +the user_data. This is what +.BR io_uring_prep_cancel_fd (3) +sets up. Available since 5.19. +.TP +.B IORING_ASYNC_CANCEL_FD_FIXED +Set in conjunction with +.B IORING_ASYNC_CANCEL_FD , +indicating that the file descriptor given is a direct descriptor rather than +a normal file descriptor. Available since 6.0. +.TP +.B IORING_ASYNC_CANCEL_ANY +Match any request in the ring, regardless of user_data or file descriptor. +Can be used to cancel any pending request in the ring. Available since 5.19. +.TP +.B IORING_ASYNC_CANCEL_USERDATA +Match request based on the user data field set in the original request. This +is the default lookup key, if no other key matching has been specified. +Available since 6.6. +.TP +.B IORING_ASYNC_CANCEL_OP +Use the original request opcode as the matching key. The opcopde requested +must be set in the sqe +.I len +field after using one of the generic cancel preparation helpers. Available +since 6.6. +.P + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. If no flags are used to cancel multiple requests, +.B 0 +is returned on success. If flags are used to match multiple requests, then +a positive value is returned indicating how many requests were found and +canceled. +.TP +.B -ENOENT +The request identified by +.I user_data +could not be located. This could be because it completed before the cancelation +request was issued, or if an invalid identifier is used. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EALREADY +The execution state of the request has progressed far enough that cancelation +is no longer possible. This should normally mean that it will complete shortly, +either successfully, or interrupted due to the cancelation. +.SH NOTES +Although the cancelation request uses async request syntax, the kernel side of +the cancelation is always run synchronously. It is guaranteed that a CQE is +always generated by the time the cancel request has been submitted. If the +cancelation is successful, the completion for the request targeted for +cancelation will have been posted by the time submission returns. For +.B -EALREADY +it may take a bit of time to do so. For this case, the caller must wait for the +canceled request to post its completion event. +.SH SEE ALSO +.BR io_uring_prep_poll_remove (3), +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3) diff --git a/man/man3/io_uring_prep_cancel_fd.3 b/man/man3/io_uring_prep_cancel_fd.3 new file mode 100644 index 0000000000000000000000000000000000000000..75d4fb55deec8dd5e6a8882358f6873216001382 --- /dev/null +++ b/man/man3/io_uring_prep_cancel_fd.3 @@ -0,0 +1,136 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_cancel 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_cancel \- prepare a cancelation request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_cancel64(struct io_uring_sqe *" sqe "," +.BI " __u64 " user_data "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_cancel(struct io_uring_sqe *" sqe "," +.BI " void *" user_data "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_cancel_fd(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " unsigned int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_cancel (3) +function prepares a cancelation request. The submission queue entry +.I sqe +is prepared to cancel an existing request identified by +.IR user_data . +For the +.I flags +argument, see below. + +.BR io_uring_prep_cancel64 (3) +is identical to +.BR io_uring_prep_cancel (3) , +except it takes a 64-bit integer rather than a pointer type. + +The cancelation request will attempt to find the previously issued request +identified by +.I user_data +and cancel it. The identifier is what the previously issued request has in +their +.I user_data +field in the SQE. + +The +.BR io_uring_prep_cancel_fd (3) +function prepares a cancelation request. The submission queue entry +.I sqe +is prepared to cancel an existing request that used the file descriptor +.IR fd . +For the +.I flags +argument, see below. + +The cancelation request will attempt to find the previously issued request +that used +.I fd +as the file descriptor and cancel it. + +By default, the first request matching the criteria given will be canceled. +This can be modified with any of the following flags passed in: +.TP +.B IORING_ASYNC_CANCEL_ALL +Cancel all requests that match the given criteria, rather than just canceling +the first one found. Available since 5.19. +.TP +.B IORING_ASYNC_CANCEL_FD +Match based on the file descriptor used in the original request rather than +the user_data. This is what +.BR io_uring_prep_cancel_fd (3) +sets up. Available since 5.19. +.TP +.B IORING_ASYNC_CANCEL_FD_FIXED +Set in conjunction with +.B IORING_ASYNC_CANCEL_FD , +indicating that the file descriptor given is a direct descriptor rather than +a normal file descriptor. Available since 6.0. +.TP +.B IORING_ASYNC_CANCEL_ANY +Match any request in the ring, regardless of user_data or file descriptor. +Can be used to cancel any pending request in the ring. Available since 5.19. +.TP +.B IORING_ASYNC_CANCEL_USERDATA +Match request based on the user data field set in the original request. This +is the default lookup key, if no other key matching has been specified. +Available since 6.6. +.TP +.B IORING_ASYNC_CANCEL_OP +Use the original request opcode as the matching key. The opcopde requested +must be set in the sqe +.I len +field after using one of the generic cancel preparation helpers. Available +since 6.6. +.P + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. If no flags are used to cancel multiple requests, +.B 0 +is returned on success. If flags are used to match multiple requests, then +a positive value is returned indicating how many requests were found and +canceled. +.TP +.B -ENOENT +The request identified by +.I user_data +could not be located. This could be because it completed before the cancelation +request was issued, or if an invalid identifier is used. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EALREADY +The execution state of the request has progressed far enough that cancelation +is no longer possible. This should normally mean that it will complete shortly, +either successfully, or interrupted due to the cancelation. +.SH NOTES +Although the cancelation request uses async request syntax, the kernel side of +the cancelation is always run synchronously. It is guaranteed that a CQE is +always generated by the time the cancel request has been submitted. If the +cancelation is successful, the completion for the request targeted for +cancelation will have been posted by the time submission returns. For +.B -EALREADY +it may take a bit of time to do so. For this case, the caller must wait for the +canceled request to post its completion event. +.SH SEE ALSO +.BR io_uring_prep_poll_remove (3), +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3) diff --git a/man/man3/io_uring_prep_close_direct.3 b/man/man3/io_uring_prep_close_direct.3 new file mode 100644 index 0000000000000000000000000000000000000000..d7eac2e89d0cca9128a90c31346ea8b1608a7ab3 --- /dev/null +++ b/man/man3/io_uring_prep_close_direct.3 @@ -0,0 +1,67 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_close 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_close \- prepare a file descriptor close request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_close(struct io_uring_sqe *" sqe "," +.BI " int " fd ");" +.PP +.BI "void io_uring_prep_close_direct(struct io_uring_sqe *" sqe "," +.BI " unsigned " file_index ");" +.PP +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_close (3) +function prepares a close request. The submission queue entry +.I sqe +is setup to close the file descriptor indicated by +.IR fd . + +For a direct descriptor close request, the offset is specified by the +.I file_index +argument instead of the +.IR fd . +This is identical to unregistering the direct descriptor, and is provided as +a convenience. Note that even though it's closing a direct descriptor, the +application must not set +.B IOSQE_FIXED_FILE +on the SQE. Otherwise the request will complete with +.B -EBADF +as the result. + +These functions prepare an async +.BR close (2) +request. See that man page for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. For closing of a direct descriptor, the only +failure cases are the kernel running completely out of memory, or if the +application has specified an invalid direct descriptor. Note that where +synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR close (2) diff --git a/man/man3/io_uring_prep_epoll_wait.3 b/man/man3/io_uring_prep_epoll_wait.3 new file mode 100644 index 0000000000000000000000000000000000000000..292f3974d7f8b4dd5869f39c59812b46da2f1575 --- /dev/null +++ b/man/man3/io_uring_prep_epoll_wait.3 @@ -0,0 +1,64 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_epoll_wait 3 "March 6, 2025" "liburing-2.10" "liburing Manual" +.SH NAME +io_uring_prep_epoll_wait \- prepare an epoll wait request +.SH SYNOPSIS +.nf +.B #include +.B #include +.PP +.BI "void io_uring_prep_epoll_wait(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " struct epoll_event *" events "," +.BI " int " maxevents "," +.BI " unsigned flags ");" +.PP +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_epoll_wait (3) +function prepares an epoll_wait request. The submission queue entry +.I sqe +is setup to wait on a maximum of +.IR maxevents +events on the epoll file descriptor indicated by +.IR fd , +and filling the received events into the memory pointed to by +.IR events . + +This function prepares an async +.BR epoll_wait (2) +request. See that man page for details. The use case is mostly for legacy +event loops, where certain file descriptors may still be using epoll for +readiness notifications. Normally this would necessitate using epoll_wait +with the io_uring fd added to that set as well, which is suboptimal as +epoll doesn't provide the same kind of fine grained batch control and +wakeup reductions that io_uring does. By using io_uring to read epoll events, +the event loop can be entirely switched to io_uring, and reap the benefits +of batch waiting and context switch reductions. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR epoll_wait (2) diff --git a/man/man3/io_uring_prep_fallocate.3 b/man/man3/io_uring_prep_fallocate.3 new file mode 100644 index 0000000000000000000000000000000000000000..426e1d52d08e145ce2d156b73e418fbbac0e9d7c --- /dev/null +++ b/man/man3/io_uring_prep_fallocate.3 @@ -0,0 +1,59 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_fallocate 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_fallocate \- prepare a fallocate request +.SH SYNOPSIS +.nf +.B #include +.B #include +.PP +.BI "void io_uring_prep_fallocate(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " int " mode "," +.BI " __u64 " offset "," +.BI " __u64 " len ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_fallocate (3) +function prepares a fallocate request. The submission queue entry +.I sqe +is setup to use the file descriptor pointed to by +.I fd +to start a fallocate operation described by +.I mode +at offset +.I offset +and +.I len +length in bytes. + +This function prepares an async +.BR fallocate (2) +request. See that man page for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR fallocate (2) diff --git a/man/man3/io_uring_prep_files_update.3 b/man/man3/io_uring_prep_files_update.3 new file mode 100644 index 0000000000000000000000000000000000000000..bedb85e0debf53e395fa44a7830811af5677cbe2 --- /dev/null +++ b/man/man3/io_uring_prep_files_update.3 @@ -0,0 +1,92 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_files_update 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_files_update \- prepare a registered file update request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_files_update(struct io_uring_sqe *" sqe "," +.BI " int *" fds "," +.BI " unsigned " nr_fds "," +.BI " int " offset ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_files_update (3) +function prepares a request for updating a number of previously registered file +descriptors. The submission queue entry +.I sqe +is setup to use the file descriptor array pointed to by +.I fds +and of +.I nr_fds +in length to update that amount of previously registered files starting at +offset +.IR offset . + +Once a previously registered file is updated with a new one, the existing +entry is updated and then removed from the table. This operation is equivalent to +first unregistering that entry and then inserting a new one, just bundled into +one combined operation. + +If +.I offset +is specified as IORING_FILE_INDEX_ALLOC, io_uring will allocate free direct +descriptors instead of having the application to pass, and store allocated +direct descriptors into +.I fds +array, +.I cqe->res +will return the number of direct descriptors allocated. + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. On success, +.I res +will contain the number of successfully updated file descriptors. On error, +the following errors can occur. +.TP +.B -ENOMEM +The kernel was unable to allocate memory for the request. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EFAULT +The kernel was unable to copy in the memory pointed to by +.IR fds . +.TP +.B -EBADF +On of the descriptors located in +.I fds +didn't refer to a valid file descriptor, or one of the file descriptors in +the array referred to an io_uring instance. +.TP +.B -EOVERFLOW +The product of +.I offset +and +.I nr_fds +exceed the valid amount or overflowed. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_register (2) diff --git a/man/man3/io_uring_prep_linkat.3 b/man/man3/io_uring_prep_linkat.3 new file mode 100644 index 0000000000000000000000000000000000000000..0949e3b42fb55ebc30effff93eb221ec3829ee37 --- /dev/null +++ b/man/man3/io_uring_prep_linkat.3 @@ -0,0 +1,91 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_linkat 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_linkat \- prepare a linkat request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_linkat(struct io_uring_sqe *" sqe "," +.BI " int " olddirfd "," +.BI " const char *" oldpath "," +.BI " int " newdirfd "," +.BI " const char *" newpath "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_link(struct io_uring_sqe *" sqe "," +.BI " const char *" oldpath "," +.BI " const char *" newpath "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_linkat (3) +function prepares a linkat request. The submission queue entry +.I sqe +is setup to use the old directory file descriptor pointed to by +.I olddirfd +and old path pointed to by +.I oldpath +with the new directory file descriptor pointed to by +.I newdirfd +and the new path pointed to by +.I newpath +and using the specified flags in +.IR flags . + +The +.BR io_uring_prep_link (3) +function prepares a link request. The submission queue entry +.I sqe +is setup to use the old path pointed to by +.I oldpath +and the new path pointed to by +.IR newpath , +both relative to the current working directory and using the specified flags in +.IR flags . + +These functions prepare an async +.BR linkat (2) +or +.BR link (2) +request. See those man pages for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR linkat (2), +.BR link (2) diff --git a/man/man3/io_uring_prep_mkdir.3 b/man/man3/io_uring_prep_mkdir.3 new file mode 100644 index 0000000000000000000000000000000000000000..a98b4e354078ffef3a94e0d737390748d211cf4b --- /dev/null +++ b/man/man3/io_uring_prep_mkdir.3 @@ -0,0 +1,83 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_mkdirat 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_mkdirat \- prepare an mkdirat request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_mkdirat(struct io_uring_sqe *" sqe "," +.BI " int " dirfd "," +.BI " const char *" path "," +.BI " mode_t " mode ");" +.PP +.BI "void io_uring_prep_mkdir(struct io_uring_sqe *" sqe "," +.BI " const char *" path "," +.BI " mode_t " mode ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_mkdirat (3) +function prepares a mkdirat request. The submission queue entry +.I sqe +is setup to use the directory file descriptor pointed to by +.I dirfd +to start a mkdirat operation on the path identified by +.I path +with the mode given in +.IR mode . + +The +.BR io_uring_prep_mkdir (3) +function prepares a mkdir request. The submission queue entry +.I sqe +is setup to use the current working directory to start a mkdir +operation on the path identified by +.I path +with the mode given in +.IR mode . + +These functions prepare an async +.BR mkdir (2) +or +.BR mkdirat (2) +request. See those man pages for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR mkdirat (2), +.BR mkdir (2) diff --git a/man/man3/io_uring_prep_mkdirat.3 b/man/man3/io_uring_prep_mkdirat.3 new file mode 100644 index 0000000000000000000000000000000000000000..a98b4e354078ffef3a94e0d737390748d211cf4b --- /dev/null +++ b/man/man3/io_uring_prep_mkdirat.3 @@ -0,0 +1,83 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_mkdirat 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_mkdirat \- prepare an mkdirat request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_mkdirat(struct io_uring_sqe *" sqe "," +.BI " int " dirfd "," +.BI " const char *" path "," +.BI " mode_t " mode ");" +.PP +.BI "void io_uring_prep_mkdir(struct io_uring_sqe *" sqe "," +.BI " const char *" path "," +.BI " mode_t " mode ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_mkdirat (3) +function prepares a mkdirat request. The submission queue entry +.I sqe +is setup to use the directory file descriptor pointed to by +.I dirfd +to start a mkdirat operation on the path identified by +.I path +with the mode given in +.IR mode . + +The +.BR io_uring_prep_mkdir (3) +function prepares a mkdir request. The submission queue entry +.I sqe +is setup to use the current working directory to start a mkdir +operation on the path identified by +.I path +with the mode given in +.IR mode . + +These functions prepare an async +.BR mkdir (2) +or +.BR mkdirat (2) +request. See those man pages for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR mkdirat (2), +.BR mkdir (2) diff --git a/man/man3/io_uring_prep_msg_ring.3 b/man/man3/io_uring_prep_msg_ring.3 new file mode 100644 index 0000000000000000000000000000000000000000..70caebe770b42a3c0061fd3041726a48867792bb --- /dev/null +++ b/man/man3/io_uring_prep_msg_ring.3 @@ -0,0 +1,92 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_msg_ring 3 "March 10, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_msg_ring \- send a message to another ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_msg_ring(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " unsigned int " len "," +.BI " __u64 " data "," +.BI " unsigned int " flags ");" +.PP +.BI "void io_uring_prep_msg_ring_cqe_flags(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " unsigned int " len "," +.BI " __u64 " data "," +.BI " unsigned int " flags "," +.BI " unsigned int " cqe_flags ");" +.fi +.SH DESCRIPTION +.PP +.BR io_uring_prep_msg_ring (3) +prepares to send a CQE to an io_uring file descriptor. The submission queue +entry +.I sqe +is setup to use the file descriptor +.IR fd , +which must identify a io_uring context, to post a CQE on that ring where the +target CQE +.B res +field will contain the content of +.I len +and the +.B user_data +of +.I data +with the request modifier flags set by +.IR flags . +Currently there are no valid flag modifiers, this field must contain +.BR 0 . + +The targeted ring may be any ring that the user has access to, even the ring +itself. This request can be used for simple message passing to another ring, +allowing 32+64 bits of data to be transferred through the +.I len +and +.I data +fields. The use case may be anything from simply waking up someone waiting +on the targeted ring, or it can be used to pass messages between the two +rings. + +.BR io_uring_prep_msg_ring_cqe_flags (3) +is similar to +.BR io_uring_prep_msg_ring (3) . +But has an addition +.I cqe_flags +parameter, which is used to set +.I flags +field on CQE side. That way, you can set the CQE flags field +.I cqe->flags +when sending a message. Be aware that io_uring could potentially set additional +bits into this field. + +.SH RETURN VALUE +None + +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. +.TP +.B -ENOMEM +The kernel was unable to allocate memory for the request. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EBADFD +The descriptor passed in +.I fd +does not refer to an io_uring file descriptor, or the ring is in a disabled +state. +.TP +.B -EOVERFLOW +The kernel was unable to fill a CQE on the target ring. This can happen if +the target CQ ring is in an overflow state and the kernel wasn't able to +allocate memory for a new CQE entry. diff --git a/man/man3/io_uring_prep_msg_ring_fd.3 b/man/man3/io_uring_prep_msg_ring_fd.3 new file mode 100644 index 0000000000000000000000000000000000000000..39cd34aa454da5fe72c9da425b746e7ee9d3f7e2 --- /dev/null +++ b/man/man3/io_uring_prep_msg_ring_fd.3 @@ -0,0 +1,83 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_msg_ring_fd 3 "Mar 16, 2023" "liburing-2.4" "liburing Manual" +.SH NAME +io_uring_prep_msg_ring_fd \- send a direct descriptor to another ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_msg_ring_fd(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " int " source_fd "," +.BI " int " target_fd "," +.BI " __u64 " data "," +.BI " unsigned int " flags ");" +.PP +.BI "void io_uring_prep_msg_ring_fd_alloc(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " int " source_fd "," +.BI " __u64 " data "," +.BI " unsigned int " flags ");" +.fi +.SH DESCRIPTION +.PP +.BR io_uring_prep_msg_ring_fd (3) +prepares an SQE to send a direct file descriptor to another ring. The submission +queue entry +.I sqe +is setup to use the file descriptor +.IR fd , +which must identify a target io_uring context, to send the locally registered +file descriptor with value +.I source_fd +to the destination ring into index +.I target_fd +and passing +.I data +as the user data in the target CQE with the request modifier flags set by +.IR flags . +Currently there are no valid flag modifiers, this field must contain +.BR 0 . + +.BR io_uring_prep_msg_ring_fd_alloc (3) +is similar to +.BR io_uring_prep_msg_ring_fd (3) , +but doesn't specify a target index for the direct descriptor. Instead, this +index is allocated in the target ring and returned in the CQE +.IR res +field. + +.SH RETURN VALUE +None + +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. +.TP +.B -ENOMEM +The kernel was unable to allocate memory for the request. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EINVAL +Target ring is identical to the source ring. +.TP +.B -EBADFD +The descriptor passed in +.I fd +does not refer to an io_uring file descriptor, or the ring is in a disabled +state. +.TP +.B -EOVERFLOW +The kernel was unable to fill a CQE on the target ring. This can happen if +the target CQ ring is in an overflow state and the kernel wasn't able to +allocate memory for a new CQE entry. +.TP +.B -ENFILE +The direct descriptor table in the target ring was full, no new descriptors +could be successfully allocated. diff --git a/man/man3/io_uring_prep_msg_ring_fd_alloc.3 b/man/man3/io_uring_prep_msg_ring_fd_alloc.3 new file mode 100644 index 0000000000000000000000000000000000000000..39cd34aa454da5fe72c9da425b746e7ee9d3f7e2 --- /dev/null +++ b/man/man3/io_uring_prep_msg_ring_fd_alloc.3 @@ -0,0 +1,83 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_msg_ring_fd 3 "Mar 16, 2023" "liburing-2.4" "liburing Manual" +.SH NAME +io_uring_prep_msg_ring_fd \- send a direct descriptor to another ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_msg_ring_fd(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " int " source_fd "," +.BI " int " target_fd "," +.BI " __u64 " data "," +.BI " unsigned int " flags ");" +.PP +.BI "void io_uring_prep_msg_ring_fd_alloc(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " int " source_fd "," +.BI " __u64 " data "," +.BI " unsigned int " flags ");" +.fi +.SH DESCRIPTION +.PP +.BR io_uring_prep_msg_ring_fd (3) +prepares an SQE to send a direct file descriptor to another ring. The submission +queue entry +.I sqe +is setup to use the file descriptor +.IR fd , +which must identify a target io_uring context, to send the locally registered +file descriptor with value +.I source_fd +to the destination ring into index +.I target_fd +and passing +.I data +as the user data in the target CQE with the request modifier flags set by +.IR flags . +Currently there are no valid flag modifiers, this field must contain +.BR 0 . + +.BR io_uring_prep_msg_ring_fd_alloc (3) +is similar to +.BR io_uring_prep_msg_ring_fd (3) , +but doesn't specify a target index for the direct descriptor. Instead, this +index is allocated in the target ring and returned in the CQE +.IR res +field. + +.SH RETURN VALUE +None + +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. +.TP +.B -ENOMEM +The kernel was unable to allocate memory for the request. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EINVAL +Target ring is identical to the source ring. +.TP +.B -EBADFD +The descriptor passed in +.I fd +does not refer to an io_uring file descriptor, or the ring is in a disabled +state. +.TP +.B -EOVERFLOW +The kernel was unable to fill a CQE on the target ring. This can happen if +the target CQ ring is in an overflow state and the kernel wasn't able to +allocate memory for a new CQE entry. +.TP +.B -ENFILE +The direct descriptor table in the target ring was full, no new descriptors +could be successfully allocated. diff --git a/man/man3/io_uring_prep_multishot_accept_direct.3 b/man/man3/io_uring_prep_multishot_accept_direct.3 new file mode 100644 index 0000000000000000000000000000000000000000..950ab7d40b83a6cc085c4380ed1d83a1d112f0c8 --- /dev/null +++ b/man/man3/io_uring_prep_multishot_accept_direct.3 @@ -0,0 +1,203 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_accept 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_accept \- prepare an accept request +.SH SYNOPSIS +.nf +.B #include +.B #include +.PP +.BI "void io_uring_prep_accept(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_accept_direct(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags "," +.BI " unsigned int " file_index ");" +.PP +.BI "void io_uring_prep_multishot_accept(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_multishot_accept_direct(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " struct sockaddr *" addr "," +.BI " socklen_t *" addrlen "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_accept (3) +function and its three variants prepare an accept request similar to +.BR accept4 (2). +The submission queue entry +.I sqe +is setup to use the file descriptor +.I sockfd +to start accepting a connection request described by the socket address at +.I addr +and of structure length +.I addrlen +and using modifier flags in +.IR flags . + +The three variants allow combining the direct file table and multishot features. + +Direct descriptors are io_uring private file descriptors. They +avoid some of the overhead associated with thread shared file tables and +can be used in any io_uring request that takes a file descriptor. +The two direct variants here create such direct descriptors. +Subsequent to their creation, they can be used by setting +.B IOSQE_FIXED_FILE +in the SQE +.I flags +member, and setting the SQE +.I fd +field to the direct descriptor value rather than the regular file +descriptor. Direct descriptors are managed like registered files. + +To use an accept direct variant, the application must first have registered +a file table of a desired size using +.BR io_uring_register_files (3) +or +.BR io_uring_register_files_sparse (3). +Once registered, +.BR io_uring_prep_accept_direct (3) +allows an entry in that table to be specifically selected through the +.I file_index +argument. +If the specified entry already contains a file, the file will first be removed +from the table and closed, consistent with the behavior of updating an +existing file with +.BR io_uring_register_files_update (3). +.I file_index +can also be set to +.B IORING_FILE_INDEX_ALLOC +for this variant and +an unused table index will be dynamically chosen and returned. +Likewise, +.B io_uring_prep_multishot_accept_direct +will have an unused table index dynamically chosen and returned for each connection accepted. +If both forms of direct selection will be employed, specific and dynamic, see +.BR io_uring_register_file_alloc_range (3) +for setting up the table so dynamically chosen entries are made against +a different range than that targeted by specific requests. + +Note that old kernels don't check the SQE +.I file_index +field meaning +applications cannot rely on a +.B -EINVAL +CQE +.I res +being returned when the kernel is too old because older kernels +may not recognize they are being asked to use a direct table slot. + +When a direct descriptor accept request asks for a table slot to be +dynamically chosen but there are no free entries, +.B -ENFILE +is returned as the CQE +.IR res . + +The multishot variants allow an application to issue +a single accept request, which will repeatedly trigger a CQE when a connection +request comes in. Like other multishot type requests, the application should +look at the CQE +.I flags +and see if +.B IORING_CQE_F_MORE +is set on completion as an indication of whether or not the accept request +will generate further CQEs. Note that for the multishot variants, setting +.B addr +and +.B addrlen +may not make a lot of sense, as the same value would be used for every +accepted connection. This means that the data written to +.B addr +may be overwritten by a new connection before the application has had time +to process a past connection. If the application knows that a new connection +cannot come in before a previous one has been processed, it may be used as +expected. The multishot variants are available since 5.19. + +See the man page +.BR accept4 (2) +for details of the accept function itself. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. + +.BR io_uring_prep_accept (3) +generates the installed file descriptor as its result. + +.BR io_uring_prep_accept_direct (3) +and +.I file_index +set to a specific direct descriptor +generates +.B 0 +on success. +The caller must remember which direct descriptor was picked for this request. + +.BR io_uring_prep_accept_direct (3) +and +.I file_index +set to +.B IORING_FILE_INDEX_ALLOC +generates the dynamically chosen direct descriptor. + +.BR io_uring_prep_multishot_accept (3) +generates the installed file descriptor in each result. + +.BR io_uring_prep_multishot_accept_direct (3), +generates the dynamically chosen direct descriptor in each result. + +Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it generates the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.P +Note that the direct versions of accept do not accept +.B SOCK_CLOEXEC , +and setting that flag will result in an +.B -EINVAL +error in the CQE. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_register_files (3), +.BR io_uring_register_files_sparse (3), +.BR io_uring_register_file_alloc_range (3), +.BR io_uring_register (2), +.BR accept4 (2) diff --git a/man/man3/io_uring_prep_poll_multishot.3 b/man/man3/io_uring_prep_poll_multishot.3 new file mode 100644 index 0000000000000000000000000000000000000000..82539b9aef68f1d5b345978f22588e2a498937b2 --- /dev/null +++ b/man/man3/io_uring_prep_poll_multishot.3 @@ -0,0 +1,72 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_poll_add 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_poll_add \- prepare a poll request +.SH SYNOPSIS +.nf +.B #include +.B #include +.PP +.BI "void io_uring_prep_poll_add(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " unsigned " poll_mask ");" +.PP +.BI "void io_uring_prep_poll_multishot(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " unsigned " poll_mask ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_poll_add (3) +function prepares a poll request. The submission queue entry +.I sqe +is setup to use the file descriptor +.I fd +that should get polled, with the events desired specified in the +.I poll_mask +argument. + +The default behavior is a single-shot poll request. When the specified event +has triggered, a completion CQE is posted and no more events will be generated +by the poll request. +.BR io_uring_prep_poll_multishot (3) +behaves identically in terms of events, but it persists across notifications +and will repeatedly post notifications for the same registration. A CQE +posted from a multishot poll request will have +.B IORING_CQE_F_MORE +set in the CQE +.I flags +member, indicating that the application should expect more completions from +this request. If the multishot poll request gets terminated or experiences +an error, this flag will not be set in the CQE. If this happens, the application +should not expect further CQEs from the original request and must reissue a +new one if it still wishes to get notifications on this file descriptor. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation, which is a bitmask of the +events notified. See the +.BR poll (2) +man page for details. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR poll (2), +.BR epoll_ctl (3) diff --git a/man/man3/io_uring_prep_poll_update.3 b/man/man3/io_uring_prep_poll_update.3 new file mode 100644 index 0000000000000000000000000000000000000000..41cf7766a86481605a196ef842f14c9d70bdfd28 --- /dev/null +++ b/man/man3/io_uring_prep_poll_update.3 @@ -0,0 +1,101 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_poll_update 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_poll_update \- update an existing poll request +.SH SYNOPSIS +.nf +.B #include +.B #include +.PP +.BI "void io_uring_prep_poll_update(struct io_uring_sqe *" sqe "," +.BI " __u64 " old_user_data "," +.BI " __u64 " new_user_data "," +.BI " unsigned " poll_mask "," +.BI " unsigned " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_poll_update (3) +function prepares a poll update request. The submission queue entry +.I sqe +is setup to update a poll request identified by +.IR old_user_data , +replacing it with the +.I new_user_data +information. The +.I poll_mask +arguments contains the new mask to use for the poll request, and +.I flags +argument contains modifier flags telling io_uring what fields to update. + +The +.I flags +modifier flags is a bitmask and may contain and OR'ed mask of: +.TP +.B IORING_POLL_UPDATE_EVENTS +If set, the poll update request will replace the existing events being waited +for with the ones specified in the +.I poll_mask +argument to the function. Note that only the lower 16 bits of events can +be updated. This includes things like +.B EPOLLIN +and +.B EPOLLOUT . +Higher order masks/settings are included as internal state, and cannot be +modified. That includes settings like +.B EPOLLONESHOT , +.B EPOLLEXCLUSIVE , +and +.B EPOLLET . +If an application wishes to modify these, it must cancel/remove the existing +poll request and arm a new one. +.TP +.B IORING_POLL_UPDATE_USER_DATA +If set, the poll update request will update the existing user_data of the +request with the value passed in as the +.I new_user_data +argument. +.TP +.B IORING_POLL_ADD_MULTI +If set, this will change the poll request from a singleshot to a multishot +request. This must be used along with +.B IORING_POLL_UPDATE_EVENTS +as the event field must be updated to enable multishot. + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. On success, +.B 0 +is returned. +.TP +.B -ENOENT +The request identified by +.I user_data +could not be located. This could be because it completed before the cancelation +request was issued, or if an invalid identifier is used. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -EALREADY +The execution state of the request has progressed far enough that cancelation +is no longer possible. This should normally mean that it will complete shortly, +either successfully, or interrupted due to the cancelation. +.TP +.B -ECANCELED +.B IORING_POLL_UPDATE_EVENTS +was set and an error occurred re-arming the poll request with the new mask. +The original poll request is terminated if this happens, and that termination +CQE will contain the reason for the error re-arming. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_prep_poll_add (3), +.BR io_uring_prep_poll_multishot (3) diff --git a/man/man3/io_uring_prep_read_fixed.3 b/man/man3/io_uring_prep_read_fixed.3 new file mode 100644 index 0000000000000000000000000000000000000000..5b7c1c6653b63585e2dfce20073f6ab68e150092 --- /dev/null +++ b/man/man3/io_uring_prep_read_fixed.3 @@ -0,0 +1,72 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_read_fixed 3 "February 13, 2022" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_prep_read_fixed \- prepare I/O read request with registered buffer +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_read_fixed(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " void *" buf "," +.BI " unsigned " nbytes "," +.BI " __u64 " offset "," +.BI " int " buf_index ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_read_fixed (3) +prepares an IO read request with a previously registered IO buffer. The +submission queue entry +.I sqe +is setup to use the file descriptor +.I fd +to start reading +.I nbytes +into the buffer +.I buf +at the specified +.IR offset , +and with the buffer matching the registered index of +.IR buf_index . + +This works just like +.BR io_uring_prep_read (3) +except it requires the use of buffers that have been registered with +.BR io_uring_register_buffers (3). +The +.I buf +and +.I nbytes +arguments must fall within a region specified by +.I buf_index +in the previously registered buffer. The buffer need not be aligned with +the start of the registered buffer. + +After the read has been prepared it can be submitted with one of the submit +functions. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_prep_read (3), +.BR io_uring_register_buffers (3) diff --git a/man/man3/io_uring_prep_recv.3 b/man/man3/io_uring_prep_recv.3 new file mode 100644 index 0000000000000000000000000000000000000000..54ef49b6c2bebbb7197f78795a79286919724131 --- /dev/null +++ b/man/man3/io_uring_prep_recv.3 @@ -0,0 +1,139 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_recv 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_recv \- prepare a recv request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_recv(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " void *" buf "," +.BI " size_t " len "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_recv_multishot(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " void *" buf "," +.BI " size_t " len "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_recv (3) +function prepares a recv request. The submission +queue entry +.I sqe +is setup to use the file descriptor +.I sockfd +to start receiving the data into the destination buffer +.I buf +of size +.I len +and with modifier flags +.IR flags . + +This function prepares an async +.BR recv (2) +request. See that man page for details on the arguments specified to this +prep helper. + +The multishot version allows the application to issue a single receive request, +which repeatedly posts a CQE when data is available. It requires length to +be 0, the +.B IOSQE_BUFFER_SELECT +flag to be set and no +.B MSG_WAITALL +flag to be set. +Therefore each CQE will take a buffer out of a provided buffer pool for receiving. +The application should check the flags of each CQE, regardless of its result. +If a posted CQE does not have the +.B IORING_CQE_F_MORE +flag set then the multishot receive will be done and the application should issue a +new request. +Multishot variants are available since kernel 6.0. + + +After calling this function, additional io_uring internal modifier flags +may be set in the SQE +.I ioprio +field. The following flags are supported: +.TP +.B IORING_RECVSEND_POLL_FIRST +If set, io_uring will assume the socket is currently empty and attempting to +receive data will be unsuccessful. For this case, io_uring will arm internal +poll and trigger a receive of the data when the socket has data to be read. +This initial receive attempt can be wasteful for the case where the socket +is expected to be empty, setting this flag will bypass the initial receive +attempt and go straight to arming poll. If poll does indicate that data is +ready to be received, the operation will proceed. + +Can be used with the CQE +.B IORING_CQE_F_SOCK_NONEMPTY +flag, which io_uring will set on CQEs after a +.BR recv (2) +or +.BR recvmsg (2) +operation. If set, the socket still had data to be read after the operation +completed. Both these flags are available since 5.19. + +.TP +.B IORING_RECVSEND_BUNDLE +If set and provided buffers are used with +.B IOSQE_BUFFER_SELECT , +the receive operation will attempt to fill multiple buffers with rather than +just pick a single buffer to fill. To receive multiple buffers in a single +receive, the buffer group ID set in the SQE must be of the ring provided type. +If set, the CQE +.I res +field indicates the total number of bytes received, and the buffer ID returned +in the CQE +.I flags +field indicates the first buffer in the receive operation. The application must +process the indicated initial buffer ID and until all +.I res +bytes have been seen to know which is the last buffer in the receive operation. +The buffers consumed will be contiguous from the initial buffer, in the order +in which they appear in the buffer ring. The CQE struct does not contain +the position of the buffer in the buffer ring, therefore in order to identify +buffers contained by the bundle, it is advised to maintain the cached head +index per buffer ring. This uint16_t index represents the position of the next +buffer to be consumed within the ring. Upon completion of a receive operation, +the cached head index should be incremented accordingly. +Receiving in bundles can improve performance when more than one chunk of +data is available to receive, +by eliminating redundant round trips through the networking stack. Receive +bundles may be used by both single shot and multishot receive operations. Note +that, internally, bundles rely on the networking stack passing back how much +data is left in the socket after the initial receive. This means that the +initial receive may contain less buffers than what is available, with the +followup receive(s) containing more buffers. Available since 6.10. +.P + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_buf_ring_init (3), +.BR io_uring_buf_ring_add (3), +.BR recv (2) diff --git a/man/man3/io_uring_prep_recvmsg.3 b/man/man3/io_uring_prep_recvmsg.3 new file mode 100644 index 0000000000000000000000000000000000000000..a54e3fd0e51a3db551065f8a226a6c37b3fa53b9 --- /dev/null +++ b/man/man3/io_uring_prep_recvmsg.3 @@ -0,0 +1,126 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_recvmsg 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_recvmsg \- prepare a recvmsg request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_recvmsg(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " struct msghdr *" msg "," +.BI " unsigned " flags ");" +.PP +.BI "void io_uring_prep_recvmsg_multishot(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " struct msghdr *" msg "," +.BI " unsigned " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_recvmsg (3) +function prepares a recvmsg request. The submission queue entry +.I sqe +is setup to use the file descriptor +.I fd +to start receiving the data indicated by +.I msg +with the +.BR recvmsg (2) +defined flags in the +.I flags +argument. + +This function prepares an async +.BR recvmsg (2) +request. See that man page for details on the arguments specified to this +prep helper. + +The multishot version allows the application to issue a single receive request, +which repeatedly posts a CQE when data is available. It requires the +.B IOSQE_BUFFER_SELECT +flag to be set and no +.B MSG_WAITALL +flag to be set. +Therefore each CQE will take a buffer out of a provided buffer pool for receiving. +The application should check the flags of each CQE, regardless of its result. +If a posted CQE does not have the +.B IORING_CQE_F_MORE +flag set then the multishot receive will be done and the application should issue a +new request. + +Unlike +.BR recvmsg (2), +multishot recvmsg will prepend a +.I struct io_uring_recvmsg_out +which describes the layout of the rest of the buffer in combination with the initial +.I struct msghdr +submitted with the request. See +.BR io_uring_recvmsg_out (3) +for more information on accessing the data. + +Multishot variants are available since kernel 6.0. + +After calling this function, additional io_uring internal modifier flags +may be set in the SQE +.I ioprio +field. The following flags are supported: +.TP +.B IORING_RECVSEND_POLL_FIRST +If set, io_uring will assume the socket is currently empty and attempting to +receive data will be unsuccessful. For this case, io_uring will arm internal +poll and trigger a receive of the data when the socket has data to be read. +This initial receive attempt can be wasteful for the case where the socket +is expected to be empty, setting this flag will bypass the initial receive +attempt and go straight to arming poll. If poll does indicate that data is +ready to be received, the operation will proceed. + +Can be used with the CQE +.B IORING_CQE_F_SOCK_NONEMPTY +flag, which io_uring will set on CQEs after a +.BR recv (2) +or +.BR recvmsg (2) +operation. If set, the socket still had data to be read after the operation +completed. Both these flags are available since 5.19. +.P + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_buf_ring_init (3), +.BR io_uring_buf_ring_add (3), +.BR recvmsg (2) diff --git a/man/man3/io_uring_prep_recvmsg_multishot.3 b/man/man3/io_uring_prep_recvmsg_multishot.3 new file mode 100644 index 0000000000000000000000000000000000000000..a54e3fd0e51a3db551065f8a226a6c37b3fa53b9 --- /dev/null +++ b/man/man3/io_uring_prep_recvmsg_multishot.3 @@ -0,0 +1,126 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_recvmsg 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_recvmsg \- prepare a recvmsg request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_recvmsg(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " struct msghdr *" msg "," +.BI " unsigned " flags ");" +.PP +.BI "void io_uring_prep_recvmsg_multishot(struct io_uring_sqe *" sqe "," +.BI " int " fd "," +.BI " struct msghdr *" msg "," +.BI " unsigned " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_recvmsg (3) +function prepares a recvmsg request. The submission queue entry +.I sqe +is setup to use the file descriptor +.I fd +to start receiving the data indicated by +.I msg +with the +.BR recvmsg (2) +defined flags in the +.I flags +argument. + +This function prepares an async +.BR recvmsg (2) +request. See that man page for details on the arguments specified to this +prep helper. + +The multishot version allows the application to issue a single receive request, +which repeatedly posts a CQE when data is available. It requires the +.B IOSQE_BUFFER_SELECT +flag to be set and no +.B MSG_WAITALL +flag to be set. +Therefore each CQE will take a buffer out of a provided buffer pool for receiving. +The application should check the flags of each CQE, regardless of its result. +If a posted CQE does not have the +.B IORING_CQE_F_MORE +flag set then the multishot receive will be done and the application should issue a +new request. + +Unlike +.BR recvmsg (2), +multishot recvmsg will prepend a +.I struct io_uring_recvmsg_out +which describes the layout of the rest of the buffer in combination with the initial +.I struct msghdr +submitted with the request. See +.BR io_uring_recvmsg_out (3) +for more information on accessing the data. + +Multishot variants are available since kernel 6.0. + +After calling this function, additional io_uring internal modifier flags +may be set in the SQE +.I ioprio +field. The following flags are supported: +.TP +.B IORING_RECVSEND_POLL_FIRST +If set, io_uring will assume the socket is currently empty and attempting to +receive data will be unsuccessful. For this case, io_uring will arm internal +poll and trigger a receive of the data when the socket has data to be read. +This initial receive attempt can be wasteful for the case where the socket +is expected to be empty, setting this flag will bypass the initial receive +attempt and go straight to arming poll. If poll does indicate that data is +ready to be received, the operation will proceed. + +Can be used with the CQE +.B IORING_CQE_F_SOCK_NONEMPTY +flag, which io_uring will set on CQEs after a +.BR recv (2) +or +.BR recvmsg (2) +operation. If set, the socket still had data to be read after the operation +completed. Both these flags are available since 5.19. +.P + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_buf_ring_init (3), +.BR io_uring_buf_ring_add (3), +.BR recvmsg (2) diff --git a/man/man3/io_uring_prep_remove_buffers.3 b/man/man3/io_uring_prep_remove_buffers.3 new file mode 100644 index 0000000000000000000000000000000000000000..cf4f22640829ac17d27c4ad52b2392b4a21810af --- /dev/null +++ b/man/man3/io_uring_prep_remove_buffers.3 @@ -0,0 +1,52 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_remove_buffers 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_remove_buffers \- prepare a remove buffers request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_remove_buffers(struct io_uring_sqe *" sqe "," +.BI " int " nr "," +.BI " int " bgid ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_remove_buffers (3) +function prepares a request for removing previously supplied buffers. The +submission queue entry +.I sqe +is setup to remove +.I nr +number of buffers from the buffer group ID indicated by +.IR bgid . + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. On success, +.I res +will contain the number of successfully removed buffers. On error, +the following errors can occur. +.TP +.B -ENOMEM +The kernel was unable to allocate memory for the request. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. +.TP +.B -ENOENT +No buffers exist at the specified +.I bgid +buffer group ID. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_register (2), +.BR io_uring_prep_provide_buffers (3) diff --git a/man/man3/io_uring_prep_send_zc.3 b/man/man3/io_uring_prep_send_zc.3 new file mode 100644 index 0000000000000000000000000000000000000000..f5ec5d298d46eee8d05524477c2000a256a901c8 --- /dev/null +++ b/man/man3/io_uring_prep_send_zc.3 @@ -0,0 +1,96 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_send_zc 3 "September 6, 2022" "liburing-2.3" "liburing Manual" +.SH NAME +io_uring_prep_send_zc \- prepare a zerocopy send request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_send_zc(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " const void *" buf "," +.BI " size_t " len "," +.BI " int " flags "," +.BI " unsigned " zc_flags ");" +.PP +.BI "void io_uring_prep_send_zc_fixed(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " const void *" buf "," +.BI " size_t " len "," +.BI " int " flags "," +.BI " unsigned " zc_flags ");" +.BI " unsigned " buf_index ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_send_zc (3) +function prepares a zerocopy send request. The submission queue entry +.I sqe +is setup to use the file descriptor +.I sockfd +to start sending the data from +.I buf +of size +.I len +bytes with send modifier flags +.I flags +and zerocopy modifier flags +.IR zc_flags . + +The +.BR io_uring_prep_send_zc_fixed (3) +works just like +.BR io_uring_prep_send_zc (3) +except it requires the use of buffers that have been registered with +.BR io_uring_register_buffers (3). +The +.I buf +and +.I len +arguments must fall within a region specified by +.I buf_index +in the previously registered buffer. The buffer need not be aligned with the +start of the registered buffer. + +Note that using +.B IOSQE_IO_LINK +with this request type requires the setting of +.B MSG_WAITALL +in the +.I flags +argument, as a short send isn't considered an error condition without +that being set. + +These functions prepare an async zerocopy +.BR send (2) +request. See that man page for details. For details on the zerocopy nature +of it, see +.BR io_uring_enter (2) . + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_prep_send (3), +.BR io_uring_enter (2), +.BR send (2) diff --git a/man/man3/io_uring_prep_sendto.3 b/man/man3/io_uring_prep_sendto.3 new file mode 100644 index 0000000000000000000000000000000000000000..e61ea432cb754f10dce9de8567c934d67ae7a248 --- /dev/null +++ b/man/man3/io_uring_prep_sendto.3 @@ -0,0 +1,146 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_send 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_send \- prepare a send request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_send(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " const void *" buf "," +.BI " size_t " len "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_sendto(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " const void *" buf "," +.BI " size_t " len "," +.BI " int " flags "," +.BI " const struct sockaddr *" addr "," +.BI " socklen_t " addrlen ");" +.PP +.BI "void io_uring_prep_send_bundle(struct io_uring_sqe *" sqe "," +.BI " int " sockfd "," +.BI " size_t " len "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_send (3) +function prepares a send request. The submission queue entry +.I sqe +is setup to use the file descriptor +.I sockfd +to start sending the data from +.I buf +of size +.I len +bytes and with modifier flags +.IR flags . + +Note that using +.B IOSQE_IO_LINK +with this request type requires the setting of +.B MSG_WAITALL +in the +.IR flags +argument, as a short send isn't a considered an error condition without +that being set. + +This function prepares an async +.BR send (2) +request. See that man page for details. + +The +.BR io_uring_prep_sendto (3) +function prepares a sendto request. The submission queue entry +.I sqe +is setup to use the file descriptor +.I sockfd +to start sending the data from +.I buf +of size +.I len +bytes and with modifier flags +.IR flags . +The destination address is specified by +.I addr +and +.I addrlen +and must be a valid address for the socket type. + +This function prepares an async +.BR sendto (2) +request. See that man page for details. + +Both of the above send variants may be used with provided buffers, where rather +than pass a buffer in directly with the request, +.B IOSQE_BUFFER_SELECT +is set in the SQE +.I flags +field, and additionally a buffer group ID is set in the SQE +.I buf_group +field. By using provided buffers with send requests, the application can +prevent any kind of reordering of the outgoing data which can otherwise +occur if the application has more than one send request inflight for a single +socket. This provides better pipelining of data, where previously the app +needed to manually serialize sends. + +The bundle version allows the application to issue a single send request, +with a buffer group ID given in the SQE +.I buf_group +field, which keeps sending from that buffer group until it runs out of buffers. +As with any other request using provided buffers, +.B IOSQE_BUFFER_SELECT +must also be set in the SQE +.I flags +before submission. Currently +.I len +must be given as +.B 0 +otherwise the request will be errored with +.B -EINVAL +as the result code. Future versions may allow setting +.I +to limit the transfer size. A single CQE is posted for the send, with the result +being how many bytes were sent, on success. When used with provided buffers, +send or send bundle will contain the starting buffer group ID in the CQE +.I flags +field. The number of bytes sent starts from there, and will be in contiguous +buffer IDs after that. Send bundle, and send with provided buffers in general, +are available since kernel 6.10, and can be further identified by checking for +the +.B IORING_FEAT_SEND_BUF_SELECT +flag returned in when using +.BR io_uring_init_queue_params (3) +to setup the ring. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_buf_ring_init (3), +.BR io_uring_buf_ring_add (3), +.BR send (2) +.BR sendto (2) diff --git a/man/man3/io_uring_prep_statx.3 b/man/man3/io_uring_prep_statx.3 new file mode 100644 index 0000000000000000000000000000000000000000..d9d983a0470f444c2222fb70d090718940026aa4 --- /dev/null +++ b/man/man3/io_uring_prep_statx.3 @@ -0,0 +1,74 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_statx 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_statx \- prepare a statx request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_statx(struct io_uring_sqe *" sqe "," +.BI " int " dirfd "," +.BI " const char *" path "," +.BI " int " flags "," +.BI " unsigned " mask "," +.BI " struct statx *" statxbuf ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_statx (3) +function prepares a statx request. The submission queue entry +.I sqe +is setup to use the directory file descriptor pointed to by +.I dirfd +to start a statx operation on the path identified by +.I path +and using the flags given in +.I flags +for the fields specified by +.I mask +and into the buffer located at +.IR statxbuf . + +This function prepares an async +.BR statx (2) +request. See that man page for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR statx (2) diff --git a/man/man3/io_uring_prep_timeout.3 b/man/man3/io_uring_prep_timeout.3 new file mode 100644 index 0000000000000000000000000000000000000000..a944d6e76e3565138614f6292c57837ca790675f --- /dev/null +++ b/man/man3/io_uring_prep_timeout.3 @@ -0,0 +1,107 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_timeout 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_timeout \- prepare a timeout request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_timeout(struct io_uring_sqe *" sqe "," +.BI " struct __kernel_timespec *" ts "," +.BI " unsigned " count "," +.BI " unsigned " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_timeout (3) +function prepares a timeout request. The submission queue entry +.I sqe +is setup to arm a timeout specified by +.I ts +and with a timeout count of +.I count +completion entries. The +.I flags +argument holds modifier flags for the request. + +This request type can be used as a timeout waking anyone sleeping +for events on the CQ ring. The +.I flags +argument may contain: +.TP +.B IORING_TIMEOUT_ABS +The value specified in +.I ts +is an absolute value rather than a relative one. +.TP +.B IORING_TIMEOUT_BOOTTIME +The boottime clock source should be used. +.TP +.B IORING_TIMEOUT_REALTIME +The realtime clock source should be used. +.TP +.B IORING_TIMEOUT_ETIME_SUCCESS +Consider an expired timeout a success in terms of the posted completion. This +means it will not sever dependent links, as a failed request normally would. The +posted CQE result code will still contain +.B -ETIME +in the +.I res +value. +.TP +.B IORING_TIMEOUT_MULTISHOT +The request will return multiple timeout completions. The completion flag +IORING_CQE_F_MORE is set if more timeouts are expected. The value specified in +.I count +is the number of repeats. A value of 0 means the timeout is indefinite and can +only be stopped by a removal request. Available since the 6.4 kernel. +.PP +If no alternate clock source is given in the above flags, then +.B CLOCK_MONOTONIC +is used. + +The timeout completion event will trigger if either the specified timeout +has occurred, or the specified number of events to wait for have been posted +to the CQ ring. + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. On success, +.B 0 +is returned. +.TP +.B -ETIME +The specified timeout occurred and triggered the completion event. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. For example, two clocksources +were given, or the specified timeout seconds or nanoseconds were < 0. +.TP +.B -EFAULT +io_uring was unable to access the data specified by +.IR ts . +.TP +.B -ECANCELED +The timeout was canceled by a removal request. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_prep_timeout_remove (3), +.BR io_uring_prep_timeout_update (3) diff --git a/man/man3/io_uring_prep_timeout_update.3 b/man/man3/io_uring_prep_timeout_update.3 new file mode 100644 index 0000000000000000000000000000000000000000..606fbc6329bcdb2cc16c967741cb75011db44927 --- /dev/null +++ b/man/man3/io_uring_prep_timeout_update.3 @@ -0,0 +1,99 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_timeout_update 3 "March 12, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_timeout_update \- prepare a request to update an existing timeout +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_prep_timeout_update(struct io_uring_sqe *" sqe "," +.BI " struct __kernel_timespec *" ts "," +.BI " __u64 " user_data "," +.BI " unsigned " flags ");" +.PP +.BI "void io_uring_prep_timeout_remove(struct io_uring_sqe *" sqe "," +.BI " __u64 " user_data "," +.BI " unsigned " flags ");" +.fi +.SH DESCRIPTION +.PP +These functions modify or cancel an existing timeout request. The submission +queue entry +.I sqe +is setup to arm a timeout update or removal specified by +.I user_data +and with modifier flags given by +.IR flags . +Additionally, the update request includes a +.I ts +structure, which contains new timeout information. + +For an update request, the +.I flags +member may contain a bitmask of the following values: +.TP +.B IORING_TIMEOUT_ABS +The value specified in +.I ts +is an absolute value rather than a relative one. +.TP +.B IORING_TIMEOUT_BOOTTIME +The boottime clock source should be used. +.TP +.B IORING_TIMEOUT_REALTIME +The realtime clock source should be used. +.TP +.B IORING_TIMEOUT_ETIME_SUCCESS +Consider an expired timeout a success in terms of the posted completion. +Normally a timeout that triggers would return in a +.B -ETIME +CQE +.I res +value. +.PP +The timeout remove command does not currently accept any flags. + +.SH RETURN VALUE +None +.SH ERRORS +These are the errors that are reported in the CQE +.I res +field. On success, +.B 0 +is returned. +.TP +.B -ENOENT +The timeout identified by +.I user_data +could not be found. It may be invalid, or triggered before the update or +removal request was processed. +.TP +.B -EALREADY +The timeout identified by +.I user_data +is already firing and cannot be canceled. +.TP +.B -EINVAL +One of the fields set in the SQE was invalid. For example, two clocksources +were given, or the specified timeout seconds or nanoseconds were < 0. +.TP +.B -EFAULT +io_uring was unable to access the data specified by +.IR ts . +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_prep_timeout (3) diff --git a/man/man3/io_uring_prep_unlink.3 b/man/man3/io_uring_prep_unlink.3 new file mode 100644 index 0000000000000000000000000000000000000000..ba2633cf0b91509ea4c6e44ce734032e0e2ff712 --- /dev/null +++ b/man/man3/io_uring_prep_unlink.3 @@ -0,0 +1,82 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_unlinkat 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_unlinkat \- prepare an unlinkat request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_unlinkat(struct io_uring_sqe *" sqe "," +.BI " int " dirfd "," +.BI " const char *" path "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_unlink(struct io_uring_sqe *" sqe "," +.BI " const char *" path "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_unlinkat (3) +function prepares an unlinkat request. The submission queue entry +.I sqe +is setup to use the directory file descriptor pointed to by +.I dirfd +to start an unlinkat operation on the path identified by +.I path +and using the flags given in +.IR flags . + +The +.BR io_uring_prep_unlink (3) +function prepares an unlink request. The submission queue entry +.I sqe +is setup to start an unlinkat operation on the path identified by +.I path +relative to the current working directory and using the flags given in +.IR flags . + +These functions prepare an async +.BR unlinkat (2) +or +.BR unlink (2) +request. See those man pages for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR unlinkat (2), +.BR unlink (2) diff --git a/man/man3/io_uring_prep_unlinkat.3 b/man/man3/io_uring_prep_unlinkat.3 new file mode 100644 index 0000000000000000000000000000000000000000..ba2633cf0b91509ea4c6e44ce734032e0e2ff712 --- /dev/null +++ b/man/man3/io_uring_prep_unlinkat.3 @@ -0,0 +1,82 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_prep_unlinkat 3 "March 13, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_prep_unlinkat \- prepare an unlinkat request +.SH SYNOPSIS +.nf +.B #include +.B #include +.B #include +.PP +.BI "void io_uring_prep_unlinkat(struct io_uring_sqe *" sqe "," +.BI " int " dirfd "," +.BI " const char *" path "," +.BI " int " flags ");" +.PP +.BI "void io_uring_prep_unlink(struct io_uring_sqe *" sqe "," +.BI " const char *" path "," +.BI " int " flags ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_prep_unlinkat (3) +function prepares an unlinkat request. The submission queue entry +.I sqe +is setup to use the directory file descriptor pointed to by +.I dirfd +to start an unlinkat operation on the path identified by +.I path +and using the flags given in +.IR flags . + +The +.BR io_uring_prep_unlink (3) +function prepares an unlink request. The submission queue entry +.I sqe +is setup to start an unlinkat operation on the path identified by +.I path +relative to the current working directory and using the flags given in +.IR flags . + +These functions prepare an async +.BR unlinkat (2) +or +.BR unlink (2) +request. See those man pages for details. + +.SH RETURN VALUE +None +.SH ERRORS +The CQE +.I res +field will contain the result of the operation. See the related man page for +details on possible values. Note that where synchronous system calls will return +.B -1 +on failure and set +.I errno +to the actual error value, io_uring never uses +.IR errno . +Instead it returns the negated +.I errno +directly in the CQE +.I res +field. +.SH NOTES +As with any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR unlinkat (2), +.BR unlink (2) diff --git a/man/man3/io_uring_recvmsg_cmsg_nexthdr.3 b/man/man3/io_uring_recvmsg_cmsg_nexthdr.3 new file mode 100644 index 0000000000000000000000000000000000000000..8d605d81352fa4fe929a589a1467c4d4fc018240 --- /dev/null +++ b/man/man3/io_uring_recvmsg_cmsg_nexthdr.3 @@ -0,0 +1,82 @@ +.\" Copyright (C), 2022 Dylan Yudaken +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_recvmsg_out 3 "July 26, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_recvmsg_out - access data from multishot recvmsg +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "struct io_uring_recvmsg_out *io_uring_recvmsg_validate(void *" buf "," +.BI " int " buf_len "," +.BI " struct msghdr *" msgh ");" +.PP +.BI "void *io_uring_recvmsg_name(struct io_uring_recvmsg_out *" o ");" +.PP +.BI "struct cmsghdr *io_uring_recvmsg_cmsg_firsthdr(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh ");" +.BI "struct cmsghdr *io_uring_recvmsg_cmsg_nexthdr(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh "," +.BI " struct cmsghdr *" cmsg ");" +.PP +.BI "void *io_uring_recvmsg_payload(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh ");" +.BI "unsigned int io_uring_recvmsg_payload_length(struct io_uring_recvmsg_out *" o "," +.BI " int " buf_len "," +.BI " struct msghdr *" msgh ");" +.PP +.fi + +.SH DESCRIPTION + +These functions are used to access data in the payload delivered by +.BR io_uring_prep_recvmsg_multishot (3). +.PP +.I msgh +should point to the +.I struct msghdr +submitted with the request. +.PP +.BR io_uring_recvmsg_validate (3) +will validate a buffer delivered by +.BR io_uring_prep_recvmsg_multishot (3) +and extract the +.I io_uring_recvmsg_out +if it is valid, returning a pointer to it or else NULL. +.PP +The structure is defined as follows: +.PP +.in +4n +.EX + +struct io_uring_recvmsg_out { + __u32 namelen; /* Name byte count as would have been populated + * by recvmsg(2) */ + __u32 controllen; /* Control byte count */ + __u32 payloadlen; /* Payload byte count as would have been returned + * by recvmsg(2) */ + __u32 flags; /* Flags result as would have been populated + * by recvmsg(2) */ +}; + +.IP * 3 +.BR io_uring_recvmsg_name (3) +returns a pointer to the name in the buffer. +.IP * +.BR io_uring_recvmsg_cmsg_firsthdr (3) +returns a pointer to the first cmsg in the buffer, or NULL. +.IP * +.BR io_uring_recvmsg_cmsg_nexthdr (3) +returns a pointer to the next cmsg in the buffer, or NULL. +.IP * +.BR io_uring_recvmsg_payload (3) +returns a pointer to the payload in the buffer. +.IP * +.BR io_uring_recvmsg_payload_length (3) +Calculates the usable payload length in bytes. + + +.SH "SEE ALSO" +.BR io_uring_prep_recvmsg_multishot (3) diff --git a/man/man3/io_uring_recvmsg_payload.3 b/man/man3/io_uring_recvmsg_payload.3 new file mode 100644 index 0000000000000000000000000000000000000000..8d605d81352fa4fe929a589a1467c4d4fc018240 --- /dev/null +++ b/man/man3/io_uring_recvmsg_payload.3 @@ -0,0 +1,82 @@ +.\" Copyright (C), 2022 Dylan Yudaken +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_recvmsg_out 3 "July 26, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_recvmsg_out - access data from multishot recvmsg +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "struct io_uring_recvmsg_out *io_uring_recvmsg_validate(void *" buf "," +.BI " int " buf_len "," +.BI " struct msghdr *" msgh ");" +.PP +.BI "void *io_uring_recvmsg_name(struct io_uring_recvmsg_out *" o ");" +.PP +.BI "struct cmsghdr *io_uring_recvmsg_cmsg_firsthdr(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh ");" +.BI "struct cmsghdr *io_uring_recvmsg_cmsg_nexthdr(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh "," +.BI " struct cmsghdr *" cmsg ");" +.PP +.BI "void *io_uring_recvmsg_payload(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh ");" +.BI "unsigned int io_uring_recvmsg_payload_length(struct io_uring_recvmsg_out *" o "," +.BI " int " buf_len "," +.BI " struct msghdr *" msgh ");" +.PP +.fi + +.SH DESCRIPTION + +These functions are used to access data in the payload delivered by +.BR io_uring_prep_recvmsg_multishot (3). +.PP +.I msgh +should point to the +.I struct msghdr +submitted with the request. +.PP +.BR io_uring_recvmsg_validate (3) +will validate a buffer delivered by +.BR io_uring_prep_recvmsg_multishot (3) +and extract the +.I io_uring_recvmsg_out +if it is valid, returning a pointer to it or else NULL. +.PP +The structure is defined as follows: +.PP +.in +4n +.EX + +struct io_uring_recvmsg_out { + __u32 namelen; /* Name byte count as would have been populated + * by recvmsg(2) */ + __u32 controllen; /* Control byte count */ + __u32 payloadlen; /* Payload byte count as would have been returned + * by recvmsg(2) */ + __u32 flags; /* Flags result as would have been populated + * by recvmsg(2) */ +}; + +.IP * 3 +.BR io_uring_recvmsg_name (3) +returns a pointer to the name in the buffer. +.IP * +.BR io_uring_recvmsg_cmsg_firsthdr (3) +returns a pointer to the first cmsg in the buffer, or NULL. +.IP * +.BR io_uring_recvmsg_cmsg_nexthdr (3) +returns a pointer to the next cmsg in the buffer, or NULL. +.IP * +.BR io_uring_recvmsg_payload (3) +returns a pointer to the payload in the buffer. +.IP * +.BR io_uring_recvmsg_payload_length (3) +Calculates the usable payload length in bytes. + + +.SH "SEE ALSO" +.BR io_uring_prep_recvmsg_multishot (3) diff --git a/man/man3/io_uring_recvmsg_validate.3 b/man/man3/io_uring_recvmsg_validate.3 new file mode 100644 index 0000000000000000000000000000000000000000..8d605d81352fa4fe929a589a1467c4d4fc018240 --- /dev/null +++ b/man/man3/io_uring_recvmsg_validate.3 @@ -0,0 +1,82 @@ +.\" Copyright (C), 2022 Dylan Yudaken +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_recvmsg_out 3 "July 26, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_recvmsg_out - access data from multishot recvmsg +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "struct io_uring_recvmsg_out *io_uring_recvmsg_validate(void *" buf "," +.BI " int " buf_len "," +.BI " struct msghdr *" msgh ");" +.PP +.BI "void *io_uring_recvmsg_name(struct io_uring_recvmsg_out *" o ");" +.PP +.BI "struct cmsghdr *io_uring_recvmsg_cmsg_firsthdr(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh ");" +.BI "struct cmsghdr *io_uring_recvmsg_cmsg_nexthdr(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh "," +.BI " struct cmsghdr *" cmsg ");" +.PP +.BI "void *io_uring_recvmsg_payload(struct io_uring_recvmsg_out *" o "," +.BI " struct msghdr *" msgh ");" +.BI "unsigned int io_uring_recvmsg_payload_length(struct io_uring_recvmsg_out *" o "," +.BI " int " buf_len "," +.BI " struct msghdr *" msgh ");" +.PP +.fi + +.SH DESCRIPTION + +These functions are used to access data in the payload delivered by +.BR io_uring_prep_recvmsg_multishot (3). +.PP +.I msgh +should point to the +.I struct msghdr +submitted with the request. +.PP +.BR io_uring_recvmsg_validate (3) +will validate a buffer delivered by +.BR io_uring_prep_recvmsg_multishot (3) +and extract the +.I io_uring_recvmsg_out +if it is valid, returning a pointer to it or else NULL. +.PP +The structure is defined as follows: +.PP +.in +4n +.EX + +struct io_uring_recvmsg_out { + __u32 namelen; /* Name byte count as would have been populated + * by recvmsg(2) */ + __u32 controllen; /* Control byte count */ + __u32 payloadlen; /* Payload byte count as would have been returned + * by recvmsg(2) */ + __u32 flags; /* Flags result as would have been populated + * by recvmsg(2) */ +}; + +.IP * 3 +.BR io_uring_recvmsg_name (3) +returns a pointer to the name in the buffer. +.IP * +.BR io_uring_recvmsg_cmsg_firsthdr (3) +returns a pointer to the first cmsg in the buffer, or NULL. +.IP * +.BR io_uring_recvmsg_cmsg_nexthdr (3) +returns a pointer to the next cmsg in the buffer, or NULL. +.IP * +.BR io_uring_recvmsg_payload (3) +returns a pointer to the payload in the buffer. +.IP * +.BR io_uring_recvmsg_payload_length (3) +Calculates the usable payload length in bytes. + + +.SH "SEE ALSO" +.BR io_uring_prep_recvmsg_multishot (3) diff --git a/man/man3/io_uring_register_clock.3 b/man/man3/io_uring_register_clock.3 new file mode 100644 index 0000000000000000000000000000000000000000..56ed1ac2bcb5cb594761bf45f676f78e25b7ed41 --- /dev/null +++ b/man/man3/io_uring_register_clock.3 @@ -0,0 +1,72 @@ +.\" Copyright (C) 2024 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_clock 3 "Aug 18, 2024" "liburing-2.8" "liburing Manual" +.SH NAME +io_uring_register_clock \- set clock source for event waiting +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_clock(struct io_uring *" ring ", +.BI " struct io_uring_clock_register *" arg ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_register_clock (3) +function registers which clock source should be used by io_uring, when an +application waits for event completions. The +.IR ring +argument should point to the ring in question, and the +.IR arg +argument should be a pointer to a +.B struct io_uring_clock_register . + +The +.IR arg +argument must be filled in with the appropriate information. It looks as +follows: +.PP +.in +4n +.EX +struct io_uring_clock_register { + __u32 clockid; + __u32 __resv[3]; +}; +.EE +.in +.PP +The +.I clockid +field must contain the clock source, with valid sources being: +.TP +.B CLOCK_MONOTONIC +a nonsettable system-wide clock that represents monotonic time. +.TP +.B CLOCK_BOOTTIME +A nonsettable system-wide clock that is identical to +.B CLOCK_MONOTONIC , +except that is also icnludes any time that the system is suspended. +.PP +See +.BR clock_gettime (3) +for more details. + +The +.I __resv +fields must be filled with zeroes. + +Available since 6.12. + +.SH RETURN VALUE +On success +.BR io_uring_register_clock (3) +returns 0. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR clock_gettime (3), +.BR io_uring_register (2), +.BR io_uring_wait_cqe (3), +.BR io_uring_wait_cqe_timeout (3), diff --git a/man/man3/io_uring_register_eventfd.3 b/man/man3/io_uring_register_eventfd.3 new file mode 100644 index 0000000000000000000000000000000000000000..d7b23ee417d97cb27a18ed59a6ad4db9af1c7d0e --- /dev/null +++ b/man/man3/io_uring_register_eventfd.3 @@ -0,0 +1,50 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_eventfd 3 "April 16, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_register_eventfd \- register an eventfd with a ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_eventfd(struct io_uring *" ring "," +.BI " int " fd ");" +.PP +.BI "int io_uring_register_eventfd_async(struct io_uring *" ring "," +.BI " int " fd ");" +.PP +.BI "int io_uring_unregister_eventfd(struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +.BR io_uring_register_eventfd (3) +registers the eventfd file descriptor +.I fd +with the ring identified by +.IR ring . + +Whenever completions are posted to the CQ ring, an eventfd notification +is generated with the registered eventfd descriptor. If +.BR io_uring_register_eventfd_async (3) +is used, only events that completed out-of-line will trigger a notification. + +It notifications are no longer desired, +.BR io_uring_unregister_eventfd (3) +may be called to remove the eventfd registration. No eventfd argument is +needed, as a ring can only have a single eventfd registered. + +.SH NOTES +While io_uring generally takes care to avoid spurious events, they can occur. +Similarly, batched completions of CQEs may only trigger a single eventfd +notification even if multiple CQEs are posted. The application should make no +assumptions on number of events being available having a direct correlation to +eventfd notifications posted. An eventfd notification must thus only be treated +as a hint to check the CQ ring for completions. +.SH RETURN VALUE +Returns 0 on success, or +.BR -errno +on error. +.SH SEE ALSO +.BR eventfd (2) diff --git a/man/man3/io_uring_register_eventfd_async.3 b/man/man3/io_uring_register_eventfd_async.3 new file mode 100644 index 0000000000000000000000000000000000000000..d7b23ee417d97cb27a18ed59a6ad4db9af1c7d0e --- /dev/null +++ b/man/man3/io_uring_register_eventfd_async.3 @@ -0,0 +1,50 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_eventfd 3 "April 16, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_register_eventfd \- register an eventfd with a ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_eventfd(struct io_uring *" ring "," +.BI " int " fd ");" +.PP +.BI "int io_uring_register_eventfd_async(struct io_uring *" ring "," +.BI " int " fd ");" +.PP +.BI "int io_uring_unregister_eventfd(struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +.BR io_uring_register_eventfd (3) +registers the eventfd file descriptor +.I fd +with the ring identified by +.IR ring . + +Whenever completions are posted to the CQ ring, an eventfd notification +is generated with the registered eventfd descriptor. If +.BR io_uring_register_eventfd_async (3) +is used, only events that completed out-of-line will trigger a notification. + +It notifications are no longer desired, +.BR io_uring_unregister_eventfd (3) +may be called to remove the eventfd registration. No eventfd argument is +needed, as a ring can only have a single eventfd registered. + +.SH NOTES +While io_uring generally takes care to avoid spurious events, they can occur. +Similarly, batched completions of CQEs may only trigger a single eventfd +notification even if multiple CQEs are posted. The application should make no +assumptions on number of events being available having a direct correlation to +eventfd notifications posted. An eventfd notification must thus only be treated +as a hint to check the CQ ring for completions. +.SH RETURN VALUE +Returns 0 on success, or +.BR -errno +on error. +.SH SEE ALSO +.BR eventfd (2) diff --git a/man/man3/io_uring_register_file_alloc_range.3 b/man/man3/io_uring_register_file_alloc_range.3 new file mode 100644 index 0000000000000000000000000000000000000000..239ea7d67b93caebbc5520db8feac31016b0672e --- /dev/null +++ b/man/man3/io_uring_register_file_alloc_range.3 @@ -0,0 +1,52 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_file_alloc_range 3 "Oct 21, 2022" "liburing-2.3" "liburing Manual" +.SH NAME +io_uring_register_file_alloc_range \- set range for fixed file allocations +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_file_alloc_range(struct io_uring *" ring ", +.BI " unsigned " off "," +.BI " unsigned " len ");" +.BI " +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_register_file_alloc_range (3) +function sets the allowable range for fixed file index allocations within the +kernel. When requests that can instantiate a new fixed file are used with +.B IORING_FILE_INDEX_ALLOC , +the application is asking the kernel to allocate a new fixed file descriptor +rather than pass in a specific value for one. By default, the kernel will +pick any available fixed file descriptor within the range available. Calling +this function with +.I off +set to the starting offset and +.I len +set to the number of descriptors, the application can limit the allocated +descriptors to that particular range. This effectively allows the application +to set aside a range just for dynamic allocations, with the remainder being +used for specific values. + +The application must have registered a fixed file table upfront, eg through +.BR io_uring_register_files (3) +or +.BR io_uring_register_files_sparse (3) . + +Available since 6.0. + +.SH RETURN VALUE +On success +.BR io_uring_register_file_alloc_range (3) +returns 0. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_register_files (3) +.BR io_uring_prep_accept_direct (3) +.BR io_uring_prep_openat_direct (3) +.BR io_uring_prep_socket_direct (3) diff --git a/man/man3/io_uring_register_files.3 b/man/man3/io_uring_register_files.3 new file mode 100644 index 0000000000000000000000000000000000000000..c7f73e922b40701d4fcdce2dbfbafe4c5bb096f7 --- /dev/null +++ b/man/man3/io_uring_register_files.3 @@ -0,0 +1,120 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_files 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_register_files \- register file descriptors +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_files(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_tags(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr ");" +.PP +.BI "int io_uring_register_files_sparse(struct io_uring *" ring "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update_tag(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr_files ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_register_files (3) +function registers +.I nr_files +number of file descriptors defined by the array +.I files +belonging to the +.I ring +for subsequent operations. + +The +.BR io_uring_register_files_tags (3) +function behaves the same as +.BR io_uring_register_files (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +The +.BR io_uring_register_files_sparse (3) +function registers an empty file table of +.I nr_files +number of file descriptors. These files must be updated before use, using eg +.BR io_uring_register_files_update_tag (3). +Note that if the size of the sparse table exceeds what +.B RLIMIT_NOFILE +allows, then +.BR io_uring_register_files_sparse (3) +will attempt to raise the limit using +.B setrlimit (2) +and retry the operation. If the registration fails after doing that, then an +error will be returned. +The sparse variant is available in kernels 5.19 and later. + +Registering a file table is a prerequisite for using any request that uses +direct descriptors. + +Registered files have less overhead per operation than normal files. This +is due to the kernel grabbing a reference count on a file when an operation +begins, and dropping it when it's done. When the process file table is +shared, for example if the process has ever created any threads, then this +cost goes up even more. Using registered files reduces the overhead of +file reference management across requests that operate on a file. + +The +.BR io_uring_register_files_update (3) +function updates existing registered files. The +.I off +is offset on which to start the update +.I nr_files +number of files defined by the array +.I files +belonging to the +.IR ring . + +The +.BR io_uring_register_files_update_tag (3) +function behaves the same as +.BR io_uring_register_files_update (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +.SH RETURN VALUE +On success +.BR io_uring_register_files (3), +.BR io_uring_register_files_tags (3) +and +.BR io_uring_register_files_sparse (3) +return 0. +.BR io_uring_register_files_update (3) +and +.BR io_uring_register_files_update_tag (3) +return number of files updated. +On failure they return +.BR -errno . +.SH SEE ALSO +.BR io_uring_register (2), +.BR io_uring_get_sqe (3), +.BR io_uring_unregister_files (3) diff --git a/man/man3/io_uring_register_files_tags.3 b/man/man3/io_uring_register_files_tags.3 new file mode 100644 index 0000000000000000000000000000000000000000..c7f73e922b40701d4fcdce2dbfbafe4c5bb096f7 --- /dev/null +++ b/man/man3/io_uring_register_files_tags.3 @@ -0,0 +1,120 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_files 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_register_files \- register file descriptors +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_files(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_tags(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr ");" +.PP +.BI "int io_uring_register_files_sparse(struct io_uring *" ring "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update_tag(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr_files ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_register_files (3) +function registers +.I nr_files +number of file descriptors defined by the array +.I files +belonging to the +.I ring +for subsequent operations. + +The +.BR io_uring_register_files_tags (3) +function behaves the same as +.BR io_uring_register_files (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +The +.BR io_uring_register_files_sparse (3) +function registers an empty file table of +.I nr_files +number of file descriptors. These files must be updated before use, using eg +.BR io_uring_register_files_update_tag (3). +Note that if the size of the sparse table exceeds what +.B RLIMIT_NOFILE +allows, then +.BR io_uring_register_files_sparse (3) +will attempt to raise the limit using +.B setrlimit (2) +and retry the operation. If the registration fails after doing that, then an +error will be returned. +The sparse variant is available in kernels 5.19 and later. + +Registering a file table is a prerequisite for using any request that uses +direct descriptors. + +Registered files have less overhead per operation than normal files. This +is due to the kernel grabbing a reference count on a file when an operation +begins, and dropping it when it's done. When the process file table is +shared, for example if the process has ever created any threads, then this +cost goes up even more. Using registered files reduces the overhead of +file reference management across requests that operate on a file. + +The +.BR io_uring_register_files_update (3) +function updates existing registered files. The +.I off +is offset on which to start the update +.I nr_files +number of files defined by the array +.I files +belonging to the +.IR ring . + +The +.BR io_uring_register_files_update_tag (3) +function behaves the same as +.BR io_uring_register_files_update (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +.SH RETURN VALUE +On success +.BR io_uring_register_files (3), +.BR io_uring_register_files_tags (3) +and +.BR io_uring_register_files_sparse (3) +return 0. +.BR io_uring_register_files_update (3) +and +.BR io_uring_register_files_update_tag (3) +return number of files updated. +On failure they return +.BR -errno . +.SH SEE ALSO +.BR io_uring_register (2), +.BR io_uring_get_sqe (3), +.BR io_uring_unregister_files (3) diff --git a/man/man3/io_uring_register_files_update.3 b/man/man3/io_uring_register_files_update.3 new file mode 100644 index 0000000000000000000000000000000000000000..c7f73e922b40701d4fcdce2dbfbafe4c5bb096f7 --- /dev/null +++ b/man/man3/io_uring_register_files_update.3 @@ -0,0 +1,120 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_files 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_register_files \- register file descriptors +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_files(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_tags(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr ");" +.PP +.BI "int io_uring_register_files_sparse(struct io_uring *" ring "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update_tag(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr_files ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_register_files (3) +function registers +.I nr_files +number of file descriptors defined by the array +.I files +belonging to the +.I ring +for subsequent operations. + +The +.BR io_uring_register_files_tags (3) +function behaves the same as +.BR io_uring_register_files (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +The +.BR io_uring_register_files_sparse (3) +function registers an empty file table of +.I nr_files +number of file descriptors. These files must be updated before use, using eg +.BR io_uring_register_files_update_tag (3). +Note that if the size of the sparse table exceeds what +.B RLIMIT_NOFILE +allows, then +.BR io_uring_register_files_sparse (3) +will attempt to raise the limit using +.B setrlimit (2) +and retry the operation. If the registration fails after doing that, then an +error will be returned. +The sparse variant is available in kernels 5.19 and later. + +Registering a file table is a prerequisite for using any request that uses +direct descriptors. + +Registered files have less overhead per operation than normal files. This +is due to the kernel grabbing a reference count on a file when an operation +begins, and dropping it when it's done. When the process file table is +shared, for example if the process has ever created any threads, then this +cost goes up even more. Using registered files reduces the overhead of +file reference management across requests that operate on a file. + +The +.BR io_uring_register_files_update (3) +function updates existing registered files. The +.I off +is offset on which to start the update +.I nr_files +number of files defined by the array +.I files +belonging to the +.IR ring . + +The +.BR io_uring_register_files_update_tag (3) +function behaves the same as +.BR io_uring_register_files_update (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +.SH RETURN VALUE +On success +.BR io_uring_register_files (3), +.BR io_uring_register_files_tags (3) +and +.BR io_uring_register_files_sparse (3) +return 0. +.BR io_uring_register_files_update (3) +and +.BR io_uring_register_files_update_tag (3) +return number of files updated. +On failure they return +.BR -errno . +.SH SEE ALSO +.BR io_uring_register (2), +.BR io_uring_get_sqe (3), +.BR io_uring_unregister_files (3) diff --git a/man/man3/io_uring_register_files_update_tag.3 b/man/man3/io_uring_register_files_update_tag.3 new file mode 100644 index 0000000000000000000000000000000000000000..c7f73e922b40701d4fcdce2dbfbafe4c5bb096f7 --- /dev/null +++ b/man/man3/io_uring_register_files_update_tag.3 @@ -0,0 +1,120 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_files 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_register_files \- register file descriptors +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_files(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_tags(struct io_uring *" ring "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr ");" +.PP +.BI "int io_uring_register_files_sparse(struct io_uring *" ring "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " unsigned " nr_files ");" +.PP +.BI "int io_uring_register_files_update_tag(struct io_uring *" ring "," +.BI " unsigned " off "," +.BI " const int *" files "," +.BI " const __u64 *" tags "," +.BI " unsigned " nr_files ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_register_files (3) +function registers +.I nr_files +number of file descriptors defined by the array +.I files +belonging to the +.I ring +for subsequent operations. + +The +.BR io_uring_register_files_tags (3) +function behaves the same as +.BR io_uring_register_files (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +The +.BR io_uring_register_files_sparse (3) +function registers an empty file table of +.I nr_files +number of file descriptors. These files must be updated before use, using eg +.BR io_uring_register_files_update_tag (3). +Note that if the size of the sparse table exceeds what +.B RLIMIT_NOFILE +allows, then +.BR io_uring_register_files_sparse (3) +will attempt to raise the limit using +.B setrlimit (2) +and retry the operation. If the registration fails after doing that, then an +error will be returned. +The sparse variant is available in kernels 5.19 and later. + +Registering a file table is a prerequisite for using any request that uses +direct descriptors. + +Registered files have less overhead per operation than normal files. This +is due to the kernel grabbing a reference count on a file when an operation +begins, and dropping it when it's done. When the process file table is +shared, for example if the process has ever created any threads, then this +cost goes up even more. Using registered files reduces the overhead of +file reference management across requests that operate on a file. + +The +.BR io_uring_register_files_update (3) +function updates existing registered files. The +.I off +is offset on which to start the update +.I nr_files +number of files defined by the array +.I files +belonging to the +.IR ring . + +The +.BR io_uring_register_files_update_tag (3) +function behaves the same as +.BR io_uring_register_files_update (3) +function but additionally takes +.I tags +parameter. See +.B IORING_REGISTER_BUFFERS2 +for the resource tagging description. + +.SH RETURN VALUE +On success +.BR io_uring_register_files (3), +.BR io_uring_register_files_tags (3) +and +.BR io_uring_register_files_sparse (3) +return 0. +.BR io_uring_register_files_update (3) +and +.BR io_uring_register_files_update_tag (3) +return number of files updated. +On failure they return +.BR -errno . +.SH SEE ALSO +.BR io_uring_register (2), +.BR io_uring_get_sqe (3), +.BR io_uring_unregister_files (3) diff --git a/man/man3/io_uring_register_ring_fd.3 b/man/man3/io_uring_register_ring_fd.3 new file mode 100644 index 0000000000000000000000000000000000000000..0284fe415744acd4e2a91b5bda75451006c9a53a --- /dev/null +++ b/man/man3/io_uring_register_ring_fd.3 @@ -0,0 +1,51 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_ring_fd 3 "March 11, 2022" "liburing-2.2" "liburing Manual" +.SH NAME +io_uring_register_ring_fd \- register a ring file descriptor +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_ring_fd(struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +.BR io_uring_register_ring_fd (3) +registers the file descriptor of the ring. + +Whenever +.BR io_uring_enter (2) +is called to submit request or wait for completions, the kernel must grab a +reference to the file descriptor. If the application using io_uring is threaded, +the file table is marked as shared, and the reference grab and put of the file +descriptor count is more expensive than it is for a non-threaded application. + +Similarly to how io_uring allows registration of files, this allow registration +of the ring file descriptor itself. This reduces the overhead of the +.BR io_uring_enter (2) +system call. + +If an application using liburing is threaded, then an application should call +this function to register the ring descriptor when a ring is set up. See NOTES +for restrictions when a ring is shared. + +Available since kernel 5.18. + +.SH NOTES +When the ring descriptor is registered, it is stored internally in the +.I struct io_uring +structure. For applications that share a ring between threads, for example +having one thread do submits and another reap events, then this optimization +cannot be used as each thread may have a different index for the registered +ring fd. +.SH RETURN VALUE +Returns 1 on success, indicating that one file descriptor was registered, +or +.BR -errno +on error. +.SH SEE ALSO +.BR io_uring_unregister_ring_fd (3), +.BR io_uring_register_files (3) diff --git a/man/man3/io_uring_register_sync_cancel.3 b/man/man3/io_uring_register_sync_cancel.3 new file mode 100644 index 0000000000000000000000000000000000000000..449bc0ff9ef8542a8bcdf640d194d0916694465f --- /dev/null +++ b/man/man3/io_uring_register_sync_cancel.3 @@ -0,0 +1,73 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_register_sync_cancel 3 "September 21, 2022" "liburing-2.3" "liburing Manual" +.SH NAME +io_uring_register_sync_cancel \- issue a synchronous cancelation request +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_register_sync_cancel(struct io_uring *" ring ", +.BI " struct io_uring_sync_cancel_reg *" reg "); +.PP +.SH DESCRIPTION +.PP +The +.BR io_uring_register_sync_cancel (3) +function performs a synchronous cancelation request based on the parameters +specified in +.I reg . + +The +.I reg +argument must be filled in with the appropriate information for the +cancelation request. It looks as follows: +.PP +.in +4n +.EX +struct io_uring_sync_cancel_reg { + __u64 addr; + __s32 fd; + __u32 flags; + struct __kernel_timespec timeout; + __u8 opcode; + __u8 pad[7]; + __u64 pad2[3]; +}; +.EE +.in +.PP + +The arguments largely mirror what the async prep functions support, see +.BR io_uring_prep_cancel (3) +for details. Similarly, the return value is the same. The exception is the +.I timeout +argument, which can be used to limit the time that the kernel will wait for +cancelations to be successful. If the +.I tv_sec +and +.I tv_nsec +values are set to anything but +.B -1UL , +then they indicate a relative timeout upon which cancelations should be +completed by. + +The +.I pad +values must be zero filled. + +.SH RETURN VALUE +See +.BR io_uring_prep_cancel (3) +for details on the return value. If +.I timeout +is set to indicate a timeout, then +.B -ETIME +will be returned if exceeded. If an unknown value is set in the request, +or if the pad values are not cleared to zero, then +.I -EINVAL +is returned. +.SH SEE ALSO +.BR io_uring_prep_cancel (3) diff --git a/man/man3/io_uring_resize_rings.3 b/man/man3/io_uring_resize_rings.3 new file mode 100644 index 0000000000000000000000000000000000000000..4d4a92867da275182277e266147f31711200c3bb --- /dev/null +++ b/man/man3/io_uring_resize_rings.3 @@ -0,0 +1,116 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_resize_rings 3 "October 29, 2024" "liburing-2.9" "liburing Manual" +.SH NAME +io_uring_resize_rings \- resize the SQ and CQ rings +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_resize_rings(struct io_uring *" ring ", +.BI " struct io_uring_params *" p "); +.PP +.SH DESCRIPTION +.PP +The +.BR io_uring_resize_rings (3) +function performs resizes the SQ and/or CQ ring associated with +.I ring +by the parameters specified in +.I p . + +The +.I p +argument must be filled in with the appropriate information for the resize +operations, most notably the +.IR sq_entries +and +.IR cq_entries +fields must be filled out. The +.IR flags +field can also be set, see below for potential values that may be used with +a resize operation. + +It's fairly uncommon to need to resize the SQ ring, but not that uncommon +that the CQ ring would need resizing. For networked workloads, it can be +hard to appropriately size the CQ ring upfront, as it's not always known what +load a given ring will see. If overflow conditions are seen for the CQ ring, +then resizing it larger may be a good idea. + +When a ring is resized, any pending SQ or CQ entries are copied along the +way. It is not legal to resize a CQ ring that is in an overflow condition, +and attempting to do so will fail. + +Currently doesn't support resizing rings setup with +.B IORING_SETUP_NO_MMAP . +This is purely a liburing limitation, the kernel does support it. + +Also note that ring resizing is currently only supported on rings setup +with +.B IORING_SETUP_DEFER_TASKRUN . +Attempting to resize differently configured rings will result in an +.BR -EINVAL +error. + +Valid flags in +.IR flags : +.TP +.B IORING_SETUP_CQSIZE +If this isn't set, then the CQ ring size is set based on the specified +SQ ring size. The default is twice as many CQ ring entries as there are +SQ ring entries. If set, then +.IR cq_entries +will be used to size the CQ ring. +.TP +.B IORING_SETUP_CLAMP +If set, then SQ and CQ ring entries are clamped to the maximum allowable +size, if they exceed that. If not set, setting sizes too large will cause +the operation to fail. +.PP + +Other flags are inherited from the way the ring was setup, that includes flags +like +.B IORING_SETUP_NO_SQARRAY , +.B IORING_SETUP_SQE128 , +.B IORING_SETUP_CQE32 , +and +.B IORING_SETUP_NO_MMAP . + +Other fields in +.IR p +should be cleared to zero. + +Available since kernel 6.13. + +Also see +.BR io_uring_setup (2) +for a detailed description of the setup flags. + +.SH RETURN VALUE +.PP +Returns 0 on success, and < 0 on failure. Potential common failure cases: +.TP +.B -EEXIST +Attempting to resize a ring setup with +.B IORING_SETUP_SINGLE_ISSUER +and the resizing task is different from the one that created/enabled the ring. +.TP +.B -EFAULT +Copying of +.I p +was unsuccessful. +.TP +.B -EINVAL +Invalid flags were specified for the operation +.TP +.B -EINVAL +Attempt to resize a ring not setup with +.BR IORING_SETUP_DEFER_TASKRUN . +.TP +.B -EOVERFLOW +The values specified for SQ or CQ entries would cause an overflow. + +.SH SEE ALSO +.BR io_uring_setup (2) diff --git a/man/man3/io_uring_setup_buf_ring.3 b/man/man3/io_uring_setup_buf_ring.3 new file mode 100644 index 0000000000000000000000000000000000000000..c50748ddbd68b07d6f722d890ebf04243dee8fb8 --- /dev/null +++ b/man/man3/io_uring_setup_buf_ring.3 @@ -0,0 +1,94 @@ +.\" Copyright (C) 2022 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_setup_buf_ring 3 "Mar 07, 2023" "liburing-2.4" "liburing Manual" +.SH NAME +io_uring_setup_buf_ring \- setup and register buffer ring for provided buffers +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "struct io_uring_buf_ring *io_uring_setup_buf_ring(struct io_uring *" ring ", +.BI " unsigned int " nentries ", +.BI " int " bgid ", +.BI " unsigned int " flags ", +.BI " int *" err ");" +.BI " +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_setup_buf_ring (3) +function registers a shared buffer ring to be used with provided buffers. For +the request types that support it, provided buffers are given to the ring and +one is selected by a request if it has +.B IOSQE_BUFFER_SELECT +set in the SQE +.IR flags , +when the request is ready to receive data. This allows both clear ownership +of the buffer lifetime, and a way to have more read/receive type of operations +in flight than buffers available. + +The +.I ring +argument must pointer to the ring for which the provided buffer ring is being +registered, +.I nentries +is the number of entries requested in the buffer ring. This argument must be +a power-of 2 in size, and can be up to 32768 in size. +.I bgid +is the chosen buffer group ID, +.I flags +are modifier flags for the operation, and +.I *err +is is a pointer to an integer for the error value if any part of the ring +allocation and registration fails. + +The +.I flags +argument can be set to one of the following values: +.TP +.B IOU_PBUF_RING_INC +The buffers in this ring can be incrementally consumed. With partial +consumption, each completion of a given buffer ID will continue where the +previous one left off, or from the start if no completions have been seen yet. +When more completions should be expected for a given buffer ID, the CQE will +have +.B IORING_CQE_F_BUF_MORE +set in the +.I flags +member. Available since 6.12. +.PP + +Under the covers, this function uses +.BR io_uring_register_buf_ring (3) +to register the ring, and handles the allocation of the ring rather than +letting the application open code it. + +To unregister and free a buffer group ID setup with this function, the +application must call +.BR io_uring_free_buf_ring (3) . + +Available since 5.19. + +.SH RETURN VALUE +On success +.BR io_uring_setup_buf_ring (3) +returns a pointer to the buffer ring. On failure it returns +.BR NULL +and sets +.I *err +to -errno. +.SH NOTES +Note that even if the kernel supports this feature, registering a provided +buffer ring may still fail with +.B -EINVAL +if the host is a 32-bit architecture and the memory being passed in resides in +high memory. +.SH SEE ALSO +.BR io_uring_register_buf_ring (3), +.BR io_uring_buf_ring_init (3), +.BR io_uring_buf_ring_add (3), +.BR io_uring_buf_ring_advance (3), +.BR io_uring_buf_ring_cq_advance (3) diff --git a/man/man3/io_uring_sq_ready.3 b/man/man3/io_uring_sq_ready.3 new file mode 100644 index 0000000000000000000000000000000000000000..ba155b3210d02c544708a47c1440773cda90e82e --- /dev/null +++ b/man/man3/io_uring_sq_ready.3 @@ -0,0 +1,31 @@ +.\" Copyright (C) 2022 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_sq_ready 3 "January 25, 2022" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_sq_ready \- number of unconsumed or unsubmitted entries in the SQ ring +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "unsigned io_uring_sq_ready(const struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_sq_ready (3) +function returns the number of unconsumed (if SQPOLL) or unsubmitted entries +that exist in the SQ ring belonging to the +.I ring +param. + +Usage of this function only applies if the ring has been setup with +.B IORING_SETUP_SQPOLL, +where request submissions, and hence consumption from the SQ ring, happens +through a polling thread. + +.SH RETURN VALUE +Returns the number of unconsumed or unsubmitted entries in the SQ ring. +.SH SEE ALSO +.BR io_uring_cq_ready (3) diff --git a/man/man3/io_uring_sqe_set_buf_group.3 b/man/man3/io_uring_sqe_set_buf_group.3 new file mode 100644 index 0000000000000000000000000000000000000000..5299051d07e30271b4b0dc069df4157930ca19a7 --- /dev/null +++ b/man/man3/io_uring_sqe_set_buf_group.3 @@ -0,0 +1,32 @@ +.\" Copyright (C) 2024 Christian Mazakas +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_sqe_set_buf_group 3 "December 9, 2024" "liburing-2.9" "liburing Manual" +.SH NAME +io_uring_sqe_set_buf_group \- set buf group for submission queue event +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "void io_uring_sqe_set_buf_group(struct io_uring_sqe *" sqe "," +.BI " int " bgid ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_sqe_set_buf_group (3) +function sets the associated buf_group of the +.I sqe +to +.IR bgid . + +After the caller has requested a submission queue entry (SQE) with +.BR io_uring_get_sqe (3) , +they can associate a buf_group with the SQE used for multishot operations. + +.SH RETURN VALUE +None +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_cqe_set_data (3) diff --git a/man/man3/io_uring_submit.3 b/man/man3/io_uring_submit.3 new file mode 100644 index 0000000000000000000000000000000000000000..c7dbbed21dfb6d4ad8effa91e9d029d0edd911fc --- /dev/null +++ b/man/man3/io_uring_submit.3 @@ -0,0 +1,51 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_submit 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_submit \- submit requests to the submission queue +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_submit(struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_submit (3) +function submits the next events to the submission queue belonging to the +.IR ring . + +After the caller retrieves a submission queue entry (SQE) with +.BR io_uring_get_sqe (3) +and prepares the SQE using one of the provided helpers, it can be submitted with +.BR io_uring_submit (3) . + +.SH RETURN VALUE +On success +.BR io_uring_submit (3) +returns the number of submitted submission queue entries, if SQPOLL is not used. +If SQPOLL is used, the return value may report a higher number of submitted +entries than actually submitted. If the user requires accurate information +about how many submission queue entries have been successfully submitted, while +using SQPOLL, the user must fall back to repeatedly submitting a single submission +queue entry. On failure it returns +.BR -errno . +.SH NOTES +For any request that passes in data in a struct, that data must remain +valid until the request has been successfully submitted. It need not remain +valid until completion. Once a request has been submitted, the in-kernel +state is stable. Very early kernels (5.4 and earlier) required state to be +stable until the completion occurred. Applications can test for this +behavior by inspecting the +.B IORING_FEAT_SUBMIT_STABLE +flag passed back from +.BR io_uring_queue_init_params (3). +In general, the man pages for the individual prep helpers will have a note +mentioning this fact as well, if required for the given command. +.SH SEE ALSO +.BR io_uring_get_sqe (3), +.BR io_uring_submit_and_wait (3), +.BR io_uring_submit_and_wait_timeout (3) diff --git a/man/man3/io_uring_submit_and_get_events.3 b/man/man3/io_uring_submit_and_get_events.3 new file mode 100644 index 0000000000000000000000000000000000000000..9e143d1dff4767151b73356ab7ee00dcd4a5947e --- /dev/null +++ b/man/man3/io_uring_submit_and_get_events.3 @@ -0,0 +1,31 @@ +.\" Copyright (C), 2022 dylany +.\" You may distribute this file under the terms of the GNU Free +.\" Documentation License. +.TH io_uring_submit_and_get_events 3 "September 5, 2022" "liburing-2.3" "liburing Manual" +.SH NAME +io_uring_submit_and_get_events \- submit requests to the submission queue and flush completions +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_submit_and_get_events(struct io_uring *" ring ");" +.fi + +.SH DESCRIPTION +The +.BR io_uring_submit_and_get_events (3) +function submits the next events to the submission queue as with +.BR io_uring_submit (3) . +After submission it will flush CQEs as with +.BR io_uring_get_events (3) . + +The benefit of this function is that it does both with only one system call. + +.SH RETURN VALUE +On success +.BR io_uring_submit_and_get_events (3) +returns the number of submitted submission queue entries. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_submit (3), +.BR io_uring_get_events (3) diff --git a/man/man3/io_uring_submit_and_wait.3 b/man/man3/io_uring_submit_and_wait.3 new file mode 100644 index 0000000000000000000000000000000000000000..2351f335a7aa591fe07bcaa82a71b164ad181af4 --- /dev/null +++ b/man/man3/io_uring_submit_and_wait.3 @@ -0,0 +1,44 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_submit_and_wait 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_submit_and_wait \- submit requests to the submission queue and wait for completion +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_submit_and_wait(struct io_uring *" ring "," +.BI " unsigned " wait_nr ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_submit_and_wait (3) +function submits the next requests from the submission queue belonging to the +.I ring +and waits for +.I wait_nr +completion events. + +After the caller retrieves a submission queue entry (SQE) with +.BR io_uring_get_sqe (3) +and prepares the SQE, it can be submitted with +.BR io_uring_submit_and_wait (3) . + +Ideally used with a ring setup with +.BR IORING_SETUP_SINGLE_ISSUER | IORING_SETUP_DEFER_TASKRUN +as that will greatly reduce the number of context switches that an application +will see waiting on multiple requests. + +.SH RETURN VALUE +On success +.BR io_uring_submit_and_wait (3) +returns the number of submitted submission queue entries. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_queue_init_params (3), +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_submit_and_wait_timeout (3) diff --git a/man/man3/io_uring_submit_and_wait_timeout.3 b/man/man3/io_uring_submit_and_wait_timeout.3 new file mode 100644 index 0000000000000000000000000000000000000000..74611766b38545cc07b45789d76a233dc7abf538 --- /dev/null +++ b/man/man3/io_uring_submit_and_wait_timeout.3 @@ -0,0 +1,74 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_submit_and_wait_timeout 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_submit_and_wait_timeout \- submit requests to the submission queue and +wait for the completion with timeout +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_submit_and_wait_timeout(struct io_uring *" ring "," +.BI " struct io_uring_cqe **" cqe_ptr "," +.BI " unsigned " wait_nr "," +.BI " struct __kernel_timespec *" ts "," +.BI " sigset_t *" sigmask ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_submit_and_wait_timeout (3) +function submits the next requests from the submission queue belonging to the +.I ring +and waits for +.I wait_nr +completion events, or until the timeout +.I ts +expires. The completion events are stored in the +.I cqe_ptr +array. +.PP +The +.I sigmask +specifies the set of signals to block. If set, it is equivalent to atomically +executing the following calls: +.PP +.in +4n +.EX +sigset_t origmask; + +pthread_sigmask(SIG_SETMASK, &sigmask, &origmask); +ret = io_uring_submit_and_wait_timeout(ring, cqe, wait_nr, ts, NULL); +pthread_sigmask(SIG_SETMASK, &origmask, NULL); +.EE +.in +.PP +After the caller retrieves a submission queue entry (SQE) with +.BR io_uring_get_sqe (3) +and prepares the SQE, it can be submitted with +.BR io_uring_submit_and_wait_timeout (3) . + +Ideally used with a ring setup with +.BR IORING_SETUP_SINGLE_ISSUER | IORING_SETUP_DEFER_TASKRUN +as that will greatly reduce the number of context switches that an application +will see waiting on multiple requests. + +.SH RETURN VALUE +On success +.BR io_uring_submit_and_wait_timeout (3) +returns the number of submitted submission queue entries. On failure it returns +.BR -errno . +Note that in earlier versions of the liburing library, the return value was 0 +on success. +The most common failure case is not receiving a completion within the specified +timeout, +.B -ETIME +is returned in this case. +.SH SEE ALSO +.BR io_uring_queue_init_params (3), +.BR io_uring_get_sqe (3), +.BR io_uring_submit (3), +.BR io_uring_submit_and_wait (3), +.BR io_uring_wait_cqe (3) diff --git a/man/man3/io_uring_unregister_files.3 b/man/man3/io_uring_unregister_files.3 new file mode 100644 index 0000000000000000000000000000000000000000..c468d0813f2489a0cb342573e89daddebe7d051b --- /dev/null +++ b/man/man3/io_uring_unregister_files.3 @@ -0,0 +1,27 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_unregister_files 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_unregister_files \- unregister file descriptors +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_unregister_files(struct io_uring *" ring ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_unregister_files (3) +function unregisters the file descriptors previously registered to the +.IR ring . + +.SH RETURN VALUE +On success +.BR io_uring_unregister_files (3) +returns 0. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_register_files (3) diff --git a/man/man3/io_uring_wait_cqe_timeout.3 b/man/man3/io_uring_wait_cqe_timeout.3 new file mode 100644 index 0000000000000000000000000000000000000000..901772b91679f2ee5eaae4ca7e5f5e25f48369ed --- /dev/null +++ b/man/man3/io_uring_wait_cqe_timeout.3 @@ -0,0 +1,61 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_wait_cqe_timeout 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_wait_cqe_timeout \- wait for one io_uring completion event with timeout +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_wait_cqe_timeout(struct io_uring *" ring "," +.BI " struct io_uring_cqe **" cqe_ptr "," +.BI " struct __kernel_timespec *" ts ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_wait_cqe_timeout (3) +function waits for one IO completion to be available from the queue belonging +to the +.I ring +param, waiting for it if necessary or until the timeout +.I ts +expires. If an event is already available in the ring when invoked, no waiting +will occur. + +The +.I cqe_ptr +param is filled in on success. + +If +.I ts +is specified and an older kernel without +.B IORING_FEAT_EXT_ARG +is used, the application does not need to call +.BR io_uring_submit (3) +before calling +.BR io_uring_wait_cqes (3). +For newer kernels with that feature flag set, there is no implied submit +when waiting for a request. + +If +.I ts +is +.B NULL , +then this behaves like +.BR io_uring_wait_cqe (3) +in that it will wait forever for an event. + +.SH RETURN VALUE +On success +.BR io_uring_wait_cqe_timeout (3) +returns 0 and the cqe_ptr param is filled in. On failure it returns +.BR -errno . +The return value indicates the result of waiting for a CQE, and it has no +relation to the CQE result itself. +.SH SEE ALSO +.BR io_uring_submit (3), +.BR io_uring_wait_cqes (3), +.BR io_uring_wait_cqe (3) diff --git a/man/man3/io_uring_wait_cqes.3 b/man/man3/io_uring_wait_cqes.3 new file mode 100644 index 0000000000000000000000000000000000000000..816cd73abac3d6164b85379e8beb011bedd5cb1e --- /dev/null +++ b/man/man3/io_uring_wait_cqes.3 @@ -0,0 +1,80 @@ +.\" Copyright (C) 2021 Stefan Roesch +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_wait_cqes 3 "November 15, 2021" "liburing-2.1" "liburing Manual" +.SH NAME +io_uring_wait_cqes \- wait for one or more io_uring completion events +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_wait_cqes(struct io_uring *" ring "," +.BI " struct io_uring_cqe **" cqe_ptr "," +.BI " unsigned " wait_nr "," +.BI " struct __kernel_timespec *" ts "," +.BI " sigset_t *" sigmask "); +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_wait_cqes (3) +function returns +.I wait_nr +IO completions from the queue belonging to the +.I ring +param, waiting for them if necessary or until the timeout +.I ts +expires. +.PP +The +.I sigmask +specifies the set of signals to block. If set, it is equivalent to atomically +executing the following calls: +.PP +.in +4n +.EX +sigset_t origmask; + +pthread_sigmask(SIG_SETMASK, &sigmask, &origmask); +ret = io_uring_wait_cqes(ring, cqe, wait_nr, ts, NULL); +pthread_sigmask(SIG_SETMASK, &origmask, NULL); +.EE +.in +.PP +The +.I cqe_ptr +param is filled in on success with the first CQE. Callers of this function +should use +.BR io_uring_for_each_cqe (3) +to iterate all available CQEs. + +If +.I ts +is specified and an older kernel without +.B IORING_FEAT_EXT_ARG +is used, the application does not need to call +.BR io_uring_submit (3) +before calling +.BR io_uring_wait_cqes (3). +For newer kernels with that feature flag set, there is no implied submit +when waiting for a request. + +If +.I ts +is +.B NULL , +then this behaves like +.BR io_uring_wait_cqe (3) +in that it will wait forever for an event. + +.SH RETURN VALUE +On success +.BR io_uring_wait_cqes (3) +returns 0 and the cqe_ptr param is filled in. On failure it returns +.BR -errno . +.SH SEE ALSO +.BR io_uring_submit (3), +.BR io_uring_for_each_cqe (3), +.BR io_uring_wait_cqe_timeout (3), +.BR io_uring_wait_cqe (3) diff --git a/man/man3/io_uring_wait_cqes_min_timeout.3 b/man/man3/io_uring_wait_cqes_min_timeout.3 new file mode 100644 index 0000000000000000000000000000000000000000..e3d9849d44b681bb15999fb3038951f82fa7d405 --- /dev/null +++ b/man/man3/io_uring_wait_cqes_min_timeout.3 @@ -0,0 +1,76 @@ +.\" Copyright (C) 2024 Jens Axboe +.\" +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" +.TH io_uring_wait_cqes_min_timeout 3 "Feb 13, 2024" "liburing-2.8" "liburing Manual" +.SH NAME +io_uring_wait_cqes_min_timeout \- wait for completions with both batch and normal timeout +.SH SYNOPSIS +.nf +.B #include +.PP +.BI "int io_uring_wait_cqes_min_timeout(struct io_uring *" ring "," +.BI " struct io_uring_cqe **" cqe_ptr "," +.BI " unsigned " wait_nr "," +.BI " struct __kernel_timespec *" ts "," +.BI " unsigned int " min_wait_usec ", +.BI " sigset_t *" sigmask ");" +.fi +.SH DESCRIPTION +.PP +The +.BR io_uring_wait_cqes_min_timeout (3) +waits for completions from the submission queue belonging to the +.I ring +and waits for +.I wait_nr +completion events, or until the timeout +.I ts +expires. The completion events are stored in the +.I cqe_ptr +array. If non-zero, +.I min_wait_usec +denotes a timeout for the +.I wait_nr +batch. + +The +.I sigmask +specifies the set of signals to block. If set, it is equivalent to atomically +executing the following calls: +.PP +.in +4n +.EX +sigset_t origmask; + +pthread_sigmask(SIG_SETMASK, &sigmask, &origmask); +ret = io_uring_wait_cqes_min_timeout(ring, cqe, wait_nr, ts, min_wait, NULL); +pthread_sigmask(SIG_SETMASK, &origmask, NULL); +.EE +.in +.PP +This works like +.BR io_uring_submit_and_wait_min_timeout (3) +except that it doesn't submit requests. See that man page for a description +for how the min timeout waiting works. + +Available since 6.12. + +.SH RETURN VALUE +On success +.BR io_uring_wait_cqes_min_timeout (3) +returns the 0.On failure it returns +.BR -errno . +If the kernel doesn't support this functionality, +.BR -EINVAL +will be returned. See note on the feature flag. +The most common failure case is not receiving a completion within the specified +timeout, +.B -ETIME +is returned in this case. +.SH SEE ALSO +.BR io_uring_wait_cqe (3), +.BR io_uring_wait_cqes (3), +.BR io_uring_wait_cqe_timeout (3), +.BR io_uring_wait_cqes (3), +.BR io_uring_submit_and_wait_min_timeout (3) diff --git a/man/man7/fsf-funding.7 b/man/man7/fsf-funding.7 new file mode 100644 index 0000000000000000000000000000000000000000..c43f19a72cb9bcec6fb99e521de955f71cc811f2 --- /dev/null +++ b/man/man7/fsf-funding.7 @@ -0,0 +1,189 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.if !\nF .nr F 0 +.if \nF>0 \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "FSF-FUNDING 7" +.TH FSF-FUNDING 7 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +fsf\-funding \- Funding Free Software +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +.SS "Funding Free Software" +.IX Subsection "Funding Free Software" +If you want to have more free software a few years from now, it makes +sense for you to help encourage people to contribute funds for its +development. The most effective approach known is to encourage +commercial redistributors to donate. +.PP +Users of free software systems can boost the pace of development by +encouraging for-a-fee distributors to donate part of their selling price +to free software developers\-\-\-the Free Software Foundation, and others. +.PP +The way to convince distributors to do this is to demand it and expect +it from them. So when you compare distributors, judge them partly by +how much they give to free software development. Show distributors +they must compete to be the one who gives the most. +.PP +To make this approach work, you must insist on numbers that you can +compare, such as, \*(L"We will donate ten dollars to the Frobnitz project +for each disk sold.\*(R" Don't be satisfied with a vague promise, such as +\&\*(L"A portion of the profits are donated,\*(R" since it doesn't give a basis +for comparison. +.PP +Even a precise fraction \*(L"of the profits from this disk\*(R" is not very +meaningful, since creative accounting and unrelated business decisions +can greatly alter what fraction of the sales price counts as profit. +If the price you pay is \f(CW$50\fR, ten percent of the profit is probably +less than a dollar; it might be a few cents, or nothing at all. +.PP +Some redistributors do development work themselves. This is useful too; +but to keep everyone honest, you need to inquire how much they do, and +what kind. Some kinds of development make much more long-term +difference than others. For example, maintaining a separate version of +a program contributes very little; maintaining the standard version of a +program for the whole community contributes much. Easy new ports +contribute little, since someone else would surely do them; difficult +ports such as adding a new \s-1CPU\s0 to the \s-1GNU\s0 Compiler Collection contribute more; +major new features or packages contribute the most. +.PP +By establishing the idea that supporting further development is \*(L"the +proper thing to do\*(R" when distributing free software for a fee, we can +assure a steady flow of resources into making more free software. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7). +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1994 Free Software Foundation, Inc. +Verbatim copying and redistribution of this section is permitted +without royalty; alteration is not permitted. diff --git a/man/man7/gfdl.7 b/man/man7/gfdl.7 new file mode 100644 index 0000000000000000000000000000000000000000..72165455a3a62ab61bcc6c73a7e7d7952e7e4c10 --- /dev/null +++ b/man/man7/gfdl.7 @@ -0,0 +1,647 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.if !\nF .nr F 0 +.if \nF>0 \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GFDL 7" +.TH GFDL 7 "2022-05-27" "gcc-9.5.0" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gfdl \- GNU Free Documentation License +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\f(CW@comment\fR For some cases, this default \f(CW@node\fR/@unnumbered is not applicable and +\&\f(CW@comment\fR causes warnings. In those cases, the including file can set +\&\f(CW@comment\fR nodefaultgnufreedocumentationlicensenode and provide it's own version. +\&\f(CW@comment\fR F.i., when this file is included in an \f(CW@raisesections\fR context, the +\&\f(CW@comment\fR including file can use an \f(CW@unnumberedsec\fR. +.SS "\s-1GNU\s0 Free Documentation License" +.IX Subsection "GNU Free Documentation License" +.SS "Version 1.3, 3 November 2008" +.IX Subsection "Version 1.3, 3 November 2008" +.Vb 2 +\& Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. +\& EBE +\& +\& Everyone is permitted to copy and distribute verbatim copies +\& of this license document, but changing it is not allowed. +.Ve +.IP "0." 4 +.IX Item "0." +\&\s-1PREAMBLE\s0 +.Sp +The purpose of this License is to make a manual, textbook, or other +functional and useful document \fIfree\fR in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. +.Sp +This License is a kind of \*(L"copyleft\*(R", which means that derivative +works of the document must themselves be free in the same sense. It +complements the \s-1GNU\s0 General Public License, which is a copyleft +license designed for free software. +.Sp +We have designed this License in order to use it for manuals for free +software, because free software needs free documentation: a free +program should come with manuals providing the same freedoms that the +software does. But this License is not limited to software manuals; +it can be used for any textual work, regardless of subject matter or +whether it is published as a printed book. We recommend this License +principally for works whose purpose is instruction or reference. +.IP "1." 4 +.IX Item "1." +\&\s-1APPLICABILITY AND DEFINITIONS\s0 +.Sp +This License applies to any manual or other work, in any medium, that +contains a notice placed by the copyright holder saying it can be +distributed under the terms of this License. Such a notice grants a +world-wide, royalty-free license, unlimited in duration, to use that +work under the conditions stated herein. The \*(L"Document\*(R", below, +refers to any such manual or work. Any member of the public is a +licensee, and is addressed as \*(L"you\*(R". You accept the license if you +copy, modify or distribute the work in a way requiring permission +under copyright law. +.Sp +A \*(L"Modified Version\*(R" of the Document means any work containing the +Document or a portion of it, either copied verbatim, or with +modifications and/or translated into another language. +.Sp +A \*(L"Secondary Section\*(R" is a named appendix or a front-matter section +of the Document that deals exclusively with the relationship of the +publishers or authors of the Document to the Document's overall +subject (or to related matters) and contains nothing that could fall +directly within that overall subject. (Thus, if the Document is in +part a textbook of mathematics, a Secondary Section may not explain +any mathematics.) The relationship could be a matter of historical +connection with the subject or with related matters, or of legal, +commercial, philosophical, ethical or political position regarding +them. +.Sp +The \*(L"Invariant Sections\*(R" are certain Secondary Sections whose titles +are designated, as being those of Invariant Sections, in the notice +that says that the Document is released under this License. If a +section does not fit the above definition of Secondary then it is not +allowed to be designated as Invariant. The Document may contain zero +Invariant Sections. If the Document does not identify any Invariant +Sections then there are none. +.Sp +The \*(L"Cover Texts\*(R" are certain short passages of text that are listed, +as Front-Cover Texts or Back-Cover Texts, in the notice that says that +the Document is released under this License. A Front-Cover Text may +be at most 5 words, and a Back-Cover Text may be at most 25 words. +.Sp +A \*(L"Transparent\*(R" copy of the Document means a machine-readable copy, +represented in a format whose specification is available to the +general public, that is suitable for revising the document +straightforwardly with generic text editors or (for images composed of +pixels) generic paint programs or (for drawings) some widely available +drawing editor, and that is suitable for input to text formatters or +for automatic translation to a variety of formats suitable for input +to text formatters. A copy made in an otherwise Transparent file +format whose markup, or absence of markup, has been arranged to thwart +or discourage subsequent modification by readers is not Transparent. +An image format is not Transparent if used for any substantial amount +of text. A copy that is not \*(L"Transparent\*(R" is called \*(L"Opaque\*(R". +.Sp +Examples of suitable formats for Transparent copies include plain +\&\s-1ASCII\s0 without markup, Texinfo input format, LaTeX input +format, \s-1SGML\s0 or \s-1XML\s0 using a publicly available +\&\s-1DTD,\s0 and standard-conforming simple \s-1HTML,\s0 +PostScript or \s-1PDF\s0 designed for human modification. Examples +of transparent image formats include \s-1PNG, XCF\s0 and +\&\s-1JPG.\s0 Opaque formats include proprietary formats that can be +read and edited only by proprietary word processors, \s-1SGML\s0 or +\&\s-1XML\s0 for which the \s-1DTD\s0 and/or processing tools are +not generally available, and the machine-generated \s-1HTML,\s0 +PostScript or \s-1PDF\s0 produced by some word processors for +output purposes only. +.Sp +The \*(L"Title Page\*(R" means, for a printed book, the title page itself, +plus such following pages as are needed to hold, legibly, the material +this License requires to appear in the title page. For works in +formats which do not have any title page as such, \*(L"Title Page\*(R" means +the text near the most prominent appearance of the work's title, +preceding the beginning of the body of the text. +.Sp +The \*(L"publisher\*(R" means any person or entity that distributes copies +of the Document to the public. +.Sp +A section \*(L"Entitled \s-1XYZ\*(R"\s0 means a named subunit of the Document whose +title either is precisely \s-1XYZ\s0 or contains \s-1XYZ\s0 in parentheses following +text that translates \s-1XYZ\s0 in another language. (Here \s-1XYZ\s0 stands for a +specific section name mentioned below, such as \*(L"Acknowledgements\*(R", +\&\*(L"Dedications\*(R", \*(L"Endorsements\*(R", or \*(L"History\*(R".) To \*(L"Preserve the Title\*(R" +of such a section when you modify the Document means that it remains a +section \*(L"Entitled \s-1XYZ\*(R"\s0 according to this definition. +.Sp +The Document may include Warranty Disclaimers next to the notice which +states that this License applies to the Document. These Warranty +Disclaimers are considered to be included by reference in this +License, but only as regards disclaiming warranties: any other +implication that these Warranty Disclaimers may have is void and has +no effect on the meaning of this License. +.IP "2." 4 +.IX Item "2." +\&\s-1VERBATIM COPYING\s0 +.Sp +You may copy and distribute the Document in any medium, either +commercially or noncommercially, provided that this License, the +copyright notices, and the license notice saying this License applies +to the Document are reproduced in all copies, and that you add no other +conditions whatsoever to those of this License. You may not use +technical measures to obstruct or control the reading or further +copying of the copies you make or distribute. However, you may accept +compensation in exchange for copies. If you distribute a large enough +number of copies you must also follow the conditions in section 3. +.Sp +You may also lend copies, under the same conditions stated above, and +you may publicly display copies. +.IP "3." 4 +.IX Item "3." +\&\s-1COPYING IN QUANTITY\s0 +.Sp +If you publish printed copies (or copies in media that commonly have +printed covers) of the Document, numbering more than 100, and the +Document's license notice requires Cover Texts, you must enclose the +copies in covers that carry, clearly and legibly, all these Cover +Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on +the back cover. Both covers must also clearly and legibly identify +you as the publisher of these copies. The front cover must present +the full title with all words of the title equally prominent and +visible. You may add other material on the covers in addition. +Copying with changes limited to the covers, as long as they preserve +the title of the Document and satisfy these conditions, can be treated +as verbatim copying in other respects. +.Sp +If the required texts for either cover are too voluminous to fit +legibly, you should put the first ones listed (as many as fit +reasonably) on the actual cover, and continue the rest onto adjacent +pages. +.Sp +If you publish or distribute Opaque copies of the Document numbering +more than 100, you must either include a machine-readable Transparent +copy along with each Opaque copy, or state in or with each Opaque copy +a computer-network location from which the general network-using +public has access to download using public-standard network protocols +a complete Transparent copy of the Document, free of added material. +If you use the latter option, you must take reasonably prudent steps, +when you begin distribution of Opaque copies in quantity, to ensure +that this Transparent copy will remain thus accessible at the stated +location until at least one year after the last time you distribute an +Opaque copy (directly or through your agents or retailers) of that +edition to the public. +.Sp +It is requested, but not required, that you contact the authors of the +Document well before redistributing any large number of copies, to give +them a chance to provide you with an updated version of the Document. +.IP "4." 4 +.IX Item "4." +\&\s-1MODIFICATIONS\s0 +.Sp +You may copy and distribute a Modified Version of the Document under +the conditions of sections 2 and 3 above, provided that you release +the Modified Version under precisely this License, with the Modified +Version filling the role of the Document, thus licensing distribution +and modification of the Modified Version to whoever possesses a copy +of it. In addition, you must do these things in the Modified Version: +.RS 4 +.IP "A." 4 +.IX Item "A." +Use in the Title Page (and on the covers, if any) a title distinct +from that of the Document, and from those of previous versions +(which should, if there were any, be listed in the History section +of the Document). You may use the same title as a previous version +if the original publisher of that version gives permission. +.IP "B." 4 +.IX Item "B." +List on the Title Page, as authors, one or more persons or entities +responsible for authorship of the modifications in the Modified +Version, together with at least five of the principal authors of the +Document (all of its principal authors, if it has fewer than five), +unless they release you from this requirement. +.IP "C." 4 +.IX Item "C." +State on the Title page the name of the publisher of the +Modified Version, as the publisher. +.IP "D." 4 +.IX Item "D." +Preserve all the copyright notices of the Document. +.IP "E." 4 +.IX Item "E." +Add an appropriate copyright notice for your modifications +adjacent to the other copyright notices. +.IP "F." 4 +.IX Item "F." +Include, immediately after the copyright notices, a license notice +giving the public permission to use the Modified Version under the +terms of this License, in the form shown in the Addendum below. +.IP "G." 4 +.IX Item "G." +Preserve in that license notice the full lists of Invariant Sections +and required Cover Texts given in the Document's license notice. +.IP "H." 4 +.IX Item "H." +Include an unaltered copy of this License. +.IP "I." 4 +.IX Item "I." +Preserve the section Entitled \*(L"History\*(R", Preserve its Title, and add +to it an item stating at least the title, year, new authors, and +publisher of the Modified Version as given on the Title Page. If +there is no section Entitled \*(L"History\*(R" in the Document, create one +stating the title, year, authors, and publisher of the Document as +given on its Title Page, then add an item describing the Modified +Version as stated in the previous sentence. +.IP "J." 4 +.IX Item "J." +Preserve the network location, if any, given in the Document for +public access to a Transparent copy of the Document, and likewise +the network locations given in the Document for previous versions +it was based on. These may be placed in the \*(L"History\*(R" section. +You may omit a network location for a work that was published at +least four years before the Document itself, or if the original +publisher of the version it refers to gives permission. +.IP "K." 4 +.IX Item "K." +For any section Entitled \*(L"Acknowledgements\*(R" or \*(L"Dedications\*(R", Preserve +the Title of the section, and preserve in the section all the +substance and tone of each of the contributor acknowledgements and/or +dedications given therein. +.IP "L." 4 +.IX Item "L." +Preserve all the Invariant Sections of the Document, +unaltered in their text and in their titles. Section numbers +or the equivalent are not considered part of the section titles. +.IP "M." 4 +.IX Item "M." +Delete any section Entitled \*(L"Endorsements\*(R". Such a section +may not be included in the Modified Version. +.IP "N." 4 +.IX Item "N." +Do not retitle any existing section to be Entitled \*(L"Endorsements\*(R" or +to conflict in title with any Invariant Section. +.IP "O." 4 +.IX Item "O." +Preserve any Warranty Disclaimers. +.RE +.RS 4 +.Sp +If the Modified Version includes new front-matter sections or +appendices that qualify as Secondary Sections and contain no material +copied from the Document, you may at your option designate some or all +of these sections as invariant. To do this, add their titles to the +list of Invariant Sections in the Modified Version's license notice. +These titles must be distinct from any other section titles. +.Sp +You may add a section Entitled \*(L"Endorsements\*(R", provided it contains +nothing but endorsements of your Modified Version by various +parties\-\-\-for example, statements of peer review or that the text has +been approved by an organization as the authoritative definition of a +standard. +.Sp +You may add a passage of up to five words as a Front-Cover Text, and a +passage of up to 25 words as a Back-Cover Text, to the end of the list +of Cover Texts in the Modified Version. Only one passage of +Front-Cover Text and one of Back-Cover Text may be added by (or +through arrangements made by) any one entity. If the Document already +includes a cover text for the same cover, previously added by you or +by arrangement made by the same entity you are acting on behalf of, +you may not add another; but you may replace the old one, on explicit +permission from the previous publisher that added the old one. +.Sp +The author(s) and publisher(s) of the Document do not by this License +give permission to use their names for publicity for or to assert or +imply endorsement of any Modified Version. +.RE +.IP "5." 4 +.IX Item "5." +\&\s-1COMBINING DOCUMENTS\s0 +.Sp +You may combine the Document with other documents released under this +License, under the terms defined in section 4 above for modified +versions, provided that you include in the combination all of the +Invariant Sections of all of the original documents, unmodified, and +list them all as Invariant Sections of your combined work in its +license notice, and that you preserve all their Warranty Disclaimers. +.Sp +The combined work need only contain one copy of this License, and +multiple identical Invariant Sections may be replaced with a single +copy. If there are multiple Invariant Sections with the same name but +different contents, make the title of each such section unique by +adding at the end of it, in parentheses, the name of the original +author or publisher of that section if known, or else a unique number. +Make the same adjustment to the section titles in the list of +Invariant Sections in the license notice of the combined work. +.Sp +In the combination, you must combine any sections Entitled \*(L"History\*(R" +in the various original documents, forming one section Entitled +\&\*(L"History\*(R"; likewise combine any sections Entitled \*(L"Acknowledgements\*(R", +and any sections Entitled \*(L"Dedications\*(R". You must delete all +sections Entitled \*(L"Endorsements.\*(R" +.IP "6." 4 +.IX Item "6." +\&\s-1COLLECTIONS OF DOCUMENTS\s0 +.Sp +You may make a collection consisting of the Document and other documents +released under this License, and replace the individual copies of this +License in the various documents with a single copy that is included in +the collection, provided that you follow the rules of this License for +verbatim copying of each of the documents in all other respects. +.Sp +You may extract a single document from such a collection, and distribute +it individually under this License, provided you insert a copy of this +License into the extracted document, and follow this License in all +other respects regarding verbatim copying of that document. +.IP "7." 4 +.IX Item "7." +\&\s-1AGGREGATION WITH INDEPENDENT WORKS\s0 +.Sp +A compilation of the Document or its derivatives with other separate +and independent documents or works, in or on a volume of a storage or +distribution medium, is called an \*(L"aggregate\*(R" if the copyright +resulting from the compilation is not used to limit the legal rights +of the compilation's users beyond what the individual works permit. +When the Document is included in an aggregate, this License does not +apply to the other works in the aggregate which are not themselves +derivative works of the Document. +.Sp +If the Cover Text requirement of section 3 is applicable to these +copies of the Document, then if the Document is less than one half of +the entire aggregate, the Document's Cover Texts may be placed on +covers that bracket the Document within the aggregate, or the +electronic equivalent of covers if the Document is in electronic form. +Otherwise they must appear on printed covers that bracket the whole +aggregate. +.IP "8." 4 +.IX Item "8." +\&\s-1TRANSLATION\s0 +.Sp +Translation is considered a kind of modification, so you may +distribute translations of the Document under the terms of section 4. +Replacing Invariant Sections with translations requires special +permission from their copyright holders, but you may include +translations of some or all Invariant Sections in addition to the +original versions of these Invariant Sections. You may include a +translation of this License, and all the license notices in the +Document, and any Warranty Disclaimers, provided that you also include +the original English version of this License and the original versions +of those notices and disclaimers. In case of a disagreement between +the translation and the original version of this License or a notice +or disclaimer, the original version will prevail. +.Sp +If a section in the Document is Entitled \*(L"Acknowledgements\*(R", +\&\*(L"Dedications\*(R", or \*(L"History\*(R", the requirement (section 4) to Preserve +its Title (section 1) will typically require changing the actual +title. +.IP "9." 4 +.IX Item "9." +\&\s-1TERMINATION\s0 +.Sp +You may not copy, modify, sublicense, or distribute the Document +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense, or distribute it is void, and +will automatically terminate your rights under this License. +.Sp +However, if you cease all violation of this License, then your license +from a particular copyright holder is reinstated (a) provisionally, +unless and until the copyright holder explicitly and finally +terminates your license, and (b) permanently, if the copyright holder +fails to notify you of the violation by some reasonable means prior to +60 days after the cessation. +.Sp +Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. +.Sp +Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, receipt of a copy of some or all of the same material does +not give you any rights to use it. +.IP "10." 4 +.IX Item "10." +\&\s-1FUTURE REVISIONS OF THIS LICENSE\s0 +.Sp +The Free Software Foundation may publish new, revised versions +of the \s-1GNU\s0 Free Documentation License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. See +<\fBhttp://www.gnu.org/copyleft/\fR>. +.Sp +Each version of the License is given a distinguishing version number. +If the Document specifies that a particular numbered version of this +License \*(L"or any later version\*(R" applies to it, you have the option of +following the terms and conditions either of that specified version or +of any later version that has been published (not as a draft) by the +Free Software Foundation. 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A copy of the license is included in the section entitled "GNU +\& Free Documentation License". +.Ve +.PP +If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, +replace the \*(L"with...Texts.\*(R" line with this: +.PP +.Vb 3 +\& with the Invariant Sections being , with +\& the Front\-Cover Texts being , and with the Back\-Cover Texts +\& being . +.Ve +.PP +If you have Invariant Sections without Cover Texts, or some other +combination of the three, merge those two alternatives to suit the +situation. +.PP +If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the \s-1GNU\s0 General Public License, +to permit their use in free software. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIfsf\-funding\fR\|(7). +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. +<\fBhttp://fsf.org/\fR> +.PP +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. diff --git a/man/man7/gpl.7 b/man/man7/gpl.7 new file mode 100644 index 0000000000000000000000000000000000000000..8c0e2bdd478b4bc9488e50890c5d7d6ec4ff5854 --- /dev/null +++ b/man/man7/gpl.7 @@ -0,0 +1,846 @@ +.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. 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Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gpl \- GNU General Public License +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +.SS "\s-1GNU\s0 General Public License" +.IX Subsection "GNU General Public License" +.SS "Version 3, 29 June 2007" +.IX Subsection "Version 3, 29 June 2007" +.Vb 1 +\& Copyright (c) 2007 Free Software Foundation, Inc. +\& +\& Everyone is permitted to copy and distribute verbatim copies of this +\& license document, but changing it is not allowed. +.Ve +.SS "Preamble" +.IX Subsection "Preamble" +The \s-1GNU\s0 General Public License is a free, copyleft license for +software and other kinds of works. +.PP +The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Of course, your +program's commands might be different; for a \s-1GUI\s0 interface, you would +use an \*(L"about box\*(R". +.PP +You should also get your employer (if you work as a programmer) or school, +if any, to sign a \*(L"copyright disclaimer\*(R" for the program, if necessary. +For more information on this, and how to apply and follow the \s-1GNU GPL,\s0 see +<\fBhttp://www.gnu.org/licenses/\fR>. +.PP +The \s-1GNU\s0 General Public License does not permit incorporating your +program into proprietary programs. If your program is a subroutine +library, you may consider it more useful to permit linking proprietary +applications with the library. If this is what you want to do, use +the \s-1GNU\s0 Lesser General Public License instead of this License. But +first, please read <\fBhttp://www.gnu.org/philosophy/why\-not\-lgpl.html\fR>. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7). +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2007 Free Software Foundation, Inc. +.PP +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. diff --git a/man/man7/io_uring.7 b/man/man7/io_uring.7 new file mode 100644 index 0000000000000000000000000000000000000000..19714db566c39ba10a98404264e274398a50cc8a --- /dev/null +++ b/man/man7/io_uring.7 @@ -0,0 +1,864 @@ +.\" Copyright (C) 2020 Shuveb Hussain +.\" SPDX-License-Identifier: LGPL-2.0-or-later +.\" + +.TH io_uring 7 2020-07-26 "Linux" "Linux Programmer's Manual" +.SH NAME +io_uring \- Asynchronous I/O facility +.SH SYNOPSIS +.nf +.B "#include " +.fi +.PP +.SH DESCRIPTION +.PP +.B io_uring +is a Linux-specific API for asynchronous I/O. +It allows the user to submit one or more I/O requests, +which are processed asynchronously without blocking the calling process. +.B io_uring +gets its name from ring buffers which are shared between user space and +kernel space. This arrangement allows for efficient I/O, +while avoiding the overhead of copying buffers between them, +where possible. +This interface makes +.B io_uring +different from other UNIX I/O APIs, +wherein, +rather than just communicate between kernel and user space with system calls, +ring buffers are used as the main mode of communication. +This arrangement has various performance benefits which are discussed in a +separate section below. +This man page uses the terms shared buffers, shared ring buffers and +queues interchangeably. +.PP +The general programming model you need to follow for +.B io_uring +is outlined below +.IP \(bu +Set up shared buffers with +.BR io_uring_setup (2) +and +.BR mmap (2), +mapping into user space shared buffers for the submission queue (SQ) and the +completion queue (CQ). +You place I/O requests you want to make on the SQ, +while the kernel places the results of those operations on the CQ. +.IP \(bu +For every I/O request you need to make (like to read a file, write a file, +accept a socket connection, etc), you create a submission queue entry, +or SQE, +describe the I/O operation you need to get done and add it to the tail of +the submission queue (SQ). +Each I/O operation is, +in essence, +the equivalent of a system call you would have made otherwise, +if you were not using +.BR io_uring . +For instance, +a SQE with the +.I opcode +set to +.B IORING_OP_READ +will request a read operation to be issued that is similar to the +.BR read (2) +system call. Refer to the opcode documentation in +.BR io_uring_enter (2) +for all supported opcodes and their properties. +You can add more than one SQE to the queue depending on the number of +operations you want to request. +.IP \(bu +After you add one or more SQEs, +you need to call +.BR io_uring_enter (2) +to tell the kernel to dequeue your I/O requests off the SQ and begin +processing them. +.IP \(bu +For each SQE you submit, +once it is done processing the request, +the kernel places a completion queue event or CQE at the tail of the +completion queue or CQ. +The kernel places exactly one matching CQE in the CQ for every SQE you +submit on the SQ. +After you retrieve a CQE, +minimally, +you might be interested in checking the +.I res +field of the CQE structure, +which corresponds to the return value of the system +call's equivalent, +had you used it directly without using +.BR io_uring . +Given that +.B io_uring +is an async interface, +.I errno +is never used for passing back error information. Instead, +.I res +will contain what the equivalent system call would have returned in case +of success, and in case of error +.I res +will contain +.IR -errno . +For example, if the normal read system call would have returned -1 and set +.I errno +to +.BR EINVAL , +then +.I res +would contain +.BR -EINVAL . +If the normal system call would have returned a read size of 1024, then +.I res +would contain 1024. +.IP \(bu +Optionally, +.BR io_uring_enter (2) +can also wait for a specified number of requests to be processed by the kernel +before it returns. +If you specified a certain number of completions to wait for, +the kernel would have placed at least those many number of CQEs on the CQ, +which you can then readily read, +right after the return from +.BR io_uring_enter (2). +.IP \(bu +It is important to remember that I/O requests submitted to the kernel can +complete in any order. +It is not necessary for the kernel to process one request after another, +in the order you placed them. +Given that the interface is a ring, +the requests are attempted in order, +however that doesn't imply any sort of ordering on their execution or +completion. +When more than one request is in flight, +it is not possible to determine which one will execute or complete first. +When you dequeue CQEs off the CQ, +you should always check which submitted request it corresponds to. +The most common method for doing so is utilizing the +.I user_data +field in the request, which is passed back on the completion side. +.IP \(bu +Concretely, for operations where strict ordering is required, +such as for sends and receives on a stream-oriented TCP socket, +it is generally unsafe to have more than one outstanding send, +or more than one outstanding receive (the two directions are independent) +on a given socket at a time, as the kernel may reorder their execution +if poll arming or other background kernel activities are involved. +However, +.B io_uring +provides various facilities to enable applications to efficiently +pipeline their operations safely. If the requests are submitted in a +single batch, the application may use +.B IOSQE_IO_LINK +to enforce an execution order in the kernel. Otherwise, +.B io_uring +provides advanced features like +.I multi shot +and send/receive +.I bundles +to allow applications to provide more data in fewer, more efficient trips +to the kernel. Even if these features are used, applications must still +ensure they do not overlap different sends or different receives on a +given file. +.PP +Adding to and reading from the queues: +.IP \(bu +You add SQEs to the tail of the SQ. +The kernel reads SQEs off the head of the queue. +.IP \(bu +The kernel adds CQEs to the tail of the CQ. +You read CQEs off the head of the queue. +.PP +It should be noted that depending on the configuration io_uring's behavior +can deviate from the behavior outlined above, like not posting a CQE for +every SQE when setting +.B IOSQE_CQE_SKIP_SUCCESS +in the SQE or posting multiple CQEs for a single SQE for multi shot operations +or requiring an +.BR io_uring_enter (2) +syscall to make the kernel begin processing newly added SQEs when using +submission queue polling. + +.SS Submission queue polling +One of the goals of +.B io_uring +is to provide a means for efficient I/O. +To this end, +.B io_uring +supports a polling mode that lets you avoid the call to +.BR io_uring_enter (2), +which you use to inform the kernel that you have queued SQEs on to the SQ. +With SQ Polling, +.B io_uring +starts a kernel thread that polls the submission queue for any I/O +requests you submit by adding SQEs. +With SQ Polling enabled, +there is no need for you to call +.BR io_uring_enter (2), +letting you avoid the overhead of system calls. +A designated kernel thread dequeues SQEs off the SQ as you add them and +dispatches them for asynchronous processing. +.SS Setting up io_uring +.PP +The main steps in setting up +.B io_uring +consist of mapping in the shared buffers with +.BR mmap (2) +calls. +In the example program included in this man page, +the function +.BR app_setup_uring () +sets up +.B io_uring +with a QUEUE_DEPTH deep submission queue. +Pay attention to the 2 +.BR mmap (2) +calls that set up the shared submission and completion queues. +If your kernel is older than version 5.4, +three +.BR mmap(2) +calls are required. +.PP +.SS Submitting I/O requests +The process of submitting a request consists of describing the I/O +operation you need to get done using an +.B io_uring_sqe +structure instance. +These details describe the equivalent system call and its parameters. +Because the range of I/O operations Linux supports are very varied and the +.B io_uring_sqe +structure needs to be able to describe them, +it has several fields, +some packed into unions for space efficiency. +Here is a simplified version of struct +.B io_uring_sqe +with some of the most often used fields: +.PP +.in +4n +.EX +struct io_uring_sqe { + __u8 opcode; /* type of operation for this sqe */ + __s32 fd; /* file descriptor to do IO on */ + __u64 off; /* offset into file */ + __u64 addr; /* pointer to buffer or iovecs */ + __u32 len; /* buffer size or number of iovecs */ + __u64 user_data; /* data to be passed back at completion time */ + __u8 flags; /* IOSQE_ flags */ + ... +}; +.EE +.in + +Here is struct +.B io_uring_sqe +in full: + +.in +4n +.EX +struct io_uring_sqe { + __u8 opcode; /* type of operation for this sqe */ + __u8 flags; /* IOSQE_ flags */ + __u16 ioprio; /* ioprio for the request */ + __s32 fd; /* file descriptor to do IO on */ + union { + __u64 off; /* offset into file */ + __u64 addr2; + struct { + __u32 cmd_op; + __u32 __pad1; + }; + }; + union { + __u64 addr; /* pointer to buffer or iovecs */ + __u64 splice_off_in; + struct { + __u32 level; + __u32 optname; + }; + }; + __u32 len; /* buffer size or number of iovecs */ + union { + __kernel_rwf_t rw_flags; + __u32 fsync_flags; + __u16 poll_events; /* compatibility */ + __u32 poll32_events; /* word-reversed for BE */ + __u32 sync_range_flags; + __u32 msg_flags; + __u32 timeout_flags; + __u32 accept_flags; + __u32 cancel_flags; + __u32 open_flags; + __u32 statx_flags; + __u32 fadvise_advice; + __u32 splice_flags; + __u32 rename_flags; + __u32 unlink_flags; + __u32 hardlink_flags; + __u32 xattr_flags; + __u32 msg_ring_flags; + __u32 uring_cmd_flags; + __u32 waitid_flags; + __u32 futex_flags; + __u32 install_fd_flags; + __u32 nop_flags; + }; + __u64 user_data; /* data to be passed back at completion time */ + /* pack this to avoid bogus arm OABI complaints */ + union { + /* index into fixed buffers, if used */ + __u16 buf_index; + /* for grouped buffer selection */ + __u16 buf_group; + } __attribute__((packed)); + /* personality to use, if used */ + __u16 personality; + union { + __s32 splice_fd_in; + __u32 file_index; + __u32 optlen; + struct { + __u16 addr_len; + __u16 __pad3[1]; + }; + }; + union { + struct { + __u64 addr3; + __u64 __pad2[1]; + }; + __u64 optval; + /* + * If the ring is initialized with IORING_SETUP_SQE128, then + * this field is used for 80 bytes of arbitrary command data + */ + __u8 cmd[0]; + }; +}; +.EE +.in +.PP +To submit an I/O request to +.BR io_uring , +you need to acquire a submission queue entry (SQE) from the submission +queue (SQ), +fill it up with details of the operation you want to submit and call +.BR io_uring_enter (2). +There are helper functions of the form io_uring_prep_X to enable proper +setup of the SQE. If you want to avoid calling +.BR io_uring_enter (2), +you have the option of setting up Submission Queue Polling. +.PP +SQEs are added to the tail of the submission queue. +The kernel picks up SQEs off the head of the SQ. +The general algorithm to get the next available SQE and update the tail is +as follows. +.PP +.in +4n +.EX +struct io_uring_sqe *sqe; +unsigned tail, index; +tail = *sqring->tail; +index = tail & (*sqring->ring_mask); +sqe = &sqring->sqes[index]; +/* fill up details about this I/O request */ +describe_io(sqe); +/* fill the sqe index into the SQ ring array */ +sqring->array[index] = index; +tail++; +atomic_store_explicit(sqring->tail, tail, memory_order_release); +.EE +.in +.PP +To get the index of an entry, +the application must mask the current tail index with the size mask of the +ring. +This holds true for both SQs and CQs. +Once the SQE is acquired, +the necessary fields are filled in, +describing the request. +While the CQ ring directly indexes the shared array of CQEs, +the submission side has an indirection array between them. +The submission side ring buffer is an index into this array, +which in turn contains the index into the SQEs. +.PP +The following code snippet demonstrates how a read operation, +an equivalent of a +.BR preadv2 (2) +system call is described by filling up an SQE with the necessary +parameters. +.PP +.in +4n +.EX +struct iovec iovecs[16]; + ... +sqe->opcode = IORING_OP_READV; +sqe->fd = fd; +sqe->addr = (unsigned long) iovecs; +sqe->len = 16; +sqe->off = offset; +sqe->flags = 0; +.EE +.in +.TP +.B Memory ordering +Modern compilers and CPUs freely reorder reads and writes without +affecting the program's outcome to optimize performance. +Some aspects of this need to be kept in mind on SMP systems since +.B io_uring +involves buffers shared between kernel and user space. +These buffers are both visible and modifiable from kernel and user space. +As heads and tails belonging to these shared buffers are updated by kernel +and user space, +changes need to be coherently visible on either side, +irrespective of whether a CPU switch took place after the kernel-user mode +switch happened. +We use memory barriers to enforce this coherency. +Being significantly large subjects on their own, +memory barriers are out of scope for further discussion on this man page. +For more information on modern memory models the reader may refer to the +Documentation/memory-barriers.txt in the kernel tree or to the documentation +of the formal C11 or kernel memory model. +.TP +.B Letting the kernel know about I/O submissions +Once you place one or more SQEs on to the SQ, +you need to let the kernel know that you've done so. +You can do this by calling the +.BR io_uring_enter (2) +system call. +This system call is also capable of waiting for a specified count of +events to complete. +This way, +you can be sure to find completion events in the completion queue without +having to poll it for events later. +.SS Reading completion events +Similar to the submission queue (SQ), +the completion queue (CQ) is a shared buffer between the kernel and user +space. +Whereas you placed submission queue entries on the tail of the SQ and the +kernel read off the head, +when it comes to the CQ, +the kernel places completion queue events or CQEs on the tail of the CQ and +you read off its head. +.PP +Submission is flexible (and thus a bit more complicated) since it needs to +be able to encode different types of system calls that take various +parameters. +Completion, +on the other hand is simpler since we're looking only for a return value +back from the kernel. +This is easily understood by looking at the completion queue event +structure, +struct +.BR io_uring_cqe : +.PP +.in +4n +.EX +struct io_uring_cqe { + __u64 user_data; /* sqe->data submission passed back */ + __s32 res; /* result code for this event */ + __u32 flags; +}; +.EE +.in +.PP +Here, +.I user_data +is custom data that is passed unchanged from submission to completion. +That is, +from SQEs to CQEs. +This field can be used to set context, +uniquely identifying submissions that got completed. +Given that I/O requests can complete in any order, +this field can be used to correlate a submission with a completion. +.I res +is the result from the system call that was performed as part of the +submission; +its return value. + +The +.I flags +field carries request-specific information. As of the 6.12 kernel, +the following flags are defined: + +.TP +.B IORING_CQE_F_BUFFER +If set, the upper 16 bits of the flags field carries the buffer ID that was +chosen for this request. The request must have been issued with +.B IOSQE_BUFFER_SELECT +set, and used with a request type that supports buffer selection. Additionally, +buffers must have been provided upfront either via the +.B IORING_OP_PROVIDE_BUFFERS +or the +.B IORING_REGISTER_PBUF_RING +methods. +.TP +.B IORING_CQE_F_MORE +If set, the application should expect more completions from the request. This +is used for requests that can generate multiple completions, such as multi-shot +requests, receive, or accept. +.TP +.B IORING_CQE_F_SOCK_NONEMPTY +If set, upon receiving the data from the socket in the current request, the +socket still had data left on completion of this request. +.TP +.B IORING_CQE_F_NOTIF +Set for notification CQEs, as seen with the zero-copy networking send and +receive support. +.TP +.B IORING_CQE_F_BUF_MORE +If set, the buffer ID set in the completion will get more completions. This +means that the provided buffer has been partially consumed and there's more +buffer space left, and hence the application should expect more completions +with this buffer ID. Each completion will continue where the previous one +left off. This can only happen if the provided buffer ring has been setup +with +.B IOU_PBUF_RING_INC +to allow for incremental / partial consumption of buffers. +.PP +The general sequence to read completion events off the completion queue is +as follows: +.PP +.in +4n +.EX +unsigned head; +head = *cqring->head; +if (head != atomic_load_acquire(cqring->tail)) { + struct io_uring_cqe *cqe; + unsigned index; + index = head & (cqring->mask); + cqe = &cqring->cqes[index]; + /* process completed CQE */ + process_cqe(cqe); + /* CQE consumption complete */ + head++; +} +atomic_store_explicit(cqring->head, head, memory_order_release); +.EE +.in +.PP +It helps to be reminded that the kernel adds CQEs to the tail of the CQ, +while you need to dequeue them off the head. +To get the index of an entry at the head, +the application must mask the current head index with the size mask of the +ring. +Once the CQE has been consumed or processed, +the head needs to be updated to reflect the consumption of the CQE. +Attention should be paid to the read and write barriers to ensure +successful read and update of the head. +.SS io_uring performance +Because of the shared ring buffers between kernel and user space, +.B io_uring +can be a zero-copy system. +Copying buffers to and from becomes necessary when system calls that +transfer data between kernel and user space are involved. +But since the bulk of the communication in +.B io_uring +is via buffers shared between the kernel and user space, +this huge performance overhead is completely avoided. +.PP +While system calls may not seem like a significant overhead, +in high performance applications, +making a lot of them will begin to matter. +While workarounds the operating system has in place to deal with Spectre +and Meltdown are ideally best done away with, +unfortunately, +some of these workarounds are around the system call interface, +making system calls not as cheap as before on affected hardware. +While newer hardware should not need these workarounds, +hardware with these vulnerabilities can be expected to be in the wild for a +long time. +While using synchronous programming interfaces or even when using +asynchronous programming interfaces under Linux, +there is at least one system call involved in the submission of each +request. +In +.BR io_uring , +on the other hand, +you can batch several requests in one go, +simply by queueing up multiple SQEs, +each describing an I/O operation you want and make a single call to +.BR io_uring_enter (2). +This is possible due to +.BR io_uring 's +shared buffers based design. +.PP +While this batching in itself can avoid the overhead associated with +potentially multiple and frequent system calls, +you can reduce even this overhead further with Submission Queue Polling, +by having the kernel poll and pick up your SQEs for processing as you add +them to the submission queue. This avoids the +.BR io_uring_enter (2) +call you need to make to tell the kernel to pick SQEs up. +For high-performance applications, +this means even fewer system call overheads. +.SH CONFORMING TO +.B io_uring +is Linux-specific. +.SH EXAMPLES +The following example uses +.B io_uring +to copy stdin to stdout. +Using shell redirection, +you should be able to copy files with this example. +Because it uses a queue depth of only one, +this example processes I/O requests one after the other. +It is purposefully kept this way to aid understanding. +In real-world scenarios however, +you'll want to have a larger queue depth to parallelize I/O request +processing so as to gain the kind of performance benefits +.B io_uring +provides with its asynchronous processing of requests. +.PP +.EX +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define QUEUE_DEPTH 1 +#define BLOCK_SZ 1024 + +/* Macros for barriers needed by io_uring */ +#define io_uring_smp_store_release(p, v) \\ + atomic_store_explicit((_Atomic typeof(*(p)) *)(p), (v), \\ + memory_order_release) +#define io_uring_smp_load_acquire(p) \\ + atomic_load_explicit((_Atomic typeof(*(p)) *)(p), \\ + memory_order_acquire) + +int ring_fd; +unsigned *sring_tail, *sring_mask, *sring_array, + *cring_head, *cring_tail, *cring_mask; +struct io_uring_sqe *sqes; +struct io_uring_cqe *cqes; +char buff[BLOCK_SZ]; +off_t offset; + +/* + * System call wrappers provided since glibc does not yet + * provide wrappers for io_uring system calls. +* */ + +int io_uring_setup(unsigned entries, struct io_uring_params *p) +{ + int ret; + ret = syscall(__NR_io_uring_setup, entries, p); + return (ret < 0) ? -errno : ret; +} + +int io_uring_enter(int ring_fd, unsigned int to_submit, + unsigned int min_complete, unsigned int flags) +{ + int ret; + ret = syscall(__NR_io_uring_enter, ring_fd, to_submit, + min_complete, flags, NULL, 0); + return (ret < 0) ? -errno : ret; +} + +int app_setup_uring(void) { + struct io_uring_params p; + void *sq_ptr, *cq_ptr; + + /* See io_uring_setup(2) for io_uring_params.flags you can set */ + memset(&p, 0, sizeof(p)); + ring_fd = io_uring_setup(QUEUE_DEPTH, &p); + if (ring_fd < 0) { + perror("io_uring_setup"); + return 1; + } + + /* + * io_uring communication happens via 2 shared kernel-user space ring + * buffers, which can be jointly mapped with a single mmap() call in + * kernels >= 5.4. + */ + + int sring_sz = p.sq_off.array + p.sq_entries * sizeof(unsigned); + int cring_sz = p.cq_off.cqes + p.cq_entries * sizeof(struct io_uring_cqe); + + /* Rather than check for kernel version, the recommended way is to + * check the features field of the io_uring_params structure, which is a + * bitmask. If IORING_FEAT_SINGLE_MMAP is set, we can do away with the + * second mmap() call to map in the completion ring separately. + */ + if (p.features & IORING_FEAT_SINGLE_MMAP) { + if (cring_sz > sring_sz) + sring_sz = cring_sz; + cring_sz = sring_sz; + } + + /* Map in the submission and completion queue ring buffers. + * Kernels < 5.4 only map in the submission queue, though. + */ + sq_ptr = mmap(0, sring_sz, PROT_READ | PROT_WRITE, + MAP_SHARED | MAP_POPULATE, + ring_fd, IORING_OFF_SQ_RING); + if (sq_ptr == MAP_FAILED) { + perror("mmap"); + return 1; + } + + if (p.features & IORING_FEAT_SINGLE_MMAP) { + cq_ptr = sq_ptr; + } else { + /* Map in the completion queue ring buffer in older kernels separately */ + cq_ptr = mmap(0, cring_sz, PROT_READ | PROT_WRITE, + MAP_SHARED | MAP_POPULATE, + ring_fd, IORING_OFF_CQ_RING); + if (cq_ptr == MAP_FAILED) { + perror("mmap"); + return 1; + } + } + /* Save useful fields for later easy reference */ + sring_tail = sq_ptr + p.sq_off.tail; + sring_mask = sq_ptr + p.sq_off.ring_mask; + sring_array = sq_ptr + p.sq_off.array; + + /* Map in the submission queue entries array */ + sqes = mmap(0, p.sq_entries * sizeof(struct io_uring_sqe), + PROT_READ | PROT_WRITE, MAP_SHARED | MAP_POPULATE, + ring_fd, IORING_OFF_SQES); + if (sqes == MAP_FAILED) { + perror("mmap"); + return 1; + } + + /* Save useful fields for later easy reference */ + cring_head = cq_ptr + p.cq_off.head; + cring_tail = cq_ptr + p.cq_off.tail; + cring_mask = cq_ptr + p.cq_off.ring_mask; + cqes = cq_ptr + p.cq_off.cqes; + + return 0; +} + +/* +* Read from completion queue. +* In this function, we read completion events from the completion queue. +* We dequeue the CQE, update and head and return the result of the operation. +* */ + +int read_from_cq() { + struct io_uring_cqe *cqe; + unsigned head; + + /* Read barrier */ + head = io_uring_smp_load_acquire(cring_head); + /* + * Remember, this is a ring buffer. If head == tail, it means that the + * buffer is empty. + * */ + if (head == *cring_tail) + return -1; + + /* Get the entry */ + cqe = &cqes[head & (*cring_mask)]; + if (cqe->res < 0) + fprintf(stderr, "Error: %s\\n", strerror(abs(cqe->res))); + + head++; + + /* Write barrier so that update to the head are made visible */ + io_uring_smp_store_release(cring_head, head); + + return cqe->res; +} + +/* +* Submit a read or a write request to the submission queue. +* */ + +int submit_to_sq(int fd, int op) { + unsigned index, tail; + + /* Add our submission queue entry to the tail of the SQE ring buffer */ + tail = *sring_tail; + index = tail & *sring_mask; + struct io_uring_sqe *sqe = &sqes[index]; + /* Fill in the parameters required for the read or write operation */ + sqe->opcode = op; + sqe->fd = fd; + sqe->addr = (unsigned long) buff; + if (op == IORING_OP_READ) { + memset(buff, 0, sizeof(buff)); + sqe->len = BLOCK_SZ; + } + else { + sqe->len = strlen(buff); + } + sqe->off = offset; + + sring_array[index] = index; + tail++; + + /* Update the tail */ + io_uring_smp_store_release(sring_tail, tail); + + /* + * Tell the kernel we have submitted events with the io_uring_enter() + * system call. We also pass in the IORING_ENTER_GETEVENTS flag which + * causes the io_uring_enter() call to wait until min_complete + * (the 3rd param) events complete. + * */ + int ret = io_uring_enter(ring_fd, 1,1, + IORING_ENTER_GETEVENTS); + if(ret < 0) { + perror("io_uring_enter"); + return -1; + } + + return ret; +} + +int main(int argc, char *argv[]) { + int res; + + /* Setup io_uring for use */ + if(app_setup_uring()) { + fprintf(stderr, "Unable to setup uring!\\n"); + return 1; + } + + /* + * A while loop that reads from stdin and writes to stdout. + * Breaks on EOF. + */ + while (1) { + /* Initiate read from stdin and wait for it to complete */ + submit_to_sq(STDIN_FILENO, IORING_OP_READ); + /* Read completion queue entry */ + res = read_from_cq(); + if (res > 0) { + /* Read successful. Write to stdout. */ + submit_to_sq(STDOUT_FILENO, IORING_OP_WRITE); + read_from_cq(); + } else if (res == 0) { + /* reached EOF */ + break; + } + else if (res < 0) { + /* Error reading file */ + fprintf(stderr, "Error: %s\\n", strerror(abs(res))); + break; + } + offset += res; + } + + return 0; +} +.EE +.SH SEE ALSO +.BR io_uring_enter (2) +.BR io_uring_register (2) +.BR io_uring_setup (2)