# NOTICE: data sources and terms (002-hardware-verification-engineer)

This package redistributes public files collected for the task. Each file keeps its publisher's terms; its source, version, retrieval time, hash and licence note are in PROVENANCE.md.

The level instructions and the documents listed below are part of the task scenario; the organisations and people in them are fictional:

- `workspace/t2/soc/doc/firmware/profiling.md`
- `workspace/t1/soc/doc/integration/cpu_subsystem.md`
- `workspace/t1/soc/doc/meetings/2026-09-22_cpu-subsystem-sync.txt`
- `workspace/t1/soc/doc/meetings/2026-10-05_rtl-window-kickoff.txt`
- `workspace/t3/soc/doc/meetings/2026-10-09_cpu-subsystem-sync.txt`
- `workspace/t4/soc/doc/meetings/2026-10-14_security-review.txt`
- `workspace/t1/soc/doc/process/vendored_ip.md`
- `workspace/t5/soc/doc/pubs/drafts/erratum_minstret_draft0.txt`
- `workspace/t5/soc/doc/pubs/errata_style.md`
- `workspace/t5/soc/doc/pubs/product_lines.md`
- `workspace/t4/soc/doc/security/cpu_security_requirements.md`

## Publishers

- RISC-V International (riscv-non-isa/riscv-arch-test on GitHub): 2 files
- RISC-V International (riscv/riscv-compliance, now riscv-non-isa/riscv-arch-test, on GitHub): 665 files
- RISC-V International (riscv/riscv-isa-manual on GitHub): 2 files
- RISC-V International (riscv/riscv-isa-manual): 16 files
- RISC-V International (riscv/sail-riscv on GitHub): 2 files
- Verilator (verilator/verilator on GitHub): 2 files
- YosysHQ (YosysHQ/riscv-formal on GitHub): 1 file
- georgerennie/ibex (GitHub): 5 files
- lowRISC CIC (lowRISC/ibex on GitHub): 10431 files
- lowRISC CIC (lowRISC/opentitan on GitHub): 1613 files
- lowRISC/ibex (GitHub): 49 files
- lowRISC/opentitan (GitHub): 21 files
- lowRISC/riscv-isa-sim (GitHub): 3 files
- riscv-software-src/riscv-isa-sim (GitHub): 1 file