---
pretty_name: EngiBench PowerElectronics v1
license: cc-by-nc-sa-4.0
task_categories:
- tabular-regression
tags:
- engineering-design
- multi-objective-optimization
- circuit-simulation
- ngspice
- engibench
size_categories:
- 10K<n<100K
dataset_info:
  features:
  - name: dataset_schema_version
    dtype: int64
  - name: split
    dtype: string
  - name: source_index
    dtype: int64
  - name: design_sha256
    dtype: string
  - name: initial_design
    sequence: float64
  - name: v0_DcGain
    dtype: float64
  - name: v0_Voltage_Ripple
    dtype: float64
  - name: source_dataset_id
    dtype: string
  - name: source_dataset_revision
    dtype: string
  - name: problem_version
    dtype: int64
  - name: engibench_git_commit
    dtype: string
  - name: netlist_sha256
    dtype: string
  - name: simulator_version
    dtype: string
  - name: simulator_sha256
    dtype: string
  - name: simulator_platform_system
    dtype: string
  - name: simulator_platform_machine
    dtype: string
  - name: container_sha256
    dtype: string
  - name: output_voltage_mean
    dtype: float64
  - name: output_voltage_peak_to_peak
    dtype: float64
  - name: dc_gain
    dtype: float64
  - name: dc_gain_error
    dtype: float64
  - name: relative_voltage_ripple
    dtype: float64
  - name: simulation_valid
    dtype: bool
  - name: objectives_valid
    dtype: bool
  - name: simulation_status
    dtype: string
  - name: error_type
    dtype: string
  - name: error_message
    dtype: string
  splits:
  - name: train
    num_bytes: 6682584
    num_examples: 9676
  - name: val
    num_bytes: 1904125
    num_examples: 2765
  - name: test
    num_bytes: 953783
    num_examples: 1383
  download_size: 2536603
  dataset_size: 9540492
configs:
- config_name: default
  data_files:
  - split: train
    path: data/train-*.parquet
  - split: val
    path: data/val-*.parquet
  - split: test
    path: data/test-*.parquet
---

# EngiBench PowerElectronics v1

PowerElectronics v1 is a simulator-frozen EngiBench dataset for data-driven
engineering design. It re-simulates the exact 13,824 input designs and preserves
the train/validation/test membership from
[`IDEALLab/power_electronics_v0`](https://huggingface.co/datasets/IDEALLab/power_electronics_v0),
but it is a **new benchmark** and does not claim to reproduce the v0 labels.

The canonical backend is ngspice 44.2 on Linux x86_64 in a pinned Apptainer
image. v1 corrects the objective semantics, retains signed physical
measurements, and records the source, code, netlist, simulator, and container
fingerprints in every row.

## Loading

Pin the release tag in reproducible experiments:

```python
from datasets import load_dataset

dataset = load_dataset(
    "IDEALLab/power_electronics_v1",
    revision="v1.0.0",
)
```

## Splits and simulation status

| Split | Rows | Status |
| --- | ---: | --- |
| train | 9,676 | 9,674 `ok`; 2 `invalid_measurements` |
| validation (`val`) | 2,765 | 2,764 `ok`; 1 `invalid_measurements` |
| test | 1,383 | 1,383 `ok` |

The possible `simulation_status` values are:

| Status | Measurement and objective fields | Validity flags |
| --- | --- | --- |
| `ok` | Signed measurements and both objectives are finite. | `simulation_valid=true`, `objectives_valid=true` |
| `invalid_measurements` | A raw measurement is non-finite or peak-to-peak voltage is negative. Non-finite measurements and both objectives are `null`; other raw measurements may remain. | Both false |
| `undefined_relative_voltage_ripple` | Mean voltage is zero. Raw measurements, gain, and gain error remain; relative ripple is `null`. | `simulation_valid=true`, `objectives_valid=false` |
| `simulation_error` | Simulator raised an error. All measurements and objectives are `null`; `error_type` and `error_message` are populated. | Both false |

Keep every row and use `objectives_valid` to mask rows from a numeric objective
loss. The published v1.0.0 dataset happens to contain only `ok` and
`invalid_measurements` rows; the other statuses are part of the generation
schema and explain possible future or local runs.

The three invalid simulator results are retained at `train[4309]`,
`train[5960]`, and `val[223]`. Their unavailable measurements and objectives
are `null`; they are never replaced with zero, imputed, clipped, or removed.

Consumers should retain every row and use `objectives_valid` as a mask when a
numeric regression loss requires objective labels. Invalid rows may also be
used to model the simulator-failure region. Evaluation must report the number
of valid and invalid rows rather than silently dropping failures.

All finite values, including negative signed measurements and very large
relative-ripple values near zero mean voltage, remain unchanged.

## v1 objectives

The stored physical measurements are:

- signed mean output voltage, `output_voltage_mean`;
- peak-to-peak output voltage, `output_voltage_peak_to_peak`.

With a 1,000 V source, v1 derives the signed gain and two minimization
objectives:

```text
dc_gain = output_voltage_mean / 1000
dc_gain_error = abs(dc_gain - 0.25)
relative_voltage_ripple = output_voltage_peak_to_peak / abs(output_voltage_mean)
```

If the simulator does not return finite measurements, the derived objectives
are `null` and the validity/status fields identify the failure. A zero mean
voltage would similarly make relative ripple unavailable rather than assigning
an artificial value.

## Fields

### Identity and source mapping

- `dataset_schema_version`: schema version for this row format.
- `split`, `source_index`: exact v0 split membership and row index.
- `design_sha256`: stable checksum of `initial_design`.
- `initial_design`: the original 20-dimensional v0 design.
- `v0_DcGain`, `v0_Voltage_Ripple`: immutable v0 labels retained only for
  direct comparison.
- `source_dataset_id`, `source_dataset_revision`: exact v0 source.
- `problem_version`: EngiBench problem version (`1`).

### Reproducibility

- `engibench_git_commit`, `netlist_sha256`;
- `simulator_version`, `simulator_sha256`;
- `simulator_platform_system`, `simulator_platform_machine`;
- `container_sha256`.

### Measurements, objectives, and validity

- `output_voltage_mean`, `output_voltage_peak_to_peak`, `dc_gain`;
- `dc_gain_error`, `relative_voltage_ripple`;
- `simulation_valid`, `objectives_valid`, `simulation_status`;
- `error_type`, `error_message` for caught simulator exceptions.

## Frozen provenance

| Component | Identity |
| --- | --- |
| Source dataset | `IDEALLab/power_electronics_v0` |
| Source revision | `5c4adb2ec5cfc71794988b1297a7ff8ffe59daa5` |
| EngiBench commit | `64e6107d44349e67e031cad36633c1af26817784` |
| EngiBench review | [IDEALLab/EngiBench#279](https://github.com/IDEALLab/EngiBench/pull/279) |
| Simulator | ngspice 44.2, Linux x86_64 |
| ngspice binary SHA-256 | `11a4334ee90509f5edfdceef541711a34a1943d26a14cf0928ac8d5947b72374` |
| Apptainer SIF SHA-256 | `40816f203b7e1c68ae37f4d9353bd302486d77988b98733c021f1ff71f48ae02` |
| Container definition SHA-256 | `20675ae0ab31723bae9dd5881d04fcff6e7e08047898b3cbf4e6595dfb705695` |
| Netlist SHA-256 | `7a3c9f061993ceddd605394cd03d899b1933370cc0cd38b48606c1d0c23d13a7` |

The exact original v0 runtime cannot be confirmed. An archived notebook
contains evidence for Windows/x86_64 and ngspice 36, while an ngspice 44.2
ARM64 Mac reproduction is much closer to the published v0 labels than the
corresponding Linux x86_64 reproduction. Because operating system, simulator
version, compiler, and build also differ, the latter is evidence consistent
with ARM but is not proof of the original architecture.

Do not combine v0 and v1 labels or silently train on one backend and verify on
another. Cross-backend comparisons should be explicit experiments.

## Generation and audit

The `provenance/` directory contains:

- the 24 original generation manifests;
- the strict 13,824-row audit report;
- the JSONL-to-Parquet semantic conversion report;
- the container recipe and exact Python dependency freeze;
- the Euler Slurm generation script and both audit/conversion scripts.

The Parquet conversion sorts every split by `source_index`. Its report verifies
that every value and `null` round-trips exactly from the audited JSONL source.

## Limitations

- Results are specific to the frozen ngspice binary and container fingerprint.
- Relative ripple can become extremely large when the absolute mean voltage is
  close to zero. These finite values are intentional and are not clipped.
- Three designs do not have finite simulator measurements on the canonical
  backend. Their explicit invalid status is part of the benchmark.
- The v0 labels are provided for comparison, not as additional v1 targets.

## Citation

```bibtex
@inproceedings{felten_engibench_2025,
  title = {{EngiBench}: {A} {Framework} for {Data}-{Driven} {Engineering} {Design} {Research}},
  author = {Felten, Florian and Apaza, Gabriel and B\"{a}unlich, Gerhard and Diniz, Cashen and Dong, Xuliang and Drake, Arthur and Habibi, Milad and Hoffman, Nathaniel J. and Keeler, Matthew and Massoudi, Soheyl and VanGessel, Francis G. and Fuge, Mark},
  booktitle = {Proceedings of the 39th Conference on Neural Information Processing Systems ({NeurIPS} 2025)},
  year = {2025}
}
```