{"title": "AsymNVM: An Efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Teng Ma", "Mingxing Zhang", "Kang Chen", "Zhuo Song", "Yongwei Wu", "Xuehai Qian"], "abstract": "The byte-addressable non-volatile memory (NVM) is a promising technology since it simultaneously provides DRAM-like performance, disk-like capacity, and persistency. The current NVM deployment with byte-addressability is \\em symmetric, where NVM devices are directly attached to servers. Due to the higher density, NVM provides much larger capacity and should be shared among servers. Unfortunately, in the symmetric setting, the availability of NVM devices is affected by the specific machine it is attached to. High availability can be achieved by replicating data to NVM on a remote machine. However, it requires full replication of data structure in local memory --- limiting the size of the working set. This paper rethinks NVM deployment and makes a case for the \\em asymmetric byte-addressable non-volatile memory architecture, which decouples servers from persistent data storage. In the proposed \\em \\anvm architecture, NVM devices (i.e., back-end nodes) can be shared by multiple servers (i.e., front-end nodes) and provide recoverable persistent data structures. The asymmetric architecture, which follows the industry trend of \\em resource disaggregation, is made possible due to the high-performance network (e.g., RDMA). At the same time, \\anvm leads to a number of key problems such as, still relatively long network latency, persistency bottleneck, and simple interface of the back-end NVM nodes. We build \\em \\anvm framework based on \\anvm architecture that implements: 1) high performance persistent data structure update; 2) NVM data management; 3) concurrency control; and 4) crash-consistency and replication. The key idea to remove persistency bottleneck is the use of \\em operation log that reduces stall time due to RDMA writes and enables efficient batching and caching in front-end nodes. To evaluate performance, we construct eight widely used data structures and two transaction applications based on \\anvm framework. In a 10-node cluster equipped with real NVM devices, results show that \\anvm achieves similar or better performance compared to the best possible symmetric architecture while enjoying the benefits of disaggregation. We found the speedup brought by the proposed optimizations is drastic, --- 5$\\sim$12× among all benchmarks.", "doi": "10.1145/3373376.3378511", "arxiv_id": "https://doi.org/10.1145/3373376.3378511", "pmid": null, "openalex_id": null, "s2_id": "016b0854e8dce422d77297d1bec1ef0ba43ef0e0", "cited_by": 50, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378511"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378511", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CubicleOS: a library OS with software componentisation for practical isolation", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Vasily A. Sartakov", "Lluís Vilanova", "Peter R. Pietzuch"], "abstract": "Library OSs have been proposed to deploy applications isolated inside containers, VMs, or trusted execution environments. They often follow a highly modular design in which third-party components are combined to offer the OS functionality needed by an application, and they are customised at compilation and deployment time to fit application requirements. Yet their monolithic design lacks isolation across components: when applications and OS components contain security-sensitive data (e.g., cryptographic keys or user data), the lack of isolation renders library OSs open to security breaches via malicious or vulnerable third-party components.", "doi": "10.1145/3445814.3446731", "arxiv_id": "https://doi.org/10.1145/3445814.3446731", "pmid": null, "openalex_id": null, "s2_id": "01a07e49464db5ce6ba4c47c7b267fa44c58d115", "cited_by": 65, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446731"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446731", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Lazy Determinism for Faster Deterministic Multithreading", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Timothy Merrifield", "Sepideh Roghanchi", "Joseph Devietti", "Jakob Eriksson"], "abstract": "Deterministic multithreading (DMT) fundamentally requires total, deterministic ordering of synchronization operations on each synchronization variable, i.e. a partial ordering over all synchronization operations. In practice, prior DMT systems totally order all synchronization operations, regardless of synchronization variable; the result is severe performance degradation for highly concurrent applications using fine-grained synchronization. Motivated by this class of programs, we propose lazy determinism as a way to go beyond this total order bottleneck. Lazy determinism executes synchronization operations speculatively, and enforces determinism by subsequently validating the resulting order of operations. If an ordering violation is detected, part of the computation is restarted. By enforcing only the partial ordering required to guarantee determinism, lazy determinism increases the available parallelism during deterministic execution. We implement LazyDet via a pure-software runtime system accelerated by custom Linux kernel support. Our experiments with hash table benchmarks from Synchrobench show roughly an order of magnitude improvement in the performance of lock-based data structures compared to the state of the art in eager determinism. For benchmarks from PARSEC-2, SPLASH-2, and Phoenix, we demonstrate runtime improvements of up to 2× on the programs that challenge deterministic execution environments the most.", "doi": "10.1145/3297858.3304047", "arxiv_id": "https://doi.org/10.1145/3297858.3304047", "pmid": null, "openalex_id": null, "s2_id": "044f93045835efe4db4153a69e20de0dc4398d16", "cited_by": 12, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304047", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304047"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304047", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "NOREBA: a compiler-informed non-speculative out-of-order commit processor", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ali Hajiabadi", "Andreas Diavastos", "Trevor E. Carlson"], "abstract": "Modern superscalar processors execute instructions out-of-order, but commit them in program order to provide precise exception handling and safe instruction retirement. However, in-order instruction commit is highly conservative and holds on to critical resources far longer than necessary, severely limiting the reach of general-purpose processors, ultimately reducing performance. Solutions that allow for efficient, early reclamation of these critical resources could seize the opportunity to improve performance. One such solution is out-of-order commit, which has traditionally been challenging due to inefficient, complex hardware used to guarantee safe instruction retirement and provide precise exception handling. In this work, we present NOREBA, a processor for Non-speculative Out-of-order Retirement via Branch Reconvergence Analysis. In NOREBA, we enable non-speculative out-of-order commit and resource reclamation in a light-weight manner, improving performance and efficiency. We accomplish this through a combination of (1) automatic compiler annotation of true branch dependencies, and (2) an efficient re-design of the reorder buffer from traditional processors. By exploiting compiler branch dependency information, this system achieves 95% of the performance of aggressive, speculative solutions, without any additional speculation, and while maintaining energy efficiency.", "doi": "10.1145/3445814.3446726", "arxiv_id": "https://doi.org/10.1145/3445814.3446726", "pmid": null, "openalex_id": null, "s2_id": "04fc2df9d9b18542ec8a97fbd30f1be8fd3b4dff", "cited_by": 9, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446726", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446726"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446726", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Storage", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248623", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "05b5ee5b37171c2092b3e21e23a6720f2337f152", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "pLock: A Fast Lock for Architectures with Explicit Inter-core Message Passing", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiongchao Tang", "Jidong Zhai", "Xuehai Qian", "Wenguang Chen"], "abstract": "Synchronization is a significant issue for multi-threaded programs. Mutex lock, as a classic solution, is widely used in legacy programs and is still popular for its intuition. The SW26010 architecture, deployed on the supercomputer Sunway Taihulight, introduces hardware-supported inter-core message passing mechanism and exposes explicit interfaces for developers to use its fast on-chip network. This emerging architectural feature brings both opportunities and challenges for mutex lock implementation. However, there is still no general lock mechanism optimized for architectures with this new feature. In this paper, we propose pLock, a fast lock designed for architectures that support Explicit inter-core Message Passing (EMP). pLock uses partial cores as lock servers and leverages the fast on-chip network to implement high-performance mutual exclusive locks. We propose two new techniques -- chaining lock and hierarchical lock -- to reduce message count and mitigate network congestion. We implement and evaluate pLock on an SW26010 processor. The experimental results show that our proposed techniques improve the performance of EMP-lock by up to 19.4x over a basic design.", "doi": "10.1145/3297858.3304030", "arxiv_id": "https://doi.org/10.1145/3297858.3304030", "pmid": null, "openalex_id": null, "s2_id": "05f803f9c6012e0639bc0a89a7dcf4c301cb7cbc", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304030", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304030"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304030", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 1B: I/O", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252392", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "06340d07e9e78c83e1d73da90f56a0dd4c8e542c", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Sidewinder: An Energy Efficient and Developer Friendly Heterogeneous Architecture for Continuous Mobile Sensing", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daniyal Liaqat", "Silviu Jingoi", "Eyal de Lara", "Ashvin Goel", "Wilson To", "Kevin Lee", "Italo De Moraes Garcia", "Manuel Saldaña"], "abstract": "Applications that perform continuous sensing on mobile phones have the potential to revolutionize everyday life. Examples range from medical and health monitoring applications, such as pedometers and fall detectors, to participatory sensing applications, such as noise pollution, traffic and seismic activity monitoring. Unfortunately, current mobile devices are a poor match for continuous sensing applications as they require the device to remain awake for extended periods of time, resulting in poor battery life. This paper presents Sidewinder, a new approach towards offloading sensor data processing to a low-power processor and waking up the main processor when events of interest occur. This approach differs from other heterogeneous architectures in that developers are presented with a programming interface that lets them construct application specific wake-up conditions by linking together and parameterizing predefined sensor data processing algorithms. Our experiments indicate performance that is comparable to approaches that provide fully programmable offloading, but do so with a much simpler programming interface that facilitates deployment and portability.", "doi": "10.1145/2872362.2872398", "arxiv_id": "https://doi.org/10.1145/2872362.2872398", "pmid": null, "openalex_id": null, "s2_id": "06ea03222b06bb86a75c41f6ce6d4fe00d533d42", "cited_by": 26, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872398"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872398", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Big Data Analytics and Intelligence at Alibaba Cloud", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3093337.3037699", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "06f0f46ea06fdab25da0554c1fb050aab955cb34", "cited_by": 6, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3037699?download=true"], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "In-Memory Data Parallel Processor", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daichi Fujiki", "Scott A. Mahlke", "Reetuparna Das"], "abstract": "Recent developments in Non-Volatile Memories (NVMs) have opened up a new horizon for in-memory computing. Despite the significant performance gain offered by computational NVMs, previous works have relied on manual mapping of specialized kernels to the memory arrays, making it infeasible to execute more general workloads. We combat this problem by proposing a programmable in-memory processor architecture and data-parallel programming framework. The efficiency of the proposed in-memory processor comes from two sources: massive parallelism and reduction in data movement. A compact instruction set provides generalized computation capabilities for the memory array. The proposed programming framework seeks to leverage the underlying parallelism in the hardware by merging the concepts of data-flow and vector processing. To facilitate in-memory programming, we develop a compilation framework that takes a TensorFlow input and generates code for our in-memory processor. Our results demonstrate 7.5x speedup over a multi-core CPU server for a set of applications from Parsec and 763x speedup over a server-class GPU for a set of Rodinia benchmarks.", "doi": "10.1145/3173162.3173171", "arxiv_id": "https://doi.org/10.1145/3173162.3173171", "pmid": null, "openalex_id": null, "s2_id": "07aad7dce11e616999ef00d38c8eb5f9820229b4", "cited_by": 147, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173171", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173171"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173171", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "IIU: Specialized Architecture for Inverted Index Search", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jun Heo", "Jaeyeon Won", "Yejin Lee", "Shivam Bharuka", "Jaeyoung Jang", "Tae Jun Ham", "Jae W. Lee"], "abstract": "Inverted index serves as a fundamental data structure for efficient search across various applications such as full-text search engine, document analytics and other information retrieval systems. The storage requirement and query load for these structures have been growing at a rapid rate. Thus, an ideal indexing system should maintain a small index size with a low query processing time. Previous works have mainly focused on using CPUs and GPUs to exploit query parallelism while utilizing state-of-the-art compression schemes to fit the index in memory. However, scaling parallelism to maximally utilize memory bandwidth on these architectures is still challenging. In this work, we present IIU, a novel inverted index processing unit, to optimize the query performance while maintaining a low memory overhead for index storage. To this end, we co-design the indexing scheme and hardware accelerator so that the accelerator can process highly compressed inverted index at a high throughput. In addition, IIU provides flexible interconnects between modules to take advantage of both intra- and inter-query parallelism. Our evaluation using a cycle-level simulator demonstrates that IIU provides an average of 13.8\\times× query latency reduction and 5.4\\times× throughput improvement across different query types, while reducing the average energy consumption by 18.6\\times×, compared to Apache Lucene, a production-grade full-text search framework.", "doi": "10.1145/3373376.3378521", "arxiv_id": "https://doi.org/10.1145/3373376.3378521", "pmid": null, "openalex_id": null, "s2_id": "08016dcd33b7e86b8c4f5feebb71fca01e555b66", "cited_by": 8, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378521"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378521", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3623278.3624767", "arxiv_id": "2103.00194", "pmid": null, "openalex_id": null, "s2_id": "08c977c75acdeb7509c6aed1d55cfcc0b29729a5", "cited_by": 30, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3623278.3624767"], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SOFRITAS: Serializable Ordering-Free Regions for Increasing Thread Atomicity Scalably", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Christian DeLozier", "Ariel Eizenberg", "Brandon Lucia", "Joseph Devietti"], "abstract": "Correctly synchronizing multithreaded programs is challenging and errors can lead to program failures such as atomicity violations. Existing strong memory consistency models rule out some possible failures, but are limited by depending on programmer-defined locking code. We present the new Ordering-Free Region (OFR) serializability consistency model that ensures atomicity for OFRs, which are spans of dynamic instructions between consecutive ordering constructs (e.g., barriers), without breaking atomicity at lock operations. Our platform, Serializable Ordering-Free Regions for Increasing Thread Atomicity Scalably (SOFRITAS), ensures a C/C++ program's execution is equivalent to a serialization of OFRs by default. We build two systems that realize the SOFRITAS idea: a concurrency bug finding tool for testing called SOFRITEST, and a production runtime system called SOPRO. SOFRITEST uses OFRs to find concurrency bugs, including a multi-critical-section atomicity violation in memcached that weaker consistency models will miss. If OFR's are too coarse-grained, SOFRITEST suggests refinement annotations automatically. Our software-only SOPRO implementation has high performance, scales well with increased parallelism, and prevents failures despite bugs in locking code. SOFRITAS has an average overhead of just 1.59x on a single-threaded execution and 1.51x on sixteen threads, despite pthreads' much weaker memory model.", "doi": "10.1145/3173162.3173192", "arxiv_id": "https://doi.org/10.1145/3173162.3173192", "pmid": null, "openalex_id": null, "s2_id": "095bf59b6881ae193988209c905966344a1d4f24", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3173192&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173192"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173192", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Blasting through the Front-End Bottleneck with Shotgun", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Rakesh Kumar", "Boris Grot", "Vijay Nagarajan"], "abstract": "The front-end bottleneck is a well-established problem in server workloads owing to their deep software stacks and large instruction working sets. Despite years of research into effective L1-I and BTB prefetching, state-of-the-art techniques force a trade-off between performance and metadata storage costs. This work introduces Shotgun, a BTB-directed front-end prefetcher powered by a new BTB organization that maintains a logical map of an application's instruction footprint, which enables high-efficacy prefetching at low storage cost. To map active code regions, Shotgun precisely tracks an application's global control flow (e.g., function and trap routine entry points) and summarizes local control flow within each code region. Because the local control flow enjoys high spatial locality, with most functions comprised of a handful of instruction cache blocks, it lends itself to a compact region-based encoding. Meanwhile, the global control flow is naturally captured by the application's unconditional branch working set (calls, returns, traps). Based on these insights, Shotgun devotes the bulk of its BTB capacity to branches responsible for the global control flow and a spatial encoding of their target regions. By effectively capturing a map of the application's instruction footprint in the BTB, Shotgun enables highly effective BTB-directed prefetching. Using a storage budget equivalent to a conventional BTB, Shotgun outperforms the state-of-the-art BTB-directed front-end prefetcher by up to 14% on a set of varied commercial workloads.", "doi": "10.1145/3173162.3173178", "arxiv_id": "https://doi.org/10.1145/3173162.3173178", "pmid": null, "openalex_id": null, "s2_id": "0aef7a464840621c384380ac8877ae53b73d23a8", "cited_by": 78, "type": "conference", "is_oa": true, "pdf_urls": ["https://www.research.ed.ac.uk/files/51477158/ShotgunPreprint.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173178"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173178", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Exploring Branch Predictors for Constructing Transient Execution Trojans", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tao Zhang", "Kenneth Koltermann", "Dmitry Evtyushkin"], "abstract": "Transient execution is one of the most critical features used in CPUs to achieve high performance. Recent Spectre attacks demonstrated how this feature can be manipulated to force applications to reveal sensitive data. The industry quickly responded with a series of software and hardware mitigations among which microcode patches are the most prevalent and trusted. In this paper, we argue that currently deployed protections still leave room for constructing attacks. We do so by presenting transient trojans, software modules that conceal their malicious activity within transient execution mode. They appear completely benign, pass static and dynamic analysis checks, but reveal sensitive data when triggered. To construct these trojans, we perform a detailed analysis of the attack surface currently present in today's systems with respect to the recommended mitigation techniques. We reverse engineer branch predictors in several recent x86_64 processors which allows us to uncover previously unknown exploitation techniques. Using these techniques, we construct three types of transient trojans and demonstrate their stealthiness and practicality.", "doi": "10.1145/3373376.3378526", "arxiv_id": "https://doi.org/10.1145/3373376.3378526", "pmid": null, "openalex_id": null, "s2_id": "0b174c5c6e4c9a265c64b261ae217cbeba258529", "cited_by": 49, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378526", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378526"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378526", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tim Sherwood", "Emery D. Berger", "Christos Kozyrakis"], "abstract": null, "doi": "10.1145/3445814", "arxiv_id": "https://doi.org/10.1145/3445814", "pmid": null, "openalex_id": null, "s2_id": "0b35a3fd53a6304e9fed9cc24d7c22c32b0c0049", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fair Write Attribution and Allocation for Consolidated Flash Cache", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Wonil Choi", "Bhuvan Urgaonkar", "Mahmut T. Kandemir", "Myoungsoo Jung", "David Evans"], "abstract": "Consolidating multiple workloads on a single flash-based storage device is now a common practice. We identify a new problem related to lifetime management in such settings: how should one partition device resources among consolidated workloads such that their allowed contributions to the device's wear (resulting from their writes including hidden writes due to garbage collection) may be deemed fairly assigned? When flash is used as a cache/buffer, such fairness is important because it impacts what and how much traffic from various workloads may be serviced using flash which in turn affects their performance. We first clarify why the write attribution problem (i.e., which workload contributed how many writes) is non-trivial. We then present a technique for it inspired by the Shapley value, a classical concept from cooperative game theory, and demonstrate that it is accurate, fair, and feasible. We next consider how to treat an overall \"write budget\" (i.e., total allowable writes during a given time period) for the device as a first-class resource worthy of explicit management. Towards this, we propose a novel write budget allocation technique. Finally, we construct a dynamic lifetime management framework for consolidated devices by putting the above elements together. Our experiments using real-world workloads demonstrate that our write allocation and attribution techniques lead to performance fairness across consolidated workloads.", "doi": "10.1145/3373376.3378502", "arxiv_id": "https://doi.org/10.1145/3373376.3378502", "pmid": null, "openalex_id": null, "s2_id": "0bab05d4a887009b51267a0cd90e945d16bff83e", "cited_by": 8, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378502", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378502"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378502", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hop: Heterogeneity-aware Decentralized Training", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Qinyi Luo", "Jinkun Lin", "Youwei Zhuo", "Xuehai Qian"], "abstract": "Recent work has shown that decentralized algorithms can deliver superior performance over centralized ones in the context of machine learning. The two approaches, with the main difference residing in their distinct communication patterns, are both susceptible to performance degradation in heterogeneous environments. Although vigorous efforts have been devoted to supporting centralized algorithms against heterogeneity, little has been explored in decentralized algorithms regarding this problem. This paper proposes Hop, the first heterogeneity-aware decentralized training protocol. Based on a unique characteristic of decentralized training that we have identified, the iteration gap, we propose a queue-based synchronization mechanism that can efficiently implement backup workers and bounded staleness in the decentralized setting. To cope with deterministic slowdown, we propose skipping iterations so that the effect of slower workers is further mitigated. We build a prototype implementation of Hop on TensorFlow. The experiment results on CNN and SVM show significant speedup over standard decentralized training in heterogeneous settings.", "doi": "10.1145/3297858.3304009", "arxiv_id": "1902.01064", "pmid": null, "openalex_id": null, "s2_id": "0c9a109ab96110e7cb5f64cde92f47332f521a74", "cited_by": 61, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304009", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304009"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304009", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Chronos: Efficient Speculative Parallelism for Accelerators", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Maleen Abeydeera", "Daniel Sánchez"], "abstract": "We present Chronos, a framework to build accelerators for applications with speculative parallelism. These applications consist of atomic tasks, sometimes with order constraints, and need speculative execution to extract parallelism. Prior work extended conventional multicores to support speculative parallelism, but these prior architectures are a poor match for accelerators because they rely on cache coherence and add non-trivial hardware to detect conflicts among tasks. Chronos instead relies on a novel execution model, Spatially Located Ordered Tasks (SLOT), that uses order as the only synchronization mechanism and limits task accesses to a single read-write object. This simplification avoids the need for cache coherence and makes speculative execution cheap and distributed. Chronos abstracts the complexities of speculative parallelism, making accelerator design easy. We develop an FPGA implementation of Chronos and use it to build accelerators for four challenging applications. When run on commodity AWS FPGA instances, these accelerators outperform state-of-the-art software versions running on a higher-priced multicore instance by 3.5x to 15.3x.", "doi": "10.1145/3373376.3378454", "arxiv_id": "https://doi.org/10.1145/3373376.3378454", "pmid": null, "openalex_id": null, "s2_id": "0db8568982a50d78fd1163f444a7611bbdf58b9a", "cited_by": 34, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378454", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378454"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378454", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 2: ASPLOS Highlights II", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248617", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "0e11a531c9220cf478b4b66d220a97d588fd07f0", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Benchmarking, analysis, and optimization of serverless function snapshots", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dmitrii Ustiugov", "Plamen Petrov", "Marios Kogias", "Edouard Bugnion", "Boris Grot"], "abstract": "Serverless computing has seen rapid adoption due to its high scalability and flexible, pay-as-you-go billing model. In serverless, developers structure their services as a collection of functions, sporadically invoked by various events like clicks. High inter-arrival time variability of function invocations motivates the providers to start new function instances upon each invocation, leading to significant cold-start delays that degrade user experience. To reduce cold-start latency, the industry has turned to snapshotting, whereby an image of a fully-booted function is stored on disk, enabling a faster invocation compared to booting a function from scratch. This work introduces vHive, an open-source framework for serverless experimentation with the goal of enabling researchers to study and innovate across the entire serverless stack. Using vHive, we characterize a state-of-the-art snapshot-based serverless infrastructure, based on industry-leading Containerd orchestration framework and Firecracker hypervisor technologies. We find that the execution time of a function started from a snapshot is 95% higher, on average, than when the same function is memory-resident. We show that the high latency is attributable to frequent page faults as the function's state is brought from disk into guest memory one page at a time. Our analysis further reveals that functions access the same stable working set of pages across different invocations of the same function. By leveraging this insight, we build REAP, a light-weight software mechanism for serverless hosts that records functions' stable working set of guest memory pages and proactively prefetches it from disk into memory. Compared to baseline snapshotting, REAP slashes the cold-start delays by 3.7x, on average.", "doi": "10.1145/3445814.3446714", "arxiv_id": "2101.09355", "pmid": null, "openalex_id": null, "s2_id": "0e546cc9b4a98562af99188c9dfff771a8425c80", "cited_by": 251, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2101.09355", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446714"], "github": ["https://github.com/ease-lab/vhive"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446714", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 8A: Security II", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252408", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "0ef96bada1826f8c4832b689d3cbd8a9649c7435", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HIPStR: Heterogeneous-ISA Program State Relocation", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ashish Venkat", "Sriskanda Shamasunder", "Hovav Shacham", "Dean M. Tullsen"], "abstract": "Heterogeneous Chip Multiprocessors have been shown to provide significant performance and energy efficiency gains over homogeneous designs. Recent research has expanded the dimensions of heterogeneity to include diverse Instruction Set Architectures, called Heterogeneous-ISA Chip Multiprocessors. This work leverages such an architecture to realize substantial new security benefits, and in particular, to thwart Return-Oriented Programming. This paper proposes a novel security defense called HIPStR -- Heterogeneous-ISA Program State Relocation -- that performs dynamic randomization of run-time program state, both within and across ISAs. This technique outperforms the state-of-the-art just-in-time code reuse (JIT-ROP) defense by an average of 15.6%, while simultaneously providing greater security guarantees against classic return-into-libc, ROP, JOP, brute force, JIT-ROP, and several evasive variants.", "doi": "10.1145/2872362.2872408", "arxiv_id": "https://doi.org/10.1145/2872362.2872408", "pmid": null, "openalex_id": null, "s2_id": "0fa5a651cd4dd1f78546b2aa840b4b44aa807649", "cited_by": 37, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872408"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872408", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "NeuMMU: Architectural Support for Efficient Address Translations in Neural Processing Units", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bongjoon Hyun", "Youngeun Kwon", "Yujeong Choi", "John Kim", "Minsoo Rhu"], "abstract": "To satisfy the compute and memory demands of deep neural networks (DNNs), neural processing units (NPUs) are widely being utilized for accelerating DNNs. Similar to how GPUs have evolved from a slave device into a mainstream processor architecture, it is likely that NPUs will become first-class citizens in this fast-evolving heterogeneous architecture space. This paper makes a case for enabling address translation in NPUs to decouple the virtual and physical memory address space. Through a careful data-driven application characterization study, we root-cause several limitations of prior GPU-centric address translation schemes and propose a memory management unit (MMU) that is tailored for NPUs. Compared to an oracular MMU design point, our proposal incurs only an average 0.06% performance overhead.", "doi": "10.1145/3373376.3378494", "arxiv_id": "1911.06859", "pmid": null, "openalex_id": null, "s2_id": "0fdc1a05a67631d61dd4e6cf1b513c02403bfcb5", "cited_by": 32, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378494"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378494", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xing Hu", "Ling Liang", "Shuangchen Li", "Lei Deng", "Pengfei Zuo", "Yu Ji", "Xinfeng Xie", "Yufei Ding", "Chang Liu", "Timothy Sherwood", "Yuan Xie"], "abstract": "  As neural networks continue their reach into nearly every aspect of software\noperations, the details of those networks become an increasingly sensitive\nsubject. Even those that deploy neural networks embedded in physical devices\nmay wish to keep the inner working of their designs hidden -- either to protect\ntheir intellectual property or as a form of protection from adversarial inputs.\nThe specific problem we address is how, through heavy system stack, given noisy\nand imperfect memory traces, one might reconstruct the neural network\narchitecture including the set of layers employed, their connectivity, and\ntheir respective dimension sizes. Considering both the intra-layer architecture\nfeatures and the inter-layer temporal association information introduced by the\nDNN design empirical experience, we draw upon ideas from speech recognition to\nsolve this problem. We show that off-chip memory address traces and PCIe events\nprovide ample information to reconstruct such neural network architectures\naccurately. We are the first to propose such accurate model extraction\ntechniques and demonstrate an end-to-end attack experimentally in the context\nof an off-the-shelf Nvidia GPU platform with full system stack. Results show\nthat the proposed techniques achieve a high reverse engineering accuracy and\nimprove the one's ability to conduct targeted adversarial attack with success\nrate from 14.6\\%$\\sim$25.5\\% (without network architecture knowledge) to 75.9\\%\n(with extracted network architecture).\n", "doi": "10.1145/3373376.3378460", "arxiv_id": "https://doi.org/10.1145/3373376.3378460", "pmid": null, "openalex_id": null, "s2_id": "109ad71af2ffce01b60852f8141ea91be6eed9e1", "cited_by": 186, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378460", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378460", "https://arxiv.org/pdf/1903.03916"], "github": [], "sources": ["semanticscholar", "papervault", "open-arxiv"], "landing": "https://doi.org/10.1145/3373376.3378460", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems", "journal_ref": "ASPLOS-2020", "categories": "cs.CR cs.AR"}
{"title": "Time-optimal Qubit mapping", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chi Zhang", "Ari B. Hayes", "Longfei Qiu", "Yuwei Jin", "Yan-Hao Chen", "Eddy Z. Zhang"], "abstract": "Rapid progress in the physical implementation of quantum computers gave birth to multiple recent quantum machines implemented with superconducting technology. In these NISQ machines, each qubit is physically connected to a bounded number of neighbors. This limitation prevents most quantum programs from being directly executed on quantum devices. A compiler is required for converting a quantum program to a hardware-compliant circuit, in particular, making each two-qubit gate executable by mapping the two logical qubits to two physical qubits with a link between them. To solve this problem, existing studies focus on inserting SWAP gates to dynamically remap logical qubits to physical qubits. However, most of the schemes lack the consideration of time-optimality of generated quantum circuits, or are achieving time-optimality with certain constraints. In this work, we propose a theoretically time-optimal SWAP insertion scheme for the qubit mapping problem. Our model can also be extended to practical heuristic algorithms. We present exact analysis results by using our model for quantum programs with recurring execution patterns. We have for the first time discovered an optimal qubit mapping pattern for quantum fourier transformation (QFT) on 2D nearest neighbor architecture. We also present a scalable extension of our theoretical model that can be used to solve qubit mapping for large quantum circuits.", "doi": "10.1145/3445814.3446706", "arxiv_id": "https://doi.org/10.1145/3445814.3446706", "pmid": null, "openalex_id": null, "s2_id": "1102420cc29cac7076e4fe44a602a4edf8adc175", "cited_by": 111, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446706"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446706", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xuan Yang", "Mingyu Gao", "Qiaoyi Liu", "Jeff Setter", "Jing Pu", "Ankita Nayak", "Steven Bell", "Kaidi Cao", "Heonjae Ha", "Priyanka Raina", "Christos Kozyrakis", "Mark Horowitz"], "abstract": "  We show that DNN accelerator micro-architectures and their program mappings\nrepresent specific choices of loop order and hardware parallelism for computing\nthe seven nested loops of DNNs, which enables us to create a formal taxonomy of\nall existing dense DNN accelerators. Surprisingly, the loop transformations\nneeded to create these hardware variants can be precisely and concisely\nrepresented by Halide's scheduling language. By modifying the Halide compiler\nto generate hardware, we create a system that can fairly compare these prior\naccelerators. As long as proper loop blocking schemes are used, and the\nhardware can support mapping replicated loops, many different hardware\ndataflows yield similar energy efficiency with good performance. This is\nbecause the loop blocking can ensure that most data references stay on-chip\nwith good locality and the processing units have high resource utilization. How\nresources are allocated, especially in the memory system, has a large impact on\nenergy and performance. By optimizing hardware resource allocation while\nkeeping throughput constant, we achieve up to 4.2X energy improvement for\nConvolutional Neural Networks (CNNs), 1.6X and 1.8X improvement for Long\nShort-Term Memories (LSTMs) and multi-layer perceptrons (MLPs), respectively.\n", "doi": "10.1145/3373376.3378514", "arxiv_id": "1809.04070", "pmid": null, "openalex_id": null, "s2_id": "117fd3a77f887f827e7f3521964b51eb788d33c5", "cited_by": 269, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/1809.04070", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378514"], "github": [], "sources": ["semanticscholar", "papervault", "open-arxiv"], "landing": "https://doi.org/10.1145/3373376.3378514", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems", "journal_ref": "Proceedings of the Twenty-Fifth International Conference on\n  Architectural Support for Programming Languages and Operating Systems, March,\n  2020, Pages 369-383", "categories": "cs.DC"}
{"title": "Improving Datacenter Efficiency", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3093337.3046426", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "129f392d219ef8ec2f5879e0c700199cbeb676c1", "cited_by": 5, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yue Zha", "Jing Li"], "abstract": "While field-programmable gate arrays (FPGAs) have been widely deployed into cloud platforms, the high programming complexity and the inability to manage FPGA resources in an elastic/scalable manner largely limits the adoption of FPGA acceleration. Existing FPGA virtualization mechanisms partially address these limitations. Application-specific (AS) ISA provides a nice abstraction to enable a simple software programming flow that makes FPGA acceleration accessible by the mainstream software application developers. Nevertheless, existing AS ISA-based approaches can only manage FPGA resources at a per-device granularity, leading to a low resource utilization. Alternatively, hardware-specific (HS) abstraction improves the resource utilization by spatially sharing one FPGA among multiple applications. But it cannot reduce the programming complexity due to the lack of a high-level programming model.", "doi": "10.1145/3445814.3446699", "arxiv_id": "https://doi.org/10.1145/3445814.3446699", "pmid": null, "openalex_id": null, "s2_id": "12a9d12ed454e5e9182611f5793fb8ee97112084", "cited_by": 30, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446699"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446699", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Reproducible Containers", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Omar S. Navarro Leija", "Kelly Shiptoski", "Ryan G. Scott", "Baojun Wang", "Nicholas Renner", "Ryan R. Newton", "Joseph Devietti"], "abstract": "We describe the design and implementation of DetTrace, a reproducible container abstraction for Linux implemented in user space. All computation that occurs inside a DetTrace container is a pure function of the initial filesystem state of the container. Reproducible containers can be used for a variety of purposes, including replication for fault-tolerance, reproducible software builds and reproducible data analytics. We use DetTrace to achieve, in an automatic fashion, reproducibility for 12,130 Debian package builds, containing over 800 million lines of code, as well as bioinformatics and machine learning workflows. We show that, while software in each of these domains is initially irreproducible, DetTrace brings reproducibility without requiring any hardware, OS or application changes. DetTrace's performance is dictated by the frequency of system calls: IO-intensive software builds have an average overhead of 3.49x, while a compute-bound bioinformatics workflow is under 2%.", "doi": "10.1145/3373376.3378519", "arxiv_id": "https://doi.org/10.1145/3373376.3378519", "pmid": null, "openalex_id": null, "s2_id": "134b5cabd308b389883adf56ee703a1198680a4f", "cited_by": 30, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378519", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378519"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378519", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "LifeStream: a high-performance stream processing engine for periodic streams", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Anand Jayarajan", "Kimberly Hau", "Andrew Goodwin", "Gennady Pekhimenko"], "abstract": "Hospitals around the world collect massive amounts of physiological data from their patients every day. Recently, there has been an increase in research interest to subject this data to statistical analysis to gain more insights and provide improved medical diagnoses. Such analyses require complex computations on large volumes of data, demanding efficient data processing systems. This paper shows that currently available data processing solutions either fail to meet the performance requirements or lack simple and flexible programming interfaces. To address this problem, we propose LifeStream, a high-performance stream processing engine for physiological data. LifeStream hits the sweet spot between ease of programming by providing a rich temporal query language support and performance by employing optimizations that exploit the periodic nature of physiological data. We demonstrate that LifeStream achieves end-to-end performance up to 7.5× higher than state-of-the-art streaming engines and 3.2× than hand-optimized numerical libraries on real-world datasets and workloads.", "doi": "10.1145/3445814.3446725", "arxiv_id": "https://doi.org/10.1145/3445814.3446725", "pmid": null, "openalex_id": null, "s2_id": "13ec5bfa2c92499a1ec4ecd249538f62bd433517", "cited_by": 8, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446725", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446725"], "github": ["https://github.com/anandj91/LifeStream"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446725", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DCatch: Automatically Detecting Distributed Concurrency Bugs in Cloud Systems", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Haopeng Liu", "Guangpu Li", "Jeffrey F. Lukman", "Jiaxin Li", "Shan Lu", "Haryadi S. Gunawi", "Chen Tian"], "abstract": "In big data and cloud computing era, reliability of distributed systems is extremely important. Unfortunately, distributed concurrency bugs, referred to as DCbugs, widely exist. They hide in the large state space of distributed cloud systems and manifest non-deterministically depending on the timing of distributed computation and communication. Effective techniques to detect DCbugs are desired. This paper presents a pilot solution, DCatch, in the world of DCbug detection. DCatch predicts DCbugs by analyzing correct execution of distributed systems. To build DCatch, we design a set of happens-before rules that model a wide variety of communication and concurrency mechanisms in real-world distributed cloud systems. We then build runtime tracing and trace analysis tools to effectively identify concurrent conflicting memory accesses in these systems. Finally, we design tools to help prune false positives and trigger DCbugs. We have evaluated DCatch on four representative open-source distributed cloud systems, Cassandra, Hadoop MapReduce, HBase, and ZooKeeper. By monitoring correct execution of seven workloads on these systems, DCatch reports 32 DCbugs, with 20 of them being truly harmful.", "doi": "10.1145/3037697.3037735", "arxiv_id": "https://doi.org/10.1145/3037697.3037735", "pmid": null, "openalex_id": null, "s2_id": "151b71d7365328e929d5dbe75529a73d4de700c0", "cited_by": 65, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037735"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037735", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "The Guardian Council: Parallel Programmable Hardware Security", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sam Ainsworth", "Timothy M. Jones"], "abstract": "Systems security is becoming more challenging in the face of untrusted programs and system users. Safeguards against attacks currently in use, such as buffer overflows, control-flow integrity, side channels and malware, are limited. Software protection schemes, while flexible, are often too expensive, and hardware schemes, while fast, are too constrained or out-of-date to be practical. We demonstrate the best of both worlds with the Guardian Council, a novel parallel architecture to enforce a wide range of highly customisable and diverse security policies. We leverage heterogeneity and parallelism in the design of our system to perform security enforcement for a large high-performance core on a set of small microcontroller-sized cores. These Guardian Processing Elements (GPEs) are many orders of magnitude more efficient than conventional out-of-order superscalar processors, bringing high-performance security at very low power and area overheads. Alongside these highly parallel cores we provide fixed-function logging and communication units, and a powerful programming model, as part of an architecture designed for security. Evaluation on a range of existing hardware and software protection mechanisms, reimplemented on the Guardian Council, demonstrates the flexibility of our approach with negligible overheads, out-performing prior work in the literature. For instance, 4 GPEs can provide forward control-flow integrity with 0% overhead, while 6 GPEs can provide a full shadow stack at only 2%.", "doi": "10.1145/3373376.3378463", "arxiv_id": "https://doi.org/10.1145/3373376.3378463", "pmid": null, "openalex_id": null, "s2_id": "152e2d238f5a8bdf532091d5fbaf771cd4d8e3e0", "cited_by": 8, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378463", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378463"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378463", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "RAPID Programming of Pattern-Recognition Processors", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kevin Angstadt", "Westley Weimer", "Kevin Skadron"], "abstract": "We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct execution of non-deterministic finite automata (NFAs), and has been demonstrated to provide substantial speedup for a variety of data-processing applications. RAPID is clear, maintainable, concise, and efficient both at compile and run time. Language features, such as code abstraction and parallel control structures, map well to pattern-matching problems, providing clarity and maintainability. For generation of efficient runtime code, we present algorithms to convert RAPID programs into finite automata. Further, we introduce a tessellation technique for configuring the AP, which significantly reduces compile time, increases programmer productivity, and improves maintainability. We evaluate five RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by the AP. We find that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact. In addition, our tessellation technique for configuring the AP has comparable device utilization to, and results in compilation that is up to four orders of magnitude faster than, current solutions.", "doi": "10.1145/2872362.2872393", "arxiv_id": "https://doi.org/10.1145/2872362.2872393", "pmid": null, "openalex_id": null, "s2_id": "164bb40bac988ed0b90fe44366cd98c307e57b4b", "cited_by": 25, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872393", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872393"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872393", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FLEP: Enabling Flexible and Efficient Preemption on GPUs", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bo Wu", "Xu Liu", "Xiaobo Zhou", "Changjun Jiang"], "abstract": "GPUs are widely adopted in HPC and cloud computing platforms to accelerate general-purpose workloads. However, modern GPUs do not support flexible preemption, leading to performance and priority inversion problems in multi-tasking environments.", "doi": "10.1145/3037697.3037742", "arxiv_id": "https://doi.org/10.1145/3037697.3037742", "pmid": null, "openalex_id": null, "s2_id": "1883eb486e44c4a61864f538d2f0e90dca8f45f9", "cited_by": 79, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037742"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037742", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Nimble Page Management for Tiered Memory Systems", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zi Yan", "Daniel Lustig", "David W. Nellans", "Abhishek Bhattacharjee"], "abstract": "Software-controlled heterogeneous memory systems have the potential to increase the performance and cost efficiency of computing systems. However they can only deliver on this promise if supported by efficient page management policies and mechanisms within the operating system (OS). Current OS implementations do not support efficient tiering of data between heterogeneous memories. Instead, they rely on expensive offlining of memory or swapping data to disk as a means of profiling and migrating hot or cold data between memory nodes. They also leave numerous optimizations on the table; for example, multi-threaded hardware is not leveraged to maximize page migration throughput, resulting in up to 95% under-utilization of available memory bandwidth. To remedy these shortcomings, we propose and implement a general purpose OS-integrated multi-level memory management system that reuses current OS page tracking structures to tier pages directly between memories with no additional monitoring overhead. We augment this system with four additional optimizations: native support for transparent huge page migration, multi-threaded migration of a page, concurrent migration of multiple pages, and symmetric exchange of pages. Combined, these optimizations dramatically reduce kernel software overheads and improve raw page migration throughput over 15×. Implemented in Linux and evaluated on x86, Power, and ARM64 systems, our OS support for heterogeneous memories improves application performance 40% over baseline Linux for a suite of real-world memory-intensive workloads utilizing a multi-level disaggregated memory system.", "doi": "10.1145/3297858.3304024", "arxiv_id": "https://doi.org/10.1145/3297858.3304024", "pmid": null, "openalex_id": null, "s2_id": "1977cdc08901691ee57f9cb62dad388a0bdb6541", "cited_by": 206, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304024", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304024"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304024", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yu Ji", "Youyang Zhang", "Xinfeng Xie", "Shuangchen Li", "Peiqi Wang", "Xing Hu", "Youhui Zhang", "Yuan Xie"], "abstract": "Neural Network (NN) accelerators with emerging ReRAM (resistive random access memory) technologies have been investigated as one of the promising solutions to address the memory wall challenge, due to the unique capability of processing-in-memory within ReRAM-crossbar-based processing elements (PEs). However, the high efficiency and high density advantages of ReRAM have not been fully utilized due to the huge communication demands among PEs and the overhead of peripheral circuits. In this paper, we propose a full system stack solution, composed of a reconfigurable architecture design, Field Programmable Synapse Array (FPSA) and its software system including neural synthesizer, temporal-to-spatial mapper, and placement & routing. We highly leverage the software system to make the hardware design compact and efficient. To satisfy the high-performance communication demand, we optimize it with a reconfigurable routing architecture and the placement & routing tool. To improve the computational density, we greatly simplify the PE circuit with the spiking schema and then adopt neural synthesizer to enable the high density computation-resources to support different kinds of NN operations. In addition, we provide spiking memory blocks (SMBs) and configurable logic blocks (CLBs) in hardware and leverage the temporal-to-spatial mapper to utilize them to balance the storage and computation requirements of NN. Owing to the end-to-end software system, we can efficiently deploy existing deep neural networks to FPSA. Evaluations show that, compared to one of state-of-the-art ReRAM-based NN accelerators, PRIME, the computational density of FPSA improves by 31x; for representative NNs, its inference performance can achieve up to 1000x speedup.", "doi": "10.1145/3297858.3304048", "arxiv_id": "1901.09904", "pmid": null, "openalex_id": null, "s2_id": "198e0ff2f8df6bff79ec51df96e08930e716b41f", "cited_by": 60, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304048", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304048"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304048", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DNNGuard: An Elastic Heterogeneous DNN Accelerator Architecture against Adversarial Attacks", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xingbin Wang", "Rui Hou", "Boyan Zhao", "Fengkai Yuan", "Jun Zhang", "Dan Meng", "Xuehai Qian"], "abstract": "Recent studies show that Deep Neural Networks (DNN) are vulnerable to adversarial samples that are generated by perturbing correctly classified inputs to cause the misclassification of DNN models. This can potentially lead to disastrous consequences, especially in security-sensitive applications such as unmanned vehicles, finance and healthcare. Existing adversarial defense methods require a variety of computing units to effectively detect the adversarial samples. However, deploying adversary sample defense methods in existing DNN accelerators leads to many key issues in terms of cost, computational efficiency and information security. Moreover, existing DNN accelerators cannot provide effective support for special computation required in the defense methods. To address these new challenges, this paper proposes DNNGuard, an elastic heterogeneous DNN accelerator architecture that can efficiently orchestrate the simultaneous execution of original (target) DNN networks and the detect algorithm or network that detects adversary sample attacks. The architecture tightly couples the DNN accelerator with the CPU core into one chip for efficient data transfer and information protection. An elastic DNN accelerator is designed to run the target network and detection network simultaneously. Besides the capability to execute two networks at the same time, DNNGuard also supports the non-DNN computing and allows the special layer of the neural network to be effectively supported by the CPU core. To reduce off-chip traffic and improve resources utilization, we propose a dynamical resource scheduling mechanism. To build a general implementation framework, we propose an extended AI instruction set for neural networks synchronization, task scheduling and efficient data interaction. We implement DNNGuard based on RISC-V and NVDLA, and evaluate its performance impacts with six target networks and three typical detection networks. Experiment results show that DNNGuard can effectively validate the legitimacy of the input samples in parallel with the target DNN model, achieving an average 1.42x speedup compared with the state-of-the-art accelerators.", "doi": "10.1145/3373376.3378532", "arxiv_id": "https://doi.org/10.1145/3373376.3378532", "pmid": null, "openalex_id": null, "s2_id": "19c61093e89be16073c68f74c42287177023f486", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378532", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378532"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378532", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Compiler-driven FPGA virtualization with SYNERGY", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Joshua Landgraf", "Tiffany Yang", "Will Lin", "Christopher J. Rossbach", "Eric Schkufza"], "abstract": "  FPGAs are increasingly common in modern applications, and cloud providers now\nsupport on-demand FPGA acceleration in data centers. Applications in data\ncenters run on virtual infrastructure, where consolidation, multi-tenancy, and\nworkload migration enable economies of scale that are fundamental to the\nprovider's business. However, a general strategy for virtualizing FPGAs has yet\nto emerge. While manufacturers struggle with hardware-based approaches, we\npropose a compiler/runtime-based solution called Synergy. We show a compiler\ntransformation for Verilog programs that produces code able to yield control to\nsoftware at sub-clock-tick granularity according to the semantics of the\noriginal program. Synergy uses this property to efficiently support core\nvirtualization primitives: suspend and resume, program migration, and\nspatial/temporal multiplexing, on hardware which is available today. We use\nSynergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx\nFPGAs on Amazon F1. The workloads require no modification, run within 3-4x of\nunvirtualized performance, and incur a modest increase in FPGA fabric\nutilization.\n", "doi": "10.1145/3445814.3446755", "arxiv_id": "2109.02484", "pmid": null, "openalex_id": null, "s2_id": "1a6e68264a1726b867a0dcdafae536a7e1d2af78", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446755", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446755", "https://arxiv.org/pdf/2109.02484"], "github": [], "sources": ["semanticscholar", "papervault", "open-arxiv"], "landing": "https://doi.org/10.1145/3445814.3446755", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems", "journal_ref": "26th ACM International Conference on Architectural Support for\n  Programming Languages and Operating Systems (ASPLOS 2021), 2021, pp. 818-831", "categories": "cs.DC cs.AR cs.PL"}
{"title": "LeapIO: Efficient and Portable Virtual NVMe Storage on ARM SoCs", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Huaicheng Li", "Mingzhe Hao", "Stanko Novakovic", "Vaibhav Gogte", "Sriram Govindan", "Dan R. K. Ports", "Irene Zhang", "Ricardo Bianchini", "Haryadi S. Gunawi", "Anirudh Badam"], "abstract": "Today's cloud storage stack is extremely resource hungry, burning 10-20% of datacenter x86 cores, a major \"storage tax\" that cloud providers must pay. Yet, the complex cloud storage stack is not completely offload-ready to today's IO accelerators. We present LeapIO, a new cloud storage stack that leverages ARM-based co-processors to offload complex storage services. LeapIO addresses many deployment challenges, such as hardware fungibility, software portability, virtualizability, composability, and efficiency. It uses a set of OS/software techniques and new hardware properties that provide a uni- form address space across the x86 and ARM cores and ex- pose virtual NVMe storage to unmodified guest VMs, at a performance that is competitive with bare-metal servers.", "doi": "10.1145/3373376.3378531", "arxiv_id": "https://doi.org/10.1145/3373376.3378531", "pmid": null, "openalex_id": null, "s2_id": "1b797487aae43e6a483dcc3306b03d5f51e0968f", "cited_by": 85, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378531", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378531"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378531", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MERCI: efficient embedding reduction on commodity hardware via sub-query memoization", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yejin Lee", "Seong Hoon Seo", "Hyunji Choi", "Hyoung Uk Sul", "Soosung Kim", "Jae W. Lee", "Tae Jun Ham"], "abstract": "Deep neural networks (DNNs) with embedding layers are widely adopted to capture complex relationships among entities within a dataset. Embedding layers aggregate multiple embeddings — a dense vector used to represent the complicated nature of a data feature— into a single embedding; such operation is called embedding reduction. Embedding reduction spends a significant portion of its runtime on reading embeddings from memory and thus is known to be heavily memory-bandwidth-bound. Recent works attempt to accelerate this critical operation, but they often require either hardware modifications or emerging memory technologies, which makes it hardly deployable on commodity hardware. Thus, we propose MERCI, Memoization for Embedding Reduction with ClusterIng, a novel memoization framework for efficient embedding reduction. MERCI provides a mechanism for memoizing partial aggregation of correlated embeddings and retrieving the memoized partial result at a low cost. MERCI substantially reduces the number of memory accesses by 44% (29%), leading to 102% (74%) throughput improvement on real machines and 40.2% (28.6%) energy savings at the expense of 8×(1×) additional memory usage.", "doi": "10.1145/3445814.3446717", "arxiv_id": "https://doi.org/10.1145/3445814.3446717", "pmid": null, "openalex_id": null, "s2_id": "1c30be0e153bedc63c1accfd5982136c5d17c917", "cited_by": 39, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446717"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446717", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Why GPUs are Slow at Executing NFAs and How to Make them Faster", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hongyuan Liu", "Sreepathi Pai", "Adwait Jog"], "abstract": "Non-deterministic Finite Automata (NFA) are space-efficient finite state machines that have significant applications in domains such as pattern matching and data analytics. In this paper, we investigate why the Graphics Processing Unit (GPU)---a massively parallel computational device with the highest memory bandwidth available on general-purpose processors---cannot efficiently execute NFAs. First, we identify excessive data movement in the GPU memory hierarchy and describe how to privatize reads effectively using GPU's on-chip memory hierarchy to reduce this excessive data movement. We also show that in several cases, indirect table lookups in NFAs can be eliminated by converting memory reads into computation, to further reduce the number of memory reads. Although our optimization techniques significantly alleviate these memory-related bottlenecks, a side effect of these techniques is the static assignment of work to cores. This leads to poor compute utilization, where GPU cores are wasted on idle NFA states. Therefore, we propose a new dynamic scheme that effectively balances compute utilization with reduced memory usage. Our combined optimizations provide a significant improvement over the previous state-of-the-art GPU implementations of NFAs. Moreover, they enable current GPUs to outperform the domain-specific accelerator for NFAs (i.e., Automata Processor) across several applications while performing within an order of magnitude for the rest of the applications.", "doi": "10.1145/3373376.3378471", "arxiv_id": "https://doi.org/10.1145/3373376.3378471", "pmid": null, "openalex_id": null, "s2_id": "1c70b147aa2a138085793c66033eb03e015b8782", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378471", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378471"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378471", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CORF: Coalescing Operand Register File for GPUs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hodjat Asghari Esfeden", "Farzad Khorasani", "Hyeran Jeon", "Daniel Wong", "Nael B. Abu-Ghazaleh"], "abstract": "The Register File (RF) in GPUs is a critical structure that maintains the state for thousands of threads that support the GPU processing model. The RF organization substantially affects the overall performance and the energy efficiency of a GPU. For example, the frequent accesses to the RF consume a substantial amount of the dynamic energy, and port contention due to limited ports on operand collectors and register file banks affect performance as register operations are serialized. We present CORF, a compiler-assisted Coalescing Operand Register File which performs register coalescing by combining reads to multiple registers required by a single instruction, into a single physical read. To enable register coalescing, CORF utilizes register packing to co-locate narrow-width operands in the same physical register. CORF uses compiler hints to identify which register pairs are commonly accessed together. CORF saves dynamic energy by reducing the number of physical register file accesses, and improves performance by combining read operations, as well as by reducing pressure on the register file. To increase the coalescing opportunities, we re-architect the physical register file to allow coalescing reads across different physical registers that reside in mutually exclusive sub-banks; we call this design CORF++. The compiler analysis for register allocation for CORF++ becomes a form of graph coloring called the bipartite edge frustration problem. CORF++ reduces the dynamic energy of the RF by 17%, and improves IPC by 9%.", "doi": "10.1145/3297858.3304026", "arxiv_id": "https://doi.org/10.1145/3297858.3304026", "pmid": null, "openalex_id": null, "s2_id": "1c89f80f2566ab69e058e9267f3f7258b0d7f584", "cited_by": 29, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304026", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304026"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304026", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Optimizing CNNs on Multicores for Scalability, Performance and Goodput", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Samyam Rajbhandari", "Yuxiong He", "Olatunji Ruwase", "Michael Carbin", "Trishul M. Chilimbi"], "abstract": "Convolutional Neural Networks (CNN) are a class of Ar- tificial Neural Networks (ANN) that are highly efficient at the pattern recognition tasks that underlie difficult AI prob- lems in a variety of domains, such as speech recognition, object recognition, and natural language processing. CNNs are, however, computationally intensive to train. This paper presents the first characterization of the per- formance optimization opportunities for training CNNs on CPUs. Our characterization includes insights based on the structure of the network itself (i.e., intrinsic arithmetic inten- sity of the convolution and its scalability under parallelism) as well as dynamic properties of its execution (i.e., sparsity of the computation).", "doi": "10.1145/3037697.3037745", "arxiv_id": "https://doi.org/10.1145/3037697.3037745", "pmid": null, "openalex_id": null, "s2_id": "1c9be5ee1aace2562220b1040a1133678d9a0b32", "cited_by": 29, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037745"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037745", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Lifting Assembly to Intermediate Representation: A Novel Approach Leveraging Compilers", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Niranjan Hasabnis", "R. Sekar"], "abstract": "Translating low-level machine instructions into higher-level intermediate language (IL) is one of the central steps in many binary analysis and instrumentation systems. Existing systems build such translators manually. As a result, it takes a great deal of effort to support new architectures. Even for widely deployed architectures, full instruction sets may not be modeled, e.g., mature systems such as Valgrind still lack support for AVX, FMA4 and SSE4.1 for x86 processors. To overcome these difficulties, we propose a novel approach that leverages knowledge about instruction set semantics that is already embedded into modern compilers such as GCC. In particular, we present a learning-based approach for automating the translation of assembly instructions to a compiler's architecture-neutral IL. We present an experimental evaluation that demonstrates the ability of our approach to easily support many architectures (x86, ARM and AVR), including their advanced instruction sets. Our implementation is available as open-source software.", "doi": "10.1145/2872362.2872380", "arxiv_id": "https://doi.org/10.1145/2872362.2872380", "pmid": null, "openalex_id": null, "s2_id": "1d0dfb572bc16b9d1c24b73c120f4cace913535b", "cited_by": 48, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872380", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872380"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872380", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Gururaj Saileshwar", "Christopher W. Fletcher", "Moinuddin K. Qureshi"], "abstract": "Covert-channel attacks exploit contention on shared hardware resources such as processor caches to transmit information between colluding processes on the same system. In recent years, covert channels leveraging cacheline-flush instructions, such as Flush+Reload and Flush+Flush, have emerged as the fastest cross-core attacks. However, current attacks are limited in their applicability and bit-rate not due to any fundamental hardware limitations, but due to their protocol design requiring flush instructions and tight synchronization between sender and receiver, where both processes synchronize every bit-period to maintain low error-rates. In this paper, we present Streamline, a flush-less covert-channel attack faster than all prior known attacks. The key insight behind the higher channel bandwidth is asynchronous communication. Streamline communicates over a sequence of shared addresses (larger than the cache size), where the sender can move to the next address after transmitting each bit without waiting for the receiver. Furthermore, it ensures that addresses accessed by the sender are preserved in the cache until the receiver has accessed them. Finally, by the time the sender accesses the entire sequence and wraps around, the cache-thrashing property ensures that the previously transmitted addresses are automatically evicted from the cache without any cacheline flushes, which ensures functional correctness while simultaneously improving channel bandwidth. To orchestrate Streamline on a real system, we overcome multiple challenges, such as circumventing hardware optimizations (prefetching and replacement policy), and ensuring that the sender and receiver have similar execution rates. We demonstrate Streamline on an Intel Skylake CPU and show that it achieves a bit-rate of 1801 KB/s, which is 3x to 3.6x faster than the previous fastest Take-a-Way (588 KB/s) and Flush+Flush (496 KB/s) attacks, at comparable error rates. Unlike prior attacks, Streamline only relies on generic properties of caches and is applicable to processors of all ISAs (x86, ARM, etc.) and micro-architectures (Intel, AMD, etc.).", "doi": "10.1145/3445814.3446742", "arxiv_id": "https://doi.org/10.1145/3445814.3446742", "pmid": null, "openalex_id": null, "s2_id": "1d673dddef2238e0477efc5af094431650b5ac0a", "cited_by": 56, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446742"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446742", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Nikita Lazarev", "Shaojie Xiang", "Neil Adit", "Zhiru Zhang", "Christina Delimitrou"], "abstract": "The ongoing shift of cloud services from monolithic designs to mi- croservices creates high demand for efficient and high performance datacenter networking stacks, optimized for fine-grained work- loads. Commodity networking systems based on software stacks and peripheral NICs introduce high overheads when it comes to delivering small messages. We present Dagger, a hardware acceleration fabric for cloud RPCs based on FPGAs, where the accelerator is closely-coupled with the host processor over a configurable memory interconnect. The three key design principle of Dagger are: (1) offloading the entire RPC stack to an FPGA-based NIC, (2) leveraging memory interconnects instead of PCIe buses as the interface with the host CPU, and (3) making the acceleration fabric reconfigurable, so it can accommodate the diverse needs of microservices. We show that the combination of these principles significantly improves the efficiency and performance of cloud RPC systems while preserving their generality. Dagger achieves 1.3 − 3.8× higher per-core RPC throughput compared to both highly-optimized software stacks, and systems using specialized RDMA adapters. It also scales up to 84 Mrps with 8 threads on 4 CPU cores, while maintaining state-of- the-art µs-scale tail latency. We also demonstrate that large third- party applications, like memcached and MICA KVS, can be easily ported on Dagger with minimal changes to their codebase, bringing their median and tail KVS access latency down to 2.8 − 3.5 us and 5.4 − 7.8 us, respectively. Finally, we show that Dagger is beneficial for multi-tier end-to-end microservices with different threading models by evaluating it using an 8-tier application implementing a flight check-in service.", "doi": "10.1145/3445814.3446696", "arxiv_id": "https://doi.org/10.1145/3445814.3446696", "pmid": null, "openalex_id": null, "s2_id": "1de935c8fd5b735e7fc5b528ce0954842305d621", "cited_by": 74, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446696"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446696", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Caroline Trippel", "Yatin A. Manerkar", "Daniel Lustig", "Michael Pellauer", "Margaret Martonosi"], "abstract": "Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are defined at the various layers of the hardware-software stack, requiring thoroughly verified specifications, compilers, and implementations at the interfaces between layers. Current verification techniques evaluate segments of the system stack in isolation, such as proving compiler mappings from a high-level language (HLL) to an ISA or proving validity of a microarchitectural implementation of an ISA.", "doi": "10.1145/3037697.3037719", "arxiv_id": "1608.07547", "pmid": null, "openalex_id": null, "s2_id": "1eb9e5fbc5406b2cbf853bef5d5165a7c2c33ce1", "cited_by": 67, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/1608.07547", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037719"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037719", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Tigr: Transforming Irregular Graphs for GPU-Friendly Graph Processing", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amir Hossein Nodehi Sabet", "Junqiao Qiu", "Zhijia Zhao"], "abstract": "Graph analytics delivers deep knowledge by processing large volumes of highly connected data. In real-world graphs, the degree distribution tends to follow the power law -- a small portion of nodes own a large number of neighbors. The high irregularity of degree distribution acts as a major barrier to their efficient processing on GPU architectures, which are primarily designed for accelerating computations on regular data with SIMD executions. Existing solutions to the inefficiency of GPU-based graph analytics either modify the graph programming abstraction or rely on changes to the low-level thread execution models. The former requires more programming efforts for designing and maintaining graph analytics; while the latter couples with the underlying architectures, making it difficult to adapt as architectures quickly evolve. Unlike prior efforts, this work proposes to address the above fundamental problem at its origin -- the irregular graph data itself. It raises a critical question in irregular graph processing: Is it possible to transform irregular graphs into more regular ones such that the graphs can be processed more efficiently on GPU-like architectures, yet still producing the same results? Inspired by the question, this work introduces Tigr -- a graph transformation framework that can effectively reduce the irregularity of real-world graphs with correctness guarantees for a wide range of graph analytics. To make the transformations practical, Tigr features a lightweight virtual transformation scheme, which can substantially reduce the costs of graph transformations, while preserving the benefits of reduced irregularity. Evaluation on Tigr-based GPU graph processing shows significant and consistent speedup over the state-of-the-art GPU graph processing frameworks for a spectrum of irregular graphs.", "doi": "10.1145/3173162.3173180", "arxiv_id": "https://doi.org/10.1145/3173162.3173180", "pmid": null, "openalex_id": null, "s2_id": "1f0572f47be66c2c0fbf3fd0f98f25e5b5f88361", "cited_by": 129, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173180", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173180"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173180", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PMEM-spec: persistent memory speculation (strict persistency can trump relaxed persistency)", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jungi Jeong", "Changhee Jung"], "abstract": "Persistency models define the persist-order that controls the order in which stores update persistent memory (PM). As with memory consistency, the relaxed persistency models provide better performance than the strict ones by relaxing the ordering constraints. To support such relaxed persistency models, previous studies resort to APIs for annotating the persist-order in program and hardware implementations for enforcing the programmer-specified order. However, these approaches to supporting relaxed persistency impose costly burdens on both architects and programmers. In light of this, the goal of this study is to demonstrate that the strict persistency model can outperform the relaxed models with significantly less hardware complexity and programming difficulty. To achieve that, this paper presents PMEM-Spec that speculatively allows any PM accesses without stalling or buffering, detecting their ordering violation (e.g., misspeculation for PM loads and stores). PMEM-Spec treats misspeculation as power failure and thus leverages failure-atomic transactions to recover from misspeculation by aborting and restarting them purposely. Since the ordering violation rarely occurs, PMEM-Spec can accelerate persistent memory accesses without significant misspeculation penalty. Experimental results show that PMEM-Spec outperforms two epoch-based persistency models with Intel X86 ISA and the state-of-the-art hardware support by 27.2% and 10.6%, respectively.", "doi": "10.1145/3445814.3446698", "arxiv_id": "https://doi.org/10.1145/3445814.3446698", "pmid": null, "openalex_id": null, "s2_id": "1f20d310739e08ba8310f04c24a5e3e0f27553b3", "cited_by": 37, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446698", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446698"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446698", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "VIBNN: Hardware Acceleration of Bayesian Neural Networks", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ruizhe Cai", "Ao Ren", "Ning Liu", "Caiwen Ding", "Luhao Wang", "Xuehai Qian", "Massoud Pedram", "Yanzhi Wang"], "abstract": "Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number generators: 1) the RAM-based Linear Feedback Gaussian Random Number Generator (RLF-GRNG), which is inspired by the properties of binomial distribution and linear feedback logics; and 2) the Bayesian Neural Network-oriented Wallace Gaussian Random Number Generator. To achieve high scalability and efficient memory access, we propose a deep pipelined accelerator architecture with fast execution and good hardware utilization. Experimental results demonstrate that the proposed VIBNN implementations on an FPGA can achieve throughput of 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J while maintaining similar accuracy as its software counterpart.", "doi": "10.1145/3173162.3173212", "arxiv_id": "1802.00822", "pmid": null, "openalex_id": null, "s2_id": "1f4206f60ce42e0968d0ce1cfce18ee1a22ed32d", "cited_by": 101, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/1802.00822", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173212"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173212", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "How to Build Static Checking Systems Using Orders of Magnitude Less Code", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Fraser Brown", "Andres Nötzli", "Dawson R. Engler"], "abstract": "Modern static bug finding tools are complex. They typically consist of hundreds of thousands of lines of code, and most of them are wedded to one language (or even one compiler). This complexity makes the systems hard to understand, hard to debug, and hard to retarget to new languages, thereby dramatically limiting their scope. This paper reduces checking system complexity by addressing a fundamental assumption, the assumption that checkers must depend on a full-blown language specification and compiler front end. Instead, our program checkers are based on drastically incomplete language grammars (\"micro-grammars\") that describe only portions of a language relevant to a checker. As a result, our implementation is tiny-roughly 2500 lines of code, about two orders of magnitude smaller than a typical system. We hope that this dramatic increase in simplicity will allow people to use more checkers on more systems in more languages. We implement our approach in μchex, a language-agnostic framework for writing static bug checkers. We use it to build micro-grammar based checkers for six languages (C, the C preprocessor, C++, Java, JavaScript, and Dart) and find over 700 errors in real-world projects.", "doi": "10.1145/2872362.2872364", "arxiv_id": "https://doi.org/10.1145/2872362.2872364", "pmid": null, "openalex_id": null, "s2_id": "1ffeb2932f515e260c932eeff6dc4b001eff4de3", "cited_by": 39, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872364&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872364"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872364", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "3DGates: An Instruction-Level Energy Analysis and Optimization of 3D Printers", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jerry Antony Ajay", "Chen Song", "Aditya Singh Rathore", "Chi Zhou", "Wenyao Xu"], "abstract": "As the next-generation manufacturing driven force, 3D printing technology is having a transformative effect on various industrial domains and has been widely applied in a broad spectrum of applications. It also progresses towards other versatile fields with portable battery-powered 3D printers working on a limited energy budget. While reducing manufacturing energy is an essential challenge in industrial sustainability and national economics, this growing trend motivates us to explore the energy consumption of the 3D printer for the purpose of energy efficiency. To this end, we perform an in-depth analysis of energy consumption in commercial, off-the-shelf 3D printers from an instruction-level perspective. We build an instruction-level energy model and an energy profiler to analyze the energy cost during the fabrication process. From the insights obtained by the energy profiler, we propose and implement a cross-layer energy optimization solution, called 3DGates, which spans the instruction-set, the compiler and the firmware. We evaluate 3DGates over 338 benchmarks on a 3D printer and achieve an overall energy reduction of 25%.", "doi": "10.1145/3037697.3037752", "arxiv_id": "https://doi.org/10.1145/3037697.3037752", "pmid": null, "openalex_id": null, "s2_id": "21164c79302a3182064ca3cbedb248c3ebd463e0", "cited_by": 24, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037752&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037752"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037752", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Finding and Fixing Performance Pathologies in Persistent Memory Software Stacks", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jian Xu", "Juno Kim", "Amir Saman Memaripour", "Steven Swanson"], "abstract": "Emerging fast, non-volatile memories will enable systems with large amounts of non-volatile main memory (NVMM) attached to the CPU memory bus, bringing the possibility of dramatic performance gains for IO-intensive applications. This paper analyzes the impact of state-of-the-art NVMM storage systems on some of these applications and explores how those applications can best leverage the performance that NVMMs offer. Our analysis leads to several conclusions about how systems and applications should adapt to NVMMs. We propose FiLe Emulation with DAX (FLEX), a technique for moving file operations into user space, and show it and other simple changes can dramatically improve application performance. We examine the scalability of NVMM file systems in light of the rising core counts and pronounced NUMA effects in modern systems, and propose changes to Linux's virtual file system (VFS) to improve scalability. We also show that adding NUMA-aware interfaces to an NVMM file system can significantly improve performance.", "doi": "10.1145/3297858.3304077", "arxiv_id": "https://doi.org/10.1145/3297858.3304077", "pmid": null, "openalex_id": null, "s2_id": "21b0989c604cf80fd42c101d0d2f942f9b5d14ba", "cited_by": 67, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304077", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304077"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304077", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alexandros Daglis", "Mark Sutherland", "Babak Falsafi"], "abstract": "Modern online services come with stringent quality requirements in terms of response time tail latency. Because of their decomposition into fine-grained communicating software layers, a single user request fans out into a plethora of short, μs-scale RPCs, aggravating the need for faster inter-server communication. In reaction to that need, we are witnessing a technological transition characterized by the emergence of hardware-terminated user-level protocols (e.g., InfiniBand/RDMA) and new architectures with fully integrated Network Interfaces (NIs). Such architectures offer a unique opportunity for a new NI-driven approach to balancing RPCs among the cores of manycore server CPUs, yielding major tail latency improvements for μs-scale RPCs. We introduce RPCValet, an NI-driven RPC load-balancing design for architectures with hardware-terminated protocols and integrated NIs, that delivers near-optimal tail latency. RPCValet's RPC dispatch decisions emulate the theoretically optimal single-queue system, without incurring synchronization overheads currently associated with single-queue implementations. Our design improves throughput under tight tail latency goals by up to 1.4x, and reduces tail latency before saturation by up to 4x for RPCs with μs-scale service times, as compared to current systems with hardware support for RPC load distribution. RPCValet performs within 15% of the theoretically optimal single-queue system.", "doi": "10.1145/3297858.3304070", "arxiv_id": "https://doi.org/10.1145/3297858.3304070", "pmid": null, "openalex_id": null, "s2_id": "21ece3835fcc3ad84fe74a2be7fc3e11d1606b80", "cited_by": 75, "type": "conference", "is_oa": true, "pdf_urls": ["http://infoscience.epfl.ch/record/265809", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304070"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304070", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CutQC: using small Quantum computers for large Quantum circuit evaluations", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Wei Tang", "Teague Tomesh", "Martin Suchara", "Jeffrey Larson", "Margaret Martonosi"], "abstract": "Quantum computing (QC) is a new paradigm offering the potential of exponential speedups over classical computing for certain computational problems. Each additional qubit doubles the size of the computational state space available to a QC algorithm. This exponential scaling underlies QC’s power, but today’s Noisy Intermediate-Scale Quantum (NISQ) devices face significant engineering challenges in scalability. The set of quantum circuits that can be reliably run on NISQ devices is limited by their noisy operations and low qubit counts. This paper introduces CutQC, a scalable hybrid computing approach that combines classical computers and quantum computers to enable evaluation of quantum circuits that cannot be run on classical or quantum computers alone. CutQC cuts large quantum circuits into smaller subcircuits, allowing them to be executed on smaller quantum devices. Classical postprocessing can then reconstruct the output of the original circuit. This approach offers significant runtime speedup compared with the only viable current alternative—purely classical simulations—and demonstrates evaluation of quantum circuits that are larger than the limit of QC or classical simulation. Furthermore, in real-system runs, CutQC achieves much higher quantum circuit evaluation fidelity using small prototype quantum computers than the state-of-the-art large NISQ devices achieve. Overall, this hybrid approach allows users to leverage classical and quantum computing resources to evaluate quantum programs far beyond the reach of either one alone.", "doi": "10.1145/3445814.3446758", "arxiv_id": "2012.02333", "pmid": null, "openalex_id": null, "s2_id": "21ff66fca03c404b2778f7280ceb25edeb3905e6", "cited_by": 254, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2012.02333", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446758"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446758", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CALOREE: Learning Control for Predictable Latency and Low Energy", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Nikita Mishra", "Connor Imes", "John D. Lafferty", "Henry Hoffmann"], "abstract": "Many modern computing systems must provide reliable latency with minimal energy. Two central challenges arise when allocating system resources to meet these conflicting goals: (1) complexity modern hardware exposes diverse resources with complicated interactions and (2) dynamics latency must be maintained despite unpredictable changes in operating environment or input. Machine learning accurately models the latency of complex, interacting resources, but does not address system dynamics; control theory adjusts to dynamic changes, but struggles with complex resource interaction. We therefore propose CALOREE, a resource manager that learns key control parameters to meet latency requirements with minimal energy in complex, dynamic en- vironments. CALOREE breaks resource allocation into two sub-tasks: learning how interacting resources affect speedup, and controlling speedup to meet latency requirements with minimal energy. CALOREE deines a general control system whose parameters are customized by a learning framework while maintaining control-theoretic formal guarantees that the latency goal will be met. We test CALOREE's ability to deliver reliable latency on heterogeneous ARM big.LITTLE architectures in both single and multi-application scenarios. Compared to the best prior learning and control solutions, CALOREE reduces deadline misses by 60% and energy consumption by 13%.", "doi": "10.1145/3173162.3173184", "arxiv_id": "https://doi.org/10.1145/3173162.3173184", "pmid": null, "openalex_id": null, "s2_id": "2228b4cb1d342bba8b3c8d000e9105636cb19e55", "cited_by": 113, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3173162.3173184", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173184"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173184", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Wild and Crazy Ideas", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252397", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "2263aeb08319e49a53ed25d32c344b98575c75c0", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Gloss: Seamless Live Reconfiguration and Reoptimization of Stream Programs", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sumanaruban Rajadurai", "Jeffrey Bosboom", "Weng-Fai Wong", "Saman P. Amarasinghe"], "abstract": "An important class of applications computes on long-running or infinite streams of data, often with known fixed data rates. The latter is referred to as synchronous data flow ~(SDF) streams. These stream applications need to run on clusters or the cloud due to the high performance requirement. Further, they require live reconfiguration and reoptimization for various reasons such as hardware maintenance, elastic computation, or to respond to fluctuations in resources or application workload. However, reconfiguration and reoptimization without downtime while accurately preserving program state in a distributed environment is difficult. In this paper, we introduce Gloss, a suite of compiler and runtime techniques for live reconfiguration of distributed stream programs. Gloss, for the first time, avoids periods of zero throughput during the reconfiguration of both stateless and stateful SDF based stream programs. Furthermore, unlike other systems, Gloss globally reoptimizes and completely recompiles the program during reconfiguration. This permits it to reoptimize the application for entirely new configurations that it may not have encountered before. All these Gloss operations happen in-situ, requiring no extra hardware resources. We show how Gloss allows stream programs to reconfigure and reoptimize with no downtime and minimal overhead, and demonstrate the wider applicability of it via a variety of experiments.", "doi": "10.1145/3173162.3173170", "arxiv_id": "https://doi.org/10.1145/3173162.3173170", "pmid": null, "openalex_id": null, "s2_id": "2327e2a6b70578d599654055b55192eb0ab648f3", "cited_by": 22, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173170", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173170"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173170", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Shredder: Learning Noise Distributions to Protect Inference Privacy", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Fatemehsadat Mireshghallah", "Mohammadkazem Taram", "Prakash Ramrakhyani", "Ali Jalali", "Dean M. Tullsen", "Hadi Esmaeilzadeh"], "abstract": "A wide variety of deep neural applications increasingly rely on the cloud to perform their compute-heavy inference. This common practice requires sending private and privileged data over the network to remote servers, exposing it to the service provider and potentially compromising its privacy. Even if the provider is trusted, the data can still be vulnerable over communication channels or via side-channel attacks in the cloud. To that end, this paper aims to reduce the information content of the communicated data with as little as possible compromise on the inference accuracy by making the sent data noisy. An undisciplined addition of noise can significantly reduce the accuracy of inference, rendering the service unusable. To address this challenge, this paper devises Shredder, an end-to-end framework, that, without altering the topology or the weights of a pre-trained network, learns additive noise distributions that significantly reduce the information content of communicated data while maintaining the inference accuracy. The key idea is finding the additive noise distributions by casting it as a disjoint offline learning process with a loss function that strikes a balance between accuracy and information degradation. The loss function also exposes a knob for a disciplined and controlled asymmetric trade-off between privacy and accuracy. While keeping the DNN intact, Shredder divides inference between the cloud and the edge device, striking a balance between computation and communication. In the separate phase of inference, the edge device takes samples from the Laplace distributions that were collected during the proposed offline learning phase and populates a noise tensor with these sampled elements. Then, the edge device merely adds this populated noise tensor to the intermediate results to be sent to the cloud. As such, Shredder enables accurate inference on noisy intermediate data without the need to update the model or the cloud, or any training process during inference. We also formally show that Shredder maximizes privacy with minimal impact on DNN accuracy while the tradeoff between privacy and accuracy is controlled through a mathematical knob. Experimentation with six real-world DNNs from text processing and image classification shows that Shredder reduces the mutual information between the input and the communicated data to the cloud by 74.70% compared to the original execution while only sacrificing 1.58% loss in accuracy. On average, Shredder also offers a speedup of 1.79x over Wi-Fi and 2.17x over LTE compared to cloud-only execution when using an off-the-shelf mobile GPU (Tegra X2) on the edge.", "doi": "10.1145/3373376.3378522", "arxiv_id": "https://doi.org/10.1145/3373376.3378522", "pmid": null, "openalex_id": null, "s2_id": "23918ed366c60ae0ef85b0c80def63127f035e02", "cited_by": 122, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378522", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378522"], "github": ["https://github.com/mireshghallah/shredder-v1", "https://github.com/Koukyosyumei/Attack_SplitNN", "https://github.com/mireshghallah/shredder-v2-self-supervised"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378522", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Understanding Real-World Concurrency Bugs in Go", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tengfei Tu", "Xiaoyu Liu", "Linhai Song", "Yiying Zhang"], "abstract": "Go is a statically-typed programming language that aims to provide a simple, efficient, and safe way to build multi-threaded software. Since its creation in 2009, Go has matured and gained significant adoption in production and open-source software. Go advocates for the usage of message passing as the means of inter-thread communication and provides several new concurrency mechanisms and libraries to ease multi-threading programming. It is important to understand the implication of these new proposals and the comparison of message passing and shared memory synchronization in terms of program errors, or bugs. Unfortunately, as far as we know, there has been no study on Go's concurrency bugs. In this paper, we perform the first systematic study on concurrency bugs in real Go programs. We studied six popular Go software including Docker, Kubernetes, and gRPC. We analyzed 171 concurrency bugs in total, with more than half of them caused by non-traditional, Go-specific problems. Apart from root causes of these bugs, we also studied their fixes, performed experiments to reproduce them, and evaluated them with two publicly-available Go bug detectors. Overall, our study provides a better understanding on Go's concurrency models and can guide future researchers and practitioners in writing better, more reliable Go software and in developing debugging and diagnosis tools for Go.", "doi": "10.1145/3297858.3304069", "arxiv_id": "https://doi.org/10.1145/3297858.3304069", "pmid": null, "openalex_id": null, "s2_id": "246a2af5c477396f52a7af39e3c6a26049ae3310", "cited_by": 97, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304069&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304069"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304069", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Interference Management for Distributed Parallel Applications in Consolidated Clusters", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jaeung Han", "Seungheun Jeon", "Young-ri Choi", "Jaehyuk Huh"], "abstract": "Consolidating multiple applications on a system can improve the overall resource utilization of data center systems. However, such consolidation can adversely affect the performance of some applications due to interference caused by resource contention. Despite many prior studies on the interference effects in single-node systems, the interference behaviors of distributed parallel applications have not been investigated thoroughly. With distributed applications, a local interference in a node can affect the whole execution of an application spanning many nodes. This paper studies an interference modeling methodology for distributed applications to predict their performance under interference effects in consolidated clusters. This study first characterizes the effects of interference for various distributed applications over different interference settings, and analyzes how diverse interference intensities on multiple nodes affect the overall performance. Based on the characterization, this study proposes a static profiling-based model for interference propagation and heterogeneity behaviors. In addition, this paper presents use case studies of the modeling method, two interference-aware placement techniques for consolidated virtual clusters, which attempt to maximize the overall throughput or to guarantee the quality-of-service.", "doi": "10.1145/2872362.2872388", "arxiv_id": "https://doi.org/10.1145/2872362.2872388", "pmid": null, "openalex_id": null, "s2_id": "266224ef32c3b7953532dad1bd82dca289782a9b", "cited_by": 29, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872388"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872388", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SherLock: unsupervised synchronization-operation inference", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Guangpu Li", "Dongjie Chen", "Shan Lu", "Madanlal Musuvathi", "Suman Nath"], "abstract": "Synchronizations are fundamental to the correctness and performance of concurrent software. Unfortunately, correctly identifying all synchronizations has become extremely difficult in modern soft-ware systems due to the various types of synchronizations. Previous work either only infers specific type of synchronization by code analysis or relies on manual effort to annotate the synchronization. This paper proposes SherLock, a tool that uses unsupervised inference to identify synchronizations. SherLock leverages the fact that most synchronizations appear around the conflicting operations and form it into a linear system with a set of synchronization proper-ties and hypotheses. To collect enough observations, SherLock runs the unit tests a small number of times with feedback-based delay injection. We applied SherLock on 8 C# open-source applications. Without any prior knowledge, SherLock inferred 122 unique synchronizations, with few false positives. These inferred synchronizations cover a wide variety of types, including lock operations, fork-join operations, asynchronous operations, framework synchronization, and custom synchronization.", "doi": "10.1145/3445814.3446754", "arxiv_id": "https://doi.org/10.1145/3445814.3446754", "pmid": null, "openalex_id": null, "s2_id": "26d063c593cd9e8cb950b8864146818e8ffffd57", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446754"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446754", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Automatic Matching of Legacy Code to Heterogeneous APIs: An Idiomatic Approach", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Philip Ginsbach", "Toomas Remmelg", "Michel Steuwer", "Bruno Bodin", "Christophe Dubach", "Michael F. P. O'Boyle"], "abstract": "Heterogeneous accelerators often disappoint. They provide the prospect of great performance, but only deliver it when using vendor specific optimized libraries or domain specific languages. This requires considerable legacy code modifications, hindering the adoption of heterogeneous computing. This paper develops a novel approach to automatically detect opportunities for accelerator exploitation. We focus on calculations that are well supported by established APIs: sparse and dense linear algebra, stencil codes and generalized reductions and histograms. We call them idioms and use a custom constraint-based Idiom Description Language (IDL) to discover them within user code. Detected idioms are then mapped to BLAS libraries, cuSPARSE and clSPARSE and two DSLs: Halide and Lift. We implemented the approach in LLVM and evaluated it on the NAS and Parboil sequential C/C++ benchmarks, where we detect 60 idiom instances. In those cases where idioms are a significant part of the sequential execution time, we generate code that achieves 1.26x to over 20x speedup on integrated and external GPUs.", "doi": "10.1145/3173162.3173182", "arxiv_id": "https://doi.org/10.1145/3173162.3173182", "pmid": null, "openalex_id": null, "s2_id": "26dcb23d98167136cd680ee3ba6ed8ce50cf825e", "cited_by": 41, "type": "conference", "is_oa": true, "pdf_urls": ["http://eprints.gla.ac.uk/156406/7/156406.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173182"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173182", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Qraft: reverse your Quantum circuit and know the correct program output", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tirthak Patel", "Devesh Tiwari"], "abstract": "Current Noisy Intermediate-Scale Quantum (NISQ) computers are useful in developing the quantum computing stack, test quantum algorithms, and establish the feasibility of quantum computing. However, different statistically significant errors permeate NISQ computers. To reduce the effect of these errors, recent research has focused on effective mapping of a quantum algorithm to a quantum computer in an error-and-constraints-aware manner. We propose the first work, QRAFT, to leverage the reversibility property of quantum algorithms to considerably reduce the error beyond the reduction achieved by effective circuit mapping.", "doi": "10.1145/3445814.3446743", "arxiv_id": "https://doi.org/10.1145/3445814.3446743", "pmid": null, "openalex_id": null, "s2_id": "271d9a052fbd5811eb3833ce8415259651e8ab17", "cited_by": 61, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446743"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446743", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Programming Uncertain jhings", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": null, "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "2730dffe3d6402e8ab1e737be7f68738b675e4ae", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 3B: Security I", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252396", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "27f91197f4b4dc79dd40edb08468d95f47cfdf67", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "BCD deduplication: effective memory compression using partial cache-line deduplication", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sungbo Park", "Ingab Kang", "Yaebin Moon", "Jung Ho Ahn", "G. Edward Suh"], "abstract": "In this paper, we identify new partial data redundancy among multiple cache lines that are not exploited by traditional memory compression or memory deduplication. We propose Base and Compressed Difference (BCD) deduplication that effectively utilizes the partial matches among cache lines through a novel combination of compression and deduplication to increase the effective capacity of main memory. Experimental results show that BCD achieves the average compression ratio of 1.94× for SPEC2017, DaCapo, TPC-DS, and TPC-H, which is 48.4% higher than the best prior work. We also present an efficient implementation of BCD in a modern memory hierarchy, which compresses data in both the last-level cache (LLC) and main memory with modest area overhead. Even with additional meta-data accesses and compression/deduplication operations, cycle-level simulations show that BCD improves the performance of the SPEC2017 benchmarks by 2.7% on average because it increases the effective capacity of the LLC. Overall, the results show that BCD can significantly increase the capacity of main memory with little performance overhead.", "doi": "10.1145/3445814.3446722", "arxiv_id": "https://doi.org/10.1145/3445814.3446722", "pmid": null, "openalex_id": null, "s2_id": "282d0e5c49be4b8b96626ee29032063c52c68641", "cited_by": 22, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.7298/3287-6w76", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446722"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446722", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 2B: Reliability and Debugging I", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252394", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "291ea5a53e0b197b11aded7450631a6f84eab556", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ProteusTM: Abstraction Meets Performance in Transactional Memory", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Diego Didona", "Nuno Diegues", "Anne-Marie Kermarrec", "Rachid Guerraoui", "Ricardo Neves", "Paolo Romano"], "abstract": "The Transactional Memory (TM) paradigm promises to greatly simplify the development of concurrent applications. This led, over the years, to the creation of a plethora of TM implementations delivering wide ranges of performance across workloads. Yet, no universal implementation fits each and every workload. In fact, the best TM in a given workload can reveal to be disastrous for another one. This forces developers to face the complex task of tuning TM implementations, which significantly hampers their wide adoption. In this paper, we address the challenge of automatically identifying the best TM implementation for a given workload. Our proposed system, ProteusTM, hides behind the TM interface a large library of implementations. Underneath, it leverages a novel multi-dimensional online optimization scheme, combining two popular learning techniques: Collaborative Filtering and Bayesian Optimization.", "doi": "10.1145/2872362.2872385", "arxiv_id": "https://doi.org/10.1145/2872362.2872385", "pmid": null, "openalex_id": null, "s2_id": "2ae2684f120dab4c319e30d33b33e7adf384810a", "cited_by": 36, "type": "conference", "is_oa": true, "pdf_urls": ["http://infoscience.epfl.ch/record/221890", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872385"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872385", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3575693.3575747", "arxiv_id": "2107.06419", "pmid": null, "openalex_id": null, "s2_id": "2b38ddff8e24a07597c8d042ea7b8b85a678e9b2", "cited_by": 115, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3575693.3575747"], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Typed Architectures: Architectural Support for Lightweight Scripting", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Channoh Kim", "Jaehyeok Kim", "Sungmin Kim", "Doo-Young Kim", "Namho Kim", "Gitae Na", "Young H. Oh", "Hyeon-Gyu Cho", "Jae W. Lee"], "abstract": "Dynamic scripting languages are becoming more and more widely adopted not only for fast prototyping but also for developing production-grade applications. They provide high-productivity programming environments featuring high levels of abstraction with powerful built-in functions, automatic memory management, object-oriented programming paradigm and dynamic typing. However, their flexible, dynamic type systems easily become the source of inefficiency in terms of instruction count, memory footprint, and energy consumption. This overhead makes it challenging to deploy these high-productivity programming technologies on emerging single-board computers for IoT applications. Addressing this challenge, this paper introduces Typed Architectures, a high-efficiency, low-cost execution substrate for dynamic scripting languages, where each data variable retains high-level type information at an ISA level. Typed Architectures calculate and check the dynamic type of each variable implicitly in hardware, rather than explicitly in software, hence significantly reducing instruction count for dynamic type checking. Besides, Typed Architectures introduce polymorphic instructions (e.g., xadd), which are bound to the correct native instruction at runtime within the pipeline (e.g., add or fadd) to efficiently implement polymorphic operators. Finally, Typed Architectures provide hardware support for flexible yet efficient type tag extraction and insertion, capturing common data layout patterns of tag-value pairs. Our evaluation using a fully synthesizable RISC-V RTL design on FPGA shows that Typed Architectures achieve geomean speedups of 11.2% and 9.9% with maximum speedups of 32.6% and 43.5% for two production-grade scripting engines for JavaScript and Lua, respectively. Moreover, Typed Architectures improve the energy-delay product (EDP) by 19.3% for JavaScript and 16.5% for Lua with an area overhead of 1.6% at a 40nm technology node.", "doi": "10.1145/3037697.3037726", "arxiv_id": "https://doi.org/10.1145/3037697.3037726", "pmid": null, "openalex_id": null, "s2_id": "2c7cd28ce7222ac733703b79a1761066201d6419", "cited_by": 11, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037726"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037726", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Moonwalk: NRE Optimization in ASIC Clouds", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Moein Khazraee", "Lu Zhang", "Luis Vega", "Michael Bedford Taylor"], "abstract": "Cloud services are becoming increasingly globalized and data-center workloads are expanding exponentially. GPU and FPGA-based clouds have illustrated improvements in power and performance by accelerating compute-intensive workloads. ASIC-based clouds are a promising way to optimize the Total Cost of Ownership (TCO) of a given datacenter computation (e.g. YouTube transcoding) by reducing both energy consumption and marginal computation cost.", "doi": "10.1145/3037697.3037749", "arxiv_id": "https://doi.org/10.1145/3037697.3037749", "pmid": null, "openalex_id": null, "s2_id": "2d6222ee8f5ac92b9ca9bc5b7eb0341d1e3c9c58", "cited_by": 56, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037749"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037749", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3093337", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "2d99487fbb8a3d788cab7f05643651de20eaa87c", "cited_by": 1, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Accelerometer: Understanding Acceleration Opportunities for Data Center Overheads at Hyperscale", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Akshitha Sriraman", "Abhishek Dhanotia"], "abstract": "At global user population scale, important microservices in warehouse-scale data centers can grow to account for an enormous installed base of servers. With the end of Dennard scaling, successive server generations running these microservices exhibit diminishing performance returns. Hence, it is imperative to understand how important microservices spend their CPU cycles to determine acceleration opportunities across the global server fleet. To this end, we first undertake a comprehensive characterization of the top seven microservices that run on the compute-optimized data center fleet at Facebook. Our characterization reveals that microservices spend as few as 18% of CPU cycles executing core application logic (e.g., performing a key-value store); the remaining cycles are spent in common operations that are not core to the application logic (e.g., I/O processing, logging, and compression). Accelerating such common building blocks can greatly improve data center performance. Whereas developing specialized hardware acceleration for each building block might be beneficial, it becomes risky at scale if these accelerators do not yield expected gains due to performance bounds precipitated by offload-induced overheads. To identify such performance bounds early in the hardware design phase, we develop an analytical model, Accelerometer, for hardware acceleration that projects realistic speedup in microservices. We validate Accelerometer's utility in production using three retrospective case studies and demonstrate how it estimates the real speedup with ≤ 3.7% error. We then use Accelerometer to project gains from accelerating important common building blocks identified by our characterization.", "doi": "10.1145/3373376.3378450", "arxiv_id": "https://doi.org/10.1145/3373376.3378450", "pmid": null, "openalex_id": null, "s2_id": "2ddcb089c3af5d726676f56d7caf1f4ccad2c81a", "cited_by": 127, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378450"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378450", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hurdle: Securing Jump Instructions Against Code Reuse Attacks", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Christian DeLozier", "Kavya Lakshminarayanan", "Gilles Pokam", "Joseph Devietti"], "abstract": "Code-reuse attacks represent the state-of-the-art in exploiting memory safety vulnerabilities. Control-flow integrity techniques offer a promising direction for preventing code-reuse attacks, but these attacks are resilient against imprecise and heuristic-based detection and prevention mechanisms.", "doi": "10.1145/3373376.3378506", "arxiv_id": "https://doi.org/10.1145/3373376.3378506", "pmid": null, "openalex_id": null, "s2_id": "2de9eedffa5812b612b4a0be1a39601ad2916cb4", "cited_by": 9, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378506", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378506"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378506", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Dynamic Resource Management for Efficient Utilization of Multitasking GPUs", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jason Jong Kyu Park", "Yongjun Park", "Scott A. Mahlke"], "abstract": "As graphics processing units (GPUs) are broadly adopted, running multiple applications on a GPU at the same time is beginning to attract wide attention. Recent proposals on multitasking GPUs have focused on either spatial multitasking, which partitions GPU resource at a streaming multiprocessor (SM) granularity, or simultaneous multikernel (SMK), which runs multiple kernels on the same SM. However, multitasking performance varies heavily depending on the resource partitions within each scheme, and the application mixes. In this paper, we propose GPU Maestro that performs dynamic resource management for efficient utilization of multitasking GPUs. GPU Maestro can discover the best performing GPU resource partition exploiting both spatial multitasking and SMK. Furthermore, dynamism within a kernel and interference between the kernels are automatically considered because GPU Maestro finds the best performing partition through direct measurements. Evaluations show that GPU Maestro can improve average system throughput by 20.2% and 13.9% over the baseline spatial multitasking and SMK, respectively.", "doi": "10.1145/3037697.3037707", "arxiv_id": "https://doi.org/10.1145/3037697.3037707", "pmid": null, "openalex_id": null, "s2_id": "2e035b44c58eb9c24809d5af8c96162eed25358a", "cited_by": 87, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3037697.3037707", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037707"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037707", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Scalable FSM parallelization via path fusion and higher-order speculation", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Junqiao Qiu", "Xiaofan Sun", "Amir Hossein Nodehi Sabet", "Zhijia Zhao"], "abstract": "Finite-state machine (FSM) is a fundamental computation model used by many applications. However, FSM execution is known to be “embarrassingly sequential” due to the state dependences among transitions. Existing solutions leverage enumerative or speculative parallelization to break the dependences. However, the efficiency of both parallelization schemes highly depends on the properties of the FSM and its inputs. For those exhibiting unfavorable properties, the former suffers from the overhead of maintaining multiple execution paths, while the latter is bottlenecked by the serial reprocessing among the misspeculation cases. Either way, the FSM parallelization scalability is seriously compromised. This work addresses the above scalability challenges with two novel techniques. First, for enumerative parallelization, it proposes path fusion. Inspired by the classic NFA to DFA conversion, it maps a vector of states in the original FSM to a new (fused) state. In this way, path fusion can reduce multiple FSM execution paths into a single path, minimizing the overhead of path maintenance. Second, for speculative parallelization, this work introduces higher-order speculation to avoid the serial reprocessing during validations. This is a generalized speculation model that allows speculated states to be validated speculatively. Finally, this work integrates different schemes of FSM parallelization into a framework—BoostFSM, which automatically selects the best based on the relevant properties of the FSM. Evaluation using real-world FSMs with diverse characteristics shows that BoostFSM can raise the average speedup from 3.1× and 15.4× of the existing speculative and enumerative parallelization schemes, respectively, to 25.8× on a 64-core machine.", "doi": "10.1145/3445814.3446705", "arxiv_id": "https://doi.org/10.1145/3445814.3446705", "pmid": null, "openalex_id": null, "s2_id": "2eb96b495624edb25391636faa4a039b931c45e9", "cited_by": 20, "type": "conference", "is_oa": true, "pdf_urls": ["https://zenodo.org/records/4322296/files/Artifacts.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446705"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446705", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DATS - Data Containers for Web Applications", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Casen Hunger", "Lluís Vilanova", "Charalampos Papamanthou", "Yoav Etsion", "Mohit Tiwari"], "abstract": "Data containers enable users to control access to their data while untrusted applications compute on it. However, they require replicating an application inside each container - compromising functionality, programmability, and performance. We propose DATS - a system to run web applications that retains application usability and efficiency through a mix of hardware capability enhanced containers and the introduction of two new primitives modeled after the popular model-view-controller (MVC) pattern. (1) DATS introduces a templating language to create views that compose data across data containers. (2) DATS uses authenticated storage and confinement to enable an untrusted storage service, such as memcached and deduplication, to operate on plain-text data across containers. These two primitives act as robust declassifiers that allow DATS to enforce non-interference across containers, taking large applications out of the trusted computing base (TCB). We showcase eight different web applications including Gitlab and a Slack-like chat, significantly improve the worst-case overheads due to application replication, and demonstrate usable performance for common-case usage.", "doi": "10.1145/3173162.3173213", "arxiv_id": "https://doi.org/10.1145/3173162.3173213", "pmid": null, "openalex_id": null, "s2_id": "2ee2e8a704952051ed8a01386af7038944f664b5", "cited_by": 11, "type": "conference", "is_oa": true, "pdf_urls": ["https://zenodo.org/record/3503955", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173213"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173213", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "An Analysis of Persistent Memory Use with WHISPER", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sanketh Nalli", "Swapnil Haria", "Mark D. Hill", "Michael M. Swift", "Haris Volos", "Kimberly Keeton"], "abstract": "Emerging non-volatile memory (NVM) technologies promise durability with read and write latencies comparable to volatile memory (DRAM). We define Persistent Memory (PM) as NVM accessed with byte addressability at low latency via normal memory instructions. Persistent-memory applications ensure the consistency of persistent data by inserting ordering points between writes to PM allowing the construction of higher-level transaction mechanisms. An epoch is a set of writes to PM between ordering points.", "doi": "10.1145/3037697.3037730", "arxiv_id": "https://doi.org/10.1145/3037697.3037730", "pmid": null, "openalex_id": null, "s2_id": "2f94e7613656d5cd0a7d67e6cfb582be458a8521", "cited_by": 197, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037730"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037730", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Seer: Leveraging Big Data to Navigate the Complexity of Performance Debugging in Cloud Microservices", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yu Gan", "Yanqi Zhang", "Kelvin Hu", "Dailun Cheng", "Yuan He", "Meghna Pancholi", "Christina Delimitrou"], "abstract": "Performance unpredictability is a major roadblock towards cloud adoption, and has performance, cost, and revenue ramifications. Predictable performance is even more critical as cloud services transition from monolithic designs to microservices. Detecting QoS violations after they occur in systems with microservices results in long recovery times, as hotspots propagate and amplify across dependent services. We present Seer, an online cloud performance debugging system that leverages deep learning and the massive amount of tracing data cloud systems collect to learn spatial and temporal patterns that translate to QoS violations. Seer combines lightweight distributed RPC-level tracing, with detailed low-level hardware monitoring to signal an upcoming QoS violation, and diagnose the source of unpredictable performance. Once an imminent QoS violation is detected, Seer notifies the cluster manager to take action to avoid performance degradation altogether. We evaluate Seer both in local clusters, and in large-scale deployments of end-to-end applications built with microservices with hundreds of users. We show that Seer correctly anticipates QoS violations 91% of the time, and avoids the QoS violation to begin with in 84% of cases. Finally, we show that Seer can identify application-level design bugs, and provide insights on how to better architect microservices to achieve predictable performance.", "doi": "10.1145/3297858.3304004", "arxiv_id": "https://doi.org/10.1145/3297858.3304004", "pmid": null, "openalex_id": null, "s2_id": "30706b8bd5e030f39f65baf5ff06fc820b8f265e", "cited_by": 341, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304004", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304004"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304004", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Watching for Software Inefficiencies with Witch", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shasha Wen", "Xu Liu", "John Byrne", "Milind Chabbi"], "abstract": "Inefficiencies abound in complex, layered software. A variety of inefficiencies show up as wasteful memory operations. Many existing tools instrument every load and store instruction to monitor memory, which significantly slows execution and consumes enormously extra memory. Our lightweight framework, Witch, samples consecutive accesses to the same memory location by exploiting two ubiquitous hardware features: the performance monitoring units (PMU) and debug registers. Witch performs no instrumentation. Hence, witchcraft---tools built atop Witch---can detect a variety of software inefficiencies while introducing negligible slowdown and insignificant memory consumption and yet maintaining accuracy comparable to exhaustive instrumentation tools. Witch allowed us to scale our analysis to a large number of code bases. Guided by witchcraft, we detected several performance problems in important code bases; eliminating these inefficiencies resulted in significant speedups.", "doi": "10.1145/3173162.3177159", "arxiv_id": "https://doi.org/10.1145/3173162.3177159", "pmid": null, "openalex_id": null, "s2_id": "30868ee94d410fef27d3d00e423a330480eea4e3", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3177159&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177159"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177159", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Design and Operation of Shared Machine Learning Clusters on Campus", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3669940.3707266", "arxiv_id": "2110.01556", "pmid": null, "openalex_id": null, "s2_id": "310fb2e833acbd15925c91c2d113654acae78f0b", "cited_by": 41, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Enhancing Cross-ISA DBT Through Automatically Learned Translation Rules", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Wenwen Wang", "Stephen McCamant", "Antonia Zhai", "Pen-Chung Yew"], "abstract": "This paper presents a novel approach for dynamic binary translation (DBT) to automatically learn translation rules from guest and host binaries compiled from the same source code. The learned translation rules are then verified via binary symbolic execution and used in an existing DBT system, QEMU, to generate more efficient host binary code. Experimental results on SPEC CINT2006 show that the average time of learning a translation rule is less than two seconds. With the rules learned from a collection of benchmark programs excluding the targeted program itself, an average 1.25X performance speedup over QEMU can be achieved for SPEC CINT2006. Moreover, the translation overhead introduced by this rule-based approach is very small even for short-running workloads.", "doi": "10.1145/3173162.3177160", "arxiv_id": "https://doi.org/10.1145/3173162.3177160", "pmid": null, "openalex_id": null, "s2_id": "31284eda208c225f41987d33c77f547f1e1135ce", "cited_by": 23, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3177160", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177160"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177160", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Voltage Regulator Efficiency Aware Power Management", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yuxin Bai", "Victor W. Lee", "Engin Ipek"], "abstract": "Conventional off-chip voltage regulators are typically bulky and slow, and are inefficient at exploiting system and workload variability using Dynamic Voltage and Frequency Scaling (DVFS). On-die integration of voltage regulators has the potential to increase the energy efficiency of computer systems by enabling power control at a fine granularity in both space and time. The energy conversion efficiency of on-chip regulators, however, is typically much lower than off-chip regulators, which results in significant energy losses. Fine-grained power control and high voltage regulator efficiency are difficult to achieve simultaneously, with either emerging on-chip or conventional off-chip regulators.", "doi": "10.1145/3037697.3037717", "arxiv_id": "https://doi.org/10.1145/3037697.3037717", "pmid": null, "openalex_id": null, "s2_id": "322448d81cc6785dfbd32db2b46a0b1d68c2c6d6", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.1145/3093315.3037717", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037717"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037717", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Nils Asmussen", "Marcus Völp", "Benedikt Nöthen", "Hermann Härtig", "Gerhard P. Fettweis"], "abstract": "In the last decade, the number of available cores increased and heterogeneity grew. In this work, we ask the question whether the design of the current operating systems (OSes) is still appropriate if these trends continue and lead to abundantly available but heterogeneous cores, or whether it forces a fundamental rethinking of how systems are designed. We argue that: 1. hiding heterogeneity behind a common hardware interface unifies, to a large extent, the control and coordination of cores and accelerators in the OS, 2. isolating at the network-on-chip rather than with processor features (like privileged mode, memory management unit, ...), allows running untrusted code on arbitrary cores, and 3. providing OS services via protocols over the network-on-chip, instead of via system calls, makes them accessible to arbitrary types of cores as well.", "doi": "10.1145/2872362.2872371", "arxiv_id": "https://doi.org/10.1145/2872362.2872371", "pmid": null, "openalex_id": null, "s2_id": "32bd15d39a63696ffa6fb11e2c2bb60f6355c6ae", "cited_by": 82, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872371"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872371", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DiGraph: An Efficient Path-based Iterative Directed Graph Processing System on Multiple GPUs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yu Zhang", "Xiaofei Liao", "Hai Jin", "Bingsheng He", "Haikun Liu", "Lin Gu"], "abstract": "10.1145/3297858.3304029", "doi": "10.1145/3297858.3304029", "arxiv_id": "https://doi.org/10.1145/3297858.3304029", "pmid": null, "openalex_id": null, "s2_id": "33558f35e826af941c4c919cb50fb75a265f4879", "cited_by": 48, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304029"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304029", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "C11Tester: a race detector for C/C++ atomics", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Weiyu Luo", "Brian Demsky"], "abstract": "Writing correct concurrent code that uses atomics under the C/C++ memory model is extremely difficult. We present C11Tester, a race detector for the C/C++ memory model that can explore executions in a larger fragment of the C/C++ memory model than previous race detector tools. Relative to previous work, C11Tester's larger fragment includes behaviors that are exhibited by ARM processors. C11Tester uses a new constraint-based algorithm to implement modification order that is optimized to allow C11Tester to make decisions in terms of application-visible behaviors. We evaluate C11Tester on several benchmark applications, and compare C11Tester's performance to both tsan11rec, the state of the art tool that controls scheduling for C/C++; and tsan11, the state of the art tool that does not control scheduling.", "doi": "10.1145/3445814.3446711", "arxiv_id": "2102.07901", "pmid": null, "openalex_id": null, "s2_id": "34098c132acf4e1743fa7f0539a3f22b8a9ef0cd", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446711", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446711"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446711", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Maximizing Performance Under a Power Cap: A Comparison of Hardware, Software, and Hybrid Techniques", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Huazhe Zhang", "Henry Hoffmann"], "abstract": "Power and thermal dissipation constrain multicore performance scaling. Modern processors are built such that they could sustain damaging levels of power dissipation, creating a need for systems that can implement processor power caps. A particular challenge is developing systems that can maximize performance within a power cap, and approaches have been proposed in both software and hardware. Software approaches are flexible, allowing multiple hardware resources to be coordinated for maximum performance, but software is slow, requiring a long time to converge to the power target. In contrast, hardware power capping quickly converges to the the power cap, but only manages voltage and frequency, limiting its potential performance. In this work we propose PUPiL, a hybrid software/hardware power capping system. Unlike previous approaches, PUPiL combines hardware's fast reaction time with software's flexibility. We implement PUPiL on real Linux/x86 platform and compare it to Intel's commercial hardware power capping system for both single and multi-application workloads. We find PUPiL provides the same reaction time as Intel's hardware with significantly higher performance. On average, PUPiL outperforms hardware by from 1:18-2:4 depending on workload and power target. Thus, PUPiL provides a promising way to enforce power caps with greater performance than current state-of-the-art hardware-only approaches.", "doi": "10.1145/2872362.2872375", "arxiv_id": "https://doi.org/10.1145/2872362.2872375", "pmid": null, "openalex_id": null, "s2_id": "3462fb38042f0bde20c758728d7c8c28a1f47e09", "cited_by": 187, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872375"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872375", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Elaheh Sadredini", "Reza Rahimi", "Marzieh Lenjani", "Mircea Stan", "Kevin Skadron"], "abstract": "Pattern matching, especially for complex patterns with many variations, is an important task in many big-data applications and maps well to finite automata. Recently, a variety of research has focused on hardware acceleration of automata processing, especially via spatial architectures that directly map the patterns to massively parallel hardware elements, such as in FPGAs and in-memory solutions. We observed that all existing automata-acceleration architectures are designed based on fixed, 8-bit symbol processing, derived from ASCII processing. However, the alphabet size in pattern-matching applications varies from just a few up to billions of unique symbols. This makes it difficult to provide a universal and efficient mapping of this wide variety of automata applications to existing automata accelerators.", "doi": "10.1145/3373376.3378459", "arxiv_id": "https://doi.org/10.1145/3373376.3378459", "pmid": null, "openalex_id": null, "s2_id": "349d1a753ee0f66e56c32eab742bc35b8b6fd603", "cited_by": 24, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378459", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378459"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378459", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Identifying Security Critical Properties for the Dynamic Verification of a Processor", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Rui Zhang", "Natalie Stanley", "Christopher Griggs", "Andrew Chi", "Cynthia Sturton"], "abstract": "We present a methodology for identifying security critical properties for use in the dynamic verification of a processor. Such verification has been shown to be an effective way to prevent exploits of vulnerabilities in the processor, given a meaningful set of security properties. We use known processor errata to establish an initial set of security-critical invariants of the processor. We then use machine learning to infer an additional set of invariants that are not tied to any particular, known vulnerability, yet are critical to security.", "doi": "10.1145/3037697.3037734", "arxiv_id": "https://doi.org/10.1145/3037697.3037734", "pmid": null, "openalex_id": null, "s2_id": "36b77ca215e1a04cd7ffcb27fdc88118cde48855", "cited_by": 40, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037734&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037734"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037734", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fast local page-tables for virtualized NUMA servers with vMitosis", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ashish Panwar", "Reto Achermann", "Arkaprava Basu", "Abhishek Bhattacharjee", "K. Gopinath", "Jayneel Gandhi"], "abstract": "Increasing heterogeneity in the memory system mandates careful data placement to hide the non-uniform memory access (NUMA) effects on applications. However, NUMA optimizations have predominantly focused on application data in the past decades, largely ignoring the placement of kernel data structures due to their small memory footprint; this is evident in typical OS designs that pin kernel objects in memory. In this paper, we show that careful placement of kernel data structures is gaining importance in the context of page-tables: sub-optimal placement of page-tables causes severe slowdown (up to 3.1x) on virtualized NUMA servers.", "doi": "10.1145/3445814.3446709", "arxiv_id": "https://doi.org/10.1145/3445814.3446709", "pmid": null, "openalex_id": null, "s2_id": "37328625790260692f741224a71c6efac817d57b", "cited_by": 36, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446709"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446709", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Optimus Prime: Accelerating Data Transformation in Servers", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Arash Pourhabibi Zarandi", "Siddharth Gupta", "Hussein Kassir", "Mark Sutherland", "Zilu Tian", "Mario Paulo Drumond", "Babak Falsafi", "Christoph Koch"], "abstract": "Modern online services are shifting away from monolithic applications to loosely-coupled microservices because of their improved scalability, reliability, programmability and development velocity. Microservices communicating over the datacenter network require data transformation (DT) to convert messages back and forth between their internal formats. This work identifies DT as a bottleneck due to reductions in latency of the surrounding system components, namely application runtimes, protocol stacks, and network hardware. We therefore propose Optimus Prime (OP), a programmable DT accelerator that uses a novel abstraction, an in-memory schema, to represent DT operations. The schema is compatible with today's DT frameworks and enables any compliant accelerator to perform the transformations comprising a request in parallel. Our evaluation shows that OP's DT throughput matches the line rate of today's NICs and has ~60x higher throughput compared to software, at a tiny fraction of the CPU's silicon area and power. We also evaluate a set of microservices running on Thrift, and show up to 30% reduction in service latency.", "doi": "10.1145/3373376.3378501", "arxiv_id": "https://doi.org/10.1145/3373376.3378501", "pmid": null, "openalex_id": null, "s2_id": "37b2a9fa9c7df56e95ea2ea8449d45433f255eb9", "cited_by": 65, "type": "conference", "is_oa": true, "pdf_urls": ["https://infoscience.epfl.ch/record/274129/files/asplos20-op-pourhabibi-acm.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378501"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378501", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Enclosure: language-based restriction of untrusted libraries", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Adrien Ghosn", "Marios Kogias", "Mathias Payer", "James R. Larus", "Edouard Bugnion"], "abstract": "Programming languages and systems have failed to address the security implications of the increasingly frequent use of public libraries to construct modern software. Most languages provide tools and online repositories to publish, import, and use libraries; however, this double-edged sword can incorporate a large quantity of unknown, unchecked, and unverified code into an application. The risk is real, as demonstrated by malevolent actors who have repeatedly inserted malware into popular open-source libraries. This paper proposes a solution: enclosures, a new programming language construct for library isolation that provides a developer with fine-grain control over the resources that a library can access, even for libraries with complex inter-library dependencies. The programming abstraction is language-independent and could be added to most languages. These languages would then be able to take advantage of hardware isolation mechanisms that are effective across language boundaries. The enclosure policies are enforced at run time by LitterBox, a language-independent framework that uses hardware mechanisms to provide uniform and robust isolation guarantees, even for libraries written in unsafe languages. LitterBox currently supports both Intel VT-x (with general-purpose extended page tables) and the emerging Intel Memory Protection Keys (MPK). We describe an enclosure implementation for the Go and Pythonlanguages. Our evaluation demonstrates that the Go implementation can protect sensitive data in real-world applications constructed using complex untrusted libraries with deep dependencies. It requires minimal code refactoring and incurs acceptable performance overhead. The Python implementation demonstrates LitterBox’s ability to support dynamic languages.", "doi": "10.1145/3445814.3446728", "arxiv_id": "https://doi.org/10.1145/3445814.3446728", "pmid": null, "openalex_id": null, "s2_id": "39183d2ee0cf495a9d53b6fd6e9390d471a14a8e", "cited_by": 43, "type": "conference", "is_oa": true, "pdf_urls": ["https://infoscience.epfl.ch/handle/20.500.14299/175288", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446728"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446728", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 4A: Distributed Systems", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248620", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "39750032f979a0a60f22079bbb0f8dce73b48ec1", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zelalem Birhanu Aweke", "Salessawi Ferede Yitbarek", "Rui Qiao", "Reetuparna Das", "Matthew Hicks", "Yossi Oren", "Todd M. Austin"], "abstract": "Ensuring the integrity and security of the memory system is critical. Recent studies have shown serious security concerns due to \"rowhammer\" attacks, where repeated accesses to a row of memory cause bit flips in adjacent rows. Recent work by Google's Project Zero has shown how to leverage rowhammer-induced bit-flips as the basis for security exploits that include malicious code injection and memory privilege escalation. Being an important security concern, industry has attempted to defend against rowhammer attacks. Deployed defenses employ two strategies: (1) doubling the system DRAM refresh rate and (2) restricting access to the CLFLUSH instruction that attackers use to bypass the cache to increase memory access frequency (i.e., the rate of rowhammering). We demonstrate that such defenses are inadequte: we implement rowhammer attacks that both avoid using the CLFLUSH instruction and cause bit flips with a doubled refresh rate. Our next-generation CLFLUSH-free rowhammer attack bypasses the cache by manipulating cache replacement state to allow frequent misses out of the last-level cache to DRAM rows of our choosing.", "doi": "10.1145/2872362.2872390", "arxiv_id": "https://doi.org/10.1145/2872362.2872390", "pmid": null, "openalex_id": null, "s2_id": "3b3832a3c6eab569497bb29d8cfd1682c9a6a457", "cited_by": 237, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872390"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872390", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Myungsuk Kim", "Jisung Park", "Genhee Cho", "Yoona Kim", "Lois Orosa", "Onur Mutlu", "Jihong Kim"], "abstract": "As data privacy and security rapidly become key requirements, securely erasing data from a storage system becomes as important as reliably storing data in the system. Unfortunately, in modern flash-based storage systems, it is challenging to irrecoverably erase (i.e., sanitize) a file without large performance or reliability penalties. In this paper, we propose Evanesco, a new data sanitization technique specifically designed for high-density 3D NAND flash memory. Unlike existing techniques that physically destroy stored data, Evanesco provides data sanitization by blocking access to stored data. By exploiting existing spare flash cells in the flash memory chip, Evanesco efficiently supports two new flash lock commands (pLock and bLock) that disable access to deleted data at both page and block granularities. Since the locked page (or block) can be unlocked only after its data is erased, Evanesco provides a strong security guarantee even against an advanced threat model. To evaluate our technique, we build SecureSSD, an Evanesco-enabled emulated flash storage system. Our experimental results show that SecureSSD can effectively support data sanitization with a small performance overhead and no reliability degradation.", "doi": "10.1145/3373376.3378490", "arxiv_id": "https://doi.org/10.1145/3373376.3378490", "pmid": null, "openalex_id": null, "s2_id": "3b3f1ca033b549ba39255652ae7f7b2c644e2b5b", "cited_by": 35, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378490"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378490", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Computing with time: microarchitectural weird machines", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dmitry Evtyushkin", "Thomas Benjamin", "Jesse Elwell", "Jeffrey A. Eitel", "Angelo Sapello", "Abhrajit Ghosh"], "abstract": "Side-channel attacks such as Spectre rely on properties of modern CPUs that permit discovery of microarchitectural state via timing of various operations. The Weird Machine concept is an increasingly popular model for characterization of emergent execution that arises from side-effects of conventional computing constructs. In this work we introduce Microarchitectural Weird Machines (µWM): code constructions that allow performing computation through the means of side effects and conflicts between microarchitectual entities such as branch predictors and caches. The results of such computations are observed as timing variations. We demonstrate how µWMs can be used as a powerful obfuscation engine where computation operates based on events unobservable to conventional anti-obfuscation tools based on emulation, debugging, static and dynamic analysis techniques. We demonstrate that µWMs can be used to reliably perform arbitrary computation by implementing a SHA-1 hash function. We then present a practical example in which we use a µWM to obfuscate malware code such that its passive operation is invisible to an observer with full power to view the architectural state of the system until the code receives a trigger. When the trigger is received the malware decrypts and executes its payload. To show the effectiveness of obfuscation we demonstrate its use in the concealment and subsequent execution of a payload that exfiltrates a shadow password file, and a payload that creates a reverse shell.", "doi": "10.1145/3445814.3446729", "arxiv_id": "https://doi.org/10.1145/3445814.3446729", "pmid": null, "openalex_id": null, "s2_id": "3b52891f5b3973fe58f7b424cef1db52cabece90", "cited_by": 15, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446729"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446729", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Wonderland: A Novel Abstraction-Based Out-Of-Core Graph Processing System", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mingxing Zhang", "Yongwei Wu", "Youwei Zhuo", "Xuehai Qian", "Chengying Huan", "Kang Chen"], "abstract": "Many important graph applications are iterative algorithms that repeatedly process the input graph until convergence. For such algorithms, graph abstraction is an important technique: although much smaller than the original graph, it can bootstrap an initial result that can significantly accelerate the final convergence speed, leading to a better overall performance. However, existing graph abstraction techniques typically assume either fully in-memory or distributed environment, which leads to many obstacles preventing the application to an out-of-core graph processing system. In this paper, we propose Wonderland, a novel out-of-core graph processing system based on abstraction. Wonderland has three unique features: 1) A simple method applicable to out-of-core systems allowing users to extract effective abstractions from the original graph with acceptable cost and a specific memory limit; 2) Abstraction-enabled information propagation, where an abstraction can be used as a bridge over the disjoint on-disk graph partitions; 3) Abstraction guided priority scheduling, where an abstraction can infer the better priority-based order in processing on-disk graph partitions. Wonderland is a significant advance over the state-of-the-art because it not only makes graph abstraction feasible to out-of-core systems, but also broadens the applications of the concept in important ways. Evaluation results of Wonderland reveal that Wonderland achieves a drastic speedup over the other state-of-the-art systems, up to two orders of magnitude for certain cases.", "doi": "10.1145/3173162.3173208", "arxiv_id": "https://doi.org/10.1145/3173162.3173208", "pmid": null, "openalex_id": null, "s2_id": "3b57c7bcece47f2a3198e6adec38f712f2914be5", "cited_by": 73, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173208", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173208"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173208", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Forget Failure: Exploiting SRAM Data Remanence for Low-overhead Intermittent Computation", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Harrison Williams", "Xun Jian", "Matthew Hicks"], "abstract": "Energy harvesting is a promising solution to power billions of ultra-low-power Internet-of-Things devices to enable ubiquitous computing. However, energy harvesters typically output tiny amounts of energy and, therefore, cannot continuously power devices; this leads to intermittent computing, where the energy harvester periodically charges a capacitor to sufficient voltage to power brief computation, until the capacitor's charge is drained, and the cycle repeats. To retain program state across frequent power failures, prior work proposes checkpointing program state to Non-Volatile Memory (NVM) before a power failure. Unfortunately, the most widely deployed, highest performance, and lowest cost devices employ Flash as their NVM, but the power, time, and endurance limitations of Flash writes are incompatible with the frequent NVM checkpoints of intermittent computation.", "doi": "10.1145/3373376.3378478", "arxiv_id": "https://doi.org/10.1145/3373376.3378478", "pmid": null, "openalex_id": null, "s2_id": "3bb5c110d2e20c9f3a81244178519ec19da32ccd", "cited_by": 29, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378478", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378478"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378478", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Mallacc: Accelerating Memory Allocation", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Svilen Kanev", "Sam Likun Xi", "Gu-Yeon Wei", "David M. Brooks"], "abstract": "Recent work shows that dynamic memory allocation consumes nearly 7% of all cycles in Google datacenters. With the trend towards increased specialization of hardware, we propose Mallacc, an in-core hardware accelerator designed for broad use across a number of high-performance, modern memory allocators. The design of Mallacc is quite different from traditional throughput-oriented hardware accelerators. Because memory allocation requests tend to be very frequent, fast, and interspersed inside other application code, accelerators must be optimized for latency rather than throughput and area overheads must be kept to a bare minimum. Mallacc accelerates the three primary operations of a typical memory allocation request: size class computation, retrieval of a free memory block, and sampling of memory usage. Our results show that malloc latency can be reduced by up to 50% with a hardware cost of less than 1500 um2 of silicon area, less than 0.006% of a typical high-performance processor core.", "doi": "10.1145/3037697.3037736", "arxiv_id": "https://doi.org/10.1145/3037697.3037736", "pmid": null, "openalex_id": null, "s2_id": "3bbea7952f72ee0d4f7a156ba5b5805ba78a7515", "cited_by": 44, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037736"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037736", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Rethinking software runtimes for disaggregated memory", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Irina Calciu", "M. Talha Imran", "Ivan Puddu", "Sanidhya Kashyap", "Hasan Al Maruf", "Onur Mutlu", "Aasheesh Kolli"], "abstract": "Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual memory subsystem to transparently offer disaggregated memory to applications using a local memory abstraction. Unfortunately, using virtual memory for disaggregation has multiple limitations, including high overhead that comes from the use of page faults to identify what data to fetch and cache locally, and high dirty data amplification that comes from the use of page-granularity for tracking changes to the cached data (4KB or higher). In this paper, we propose a fundamentally new approach to designing software runtimes for disaggregated memory that addresses these limitations. Our main observation is that we can use cache coherence instead of virtual memory for tracking applications' memory accesses transparently, at cache-line granularity. This simple idea (1) eliminates page faults from the application critical path when accessing remote data, and (2) decouples the application memory access tracking from the virtual memory page size, enabling cache-line granularity dirty data tracking and eviction. Using this observation, we implemented a new software runtime for disaggregated memory that improves average memory access time by 1.7-5X and reduces dirty data amplification by 2-10X, compared to state-of-the-art systems.", "doi": "10.1145/3445814.3446713", "arxiv_id": "https://doi.org/10.1145/3445814.3446713", "pmid": null, "openalex_id": null, "s2_id": "3be525632e0d3ff91e8130ad889ca9825cce3f73", "cited_by": 175, "type": "conference", "is_oa": true, "pdf_urls": ["http://infoscience.epfl.ch/record/295951", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446713"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446713", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FaasCache: keeping serverless computing alive with greedy-dual caching", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alexander Fuerst", "Prateek Sharma"], "abstract": "Functions as a Service (also called serverless computing) promises to revolutionize how applications use cloud resources. However, functions suffer from cold-start problems due to the overhead of initializing their code and data dependencies before they can start executing. Keeping functions alive and warm after they have finished execution can alleviate the cold-start overhead. Keep-alive policies must keep functions alive based on their resource and usage characteristics, which is challenging due to the diversity in FaaS workloads. Our insight is that keep-alive is analogous to caching. Our caching-inspired Greedy-Dual keep-alive policy can be effective in reducing the cold-start overhead by more than 3× compared to current approaches. Caching concepts such as reuse distances and hit-ratio curves can also be used for auto-scaled server resource provisioning, which can reduce the resource requirement of FaaS providers by 30% for real-world dynamic workloads. We implement caching-based keep-alive and resource provisioning policies in our FaasCache system, which is based on OpenWhisk. We hope that our caching analogy opens the door to more principled and optimized keep-alive and resource provisioning techniques for future FaaS workloads and platforms.", "doi": "10.1145/3445814.3446757", "arxiv_id": "https://doi.org/10.1145/3445814.3446757", "pmid": null, "openalex_id": null, "s2_id": "3c05fec4087d94c61233a482e59b613388b2c3ae", "cited_by": 309, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446757"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446757", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Graspan: A Single-machine Disk-based Graph System for Interprocedural Static Analyses of Large-scale Systems Code", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kai Wang", "Aftab Hussain", "Zhiqiang Zuo", "Guoqing Xu", "Ardalan Amiri Sani"], "abstract": "There is more than a decade-long history of using static analysis to find bugs in systems such as Linux. Most of the existing static analyses developed for these systems are simple checkers that find bugs based on pattern matching. Despite the presence of many sophisticated interprocedural analyses, few of them have been employed to improve checkers for systems code due to their complex implementations and poor scalability. In this paper, we revisit the scalability problem of interprocedural static analysis from a \"Big Data\" perspective. That is, we turn sophisticated code analysis into Big Data analytics and leverage novel data processing techniques to solve this traditional programming language problem. We develop Graspan, a disk-based parallel graph system that uses an edge-pair centric computation model to compute dynamic transitive closures on very large program graphs.", "doi": "10.1145/3037697.3037744", "arxiv_id": "https://doi.org/10.1145/3037697.3037744", "pmid": null, "openalex_id": null, "s2_id": "3c831e81d29dd5ae62f20120793ba7aaabc257b3", "cited_by": 108, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037744"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037744", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 8B: Transactional Memory", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252409", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "3c8af0223f943ca4abd14f825b05537251fbb79b", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ShEF: shielded enclaves for cloud FPGAs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507733", "arxiv_id": "2103.03500", "pmid": null, "openalex_id": null, "s2_id": "3d60fe7e8d72cca03b33f5145deee81903e1a1bc", "cited_by": 78, "type": null, "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2103.03500"], "github": ["https://github.com/stanford-mast/shef"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "X-Containers: Breaking Down Barriers to Improve Performance and Isolation of Cloud-Native Containers", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhiming Shen", "Zhen Sun", "Gur-Eyal Sela", "Eugene Bagdasaryan", "Christina Delimitrou", "Robbert van Renesse", "Hakim Weatherspoon"], "abstract": "\"Cloud-native\" container platforms, such as Kubernetes, have become an integral part of production cloud environments. One of the principles in designing cloud-native applications is called Single Concern Principle, which suggests that each container should handle a single responsibility well. In this paper, we propose X-Containers as a new security paradigm for isolating single-concerned cloud-native containers. Each container is run with a Library OS (LibOS) that supports multi-processing for concurrency and compatibility. A minimal exokernel ensures strong isolation with small kernel attack surface. We show an implementation of the X-Containers architecture that leverages Xen paravirtualization (PV) to turn Linux kernel into a LibOS. Doing so results in a highly efficient LibOS platform that does not require hardware-assisted virtualization, improves inter-container isolation, and supports binary compatibility and multi-processing. By eliminating some security barriers such as seccomp and Meltdown patch, X-Containers have up to 27X higher raw system call throughput compared to Docker containers, while also achieving competitive or superior performance on various benchmarks compared to recent container platforms such as Google's gVisor and Intel's Clear Containers.", "doi": "10.1145/3297858.3304016", "arxiv_id": "https://doi.org/10.1145/3297858.3304016", "pmid": null, "openalex_id": null, "s2_id": "3f4537267241e1d4c971d05157e532aaea787d7d", "cited_by": 114, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304016", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304016"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304016", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "IOctopus: Outsmarting Nonuniform DMA", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Igor Smolyar", "Alex Markuze", "Boris Pismenny", "Haggai Eran", "Gerd Zellweger", "Austin Bolen", "Liran Liss", "Adam Morrison", "Dan Tsafrir"], "abstract": "In a multi-CPU server, memory modules are local to the CPU to which they are connected, forming a nonuniform memory access (NUMA) architecture. Because non-local accesses are slower than local accesses, the NUMA architecture might degrade application performance. Similar slowdowns occur when an I/O device issues nonuniform DMA (NUDMA) operations, as the device is connected to memory via a single CPU. NUDMA effects therefore degrade application performance similarly to NUMA effects.", "doi": "10.1145/3373376.3378509", "arxiv_id": "https://doi.org/10.1145/3373376.3378509", "pmid": null, "openalex_id": null, "s2_id": "3f5c2159834e2691dd0b332c72a72e6a0e10dc11", "cited_by": 22, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378509"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378509", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Keynote Address I", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248615", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "3fa322f304b0f03d9b44c644b3b0af51ffa5d04b", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Time-sensitive Intermittent Computing Meets Legacy Software", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Vito Kortbeek", "Kasim Sinan Yildirim", "Abu Bakar", "Jacob Sorber", "Josiah D. Hester", "Przemyslaw Pawelczak"], "abstract": "Tiny energy harvesting sensors that operate intermittently, without batteries, have become an increasingly appealing way to gather data in hard to reach places at low cost. Frequent power failures make forward progress, data preservation and consistency, and timely operation challenging. Unfortunately, state-of-the-art systems ask the programmer to solve these challenges, and have high memory overhead, lack critical programming features like pointers and recursion, and are only dimly aware of the passing of time and its effect on application quality. We present Time-sensitive Intermittent Computing System (TICS), a new platform for intermittent computing, which provides simple programming abstractions for handling the passing of time through intermittent failures, and uses this to make decisions about when data can be used or thrown away. Moreover, TICS provides predictable checkpoint sizes by keeping checkpoint and restore times small and reduces the cognitive burden of rewriting embedded code for intermittency without limiting expressibility or language functionality, enabling numerous existing embedded applications to run intermittently.", "doi": "10.1145/3373376.3378476", "arxiv_id": "https://doi.org/10.1145/3373376.3378476", "pmid": null, "openalex_id": null, "s2_id": "3fa62c599fb689ddd96d620d35d73881ca81d214", "cited_by": 94, "type": "conference", "is_oa": true, "pdf_urls": ["https://iris.unitn.it/bitstream/11572/257894/1/3373376.3378476%20%282%29.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378476"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378476", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Towards \"Full Containerization\" in Containerized Network Function Virtualization", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yang Hu", "Mingcong Song", "Tao Li"], "abstract": "With exploding traffic stuffing existing network infra-structure, today's telecommunication and cloud service providers resort to Network Function Virtualization (NFV) for greater agility and economics. Pioneer service provider such as AT&T proposes to adopt container in NFV to achieve shorter Virtualized Network Function (VNF) provisioning time and better runtime performance. However, we characterize typical NFV work-loads on the containers and find that the performance is unsatisfactory. We observe that the shared host OS net-work stack is the main bottleneck, where the traffic flow processing involves a large amount of intermediate memory buffers and results in significant last level cache pollution. Existing OS memory allocation policies fail to exploit the locality and data sharing information among buffers. In this paper, we propose NetContainer, a software framework that achieves fine-grained hardware resource management for containerized NFV platform. NetContainer employs a cache access overheads guided page coloring scheme to coordinately address the inter-flow cache access overheads and intra-flow cache access overheads. It maps the memory buffer pages that manifest low cache access overheads (across a flow or among the flows) to the same last level cache partition. NetContainer exploits a footprint theory based method to estimate the cache access overheads and a Min-Cost Max-Flow model to guide the memory buffer mappings. We implement the NetContainer in Linux kernel and extensively evaluate it with real NFV workloads. Exper-imental results show that NetContainer outperforms conventional page coloring-based memory allocator by 48% in terms of successful call rate.", "doi": "10.1145/3037697.3037713", "arxiv_id": "https://doi.org/10.1145/3037697.3037713", "pmid": null, "openalex_id": null, "s2_id": "3fd4aa3b657b4fb457ed1dfd54dc87e34f651e8b", "cited_by": 29, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3037697.3037713", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037713"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037713", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Andreas Abel", "Jan Reineke"], "abstract": "Modern microarchitectures are some of the world's most complex man-made systems. As a consequence, it is increasingly difficult to predict, explain, let alone optimize the performance of software running on such microarchitectures. As a basis for performance predictions and optimizations, we would need faithful models of their behavior, which are, unfortunately, seldom available. In this paper, we present the design and implementation of a tool to construct faithful models of the latency, throughput, and port usage of x86 instructions. To this end, we first discuss common notions of instruction throughput and port usage, and introduce a more precise definition of latency that, in contrast to previous definitions, considers dependencies between different pairs of input and output operands. We then develop novel algorithms to infer the latency, throughput, and port usage based on automatically-generated microbenchmarks that are more accurate and precise than existing work. To facilitate the rapid construction of optimizing compilers and tools for performance prediction, the output of our tool is provided in a machine-readable format. We provide experimental results for processors of all generations of Intel's Core architecture, i.e., from Nehalem to Coffee Lake, and discuss various cases where the output of our tool differs considerably from prior work.", "doi": "10.1145/3297858.3304062", "arxiv_id": "1810.04610", "pmid": null, "openalex_id": null, "s2_id": "402b6eed11b6c8718b4ae319703caf93d62b68bf", "cited_by": 133, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/1810.04610", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304062"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304062", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "memif: Towards Programming Heterogeneous Memory Asynchronously", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Felix Xiaozhu Lin", "Xu Liu"], "abstract": null, "doi": "10.1145/2872362.2872401", "arxiv_id": "https://doi.org/10.1145/2872362.2872401", "pmid": null, "openalex_id": null, "s2_id": "40718dab3e261c2456c3576d15dd0105f1e2e4e2", "cited_by": 61, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872401"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872401", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fleet: A Framework for Massively Parallel Streaming on FPGAs", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["James Thomas", "Pat Hanrahan", "Matei Zaharia"], "abstract": "The shipping of goods around the world is continually increasing, especially since the onset of the coronavirus disease 2019 (COVID-19) pandemic. If you don’t live in a port city such as Seattle, it’s hard to imagine the enormity of commerce and its impacts. Mary Iverson’s artwork raises questions about the consequences of the growing consumerism, particularly how carbon footprints of the shipping industry contribute to climate change. Fleet illustrates a post-apocalyptic vision of what rising sea levels would look like in our cities. In the depicted great flood, a group of stranded container ships (the backbone of today’s global trade) are floating around, calling attention to consumerism and its huge impacts on climate change. Imagining the big flood in cities with floating shipping containers in a climate-changing world, Fleet, a post-apocalyptic vision, asks us to consider our growing demand, consumerism, and their environmental impacts.", "doi": "10.1145/3373376.3378495", "arxiv_id": "https://doi.org/10.1145/3373376.3378495", "pmid": null, "openalex_id": null, "s2_id": "40ddc81a086fd1f660c5fbcaa0e38c2efec995bc", "cited_by": 37, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378495", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378495"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378495", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Gushu Li", "Yufei Ding", "Yuan Xie"], "abstract": "Due to little considerations in the hardware constraints, e.g., limited connections between physical qubits to enable two-qubit gates, most quantum algorithms cannot be directly executed on the Noisy Intermediate-Scale Quantum (NISQ) devices. Dynamically remapping logical qubits to physical qubits in the compiler is needed to enable the two-qubit gates in the algorithm, which introduces additional operations and inevitably reduces the fidelity of the algorithm. Previous solutions in finding such remapping suffer from high complexity, poor initial mapping quality, and limited flexibility and control. To address these drawbacks mentioned above, this paper proposes a SWAP-based Bidirectional heuristic search algorithm (SABRE), which is applicable to NISQ devices with arbitrary connections between qubits. By optimizing every search attempt, globally optimizing the initial mapping using a novel reverse traversal technique, introducing the decay effect to enable the trade-off between the depth and the number of gates of the entire algorithm, SABRE outperforms the best known algorithm with exponential speedup and comparable or better results on various benchmarks.", "doi": "10.1145/3297858.3304023", "arxiv_id": "1809.02573", "pmid": null, "openalex_id": null, "s2_id": "40f3af4560bfb6b2509d5677c40a2ab439bf4f3a", "cited_by": 800, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304023"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304023", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mark Gallagher", "Lauren Biernacki", "Shibo Chen", "Zelalem Birhanu Aweke", "Salessawi Ferede Yitbarek", "Misiker Tadesse Aga", "Austin Harris", "Zhixing Xu", "Baris Kasikci", "Valeria Bertacco", "Sharad Malik", "Mohit Tiwari", "Todd M. Austin"], "abstract": "Attacks often succeed by abusing the gap between program and machine-level semantics-- for example, by locating a sensitive pointer, exploiting a bug to overwrite this sensitive data, and hijacking the victim program's execution. In this work, we take secure system design on the offensive by continuously obfuscating information that attackers need but normal programs do not use, such as representation of code and pointers or the exact location of code and data. Our secure hardware architecture, Morpheus, combines two powerful protections: ensembles of moving target defenses and churn. Ensembles of moving target defenses randomize key program values (e.g., relocating pointers and encrypting code and pointers) which forces attackers to extensively probe the system prior to an attack. To ensure attack probes fail, the architecture incorporates churn to transparently re-randomize program values underneath the running system. With frequent churn, systems quickly become impractically difficult to penetrate. We demonstrate Morpheus through a RISC-V-based prototype designed to stop control-flow attacks. Each moving target defense in Morpheus uses hardware support to individually offer more randomness at a lower cost than previous techniques. When ensembled with churn, Morpheus defenses offer strong protection against control-flow attacks, with our security testing and performance studies revealing: i) high-coverage protection for a broad array of control-flow attacks, including protections for advanced attacks and an attack disclosed after the design of Morpheus, and ii) negligible performance impacts (1%) with churn periods up to 50 ms, which our study estimates to be at least 5000x faster than the time necessary to possibly penetrate Morpheus.", "doi": "10.1145/3297858.3304037", "arxiv_id": "https://doi.org/10.1145/3297858.3304037", "pmid": null, "openalex_id": null, "s2_id": "42cc9e1df11cb90257a60c3d8bbd1aebf17e588a", "cited_by": 66, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304037", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304037"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304037", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HiWayLib: A Software Framework for Enabling High Performance Communications for Heterogeneous Pipeline Computations", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhen Zheng", "Chanyoung Oh", "Jidong Zhai", "Xipeng Shen", "Youngmin Yi", "Wenguang Chen"], "abstract": "Pipeline is a parallel computing model underpinning a class of important applications running on CPU-GPU heterogeneous systems. A critical aspect for the efficiency of such applications is the support of communications among pipeline stages that may reside on CPU and different parts of a GPU. Existing libraries of concurrent data structures do not meet the needs, due to the massive parallelism on GPU and the complexities in CPU-GPU memory and connections. This work gives an in-depth study on the communication problem. It identifies three key issues, namely, slow and error-prone detection of the end of pipeline processing, intensive queue contentions on GPU, and cumbersome inter-device data movements. This work offers solutions to each of the issues, and integrates all together to form a unified library named HiWayLib. Experiments show that HiWayLib significantly boosts the efficiency of pipeline communications in CPU-GPU heterogeneous applications. For real-world applications, HiWayLib produces 1.22~2.13× speedups over the state-of-art implementations with little extra programming effort required.", "doi": "10.1145/3297858.3304032", "arxiv_id": "https://doi.org/10.1145/3297858.3304032", "pmid": null, "openalex_id": null, "s2_id": "42f0a2d46afa530833971d00649d46efd138c7f3", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304032", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304032"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304032", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Optimistic Hybrid Analysis: Accelerating Dynamic Analysis through Predicated Static Analysis", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["David Devecsery", "Peter M. Chen", "Jason Flinn", "Satish Narayanasamy"], "abstract": "Dynamic analysis tools, such as those that detect data-races, verify memory safety, and identify information flow, have become a vital part of testing and debugging complex software systems. While these tools are powerful, their slow speed often limits how effectively they can be deployed in practice. Hybrid analysis speeds up these tools by using static analysis to decrease the work performed during dynamic analysis. In this paper we argue that current hybrid analysis is needlessly hampered by an incorrect assumption that preserving the soundness of dynamic analysis requires an underlying sound static analysis. We observe that, even with unsound static analysis, it is possible to achieve sound dynamic analysis for the executions which fall within the set of states statically considered. This leads us to a new approach, called optimistic hybrid analysis. We first profile a small set of executions and generate a set of likely invariants that hold true during most, but not necessarily all, executions. Next, we apply a much more precise, but unsound, static analysis that assumes these invariants hold true. Finally, we run the resulting dynamic analysis speculatively while verifying whether the assumed invariants hold true during that particular execution; if not, the program is reexecuted with a traditional hybrid analysis. Optimistic hybrid analysis is as precise and sound as traditional dynamic analysis, but is typically much faster because (1) unsound static analysis can speed up dynamic analysis much more than sound static analysis can and (2) verifications rarely fail. We apply optimistic hybrid analysis to race detection and program slicing and achieve 1.8x over a state-of-the-art race detector (FastTrack) optimized with traditional hybrid analysis and 8.3x over a hybrid backward slicer (Giri).", "doi": "10.1145/3173162.3177153", "arxiv_id": "https://doi.org/10.1145/3173162.3177153", "pmid": null, "openalex_id": null, "s2_id": "432e4baac0bad1c4a4c45d8a4398f695f72a206a", "cited_by": 37, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3177153", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177153"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177153", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Warehouse-scale video acceleration: co-design and deployment in the wild", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Parthasarathy Ranganathan", "Daniel Stodolsky", "Jeff Calow", "Jeremy Dorfman", "Marisabel Guevara", "Clinton Wills Smullen IV", "Aki Kuusela", "Raghu Balasubramanian", "Sandeep Bhatia", "Prakash Chauhan", "Anna Cheung", "In Suk Chong", "Niranjani Dasharathi", "Jia Feng", "Brian Fosco", "Samuel Foss", "Ben Gelb", "Sara J. Gwin", "Yoshiaki Hase", "Da-ke He", "C. Richard Ho", "Roy W. Huffman Jr.", "Elisha Indupalli", "Indira Jayaram", "Poonacha Kongetira", "Cho Mon Kyaw", "Aaron Laursen", "Yuan Li", "Fong Lou", "Kyle A. Lucke", "J. P. Maaninen", "Ramon Macias", "Maire Mahony", "David Alexander Munday", "Srikanth Muroor", "Narayana Penukonda", "Eric Perkins-Argueta", "Devin Persaud", "Alex Ramírez", "Ville-Mikko Rautio", "Yolanda Ripley", "Amir Salek", "Sathish Sekar", "Sergey N. Sokolov", "Rob Springer", "Don Stark", "Mercedes Tan", "Mark S. Wachsler", "Andrew C. Walton", "David A. Wickeraad", "Alvin Wijaya", "Hon Kwan Wu"], "abstract": "Video sharing (e.g., YouTube, Vimeo, Facebook, TikTok) accounts for the majority of internet traffic, and video processing is also foundational to several other key workloads (video conferencing, virtual/augmented reality, cloud gaming, video in Internet-of-Things devices, etc.). The importance of these workloads motivates larger video processing infrastructures and – with the slowing of Moore’s law – specialized hardware accelerators to deliver more computing at higher efficiencies. This paper describes the design and deployment, at scale, of a new accelerator targeted at warehouse-scale video transcoding. We present our hardware design including a new accelerator building block – the video coding unit (VCU) – and discuss key design trade-offs for balanced systems at data center scale and co-designing accelerators with large-scale distributed software systems. We evaluate these accelerators “in the wild\" serving live data center jobs, demonstrating 20-33x improved efficiency over our prior well-tuned non-accelerated baseline. Our design also enables effective adaptation to changing bottlenecks and improved failure management, and new workload capabilities not otherwise possible with prior systems. To the best of our knowledge, this is the first work to discuss video acceleration at scale in large warehouse-scale environments.", "doi": "10.1145/3445814.3446723", "arxiv_id": "https://doi.org/10.1145/3445814.3446723", "pmid": null, "openalex_id": null, "s2_id": "43ae70f2480966c87aee061268f9c48a3a5cbd2d", "cited_by": 61, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.1145/3445814.3446723", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446723"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446723", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Automatically detecting and fixing concurrency bugs in go software systems", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ziheng Liu", "Shuofei Zhu", "Boqin Qin", "Hao Chen", "Linhai Song"], "abstract": "Go is a statically typed programming language designed for efficient and reliable concurrent programming. For this purpose, Go provides lightweight goroutines and recommends passing messages using channels as a less error-prone means of thread communication. Go has become increasingly popular in recent years and has been adopted to build many important infrastructure software systems. However, a recent empirical study shows that concurrency bugs, especially those due to misuse of channels, exist widely in Go. These bugs severely hurt the reliability of Go concurrent systems. To fight Go concurrency bugs caused by misuse of channels, this paper proposes a static concurrency bug detection system, GCatch, and an automated concurrency bug fixing system, GFix. After disentangling an input Go program, GCatch models the complex channel operations in Go using a novel constraint system and applies a constraint solver to identify blocking bugs. GFix automatically patches blocking bugs detected by GCatch using Go’s channel-related language features. We apply GCatch and GFix to 21 popular Go applications, including Docker, Kubernetes, and gRPC. In total, GCatch finds 149 previously unknown blocking bugs due to misuse of channels and GFix successfully fixes 124 of them. We have reported all detected bugs and generated patches to developers. So far, developers have fixed 125 blocking misuse-of-channel bugs based on our reporting. Among them, 87 bugs are fixed by applying GFix’s patches directly.", "doi": "10.1145/3445814.3446756", "arxiv_id": "https://doi.org/10.1145/3445814.3446756", "pmid": null, "openalex_id": null, "s2_id": "447b2b1602d749e1b144022f1f3c477679776457", "cited_by": 37, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446756"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446756", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "The TrieJax Architecture: Accelerating Graph Operations Through Relational Joins", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Oren Kalinsky", "Benny Kimelfeld", "Yoav Etsion"], "abstract": "Graph pattern matching (e.g., finding all cycles and cliques) has become an important component in domains such as social networks, biology and cyber-security. In recent years, the database community has shown that graph pattern matching problems can be mapped to an efficient new class of relational join algorithms.", "doi": "10.1145/3373376.3378524", "arxiv_id": "1905.08021", "pmid": null, "openalex_id": null, "s2_id": "44aa998b85e7c198af5b8cd98f0294f71481b2c3", "cited_by": 18, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378524"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378524", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HawkEye: Efficient Fine-grained OS Support for Huge Pages", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ashish Panwar", "Sorav Bansal", "K. Gopinath"], "abstract": "Effective huge page management in operating systems is necessary for mitigation of address translation overheads. However, this continues to remain a difficult area in OS design. Recent work on Ingens uncovered some interesting pitfalls in current huge page management strategies. Using both page access patterns discovered by the OS kernel and fine-grained data from hardware performance counters, we expose problematic aspects of current huge page management strategies. In our system, called HawkEye/Linux, we demonstrate alternate ways to address issues related to performance, page fault latency and memory bloat; the primary ideas behind HawkEye management algorithms are async page pre-zeroing, de-duplication of zero-filled pages, fine-grained page access tracking and measurement of address translation overheads through hardware performance counters. Our evaluation shows that HawkEye is more performant, robust and better-suited to handle diverse workloads when compared with current state-of-the-art systems.", "doi": "10.1145/3297858.3304064", "arxiv_id": "https://doi.org/10.1145/3297858.3304064", "pmid": null, "openalex_id": null, "s2_id": "46ac482a6028d16769dd6bb63365a36033f3f528", "cited_by": 105, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304064&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304064"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304064", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Time Dilation and Contraction for Programmable Analog Devices with Jaunt", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sara Achour", "Martin C. Rinard"], "abstract": "Programmable analog devices are a powerful new computing substrate that are especially appropriate for performing computationally intensive simulations of neuromorphic and cytomorphic models. Current state of the art techniques for configuring analog devices to simulate dynamical systems do not consider the current and voltage operating ranges of analog device components or the sampling limitations of the digital interface of the device. We present Jaunt, a new solver that scales the values that configure the analog device to ensure the resulting analog computation executes within the operating constraints of the device, preserves the recoverable dynamics of the original simulation, and executes slowly enough to observe these dynamics at the sampled digital outputs. Our results show that, on a set of benchmark biological simulations, 1) unscaled configurations produce incorrect simulations because they violate the operating ranges of the device and 2) Jaunt delivers scaled configurations that respect the operating ranges to produce correct simulations with observable dynamics.", "doi": "10.1145/3173162.3173179", "arxiv_id": "https://doi.org/10.1145/3173162.3173179", "pmid": null, "openalex_id": null, "s2_id": "47a2d83b06990972d6ebe142e6c69522c236978b", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3173179&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173179"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173179", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Clio: a hardware-software co-designed disaggregated memory system", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507762", "arxiv_id": "2108.03492", "pmid": null, "openalex_id": null, "s2_id": "48f15fea80f27350de427d922283ebaa24f0f746", "cited_by": 172, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3503222.3507762"], "github": ["https://github.com/wuklab/clio"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "REDSPY: Exploring Value Locality in Software", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shasha Wen", "Milind Chabbi", "Xu Liu"], "abstract": "Complex code bases with several layers of abstractions have abundant inefficiencies that affect the execution time. Value redundancy is a kind of inefficiency where the same values are repeatedly computed, stored, or retrieved over the course of execution. Not all redundancies can be easily detected or eliminated with compiler optimization passes due to the inherent limitations of the static analysis.", "doi": "10.1145/3037697.3037729", "arxiv_id": "https://doi.org/10.1145/3037697.3037729", "pmid": null, "openalex_id": null, "s2_id": "490d504d54f3c31a1f9a661d03d0e8fbb2b6b239", "cited_by": 42, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037729"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037729", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PatDNN: Achieving Real-Time DNN Execution on Mobile Devices with Pattern-based Weight Pruning", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Wei Niu", "Xiaolong Ma", "Sheng Lin", "Shihao Wang", "Xuehai Qian", "Xue Lin", "Yanzhi Wang", "Bin Ren"], "abstract": "With the emergence of a spectrum of high-end mobile devices, many applications that formerly required desktop-level computation capability are being transferred to these devices. However, executing Deep Neural Networks (DNNs) inference is still challenging considering the high computation and storage demands, specifically, if real-time performance with high accuracy is needed. Weight pruning of DNNs is proposed, but existing schemes represent two extremes in the design space: non-structured pruning is fine-grained, accurate, but not hardware friendly; structured pruning is coarse-grained, hardware-efficient, but with higher accuracy loss. In this paper, we advance the state-of-the-art by introducing a new dimension, fine-grained pruning patterns inside the coarse-grained structures, revealing a previously unknown point in the design space. With the higher accuracy enabled by fine-grained pruning patterns, the unique insight is to use the compiler to re-gain and guarantee high hardware efficiency. In other words, our method achieves the best of both worlds, and is desirable across theory/algorithm, compiler, and hardware levels. The proposed PatDNN is an end-to-end framework to efficiently execute DNN on mobile devices with the help of a novel model compression technique---pattern-based pruning based on an extended ADMM solution framework---and a set of thorough architecture-aware compiler/code generation-based optimizations, i.e., filter kernel reordering, compressed weight storage, register load redundancy elimination, and parameter auto-tuning. Evaluation results demonstrate that PatDNN outperforms three state-of-the-art end-to-end DNN frameworks, TensorFlow Lite, TVM, and Alibaba Mobile Neural Network with speedup up to 44.5X, 11.4X, and 7.1X, respectively, with no accuracy compromise. Real-time inference of representative large-scale DNNs (e.g., VGG-16, ResNet-50) can be achieved using mobile devices.", "doi": "10.1145/3373376.3378534", "arxiv_id": "2001.00138", "pmid": null, "openalex_id": null, "s2_id": "4a86fc1bb1b83860f29adef68efbfd5e5c339300", "cited_by": 255, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378534", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378534"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378534", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Vortex: Extreme-Performance Memory Abstractions for Data-Intensive Streaming Applications", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Carson Hanel", "Arif Arman", "Di Xiao", "John Keech", "Dmitri Loguinov"], "abstract": "Many applications in data analytics, information retrieval, and cluster computing process huge amounts of information. The complexity of involved algorithms and massive scale of data require a programming model that can not only offer a simple abstraction for inputs larger than RAM, but also squeeze maximum performance out of the available hardware. While these are usually conflicting goals, we show that this does not have to be the case for sequentially-processed data, i.e., in streaming applications. We develop a set of algorithms called Vortex that force the application to generate access violations (i.e., page faults) during processing of the stream, which are transparently handled in such a way that creates an illusion of an infinite buffer that fits into a regular C/C++ pointer. This design makes Vortex by far the simplest-to-use and fastest platform for various types of streaming I/O, inter-thread data transfer, and key shuffling. We introduce several such applications -- file I/O wrapper, bounded producer-consumer pipeline, vanishing array, key-partitioning engine, and novel in-place radix sort that is 3-4 times faster than the best prior approaches.", "doi": "10.1145/3373376.3378527", "arxiv_id": "https://doi.org/10.1145/3373376.3378527", "pmid": null, "openalex_id": null, "s2_id": "4adcf709def82e7e3bf7e622044a2a76e59e960a", "cited_by": 6, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378527", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378527"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378527", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Wasabi: A Framework for Dynamically Analyzing WebAssembly", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daniel Lehmann", "Michael Pradel"], "abstract": "WebAssembly is the new low-level language for the web and has now been implemented in all major browsers since over a year. To ensure the security, performance, and correctness of future web applications, there is a strong need for dynamic analysis tools for WebAssembly. However, building such tools from scratch requires knowledge of low-level details of the language and its runtime environment. This paper presents Wasabi, the first general-purpose framework for dynamically analyzing WebAssembly. Wasabi provides an easy-to-use, high-level API that supports heavyweight dynamic analyses. It is based on binary instrumentation, which inserts calls to analysis functions written in JavaScript into a WebAssembly binary. Dynamically analyzing WebAssembly comes with several unique challenges, such as the problem of tracing type-polymorphic instructions with analysis functions that have a fixed type, which we address through on-demand monomorphization. Our evaluation on compute-intensive benchmarks and real-world applications shows that Wasabi (i) faithfully preserves the original program behavior, (ii) imposes an overhead that is reasonable for heavyweight dynamic analysis, and (iii) makes it straightforward to implement various dynamic analyses, including instruction counting, call graph extraction, memory access tracing, and taint analysis.", "doi": "10.1145/3297858.3304068", "arxiv_id": "1808.10652", "pmid": null, "openalex_id": null, "s2_id": "4c2d6e7037ba8c4118eb1d2fe25de910871314c9", "cited_by": 96, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304068&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304068"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304068", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Safer Program Behavior Sharing Through Trace Wringing", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Deeksha Dangwal", "Weilong Cui", "Joseph McMahan", "Timothy Sherwood"], "abstract": "When working towards application-tuned systems, developers often find themselves caught between the need to share information (so that partners can make intelligent design choices) and the need to hide information (to protect proprietary methods or sensitive data). One place where this problem comes to a head is in the release of program traces, for example a memory address trace. A trace taken from a production server might expose details about who the users are or what they are doing, or it might even expose details of the actual computation itself (e.g. through a side channel). Engineers are often asked to make, by hand, \"analogs\" of their codes that would be free from such sensitive data or, may even try to describe behaviors at a high level with words. Both of these approaches lead to missed opportunities, confusion, and frustration. We propose a new problem for study, trace-wringing, that seeks to remove as much information from the trace as possible while still maintaining key characteristics of the original. We formalize this problem and show that, for a specific instance around memory traces, as little as a few thousand bits need to be shared. We demonstrate experimentally that the trace-wrung proxies behave similarly in the context of cache simulation but with bounded leakage, and examine the sensitivity of wrung traces to a class of attacks on AES encryption.", "doi": "10.1145/3297858.3304074", "arxiv_id": "https://doi.org/10.1145/3297858.3304074", "pmid": null, "openalex_id": null, "s2_id": "4d150a6edb5ba842467ef820541bf528c3313fa3", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304074", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304074"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304074", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Prakash Murali", "Jonathan M. Baker", "Ali Javadi-Abhari", "Frederic T. Chong", "Margaret Martonosi"], "abstract": "A massive gap exists between current quantum computing (QC) prototypes, and the size and scale required for many proposed QC algorithms. Current QC implementations are prone to noise and variability which affect their reliability, and yet with less than 80 quantum bits (qubits) total, they are too resource-constrained to implement error correction. The term Noisy Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems of 1000 qubits or less. Given NISQ's severe resource constraints, low reliability, and high variability in physical characteristics such as coherence time or error rates, it is of pressing importance to map computations onto them in ways that use resources efficiently and maximize the likelihood of successful runs. This paper proposes and evaluates backend compiler approaches to map and optimize high-level QC programs to execute with high reliability on NISQ systems with diverse hardware characteristics. Our techniques all start from an LLVM intermediate representation of the quantum program (such as would be generated from high-level QC languages like Scaffold) and generate QC executables runnable on the IBM Q public QC machine. We then use this framework to implement and evaluate several optimal and heuristic mapping methods. These methods vary in how they account for the availability of dynamic machine calibration data, the relative importance of various noise parameters, the different possible routing strategies, and the relative importance of compile-time scalability versus runtime success. Using real-system measurements, we show that fine grained spatial and temporal variations in hardware parameters can be exploited to obtain an average 2.9x (and up to 18x) improvement in program success rate over the industry standard IBM Qiskit compiler. Despite small qubit counts, NISQ systems will soon be large enough to demonstrate \"quantum supremacy\", i.e., an advantage over classical computing. Tools like ours provide significant improvements in program reliability and execution time, and offer high leverage in accelerating progress towards quantum supremacy.", "doi": "10.1145/3297858.3304075", "arxiv_id": "1901.11054", "pmid": null, "openalex_id": null, "s2_id": "4d83d4b005c6041d069ca6316052d388450ebab9", "cited_by": 518, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304075", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304075"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304075", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CSR: Core Surprise Removal in Commodity Operating Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Noam Shalev", "Eran Harpaz", "Hagar Porat", "Idit Keidar", "Yaron Weinsberg"], "abstract": "One of the adverse effects of shrinking transistor sizes is that processors have become increasingly prone to hardware faults. At the same time, the number of cores per die rises. Consequently, core failures can no longer be ruled out, and future operating systems for many-core machines will have to incorporate fault tolerance mechanisms.", "doi": "10.1145/2872362.2872369", "arxiv_id": "https://doi.org/10.1145/2872362.2872369", "pmid": null, "openalex_id": null, "s2_id": "4e68961c49ae3377ec84e649bfc54b0076e8839e", "cited_by": 5, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872369"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872369", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Targeting Classical Code to a Quantum Annealer", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Scott Pakin"], "abstract": "From a compiler's perspective, a quantum annealer represents a fundamentally different hardware target from a CPU, GPU, or other von Neumann architecture. Quantum annealers are special-purpose computers that use quantum effects to heuristically determine the set of Boolean variables that minimize a quadratic pseudo-Boolean function (an NP-hard problem). Natively programming such systems involves supplying them with a vector of function coefficients and receiving a vector of function-minimizing Booleans in return. The contribution of this work is to demonstrate how to compile conventional code into a minimization problem for solution on a quantum annealer. The resulting code can run either forward (from inputs to outputs) or backward (from outputs to inputs). We show how this capability can be exploited to simplify the expression and solution of problems in the NP complexity class.", "doi": "10.1145/3297858.3304071", "arxiv_id": "https://doi.org/10.1145/3297858.3304071", "pmid": null, "openalex_id": null, "s2_id": "4eaa12f0963548f1fa98823e569707d27eb02b47", "cited_by": 9, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304071", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304071"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304071", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jagadish B. Kotra", "Narges Shahidi", "Zeshan A. Chishti", "Mahmut T. Kandemir"], "abstract": "DRAM cells need periodic refresh to maintain data integrity. With high capacity DRAMs, DRAM refresh poses a significant performance bottleneck as the number of rows to be refreshed (and hence the refresh cycle time, tRFC) with each refresh command increases. Modern day DRAMs perform refresh at a rank-level, while LPDDRs used in mobile environments support refresh at a per-bank level. Rank-level refresh degrades the performance significantly since none of the banks in a rank can serve the on-demand requests. Per-bank refresh alleviates some of the performance bottlenecks as the other banks in a rank are available for on-demand requests. Typical DRAM retention time is in the order several of milliseconds, viz, 64msec for environments operating in temperatures below 85 deg C and 32msec for environments operating above 85 deg C.", "doi": "10.1145/3037697.3037724", "arxiv_id": "https://doi.org/10.1145/3037697.3037724", "pmid": null, "openalex_id": null, "s2_id": "4ebbbeab6e0f4ba9815889854441548fa414e16b", "cited_by": 33, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037724"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037724", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "GRIFFIN: Guarding Control Flows Using Intel Processor Trace", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xinyang Ge", "Weidong Cui", "Trent Jaeger"], "abstract": "Researchers are actively exploring techniques to enforce control-flow integrity (CFI), which restricts program execution to a predefined set of targets for each indirect control transfer to prevent code-reuse attacks. While hardware-assisted CFI enforcement may have the potential for advantages in performance and flexibility over software instrumentation, current hardware-assisted defenses are either incomplete (i.e., do not enforce all control transfers) or less efficient in comparison. We find that the recent introduction of hardware features to log complete control-flow traces, such as Intel Processor Trace (PT), provides an opportunity to explore how efficient and flexible a hardware-assisted CFI enforcement system may become. While Intel PT was designed to aid in offline debugging and failure diagnosis, we explore its effectiveness for online CFI enforcement over unmodified binaries by designing a parallelized method for enforcing various types of CFI policies. We have implemented a prototype called GRIFFIN in the Linux 4.2 kernel that enables complete CFI enforcement over a variety of software, including the Firefox browser and its jitted code. Our experiments show that GRIFFIN can enforce fine-grained CFI policies with shadow stack as recommended by researchers at a performance that is comparable to software-only instrumentation techniques. In addition, we find that alternative logging approaches yield significant performance improvements for trace processing, identifying opportunities for further hardware assistance.", "doi": "10.1145/3037697.3037716", "arxiv_id": "https://doi.org/10.1145/3037697.3037716", "pmid": null, "openalex_id": null, "s2_id": "4f4590962bde0c2050122f91e5978271bb24d556", "cited_by": 149, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037716&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037716"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037716", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "RID: Finding Reference Count Bugs with Inconsistent Path Pair Checking", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Junjie Mao", "Yu Chen", "Qixue Xiao", "Yuanchun Shi"], "abstract": "Reference counts are widely used in OS kernels for resource management. However, reference counts are not trivial to be used correctly in large scale programs because it is left to developers to make sure that an increment to a reference count is always paired with a decrement. This paper proposes inconsistent path pair checking, a novel technique that can statically discover bugs related to reference counts without knowing how reference counts should be changed in a function. A prototype called RID is implemented and evaluations show that RID can discover more than 80 bugs which were confirmed by the developers in the latest Linux kernel. The results also show that RID tends to reveal bugs caused by developers' misunderstanding on API specifications or error conditions that are not handled properly.", "doi": "10.1145/2872362.2872389", "arxiv_id": "https://doi.org/10.1145/2872362.2872389", "pmid": null, "openalex_id": null, "s2_id": "4f80ce95d5736aa06d0248a67356065dfc72c047", "cited_by": 35, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872389"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872389", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Locality-Aware CTA Clustering for Modern GPUs", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ang Li", "Shuaiwen Leon Song", "Weifeng Liu", "Xu Liu", "Akash Kumar", "Henk Corporaal"], "abstract": "Cache is designed to exploit locality; however, the role of on-chip L1 data caches on modern GPUs is often awkward. The locality among global memory requests from different SMs (Streaming Multiprocessors) is predominantly harvested by the commonly-shared L2 with long access latency; while the in-core locality, which is crucial for performance delivery, is handled explicitly by user-controlled scratchpad memory. In this work, we disclose another type of data locality that has been long ignored but with performance boosting potential --- the inter-CTA locality. Exploiting such locality is rather challenging due to unclear hardware feasibility, unknown and inaccessible underlying CTA scheduler, and small in-core cache capacity. To address these issues, we first conduct a thorough empirical exploration on various modern GPUs and demonstrate that inter-CTA locality can be harvested, both spatially and temporally, on L1 or L1/Tex unified cache. Through further quantification process, we prove the significance and commonality of such locality among GPU applications, and discuss whether such reuse is exploitable. By leveraging these insights, we propose the concept of CTA-Clustering and its associated software-based techniques to reshape the default CTA scheduling in order to group the CTAs with potential reuse together on the same SM. Our techniques require no hardware modification and can be directly deployed on existing GPUs. In addition, we incorporate these techniques into an integrated framework for automatic inter-CTA locality optimization. We evaluate our techniques using a wide range of popular GPU applications on all modern generations of NVIDIA GPU architectures. The results show that our proposed techniques significantly improve cache performance through reducing L2 cache transactions by 55%, 65%, 29%, 28% on average for Fermi, Kepler, Maxwell and Pascal, respectively, leading to an average of 1.46x, 1.48x, 1.45x, 1.41x (up to 3.8x, 3.6x, 3.1x, 3.3x) performance speedups for applications with algorithm-related inter-CTA reuse.", "doi": "10.1145/3037697.3037709", "arxiv_id": "https://doi.org/10.1145/3037697.3037709", "pmid": null, "openalex_id": null, "s2_id": "4fa62de1bf9ed8b2543489ae1be7b08007a1dd76", "cited_by": 84, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037709"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037709", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Safecracker: Leaking Secrets through Compressed Caches", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Po-An Tsai", "Andrés Sánchez", "Christopher W. Fletcher", "Daniel Sánchez"], "abstract": "The hardware security crisis brought on by recent speculative execution attacks has shown that it is crucial to adopt a security-conscious approach to architecture research, analyzing the security of promising architectural techniques before they are deployed in hardware. This paper offers the first security analysis of cache compression, one such promising technique that is likely to appear in future processors. We find that cache compression is insecure because the compressibility of a cache line reveals information about its contents. Compressed caches introduce a new side channel that is especially insidious, as simply storing data transmits information about it. We present two techniques that make attacks on compressed caches practical. Pack+Probe allows an attacker to learn the compressibility of victim cache lines, and Safecracker leaks secret data efficiently by strategically changing the values of nearby data. Our evaluation on a proof-of-concept application shows that, on a common compressed cache architecture, Safecracker lets an attacker compromise a secret key in under 10ms, and worse, leak large fractions of program memory when used in conjunction with latent memory safety vulnerabilities. We also discuss potential ways to close this new compression-induced side channel. We hope this work prevents insecure cache compression techniques from reaching mainstream processors.", "doi": "10.1145/3373376.3378453", "arxiv_id": "https://doi.org/10.1145/3373376.3378453", "pmid": null, "openalex_id": null, "s2_id": "506481b6c9f8922415b28eae94b3cddc0e9fd774", "cited_by": 21, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378453", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378453"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378453", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Failure-Atomic Persistent Memory Updates via JUSTDO Logging", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Joseph Izraelevitz", "Terence Kelly", "Aasheesh Kolli"], "abstract": "Persistent memory invites applications to manipulate persistent data via load and store instructions. Because failures during updates may destroy transient data (e.g., in CPU registers), preserving data integrity in the presence of failures requires failure-atomic bundles of updates. Prior failure atomicity approaches for persistent memory entail overheads due to logging and CPU cache flushing. Persistent caches can eliminate the need for flushing, but conventional logging remains complex and memory intensive. We present the design and implementation of JUSTDO logging, a new failure atomicity mechanism that greatly reduces the memory footprint of logs, simplifies log management, and enables fast parallel recovery following failure. Crash-injection tests confirm that JUSTDO logging preserves application data integrity and performance evaluations show that it improves throughput 3x or more compared with a state-of-the-art alternative for a spectrum of data-intensive algorithms.", "doi": "10.1145/2872362.2872410", "arxiv_id": "https://doi.org/10.1145/2872362.2872410", "pmid": null, "openalex_id": null, "s2_id": "512a8925693d5f4b8e4cfde32bcd3c846a14b71e", "cited_by": 177, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872410", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872410"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872410", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proactive Control of Approximate Programs", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xin Sui", "Andrew Lenharth", "Donald S. Fussell", "Keshav Pingali"], "abstract": "Approximate computing trades off accuracy of results for resources such as energy or computing time. There is a large and rapidly growing literature on approximate computing that has focused mostly on showing the benefits of approximate computing. However, we know relatively little about how to control approximation in a disciplined way. In this paper, we address the problem of controlling approximation for non-streaming programs that have a set of \"knobs\" that can be dialed up or down to control the level of approximation of different components in the program. We formulate this control problem as a constrained optimization problem, and describe a system called Capri that uses machine learning to learn cost and error models for the program, and uses these models to determine, for a desired level of approximation, knob settings that optimize metrics such as running time or energy usage. Experimental results with complex benchmarks from different problem domains demonstrate the effectiveness of this approach.", "doi": "10.1145/2872362.2872402", "arxiv_id": "https://doi.org/10.1145/2872362.2872402", "pmid": null, "openalex_id": null, "s2_id": "514e626778a94c6781887b3109d646e852d50813", "cited_by": 74, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872402&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872402"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872402", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yiping Kang", "Johann Hauswald", "Cao Gao", "Austin Rovinski", "Trevor N. Mudge", "Jason Mars", "Lingjia Tang"], "abstract": "The computation for today's intelligent personal assistants such as Apple Siri, Google Now, and Microsoft Cortana, is performed in the cloud. This cloud-only approach requires significant amounts of data to be sent to the cloud over the wireless network and puts significant computational pressure on the datacenter. However, as the computational resources in mobile devices become more powerful and energy efficient, questions arise as to whether this cloud-only processing is desirable moving forward, and what are the implications of pushing some or all of this compute to the mobile devices on the edge.", "doi": "10.1145/3037697.3037698", "arxiv_id": "https://doi.org/10.1145/3037697.3037698", "pmid": null, "openalex_id": null, "s2_id": "51871d01c26acb651c81adaf073c32c3d9ec0f0b", "cited_by": 1598, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037698&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037698"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037698", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Reto Achermann", "Ashish Panwar", "Abhishek Bhattacharjee", "Timothy Roscoe", "Jayneel Gandhi"], "abstract": "Multi-socket machines with 1-100 TBs of physical memory are becoming prevalent. Applications running on such multi-socket machines suffer non-uniform bandwidth and latency when accessing physical memory. Decades of research have focused on data allocation and placement policies in NUMA settings, but there have been no studies on the question of how to place page-tables amongst sockets. We make the case for explicit page-table allocation policies and show that page-table placement is becoming crucial to overall performance. We propose Mitosis to mitigate NUMA effects on page-table walks by transparently replicating and migrating page-tables across sockets without application changes. This reduces the frequency of accesses to remote NUMA nodes when performing page-table walks. Mitosis uses two components: (i) a mechanism to efficiently enable and (ii) policies to effectively control -- page-table replication and migration. We implement Mitosis in Linux and evaluate its benefits on real hardware. Mitosis improves performance for large-scale multi-socket workloads by up to 1.34x by replicating page-tables across sockets. Moreover, it improves performance by up to 3.24x in cases when the OS migrates a process across sockets by enabling cross-socket page-table migration.", "doi": "10.1145/3373376.3378468", "arxiv_id": "1910.05398", "pmid": null, "openalex_id": null, "s2_id": "518c725c1d43a8a356c5f3cc57917df57359404a", "cited_by": 80, "type": "conference", "is_oa": true, "pdf_urls": ["https://figshare.com/articles/Mitosis_Transparently_Self-Replicating_Page-Tables_for_Large-Memory_Machines/11292692", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378468"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378468", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "KickStarter: Fast and Accurate Computations on Streaming Graphs via Trimmed Approximations", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Keval Vora", "Rajiv Gupta", "Guoqing Xu"], "abstract": "Continuous processing of a streaming graph maintains an approximate result of the iterative computation on a recent version of the graph. Upon a user query, the accurate result on the current graph can be quickly computed by feeding the approximate results to the iterative computation --- a form of incremental computation that corrects the (small amount of) error in the approximate result. Despite the effectiveness of this approach in processing growing graphs, it is generally not applicable when edge deletions are present --- existing approximations can lead to either incorrect results (e.g., monotonic computations terminate at an incorrect minima/maxima) or poor performance (e.g., with approximations, convergence takes longer than performing the computation from scratch).", "doi": "10.1145/3037697.3037748", "arxiv_id": "https://doi.org/10.1145/3037697.3037748", "pmid": null, "openalex_id": null, "s2_id": "52ae43121568425584b4b746b8266811b204302d", "cited_by": 178, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037748&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037748"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037748", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "An Energy-interference-free Hardware-Software Debugger for Intermittent Energy-harvesting Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alexei Colin", "Graham Harvey", "Brandon Lucia", "Alanson P. Sample"], "abstract": "Energy-autonomous computing devices have the potential to extend the reach of computing to a scale beyond either wired or battery-powered systems. However, these devices pose a unique set of challenges to application developers who lack both hardware and software support tools. Energy harvesting devices experience power intermittence which causes the system to reset and power-cycle unpredictably, tens to hundreds of times per second. This can result in code execution errors that are not possible in continuously-powered systems and cannot be diagnosed with conventional debugging tools such as JTAG and/or oscilloscopes. We propose the Energy-interference-free Debugger, a hardware and software platform for monitoring and debugging intermittent systems without adversely effecting their energy state. The Energy-interference-free Debugger re-creates a familiar debugging environment for intermittent software and augments it with debugging primitives for effective diagnosis of intermittence bugs. Our evaluation of the Energy-interference-free Debugger quantifies its energy-interference-freedom and shows its value in a set of debugging tasks in complex test programs and several real applications, including RFID code and a machine-learning-based activity recognition system.", "doi": "10.1145/2872362.2872409", "arxiv_id": "https://doi.org/10.1145/2872362.2872409", "pmid": null, "openalex_id": null, "s2_id": "5344d72cf5e9418e4d25deb85443ced111aa9ec8", "cited_by": 73, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872409"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872409", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SmoothOperator: Reducing Power Fragmentation and Improving Power Utilization in Large-scale Datacenters", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chang-Hong Hsu", "Qingyuan Deng", "Jason Mars", "Lingjia Tang"], "abstract": "With the ever growing popularity of cloud computing and web services, Internet companies are in need of increased computing capacity to serve the demand. However, power has become a major limiting factor prohibiting the growth in industry: it is often the case that no more servers can be added to datacenters without surpassing the capacity of the existing power infrastructure. In this work, we first investigate the power utilization in Facebook datacenters. We observe that the combination of provisioning for peak power usage, highly fluctuating traffic, and multi-level power delivery infrastructure leads to significant power budget fragmentation problem and inefficiently low power utilization. To address this issue, our insight is that heterogeneity of power consumption patterns among different services provides opportunities to re-shape the power profile of each power node by re-distributing services. By grouping services with asynchronous peak times under the same power node, we can reduce the peak power of each node and thus creating more power head-rooms to allow more servers hosted, achieving higher throughput. Based on this insight, we develop a workload-aware service placement framework to systematically spread the service instances with synchronous power patterns evenly under the power supply tree, greatly reducing the peak power draw at power nodes. We then leverage dynamic power profile reshaping to maximally utilize the headroom unlocked by our placement framework. Our experiments based on real production workload and power traces show that we are able to host up to 13% more machines in production, without changing the underlying power infrastructure. Utilizing the unleashed power headroom with dynamic reshaping, we achieve up to an estimated total of 15% and 11% throughput improvement for latency-critical service and batch service respectively at the same time, with up to 44% of energy slack reduction.", "doi": "10.1145/3173162.3173190", "arxiv_id": "https://doi.org/10.1145/3173162.3173190", "pmid": null, "openalex_id": null, "s2_id": "5483feb2b08312c7ed39336c0b3e68a39be8e016", "cited_by": 63, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173190", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173190"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173190", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507715", "arxiv_id": "2109.03371", "pmid": null, "openalex_id": null, "s2_id": "54b2afe54070c90755cee44c6d02f9a915a57a85", "cited_by": 126, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3503222.3507715"], "github": ["https://github.com/iqubit-org/phoenix", "https://zenodo.org/record/5780204"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Training for multi-resolution inference using reusable quantization terms", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sai Qian Zhang", "Bradley McDanel", "H. T. Kung", "Xin Dong"], "abstract": "Low-resolution uniform quantization (e.g., 4-bit bitwidth) for both Deep Neural Network (DNN) weights and data has emerged as an important technique for efficient inference. Departing from conventional quantization, we describe a novel training approach to support inference at multiple resolutions by reusing a single set of quantization terms (the same set of nonzero bits in values). The proposed approach streamlines the training and supports dynamic selection of resolution levels during inference. We evaluate the method on a diverse range of applications including multiple CNNs on ImageNet, an LSTM on Wikitext-2, and YOLO-v5 on COCO. We show that models resulting from our multi-resolution training can support up to 10 resolutions with only a moderate performance reduction (e.g., ≤ 1%) compared to training them individually. Lastly, using an FPGA, we compare our multi-resolution multiplier-accumulator (mMAC) against other conventional MAC designs and evaluate the inference performance. We show that the mMAC design broadens the choices in trading off cost, efficiency, and latency across a range of computational budgets.", "doi": "10.1145/3445814.3446741", "arxiv_id": "https://doi.org/10.1145/3445814.3446741", "pmid": null, "openalex_id": null, "s2_id": "5696ad182434f683eaa9b6e56fd9af001c345ae7", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446741"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446741", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 1A: New Architectures", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3296957.3252952", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "56c314a6c98416acaf1438d6c671de005fc23b04", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "StreamBox-HBM: Stream Analytics on High Bandwidth Hybrid Memory", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hongyu Miao", "Myeongjae Jeon", "Gennady Pekhimenko", "Kathryn S. McKinley", "Felix Xiaozhu Lin"], "abstract": "Stream analytics has an insatiable demand for memory and performance. Emerging hybrid memories combine commodity DDR4 DRAM with 3D-stacked High Bandwidth Memory (HBM) DRAM to meet such demands. However, achieving this promise is challenging because (1) HBM is capacity-limited and (2) HBM boosts performance best for sequential access and high parallelism workloads. At first glance, stream analytics appears a particularly poor match for HBM because they have high capacity demands and data grouping operations, their most demanding computations, use random access. This paper presents the design and implementation of StreamBox-HBM, a stream analytics engine that exploits hybrid memories to achieve scalable high performance. StreamBox-HBM performs data grouping with sequential access sorting algorithms in HBM, in contrast to random access hashing algorithms commonly used in DRAM. StreamBox-HBM solely uses HBM to store Key Pointer Array (KPA) data structures that contain only partial records (keys and pointers to full records) for grouping operations. It dynamically creates and manages prodigious data and pipeline parallelism, choosing when to allocate KPAs in HBM. It dynamically optimizes for both the high bandwidth and limited capacity of HBM, and the limited bandwidth and high capacity of standard DRAM. StreamBox-HBM achieves 110 million records per second and 238 GB/s memory bandwidth while effectively utilizing all 64 cores of Intel's Knights Landing, a commercial server with hybrid memory. It outperforms stream engines with sequential access algorithms without KPAs by 7x and stream engines with random access algorithms by an order of magnitude in throughput. To the best of our knowledge, StreamBox-HBM is the first stream engine optimized for hybrid memories.", "doi": "10.1145/3297858.3304031", "arxiv_id": "1901.01328", "pmid": null, "openalex_id": null, "s2_id": "57a717f57b364df675a46f30a4e895c2d3e647f1", "cited_by": 32, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304031", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304031"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304031", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Learning-based Memory Allocation for C++ Server Workloads", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Martin Maas", "David G. Andersen", "Michael Isard", "Mohammad Mahdi Javanmard", "Kathryn S. McKinley", "Colin Raffel"], "abstract": "Modern C++ servers have memory footprints that vary widely over time, causing persistent heap fragmentation of up to 2x from long-lived objects allocated during peak memory usage. This fragmentation is exacerbated by the use of huge (2MB) pages, a requirement for high performance on large heap sizes. Reducing fragmentation automatically is challenging because C++ memory managers cannot move objects. This paper presents a new approach to huge page fragmentation. It combines modern machine learning techniques with a novel memory manager (LLAMA) that manages the heap based on object lifetimes and huge pages (divided into blocks and lines). A neural network-based language model predicts lifetime classes using symbolized calling contexts. The model learns context-sensitive per-allocation site lifetimes from previous runs, generalizes over different binary versions, and extrapolates from samples to unobserved calling contexts. Instead of size classes, LLAMA's heap is organized by lifetime classes that are dynamically adjusted based on observed behavior at a block granularity. LLAMA reduces memory fragmentation by up to 78% while only using huge pages on several production servers. We address ML-specific questions such as tolerating mispredictions and amortizing expensive predictions across application execution. Although our results focus on memory allocation, the questions we identify apply to other system-level problems with strict latency and resource requirements where machine learning could be applied.", "doi": "10.1145/3373376.3378525", "arxiv_id": "https://doi.org/10.1145/3373376.3378525", "pmid": null, "openalex_id": null, "s2_id": "57c60eeaf38c1bfabc50daf202bdc0b8a1412f23", "cited_by": 85, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.1145/3373376.3378525", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378525"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378525", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Artemiy Margaritov", "Dmitrii Ustiugov", "Amna Shahab", "Boris Grot"], "abstract": "The last few years have seen a rapid adoption of cloud computing for data-intensive tasks. In the cloud environment, it is common for applications to run under virtualization and to share a virtual machine with other applications (e.g., in a virtual private cloud setup). In this setting, our work identifies a new address translation bottleneck caused by memory fragmentation stemming from the interaction of virtualization, colocation, and the Linux memory allocator. The fragmentation results in the effective cache footprint of the host PT being larger than that of the guest PT. The bloated footprint of the host PT leads to frequent cache misses during nested page walks, increasing page walk latency.", "doi": "10.1145/3445814.3446704", "arxiv_id": "https://doi.org/10.1145/3445814.3446704", "pmid": null, "openalex_id": null, "s2_id": "584301cb43c4e40d934b0e53290d99208e81a80d", "cited_by": 24, "type": "conference", "is_oa": true, "pdf_urls": ["https://www.research.ed.ac.uk/en/publications/ee19c3ca-15f5-4912-8b5f-b9ec0a9e6a60", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446704"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446704", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Page Fault Support for Network Controllers", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ilya Lesokhin", "Haggai Eran", "Shachar Raindel", "Guy Shapiro", "Sagi Grimberg", "Liran Liss", "Muli Ben-Yehuda", "Nadav Amit", "Dan Tsafrir"], "abstract": "Direct network I/O allows network controllers (NICs) to expose multiple instances of themselves, to be used by untrusted software without a trusted intermediary. Direct I/O thus frees researchers from legacy software, fueling studies that innovate in multitenant setups. Such studies, however, overwhelmingly ignore one serious problem: direct memory accesses (DMAs) of NICs disallow page faults, forcing systems to either pin entire address spaces to physical memory and thereby hinder memory utilization, or resort to APIs that pin/unpin memory buffers before/after they are DMAed, which complicates the programming model and hampers performance.", "doi": "10.1145/3037697.3037710", "arxiv_id": "https://doi.org/10.1145/3037697.3037710", "pmid": null, "openalex_id": null, "s2_id": "58badc39993fb8fbe29623dbece9405b0010b459", "cited_by": 39, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037710"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037710", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "RecSSD: near data processing for solid state drive based recommendation inference", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mark Wilkening", "Udit Gupta", "Samuel Hsia", "Caroline Trippel", "Carole-Jean Wu", "David Brooks", "Gu-Yeon Wei"], "abstract": "Neural personalized recommendation models are used across a wide variety of datacenter applications including search, social media, and entertainment. State-of-the-art models comprise large embedding tables that have billions of parameters requiring large memory capacities. Unfortunately, large and fast DRAM-based memories levy high infrastructure costs. Conventional SSD-based storage solutions offer an order of magnitude larger capacity, but have worse read latency and bandwidth, degrading inference performance. RecSSD is a near data processing based SSD memory system customized for neural recommendation inference that reduces end-to-end model inference latency by 2× compared to using COTS SSDs across eight industry-representative models.", "doi": "10.1145/3445814.3446763", "arxiv_id": "2102.00075", "pmid": null, "openalex_id": null, "s2_id": "595101f13b961d69c553ce1ed24f60f3f1085e02", "cited_by": 138, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2102.00075", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446763"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446763", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "COATCheck: Verifying Memory Ordering at the Hardware-OS Interface", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daniel Lustig", "Geet Sethi", "Margaret Martonosi", "Abhishek Bhattacharjee"], "abstract": "Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck, an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.", "doi": "10.1145/2872362.2872399", "arxiv_id": "https://doi.org/10.1145/2872362.2872399", "pmid": null, "openalex_id": null, "s2_id": "5a162249779f2a8ec0a51d83061f99a9a4d43cc0", "cited_by": 66, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872399?download=true", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872399"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872399", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 3A: Memory I", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248618", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "5bce508df2c23f50f461e4f2071400b5f30720a2", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 3A: Heterogeneous Architectures and Accelerators I", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252395", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "5bf9608ea8daac2235ca9d46a204d82ad8f387d5", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Beating OPT with Statistical Clairvoyance and Variable Size Caching", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Pengcheng Li", "Colin Pronovost", "William Wilson", "Benjamin Tait", "Jie Zhou", "Chen Ding", "John Criswell"], "abstract": "Caching techniques are widely used in today's computing infrastructure from virtual memory management to server cache and memory cache. This paper builds on two observations. First, the space utilization in cache can be improved by varying the cache size based on dynamic application demand. Second, it is easier to predict application behavior statistically than precisely. This paper presents a new variable-size cache that uses statistical knowledge of program behavior to maximize the cache performance. We measure performance using data access traces from real-world workloads, including Memcached traces from Facebook and storage traces from Microsoft Research. In an offline setting, the new cache is demonstrated to outperform even OPT, the optimal fixedsize cache which makes use of precise knowledge of program behavior.", "doi": "10.1145/3297858.3304067", "arxiv_id": "https://doi.org/10.1145/3297858.3304067", "pmid": null, "openalex_id": null, "s2_id": "5c27375e3c2051161063f885c61860bed1e10daf", "cited_by": 26, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304067", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304067"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304067", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Software Mitigation of Crosstalk on Noisy Intermediate-Scale Quantum Computers", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Prakash Murali", "David C. McKay", "Margaret Martonosi", "Ali Javadi-Abhari"], "abstract": "Crosstalk is a major source of noise in Noisy Intermediate-Scale Quantum (NISQ) systems and is a fundamental challenge for hardware design. When multiple instructions are executed in parallel, crosstalk between the instructions can corrupt the quantum state and lead to incorrect program execution. Our goal is to mitigate the application impact of crosstalk noise through software techniques. This requires (i) accurate characterization of hardware crosstalk, and (ii) intelligent instruction scheduling to serialize the affected operations. Since crosstalk characterization is computationally expensive, we develop optimizations which reduce the characterization overhead. On 3 20-qubit IBMQ systems, we demonstrate two orders of magnitude reduction in characterization time (compute time on the QC device) compared to all-pairs crosstalk measurements. Informed by these characterization, we develop a scheduler that judiciously serializes high crosstalk instructions balancing the need to mitigate crosstalk and exponential decoherence errors from serialization. On real-system runs on 3 IBMQ systems, our scheduler improves the error rate of application circuits by up to 5.6x, compared to the IBM instruction scheduler and offers near-optimal crosstalk mitigation in practice. In a broader picture, the difficulty of mitigating crosstalk has recently driven QC vendors to move towards sparser qubit connectivity or disabling nearby operations entirely in hardware, which can be detrimental to performance. Our work makes the case for software mitigation of crosstalk errors.", "doi": "10.1145/3373376.3378477", "arxiv_id": "2001.02826", "pmid": null, "openalex_id": null, "s2_id": "5c9ebbc55a0bb80a3ebbbcd258ca7554decbc6ef", "cited_by": 307, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378477", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378477"], "github": ["https://github.com/Qiskit/qiskit-terra"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378477", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Jaaru: efficiently model checking persistent memory programs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hamed Gorjiara", "Guoqing Harry Xu", "Brian Demsky"], "abstract": "Persistent memory (PM) technologies combine near DRAM performance with persistency and open the possibility of using one copy of a data structure as both a working copy and a persistent store of the data. Ensuring that these persistent data structures are crash consistent (i.e., power failures) is a major challenge. Stores to persistent memory are not immediately made persistent --- they initially reside in processor cache and are only written to PM when a flush occurs due to space constraints or explicit flush instructions. It is more challenging to test crash consistency for PM than for disks given the PM's byte-addressability that leads to significantly more states. We present Jaaru, a fully-automated and ultra-efficient model checker for PM programs. Key to Jaaru's efficiency is a new technique based on constraint refinement that can reduce the number of executions that must be explored by many orders of magnitude. This exploration technique effectively leverages commit stores, a common coding pattern, to reduce the model checking complexity from exponential in the length of program executions to quadratic. We have evaluated Jaaru with PMDK and RECIPE, and found 25 persistency bugs, 18 of which are new. Jaaru is also orders of magnitude more efficient than Yat, a model checker that eagerly explores all possible states.", "doi": "10.1145/3445814.3446735", "arxiv_id": "https://doi.org/10.1145/3445814.3446735", "pmid": null, "openalex_id": null, "s2_id": "5ce7bc7bf6a666f70a328e538f4a9b461f7957c7", "cited_by": 44, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446735", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446735"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446735", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "OpenPiton: An Open Source Manycore Research Framework", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jonathan Balkind", "Michael McKeown", "Yaosheng Fu", "Tri Minh Nguyen", "Yanqi Zhou", "Alexey Lavrov", "Mohammad Shahrad", "Adi Fuchs", "Samuel Payne", "Xiaohua Liang", "Matthew Matl", "David Wentzlaff"], "abstract": "Industry is building larger, more complex, manycore processors on the back of strong institutional knowledge, but academic projects face difficulties in replicating that scale. To alleviate these difficulties and to develop and share knowledge, the community needs open architecture frameworks for simulation, synthesis, and software exploration which support extensibility, scalability, and configurability, alongside an established base of verification tools and supported software. In this paper we present OpenPiton, an open source framework for building scalable architecture research prototypes from 1 core to 500 million cores. OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design. In addition, OpenPiton provides synthesis and backend scripts for ASIC and FPGA to enable other researchers to bring their designs to implementation. OpenPiton provides a complete verification infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and is written in industry standard Verilog. Multiple implementations of OpenPiton have been created including a taped-out 25-core implementation in IBM's 32nm process and multiple Xilinx FPGA prototypes.", "doi": "10.1145/2872362.2872414", "arxiv_id": "https://doi.org/10.1145/2872362.2872414", "pmid": null, "openalex_id": null, "s2_id": "5ced6a0aab1350ef1dba574e1faa05a726d9517e", "cited_by": 250, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872414&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872414"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872414", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "VeGen: a vectorizer generator for SIMD and beyond", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yishen Chen", "Charith Mendis", "Michael Carbin", "Saman P. Amarasinghe"], "abstract": "Vector instructions are ubiquitous in modern processors. Traditional compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications in domains such as image processing, digital signal processing, and machine learning. To target non-SIMD instruction, compiler developers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. As vector instruction sets continue to rapidly evolve, compilers cannot keep up with these new hardware capabilities. In this paper, we introduce Lane Level Parallelism (LLP), which captures the model of parallelism implemented by both SIMD and non-SIMD vector instructions. We present VeGen, a vectorizer generator that automatically generates a vectorization pass to uncover target-architecture-specific LLP in programs while using only instruction semantics as input. VeGen decouples, yet coordinates automatically generated target-specific vectorization utilities with its target-independent vectorization algorithm. This design enables us to systematically target non-SIMD vector instructions that until now require ad hoc coordination between different compiler stages. We show that VeGen can use non-SIMD vector instructions effectively, for example, getting speedup 3× (compared to LLVM’s vectorizer) on x265’s idct4 kernel.", "doi": "10.1145/3445814.3446692", "arxiv_id": "https://doi.org/10.1145/3445814.3446692", "pmid": null, "openalex_id": null, "s2_id": "5cfa2eb3d9f483e779204690cdfb0c057df09fbf", "cited_by": 53, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446692", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446692"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446692", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Programmer Productivity in a World of Mushy Interfaces: Challenges of the Post-ISA Reality", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Emmett Witchel"], "abstract": "Since 1964, we had the notion that the instruction set architecture (ISA) is a useful and fairly opaque abstraction layer between hardware and software. Software rode hardware's performance wave while remaining gloriously oblivious to hardware's growing complexity. Unfortunately, the jig is up. We still have ISAs, but the abstraction no longer offers seamless portability---parallel software needs to be tuned for different core counts, and heterogeneous processing elements (CPUs, GPUs, accelerators) further complicate programmability. We are better at building large-scale heterogeneous processors than we are at programming them. Maintaining software across multiple current platforms is difficult and porting to future platforms is also difficult. There have been many technical responses: virtual ISAs (e.g., NVIDIA's PTX), higher-level programming interfaces (e.g., CUDA or OpenCL), and late-stage compilation and platform-specific tailoring (e.g., Android ART), etc.", "doi": "10.1145/2872362.2876511", "arxiv_id": "https://doi.org/10.1145/2872362.2876511", "pmid": null, "openalex_id": null, "s2_id": "5d84e1d5fa3b95ab86cd203332c0b707f20ec776", "cited_by": 0, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2876511"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2876511", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ao Ren", "Zhe Li", "Caiwen Ding", "Qinru Qiu", "Yanzhi Wang", "Ji Li", "Xuehai Qian", "Bo Yuan"], "abstract": "With the recent advance of wearable devices and Internet of Things (IoTs), it becomes attractive to implement the Deep Convolutional Neural Networks (DCNNs) in embedded and portable systems. Currently, executing the software-based DCNNs requires high-performance servers, restricting the widespread deployment on embedded and mobile IoT devices. To overcome this obstacle, considerable research efforts have been made to develop highly-parallel and specialized DCNN accelerators using GPGPUs, FPGAs or ASICs. Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing DCNNs with high scalability and ultra-low hardware footprint. Since multiplications and additions can be calculated using AND gates and multiplexers in SC, significant reductions in power (energy) and hardware footprint can be achieved compared to the conventional binary arithmetic implementations. The tremendous savings in power (energy) and hardware resources allow immense design space for enhancing scalability and robustness for hardware DCNNs. This paper presents SC-DCNN, the first comprehensive design and optimization framework of SC-based DCNNs, using a bottom-up approach. We first present the designs of function blocks that perform the basic operations in DCNN, including inner product, pooling, and activation function. Then we propose four designs of feature extraction blocks, which are in charge of extracting features from input feature maps, by connecting different basic function blocks with joint optimization. Moreover, the efficient weight storage methods are proposed to reduce the area and power (energy) consumption. Putting all together, with feature extraction blocks carefully selected, SC-DCNN is holistically optimized to minimize area and power (energy) consumption while maintaining high network accuracy. Experimental results demonstrate that the LeNet5 implemented in SC-DCNN consumes only 17 mm2 area and 1.53 W power, achieves throughput of 781250 images/s, area efficiency of 45946 images/s/mm2, and energy efficiency of 510734 images/J.", "doi": "10.1145/3037697.3037746", "arxiv_id": "1611.05939", "pmid": null, "openalex_id": null, "s2_id": "5d89747390f1d5c3738b4bd95d46f26311d5f3cb", "cited_by": 212, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037746"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037746", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Challenging Sequential Bitstream Processing via Principled Bitwise Speculation", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Junqiao Qiu", "Lin Jiang", "Zhijia Zhao"], "abstract": "Many performance-critical applications traverse bitstreams with bitwise computations for better performance or higher space efficiency, such as multimedia processing and bitmap indexing. However, when these bitwise computations carry dependences, the entire bitstream traversal becomes serial, fundamentally limiting the scalability. In this work, we show that bitstream-carried dependences are actually \"breakable\" in many cases, with the adoption of a systematic treatment - principled bitwise speculation (PBS). The core idea of PBS stems from an analogy drawn between bitstream programs and sequential circuits, both of which transform binary sequences. In this new perspective, it becomes natural to model the dependences in bitstream programs with finite-state machines (FSM), a basic model for sequential circuits. To achieve this, PBS features an assembly of static analyses that reason about bitstream programs down to the bit level to identify the bits causing dependences, then it treats the value combinations of dependent bits as states to construct FSMs. The modeling, for the first time, enables the use of FSM speculation techniques to parallelize bitstream programs. Basically, by leveraging the state convergence of FSMs, the values of dependent bits can be predicted with much higher accuracies. In cases the prediction fails, PBS tries to directly \"rectify\" the wrong outputs based on bitwise logic, minimizing the mis-speculation costs. In addition, FSM shows even higher execution efficiency than the original program in some cases, making itself an optimized version to accelerate serial bitstream processing. We prototyped PBS using LLVM. Evaluation with real-world bitstream programs confirms the effectiveness of PBS, showing up to near-linear speedup on multicore/manycore machines.", "doi": "10.1145/3373376.3378461", "arxiv_id": "https://doi.org/10.1145/3373376.3378461", "pmid": null, "openalex_id": null, "s2_id": "5dc71b519ca0604e304d6b9f72289023bacc46e5", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378461", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378461"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378461", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Thesaurus: Efficient Cache Compression via Dynamic Clustering", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amin Ghasemazar", "Prashant J. Nair", "Mieszko Lis"], "abstract": "In this paper, we identify a previously untapped source of compressibility in cache working sets: clusters of cachelines that are similar, but not identical, to one another. To compress the cache, we can then store the \"clusteroid\" of each cluster together with the (much smaller) \"diffs\" needed to reconstruct the rest of the cluster. To exploit this opportunity, we propose a hardware-level on-line cacheline clustering mechanism based on locality-sensitive hashing. Our method dynamically forms clusters as they appear in the data access stream and retires them as they disappear from the cache. Our evaluations show that we achieve 2.25× compression on average (and up to 9.9×) on SPEC~CPU~2017 suite and is significantly higher than prior proposals scaled to an iso-silicon budget.", "doi": "10.1145/3373376.3378518", "arxiv_id": "https://doi.org/10.1145/3373376.3378518", "pmid": null, "openalex_id": null, "s2_id": "5de14798093866079c9472ab8c2ee6963ce381c9", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378518"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378518", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hyoukjun Kwon", "Ananda Samajdar", "Tushar Krishna"], "abstract": "Deep neural networks (DNN) have demonstrated highly promising results across computer vision and speech recognition, and are becoming foundational for ubiquitous AI. The computational complexity of these algorithms and a need for high energy-efficiency has led to a surge in research on hardware accelerators. % for this paradigm. To reduce the latency and energy costs of accessing DRAM, most DNN accelerators are spatial in nature, with hundreds of processing elements (PE) operating in parallel and communicating with each other directly. DNNs are evolving at a rapid rate, and it is common to have convolution, recurrent, pooling, and fully-connected layers with varying input and filter sizes in the most recent topologies.They may be dense or sparse. They can also be partitioned in myriad ways (within and across layers) to exploit data reuse (weights and intermediate outputs). All of the above can lead to different dataflow patterns within the accelerator substrate. Unfortunately, most DNN accelerators support only fixed dataflow patterns internally as they perform a careful co-design of the PEs and the network-on-chip (NoC). In fact, the majority of them are only optimized for traffic within a convolutional layer. This makes it challenging to map arbitrary dataflows on the fabric efficiently, and can lead to underutilization of the available compute resources. DNN accelerators need to be programmable to enable mass deployment. For them to be programmable, they need to be configurable internally to support the various dataflow patterns that could be mapped over them. To address this need, we present MAERI, which is a DNN accelerator built with a set of modular and configurable building blocks that can easily support myriad DNN partitions and mappings by appropriately configuring tiny switches. MAERI provides 8-459% better utilization across multiple dataflow mappings over baselines with rigid NoC fabrics.", "doi": "10.1145/3173162.3173176", "arxiv_id": "https://doi.org/10.1145/3173162.3173176", "pmid": null, "openalex_id": null, "s2_id": "5f0da3cedda449b72fe36fa78798651a038f515c", "cited_by": 450, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173176"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173176", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 7A: Accelerators: GPUs, ASICs, and Heterogeneous Systems", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248626", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "6027e94e00e54d1438c62363665441a98cf4fb3d", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Framework for Memory Oversubscription Management in Graphics Processing Units", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chen Li", "Rachata Ausavarungnirun", "Christopher J. Rossbach", "Youtao Zhang", "Onur Mutlu", "Yang Guo", "Jun Yang"], "abstract": "Modern discrete GPUs support unified memory and demand paging. Automatic management of data movement between CPU memory and GPU memory dramatically reduces developer effort. However, when application working sets exceed physical memory capacity, the resulting data movement can cause great performance loss.", "doi": "10.1145/3297858.3304044", "arxiv_id": "https://doi.org/10.1145/3297858.3304044", "pmid": null, "openalex_id": null, "s2_id": "602bde853df1ad413db5787c2a92f36253ae3692", "cited_by": 91, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304044", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304044"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304044", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "In-fat pointer: hardware-assisted tagged-pointer spatial memory safety defense with subobject granularity protection", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shengjie Xu", "Wei Huang", "David Lie"], "abstract": "Programming languages like C and C++ are not memory-safe because they provide programmers with low-level pointer manipulation primitives. The incorrect use of these primitives can result in bugs and security vulnerabilities: for example, spatial memory safety errors can be caused by dereferencing pointers outside the legitimate address range belonging to the corresponding object. While a range of schemes to provide protection against these vulnerabilities have been proposed, they all suffer from the lack of one or more of low performance overhead, compatibility with legacy code, or comprehensive protection for all objects and subobjects.", "doi": "10.1145/3445814.3446761", "arxiv_id": "https://doi.org/10.1145/3445814.3446761", "pmid": null, "openalex_id": null, "s2_id": "60c2723035c25b08c2aaaee4a77706d3a6ba40ab", "cited_by": 41, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446761", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446761"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446761", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Enabling Lightweight Transactions with Precision Time", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Pulkit A. Misra", "Jeffrey S. Chase", "Johannes Gehrke", "Alvin R. Lebeck"], "abstract": "Distributed transactional storage is an important service in today's data centers. Achieving high performance without high complexity is often a challenge for these systems due to sophisticated consistency protocols and multiple layers of abstraction. In this paper we show how to combine two emerging technologies---Software-Defined Flash (SDF) and precise synchronized clocks---to improve performance and reduce complexity for transactional storage within the data center.", "doi": "10.1145/3037697.3037722", "arxiv_id": "https://doi.org/10.1145/3037697.3037722", "pmid": null, "openalex_id": null, "s2_id": "614bdb9fce7c3088050520fc769376722eebe8e2", "cited_by": 5, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037722"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037722", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Antonios Katsarakis", "Vasilis Gavrielatos", "M. R. Siavash Katebzadeh", "Arpit Joshi", "Aleksandar Dragojevic", "Boris Grot", "Vijay Nagarajan"], "abstract": "Today's datacenter applications are underpinned by datastores that are responsible for providing availability, consistency, and performance. For high availability in the presence of failures, these datastores replicate data across several nodes. This is accomplished with the help of a reliable replication protocol that is responsible for maintaining the replicas strongly-consistent even when faults occur. Strong consistency is preferred to weaker consistency models that cannot guarantee an intuitive behavior for the clients. Furthermore, to accommodate high demand at real-time latencies, datastores must deliver high throughput and low latency.", "doi": "10.1145/3373376.3378496", "arxiv_id": "2001.09804", "pmid": null, "openalex_id": null, "s2_id": "61b34530352be07503e2a335acaf3f5c76873361", "cited_by": 79, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2001.09804", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378496"], "github": ["https://github.com/ease-lab/Hermes"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378496", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Frightening Small Children and Disconcerting Grown-ups: Concurrency in the Linux Kernel", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jade Alglave", "Luc Maranget", "Paul E. McKenney", "Andrea Parri", "Alan S. Stern"], "abstract": "Concurrency in the Linux kernel can be a contentious topic. The Linux kernel mailing list features numerous discussions related to consistency models, including those of the more than 30 CPU architectures supported by the kernel and that of the kernel itself. How are Linux programs supposed to behave? Do they behave correctly on exotic hardware? A formal model can help address such questions. Better yet, an executable model allows programmers to experiment with the model to develop their intuition. Thus we offer a model written in the cat language, making it not only formal, but also executable by the herd simulator. We tested our model against hardware and refined it in consultation with maintainers. Finally, we formalised the fundamental law of the Read-Copy-Update synchronisation mechanism, and proved that one of its implementations satisfies this law.", "doi": "10.1145/3173162.3177156", "arxiv_id": "https://doi.org/10.1145/3173162.3177156", "pmid": null, "openalex_id": null, "s2_id": "630b78dddd7d66a2e4513131727bb5ac80030c86", "cited_by": 65, "type": "conference", "is_oa": true, "pdf_urls": ["https://inria.hal.science/hal-01873636/document", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177156"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177156", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Rachata Ausavarungnirun", "Vance Miller", "Joshua Landgraf", "Saugata Ghose", "Jayneel Gandhi", "Adwait Jog", "Christopher J. Rossbach", "Onur Mutlu"], "abstract": "Graphics Processing Units (GPUs) exploit large amounts of threadlevel parallelism to provide high instruction throughput and to efficiently hide long-latency stalls. The resulting high throughput, along with continued programmability improvements, have made GPUs an essential computational resource in many domains. Applications from different domains can have vastly different compute and memory demands on the GPU. In a large-scale computing environment, to efficiently accommodate such wide-ranging demands without leaving GPU resources underutilized, multiple applications can share a single GPU, akin to how multiple applications execute concurrently on a CPU. Multi-application concurrency requires several support mechanisms in both hardware and software. One such key mechanism is virtual memory, which manages and protects the address space of each application. However, modern GPUs lack the extensive support for multi-application concurrency available in CPUs, and as a result suffer from high performance overheads when shared by multiple applications, as we demonstrate. We perform a detailed analysis of which multi-application concurrency support limitations hurt GPU performance the most. We find that the poor performance is largely a result of the virtual memory mechanisms employed in modern GPUs. In particular, poor address translation performance is a key obstacle to efficient GPU sharing. State-of-the-art address translation mechanisms, which were designed for single-application execution, experience significant inter-application interference when multiple applications spatially share the GPU. This contention leads to frequent misses in the shared translation lookaside buffer (TLB), where a single miss can induce long-latency stalls for hundreds of threads. As a result, the GPU often cannot schedule enough threads to successfully hide the stalls, which diminishes system throughput and becomes a first-order performance concern. Based on our analysis, we propose MASK, a new GPU framework that provides low-overhead virtual memory support for the concurrent execution of multiple applications. MASK consists of three novel address-translation-aware cache and memory management mechanisms that work together to largely reduce the overhead of address translation: (1) a token-based technique to reduce TLB contention, (2) a bypassing mechanism to improve the effectiveness of cached address translations, and (3) an application-aware memory scheduling scheme to reduce the interference between address translation and data requests. Our evaluations show that MASK restores much of the throughput lost to TLB contention. Relative to a state-of-the-art GPU TLB, MASK improves system throughput by 57.8%, improves IPC throughput by 43.4%, and reduces applicationlevel unfairness by 22.4%. MASK's system throughput is within 23.2% of an ideal GPU system with no address translation overhead.", "doi": "10.1145/3173162.3173169", "arxiv_id": "https://doi.org/10.1145/3173162.3173169", "pmid": null, "openalex_id": null, "s2_id": "636a4d1dcd7f1cfdd41db52b6c5de6c527b183e7", "cited_by": 120, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173169", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173169"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173169", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ReBudget: Trading Off Efficiency vs. Fairness in Market-Based Multicore Resource Allocation via Runtime Budget Reassignment", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiaodong Wang", "José F. Martínez"], "abstract": "Efficiently allocating shared resources in computer systems is critical to optimizing execution. Recently, a number of market-based solutions have been proposed to attack this problem. Some of them provide provable theoretical bounds to efficiency and/or fairness losses under market equilibrium. However, they are limited to markets with potentially important constraints, such as enforcing equal budget for all players, or curve-fitting players' utility into a specific function type. Moreover, they do not generally provide an intuitive \"knob\" to control efficiency vs. fairness. In this paper, we introduce two new metrics, Market Utility Range (MUR) and Market Budget Range (MBR), through which we provide for the first time theoretical bounds on efficiency and fairness of market equilibria under arbitrary budget assignments. We leverage this result and propose ReBudget, an iterative budget re-assignment algorithm that can be used to control efficiency vs. fairness at run-time. We apply our algorithm to a multi-resource allocation problem in multicore chips. Our evaluation using detailed execution-driven simulations shows that our budget re-assignment technique is intuitive, effective, and efficient.", "doi": "10.1145/2872362.2872382", "arxiv_id": "https://doi.org/10.1145/2872362.2872382", "pmid": null, "openalex_id": null, "s2_id": "6372699d8dda5d68d68dfb5f52f0d9193bbd5d52", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872382"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872382", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SIMDRAM: a framework for bit-serial SIMD processing using DRAM", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Nastaran Hajinazar", "Geraldo F. Oliveira", "Sven Gregorio", "João Dinis Ferreira", "Nika Mansouri-Ghiasi", "Minesh Patel", "Mohammed Alser", "Saugata Ghose", "Juan Gómez-Luna", "Onur Mutlu"], "abstract": "Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable full adoption of processing-using-DRAM, it is necessary to provide support for more complex operations. In this paper, we propose SIMDRAM, a flexible general-purpose processing-using-DRAM framework that (1) enables the efficient implementation of complex operations, and (2) provides a flexible mechanism tosupport the implementation of arbitrary user-defined operations. The SIMDRAM framework comprises three key steps. The first step builds an efficient MAJ/NOT representation of a given desired operation. The second step allocates DRAM rows that are reserved for computation to the operation’s input and output operands, and generates the required sequence of DRAM commands to perform the MAJ/NOT implementation of the desired operation in DRAM. The third step uses the SIMDRAM control unit located inside the memory controller to manage the computation of the operation from start to end, by executing the DRAM commands generated in the second step of the framework. We design the hardware and ISA support for SIMDRAM framework to (1) address key system integration challenges, and (2) allow programmers to employ new SIMDRAM operations without hardware changes.", "doi": "10.1145/3445814.3446749", "arxiv_id": "https://doi.org/10.1145/3445814.3446749", "pmid": null, "openalex_id": null, "s2_id": "63a77243ccf7ae22fd545ebba64866e352782f50", "cited_by": 219, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2012.11890", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446749"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446749", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "NVWAL: Exploiting NVRAM in Write-Ahead Logging", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Wook-Hee Kim", "Jinwoong Kim", "Woongki Baek", "Beomseok Nam", "Youjip Won"], "abstract": "Emerging byte-addressable non-volatile memory is considered an alternative storage device for database logs that require persistency and high performance. In this work, we develop NVWAL (NVRAM Write-Ahead Logging) for SQLite. The contribution of NVWAL consists of three elements: (i) byte-granularity differential logging that effectively eliminates the excessive I/O overhead of filesystem-based logging or journaling, (ii) transaction-aware lazy synchronization that reduces cache synchronization overhead by two-thirds, and (iii) user-level heap management of the NVRAM persistent WAL structure, which reduces the overhead of managing persistent objects.", "doi": "10.1145/2872362.2872392", "arxiv_id": "https://doi.org/10.1145/2872362.2872392", "pmid": null, "openalex_id": null, "s2_id": "642dd27ce62d51b042e134b0d0aec2f2e7cc4d29", "cited_by": 111, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872392"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872392", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Towards Efficient Superconducting Quantum Processor Architecture Design", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Gushu Li", "Yufei Ding", "Yuan Xie"], "abstract": "More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.,0", "doi": "10.1145/3373376.3378500", "arxiv_id": "1911.12879", "pmid": null, "openalex_id": null, "s2_id": "65ae097b05c9b6af717a141ee8450143c51f2a57", "cited_by": 66, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378500", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378500"], "github": ["https://github.com/cda-tum/dasqa"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378500", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Devirtualizing Memory in Heterogeneous Systems", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Swapnil Haria", "Mark D. Hill", "Michael M. Swift"], "abstract": "Accelerators are increasingly recognized as one of the major drivers of future computational growth. For accelerators, shared virtual memory (VM) promises to simplify programming and provide safe data sharing with CPUs. Unfortunately, the overheads of virtual memory, which are high for general-purpose processors, are even higher for accelerators. Providing accelerators with direct access to physical memory (PM) in contrast, provides high performance but is both unsafe and more difficult to program. We propose Devirtualized Memory (DVM) to combine the protection of VM with direct access to PM. By allocating memory such that physical and virtual addresses are almost always identical (VA==PA), DVM mostly replaces page-level address translation with faster region-level Devirtualized Access Validation (DAV). Optionally on read accesses, DAV can be overlapped with data fetch to hide VM overheads. DVM requires modest OS and IOMMU changes, and is transparent to the application. Implemented in Linux 4.10, DVM reduces VM overheads in a graph-processing accelerator to just 1.6% on average. DVM also improves performance by 2.1X over an optimized conventional VM implementation, while consuming 3.9X less dynamic energy for memory management. We further discuss DVM's potential to extend beyond accelerators to CPUs, where it reduces VM overheads to 5% on average, down from 29% for conventional VM.", "doi": "10.1145/3173162.3173194", "arxiv_id": "https://doi.org/10.1145/3173162.3173194", "pmid": null, "openalex_id": null, "s2_id": "65c302fc5eedfb33824ef18879eb53cc0327ea41", "cited_by": 64, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173194", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173194"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173194", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Rhythmic pixel regions: multi-resolution visual sensing system towards high-precision visual computing at low power", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Venkatesh Kodukula", "Alexander Shearer", "Van Nguyen", "Srinivas Lingutla", "Yifei Liu", "Robert LiKamWa"], "abstract": "High spatiotemporal resolution can offer high precision for vision applications, which is particularly useful to capture the nuances of visual features, such as for augmented reality. Unfortunately, capturing and processing high spatiotemporal visual frames generates energy-expensive memory traffic. On the other hand, low resolution frames can reduce pixel memory throughput, but reduce also the opportunities of high-precision visual sensing. However, our intuition is that not all parts of the scene need to be captured at a uniform resolution. Selectively and opportunistically reducing resolution for different regions of image frames can yield high-precision visual computing at energy-efficient memory data rates. To this end, we develop a visual sensing pipeline architecture that flexibly allows application developers to dynamically adapt the spatial resolution and update rate of different \"rhythmic pixel regions\" in the scene. We develop a system that ingests pixel streams from commercial image sensors with their standard raster-scan pixel read-out patterns, but only encodes relevant pixels prior to storing them in the memory. We also present streaming hardware to decode the stored rhythmic pixel region stream into traditional frame-based representations to feed into standard computer vision algorithms. We integrate our encoding and decoding hardware modules into existing video pipelines. On top of this, we develop runtime support allowing developers to flexibly specify the region labels. Evaluating our system on a Xilinx FPGA platform over three vision workloads shows 43-64% reduction in interface traffic and memory footprint, while providing controllable task accuracy.", "doi": "10.1145/3445814.3446737", "arxiv_id": "https://doi.org/10.1145/3445814.3446737", "pmid": null, "openalex_id": null, "s2_id": "65df3545d639ba40c4386b00fce5527a73ad9837", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446737"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446737", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PIBE: practical kernel control-flow hardening with profile-guided indirect branch elimination", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Victor Duta", "Cristiano Giuffrida", "Herbert Bos", "Erik van der Kouwe"], "abstract": "Control-flow hijacking, which allows an attacker to execute arbitrary code, remains a dangerous software vulnerability. Control-flow hijacking in speculated or transient execution is particularly insidious as it allows attackers to leak data from operating system kernels and other targets on commodity hardware, even in the absence of software bugs. Having made the jump from regular to transient execution in recent attacks, control-flow hijacking has become a top priority for developers. While powerful defenses against control-flow hijacking in regular execution are now sufficiently low-overhead to see wide-spread adoption, this is not the case for defenses in transient execution. Unfortunately, current techniques for mitigating attacks in transient execution exhibit high overheads—requiring a costly combination of defenses for every indirect branch. We show that the high overhead incurred by state-of-the-art mitigations is mostly due to the effect of hardening frequently executed branches. We propose PIBE, which offers comprehensive protection against control-flow hijacking at a fraction of the cost of existing solutions, by revisiting design choices in the compiler’s optimization passes. For every indirect branch, it decides whether to harden it with instrumentation code or elide it altogether using code transformations. By specifically removing the heavy hitters among the indirect branches through tailored profile-guided optimization, PIBE aggressively reduces the number of vulnerable branches to allow the simultaneous application of multiple state-of-the-art defenses on the remaining branches with practical overhead. Demonstrating our solution on the Linux kernel, one of the largest, most complex and most security-critical code bases on modern systems, we show that PIBE reduces the overhead of comprehensive defenses against transient control flow hijacking by an order of magnitude, from 149% to 10.6% on microbenchmarks and from ~ 40% to around 6% on several application benchmarks.", "doi": "10.1145/3445814.3446740", "arxiv_id": "https://doi.org/10.1145/3445814.3446740", "pmid": null, "openalex_id": null, "s2_id": "65e53168732b276d2fe81a1a7b769ac475605747", "cited_by": 15, "type": "conference", "is_oa": true, "pdf_urls": ["https://research.vu.nl/en/publications/2b26e535-a2a6-4627-882b-a333bb2c0e49", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446740"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446740", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sergi Abadal", "Albert Cabellos-Aparicio", "Eduard Alarcón", "Josep Torrellas"], "abstract": "In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.", "doi": "10.1145/2872362.2872396", "arxiv_id": "https://doi.org/10.1145/2872362.2872396", "pmid": null, "openalex_id": null, "s2_id": "6615bcd809168b1ae56505f9eb3b20c067a41547", "cited_by": 38, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872396?download=true", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872396"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872396", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Just-In-Time Compilation for Verilog: A New Technique for Improving the FPGA Programming Experience", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Eric Schkufza", "Michael Wei", "Christopher J. Rossbach"], "abstract": "FPGAs offer compelling acceleration opportunities for modern applications. However compilation for FPGAs is painfully slow, potentially requiring hours or longer. We approach this problem with a solution from the software domain: the use of a JIT. Code is executed immediately in a software simulator, and compilation is performed in the background. When finished, the code is moved into hardware, and from the user's perspective it simply gets faster. We have embodied these ideas in Cascade: the first JIT compiler for Verilog. Cascade reduces the time between initiating compilation and running code to less than a second, and enables generic printf debugging from hardware. Cascade preserves program performance to within 3× in a debugging environment, and has minimal effect on a finalized design. Crucially, these properties hold even for programs that perform side effects on connected IO devices. A user study demonstrates the value to experts and non-experts alike: Cascade encourages more frequent compilation, and reduces the time to produce working hardware designs.", "doi": "10.1145/3297858.3304010", "arxiv_id": "https://doi.org/10.1145/3297858.3304010", "pmid": null, "openalex_id": null, "s2_id": "66769bc2f4596f8e3ed72e999e074559ca8a02b5", "cited_by": 35, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304010&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304010"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304010", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Heterogeneous Isolated Execution for Commodity GPUs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Insu Jang", "Adrian Tang", "Taehoon Kim", "Simha Sethumadhavan", "Jaehyuk Huh"], "abstract": "Traditional CPUs and cloud systems based on them have embraced the hardware-based trusted execution environments to securely isolate computation from malicious OS or hardware attacks. However, GPUs and their cloud deployments have yet to include such support for hardware-based trusted computing. As large amounts of sensitive data are offloaded to GPU acceleration in cloud environments, ensuring the security of the data is a current and pressing need. As deployed today, the outsourced GPU model is vulnerable to attacks from compromised privileged software. To support isolated remote execution on GPUs even under vulnerable operating systems, this paper proposes a novel hardware and software architecture, called HIX (Heterogeneous Isolated eXecution). HIX does not require modifications to the GPU architecture to offer protections: Instead, it offers security by modifying the I/O interconnect between the CPU and GPU, and by refactoring the GPU device driver to work from within the CPU trusted environment. A result of the architectural choices behind HIX is that the concept can be applied to other offload accelerators besides GPUs. This work implements the proposed HIX architecture on an emulated machine with KVM and QEMU. Experimental results from the emulated security support with a real GPU show that the performance overhead for security is curtailed to 26% on average for the Rodinia benchmark, while providing secure isolated GPU computing.", "doi": "10.1145/3297858.3304021", "arxiv_id": "https://doi.org/10.1145/3297858.3304021", "pmid": null, "openalex_id": null, "s2_id": "67138d820d87b539b8ecf8d58b9d7c474a16dec6", "cited_by": 153, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304021&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304021"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304021", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PMTest: A Fast and Flexible Testing Framework for Persistent Memory Programs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sihang Liu", "Yizhou Wei", "Jishen Zhao", "Aasheesh Kolli", "Samira Manabi Khan"], "abstract": "Recent non-volatile memory technologies such as 3D XPoint and NVDIMMs have enabled persistent memory (PM) systems that can manipulate persistent data directly in memory. This advancement of memory technology has spurred the development of a new set of crash-consistent software (CCS) for PM - applications that can recover persistent data from memory in a consistent state in the event of a crash (e.g., power failure). CCS developed for persistent memory ranges from kernel modules to user-space libraries and custom applications. However, ensuring crash consistency in CCS is difficult and error-prone. Programmers typically employ low-level hardware primitives or transactional libraries to enforce ordering and durability guarantees that are required for ensuring crash consistency. Unfortunately, hardware can reorder instructions at runtime, making it difficult for the programmers to test whether the implementation enforces the correct ordering and durability guarantees. We believe that there is an urgent need for developing a testing framework that helps programmers identify crash consistency bugs in their CCS. We find that prior testing tools lack generality, i.e., they work only for one specific CCS or memory persistency model and/or introduce significant performance overhead. To overcome these drawbacks, we propose PMTest (available at https://pmtest.persistentmemory.org), a crash consistency testing framework that is both flexible and fast. PMTest provides flexibility by providing two basic assertion-like software checkers to test two fundamental characteristics of all CCS: the ordering and durability guarantee. These checkers can also serve as the building blocks of other application-specific, high-level checkers. PMTest enables fast testing by deducing the persist order without exhausting all possible orders. In the evaluation with eight programs, PMTest not only identified 45 synthetic crash consistency bugs, but also detected 3 new bugs in a file system (PMFS) and in applications developed using a transactional library (PMDK), while on average being 7.1× faster than the state-of-the-art tool.", "doi": "10.1145/3297858.3304015", "arxiv_id": "https://doi.org/10.1145/3297858.3304015", "pmid": null, "openalex_id": null, "s2_id": "6722d683f373f8fc8aef3b0db5e4fc95b549a014", "cited_by": 106, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304015&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304015"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304015", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Darwin: A Genomics Co-processor Provides up to 15,000X Acceleration on Long Read Assembly", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yatish Turakhia", "Gill Bejerano", "William J. Dally"], "abstract": "Genomics is transforming medicine and our understanding of life in fundamental ways. Genomics data, however, is far outpacing Moore»s Law. Third-generation sequencing technologies produce 100X longer reads than second generation technologies and reveal a much broader mutation spectrum of disease and evolution. However, these technologies incur prohibitively high computational costs. Over 1,300 CPU hours are required for reference-guided assembly of the human genome, and over 15,600 CPU hours are required for de novo assembly. This paper describes \"Darwin\" --- a co-processor for genomic sequence alignment that, without sacrificing sensitivity, provides up to $15,000X speedup over the state-of-the-art software for reference-guided assembly of third-generation reads. Darwin achieves this speedup through hardware/algorithm co-design, trading more easily accelerated alignment for less memory-intensive filtering, and by optimizing the memory system for filtering. Darwin combines a hardware-accelerated version of D-SOFT, a novel filtering algorithm, alignment at high speed, and with a hardware-accelerated version of GACT, a novel alignment algorithm. GACT generates near-optimal alignments of arbitrarily long genomic sequences using constant memory for the compute-intensive step. Darwin is adaptable, with tunable speed and sensitivity to match emerging sequencing technologies and to meet the requirements of genomic applications beyond read assembly.", "doi": "10.1145/3173162.3173193", "arxiv_id": "https://doi.org/10.1145/3173162.3173193", "pmid": null, "openalex_id": null, "s2_id": "67961a397a25380025a5bd4e9168e25798f81fd5", "cited_by": 183, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173193"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173193", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Noise-Aware Dynamical System Compilation for Analog Devices with Legno", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sara Achour", "Martin C. Rinard"], "abstract": "Reconfigurable analog devices are a powerful new computing substrate especially appropriate for executing computationally intensive dynamical system computations in an energy efficient manner. We present Legno, a compilation toolchain for programmable analog devices. Legno targets the HCDCv2, a programmable analog device designed to execute general nonlinear dynamical systems. To the best of our knowledge, Legno is the first compiler to successfully target a physical (as opposed to simulated) programmable analog device for dynamical systems and this paper is the first to present experimental results for any compiled computation executing on any physical programmable analog device of this class. The Legno compiler synthesizes analog circuits from parametric and specialized blocks and account for analog noise, quantization error, and manufacturing variations within the device. We evaluate the compiled configurations on the Sendyne S100Asy RevU development board on twelve benchmarks from physics, controls, and biology. Our results show that Legno produces accurate computations on the analog device. The computations execute in 0.50-5.92 ms and consume 0.28-5.67 uJ of energy.", "doi": "10.1145/3373376.3378449", "arxiv_id": "https://doi.org/10.1145/3373376.3378449", "pmid": null, "openalex_id": null, "s2_id": "693e576650a91b404679967375dbd29c6ba5ddad", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378449", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378449"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378449", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tanmay Gangwani", "Adam Morrison", "Josep Torrellas"], "abstract": "In multicores, performance-critical synchronization is increasingly performed in a lock-free manner using atomic instructions such as CAS or LL/SC. However, when many processors synchronize on the same variable, performance can still degrade significantly. Contending writes get serialized, creating a non-scalable condition. Past proposals that build hardware queues of synchronizing processors do not fundamentally solve this problem---at best, they help to efficiently serialize the contending writes.", "doi": "10.1145/2872362.2872400", "arxiv_id": "https://doi.org/10.1145/2872362.2872400", "pmid": null, "openalex_id": null, "s2_id": "6a26ded787801fb7c29d2fe78286dff3abd7a8f5", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872400"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872400", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Static Detection of Event-based Races in Android Apps", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yongjian Hu", "Iulian Neamtiu"], "abstract": "Event-based races are the main source of concurrency errors in Android apps. Prior approaches for scalable detection of event-based races have been dynamic. Due to their dynamic nature, these approaches suffer from coverage and false negative issues. We introduce a precise and scalable static approach and tool, named SIERRA, for detecting Android event-based races. SIERRA is centered around a new concept of \"concurrency action\" (that reifies threads, events/messages, system and user actions) and statically-derived order (happens-before relation) between actions. Establishing action order is complicated in Android, and event-based systems in general, because of externally-orchestrated control flow, use of callbacks, asynchronous tasks, and ad-hoc synchronization. We introduce several novel approaches that enable us to infer order relations statically: auto-generated code models which impose order among lifecycle and GUI events; a novel context abstraction for event-driven programs named action-sensitivity and finally, on-demand path sensitivity via backward symbolic execution to further rule out false positives. We have evaluated SIERRA on 194 Android apps. Of these, we chose 20 apps for manual analysis and comparison with a state-of-the-art dynamic race detector. Experimental results show that SIERRA is effective and efficient, typically taking 960 seconds to analyze an app and revealing 43 potential races. Compared with the dynamic race detector, SIERRA discovered an average 29.5 true races with 3.5 false positives, where the dynamic detector only discovered 4 races (hence missing 25.5 races per app) -- this demonstrates the advantage of a precise static approach. We believe that our approach opens the way for precise analysis and static event race detection in other event-driven systems beyond Android.", "doi": "10.1145/3173162.3173173", "arxiv_id": "https://doi.org/10.1145/3173162.3173173", "pmid": null, "openalex_id": null, "s2_id": "6a86642f53aabfbaf0fd309377323a58f3c1d864", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173173", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173173"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173173", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Architectural Support for Containment-based Security", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hansen Zhang", "Soumyadeep Ghosh", "Jordan Fix", "Sotiris Apostolakis", "Stephen R. Beard", "Nayana P. Nagendra", "Taewook Oh", "David I. August"], "abstract": "Software security techniques rely on correct execution by the hardware. Securing hardware components has been challenging due to their complexity and the proportionate attack surface they present during their design, manufacture, deployment, and operation. Recognizing that external communication represents one of the greatest threats to a system's security, this paper introduces the TrustGuard containment architecture. TrustGuard contains malicious and erroneous behavior using a relatively simple and pluggable gatekeeping hardware component called the Sentry. The Sentry bridges a physical gap between the untrusted system and its external interfaces. TrustGuard allows only communication that results from the correct execution of trusted software, thereby preventing the ill effects of actions by malicious hardware or software from leaving the system. The simplicity and pluggability of the Sentry, which is implemented in less than half the lines of code of a simple in-order processor, enables additional measures to secure this root of trust, including formal verification, supervised manufacture, and supply chain diversification with less than a 15% impact on performance.", "doi": "10.1145/3297858.3304020", "arxiv_id": "https://doi.org/10.1145/3297858.3304020", "pmid": null, "openalex_id": null, "s2_id": "6ad1ee1c94d81d39529377a751c9544dae783576", "cited_by": 11, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304020", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304020"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304020", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 5B: Cloud Computing", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252402", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "6e21023b9b155305b8bb9189ea436cac50f83a62", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 8A: Cloud", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248628", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "6e42bb1431325b232b255971a6fd92102c69184d", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Scaling up Superoptimization", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Phitchaya Mangpo Phothilimthana", "Aditya Thakur", "Rastislav Bodík", "Dinakar Dhurjati"], "abstract": "Developing a code optimizer is challenging, especially for new, idiosyncratic ISAs. Superoptimization can, in principle, discover machine-specific optimizations automatically by searching the space of all instruction sequences. If we can increase the size of code fragments a superoptimizer can optimize, we will be able to discover more optimizations. We develop LENS, a search algorithm that increases the size of code a superoptimizer can synthesize by rapidly pruning away invalid candidate programs. Pruning is achieved by selectively refining the abstraction under which candidates are considered equivalent, only in the promising part of the candidate space. LENS also uses a bidirectional search strategy to prune the candidate space from both forward and backward directions. These pruning strategies allow LENS to solve twice as many benchmarks as existing enumerative search algorithms, while LENS is about 11-times faster. Additionally, we increase the effective size of the superoptimized fragments by relaxing the correctness condition using contexts (surrounding code). Finally, we combine LENS with complementary search techniques into a cooperative superoptimizer, which exploits the stochastic search to make random jumps in a large candidate space, and a symbolic (SAT-solver-based) search to synthesize arbitrary constants. While existing superoptimizers consistently solve 9--16 out of 32 benchmarks, the cooperative superoptimizer solves 29 benchmarks. It can synthesize code fragments that are up to 82% faster than code generated by gcc -O3 from WiBench and MiBench.", "doi": "10.1145/2872362.2872387", "arxiv_id": "https://doi.org/10.1145/2872362.2872387", "pmid": null, "openalex_id": null, "s2_id": "6f16d9747d257c6a1ef91dc6a73fe32386c7ea8d", "cited_by": 119, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872387&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872387"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872387", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Prudent Memory Reclamation in Procrastination-Based Synchronization", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Aravinda Prasad", "K. Gopinath"], "abstract": "Procrastination is the fundamental technique used in synchronization mechanisms such as Read-Copy-Update (RCU) where writers, in order to synchronize with readers, defer the freeing of an object until there are no readers referring to the object. The synchronization mechanism determines when the deferred object is safe to reclaim and when it is actually reclaimed. Hence, such memory reclamations are completely oblivious of the memory allocator state. This induces poor memory allocator performance, for instance, when the reclamations are ill-timed. Furthermore, deferred objects provide hints about the future that inform memory regions that are about to be freed. Although useful, hints are not exploited as deferred objects are not visible to memory allocators. We introduce Prudence, a dynamic memory allocator, that is tightly integrated with the synchronization mechanism to ensure visibility of deferred objects to the memory allocator. Such an integration enables Prudence to (i) identify the safe time to reclaim deferred objects' memory, (ii) have an inclusive view of the allocated, free and about-to-be-freed objects, and (iii) exploit optimizations based on the hints about the future during important state transitions. Our evaluation in the Linux kernel shows that Prudence integrated with RCU performs 3.9X to 28X better in micro-benchmarks compared to SLUB, a recent memory allocator in the Linux kernel. It also improves the overall performance perceptibly (4%-18%) for a mix of widely used synthetic and application benchmarks. Further, it performs better (up to 98%) in terms of object hits in caches, object cache churns, slab churns, peak memory usage and total fragmentation, when compared with the SLUB allocator.", "doi": "10.1145/2872362.2872405", "arxiv_id": "https://doi.org/10.1145/2872362.2872405", "pmid": null, "openalex_id": null, "s2_id": "6f86cbe7b4b98862476529fcda29fee0b2004e62", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872405"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872405", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Meysam Taassori", "Ali Shafiee", "Rajeev Balasubramonian"], "abstract": "Intel's SGX offers state-of-the-art security features, including confidentiality, integrity, and authentication (CIA) when accessing sensitive pages in memory. Sensitive pages are placed in an Enclave Page Cache (EPC) within the physical memory before they can be accessed by the processor. To control the overheads imposed by CIA guarantees, the EPC operates with a limited capacity (currently 128 MB). Because of this limited EPC size, sensitive pages must be frequently swapped between EPC and non-EPC regions in memory. A page swap is expensive (about 40K cycles) because it requires an OS system call, page copying, updates to integrity trees and metadata, etc. Our analysis shows that the paging overhead can slow the system on average by 5×, and other studies have reported even higher slowdowns for memory-intensive workloads. The paging overhead can be reduced by growing the size of the EPC to match the size of physical memory, while allowing the EPC to also accommodate non-sensitive pages. However, at least two important problems must be addressed to enable this growth in EPC: (i) the depth of the integrity tree and its cacheability must be improved to keep memory bandwidth overheads in check, (ii) the space overheads of integrity verification (tree and MACs) must be reduced. We achieve both goals by introducing a variable arity unified tree (VAULT) organization that is more compact and has lower depth. We further reduce the space overheads with techniques that combine MAC sharing and compression. With simulations, we show that the combination of our techniques can address most inefficiencies in SGX memory access and improve overall performance by 3.7×, relative to an SGX baseline, while incurring a memory capacity over-head of only 4.7%.", "doi": "10.1145/3173162.3177155", "arxiv_id": "https://doi.org/10.1145/3173162.3177155", "pmid": null, "openalex_id": null, "s2_id": "71051ca775b27751a77a751263b837157f4cd013", "cited_by": 168, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3173162.3177155", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177155"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177155", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "An Architecture Supporting Formal and Compositional Binary Analysis", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Joseph McMahan", "Michael Christensen", "Lawton Nichols", "Jared Roesch", "Sung-Yee Guo", "Ben Hardekopf", "Timothy Sherwood"], "abstract": "Building a trustworthy life-critical embedded system requires deep reasoning about the potential effects that sequences of machine instructions can have on full system operation. Rather than trying to analyze complete binaries and the countless ways their instructions can interact with one another --- memory, side effects, control registers, implicit state, etc. --- we explore a new approach. We propose an architecture controlled by a thin computational layer designed to tightly correspond with the lambda calculus, drawing on principles of functional programming to bring the assembly much closer to myriad reasoning frameworks, such as the Coq proof assistant. This approach allows assembly-level verified versions of critical code to operate safely in tandem with arbitrary code, including imperative and unverified system components, without the need for large supporting trusted computing bases. We demonstrate that this computational layer can be built in such a way as to simultaneously provide full programmability and compact, precise, and complete semantics, while still using hardware resources comparable to normal embedded systems. To demonstrate the practicality of this approach, our FPGA-implemented prototype runs an embedded medical application which monitors and treats life-threatening arrhythmias. Though the system integrates untrusted and imperative components, our architecture allows for the formal verification of multiple properties of the end-to-end system, including a proof of correctness of the assembly-level implementation of the core algorithm, the integrity of trusted data via a non-interference proof, and a guarantee that our prototype meets critical timing requirements.", "doi": "10.1145/3037697.3037733", "arxiv_id": "https://doi.org/10.1145/3037697.3037733", "pmid": null, "openalex_id": null, "s2_id": "72b671d4415201f4e428179929202eeb3236438d", "cited_by": 6, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037733"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037733", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Specifying and Checking File System Crash-Consistency Models", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["James Bornholt", "Antoine Kaufmann", "Jialin Li", "Arvind Krishnamurthy", "Emina Torlak", "Xi Wang"], "abstract": "Applications depend on persistent storage to recover state after system crashes. But the POSIX file system interfaces do not define the possible outcomes of a crash. As a result, it is difficult for application writers to correctly understand the ordering of and dependencies between file system operations, which can lead to corrupt application state and, in the worst case, catastrophic data loss. This paper presents crash-consistency models, analogous to memory consistency models, which describe the behavior of a file system across crashes. Crash-consistency models include both litmus tests, which demonstrate allowed and forbidden behaviors, and axiomatic and operational specifications. We present a formal framework for developing crash-consistency models, and a toolkit, called Ferrite, for validating those models against real file system implementations. We develop a crash-consistency model for ext4, and use Ferrite to demonstrate unintuitive crash behaviors of the ext4 implementation. To demonstrate the utility of crash-consistency models to application writers, we use our models to prototype proof-of-concept verification and synthesis tools, as well as new library interfaces for crash-safe applications.", "doi": "10.1145/2872362.2872406", "arxiv_id": "https://doi.org/10.1145/2872362.2872406", "pmid": null, "openalex_id": null, "s2_id": "730bf7743b4e3d355d435a73d866a9f7646f1751", "cited_by": 89, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872406&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872406"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872406", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mingyu Gao", "Jing Pu", "Xuan Yang", "Mark Horowitz", "Christos Kozyrakis"], "abstract": "The high accuracy of deep neural networks (NNs) has led to the development of NN accelerators that improve performance by two orders of magnitude. However, scaling these accelerators for higher performance with increasingly larger NNs exacerbates the cost and energy overheads of their memory systems, including the on-chip SRAM buffers and the off-chip DRAM channels.", "doi": "10.1145/3037697.3037702", "arxiv_id": "https://doi.org/10.1145/3037697.3037702", "pmid": null, "openalex_id": null, "s2_id": "733a765e1f54eb86dbaabe03d7ba66d72363f665", "cited_by": 567, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037702&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037702"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037702", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yunong Shi", "Nelson Leung", "Pranav Gokhale", "Zane M. Rossi", "David I. Schuster", "Henry Hoffmann", "Frederic T. Chong"], "abstract": "Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of $5\\times$, with a maximum of $10\\times$. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.", "doi": "10.1145/3297858.3304018", "arxiv_id": "1902.01474", "pmid": null, "openalex_id": null, "s2_id": "73f6255c81418fb8eb4610cd279bf378b29b4534", "cited_by": 145, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304018", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304018"], "github": ["https://github.com/kashish0405/QuantumComputing_GateOptimisation", "https://github.com/kashish0405/Gate-Optimisation"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304018", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 1: ASPLOS Highlights I", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248616", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "73fb077aca3b092f64ee2a4bba7791821f786974", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Lynx: A SmartNIC-driven Accelerator-centric Architecture for Network Servers", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Maroun Tork", "Lina Maudlej", "Mark Silberstein"], "abstract": "This paper explores new opportunities afforded by the growing deployment of compute and I/O accelerators to improve the performance and efficiency of hardware-accelerated computing services in data centers.", "doi": "10.1145/3373376.3378528", "arxiv_id": "https://doi.org/10.1145/3373376.3378528", "pmid": null, "openalex_id": null, "s2_id": "741dcb898f55439db52283d0cb44490a2712f343", "cited_by": 96, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378528"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378528", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Swizzle Inventor: Data Movement Synthesis for GPU Kernels", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Phitchaya Mangpo Phothilimthana", "Archibald Samuel Elliott", "An Wang", "Abhinav Jangda", "Bastian Hagedorn", "Henrik Barthels", "Samuel J. Kaufman", "Vinod Grover", "Emina Torlak", "Rastislav Bodík"], "abstract": "Utilizing memory and register bandwidth in modern architectures may require swizzles --- non-trivial mappings of data and computations onto hardware resources --- such as shuffles. We develop Swizzle Inventor to help programmers implement swizzle programs, by writing program sketches that omit swizzles and delegating their creation to an automatic synthesizer. Our synthesis algorithm scales to real-world programs, allowing us to invent new GPU kernels for stencil computations, matrix transposition, and a finite field multiplication algorithm (used in cryptographic applications). The synthesized 2D convolution and finite field multiplication kernels are on average 1.5--3.2x and 1.1--1.7x faster, respectively, than expert-optimized CUDA kernels.", "doi": "10.1145/3297858.3304059", "arxiv_id": "https://doi.org/10.1145/3297858.3304059", "pmid": null, "openalex_id": null, "s2_id": "744ac2aea687aa5ffa410f5e0fb1c353232b6a2f", "cited_by": 45, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304059", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304059"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304059", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Computational Temporal Logic for Superconducting Accelerators", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Georgios Tzimpragos", "Dilip Vasudevan", "Nestan Tsiskaridze", "George Michelogiannakis", "Advait Madhavan", "Jennifer Volk", "John Shalf", "Timothy Sherwood"], "abstract": "Superconducting logic offers the potential to perform computation at tremendous speeds and energy savings. However, a \"semantic gap\" lies between the level-driven logic that traditional hardware designs accept as a foundation and the pulse-driven logic that is naturally supported by the most compelling superconducting technologies. A pulse, unlike a level signal, will fire through a channel for only an instant. Arranging the network of superconducting components so that input pulses always arrive simultaneously to \"logic gates'' to maintain the illusion of Boolean-only evaluation is a significant engineering hurdle. In this paper, we explore computing in a new and more native tongue for superconducting logic: time of arrival. Building on recent work in delay-based computations we show that superconducting logic can naturally compute directly over temporal relationships between pulse arrivals, that the computational relationships between those pulse arrivals can be formalized through a functional extension to a temporal predicate logic used in the verification community, and that the resulting architectures can operate asynchronously and describe real and useful computations. We verify our hypothesis through a combination of detailed analog circuit models, a formal analysis of our abstractions, and an evaluation in the context of several superconducting accelerators.", "doi": "10.1145/3373376.3378517", "arxiv_id": "https://doi.org/10.1145/3373376.3378517", "pmid": null, "openalex_id": null, "s2_id": "746d77585ee8a9eb1b1bf70f3340ff7abcf4a6f2", "cited_by": 45, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378517", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378517"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378517", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ProbeGuard: Mitigating Probing Attacks Through Reactive Program Transformations", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Koustubha Bhat", "Erik van der Kouwe", "Herbert Bos", "Cristiano Giuffrida"], "abstract": "Many modern defenses against code reuse rely on hiding sensitive data such as shadow stacks in a huge memory address space. While much more efficient than traditional integrity-based defenses, these solutions are vulnerable to probing attacks which quickly locate the hidden data and compromise security. This has led researchers to question the value of information hiding in real-world software security. Instead, we argue that such a limitation is not fundamental and that information hiding and integrity-based defenses are two extremes of a continuous spectrum of solutions. We propose a solution, ProbeGuard, that automatically balances performance and security by deploying an existing information hiding based baseline defense and then incrementally moving to more powerful integrity-based defenses by hotpatching when probing attacks occur. ProbeGuard is efficient, provides strong security, and gracefully trades off performance upon encountering more probing primitives.", "doi": "10.1145/3297858.3304073", "arxiv_id": "https://doi.org/10.1145/3297858.3304073", "pmid": null, "openalex_id": null, "s2_id": "747a5720733cd291ff60431552e58d8a68ff0a98", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304073", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304073"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304073", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PnP: Pruning and Prediction for Point-To-Point Iterative Graph Analytics", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chengshuo Xu", "Keval Vora", "Rajiv Gupta"], "abstract": "Frequently used parallel iterative graph analytics algorithms are computationally expensive. However, researchers have observed that applications often require point-to-point versions of these analytics algorithms that are less demanding. In this paper we introduce the PnP parallel framework for iterative graph analytics that processes a stream of pointto-point queries with each involving a single source and destination vertex pair. The efficiency of our framework is derived from the following two novel features: online Pruning of graph exploration that eliminates propagation from vertices that are determined to not contribute to a query's final solution; and dynamic direction Prediction for solving the query in either forward (from source) or backward (from destination) direction as their costs can differ greatly. PnP employs a two-phase algorithm where, Phase 1 briefly traverses the graph in both directions to predict the faster direction and enable pruning; then Phase 2 completes query evaluation by running the algorithm for the chosen direction till it converges. Our experiments show that PnP responds to queries rapidly because of accurate direction selection and effective pruning that often offsets the runtime overhead of direction prediction. PnP substantially outperforms Quegel, the only other point-to-point query evaluation framework. Our experiments on multiple benchmarks and graphs show that PnP on a single machine is 8.2 to 3116 faster than Quegel on a cluster of four machines.", "doi": "10.1145/3297858.3304012", "arxiv_id": "https://doi.org/10.1145/3297858.3304012", "pmid": null, "openalex_id": null, "s2_id": "7480092a3c7051557b75b03afe443c30970b6eb1", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304012", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304012"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304012", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Klotski: Efficient Obfuscated Execution against Controlled-Channel Attacks", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Pan Zhang", "Chengyu Song", "Heng Yin", "Deqing Zou", "Elaine Shi", "Hai Jin"], "abstract": "Intel Software Guard eXtensions (SGX) provides a hardware-based trusted execution environment for security-sensitive computations. A program running inside the trusted domain (an enclave) is protected against direct attacks from other software, including privileged software like the operating system (OS), the hypervisor, and low-level firmwares. However, recent research has shown that the SGX is vulnerable to a set of side-channel attacks that allow attackers to compromise the confidentiality of an enclave's execution, such as the controlled-channel attack. Unfortunately, existing defenses either provide an incomplete protection or impose too much performance overhead. In this work, we propose Klotski, an efficient obfuscated execution technique to defeat the controlled-channel attacks with a tunable trade-off between security and performance. From a high level, Klotski emulates a secure memory subsystem. It leverages an enhanced ORAM protocol to load code and data into two software caches with configurable size, which are re-randomized for after a configurable interval. More importantly, Klotski employs several optimizations to reduce the performance overhead caused by software-based address translation and software cache replacement. Evaluation results show that Klotski is secure against controlled-channel attacks and its performance overhead much lower than previous solutions.", "doi": "10.1145/3373376.3378487", "arxiv_id": "https://doi.org/10.1145/3373376.3378487", "pmid": null, "openalex_id": null, "s2_id": "74aa5ca8997a7292edac2d064380f782fbd7c0b6", "cited_by": 25, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378487", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378487"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378487", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Quantum Computing is Getting Real: Architecture, PL, and OS Roles in Closing the Gap between Quantum Algorithms and Machines", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Frederic T. Chong"], "abstract": "Quantum computing is at an inflection point, where 50-qubit (quantum bit) machines have been built, 100-qubit machines are just around the corner, and even 1000-qubit machines are perhaps only a few years away. These machines have the potential to fundamentally change our concept of what is computable and demonstrate practical applications in areas such as quantum chemistry, optimization, and quantum simulation. Yet a significant resource gap remains between practical quantum algorithms and real machines. There is an urgent shortage of the necessary computer scientists to work on software and architectures to close this gap. I will outline several grand research challenges in closing this gap, including programming language design, software and hardware verification, defining and perforating abstraction boundaries, cross-layer optimization, managing parallelism and communication, mapping and scheduling computations, reducing control complexity, machine-specific optimizations, learning error patterns, and many more. I will also describe the resources and infrastructure available for starting research in quantum computing and for tackling these challenges.", "doi": "10.1145/3173162.3177152", "arxiv_id": "https://doi.org/10.1145/3173162.3177152", "pmid": null, "openalex_id": null, "s2_id": "75ba2313e3156fe8c35dce92c60af828a4fe56ee", "cited_by": 4, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3177152", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177152"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177152", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sabrina M. Neuman", "Brian Plancher", "Thomas Bourgeat", "Thierry Tambe", "Srinivas Devadas", "Vijay Janapa Reddi"], "abstract": "Robotics applications have hard time constraints and heavy computational burdens that can greatly benefit from domain-specific hardware accelerators. For the latency-critical problem of robot motion planning and control, there exists a performance gap of at least an order of magnitude between joint actuator response rates and state-of-the-art software solutions. Hardware acceleration can close this gap, but it is essential to define automated hardware design flows to keep the design process agile as applications and robot platforms evolve. To address this challenge, we introduce robomorphic computing: a methodology to transform robot morphology into a customized hardware accelerator morphology. We (i) present this design methodology, using robot topology and structure to exploit parallelism and matrix sparsity patterns in accelerator hardware; (ii) use the methodology to generate a parameterized accelerator design for the gradient of rigid body dynamics, a key kernel in motion planning; (iii) evaluate FPGA and synthesized ASIC implementations of this accelerator for an industrial manipulator robot; and (iv) describe how the design can be automatically customized for other robot models. Our FPGA accelerator achieves speedups of 8× and 86× over CPU and GPU when executing a single dynamics gradient computation. It maintains speedups of 1.9× to 2.9× over CPU and GPU, including computation and I/O round-trip latency, when deployed as a coprocessor to a host CPU for processing multiple dynamics gradient computations. ASIC synthesis indicates an additional 7.2× speedup for single computation latency. We describe how this principled approach generalizes to more complex robot platforms, such as quadrupeds and humanoids, as well as to other computational kernels in robotics, outlining a path forward for future robomorphic computing accelerators.", "doi": "10.1145/3445814.3446746", "arxiv_id": "https://doi.org/10.1145/3445814.3446746", "pmid": null, "openalex_id": null, "s2_id": "774a46436ed19e716c716a7026c0d7640c26ff67", "cited_by": 56, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446746", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446746"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446746", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "What Scalable Programs Need from Transactional Memory", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Donald Nguyen", "Keshav Pingali"], "abstract": "Transactional memory (TM) has been the focus of numerous studies, and it is supported in processors such as the IBM Blue Gene/Q and Intel Haswell. Many studies have used the STAMP benchmark suite to evaluate their designs. However, the speedups obtained for the STAMP benchmarks on all TM systems we know of are quite limited; for example, with 64 threads on the IBM Blue Gene/Q, we observe a median speedup of 1.4X using the Blue Gene/Q hardware transactional memory (HTM), and a median speedup of 4.1X using a software transactional memory (STM).", "doi": "10.1145/3037697.3037750", "arxiv_id": "https://doi.org/10.1145/3037697.3037750", "pmid": null, "openalex_id": null, "s2_id": "77866d8b193fdc69917e5afc6542d9e31ce8f145", "cited_by": 14, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037750&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037750"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037750", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Statistical Reconstruction of Class Hierarchies in Binaries", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Omer Katz", "Noam Rinetzky", "Eran Yahav"], "abstract": "We address a fundamental problem in reverse engineering of object-oriented code: the reconstruction of a program's class hierarchy from its stripped binary. Existing approaches rely heavily on structural information that is not always available, e.g., calls to parent constructors. As a result, these approaches often leave gaps in the hierarchies they construct, or fail to construct them altogether. Our main insight is that behavioral information can be used to infer subclass/superclass relations, supplementing any missing structural information. Thus, we propose the first statistical approach for static reconstruction of class hierarchies based on behavioral similarity. We capture the behavior of each type using a statistical language model (SLM), define a metric for pairwise similarity between types based on the Kullback-Leibler divergence between their SLMs, and lift it to determine the most likely class hierarchy. We implemented our approach in a tool called ROCK and used it to automatically reconstruct the class hierarchies of several real-world stripped C++ binaries. Our results demonstrate that ROCK obtained significantly more accurate class hierarchies than those obtained using structural analysis alone.", "doi": "10.1145/3173162.3173202", "arxiv_id": "https://doi.org/10.1145/3173162.3173202", "pmid": null, "openalex_id": null, "s2_id": "782738d16efb1100529b8ccdb6333adb6fba2200", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173202"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173202", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Effective Concurrency Testing for Distributed Systems", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xinhao Yuan", "Junfeng Yang"], "abstract": "Despite their wide deployment, distributed systems remain notoriously hard to reason about. Unexpected interleavings of concurrent operations and failures may lead to undefined behaviors and cause serious consequences. We present Morpheus, the first concurrency testing tool leveraging partial order sampling, a randomized testing method formally analyzed and empirically validated to provide strong probabilistic guarantees of error-detection, for real-world distributed systems. Morpheus introduces conflict analysis to further improve randomized testing by predicting and focusing on operations that affect the testing result. Inspired by the recent shift in building distributed systems using higher-level languages and frameworks, Morpheus targets Erlang. Evaluation on four popular distributed systems in Erlang including RabbitMQ, a message broker service, and Mnesia, a distributed database in the Erlang standard libraries, shows that Morpheus is effective: It found previously unknown errors in every system checked, 11 total, all of which are flaws in their core protocols that may cause deadlocks, unexpected crashes, or inconsistent states.", "doi": "10.1145/3373376.3378484", "arxiv_id": "https://doi.org/10.1145/3373376.3378484", "pmid": null, "openalex_id": null, "s2_id": "78da14aca91746005771b880b1777a07692016ea", "cited_by": 41, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378484", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378484"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378484", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Judging a type by its pointer: optimizing GPU virtual functions", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mengchi Zhang", "Ahmad Alawneh", "Timothy G. Rogers"], "abstract": "Programmable accelerators aim to provide the flexibility of traditional CPUs with significantly improved performance. A well-known impediment to the widespread adoption of programmable accelerators, like GPUs, is the software engineering overhead involved in porting the code. Existing support for C++ on GPUs allows programmers to port polymorphic code with little effort. However, the overhead from the virtual functions introduced by polymorphic code has not been well studied or mitigated on GPUs.", "doi": "10.1145/3445814.3446734", "arxiv_id": "https://doi.org/10.1145/3445814.3446734", "pmid": null, "openalex_id": null, "s2_id": "7924e9d8654bb8bc6f621032260e57b52c103641", "cited_by": 3, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446734", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446734"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446734", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "BYOC: A \"Bring Your Own Core\" Framework for Heterogeneous-ISA Research", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jonathan Balkind", "Katie Lim", "Michael Schaffner", "Fei Gao", "Grigory Chirkov", "Ang Li", "Alexey Lavrov", "Tri M. Nguyen", "Yaosheng Fu", "Florian Zaruba", "Kunal Gulati", "Luca Benini", "David Wentzlaff"], "abstract": "Heterogeneous architectures and heterogeneous-ISA designs are growing areas of computer architecture and system software research. Unfortunately, this line of research is significantly hindered by the lack of experimental systems and modifiable hardware frameworks. This work proposes BYOC, a \"Bring Your Own Core\" framework that is specifically designed to enable heterogeneous-ISA and heterogeneous system research. BYOC is an open-source hardware framework that provides a scalable cache coherence system, that includes out-of-the-box support for four different ISAs (RISC-V 32-bit, RISC-V 64-bit, x86, and SPARCv9) and has been connected to ten different cores. The framework also supports multiple loosely coupled accelerators and is a fully working system supporting SMP Linux. The Transaction-Response Interface (TRI) introduced with BYOC has been specifically designed to make it easy to add in new cores with new ISAs and memory interfaces. This work demonstrates multiple multi-ISA designs running on FPGA and characterises the communication costs. This work describes many of the architectural design trade-offs for building such a flexible system. BYOC is well suited to be the premiere platform for heterogeneous-ISA architecture, system software, and compiler research.", "doi": "10.1145/3373376.3378479", "arxiv_id": "https://doi.org/10.1145/3373376.3378479", "pmid": null, "openalex_id": null, "s2_id": "79cac86d0bbf787bd72479c8098af8d9b2b32e75", "cited_by": 43, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378479", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378479"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378479", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hari Cherupalli", "Henry Duwe", "Weidong Ye", "Rakesh Kumar", "John Sartori"], "abstract": "Many emerging applications such as IoT, wearables, implantables, and sensor networks are power- and energy-constrained. These applications rely on ultra-low-power processors that have rapidly become the most abundant type of processor manufactured today. In the ultra-low-power embedded systems used by these applications, peak power and energy requirements are the primary factors that determine critical system characteristics, such as size, weight, cost, and lifetime. While the power and energy requirements of these systems tend to be application-specific, conventional techniques for rating peak power and energy cannot accurately bound the power and energy requirements of an application running on a processor, leading to over-provisioning that increases system size and weight. In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak power and energy requirements. Our technique provides more accurate, tighter bounds than conventional techniques for determining peak power and energy requirements, reporting 15% lower peak power and 17% lower peak energy, on average, than a conventional approach based on profiling and guardbanding. Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average. Also, unlike conventional approaches, our technique reports guaranteed bounds on peak power and energy independent of an application's input set. Tighter bounds on peak power and energy can be exploited to reduce system size, weight, and cost.", "doi": "10.1145/3037697.3037711", "arxiv_id": "https://doi.org/10.1145/3037697.3037711", "pmid": null, "openalex_id": null, "s2_id": "7a25330b99d5264c87bbd3d220ca19bae5ff4445", "cited_by": 18, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037711&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037711"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037711", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SAC: A Co-Design Cache Algorithm for Emerging SMR-based High-Density Disks", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Diansen Sun", "Yunpeng Chai"], "abstract": "To satisfy the huge storage capacity requirements of big data, the emerging high-density disks gradually adopt the Shingled Magnetic Recording (SMR) technique. However, the most serious challenge of SMR disks lies in their weak fine-grained random write performance caused by the write amplification inner SMRs and its extremely unbalanced read and write latencies. Although fast storage devices like Flash-based SSDscan be used to boost SMR disks in SMR-based hybrid storage, the optimization targets of existing cache algorithms (e.g., higher popularity for LRU, lower SMR write amplification ratio for MOST) are NOT the crucial factor for the performance of the SMR-based hybrid storage. In this paper, we propose a new SMR-Aware Co-design cache algorithm called SAC to accelerate the SMR-based hybrid storage. SAC adopts a hardware/software co-design method to fit the characteristics of SMR disks and to optimize the crucial factor, i.e., RMW operations inner SMR disks, effectively. Furthermore, SAC also makes a good balance between some conflicting factors, e.g., the data popularity vs. the SMR write amplification and clean cache space vs. dirty cache space. In our evaluations under real-world traces, SAC achieves a 7.5× performance speedup compared with LRU in the write-only mode, and a 2.9× speedup in the read-write mixed mode.", "doi": "10.1145/3373376.3378474", "arxiv_id": "https://doi.org/10.1145/3373376.3378474", "pmid": null, "openalex_id": null, "s2_id": "7c2c7d9a821a0d5b8a351ef2dcbae8393dbb7a71", "cited_by": 14, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378474"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378474", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SwapAdvisor: Pushing Deep Learning Beyond the GPU Memory Limit via Smart Swapping", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chien-Chin Huang", "Gu Jin", "Jinyang Li"], "abstract": "It is known that deeper and wider neural networks can achieve better accuracy. But it is difficult to continue the trend to increase model size due to limited GPU memory. One promising solution is to support swapping between GPU and CPU memory. However, existing work on swapping only handle certain models and do not achieve satisfactory performance. Deep learning computation is commonly expressed as a dataflow graph which can be analyzed to improve swapping. We propose SwapAdvisor, which performs joint optimization along 3 dimensions based on a given dataflow graph: operator scheduling, memory allocation, and swap decisions. SwapAdvisor explores the vast search space using a custom-designed genetic algorithm. Evaluations using a variety of large models show that SwapAdvisor can train models up to 12 times the GPU memory limit while achieving 53-99% of the throughput of a hypothetical baseline with infinite GPU memory.", "doi": "10.1145/3373376.3378530", "arxiv_id": "https://doi.org/10.1145/3373376.3378530", "pmid": null, "openalex_id": null, "s2_id": "7cb7b80e50fd5418b7f47326e60ce32c9a0f6b38", "cited_by": 238, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378530", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378530"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378530", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Compress Objects, Not Cache Lines: An Object-Based Compressed Memory Hierarchy", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Po-An Tsai", "Daniel Sánchez"], "abstract": "Existing cache and main memory compression techniques compress data in small fixed-size blocks, typically cache lines. Moreover, they use simple compression algorithms that focus on exploiting redundancy within a block. These techniques work well for scientific programs that are dominated by arrays. However, they are ineffective on object-based programs because objects do not fall neatly into fixed-size blocks and have a more irregular layout. We present the first compressed memory hierarchy designed for object-based applications. We observe that (i) objects, not cache lines, are the natural unit of compression for these programs, as they traverse and operate on object pointers; and (ii) though redundancy within each object is limited, redundancy across objects of the same type is plentiful. We exploit these insights through Zippads, an object-based compressed memory hierarchy, and COCO, a cross-object-compression algorithm. Building on a recent object-based memory hierarchy, Zippads transparently compresses variable-sized objects and stores them compactly. As a result, Zippads consistently outperforms a state-of-the-art compressed memory hierarchy: on a mix of array- and object-dominated workloads, Zippads achieves 1.63x higher compression ratio and improves performance by 17%.", "doi": "10.1145/3297858.3304006", "arxiv_id": "https://doi.org/10.1145/3297858.3304006", "pmid": null, "openalex_id": null, "s2_id": "7f6bb7771763eca9ff3176a80c1f7bdee570290a", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304006", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304006"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304006", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fine-Grain Checkpointing with In-Cache-Line Logging", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Nachshon Cohen", "David T. Aksun", "Hillel Avni", "James R. Larus"], "abstract": "Non-Volatile Memory offers the possibility of implementing high-performance, durable data structures. However, achieving performance comparable to well-designed data structures in non-persistent (transient) memory is difficult, primarily because of the cost of ensuring the order in which memory writes reach NVM.\\@ Often, this requires flushing data to NVM and waiting a full memory round-trip time. In this paper, we introduce two new techniques: Fine-Grained Checkpointing, which ensures a consistent, quickly recoverable data structure in NVM after a system failure, and In-Cache-Line Logging, an undo-logging technique that enables recovery of earlier state without requiring cache-line flushes in the normal case. We implemented these techniques in the Masstree data structure, making it persistent and demonstrating the ease of applying them to a highly optimized system and their low (5.9-15.4%) runtime overhead cost.", "doi": "10.1145/3297858.3304046", "arxiv_id": "1902.00660", "pmid": null, "openalex_id": null, "s2_id": "7f704a58c598a44378649ef1db0b83afde200ec7", "cited_by": 39, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304046", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304046"], "github": ["https://github.com/epfl-vlsc/Incll"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304046", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Batch-Aware Unified Memory Management in GPUs for Irregular Workloads", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hyojong Kim", "Jaewoong Sim", "Prasun Gera", "Ramyad Hadidi", "Hyesoon Kim"], "abstract": "While unified virtual memory and demand paging in modern GPUs provide convenient abstractions to programmers for working with large-scale applications, they come at a significant performance cost. We provide the first comprehensive analysis of major inefficiencies that arise in page fault handling mechanisms employed in modern GPUs. To amortize the high costs in fault handling, the GPU runtime processes a large number of GPU page faults together. We observe that this batched processing of page faults introduces large-scale serialization that greatly hurts the GPU's execution throughput. We show real machine measurements that corroborate our findings. Our goal is to mitigate these inefficiencies and enable efficient demand paging for GPUs. To this end, we propose a GPU runtime software and hardware solution that (1) increases the batch size (i.e., the number of page faults handled together), thereby amortizing the øverheadName time, and reduces the number of batches by supporting CPU-like thread block context switching, and (2) takes page eviction off the critical path with no hardware changes by overlapping evictions with CPU-to-GPU page migrations. Our evaluation demonstrates that the proposed solution provides an average speedup of 2x over the state-of-the-art page prefetching. We show that our solution increases the batch size by 2.27x and reduces the total number of batches by 51% on average. We also show that the average batch processing time is reduced by 27%.", "doi": "10.1145/3373376.3378529", "arxiv_id": "https://doi.org/10.1145/3373376.3378529", "pmid": null, "openalex_id": null, "s2_id": "7fc5acf327fffe54db99119355e06c8461b7e791", "cited_by": 96, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378529"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378529", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Kard: lightweight data race detection with per-thread memory protection", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Adil Ahmad", "Sangho Lee", "Pedro Fonseca", "Byoungyoung Lee"], "abstract": "Finding data race bugs in multi-threaded programs has proven challenging. A promising direction is to use dynamic detectors that monitor the program’s execution for data races. However, despite extensive work on dynamic data race detection, most proposed systems for commodity hardware incur prohibitive overheads due to expensive compiler instrumentation of memory accesses; hence, they are not efficient enough to be used in all development and testing settings.", "doi": "10.1145/3445814.3446727", "arxiv_id": "https://doi.org/10.1145/3445814.3446727", "pmid": null, "openalex_id": null, "s2_id": "7fdf5539a75668175cfda3c3d93447232edd2433", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446727"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446727", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Taurus: A Holistic Language Runtime System for Coordinating Distributed Managed-Language Applications", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Martin Maas", "Krste Asanovic", "Tim Harris", "John Kubiatowicz"], "abstract": "Many distributed workloads in today's data centers are written in managed languages such as Java or Ruby. Examples include big data frameworks such as Hadoop, data stores such as Cassandra or applications such as the SOLR search engine. These workloads typically run across many independent language runtime systems on different nodes. This setup represents a source of inefficiency, as these language runtime systems are unaware of each other. For example, they may perform Garbage Collection at times that are locally reasonable but not in a distributed setting.", "doi": "10.1145/2872362.2872386", "arxiv_id": "https://doi.org/10.1145/2872362.2872386", "pmid": null, "openalex_id": null, "s2_id": "7ffa58ea84b5811793311f0d639c71b9f6601ef6", "cited_by": 69, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2980024.2872386?download=true", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872386"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872386", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "The Architectural Implications of Autonomous Driving: Constraints and Acceleration", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shih-Chieh Lin", "Yunqi Zhang", "Chang-Hong Hsu", "Matt Skach", "Md. Enamul Haque", "Lingjia Tang", "Jason Mars"], "abstract": "Autonomous driving systems have attracted a significant amount of interest recently, and many industry leaders, such as Google, Uber, Tesla, and Mobileye, have invested a large amount of capital and engineering power on developing such systems. Building autonomous driving systems is particularly challenging due to stringent performance requirements in terms of both making the safe operational decisions and finishing processing at real-time. Despite the recent advancements in technology, such systems are still largely under experimentation and architecting end-to-end autonomous driving systems remains an open research question. To investigate this question, we first present and formalize the design constraints for building an autonomous driving system in terms of performance, predictability, storage, thermal and power. We then build an end-to-end autonomous driving system using state-of-the-art award-winning algorithms to understand the design trade-offs for building such systems. In our real-system characterization, we identify three computational bottlenecks, which conventional multicore CPUs are incapable of processing under the identified design constraints. To meet these constraints, we accelerate these algorithms using three accelerator platforms including GPUs, FPGAs, and ASICs, which can reduce the tail latency of the system by 169x, 10x, and 93x respectively. With accelerator-based designs, we are able to build an end-to-end autonomous driving system that meets all the design constraints, and explore the trade-offs among performance, power and the higher accuracy enabled by higher resolution cameras.", "doi": "10.1145/3173162.3173191", "arxiv_id": "https://doi.org/10.1145/3173162.3173191", "pmid": null, "openalex_id": null, "s2_id": "801aed0fcb0485ce262a99be06c6ef96a161a663", "cited_by": 503, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173191", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173191"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173191", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Keynote Address II", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252398", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "80295c6adb86cc3acf8c4060459ec892bb49f196", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Sinan: ML-based and QoS-aware resource management for cloud microservices", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yanqi Zhang", "Weizhe Hua", "Zhuangzhuang Zhou", "G. Edward Suh", "Christina Delimitrou"], "abstract": "Cloud applications are increasingly shifting from large monolithic services, to large numbers of loosely-coupled, specialized microservices. Despite their advantages in terms of facilitating development, deployment, modularity, and isolation, microservices complicate resource management, as dependencies between them introduce backpressure effects and cascading QoS violations.", "doi": "10.1145/3445814.3446693", "arxiv_id": "https://doi.org/10.1145/3445814.3446693", "pmid": null, "openalex_id": null, "s2_id": "8038a746a821d123073a36fdf6d7a79389fe75ec", "cited_by": 280, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446693"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446693", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Classifying Memory Access Patterns for Prefetching", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Grant Ayers", "Heiner Litz", "Christos Kozyrakis", "Parthasarathy Ranganathan"], "abstract": "Prefetching is a well-studied technique for addressing the memory access stall time of contemporary microprocessors. However, despite a large body of related work, the memory access behavior of applications is not well understood, and it remains difficult to predict whether a particular application will benefit from a given prefetcher technique. In this work we propose a novel methodology to classify the memory access patterns of applications, enabling well-informed reasoning about the applicability of a certain prefetcher. Our approach leverages instruction dataflow information to uncover a wide range of access patterns, including arbitrary combinations of offsets and indirection. These combinations or prefetch kernels represent reuse, strides, reference locality, and complex address generation. By determining the complexity and frequency of these access patterns, we enable reasoning about prefetcher timeliness and criticality, exposing the limitations of existing prefetchers today. Moreover, using these kernels, we are able to compute the next address for the majority of top-missing instructions, and we propose a software prefetch injection methodology that is able to outperform state-of-the-art hardware prefetchers.", "doi": "10.1145/3373376.3378498", "arxiv_id": "https://doi.org/10.1145/3373376.3378498", "pmid": null, "openalex_id": null, "s2_id": "804f23ac1a4a56b8dc5bb7201dab7b8cece76a70", "cited_by": 90, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.1145/3373376.3378498", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378498"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378498", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Towards Practical Default-On Multi-Core Record/Replay", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ali José Mashtizadeh", "Tal Garfinkel", "David Terei", "David Mazières", "Mendel Rosenblum"], "abstract": "We present Castor, a record/replay system for multi-core applications that provides consistently low and predictable overheads. With Castor, developers can leave record and replay on by default, making it practical to record and reproduce production bugs, or employ fault tolerance to recover from hardware failures.", "doi": "10.1145/3037697.3037751", "arxiv_id": "https://doi.org/10.1145/3037697.3037751", "pmid": null, "openalex_id": null, "s2_id": "808307ae1850f262ae3f5ad41ecd8385bedf00c2", "cited_by": 61, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037751&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037751"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037751", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FlatStore: An Efficient Log-Structured Key-Value Storage Engine for Persistent Memory", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Youmin Chen", "Youyou Lu", "Fan Yang", "Qing Wang", "Yang Wang", "Jiwu Shu"], "abstract": "Emerging hardware like persistent memory (PM) and high-speed NICs are promising to build efficient key-value stores. However, we observe that the small-sized access pattern in key-value stores doesn't match with the persistence granularity in PMs, leaving the PM bandwidth underutilized. This paper proposes an efficient PM-based key-value storage engine named FlatStore. Specifically, it decouples the role of a KV store into a persistent log structure for efficient storage and a volatile index for fast indexing. Upon it, FlatStore further incorporates two techniques: 1) compacted log format to maximize the batching opportunity in the log; 2) pipelined horizontal batching to steal log entries from other cores when creating a batch, thus delivering low-latency and high-throughput performance. We implement FlatStore with the volatile index of both a hash table and Masstree. We deploy FlatStore on Optane DC Persistent Memory, and our experiments show that FlatStore achieves up to 35 Mops/s with a single server node, 2.5 - 6.3 times faster than existing systems.", "doi": "10.1145/3373376.3378515", "arxiv_id": "https://doi.org/10.1145/3373376.3378515", "pmid": null, "openalex_id": null, "s2_id": "809d2232c2a3ac831f65eb8da855b6a397682ebf", "cited_by": 186, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378515"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378515", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Unconventional Parallelization of Nondeterministic Applications", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Enrico Armenio Deiana", "Vincent St-Amour", "Peter A. Dinda", "Nikos Hardavellas", "Simone Campanoni"], "abstract": "The demand for thread-level-parallelism (TLP) on commodity processors is endless as it is essential for gaining performance and saving energy. However, TLP in today's programs is limited by dependences that must be satisfied at run time. We have found that for nondeterministic programs, some of these actual dependences can be satisfied with alternative data that can be generated in parallel, thus boosting the program's TLP. Satisfying these dependences with alternative data nonetheless produces final outputs that match those of the original nondeterministic program. To demonstrate the practicality of our technique, we describe the design, implementation, and evaluation of our compilers, autotuner, profiler, and runtime, which are enabled by our proposed C++ programming language extensions. The resulting system boosts the performance of six well-known nondeterministic and multi-threaded benchmarks by 158.2% (geometric mean) on a 28-core Intel-based platform.", "doi": "10.1145/3173162.3173181", "arxiv_id": "https://doi.org/10.1145/3173162.3173181", "pmid": null, "openalex_id": null, "s2_id": "80d44c1d3b0d208e1d61adc9d49ec8db9d4f1516", "cited_by": 15, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173181", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173181"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173181", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Browsix: Bridging the Gap Between Unix and the Browser", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bobby Powers", "John Vilk", "Emery D. Berger"], "abstract": "  Applications written to run on conventional operating systems typically\ndepend on OS abstractions like processes, pipes, signals, sockets, and a shared\nfile system. Porting these applications to the web currently requires extensive\nrewriting or hosting significant portions of code server-side because browsers\npresent a nontraditional runtime environment that lacks OS functionality.\n  This paper presents Browsix, a framework that bridges the considerable gap\nbetween conventional operating systems and the browser, enabling unmodified\nprograms expecting a Unix-like environment to run directly in the browser.\nBrowsix comprises two core parts: (1) a JavaScript-only system that makes core\nUnix features (including pipes, concurrent processes, signals, sockets, and a\nshared file system) available to web applications; and (2) extended JavaScript\nruntimes for C, C++, Go, and Node.js that support running programs written in\nthese languages as processes in the browser. Browsix supports running a POSIX\nshell, making it straightforward to connect applications together via pipes.\n  We illustrate Browsix's capabilities via case studies that demonstrate how it\neases porting legacy applications to the browser and enables new functionality.\nWe demonstrate a Browsix-enabled LaTeX editor that operates by executing\nunmodified versions of pdfLaTeX and BibTeX. This browser-only LaTeX editor can\nrender documents in seconds, making it fast enough to be practical. We further\ndemonstrate how Browsix lets us port a client-server application to run\nentirely in the browser for disconnected operation. Creating these applications\nrequired less than 50 lines of glue code and no code modifications,\ndemonstrating how easily Browsix can be used to build sophisticated web\napplications from existing parts without modification.\n", "doi": "10.1145/3037697.3037727", "arxiv_id": "1611.07862", "pmid": null, "openalex_id": null, "s2_id": "8301faa48336978a7ea20b3471115334bdbfc021", "cited_by": 20, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/1611.07862", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037727"], "github": [], "sources": ["semanticscholar", "papervault", "open-arxiv"], "landing": "https://doi.org/10.1145/3037697.3037727", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems", "journal_ref": "ASPLOS 2017", "categories": "cs.OS cs.PL"}
{"title": "NeuroEngine: a hardware-based event-driven simulation system for advanced brain-inspired computing", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hunjun Lee", "Chanmyeong Kim", "Yujin Chung", "Jangwoo Kim"], "abstract": "Brain-inspired computing aims to understand the cognitive mechanisms of a brain and apply them to advance various areas in computer science. Deep learning is an example to greatly improve the field of pattern recognition and classification by utilizing an artificial neural network (ANN). To exploit advanced mechanisms of a brain and thus make more great advances, researchers need a methodology that can simulate neural networks with higher computational capabilities such as advanced spiking neural networks (SNNs) with two-stage neurons and synaptic delays. However, existing SNN simulation methodologies are too slow and energy-inefficient due to their software-based simulation or hardware-based but time-driven execution mechanisms. In this paper, we present NeuroEngine, a fast and energy-efficient hardware-based system to efficiently simulate advanced SNNs. The key idea is to design an accelerator to enable event-driven simulations of the SNNs at a minimum cost. NeuroEngine achieves high speed and energy efficiency by carefully architecting its datapath and memory units to take the best advantage of the event-driven mechanism while satisfying all the important requirements to simulate our target SNNs. For high performance and energy efficiency, NeuroEngine applies a simpler datapath, multi-queue scheduler, and lazy update to minimize its neuron computation and event scheduling overhead. Then, we build an end-to-end simulation system by implementing a programming interface and a compilation toolchain for NeuroEngine hardware. Our evaluations show that NeuroEngine greatly improves the harmonic mean performance and energy efficiency by 4.30× and 2.60×, respectively, over the state-of-the-art time-driven simulator.", "doi": "10.1145/3445814.3446738", "arxiv_id": "https://doi.org/10.1145/3445814.3446738", "pmid": null, "openalex_id": null, "s2_id": "830de2df888465ac9758c1b7476bd319ea71cb89", "cited_by": 18, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446738"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446738", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shuwen Deng", "Wenjie Xiong", "Jakub Szefer"], "abstract": "Based on improvements to an existing three-step model for cache timing-based attacks, this work presents 88 Strong types of theoretical timing-based vulnerabilities in processor caches. It also presents and implements a new benchmark suite that can be used to test if processor cache is vulnerable to one of the attacks. In total, there are 1094 automatically-generated test programs which cover the 88 Strong theoretical vulnerabilities. The benchmark suite generates the Cache Timing Vulnerability Score (CTVS) which can be used to evaluate how vulnerable a specific cache implementation is to different attacks. A smaller CTVS means the design is more secure. Evaluation is conducted on commodity Intel and AMD processors and shows how the differences in processor implementations can result in different types of attacks that they are vulnerable to. Further, the benchmarks and the CTVS can be used in simulation to help designers of new secure processors and caches evaluate their designs' susceptibility to cache timing-based attacks.", "doi": "10.1145/3373376.3378510", "arxiv_id": "1911.08619", "pmid": null, "openalex_id": null, "s2_id": "8483c7126844ad209c24a1c7220cbf7e541950d9", "cited_by": 24, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378510", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378510"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378510", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "LightStore: Software-defined Network-attached Key-value Drives", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chanwoo Chung", "Jinhyung Koo", "Junsu Im", "Arvind", "Sungjin Lee"], "abstract": "We propose LightStore, a key-value flash store, as a substitute for x86-based storage servers. A LightStore node has a low-power embedded-class processor, a few gigabytes of DRAM and a few terabytes of NAND flash, and can be directly connected to a network port in a datacenter. A large-scale distributed storage cluster can be formed simply by adding more LightStore nodes to the network. Applications in a datacenter can take multiple software-defined views of LightStore stores via thin LightStore adapter layers, which translate conventional KV, YCSB, block, and file accesses to KV ones for LightStore. LightStore is estimated to be 2.0x power-efficient and 2.3x space-efficient than an x86-based all-flash array system of the same capacity. Experimental results on our LightStore prototype show that 1) the LightStore node performance is comparable to an x86 server with a single SSD; 2) a four-node LightStore cluster exhibits up to 7.4x better ops/J than an x86 server with four SSDs.", "doi": "10.1145/3297858.3304022", "arxiv_id": "https://doi.org/10.1145/3297858.3304022", "pmid": null, "openalex_id": null, "s2_id": "84c65ca8edf20f241144b70b8d3aa8d5c7d225e2", "cited_by": 34, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304022", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304022"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304022", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Verification of a practical hardware security architecture", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": null, "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "86738048419308793e8763abb75af5cc387ea77c", "cited_by": 1, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CloudSeer: Workflow Monitoring of Cloud Infrastructures via Interleaved Logs", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiao Yu", "Pallavi Joshi", "Jianwu Xu", "Guoliang Jin", "Hui Zhang", "Guofei Jiang"], "abstract": "Cloud infrastructures provide a rich set of management tasks that operate computing, storage, and networking resources in the cloud. Monitoring the executions of these tasks is crucial for cloud providers to promptly find and understand problems that compromise cloud availability. However, such monitoring is challenging because there are multiple distributed service components involved in the executions. CloudSeer enables effective workflow monitoring. It takes a lightweight non-intrusive approach that purely works on interleaved logs widely existing in cloud infrastructures. CloudSeer first builds an automaton for the workflow of each management task based on normal executions, and then it checks log messages against a set of automata for workflow divergences in a streaming manner. Divergences found during the checking process indicate potential execution problems, which may or may not be accompanied by error log messages. For each potential problem, CloudSeer outputs necessary context information including the affected task automaton and related log messages hinting where the problem occurs to help further diagnosis. Our experiments on OpenStack, a popular open-source cloud infrastructure, show that CloudSeer's efficiency and problem-detection capability are suitable for online monitoring.", "doi": "10.1145/2872362.2872407", "arxiv_id": "https://doi.org/10.1145/2872362.2872407", "pmid": null, "openalex_id": null, "s2_id": "8681fa540b786a1858a3d429c0fbcaf3aeeb52ee", "cited_by": 147, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872407"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872407", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amirali Boroumand", "Saugata Ghose", "Youngsok Kim", "Rachata Ausavarungnirun", "Eric Shiu", "Rahul Thakur", "Daehyun Kim", "Aki Kuusela", "Allan Knies", "Parthasarathy Ranganathan", "Onur Mutlu"], "abstract": "We are experiencing an explosive growth in the number of consumer devices, including smartphones, tablets, web-based computers such as Chromebooks, and wearable devices. For this class of devices, energy efficiency is a first-class concern due to the limited battery capacity and thermal power budget. We find that data movement is a major contributor to the total system energy and execution time in consumer devices. The energy and performance costs of moving data between the memory system and the compute units are significantly higher than the costs of computation. As a result, addressing data movement is crucial for consumer devices. In this work, we comprehensively analyze the energy and performance impact of data movement for several widely-used Google consumer workloads: (1) the Chrome web browser; (2) TensorFlow Mobile, Google's machine learning framework; (3) video playback, and (4) video capture, both of which are used in many video services such as YouTube and Google Hangouts. We find that processing-in-memory (PIM) can significantly reduce data movement for all of these workloads, by performing part of the computation close to memory. Each workload contains simple primitives and functions that contribute to a significant amount of the overall data movement. We investigate whether these primitives and functions are feasible to implement using PIM, given the limited area and power constraints of consumer devices. Our analysis shows that offloading these primitives to PIM logic, consisting of either simple cores or specialized accelerators, eliminates a large amount of data movement, and significantly reduces total system energy (by an average of 55.4% across the workloads) and execution time (by an average of 54.2%).", "doi": "10.1145/3173162.3173177", "arxiv_id": "https://doi.org/10.1145/3173162.3173177", "pmid": null, "openalex_id": null, "s2_id": "869ffc81aad12cc59e87ed658ea6489849543fad", "cited_by": 385, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173177"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173177", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Cross-Failure Bug Detection in Persistent Memory Programs", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sihang Liu", "Korakit Seemakhupt", "Yizhou Wei", "Thomas F. Wenisch", "Aasheesh Kolli", "Samira Manabi Khan"], "abstract": "Persistent memory (PM) technologies, such as Intel's Optane memory, deliver high performance, byte-addressability, and persistence, allowing programs to directly manipulate persistent data in memory without any OS intermediaries. An important requirement of these programs is that persistent data must remain consistent across a failure, which we refer to as the crash consistency guarantee. However, maintaining crash consistency is not trivial. We identify that a consistent recovery critically depends not only on the execution before the failure, but also on the recovery and resumption after failure. We refer to these stages as the pre- and post-failure execution stages. In order to holistically detect crash consistency bugs, we categorize the underlying causes behind inconsistent recovery due to incorrect interactions between the pre- and post-failure execution. First, a program is not crash-consistent if the post-failure stage reads from locations that are not guaranteed to be persisted in all possible access interleavings during the pre-failure stage -- a type of programming error that leads to a race that we refer to as a cross-failure race. Second, a program is not crash-consistent if the post-failure stage reads persistent data that has been left semantically inconsistent during the pre-failure stage, such as a stale log or uncommitted data. We refer to this type of bugs as a cross-failure semantic bug. Together, they form the cross-failure bugs in PM programs. In this work, we provide XFDetector, a tool that detects cross-failure bugs by automatically injecting failures into the pre-failure execution, and checking for cross-failure races and semantic bugs in the post-failure continuation. XFDetector has detected four new bugs in three pieces of PM software: one of PMDK's examples, a PM-optimized Redis database, and a PMDK library function.", "doi": "10.1145/3373376.3378452", "arxiv_id": "https://doi.org/10.1145/3373376.3378452", "pmid": null, "openalex_id": null, "s2_id": "86c52a7d0e2ef8315c72680172c840beceb3d70d", "cited_by": 86, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378452"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378452", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Paravirtual Remote I/O", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yossi Kuperman", "Eyal Moscovici", "Joel Nider", "Razya Ladelsky", "Abel Gordon", "Dan Tsafrir"], "abstract": "The traditional \"trap and emulate\" I/O paravirtualization model conveniently allows for I/O interposition, yet it inherently incurs costly guest-host context switches. The newer \"sidecore\" model eliminates this overhead by dedicating host (side)cores to poll the relevant guest memory regions and react accordingly without context switching. But the dedication of sidecores on each host might be wasteful when I/O activity is low, or it might not provide enough computational power when I/O activity is high. We propose to alleviate this problem at rack scale by consolidating the dedicated sidecores spread across several hosts onto one server. The hypervisor is then effectively split into two parts: the local hypervisor that hosts the VMs, and the remote hypervisor that processes their paravirtual I/O. We call this model vRIO---paraVirtual Remote I/O. We find that by increasing the latency somewhat, it provides comparable throughput with fewer sidecores and superior throughput with the same number of sidecores as compared to the state of the art. vRIO additionally constitutes a new, cost-effective way to consolidate I/O devices (on the remote hypervisor) while supporting efficient programmable I/O interposition.", "doi": "10.1145/2872362.2872378", "arxiv_id": "https://doi.org/10.1145/2872362.2872378", "pmid": null, "openalex_id": null, "s2_id": "87064d58ef49df1b47c4ac74258fda1aecab2b68", "cited_by": 44, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872378"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872378", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "GPUReplay: a 50-KB GPU stack for client ML", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507754", "arxiv_id": "2105.05085", "pmid": null, "openalex_id": null, "s2_id": "871be4fa6d5fb36ffcf72de0a4b725eaab071091", "cited_by": 13, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3503222.3507754"], "github": ["https://github.com/bakhi/gpureplay"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Andrew Ferraiuolo", "Rui Xu", "Danfeng Zhang", "Andrew C. Myers", "G. Edward Suh"], "abstract": "Hardware-based mechanisms for software isolation are becoming increasingly popular, but implementing these mechanisms correctly has proved difficult, undermining the root of security. This work introduces an effective way to formally verify important properties of such hardware security mechanisms. In our approach, hardware is developed using a lightweight security-typed hardware description language (HDL) that performs static information flow analysis. We show the practicality of our approach by implementing and verifying a simplified but realistic multi-core prototype of the ARM TrustZone architecture. To make the security-typed HDL expressive enough to verify a realistic processor, we develop new type system features. Our experiments suggest that information flow analysis is efficient, and programmer effort is modest. We also show that information flow constraints are an effective way to detect hardware vulnerabilities, including several found in commercial processors.", "doi": "10.1145/3037697.3037739", "arxiv_id": "https://doi.org/10.1145/3037697.3037739", "pmid": null, "openalex_id": null, "s2_id": "8862841f91bea97d39872eb2aa954bd6e6b570da", "cited_by": 78, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037739&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037739"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037739", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Intelligence Beyond the Edge: Inference on Intermittent Embedded Systems", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Graham Gobieski", "Brandon Lucia", "Nathan Beckmann"], "abstract": "Energy-harvesting technology provides a promising platform for future IoT applications. However, since communication is very expensive in these devices, applications will require inference \"beyond the edge\" to avoid wasting precious energy on pointless communication. We show that application performance is highly sensitive to inference accuracy. Unfortunately, accurate inference requires large amounts of computation and memory, and energy-harvesting systems are severely resource-constrained. Moreover, energy-harvesting systems operate intermittently, suffering frequent power failures that corrupt results and impede forward progress. This paper overcomes these challenges to present the first full-scale demonstration of DNN inference on an energy-harvesting system. We design and implement SONIC, an intermittence-aware software system with specialized support for DNN inference. SONIC introduces loop continuation, a new technique that dramatically reduces the cost of guaranteeing correct intermittent execution for loop-heavy code like DNN inference. To build a complete system, we further present GENESIS, a tool that automatically compresses networks to optimally balance inference accuracy and energy, and TAILS, which exploits SIMD hardware available in some microcontrollers to improve energy efficiency. Both SONIC & TAILS guarantee correct intermittent execution without any hand-tuning or performance loss across different power systems. Across three neural networks on a commercially available microcontroller, SONIC & TAILS reduce inference energy by 6.9× and 12.2×, respectively, over the state-of-the-art.", "doi": "10.1145/3297858.3304011", "arxiv_id": "1810.07751", "pmid": null, "openalex_id": null, "s2_id": "8877a00d3a48840829f5f16bdb1d43d9ac98d599", "cited_by": 241, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304011", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304011"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304011", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 6A: Reliability and Debugging II", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252403", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "887a829a100bfab9b2bbc3049f85a0f0a73c991d", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FA3C: FPGA-Accelerated Deep Reinforcement Learning", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hyungmin Cho", "Pyeongseok Oh", "Jiyoung Park", "Wookeun Jung", "Jaejin Lee"], "abstract": "Deep Reinforcement Learning (Deep RL) is applied to many areas where an agent learns how to interact with the environment to achieve a certain goal, such as video game plays and robot controls. Deep RL exploits a DNN to eliminate the need for handcrafted feature engineering that requires prior domain knowledge. The Asynchronous Advantage Actor-Critic (A3C) is one of the state-of-the-art Deep RL methods. In this paper, we present an FPGA-based A3C Deep RL platform, called FA3C. Traditionally, FPGA-based DNN accelerators have mainly focused on inference only by exploiting fixed-point arithmetic. Our platform targets both inference and training using single-precision floating-point arithmetic. We demonstrate the performance and energy efficiency of FA3C using multiple A3C agents that learn the control policies of six Atari 2600 games. Its performance is better than a high-end GPU-based platform (NVIDIA Tesla P100). FA3C achieves 27.9% better performance than that of a state-of-the-art GPU-based implementation. Moreover, the energy efficiency of FA3C is 1.62x better than that of the GPU-based implementation.", "doi": "10.1145/3297858.3304058", "arxiv_id": "https://doi.org/10.1145/3297858.3304058", "pmid": null, "openalex_id": null, "s2_id": "88c5a5acfead1d98f2c97db5db7d6fc4dd0a6864", "cited_by": 69, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304058&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304058"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304058", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DudeTM: Building Durable Transactions with Decoupling for Persistent Memory", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mengxing Liu", "Mingxing Zhang", "Kang Chen", "Xuehai Qian", "Yongwei Wu", "Weimin Zheng", "Jinglei Ren"], "abstract": "Emerging non-volatile memory (NVM) offers non-volatility, byte-addressability and fast access at the same time. To make the best use of these properties, it has been shown by empirical evidence that programs should access NVM directly through CPU load and store instructions, so that the overhead of a traditional file system or database can be avoided. Thus, durable transactions become a common choice of applications for accessing persistent memory data in a crash consistent manner. However, existing durable transaction systems employ either undo logging, which requires a fence for every memory write, or redo logging, which requires intercepting all memory reads within transactions.", "doi": "10.1145/3037697.3037714", "arxiv_id": "https://doi.org/10.1145/3037697.3037714", "pmid": null, "openalex_id": null, "s2_id": "88cb3e214a7f2268be91298072061f3c8fba3e06", "cited_by": 205, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037714"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037714", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mohammadkazem Taram", "Ashish Venkat", "Dean M. Tullsen"], "abstract": "This paper describes context-sensitive fencing (CSF), a microcode-level defense against multiple variants of Spectre. CSF leverages the ability to dynamically alter the decoding of the instruction stream, to seamlessly inject new micro-ops, including fences, only when dynamic conditions indicate they are needed. This enables the processor to protect against the attack, but with minimal impact on the efficacy of key performance features such as speculative execution. This research also examines several alternative fence implementations, and introduces three new types of fences which allow most dynamic reorderings of loads and stores, but in a way that prevents speculative accesses from changing visible cache state. These optimizations reduce the performance overhead of the defense mechanism, compared to state-of-the-art software-based fencing mechanisms by a factor of six.", "doi": "10.1145/3297858.3304060", "arxiv_id": "https://doi.org/10.1145/3297858.3304060", "pmid": null, "openalex_id": null, "s2_id": "88f788a20e72df98ec0d349246e59e702aef4bfe", "cited_by": 121, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304060", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304060"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304060", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HerQules: securing programs via hardware-enforced message queues", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daming D. Chen", "Wen Shih Lim", "Mohammad Bakhshalipour", "Phillip B. Gibbons", "James C. Hoe", "Bryan Parno"], "abstract": "Many computer programs directly manipulate memory using unsafe pointers, which may introduce memory safety bugs. In response, past work has developed various runtime defenses, including memory safety checks, as well as mitigations like no-execute memory, shadow stacks, and control-flow integrity (CFI), which aim to prevent attackers from obtaining program control. However, software-based designs often need to update in-process runtime metadata to maximize accuracy, which is difficult to do precisely, efficiently, and securely. Hardware-based fine-grained instruction monitoring avoids this problem by maintaining metadata in special-purpose hardware, but suffers from high design complexity and requires significant microarchitectural changes.", "doi": "10.1145/3445814.3446736", "arxiv_id": "https://doi.org/10.1145/3445814.3446736", "pmid": null, "openalex_id": null, "s2_id": "894758be98a4c4b8495182a2de31f0d6d776e792", "cited_by": 5, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446736", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446736"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446736", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "∅sim: Preparing System Software for a World with Terabyte-scale Memories", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mark Mansi", "Michael M. Swift"], "abstract": "Recent advances in memory technologies mean that commodity machines may soon have terabytes of memory; however, such machines remain expensive and uncommon today. Hence, few programmers and researchers can debug and prototype fixes for scalability problems or explore new system behavior caused by terabyte-scale memories.", "doi": "10.1145/3373376.3378451", "arxiv_id": "https://doi.org/10.1145/3373376.3378451", "pmid": null, "openalex_id": null, "s2_id": "8951924ef9108c6440b6473351ed288388868dd8", "cited_by": 12, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378451", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378451"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378451", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Livia: Data-Centric Computing Throughout the Memory Hierarchy", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Elliot Lockerman", "Axel Feldmann", "Mohammad Bakhshalipour", "Alexandru Stanescu", "Shashwat Gupta", "Daniel Sánchez", "Nathan Beckmann"], "abstract": "In order to scale, future systems will need to dramatically reduce data movement. Data movement is expensive in current designs because (i) traditional memory hierarchies force computation to happen unnecessarily far away from data and (ii) processing-in-memory approaches fail to exploit locality.", "doi": "10.1145/3373376.3378497", "arxiv_id": "https://doi.org/10.1145/3373376.3378497", "pmid": null, "openalex_id": null, "s2_id": "89b396c149c206cddb82b23f358cd19d1149e6ba", "cited_by": 76, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378497", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378497"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378497", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PARTIES: QoS-Aware Resource Partitioning for Multiple Interactive Services", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shuang Chen", "Christina Delimitrou", "José F. Martínez"], "abstract": "Multi-tenancy in modern datacenters is currently limited to a single latency-critical, interactive service, running alongside one or more low-priority, best-effort jobs. This limits the efficiency gains from multi-tenancy, especially as an increasing number of cloud applications are shifting from batch jobs to services with strict latency requirements. We present PARTIES, a QoS-aware resource manager that enables an arbitrary number of interactive, latency-critical services to share a physical node without QoS violations. PARTIES leverages a set of hardware and software resource partitioning mechanisms to adjust allocations dynamically at runtime, in a way that meets the QoS requirements of each co-scheduled workload, and maximizes throughput for the machine. We evaluate PARTIES on state-of-the-art server platforms across a set of diverse interactive services. Our results show that PARTIES improves throughput under QoS by 61% on average, compared to existing resource managers, and that the rate of improvement increases with the number of co-scheduled applications per physical host.", "doi": "10.1145/3297858.3304005", "arxiv_id": "https://doi.org/10.1145/3297858.3304005", "pmid": null, "openalex_id": null, "s2_id": "89d8a0ed7f133de2f3f643ee459c32c4fb8dfdca", "cited_by": 346, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304005", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304005"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304005", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Orbital Edge Computing: Nanosatellite Constellations as a New Class of Computer System", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bradley Denby", "Brandon Lucia"], "abstract": "Advances in nanosatellite technology and a declining cost of access to space have fostered an emergence of large constellations of sensor-equipped satellites in low-Earth orbit. Many of these satellite systems operate under a \"bent-pipe\" architecture, in which ground stations send commands to orbit and satellites reply with raw data. In this work, we observe that a bent-pipe architecture for Earth-observing satellites breaks down as constellation population increases. Communication is limited by the physical configuration and constraints of the system over time, such as ground station location, nanosatellite antenna size, and energy harvested on orbit. We show quantitatively that nanosatellite constellation capabilities are determined by physical system constraints.", "doi": "10.1145/3373376.3378473", "arxiv_id": "https://doi.org/10.1145/3373376.3378473", "pmid": null, "openalex_id": null, "s2_id": "89ee7b075f148f172bfab9b2563a9cf6a5bdfc65", "cited_by": 317, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378473", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378473"], "github": ["https://github.com/CMUAbstract/cote"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378473", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mark Hildebrand", "Jawad Khan", "Sanjeev Trika", "Jason Lowe-Power", "Venkatesh Akella"], "abstract": "Memory capacity is a key bottleneck for training large scale neural networks. Intel® Optane#8482; DC PMM (persistent memory modules) which are available as NVDIMMs are a disruptive technology that promises significantly higher read bandwidth than traditional SSDs at a lower cost per bit than traditional DRAM. In this work we show how to take advantage of this new memory technology to minimize the amount of DRAM required without compromising performance significantly. Specifically, we take advantage of the static nature of the underlying computational graphs in deep neural network applications to develop a profile guided optimization based on Integer Linear Programming (ILP) called AutoTM to optimally assign and move live tensors to either DRAM or NVDIMMs. Our approach can replace 50% to 80% of a system's DRAM with PMM while only losing a geometric mean 27.7% performance. This is a significant improvement over first-touch NUMA, which loses 71.9% of performance. The proposed ILP based synchronous scheduling technique also provides 2x performance over using DRAM as a hardware-controlled cache for very large networks.", "doi": "10.1145/3373376.3378465", "arxiv_id": "https://doi.org/10.1145/3373376.3378465", "pmid": null, "openalex_id": null, "s2_id": "89f5236f12a9a5f16ab912be4b53682968cff537", "cited_by": 93, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378465", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378465"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378465", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PacketMill: toward per-Core 100-Gbps networking", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alireza Farshin", "Tom Barbette", "Amir Roozbeh", "Gerald Q. Maguire Jr.", "Dejan Kostic"], "abstract": "We present PacketMill, a system for optimizing software packet processing, which (i) introduces a new model to efficiently manage packet metadata and (ii) employs code-optimization techniques to better utilize commodity hardware. PacketMill grinds the whole packet processing stack, from the high-level network function configuration file to the low-level userspace network (specifically DPDK) drivers, to mitigate inefficiencies and produce a customized binary for a given network function. Our evaluation results show that PacketMill increases throughput (up to 36.4 Gbps -- 70%) & reduces latency (up to 101 us -- 28%) and enables nontrivial packet processing (e.g., router) at ~100 Gbps, when new packets arrive >10× faster than main memory access times, while using only one processing core.", "doi": "10.1145/3445814.3446724", "arxiv_id": "https://doi.org/10.1145/3445814.3446724", "pmid": null, "openalex_id": null, "s2_id": "8a041c20ccd7d7cbcfcf20ad79d692069dac61ef", "cited_by": 60, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446724", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446724"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446724", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Hypervisor for Shared-Memory FPGA Platforms", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jiacheng Ma", "Gefei Zuo", "Kevin Loughlin", "Xiaohe Cheng", "Yanqiang Liu", "Abel Mulugeta Eneyew", "Zhengwei Qi", "Baris Kasikci"], "abstract": "Cloud providers widely deploy FPGAs as application-specific accelerators for customer use. These providers seek to multiplex their FPGAs among customers via virtualization, thereby reducing running costs. Unfortunately, most virtualization support is confined to FPGAs that expose a restrictive, host-centric programming model in which accelerators cannot issue direct memory accesses (DMAs). The host-centric model incurs high runtime overhead for workloads that exhibit pointer chasing. Thus, FPGAs are beginning to support a shared-memory programming model in which accelerators can issue DMAs. However, virtualization support for shared-memory FPGAs is limited. This paper presents Optimus, the first hypervisor that supports scalable shared-memory FPGA virtualization. Optimus offers both spatial multiplexing and temporal multiplexing to provide efficient and flexible sharing of each accelerator on an FPGA. To share the FPGA-CPU interconnect at a high clock frequency, Optimus implements a multiplexer tree. To isolate each guest's address space, Optimus introduces the technique of page table slicing as a hardware-software co-design. To support preemptive temporal multiplexing, Optimus provides an accelerator preemption interface. We show that Optimus supports eight physical accelerators on a single FPGA and improves the aggregate throughput of twelve real-world benchmarks by 1.98x-7x.", "doi": "10.1145/3373376.3378482", "arxiv_id": "https://doi.org/10.1145/3373376.3378482", "pmid": null, "openalex_id": null, "s2_id": "8a24cd6ed1875c73761c9fa0ac76105a03e6e932", "cited_by": 74, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378482"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378482", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Translation-Triggered Prefetching", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Abhishek Bhattacharjee"], "abstract": "We propose translation-enabled memory prefetching optimizations or TEMPO, a low-overhead hardware mechanism to boost memory performance by exploiting the operating system's (OS) virtual memory subsystem. We are the first to make the following observations: (1) a substantial fraction (20-40%) of DRAM references in modern big- data workloads are devoted to accessing page tables; and (2) when memory references require page table lookups in DRAM, the vast majority of them (98%+) also look up DRAM for the subsequent data access. TEMPO exploits these observations to enable DRAM row-buffer and on-chip cache prefetching of the data that page tables point to. TEMPO requires trivial changes to the memory controller (under 3% additional area), no OS or application changes, and improves performance by 10-30% and energy by 1-14%.", "doi": "10.1145/3037697.3037705", "arxiv_id": "https://doi.org/10.1145/3037697.3037705", "pmid": null, "openalex_id": null, "s2_id": "8c10925312a296de9ad0ebc96093e4d8e6b4bc85", "cited_by": 70, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037705"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037705", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Reliable Timekeeping for Intermittent Computing", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jasper de Winkel", "Carlo Delle Donne", "Kasim Sinan Yildirim", "Przemyslaw Pawelczak", "Josiah D. Hester"], "abstract": "Energy-harvesting devices have enabled Internet of Things applications that were impossible before. One core challenge of batteryless sensors that operate intermittently is reliable timekeeping. State-of-the-art low-power real-time clocks suffer from long start-up times (order of seconds) and have low timekeeping granularity (tens of milliseconds at best), often not matching timing requirements of devices that experience numerous power outages per second. Our key insight is that time can be inferred by measuring alternative physical phenomena, like the discharge of a simple RC circuit, and that timekeeping energy cost and accuracy can be modulated depending on the run-time requirements. We achieve these goals with a multi-tier timekeeping architecture, named Cascaded Hierarchical Remanence Timekeeper (CHRT), featuring an array of different RC circuits to be used for dynamic timekeeping requirements. The CHRT and its accompanying software interface are embedded into a fresh batteryless wireless sensing platform, called Botoks, capable of tracking time across power failures. Low start-up time (max 5 ms), high resolution (up to 1 ms) and run-time reconfigurability are the key features of our timekeeping platform. We developed two time-sensitive batteryless applications to demonstrate the approach: a bicycle analytics tool, where the CHRT is used to track time between revolutions of a bicycle wheel, and wireless communication, where the CHRT enables radio synchronization between two intermittently-powered sensors.", "doi": "10.1145/3373376.3378464", "arxiv_id": "https://doi.org/10.1145/3373376.3378464", "pmid": null, "openalex_id": null, "s2_id": "8c51e521433d920d8f8ed1e847df4d86fe19e8a7", "cited_by": 98, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378464", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378464"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378464", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DeepSigns: An End-to-End Watermarking Framework for Ownership Protection of Deep Neural Networks", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bita Darvish Rouhani", "Huili Chen", "Farinaz Koushanfar"], "abstract": "Deep Learning (DL) models have created a paradigm shift in our ability to comprehend raw data in various important fields, ranging from intelligence warfare and healthcare to autonomous transportation and automated manufacturing. A practical concern, in the rush to adopt DL models as a service, is protecting the models against Intellectual Property (IP) infringement. DL models are commonly built by allocating substantial computational resources that process vast amounts of proprietary training data. The resulting models are therefore considered to be an IP of the model builder and need to be protected to preserve the owner's competitive advantage. We propose DeepSigns, the first end-to-end IP protection framework that enables developers to systematically insert digital watermarks in the target DL model before distributing the model. DeepSigns is encapsulated as a high-level wrapper that can be leveraged within common deep learning frameworks including TensorFlow and PyTorch. The libraries in DeepSigns work by dynamically learning the Probability Density Function (pdf) of activation maps obtained in different layers of a DL model. DeepSigns uses the low probabilistic regions within the model to gradually embed the owner's signature (watermark) during DL training while minimally affecting the overall accuracy and training overhead. DeepSigns can demonstrably withstand various removal and transformation attacks, including model pruning, model fine-tuning, and watermark overwriting. We evaluate DeepSigns performance on a wide variety of DL architectures including wide residual convolution neural networks, multi-layer perceptrons, and long short-term memory models. Our extensive evaluations corroborate DeepSigns' effectiveness and applicability. We further provide a highly-optimized accompanying API to facilitate training watermarked neural networks with a training overhead as low as 2.2%.", "doi": "10.1145/3297858.3304051", "arxiv_id": "https://doi.org/10.1145/3297858.3304051", "pmid": null, "openalex_id": null, "s2_id": "8c66adc178ad2a4cca93762edfe596fc9ccf14e1", "cited_by": 346, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304051", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304051"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304051", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Black-box Concurrent Data Structures for NUMA Architectures", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Irina Calciu", "Siddhartha Sen", "Mahesh Balakrishnan", "Marcos K. Aguilera"], "abstract": "High-performance servers are Non-Uniform Memory Access (NUMA) machines. To fully leverage these machines, programmers need efficient concurrent data structures that are aware of the NUMA performance artifacts. We propose Node Replication (NR), a black-box approach to obtaining such data structures. NR takes an arbitrary sequential data structure and automatically transforms it into a NUMA-aware concurrent data structure satisfying linearizability. Using NR requires no expertise in concurrent data structure design, and the result is free of concurrency bugs. NR draws ideas from two disciplines: shared-memory algorithms and distributed systems. Briefly, NR implements a NUMA-aware shared log, and then uses the log to replicate data structures consistently across NUMA nodes. NR is best suited for contended data structures, where it can outperform lock-free algorithms by 3.1x, and lock-based solutions by 30x. To show the benefits of NR to a real application, we apply NR to the data structures of Redis, an in-memory storage system. The result outperforms other methods by up to 14x. The cost of NR is additional memory for its log and replicas.", "doi": "10.1145/3037697.3037721", "arxiv_id": "https://doi.org/10.1145/3037697.3037721", "pmid": null, "openalex_id": null, "s2_id": "8e2660a880090fc1afc8e2d81840bcbba09a30df", "cited_by": 93, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037721"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037721", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": null, "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "8ecb50269237b91d3a5c6755f3f0ffa381540400", "cited_by": 3, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Automated Synthesis of Comprehensive Memory Model Litmus Test Suites", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daniel Lustig", "Andrew Wright", "Alexandros Papakonstantinou", "Olivier Giroux"], "abstract": "The memory consistency model is a fundamental part of any shared memory architecture or programming model. Modern weak memory models are notoriously difficult to define and to implement correctly. Most real-world programming languages, compilers, and (micro)architectures therefore rely heavily on black-box testing methodologies. The success of such techniques requires that the suite of litmus tests used to perform the testing be comprehensive--it should ideally stress all obscure corner cases of the model and of its implementation. Most litmus test suites today are generated from some combination of manual effort and randomization; however, the complex and subtle nature of contemporary memory models means that manual effort is both error-prone and subject to incomplete coverage.", "doi": "10.1145/3037697.3037723", "arxiv_id": "https://doi.org/10.1145/3037697.3037723", "pmid": null, "openalex_id": null, "s2_id": "8f2cba5df4d7848a43ec7cd47b742b2f2cd268c8", "cited_by": 55, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037723"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037723", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dongmoon Min", "Ilkwon Byun", "Gyu-hyeon Lee", "Seongmin Na", "Jangwoo Kim"], "abstract": "Cryogenic computing, which is to run a computer at extremely low temperatures (e.g., 77K), is a highly promising solution to dramatically improve the computer's performance and power efficiency thanks to the significantly reduced leakage power and wire resistance. However, computer architects are facing fundamental challenges in developing and deploying cryogenic-optimal architectural units due to the lack of understanding about its cost-effectiveness and feasibility (e.g., device and cooling costs vs. speedup, energy and area saving) and thus how to architect such cryogenic-optimal units. In this paper, we propose CryoCache, a cost-effective, technology-feasible cryogenic-optimal cache architecture running at 77K. For this goal, we first thoroughly analyze the cost-effectiveness and feasibility of various on-chip memory cell technologies running at 77K. Based on the analysis, we architect cryogenic-optimal caches with conventional technology-feasible 6T-SRAM and 3T-eDRAM cells whose performance, area, and power benefits at 77K clearly outweigh their cooling costs. Our evaluations show that our example CryoCache architecture achieves 2 times faster cache access and 2 times larger capacity compared to conventional caches running at the room temperature. To the best of our knowledge, this is the first work to propose a fast, large, and cost-effective cache architecture which can be applied to cryogenic computing.", "doi": "10.1145/3373376.3378513", "arxiv_id": "https://doi.org/10.1145/3373376.3378513", "pmid": null, "openalex_id": null, "s2_id": "8f49f6354c38ab5d25ee29f6f1f7f2413fbef4b5", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378513"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378513", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CHERI JNI: Sinking the Java Security Model into the C", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["David Chisnall", "Brooks Davis", "Khilan Gudka", "David Brazdil", "Alexandre Joannou", "Jonathan Woodruff", "A. Theodore Markettos", "J. Edward Maste", "Robert M. Norton", "Stacey D. Son", "Michael Roe", "Simon W. Moore", "Peter G. Neumann", "Ben Laurie", "Robert N. M. Watson"], "abstract": "Java provides security and robustness by building a high-level security model atop the foundation of memory protection. Unfortunately, any native code linked into a Java program -- including the million lines used to implement the standard library -- is able to bypass both the memory protection and the higher-level policies. We present a hardware-assisted implementation of the Java native code interface, which extends the guarantees required for Java's security model to native code.", "doi": "10.1145/3037697.3037725", "arxiv_id": "https://doi.org/10.1145/3037697.3037725", "pmid": null, "openalex_id": null, "s2_id": "8f53bef92f25071acd73b18393a436e3c05e57c1", "cited_by": 51, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037725&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037725"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037725", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HSM: A Hybrid Slowdown Model for Multitasking GPUs", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xia Zhao", "Magnus Jahre", "Lieven Eeckhout"], "abstract": "Graphics Processing Units (GPUs) are increasingly widely used in the cloud to accelerate compute-heavy tasks. However, GPU-compute applications stress the GPU architecture in different ways - leading to suboptimal resource utilization when a single GPU is used to run a single application. One solution is to use the GPU in a multitasking fashion to improve utilization. Unfortunately, multitasking leads to destructive interference between co-running applications which causes fairness issues and Quality-of-Service (QoS) violations. We propose the Hybrid Slowdown Model (HSM) to dynamically and accurately predict application slowdown due to interference. HSM overcomes the low accuracy of prior white-box models, and training and implementation overheads of pure black-box models, with a hybrid approach. More specifically, the white-box component of HSM builds upon the fundamental insight that effective bandwidth utilization is proportional to DRAM row buffer hit rate, and the black-box component of HSM uses linear regression to relate row buffer hit rate to performance. HSM accurately predicts application slowdown with an average error of 6.8%, a significant improvement over the current state-of-the-art. In addition, we use HSM to guide various resource management schemes in multitasking GPUs: HSM-Fair significantly improves fairness (by 1.59x on average) compared to even partitioning, whereas HSM-QoS improves system throughput (by 18.9% on average) compared to proportional SM partitioning while maintaining the QoS target for the high-priority application in challenging mixed memory/compute-bound multi-program workloads.", "doi": "10.1145/3373376.3378457", "arxiv_id": "https://doi.org/10.1145/3373376.3378457", "pmid": null, "openalex_id": null, "s2_id": "8fd1f229d238d1a50ba110b7ebaaa0607a605a1b", "cited_by": 42, "type": "conference", "is_oa": true, "pdf_urls": ["https://biblio.ugent.be/publication/8676313/file/8676315.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378457"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378457", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Whirlpool: Improving Dynamic Cache Management with Static Data Classification", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Anurag Mukkara", "Nathan Beckmann", "Daniel Sánchez"], "abstract": "Cache hierarchies are increasingly non-uniform and difficult to manage. Several techniques, such as scratchpads or reuse hints, use static information about how programs access data to manage the memory hierarchy. Static techniques are effective on regular programs, but because they set fixed policies, they are vulnerable to changes in program behavior or available cache space. Instead, most systems rely on dynamic caching policies that adapt to observed program behavior. Unfortunately, dynamic policies spend significant resources trying to learn how programs use memory, and yet they often perform worse than a static policy. We present Whirlpool, a novel approach that combines static information with dynamic policies to reap the benefits of each. Whirlpool statically classifies data into pools based on how the program uses memory. Whirlpool then uses dynamic policies to tune the cache to each pool. Hence, rather than setting policies statically, Whirlpool uses static analysis to guide dynamic policies. We present both an API that lets programmers specify pools manually and a profiling tool that discovers pools automatically in unmodified binaries. We evaluate Whirlpool on a state-of-the-art NUCA cache. Whirlpool significantly outperforms prior approaches: on sequential programs, Whirlpool improves performance by up to 38% and reduces data movement energy by up to 53%; on parallel programs, Whirlpool improves performance by up to 67% and reduces data movement energy by up to 2.6x.", "doi": "10.1145/2872362.2872363", "arxiv_id": "https://doi.org/10.1145/2872362.2872363", "pmid": null, "openalex_id": null, "s2_id": "90b1a77d7a7e390ff6ff0ddeb4fc65796d891890", "cited_by": 51, "type": "conference", "is_oa": true, "pdf_urls": ["http://hdl.handle.net/1721.1/112772", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872363"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872363", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "High Performance Packet Processing with FlexNIC", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Antoine Kaufmann", "Simon Peter", "Naveen Kr. Sharma", "Thomas E. Anderson", "Arvind Krishnamurthy"], "abstract": "The recent surge of network I/O performance has put enormous pressure on memory and software I/O processing sub systems. We argue that the primary reason for high memory and processing overheads is the inefficient use of these resources by current commodity network interface cards (NICs). We propose FlexNIC, a flexible network DMA interface that can be used by operating systems and applications alike to reduce packet processing overheads. FlexNIC allows services to install packet processing rules into the NIC, which then executes simple operations on packets while exchanging them with host memory. Thus, our proposal moves some of the packet processing traditionally done in software to the NIC, where it can be done flexibly and at high speed. We quantify the potential benefits of FlexNIC by emulating the proposed FlexNIC functionality with existing hardware or in software. We show that significant gains in application performance are possible, in terms of both latency and throughput, for several widely used applications, including a key-value store, a stream processing system, and an intrusion detection system.", "doi": "10.1145/2872362.2872367", "arxiv_id": "https://doi.org/10.1145/2872362.2872367", "pmid": null, "openalex_id": null, "s2_id": "90bbee5ed5c1e5806fdbbe2505ff70fa8681beac", "cited_by": 186, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872367&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872367"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872367", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Scalable Kernel TCP Design and Implementation for Short-Lived Connections", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiaofeng Lin", "Yu Chen", "Xiaodong Li", "Junjie Mao", "Jiaquan He", "Wei Xu", "Yuanchun Shi"], "abstract": "With the rapid growth of network bandwidth, increases in CPU cores on a single machine, and application API models demanding more short-lived connections, a scalable TCP stack is performance-critical. Although many clean-state designs have been proposed, production environments still call for a bottom-up parallel TCP stack design that is backward-compatible with existing applications.", "doi": "10.1145/2872362.2872391", "arxiv_id": "https://doi.org/10.1145/2872362.2872391", "pmid": null, "openalex_id": null, "s2_id": "90fe816f5af055871f63a77282d4a4849e0764d3", "cited_by": 63, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872391"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872391", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Clobber-NVM: log less, re-execute more", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yi Xu", "Joseph Izraelevitz", "Steven Swanson"], "abstract": "Non-volatile memory allows direct access to persistent storage via a load/store interface. However, because the cache is volatile, cached updates to persistent state will be dropped after a power loss. Failure-atomicity NVM libraries provide the means to apply sets of writes to persistent state atomically. Unfortunately, most of these libraries impose significant overhead.", "doi": "10.1145/3445814.3446730", "arxiv_id": "https://doi.org/10.1145/3445814.3446730", "pmid": null, "openalex_id": null, "s2_id": "918fd63893b97d756b18016f38d28ed9abe636ef", "cited_by": 41, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446730", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446730"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446730", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Breaking the computation and communication abstraction barrier in distributed machine learning workloads", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507778", "arxiv_id": "2105.05720", "pmid": null, "openalex_id": null, "s2_id": "91b29761840442005da39bc258e2298b528f31aa", "cited_by": 123, "type": null, "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2105.05720"], "github": ["https://github.com/parasailteam/coconet", "https://github.com/microsoft/msccl"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "TaxDC: A Taxonomy of Non-Deterministic Concurrency Bugs in Datacenter Distributed Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tanakorn Leesatapornwongsa", "Jeffrey F. Lukman", "Shan Lu", "Haryadi S. Gunawi"], "abstract": "We present TaxDC, the largest and most comprehensive taxonomy of non-deterministic concurrency bugs in distributed systems. We study 104 distributed concurrency (DC) bugs from four widely-deployed cloud-scale datacenter distributed systems, Cassandra, Hadoop MapReduce, HBase and ZooKeeper. We study DC-bug characteristics along several axes of analysis such as the triggering timing condition and input preconditions, error and failure symptoms, and fix strategies, collectively stored as 2,083 classification labels in TaxDC database. We discuss how our study can open up many new research directions in combating DC bugs.", "doi": "10.1145/2872362.2872374", "arxiv_id": "https://doi.org/10.1145/2872362.2872374", "pmid": null, "openalex_id": null, "s2_id": "91ec7ef1b6ffeba0a2b19f00501f2f7e52a76077", "cited_by": 165, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872374&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872374"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872374", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kaisheng Ma", "Xueqing Li", "Mahmut Taylan Kandemir", "Jack Sampson", "Vijaykrishnan Narayanan", "Jinyang Li", "Tongda Wu", "Zhibo Wang", "Yongpan Liu", "Yuan Xie"], "abstract": "Nonvolatile processors have emerged as one of the promising solutions for energy harvesting scenarios, among which Wireless Sensor Networks (WSN) provide some of the most important applications. In a typical distributed sensing system, due to difference in location, energy harvester angles, power sources, etc. different nodes may have different amount of energy ready for use. While prior approaches have examined these challenges, they have not done so in the context of the features offered by nonvolatile computing approaches, which disrupt certain foundational assumptions. We propose a new set of nonvolatility-exploiting optimizations and embody them in the NEOFog system architecture. We discuss shifts in the tradeoffs in data and program distribution for nonvolatile processing-based WSNs, showing how non-volatile processing and non-volatile RF support alter the benefits of computation and communication-centric approaches. We also propose a new algorithm specific to nonvolatile sensing systems for load balancing both computation and communication demands. Collectively, the NV-aware optimizations in NEOFog increase the ability to perform in-fog processing by 4.2X and can increase this to 8X if virtualized nodes are 3X multiplexed.", "doi": "10.1145/3173162.3177154", "arxiv_id": "https://doi.org/10.1145/3173162.3177154", "pmid": null, "openalex_id": null, "s2_id": "92bef85286549db653db4c4d55864195bc02a7b2", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177154"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177154", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Q-VR: system-level design for future mobile collaborative virtual reality", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chenhao Xie", "Xie Li", "Yang Hu", "Huwan Peng", "Michael B. Taylor", "Shuaiwen Leon Song"], "abstract": "High Quality Mobile Virtual Reality (VR) is what the incoming graphics technology era demands: users around the world, regardless of their hardware and network conditions, can all enjoy the immersive virtual experience. However, the state-of-the-art software-based mobile VR designs cannot fully satisfy the realtime performance requirements due to the highly interactive nature of user's actions and complex environmental constraints during VR execution. Inspired by the unique human visual system effects and the strong correlation between VR motion features and realtime hardware-level information, we propose Q-VR, a novel dynamic collaborative rendering solution via software-hardware co-design for enabling future low-latency high-quality mobile VR. At software-level, Q-VR provides flexible high-level tuning interface to reduce network latency while maintaining user perception. At hardware-level, Q-VR accommodates a wide spectrum of hardware and network conditions across users by effectively leveraging the computing capability of the increasingly powerful VR hardware. Extensive evaluation on real-world games demonstrates that Q-VR can achieve an average end-to-end performance speedup of 3.4x (up to 6.7x) over the traditional local rendering design in commercial VR devices, and a 4.1x frame rate improvement over the state-of-the-art static collaborative rendering.", "doi": "10.1145/3445814.3446715", "arxiv_id": "2102.13191", "pmid": null, "openalex_id": null, "s2_id": "92f337fccf5ff2a04fc38619a4921625fcca736d", "cited_by": 40, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2102.13191", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446715"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446715", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Occlum: Secure and Efficient Multitasking Inside a Single Enclave of Intel SGX", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Youren Shen", "Hongliang Tian", "Yu Chen", "Kang Chen", "Runji Wang", "Yi Xu", "Yubin Xia", "Shoumeng Yan"], "abstract": "Intel Software Guard Extensions (SGX) enables user-level code to create private memory regions called enclaves, whose code and data are protected by the CPU from software and hardware attacks outside the enclaves. Recent work introduces library operating systems (LibOSes) to SGX so that legacy applications can run inside enclaves with few or even no modifications. As virtually any non-trivial application demands multiple processes, it is essential for LibOSes to support multitasking. However, none of the existing SGX LibOSes support multitasking both securely and efficiently.", "doi": "10.1145/3373376.3378469", "arxiv_id": "2001.07450", "pmid": null, "openalex_id": null, "s2_id": "93943a87eb451d11163d99a7ecf06944ba414c2a", "cited_by": 215, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2001.07450", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378469"], "github": ["https://github.com/SecComputing/occlum", "https://github.com/occlum/ngo", "https://github.com/henrysun007/occlum", "https://github.com/occlum/occlum", "https://github.com/tatetian/occlum-old", "https://github.com/tatetian/occlum", "https://github.com/tatetian/ngo.old"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378469", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["James R. Larus", "Luis Ceze", "Karin Strauss"], "abstract": null, "doi": "10.1145/3373376", "arxiv_id": "https://doi.org/10.1145/3373376", "pmid": null, "openalex_id": null, "s2_id": "939f70d6f44202ce48fa99f85c536596ae2221ac", "cited_by": 6, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "LDX: Causality Inference by Lightweight Dual Execution", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yonghwi Kwon", "Dohyeong Kim", "William N. Sumner", "Kyungtae Kim", "Brendan Saltaformaggio", "Xiangyu Zhang", "Dongyan Xu"], "abstract": "Causality inference, such as dynamic taint anslysis, has many applications (e.g., information leak detection). It determines whether an event e is causally dependent on a preceding event c during execution. We develop a new causality inference engine LDX. Given an execution, it spawns a slave execution, in which it mutates c and observes whether any change is induced at e. To preclude non-determinism, LDX couples the executions by sharing syscall outcomes. To handle path differences induced by the perturbation, we develop a novel on-the-fly execution alignment scheme that maintains a counter to reflect the progress of execution. The scheme relies on program analysis and compiler transformation. LDX can effectively detect information leak and security attacks with an average overhead of 6.08% while running the master and the slave concurrently on separate CPUs, much lower than existing systems that require instruction level monitoring. Furthermore, it has much better accuracy in causality inference.", "doi": "10.1145/2872362.2872395", "arxiv_id": "https://doi.org/10.1145/2872362.2872395", "pmid": null, "openalex_id": null, "s2_id": "94247306a2c67d0ec3e631fc9ff848bc8218b5f0", "cited_by": 74, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872395"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872395", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Cogent: Verifying High-Assurance File System Implementations", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sidney Amani", "Alex Hixon", "Zilin Chen", "Christine Rizkallah", "Peter Chubb", "Liam O'Connor", "Joel Beeren", "Yutaka Nagashima", "Japheth Lim", "Thomas Sewell", "Joseph Tuong", "Gabriele Keller", "Toby C. Murray", "Gerwin Klein", "Gernot Heiser"], "abstract": "We present an approach to writing and formally verifying high-assurance file-system code in a restricted language called Cogent, supported by a certifying compiler that produces C code, high-level specification of Cogent, and translation correctness proofs. The language is strongly typed and guarantees absence of a number of common file system implementation errors. We show how verification effort is drastically reduced for proving higher-level properties of the file system implementation by reasoning about the generated formal specification rather than its low-level C code. We use the framework to write two Linux file systems, and compare their performance with their native C implementations.", "doi": "10.1145/2872362.2872404", "arxiv_id": "https://doi.org/10.1145/2872362.2872404", "pmid": null, "openalex_id": null, "s2_id": "948837266d3df839d4e3e1bc4d63b90e2fc9cae9", "cited_by": 106, "type": "conference", "is_oa": true, "pdf_urls": ["http://handle.unsw.edu.au/1959.4/unsworks_43147", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872404"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872404", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Iris Bahar", "Maurice Herlihy", "Emmett Witchel", "Alvin R. Lebeck"], "abstract": "On behalf of the organizing committee, we welcome you to the 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XXIV). The conference is located in Providence, Rhode Island, USA, a beautiful, walkable city that combines colonial period neighborhoods with fun architecture and excellent restaurants. Providence is also home to Brown University and the Rhode Island School of Design (both a short walk from the conference hotel). This year's conference continues the tradition of ASPLOS, providing a strong program that features exciting progress in computer architecture, programming languages, and operating systems. It represents the outstanding work of the Program Committee Chairs, Emmett Witchel and Alvin Lebeck, as well as the great reviewing efforts put forth by the program committee members and external reviewers. Our thanks also go to the steering committee for their support. An efficient and effective Organization Committee is essential to ASPLOS 2019. Much gratitude is due to Joshua San Miguel, who managed the whole finance flow. Our workshop co-chairs Ulya Karpuzcu, Paul Gratz, and Brian Greskamp organized an excellent set of interesting and attractive workshops and tutorials. Tali Moreshet and Christina Delimitrou took charge of the travel grants for the students and securing funding from the National Science Foundation to support the grants. Yufei Ding and Linhai Song did a great job in organizing the ACM Student Research Competition. Brandon Lucia and Tim Sherwood put together an amazing Wild and Crazy Ideas program. Many thanks to Rujia Wang for her great efforts in setting up the registration website. Thanks also to Abhishek Bhattacharjee and Guilherme Cox for organizing the online lightning talks. Jishen Zhao, Yiying Zhang, and Michel Kinsy did a wonderful job sending the word out and publicizing the calls for submissions and participation of ASPLOS and affiliated workshops and tutorials. Thank you to Xuehai Qian for developing and maintaining the conference website. Yungang Bao, Rudolf Eigenmann, Reetuparna Das, and Lawrence Rauchwerger used their connections to secure funding from our generous industrial sponsors. Our publications chair, Dimitra Papagiannopoulou worked diligently to collect and compile all the papers for the ASPLOS proceedings. Once again, we are co-located with VEE this year. We thank Jennifer Sartor, member of the VEE Organizing Committee, for working with us to make sure everything ran smoothly. Special thanks to Brown University for hosting the opening reception on Sunday evening. We send a big thank you to all the many student volunteers from Brown University who spent many hours assisting with registration and local arrangements.", "doi": "10.1145/3297858", "arxiv_id": "https://doi.org/10.1145/3297858", "pmid": null, "openalex_id": null, "s2_id": "94b5c607d275657bd00f3fe7934f67c2c5312c57", "cited_by": 16, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 4B: Energy and Thermal Management", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252400", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "94c4cd50ab02937773ccdc2a73daedd7c52e227f", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "vbench: Benchmarking Video Transcoding in the Cloud", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Andrea Lottarini", "Alex Ramírez", "Joel Coburn", "Martha A. Kim", "Parthasarathy Ranganathan", "Daniel Stodolsky", "Mark Wachsler"], "abstract": "This paper presents vbench, a publicly available benchmark for cloud video services. We are the first study, to the best of our knowledge, to characterize the emerging video-as-a-service workload. Unlike prior video processing benchmarks, vbench's videos are algorithmically selected to represent a large commercial corpus of millions of videos. Reflecting the complex infrastructure that processes and hosts these videos, vbench includes carefully constructed metrics and baselines. The combination of validated corpus, baselines, and metrics reveal nuanced tradeoffs between speed, quality, and compression. We demonstrate the importance of video selection with a microarchitectural study of cache, branch, and SIMD behavior. vbench reveals trends from the commercial corpus that are not visible in other video corpuses. Our experiments with GPUs under vbench's scoring scenarios reveal that context is critical: GPUs are well suited for live-streaming, while for video-on-demand shift costs from compute to storage and network. Counterintuitively, they are not viable for popular videos, for which highly compressed, high quality copies are required. We instead find that popular videos are currently well-served by the current trajectory of software encoders.", "doi": "10.1145/3173162.3173207", "arxiv_id": "https://doi.org/10.1145/3173162.3173207", "pmid": null, "openalex_id": null, "s2_id": "957e98a2084f6c2d22694aadd22f57070b5d7e23", "cited_by": 46, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3173207&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173207"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173207", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yue Zha", "Jing Li"], "abstract": "With the recent trend of promoting Field-Programmable Gate Arrays (FPGAs) to first-class citizens in accelerating compute-intensive applications in networking, cloud services and artificial intelligence, FPGAs face two major challenges in sustaining competitive advantages in performance and energy efficiency for diverse cloud workloads: 1) limited configuration capability for supporting light-weight computations/on-chip data storage to accelerate emerging search-/data-intensive applications. 2) lack of architectural support to hide reconfiguration overhead for assisting virtualization in a cloud computing environment. In this paper, we propose a reconfigurable memory-oriented computing fabric, namely Liquid Silicon-Monona (L-Si), enabled by emerging nonvolatile memory technology i.e. RRAM, to address these two challenges. Specifically, L-Si addresses the first challenge by virtue of a new architecture comprising a 2D array of physically identical but functionally-configurable building blocks. It, for the first time, extends the configuration capabilities of existing FPGAs from computation to the whole spectrum ranging from computation to data storage. It allows users to better customize hardware by flexibly partitioning hardware resources between computation and memory, greatly benefiting emerging search- and data-intensive applications. To address the second challenge, L-Si provides scalable multi-context architectural support to minimize reconfiguration overhead for assisting virtualization. In addition, we provide compiler support to facilitate the programming of applications written in high-level programming languages (e.g. OpenCL) and frameworks (e.g. TensorFlow, MapReduce) while fully exploiting the unique architectural capability of L-Si. Our evaluation results show L-Si achieves 99.6% area reduction, 1.43× throughput improvement and 94.0% power reduction on search-intensive benchmarks, as compared with the FPGA baseline. For neural network benchmarks, on average, L-Si achieves 52.3× speedup, 113.9× energy reduction and 81% area reduction over the FPGA baseline. In addition, the multi-context architecture of L-Si reduces the context switching time to - 10ns, compared with an off-the-shelf FPGA (∼100ms), greatly facilitating virtualization.", "doi": "10.1145/3173162.3173167", "arxiv_id": "https://doi.org/10.1145/3173162.3173167", "pmid": null, "openalex_id": null, "s2_id": "96bcfbb766744dbd2127ca50f4411a8857849dad", "cited_by": 14, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173167"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173167", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Potluck: Cross-Application Approximate Deduplication for Computation-Intensive Mobile Applications", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Peizhen Guo", "Wenjun Hu"], "abstract": "Emerging mobile applications, such as cognitive assistance and augmented reality (AR) based gaming, are increasingly computation-intensive and latency-sensitive, while running on resource-constrained devices. The standard approaches to addressing these involve either offloading to a cloud(let) or local system optimizations to speed up the computation, often trading off computation quality for low latency. Instead, we observe that these applications often operate on similar input data from the camera feed and share common processing components, both within the same (type of) applications and across different ones. Therefore, deduplicating processing across applications could deliver the best of both worlds. In this paper, we present Potluck, to achieve approximate deduplication. At the core of the system is a cache service that stores and shares processing results between applications and a set of algorithms to process the input data to maximize deduplication opportunities. This is implemented as a background service on Android. Extensive evaluation shows that Potluck can reduce the processing latency for our AR and vision workloads by a factor of 2.5 to 10.", "doi": "10.1145/3173162.3173185", "arxiv_id": "https://doi.org/10.1145/3173162.3173185", "pmid": null, "openalex_id": null, "s2_id": "9809ca7526b57a8494541e0365661743b45debbf", "cited_by": 77, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173185"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173185", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Michael Pellauer", "Yakun Sophia Shao", "Jason Clemons", "Neal Clayton Crago", "Kartik Hegde", "Rangharajan Venkatesan", "Stephen W. Keckler", "Christopher W. Fletcher", "Joel S. Emer"], "abstract": "Accelerators spend significant area and effort on custom on-chip buffering. Unfortunately, these solutions are strongly tied to particular designs, hampering re-usability across other accelerators or domains. We present buffets, an efficient and composable storage idiom for the needs of accelerators that is independent of any particular design. Buffets have several distinguishing characteristics, including efficient decoupled fills and accesses with fine-grained synchronization, hierarchical composition, and efficient multi-casting. We implement buffets in RTL and show that they only add 2% control overhead over an 8KB RAM. When compared with DMA-managed double-buffered scratchpads and caches across a range of workloads, buffets improve energy-delay-product by 1.53x and 5.39x, respectively.", "doi": "10.1145/3297858.3304025", "arxiv_id": "https://doi.org/10.1145/3297858.3304025", "pmid": null, "openalex_id": null, "s2_id": "988989673e463db8227e3e4b74bc299ff3ae087c", "cited_by": 93, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304025", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304025"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304025", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Protecting Page Tables from RowHammer Attacks using Monotonic Pointers in DRAM True-Cells", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xin-Chuan Wu", "Timothy Sherwood", "Frederic T. Chong", "Yanjing Li"], "abstract": "We identify an important asymmetry in physical DRAM cells that can be utilized to prevent RowHammer attacks by adding 18 lines of code to modify the OS memory allocator. Our small modification has a powerful impact on RowHammer's ability to bypass memory protection mechanisms and achieve a successful attack. Specifically, we identify two types of DRAM cells: true-cells and anti-cells. In a true-cell, a leaking capacitor will induce a '1'->'0' error, while in anti-cells, errors flow from '0'->'1'. We then create DRAM cell-type-aware memory allocation which enables a \"monotonicity property\" for a given data object. The monotonicity property is able to counter RowHammer attacks (and, to a broader extent, other memory attacks) by allocating only one type of cells for an object, thereby restricting error direction. We apply the monotonicity property to pointers in page tables by placing all page tables in true-cells that are above a \"low water mark\". We show that this approach successfully defends against page-table-based privilege escalation RowHammer attacks. Using established RowHammer-induced bit-flip error statistics, we provide proofs of the soundness and completeness of our technique and show that with our technique only one out of 2.04x10 5 systems is vulnerable to the attack, and the expected attack time on the vulnerable system is 231 days. We also provide application performance results from prototypes implemented through modifications to Linux kernels. Our cross-layer approach avoids undesirable energy cost, hardware changes, performance overhead, and high software complexity associated with prior countermeasures.", "doi": "10.1145/3297858.3304039", "arxiv_id": "https://doi.org/10.1145/3297858.3304039", "pmid": null, "openalex_id": null, "s2_id": "99f9a30daba8ac3ba4ea2c6a3f9b0591e0ca337f", "cited_by": 51, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304039&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304039"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304039", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Exploiting Intra-Request Slack to Improve SSD Performance", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Nima Elyasi", "Mohammad Arjomand", "Anand Sivasubramaniam", "Mahmut T. Kandemir", "Chita R. Das", "Myoungsoo Jung"], "abstract": "With Solid State Disks (SSDs) offering high degrees of parallelism, SSD controllers place data and direct requests to exploit the maximum offered hardware parallelism. In the quest to maximize parallelism and utilization, sub-requests of a request that are directed to different flash chips by the scheduler can experience differential wait times since their individual queues are not coordinated and load balanced at all times. Since the macro request is considered complete only when its last sub-request completes, some of its sub-requests that complete earlier have to necessarily wait for this last sub-request. This paper opens the door to a new class of schedulers to leverage such slack between sub-requests in order to improve response times. Specifically, the paper presents the design and implementation of a slack-enabled re-ordering scheduler, called Slacker, for sub-requests issued to each flash chip. Layered under a modern SSD request scheduler, Slacker estimates the slack of each incoming sub-request to a flash chip and allows them to jump ahead of existing sub-requests with sufficient slack so as to not detrimentally impact their response times. Slacker is simple to implement and imposes only marginal additions to the hardware. Using a spectrum of 21 workloads with diverse read-write characteristics, we show that Slacker provides as much as 19.5%, 13% and 14.5% improvement in response times, with average improvements of 12%, 6.5% and 8.5%, for write-intensive, read-intensive and read-write balanced workloads, respectively.", "doi": "10.1145/3037697.3037728", "arxiv_id": "https://doi.org/10.1145/3037697.3037728", "pmid": null, "openalex_id": null, "s2_id": "9a3166a3211c839526d2270ff49bd4519bbac084", "cited_by": 68, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037728&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037728"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037728", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tian Jin", "Seokin Hong"], "abstract": "We present an interdisciplinary study to tackle the memory bottleneck of training deep convolutional neural networks (CNN). Firstly, we introduce Split Convolutional Neural Network (Split-CNN) that is derived from the automatic transformation of the state-of-the-art CNN models. The main distinction between Split-CNN and regular CNN is that Split-CNN splits the input images into small patches and operates on these patches independently before entering later stages of the CNN model. Secondly, we propose a novel heterogeneous memory management system (HMMS) to utilize the memory-friendly properties of Split-CNN. Through experiments, we demonstrate that Split-CNN achieves significantly higher training scalability by dramatically reducing the memory requirements of training algorithms on GPU accelerators. Furthermore, we provide empirical evidence that splitting at randomly chosen boundaries can even result in accuracy gains over baseline CNN due to its regularization effect.", "doi": "10.1145/3297858.3304038", "arxiv_id": "https://doi.org/10.1145/3297858.3304038", "pmid": null, "openalex_id": null, "s2_id": "9a556b5a50b6d7a017935eb6a8a9dfd79b264729", "cited_by": 51, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304038"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304038", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MOD: Minimally Ordered Durable Datastructures for Persistent Memory", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Swapnil Haria", "Mark D. Hill", "Michael M. Swift"], "abstract": "Persistent Memory (PM) makes possible recoverable applications that can preserve application progress across system reboots and power failures. Actual recoverability requires careful ordering of cacheline flushes, currently done in two extreme ways. On one hand, expert programmers have reasoned deeply about consistency and durability to create applications centered on a single custom-crafted durable datastructure. On the other hand, less-expert programmers have used software transaction memory (STM) to make atomic one or more updates, albeit at a significant performance cost due largely to ordered log updates. In this work, we propose the middle ground of composable persistent datastructures called Minimally Ordered Durable datastructures (MOD). We prototype MOD as a library of C++ datastructures---currently, map, set, stack, queue and vector---that often perform better than STM and yet are relatively easy to use. They allow multiple updates to one or more datastructures to be atomic with respect to failure. Moreover, we provide a recipe to create additional recoverable datastructures. MOD is motivated by our analysis of real Intel Optane PM hardware showing that allowing unordered, overlapping flushes significantly improves performance. MOD reduces ordering by adapting existing techniques for out-of-place updates (like shadow paging) with space-reducing structural sharing (from functional programming). MOD exposes a Basic interface for single updates and a Composition interface for atomically performing multiple updates. Relative to widely used Intel PMDK v1.5 STM, MOD improves map, set, stack, queue microbenchmark performance by 40%, and speeds up application benchmark performance by 38%.", "doi": "10.1145/3373376.3378472", "arxiv_id": "1908.11850", "pmid": null, "openalex_id": null, "s2_id": "9a850089b0b183b23f2eb8b9c35158d6d338b291", "cited_by": 59, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378472", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378472"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378472", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Scalable Processing of Contemporary Semi-Structured Data on Commodity Parallel Processors - A Compilation-based Approach", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Lin Jiang", "Xiaofan Sun", "Umar Farooq", "Zhijia Zhao"], "abstract": "JSON (JavaScript Object Notation) and its derivatives are essential in the modern computing infrastructure. However, existing software often fails to process such types of data in a scalable way, mainly for two reasons: (i) the processing often requires to build a memory-consuming parse tree; (ii) there exist inherent dependences in processing the data stream, preventing any data-level parallelization. Facing the challenges, developers often have to construct ad-hoc pre-parsers to split the data stream in order to reduce the memory consumption and increase the data parallelism. However, this strategy requires more programming efforts. Moreover, the pre-parsing itself is non-trivial to parallelize, thus introducing a new serial bottleneck. To solve the dilemma, this work introduces a scalable yet fully automatic solution - a compilation system, namely JPStream, that compiles standard JSONPath queries into parallel executables with bounded memory footprints. First, JPStream adopts a stream processing design that combines the querying and parsing into one pass, without generating any in-memory parse tree. To achieve this, JPStream uses a novel joint compilation technique that compiles the queries and the JSON syntax together into a single automaton. Furthermore, JPStream leverages the \"enumerability'' of automaton to break the dependences and reason about the transition rules to prune infeasible states. It also features a runtime that learns structural constraints from the input to enhance the pruning. Evaluation on real-world JSON datasets with standard JSONPath queries shows that JPStream can reduce the memory consumption significantly, by up to 95%, meanwhile achieving near-linear speedup on multicore and manycore processors.", "doi": "10.1145/3297858.3304008", "arxiv_id": "https://doi.org/10.1145/3297858.3304008", "pmid": null, "openalex_id": null, "s2_id": "9aed88586ae86fdd75f5edbb2e351e5c2651e92d", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304008", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304008"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304008", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ProRace: Practical Data Race Detection for Production Use", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tong Zhang", "Changhee Jung", "Dongyoon Lee"], "abstract": "This paper presents ProRace, a dynamic data race detector practical for production runs. It is lightweight, but still offers high race detection capability. To track memory accesses, ProRace leverages instruction sampling using the performance monitoring unit (PMU) in commodity processors. Our PMU driver enables ProRace to sample more memory accesses at a lower cost compared to the state-of-the-art Linux driver. Moreover, ProRace uses PMU-provided execution contexts including register states and program path, and reconstructs unsampled memory accesses offline. This technique allows \\ProRace to overcome inherent limitations of sampling and improve the detection coverage by performing data race detection on the trace with not only sampled but also reconstructed memory accesses. Experiments using racy production software including apache and mysql shows that, with a reasonable offline cost, ProRace incurs only 2.6% overhead at runtime with 27.5% detection probability with a sampling period of 10,000.", "doi": "10.1145/3037697.3037708", "arxiv_id": "https://doi.org/10.1145/3037697.3037708", "pmid": null, "openalex_id": null, "s2_id": "9c0734e4473354cd73dd270459b41e85abe6af9a", "cited_by": 50, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037708"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037708", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Datasize-Aware High Dimensional Configurations Auto-Tuning of In-Memory Cluster Computing", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhibin Yu", "Zhendong Bei", "Xuehai Qian"], "abstract": "In-Memory cluster Computing (IMC) frameworks (e.g., Spark) have become increasingly important because they typically achieve more than 10× speedups over the traditional On-Disk cluster Computing (ODC) frameworks for iterative and interactive applications. Like ODC, IMC frameworks typically run the same given programs repeatedly on a given cluster with similar input dataset size each time. It is challenging to build performance model for IMC program because: 1) the performance of IMC programs is more sensitive to the size of input dataset, which is known to be difficult to be incorporated into a performance model due to its complex effects on performance; 2) the number of performance-critical configuration parameters in IMC is much larger than ODC (more than 40 vs. around 10), the high dimensionality requires more sophisticated models to achieve high accuracy. To address this challenge, we propose DAC, a datasize-aware auto-tuning approach to efficiently identify the high dimensional configuration for a given IMC program to achieve optimal performance on a given cluster. DAC is a significant advance over the state-of-the-art because it can take the size of input dataset and 41 configuration parameters as the parameters of the performance model for a given IMC program, --- unprecedented in previous work. It is made possible by two key techniques: 1) Hierarchical Modeling (HM), which combines a number of individual sub-models in a hierarchical manner; 2) Genetic Algorithm (GA) is employed to search the optimal configuration. To evaluate DAC, we use six typical Spark programs, each with five different input dataset sizes. The evaluation results show that DAC improves the performance of six typical Spark programs, each with five different input dataset sizes compared to default configurations by a factor of 30.4x on average and up to 89x. We also report that the geometric mean speedups of DAC over configurations by default, expert, and RFHOC are 15.4x, 2.3x, and 1.5x, respectively.", "doi": "10.1145/3173162.3173187", "arxiv_id": "https://doi.org/10.1145/3173162.3173187", "pmid": null, "openalex_id": null, "s2_id": "9c1ba2c29050ac2b629d1411b1eee24eb11f1b4e", "cited_by": 92, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173187"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173187", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Efficient Compactions between Storage Tiers with PrismDB", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3582016.3582052", "arxiv_id": "2008.02352", "pmid": null, "openalex_id": null, "s2_id": "9dcd2ed4cadfbf84b761a3c6811523523db5e6d3", "cited_by": 15, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3582016.3582052"], "github": ["https://github.com/princeton-sns/prismdb"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 7A: Non-traditional Computer Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252406", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "9ee6239439405ccf838c1f6b315d02afbc835795", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Accelerating Legacy String Kernels via Bounded Automata Learning", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kevin Angstadt", "Jean-Baptiste Jeannin", "Westley Weimer"], "abstract": "The adoption of hardware accelerators, such as FPGAs, into general-purpose computation pipelines continues to rise, but programming models for these devices lag far behind their CPU counterparts. Legacy programs must often be rewritten at very low levels of abstraction, requiring intimate knowledge of the target accelerator architecture. While techniques such as high-level synthesis can help port some legacy software, many programs perform poorly without manual, architecture-specific optimization.", "doi": "10.1145/3373376.3378503", "arxiv_id": "https://doi.org/10.1145/3373376.3378503", "pmid": null, "openalex_id": null, "s2_id": "9ef22b72ee28c1cb04e07108bf3cc899ab6f5332", "cited_by": 9, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378503", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378503"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378503", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Bit-Tactical: A Software/Hardware Approach to Exploiting Value and Bit Sparsity in Neural Networks", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alberto Delmas Lascorz", "Patrick Judd", "Dylan Malone Stuart", "Zissis Poulos", "Mostafa Mahmoud", "Sayeh Sharify", "Milos Nikolic", "Kevin Siu", "Andreas Moshovos"], "abstract": "Weight and activation sparsity can be leveraged in hardware to boost the performance and energy efficiency of Deep Neural Networks during inference. Fully capitalizing on sparsity requires re-scheduling and mapping the execution stream to deliver non-zero weight/activation pairs to multiplier units for maximal utilization and reuse. However, permitting arbitrary value re-scheduling in memory space and in time places a considerable burden on hardware to perform dynamic at-runtime routing and matching of values, and incurs significant energy inefficiencies. Bit-Tactical (TCL) is a neural network accelerator where the responsibility for exploiting weight sparsity is shared between a novel static scheduling middleware, and a co-designed hardware front-end with a lightweight sparse shuffling network comprising two (2- to 8-input) multiplexers per activation input. We empirically motivate two back-end designs chosen to target bit-sparsity in activations, rather than value-sparsity, with two benefits: a) we avoid handling the dynamically sparse whole-value activation stream, and b) we uncover more ineffectual work. TCL outperforms other state-of-the-art accelerators that target sparsity for weights and activations, the dynamic precision requirements of activations, or their bit-level sparsity for a variety of neural networks.", "doi": "10.1145/3297858.3304041", "arxiv_id": "https://doi.org/10.1145/3297858.3304041", "pmid": null, "openalex_id": null, "s2_id": "9f9c4dd9a761a708cfcec6951ff67ce8953978c0", "cited_by": 110, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304041&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304041"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304041", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "An Open-Source Benchmark Suite for Microservices and Their Hardware-Software Implications for Cloud & Edge Systems", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yu Gan", "Yanqi Zhang", "Dailun Cheng", "Ankitha Shetty", "Priyal Rathi", "Nayan Katarki", "Ariana Bruno", "Justin Hu", "Brian Ritchken", "Brendon Jackson", "Kelvin Hu", "Meghna Pancholi", "Yuan He", "Brett Clancy", "Chris Colen", "Fukang Wen", "Catherine Leung", "Siyuan Wang", "Leon Zaruvinsky", "Mateo Espinosa", "Rick Lin", "Zhongling Liu", "Jake Padilla", "Christina Delimitrou"], "abstract": "Cloud services have recently started undergoing a major shift from monolithic applications, to graphs of hundreds or thousands of loosely-coupled microservices. Microservices fundamentally change a lot of assumptions current cloud systems are designed with, and present both opportunities and challenges when optimizing for quality of service (QoS) and cloud utilization.", "doi": "10.1145/3297858.3304013", "arxiv_id": "https://doi.org/10.1145/3297858.3304013", "pmid": null, "openalex_id": null, "s2_id": "a022334521d88eb0181e76f01b53ce42e7dcc302", "cited_by": 873, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304013", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304013"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304013", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A DNA-Based Archival Storage System", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["James Bornholt", "Randolph Lopez", "Douglas M. Carmean", "Luis Ceze", "Georg Seelig", "Karin Strauss"], "abstract": "Demand for data storage is growing exponentially, but the capacity of existing storage media is not keeping up. Using DNA to archive data is an attractive possibility because it is extremely dense, with a raw limit of 1 exabyte/mm3 (109 GB/mm3), and long-lasting, with observed half-life of over 500 years. This paper presents an architecture for a DNA-based archival storage system. It is structured as a key-value store, and leverages common biochemical techniques to provide random access. We also propose a new encoding scheme that offers controllable redundancy, trading off reliability for density. We demonstrate feasibility, random access, and robustness of the proposed encoding with wet lab experiments involving 151 kB of synthesized DNA and a 42 kB random-access subset, and simulation experiments of larger sets calibrated to the wet lab experiments. Finally, we highlight trends in biotechnology that indicate the impending practicality of DNA storage for much larger datasets.", "doi": "10.1145/2872362.2872397", "arxiv_id": "https://doi.org/10.1145/2872362.2872397", "pmid": null, "openalex_id": null, "s2_id": "a0665a7fd8fc3e25b527f0a0e983c383dc40ba20", "cited_by": 485, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872397&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872397"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872397", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mohammad Sadrosadati", "Amirhossein Mirhosseini", "Seyed Borna Ehsani", "Hamid Sarbazi-Azad", "Mario Drumond", "Babak Falsafi", "Rachata Ausavarungnirun", "Onur Mutlu"], "abstract": "Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical structure while keeping power consumption low. We observe that compile-time interval analysis enables us to divide GPU program execution into intervals with an accurate estimate of a warp's aggregate register working-set within each interval. The key idea of LTRF is to prefetch the estimated register working-set from the main register file to the register file cache under software control, at the beginning of each interval, and overlap the prefetch latency with the execution of other warps. Our experimental results show that LTRF enables high-capacity yet long-latency main GPU register files, paving the way for various optimizations. As an example optimization, we implement the main register file with emerging high-density high-latency memory technologies, enabling 8X larger capacity and improving overall GPU performance by 31% while reducing register file power consumption by 46%.", "doi": "10.1145/3173162.3173211", "arxiv_id": "https://doi.org/10.1145/3173162.3173211", "pmid": null, "openalex_id": null, "s2_id": "a0c083adccc90b29a9680e1277f72dfdfc37e8a2", "cited_by": 48, "type": "conference", "is_oa": true, "pdf_urls": ["http://infoscience.epfl.ch/record/254995", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173211"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173211", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Reconfigurable Energy Storage Architecture for Energy-harvesting Devices", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alexei Colin", "Emily Ruppel", "Brandon Lucia"], "abstract": "Battery-free, energy-harvesting devices operate using energy collected exclusively from their environment. Energy-harvesting devices allow maintenance-free deployment in extreme environments, but requires a power system to provide the right amount of energy when an application needs it. Existing systems must provision energy capacity statically based on an application's peak demand which compromises efficiency and responsiveness when not at peak demand. This work presents Capybara: a co-designed hardware/software power system with dynamically reconfigurable energy storage capacity that meets varied application energy demand. The Capybara software interface allows programmers to specify the energy mode of an application task. Capybara's runtime system reconfigures Capybara's hardware energy capacity to match application demand. Capybara also allows a programmer to write reactive application tasks that pre-allocate a burst of energy that it can spend in response to an asynchronous (e.g., external) event. We instantiated Capybara's hardware design in two EH devices and implemented three reactive sensing applications using its software interface. Capybara improves event detection accuracy by 2x-4x over statically-provisioned energy capacity, maintains response latency within 1.5x of a continuously-powered baseline, and enables reactive applications that are intractable with existing power systems.", "doi": "10.1145/3173162.3173210", "arxiv_id": "https://doi.org/10.1145/3173162.3173210", "pmid": null, "openalex_id": null, "s2_id": "a0fd9e7b1df7274f6e568b11d3861452497a7065", "cited_by": 223, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173210", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173210"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173210", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Coterie: Exploiting Frame Similarity to Enable High-Quality Multiplayer VR on Commodity Mobile Devices", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jiayi Meng", "Sibendu Paul", "Y. Charlie Hu"], "abstract": "In this paper, we study how to support high-quality immersive multiplayer VR on commodity mobile devices. First, we perform a scaling experiment that shows simply replicating the prior-art 2-layer distributed VR rendering architecture to multiple players cannot support more than one player due to the linear increase in network bandwidth requirement. Second, we propose to exploit the similarity of background environment (BE) frames to reduce the bandwidth needed for prefetching BE frames from the server, by caching and reusing similar frames. We find that there is often little similarly between the BE frames of even adjacent locations in the virtual world due to a \"near-object\" effect. We propose a novel technique that splits the rendering of BE frames between the mobile device and the server that drastically enhances the similarity of the BE frames and reduces the network load from frame caching. Evaluation of our implementation on top of Unity and Google Daydream shows our new VR framework, Coterie, reduces per-player network requirement by 10.6X-25.7X and easily supports 4 players for high-resolution VR apps on Pixel 2 over 802.11ac, with 60 FPS and under 16ms responsiveness.", "doi": "10.1145/3373376.3378516", "arxiv_id": "https://doi.org/10.1145/3373376.3378516", "pmid": null, "openalex_id": null, "s2_id": "a25b77e58d962ec525b990e610a7cfd634222724", "cited_by": 79, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378516"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378516", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "AMNESIAC: Amnesic Automatic Computer", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ismail Akturk", "Ulya R. Karpuzcu"], "abstract": "Due to imbalances in technology scaling, the energy consumption of data storage and communication by far exceeds the energy consumption of actual data production, i.e., computation. As a consequence, recomputing data can become more energy efficient than storing and retrieving precomputed data. At the same time, recomputation can relax the pressure on the memory hierarchy and the communication bandwidth. This study hence assesses the energy efficiency prospects of trading computation for communication. We introduce an illustrative proof-of-concept design, identify practical limitations, and provide design guidelines.", "doi": "10.1145/3037697.3037741", "arxiv_id": "https://doi.org/10.1145/3037697.3037741", "pmid": null, "openalex_id": null, "s2_id": "a31583838981180cfda4d4f9361c75f55a81853c", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037741"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037741", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Lazy Release Persistency", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mahesh Dananjaya", "Vasilis Gavrielatos", "Arpit Joshi", "Vijay Nagarajan"], "abstract": "Fast non-volatile memory (NVM) has sparked interest in log-free data structures (LFDs) that enable crash recovery without the overhead of logging. However, recovery hinges on primitives that provide guarantees on what remains in NVM upon a crash. While ordering and atomicity are two well-understood primitives, we focus on ordering and its efficacy in enabling recovery of LFDs. We identify that one-sided persist barriers of acquire-release persistency (ARP)--the state-of-the-art ordering primitive and its microarchitectural implementation--are not strong enough to enable recovery of an LFD. Therefore, correct recovery necessitates the inclusion of the more expensive full barriers. In this paper, we propose strengthening the one-sided barrier semantics of ARP. The resulting persistency model, release persistency (RP), guarantees that NVM will hold a consistent-cut of the execution upon a crash, thereby satisfying the criterion for correct recovery of an LFD. We then propose lazy release persistency (LRP), a microarchitectural mechanism for efficiently enforcing RP's one-sided barriers. Our evaluation on 5 commonly used LFDs suggests that LRP provides a 14%-44% performance improvement over the state-of-the-art full barrier.", "doi": "10.1145/3373376.3378481", "arxiv_id": "https://doi.org/10.1145/3373376.3378481", "pmid": null, "openalex_id": null, "s2_id": "a39c727dedeb3e81bb39d21a1a5a427a483bfdf7", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378481"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378481", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Making Huge Pages Actually Useful", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ashish Panwar", "Aravinda Prasad", "K. Gopinath"], "abstract": "The virtual-to-physical address translation overhead, a major performance bottleneck for modern workloads, can be effectively alleviated with huge pages. However, since huge pages must be mapped contiguously, OSs have not been able to use them well because of the memory fragmentation problem despite hardware support for huge pages being available for nearly two decades. This paper presents a comprehensive study of the interaction of fragmentation with huge pages in the Linux kernel. We observe that when huge pages are used, problems such as high CPU utilization and latency spikes occur because of unnecessary work (e.g., useless page migration) performed by memory management related subsystems due to the poor handling of unmovable (i.e., kernel) pages. This behavior is even more harmful in virtualized systems where unnecessary work may be performed in both guest and host OSs. We present Illuminator, an efficient memory manager that provides various subsystems, such as the page allocator, the ability to track all unmovable pages. It allows subsystems to make informed decisions and eliminate unnecessary work which in turn leads to cost-effective huge page allocations. Illuminator reduces the cost of compaction (up to 99%), improves application performance (up to 2.3x) and reduces the maximum latency of MySQL database server (by 30x). Importantly, this work shows the effectiveness of a simple solution for long-standing huge page related problems.", "doi": "10.1145/3173162.3173203", "arxiv_id": "https://doi.org/10.1145/3173162.3173203", "pmid": null, "openalex_id": null, "s2_id": "a4710ac80826e48a410b1b9da80c2ca0f4a6a357", "cited_by": 124, "type": "conference", "is_oa": true, "pdf_urls": ["http://eprints.iisc.ac.in/61408/1/Acm_Sig_Not_53-2_2018.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173203"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173203", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 8B: Debugging", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248629", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "a49e3c5a91d6ba19ea162e04ea022041e9b66a90", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A compiler infrastructure for accelerator generators", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Rachit Nigam", "Samuel Thomas", "Zhijing Li", "Adrian Sampson"], "abstract": "  We present Calyx, a new intermediate language (IL) for compiling high-level\nprograms into hardware designs. Calyx combines a hardware-like structural\nlanguage with a software-like control flow representation with loops and\nconditionals. This split representation enables a new class of hardware-focused\noptimizations that require both structural and control flow information which\nare crucial for high-level programming models for hardware design. The Calyx\ncompiler lowers control flow constructs using finite-state machines and\ngenerates synthesizable hardware descriptions.\n  We have implemented Calyx in an optimizing compiler that translates\nhigh-level programs to hardware. We demonstrate Calyx using two DSL-to-RTL\ncompilers, a systolic array generator and one for a recent imperative\naccelerator language, and compare them to equivalent designs generated using\nhigh-level synthesis (HLS). The systolic arrays are $4.6\\times$ faster and\n$1.1\\times$ larger on average than HLS implementations, and the HLS-like\nimperative language compiler is within a few factors of a highly optimized\ncommercial HLS toolchain. We also describe three optimizations implemented in\nthe Calyx compiler.\n", "doi": "10.1145/3445814.3446712", "arxiv_id": "2102.09713", "pmid": null, "openalex_id": null, "s2_id": "a559717fc77c041ab28e3f51ceba0ddae82547ab", "cited_by": 73, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2102.09713", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446712"], "github": ["https://github.com/cucapra/calyx"], "sources": ["semanticscholar", "papervault", "open-arxiv"], "landing": "https://doi.org/10.1145/3445814.3446712", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems", "journal_ref": "ASPLOS 2021: Proceedings of the 26th ACM International Conference\n  on Architectural Support for Programming Languages and Operating Systems", "categories": "cs.PL cs.AR"}
{"title": "Understanding and Auto-Adjusting Performance-Sensitive Configurations", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Shu Wang", "Chi Li", "Henry Hoffmann", "Shan Lu", "William Sentosa", "Achmad Imam Kistijantoro"], "abstract": "Modern software systems are often equipped with hundreds to thousands of configurations, many of which greatly affect performance. Unfortunately, properly setting these configurations is challenging for developers due to the complex and dynamic nature of system workload and environment. In this paper, we first conduct an empirical study to understand performance-sensitive configurations and the challenges of setting them in the real-world. Guided by our study, we design a systematic and general control-theoretic framework, SmartConf, to automatically set and dynamically adjust performance-sensitive configurations to meet required operating constraints while optimizing other performance metrics. Evaluation shows that SmartConf is effective in solving real-world configuration problems, often providing better performance than even the best static configuration developers can choose under existing configuration systems.", "doi": "10.1145/3173162.3173206", "arxiv_id": "https://doi.org/10.1145/3173162.3173206", "pmid": null, "openalex_id": null, "s2_id": "a55a685d254caeeb4f071062d5910734f8135057", "cited_by": 87, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173206", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173206"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173206", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Brooks Davis", "Robert N. M. Watson", "Alexander Richardson", "Peter G. Neumann", "Simon W. Moore", "John Baldwin", "David Chisnall", "Jessica Clarke", "Nathaniel Wesley Filardo", "Khilan Gudka", "Alexandre Joannou", "Ben Laurie", "A. Theodore Markettos", "J. Edward Maste", "Alfredo Mazzinghi", "Edward Tomasz Napierala", "Robert M. Norton", "Michael Roe", "Peter Sewell", "Stacey D. Son", "Jonathan Woodruff"], "abstract": "The CHERI architecture allows pointers to be implemented as capabilities (rather than integer virtual addresses) in a manner that is compatible with, and strengthens, the semantics of the C language. In addition to the spatial protections offered by conventional fat pointers, CHERI capabilities offer strong integrity, enforced provenance validity, and access monotonicity. The stronger guarantees of these architectural capabilities must be reconciled with the real-world behavior of operating systems, run-time environments, and applications. When the process model, user-kernel interactions, dynamic linking, and memory management are all considered, we observe that simple derivation of architectural capabilities is insufficient to describe appropriate access to memory. We bridge this conceptual gap with a notional abstract capability that describes the accesses that should be allowed at a given point in execution, whether in the kernel or userspace. To investigate this notion at scale, we describe the first adaptation of a full C-language operating system (FreeBSD) with an enterprise database (PostgreSQL) for complete spatial and referential memory safety. We show that awareness of abstract capabilities, coupled with CHERI architectural capabilities, can provide more complete protection, strong compatibility, and acceptable performance overhead compared with the pre-CHERI baseline and software-only approaches. Our observations also have potentially significant implications for other mitigation techniques.", "doi": "10.1145/3297858.3304042", "arxiv_id": "https://doi.org/10.1145/3297858.3304042", "pmid": null, "openalex_id": null, "s2_id": "a57a50eae342694625a7866c3cae8118ac03f8d3", "cited_by": 77, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304042", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304042"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304042", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Incremental CFG patching for binary rewriting", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiaozhu Meng", "Weijie Liu"], "abstract": "Binary rewriting has been widely used in software security, software correctness assessment, performance analysis, and debugging. One approach for binary rewriting lifts the binary to IR and then regenerates a new one, which achieves near-to-zero runtime overhead, but relies on several limiting assumptions on binaries to achieve complete binary analysis to perform IR lifting. Another approach patches individual instructions without utilizing any binary analysis, which has great reliability as it does not make assumptions about the binary, but incurs prohibitive runtime overhead.", "doi": "10.1145/3445814.3446765", "arxiv_id": "https://doi.org/10.1145/3445814.3446765", "pmid": null, "openalex_id": null, "s2_id": "a5bfaed9d58e5fd99681fc5aa4c019f83e4b39ef", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446765"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446765", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Keynote: Multicore Programming", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Barbara Liskov"], "abstract": "This talk describes a new approach to implementing efficient concurrent programs that run on multicore computers. The approach is inspired by work on software transactional memory, and like that work aims to make it easier to write correct concurrent programs through the use of atomic transactions. A conventional STM tracks reads and writes of memory words, which can lead to high overhead. Our approach, called STO (software transactional objects), is based on data abstraction instead. Implementations of transactionaware datatypes can take advantage of datatype semantics to reduce bookkeeping, limit false conficts, and implement efficient concurrency control. This way we can provide both good performance and correctness based on modularity and encapsulation.", "doi": "10.1145/3297858.3304078", "arxiv_id": "https://doi.org/10.1145/3297858.3304078", "pmid": null, "openalex_id": null, "s2_id": "a6965623bc5b5106c608c7aa15d2b0b23acb588d", "cited_by": 0, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304078"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304078", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Autonomous NIC offloads", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Boris Pismenny", "Haggai Eran", "Aviad Yehezkel", "Liran Liss", "Adam Morrison", "Dan Tsafrir"], "abstract": "CPUs routinely offload to NICs network-related processing tasks like packet segmentation and checksum. NIC offloads are advantageous because they free valuable CPU cycles. But their applicability is typically limited to layer≤4 protocols (TCP and lower), and they are inapplicable to layer-5 protocols (L5Ps) that are built on top of TCP. This limitation is caused by a misfeature we call ”offload dependence,” which dictates that L5P offloading additionally requires offloading the underlying layer≤4 protocols and related functionality: TCP, IP, firewall, etc. The dependence of L5P offloading hinders innovation, because it implies hard-wiring the complicated, ever-changing implementation of the lower-level protocols. We propose ”autonomous NIC offloads,” which eliminate offload dependence. Autonomous offloads provide a lightweight software-device architecture that accelerates L5Ps without having to migrate the entire layer≤4 TCP/IP stack into the NIC. A main challenge that autonomous offloads address is coping with out-of-sequence packets. We implement autonomous offloads for two L5Ps: (i) NVMe-over-TCP zero-copy and CRC computation, and (ii) https authentication, encryption, and decryption. Our autonomous offloads increase throughput by up to 3.3x, and they deliver CPU consumption and latency that are as low as 0.4x and 0.7x, respectively. Their implementation is already upstreamed in the Linux kernel, and they will be supported in the next-generation of Mellanox NICs.", "doi": "10.1145/3445814.3446732", "arxiv_id": "https://doi.org/10.1145/3445814.3446732", "pmid": null, "openalex_id": null, "s2_id": "a6ba411842cfd3cc7ba28cc1438b8a4946b64780", "cited_by": 49, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446732"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446732", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Virtualizing FPGAs in the Cloud", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yue Zha", "Jing Li"], "abstract": "Field-Programmable Gate Arrays (FPGAs) have been integrated into the cloud infrastructure to enhance its computing performance by supporting on-demand acceleration. However, system support for FPGAs in the context of the cloud environment is still in its infancy with two major limitations, i.e., the inefficient runtime management due to the tight coupling between compilation and resource allocation, and the high programming complexity when exploiting scale-out acceleration. The root cause is that FPGA resources are not virtualized. In this paper, we propose a full-stack solution, namely ViTAL, to address the aforementioned limitations by virtualizing FPGA resources. Specifically, ViTAL provides a homogeneous abstraction to decouple the compilation and resource allocation. Applications are offline compiled onto the abstraction, while the resource allocation is dynamically determined at runtime. Enabled by a latency-insensitive communication interface, applications can be mapped flexibly onto either one FPGA or multiple FPGAs to maximize the resource utilization and the aggregated system throughput. Meanwhile, ViTAL creates an illusion of a single and large FPGA to users, thereby reducing the programming complexity and supporting scale-out acceleration. Moreover, ViTAL also provides virtualization support for peripheral components (e.g., on-board DRAM and Ethernet), as well as protection and isolation support to ensure a secure execution in the multi-user cloud environment. We evaluate ViTAL on a real system - an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (XCVU37P). The results show that, compared with the existing management method, ViTAL enables fine-grained resource sharing and reduces the response time by 82% on average (improving Quality-of-Service) with a marginal virtualization overhead. Moreover, ViTAL also reduces the response time by 25% compared to AmorphOS (operating in high-throughput mode), a recently proposed FPGA virtualization method.", "doi": "10.1145/3373376.3378491", "arxiv_id": "https://doi.org/10.1145/3373376.3378491", "pmid": null, "openalex_id": null, "s2_id": "a6e32e5ed9789fc2f14e0f70b8e81a6556a25c1c", "cited_by": 103, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378491"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378491", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PIFT: Predictive Information-Flow Tracking", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Man-Ki Yoon", "Negin Salajegheh", "Yin Chen", "Mihai Christodorescu"], "abstract": "Phones today carry sensitive information and have a great number of ways to communicate that data. As a result, malware that steal money, information, or simply disable functionality have hit the app stores. Current security solutions for preventing undesirable data leaks are mostly high-overhead and have not been practical enough for smartphones. In this paper, we show that simply monitoring just some instructions (only memory loads and stores) it is possible to achieve low overhead, highly accurate information flow tracking. Our method achieves 98% accuracy (0% false positive and 2% false negative) over DroidBench and was able to successfully catch seven real-world malware instances that steal phone number, location, and device ID using SMS messages and HTTP connections.", "doi": "10.1145/2872362.2872403", "arxiv_id": "https://doi.org/10.1145/2872362.2872403", "pmid": null, "openalex_id": null, "s2_id": "a731b88739279e402979f8635677c69f9b3a7a31", "cited_by": 12, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872403"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872403", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Analyzing Behavior Specialized Acceleration", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tony Nowatzki", "Karthikeyan Sankaralingam"], "abstract": "Hardware specialization has become a promising paradigm for overcoming the inefficiencies of general purpose microprocessors. Of significant interest are Behavioral Specialized Accelerators (BSAs), which are designed to efficiently execute code with only certain properties, but remain largely configurable or programmable. The most important strength of BSAs -- their ability to target a wide variety of codes -- also makes their interactions and analysis complex, raising the following questions: can multiple BSAs be composed synergistically, what are their interactions with the general purpose core, and what combinations favor which workloads? From a methodological standpoint, BSAs are also challenging, as they each require ISA development, compiler and assembler extensions, and either simulator or RTL models.", "doi": "10.1145/2872362.2872412", "arxiv_id": "https://doi.org/10.1145/2872362.2872412", "pmid": null, "openalex_id": null, "s2_id": "a73d474a2c4e28a08553b4e27068b5e76004060d", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872412"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872412", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Case for Lease-Based, Utilitarian Resource Management on Mobile Devices", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yigong Hu", "Suyi Liu", "Peng Huang"], "abstract": "Mobile apps have become indispensable in our daily lives, but many apps are not designed to be energy-aware that they may consume the constrained resources on mobile devices in a wasteful manner. Blindly throttling heavy resource usage, while helps reducing energy consumption, prohibits apps from taking advantages of the resources to do useful work. We argue that addressing this issue requires mobile OS to continuously assess if a resource is still truly needed even after it is granted to an app.", "doi": "10.1145/3297858.3304057", "arxiv_id": "https://doi.org/10.1145/3297858.3304057", "pmid": null, "openalex_id": null, "s2_id": "a7d670d748c648f21bfebb060ddf7c8a6ee786a1", "cited_by": 4, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304057&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304057"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304057", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A hierarchical neural model of data prefetching", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhan Shi", "Akanksha Jain", "Kevin Swersky", "Milad Hashemi", "Parthasarathy Ranganathan", "Calvin Lin"], "abstract": "This paper presents Voyager, a novel neural network for data prefetching. Unlike previous neural models for prefetching, which are limited to learning delta correlations, our model can also learn address correlations, which are important for prefetching irregular sequences of memory accesses. The key to our solution is its hierarchical structure that separates addresses into pages and offsets and that introduces a mechanism for learning important relations among pages and offsets. Voyager provides significant prediction benefits over current data prefetchers. For a set of irregular programs from the SPEC 2006 and GAP benchmark suites, Voyager sees an average IPC improvement of 41.6% over a system with no prefetcher, compared with 21.7% and 28.2%, respectively, for idealized Domino and ISB prefetchers. We also find that for two commercial workloads for which current data prefetchers see very little benefit, Voyager dramatically improves both accuracy and coverage. At present, slow training and prediction preclude neural models from being practically used in hardware, but Voyager’s overheads are significantly lower—in every dimension—than those of previous neural models. For example, computation cost is reduced by 15- 20×, and storage overhead is reduced by 110-200×. Thus, Voyager represents a significant step towards a practical neural prefetcher.", "doi": "10.1145/3445814.3446752", "arxiv_id": "https://doi.org/10.1145/3445814.3446752", "pmid": null, "openalex_id": null, "s2_id": "a8322ff8259c5d1440b80e6d35b51ea86a5b23f6", "cited_by": 122, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446752"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446752", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Breaking the Boundaries in Heterogeneous-ISA Datacenters", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Antonio Barbalace", "Robert Lyerly", "Christopher Jelesnianski", "Anthony Carno", "Ho-Ren Chuang", "Vincent Legout", "Binoy Ravindran"], "abstract": "Energy efficiency is one of the most important design considerations in running modern datacenters. Datacenter operating systems rely on software techniques such as execution migration to achieve energy efficiency across pools of machines. Execution migration is possible in datacenters today because they consist mainly of homogeneous-ISA machines. However, recent market trends indicate that alternate ISAs such as ARM and PowerPC are pushing into the datacenter, meaning current execution migration techniques are no longer applicable. How can execution migration be applied in future heterogeneous-ISA datacenters?", "doi": "10.1145/3037697.3037738", "arxiv_id": "https://doi.org/10.1145/3037697.3037738", "pmid": null, "openalex_id": null, "s2_id": "a8625449ae98db054c998f6dab3356b1c43e074c", "cited_by": 87, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037738"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037738", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Egalito: Layout-Agnostic Binary Recompilation", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["David Williams-King", "Hidenori Kobayashi", "Kent Williams-King", "Graham Patterson", "Frank Spano", "Yu Jian Wu", "Junfeng Yang", "Vasileios P. Kemerlis"], "abstract": "For comprehensive analysis of all executable code, and fast turn-around time for transformations, it is essential to operate directly on binaries to enable profiling, security hardening, and architectural adaptation. Disassembling binaries is difficult, and prior work relies on a process virtual machine to translate references on the fly or inefficient binary code patching. Our Egalito recompiler leverages metadata present in current stripped x86_64 and ARM64 binaries to generate a complete disassembly, and allows arbitrary modifications that may affect program layout without any constraints from the original binary. We utilize our own layout-agnostic intermediate representation, which is low-level enough to make the regeneration of output code predictable, yet supports a dual high-level representation for sophisticated analysis. We demonstrate nine binary tools including a novel continuous code randomization technique where Egalito transforms itself, and software emulation of the control-flow integrity in upcoming hardware. We evaluated Egalito on a large set of Debian packages, completely analyzing 99.9% of a selection of 867 executables and libraries; a majority of 149 applicable Debian packages pass all tests under Egalito. On SPEC CPU 2006, thanks to our binary optimizations, Egalito actually observes a 1.7% performance speedup.", "doi": "10.1145/3373376.3378470", "arxiv_id": "https://doi.org/10.1145/3373376.3378470", "pmid": null, "openalex_id": null, "s2_id": "a86433916738af975c42f44c53a23c82b69e9869", "cited_by": 121, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378470", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378470"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378470", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FlatFlash: Exploiting the Byte-Accessibility of SSDs within a Unified Memory-Storage Hierarchy", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ahmed H. M. O. Abulila", "Vikram Sharma Mailthody", "Zaid Qureshi", "Jian Huang", "Nam Sung Kim", "Jinjun Xiong", "Wen-Mei W. Hwu"], "abstract": "Using flash-based solid state drives (SSDs) as main memory has been proposed as a practical solution towards scaling memory capacity for data-intensive applications. However, almost all existing approaches rely on the paging mechanism to move data between SSDs and host DRAM. This inevitably incurs significant performance overhead and extra I/O traffic. Thanks to the byte-addressability supported by the PCIe interconnect and the internal memory in SSD controllers, it is feasible to access SSDs in both byte and block granularity today. Exploiting the benefits of SSD's byte-accessibility in today's memory-storage hierarchy is, however, challenging as it lacks systems support and abstractions for programs. In this paper, we present FlatFlash, an optimized unified memory-storage hierarchy, to efficiently use byte-addressable SSD as part of the main memory. We extend the virtual memory management to provide a unified memory interface so that programs can access data across SSD and DRAM in byte granularity seamlessly. We propose a lightweight, adaptive page promotion mechanism between SSD and DRAM to gain benefits from both the byte-addressable large SSD and fast DRAM concurrently and transparently, while avoiding unnecessary page movements. Furthermore, we propose an abstraction of byte-granular data persistence to exploit the persistence nature of SSDs, upon which we rethink the design primitives of crash consistency of several representative software systems that require data persistence, such as file systems and databases. Our evaluation with a variety of applications demonstrates that, compared to the current unified memory-storage systems, FlatFlash improves the performance for memory-intensive applications by up to 2.3x, reduces the tail latency for latency-critical applications by up to 2.8x, scales the throughput for transactional database by up to 3.0x, and decreases the meta-data persistence overhead for file systems by up to 18.9x. FlatFlash also improves the cost-effectiveness by up to 3.8x compared to DRAM-only systems, while enhancing the SSD lifetime significantly.", "doi": "10.1145/3297858.3304061", "arxiv_id": "https://doi.org/10.1145/3297858.3304061", "pmid": null, "openalex_id": null, "s2_id": "a8873e42327e97f4eb6abbc1fca0158b523fed2d", "cited_by": 80, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304061&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304061"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304061", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amro Awad", "Pratyusa K. Manadhata", "Stuart Haber", "Yan Solihin", "William G. Horne"], "abstract": "As non-volatile memory (NVM) technologies are expected to replace DRAM in the near future, new challenges have emerged. For example, NVMs have slow and power-consuming writes, and limited write endurance. In addition, NVMs have a data remanence vulnerability, i.e., they retain data for a long time after being powered off. NVM encryption alleviates the vulnerability, but exacerbates the limited endurance by increasing the number of writes to memory. We observe that, in current systems, a large percentage of main memory writes result from data shredding in operating systems, a process of zeroing out physical pages before mapping them to new processes, in order to protect previous processes' data. In this paper, we propose Silent Shredder, which repurposes initialization vectors used in standard counter mode encryption to completely eliminate the data shredding writes. Silent Shredder also speeds up reading shredded cache lines, and hence reduces power consumption and improves overall performance. To evaluate our design, we run three PowerGraph applications and 26 multi-programmed workloads from the SPEC 2006 suite, on a gem5-based full system simulator. Silent Shredder eliminates an average of 48.6% of the writes in the initialization and graph construction phases. It speeds up main memory reads by 3.3 times, and improves the number of instructions per cycle (IPC) by 6.4% on average. Finally, we discuss several use cases, including virtual machines' data isolation and user-level large data initialization, where Silent Shredder can be used effectively at no extra cost.", "doi": "10.1145/2872362.2872377", "arxiv_id": "https://doi.org/10.1145/2872362.2872377", "pmid": null, "openalex_id": null, "s2_id": "a898a5d319fcffd5a304abaf47432be5dfc52c2d", "cited_by": 105, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872377"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872377", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Keynote Address I", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252390", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "a9fbe456be53580b04bf830f969a8e2b44081650", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3296957", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "aa0636eaf3958632376cfa29ec546c31ec8641d2", "cited_by": 1, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fast, flexible, and comprehensive bug detection for persistent memory programs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bang Di", "Jiawen Liu", "Hao Chen", "Dong Li"], "abstract": "Debugging persistent memory (PM) programs faces a fundamental tradeoff between performance overhead and bug coverage (comprehensiveness). Large performance overhead or limited bug coverage makes debugging infeasible or ineffective for PM programs. We present PMDebugger, a debugger that detects crash consistency bugs in PM programs. Unlike prior work, PMDebugger is fast, flexible and comprehensive. The design of PMDebugger is driven by a characterization that shows how three fundamental operations in PM programs (store, cache writeback and fence) typically occur in PM programs. PMDebugger uses a hierarchical design composed of PM debugging-specific data structures, operations and bug-detection algorithms (rules). We generalize nine rules to detect crash-consistency bugs for various PM persistency models. Compared with a state-of-the-art detector (XFDetector) and an industry-quality detector (Pmemcheck), PMDebugger leads to 49.3x and 3.4x speedup on average. Compared with another state-of-the-art detector (PMTest) optimized for high performance, PMDebugger achieves comparable performance (within a factor of 2), without heavily relying on programmer annotations, and detects 38 more bugs on ten applications. PMDebugger also identifies more bugs than XFDetector and Pmemcheck. PMDebugger detects 19 new bugs in a real application (memcached) and two new bugs from Intel PMDK.", "doi": "10.1145/3445814.3446744", "arxiv_id": "https://doi.org/10.1145/3445814.3446744", "pmid": null, "openalex_id": null, "s2_id": "aa3aa1b51e58c5cd59da6fcc90b57ac8859ca2a5", "cited_by": 51, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446744"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446744", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Filtering Translation Bandwidth with Virtual Caching", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hongil Yoon", "Jason Lowe-Power", "Gurindar S. Sohi"], "abstract": "Heterogeneous computing with GPUs integrated on the same chip as CPUs is ubiquitous, and to increase programmability many of these systems support virtual address accesses from GPU hardware. However, this entails address translation on every memory access. We observe that future GPUs and workloads show very high bandwidth demands (up to 4 accesses per cycle in some cases) for shared address translation hardware due to frequent private TLB misses. This greatly impacts performance (32% average performance degradation relative to an ideal MMU). To mitigate this overhead, we propose a software-agnostic, practical, GPU virtual cache hierarchy. We use the virtual cache hierarchy as an effective address translation bandwidth filter. We observe many requests that miss in private TLBs find corresponding valid data in the GPU cache hierarchy. With a GPU virtual cache hierarchy, these TLB misses can be filtered (i.e., virtual cache hits), significantly reducing bandwidth demands for the shared address translation hardware. In addition, accelerator-specific attributes (e.g., less likelihood of synonyms) of GPUs reduce the design complexity of virtual caches, making a whole virtual cache hierarchy (including a shared L2 cache) practical for GPUs. Our evaluation shows that the entire GPU virtual cache hierarchy effectively filters the high address translation bandwidth, achieving almost the same performance as an ideal MMU. We also evaluate L1-only virtual cache designs and show that using a whole virtual cache hierarchy obtains additional performance benefits (1.31× speedup on average).", "doi": "10.1145/3173162.3173195", "arxiv_id": "https://doi.org/10.1145/3173162.3173195", "pmid": null, "openalex_id": null, "s2_id": "ab0fe590b7b7c90e58ff2edb3fde18ca5ebc678a", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173195", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173195"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173195", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "High-density Multi-tenant Bare-metal Cloud", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiantao Zhang", "Xiao Zheng", "Zhi Wang", "Hang Yang", "Yibin Shen", "Xin Long"], "abstract": "Virtualization is the cornerstone of the infrastructure-as-a-service (IaaS) cloud, where VMs from multiple tenants share a single physical server. This increases the utilization of data-center servers, allowing cloud providers to provide cost-efficient services. However, the multi-tenant nature of this service leads to serious security concerns, especially in regard to side-channel attacks. In addition, virtualization incurs non-negligible overhead in the performance of CPU, memory, and I/O. To this end, the bare-metal cloud has become an emerging type of service in the public clouds, where a cloud user can rent dedicated physical servers. The bare-metal cloud provides users with strong isolation, full and direct access to the hardware, and more predicable performance. However, the existing single-tenant bare-metal service has poor scalability, low cost efficiency, and weak adaptability because it can only lease entire physical servers to users and have no control over user programs after the server is leased. In this paper, we propose the design of a new high-density multi-tenant bare-metal cloud called BM-Hive. In BM-Hive, each bare-metal guest runs on its own compute board, a PCIe extension board with the dedicated CPU and memory modules. Moreover, BM-Hive features a hardware-software hybrid virtio I/O system that enables the guest to directly access the cloud network and storage services. BM-Hive can significantly improve the cost efficiency of the bare-metal service by hosting up to 16 bare-metal guests in a single physical server. In addition, BM-Hive strictly isolates the bare-metal guests at the hardware level for better security and isolation. We have deployed BM-Hive in one of the largest public cloud infrastructures. It currently serves tens of thousands of users at the same time. Our evaluation of BM-Hive demonstrates its strong performance over VMs.", "doi": "10.1145/3373376.3378507", "arxiv_id": "https://doi.org/10.1145/3373376.3378507", "pmid": null, "openalex_id": null, "s2_id": "ab1b5f0743816c8cb7188019d844ff3f7d565d9f", "cited_by": 50, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378507"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378507", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Skyway: Connecting Managed Heaps in Distributed Big Data Systems", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Khanh Nguyen", "Lu Fang", "Christian Navasca", "Guoqing Xu", "Brian Demsky", "Shan Lu"], "abstract": "Managed languages such as Java and Scala are prevalently used in development of large-scale distributed systems. Under the managed runtime, when performing data transfer across machines, a task frequently conducted in a Big Data system, the system needs to serialize a sea of objects into a byte sequence before sending them over the network. The remote node receiving the bytes then deserializes them back into objects. This process is both performance-inefficient and labor-intensive: (1) object serialization/deserialization makes heavy use of reflection, an expensive runtime operation and/or (2) serialization/deserialization functions need to be hand-written and are error-prone. This paper presents Skyway, a JVM-based technique that can directly connect managed heaps of different (local or remote) JVM processes. Under Skyway, objects in the source heap can be directly written into a remote heap without changing their formats. Skyway provides performance benefits to any JVM-based system by completely eliminating the need (1) of invoking serialization/deserialization functions, thus saving CPU time, and (2) of requiring developers to hand-write serialization functions.", "doi": "10.1145/3173162.3173200", "arxiv_id": "https://doi.org/10.1145/3173162.3173200", "pmid": null, "openalex_id": null, "s2_id": "ab69f4e972fedaa94572d21547caa88f736e1e8e", "cited_by": 52, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173200", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173200"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173200", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Debugging Support for Pattern-Matching Languages and Accelerators", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Matthew Casias", "Kevin Angstadt", "Tommy Tracy II", "Kevin Skadron", "Westley Weimer"], "abstract": "Programs written for hardware accelerators can often be difficult to debug. Without adequate tool support, program maintenance tasks such as fault localization and debugging can be particularly challenging. In this work, we focus on supporting hardware that is specialized for finite automata processing, a computational paradigm that has accelerated pattern-matching applications across a diverse set of problem domains. While commodity hardware enables high-throughput data analysis, direct interactive debugging (e.g., single-stepping) is not currently supported. We propose a debugging approach for existing commodity hardware that supports step-through debugging and variable inspection of user-written automata processing programs. We focus on programs written in RAPID, a domain-specific language for pattern-matching applications. We develop a prototype of our approach for both Xilinx FPGAs and Micron's Automata Processor that supports simultaneous high-speed processing of data and interactive debugging without requiring modifications to the underlying hardware. Our empirical evaluation demonstrates low clock overheads for our approach across thirteen applications in the ANMLZoo automata processing benchmark suite on FPGAs. Additionally, we evaluate our technique through a human study involving over 60 participants and 20 buggy segments of code. Our generated debugging information increases fault localization accuracy by 22%, or 10 percentage points, in a statistically significant manner (p=0.013).", "doi": "10.1145/3297858.3304066", "arxiv_id": "https://doi.org/10.1145/3297858.3304066", "pmid": null, "openalex_id": null, "s2_id": "ab8fe18142a03f2e83b9d11c9600808396b2dbdb", "cited_by": 15, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304066", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304066"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304066", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "KLOCs: kernel-level object contexts for heterogeneous memory systems", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sudarsun Kannan", "Yujie Ren", "Abhishek Bhattacharjee"], "abstract": "Heterogeneous memory systems promise better performance, energy-efficiency, and cost trade-offs in emerging systems. But delivering on this promise requires efficient OS mechanisms and policies for data tiering and migration. Unfortunately, modern OSes are lacking inefficient support for data tiering. While this problem is known for application data, the question of how best to manage kernel objects for filesystems and networking---i.e., inodes, dentry caches, journal blocks, socket buffers, etc.---has largely been ignored and presents a performance challenge for I/O-intensive workloads. We quantify the scale of this challenge and introduce a new OS abstraction, kernel-level object contexts (KLOCs), to enable efficient tiering of kernel objects. We use KLOCs to identify and group kernel objects with similar hotness, reuse, and liveness, and demonstrate their use in data placement and migration across several heterogeneous memory system configurations, including Intel’s Optane systems. Performance evaluations using RocksDB, Redis, Cassandra, and Spark show that KLOCs enable up to 2.7× higher system throughput versus prior art.", "doi": "10.1145/3445814.3446745", "arxiv_id": "https://doi.org/10.1145/3445814.3446745", "pmid": null, "openalex_id": null, "s2_id": "ab9d3a5275be66822021e3f78a44385d41d56afb", "cited_by": 29, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446745"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446745", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, Atlanta, GA, USA, April 2-6, 2016", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/2980024", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "abffdb7e81095c18cd9dc6d63dd1ed46e9a59c9d", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dimitrios Skarlatos", "Apostolos Kokolis", "Tianyin Xu", "Josep Torrellas"], "abstract": "The unprecedented growth in the memory needs of emerging memory-intensive workloads has made virtual memory translation a major performance bottleneck. To address this problem, this paper introduces Elastic Cuckoo Page Tables, a novel page table design that transforms the sequential pointer-chasing operation used by conventional multi-level radix page tables into fully-parallel look-ups. The resulting design harvests, for the first time, the benefits of memory level parallelism for address translation. Elastic cuckoo page tables use Elastic Cuckoo Hashing, a novel extension of cuckoo hashing that supports efficient page table resizing. Elastic cuckoo page tables efficiently resolve hash collisions, provide process-private page tables, support multiple page sizes and page sharing among processes, and dynamically adapt page table sizes to meet application requirements. We evaluate elastic cuckoo page tables with full-system simulations of an 8-core processor using a set of graph analytics, bioinformatics, HPC, and system workloads. Elastic cuckoo page tables reduce the address translation overhead by an average of 41% over conventional radix page tables. The result is a 3-18% speed-up in application execution.", "doi": "10.1145/3373376.3378493", "arxiv_id": "https://doi.org/10.1145/3373376.3378493", "pmid": null, "openalex_id": null, "s2_id": "ac1c16ea497a97c586d4df9f3b318de855727548", "cited_by": 76, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378493", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378493"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378493", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yu Ji", "Youhui Zhang", "Wenguang Chen", "Yuan Xie"], "abstract": "Different from developing neural networks (NNs) for general-purpose processors, the development for NN chips usually faces with some hardware-specific restrictions, such as limited precision of network signals and parameters, constrained computation scale, and limited types of non-linear functions. This paper proposes a general methodology to address the challenges. We decouple the NN applications from the target hardware by introducing a compiler that can transform an existing trained, unrestricted NN into an equivalent network that meets the given hardware's constraints. We propose multiple techniques to make the transformation adaptable to different kinds of NN chips, and reliable for restrict hardware constraints. We have built such a software tool that supports both spiking neural networks (SNNs) and traditional artificial neural networks (ANNs). We have demonstrated its effectiveness with a fabricated neuromorphic chip and a processing-in-memory (PIM) design. Tests show that the inference error caused by this solution is insignificant and the transformation time is much shorter than the retraining time. Also, we have studied the parameter-sensitivity evaluations to explore the tradeoffs between network error and resource utilization for different transformation strategies, which could provide insights for co-design optimization of neuromorphic hardware and software.", "doi": "10.1145/3173162.3173205", "arxiv_id": "1801.00746", "pmid": null, "openalex_id": null, "s2_id": "acb4c89238b2d307b10b11ad9319546f14f9f5af", "cited_by": 57, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173205"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173205", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Software-Defined Far Memory in Warehouse-Scale Computers", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["H. Andrés Lagar-Cavilla", "Junwhan Ahn", "Suleiman Souhlal", "Neha Agarwal", "Radoslaw Burny", "Shakeel Butt", "Jichuan Chang", "Ashwin Chaugule", "Nan Deng", "Junaid Shahid", "Greg Thelen", "Kamil Adam Yurtsever", "Yu Zhao", "Parthasarathy Ranganathan"], "abstract": "Increasing memory demand and slowdown in technology scaling pose important challenges to total cost of ownership (TCO) of warehouse-scale computers (WSCs). One promising idea to reduce the memory TCO is to add a cheaper, but slower, \"far memory\" tier and use it to store infrequently accessed (or cold) data. However, introducing a far memory tier brings new challenges around dynamically responding to workload diversity and churn, minimizing stranding of capacity, and addressing brownfield (legacy) deployments. We present a novel software-defined approach to far memory that proactively compresses cold memory pages to effectively create a far memory tier in software. Our end-to-end system design encompasses new methods to define performance service-level objectives (SLOs), a mechanism to identify cold memory pages while meeting the SLO, and our implementation in the OS kernel and node agent. Additionally, we design learning-based autotuning to periodically adapt our design to fleet-wide changes without a human in the loop. Our system has been successfully deployed across Google's WSC since 2016, serving thousands of production services. Our software-defined far memory is significantly cheaper (67% or higher memory cost reduction) at relatively good access speeds (6us) and allows us to store a significant fraction of infrequently accessed data (on average, 20%), translating to significant TCO savings at warehouse scale.", "doi": "10.1145/3297858.3304053", "arxiv_id": "https://doi.org/10.1145/3297858.3304053", "pmid": null, "openalex_id": null, "s2_id": "acc47037cb9606da2b69c1a4f495179bf05a59ff", "cited_by": 193, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304053&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304053"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304053", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DySel: Lightweight Dynamic Selection for Kernel-based Data-parallel Programming Model", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Li-Wen Chang", "Hee-Seok Kim", "Wen-mei W. Hwu"], "abstract": "The rising pressure for simultaneously improving performance and reducing power is driving more diversity into all aspects of computing devices. An algorithm that is well-matched to the target hardware can run multiple times faster and more energy efficiently than one that is not. The problem is complicated by the fact that a program's input also affects the appropriate choice of algorithm. As a result, software developers have been faced with the challenge of determining the appropriate algorithm for each potential combination of target device and data. This paper presents DySel, a novel runtime system for automating such determination for kernel-based data parallel programming models such as OpenCL, CUDA, OpenACC, and C++AMP. These programming models cover many applications that demand high performance in mobile, cloud and high-performance computing. DySel systematically deploys candidate kernels on a small portion of the actual data to determine which achieves the best performance for the hardware-data combination. The test-deployment, referred to as micro-profiling, contributes to the final execution result and incurs less than 8% of overhead in the worst observed case when compared to an oracle. We show four major use cases where DySel provides significantly more consistent performance without tedious effort from the developer.", "doi": "10.1145/2872362.2872373", "arxiv_id": "https://doi.org/10.1145/2872362.2872373", "pmid": null, "openalex_id": null, "s2_id": "addbb144d195fca7ce3852ddababfa568d3ead1c", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872373"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872373", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Optimizing Nested Virtualization Performance Using Direct Virtual Hardware", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jin Tack Lim", "Jason Nieh"], "abstract": "Nested virtualization, running virtual machines and hypervisors on top of other virtual machines and hypervisors, is increasingly important because of the need to deploy virtual machines running software stacks on top of virtualized cloud infrastructure. However, performance remains a key impediment to further adoption as application workloads can perform many times worse than native execution. To address this problem, we introduce DVH (Direct Virtual Hardware), a new approach that enables a host hypervisor, the hypervisor that runs directly on the hardware, to directly provide virtual hardware to nested virtual machines without the intervention of multiple levels of hypervisors. We introduce four DVH mechanisms, virtual-passthrough, virtual timers, virtual inter-processor interrupts, and virtual idle. DVH provides virtual hardware for these mechanisms that mimics the underlying hardware and in some cases adds new enhancements that leverage the flexibility of software without the need for matching physical hardware support. We have implemented DVH in the Linux KVM hypervisor. Our experimental results show that DVH can provide near native execution speeds and improve KVM performance by more than an order of magnitude on real application workloads.", "doi": "10.1145/3373376.3378467", "arxiv_id": "https://doi.org/10.1145/3373376.3378467", "pmid": null, "openalex_id": null, "s2_id": "af687ee53dbbfc35eeec2e6e66f37587cad9ed7d", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378467", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378467"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378467", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 7B: Heterogeneous Architectures and Accelerators II", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252407", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "af9ad392c539b2c85f092d5100720fecbf3e1504", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A full-stack search technique for domain optimized deep learning accelerators", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507767", "arxiv_id": "2105.12842", "pmid": null, "openalex_id": null, "s2_id": "afa72122ba06b6a694c21cf67d82620662e4917c", "cited_by": 62, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3503222.3507767"], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hardware Multithreaded Transactions", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jordan Fix", "Nayana P. Nagendra", "Sotiris Apostolakis", "Hansen Zhang", "Sophie Qiu", "David I. August"], "abstract": "Speculation with transactional memory systems helps pro- grammers and compilers produce profitable thread-level parallel programs. Prior work shows that supporting transactions that can span multiple threads, rather than requiring transactions be contained within a single thread, enables new types of speculative parallelization techniques for both programmers and parallelizing compilers. Unfortunately, software support for multi-threaded transactions (MTXs) comes with significant additional inter-thread communication overhead for speculation validation. This overhead can make otherwise good parallelization unprofitable for programs with sizeable read and write sets. Some programs using these prior software MTXs overcame this problem through significant efforts by expert programmers to minimize these sets and optimize communication, capabilities which compiler technology has been unable to equivalently achieve. Instead, this paper makes speculative parallelization less laborious and more feasible through low-overhead speculation validation, presenting the first complete design, implementation, and evaluation of hardware MTXs. Even with maximal speculation validation of every load and store inside transactions of tens to hundreds of millions of instructions, profitable parallelization of complex programs can be achieved. Across 8 benchmarks, this system achieves a geomean speedup of 99% over sequential execution on a multicore machine with 4 cores.", "doi": "10.1145/3173162.3173172", "arxiv_id": "https://doi.org/10.1145/3173162.3173172", "pmid": null, "openalex_id": null, "s2_id": "afbbd472d04b1c1051b70f2ec245dd9cae9d7930", "cited_by": 6, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173172", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173172"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173172", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HaRMony: Heterogeneous-Reliability Memory and QoS-Aware Energy Management on Virtualized Servers", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Konstantinos Tovletoglou", "Lev Mukhanov", "Dimitrios S. Nikolopoulos", "Georgios Karakonstantis"], "abstract": "The explosive growth of data increases the storage needs, especially within servers, making DRAM responsible for more than 40% of the total system power. Such a reality has made researchers focus on energy saving schemes that relax the pessimistic DRAM circuit parameters at the cost of potential faults. In an effort to limit the resultant risk of critical data disruption, new methods were introduced that split DRAM into domains with varying reliability and power. The benefits of such schemes may have been showcased on simulators but have neither been implemented on real systems with a complete software stack, nor have been combined with any energy-reliability OS management policies. In this paper, we are the first to implement and evaluate HaRMony, a heterogeneous-reliability memory framework, in conjunction with QoS-aware energy management policies on a server with a complete virtualization stack. HaRMony overcomes the practical restrictions stemming from default hardware specifications, which were neglected in prior works, by introducing a software-based memory interleaving scheme. Furthermore, we expose the capabilities of HaRMony to the QEMU-KVM hypervisor through two unique policies. The first policy enables the hypervisor to seek the most power efficient DRAM circuit parameters based on the server availability requested by the user. The second policy enables users to exploit the inherent application error-resiliency by allowing them to limit the error protection mechanisms and allocate data structures on variably-reliable memory domains. Our evaluation shows that HaRMony reduces the performance overhead incurred due to disabling hardware interleaving from 29.3% down to 1.1% and leads to 17.7% DRAM energy savings and 8.6% total system energy savings on average in case of native execution of 28 benchmarks on an ARMv8-based server. Finally, we demonstrate that our QoS-aware scaling governor integrated with QEMU-KVM can dynamically scale the DRAM parameters, while reducing the system energy by 8.4% and meeting the targeted QoS even under extreme temperatures.", "doi": "10.1145/3373376.3378489", "arxiv_id": "https://doi.org/10.1145/3373376.3378489", "pmid": null, "openalex_id": null, "s2_id": "afd0d496ec266f49049f95ea4e8898475004ce12", "cited_by": 14, "type": "conference", "is_oa": true, "pdf_urls": ["https://pureadmin.qub.ac.uk/ws/files/199085012/aspl1833a_tovletoglouA.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378489"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378489", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 9A: Memory II", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248630", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "afdd26c27a1c913bedeeeaa7682601c8a728add8", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DCNS: Automated Detection Of Conservative Non-Sleep Defects in the Linux Kernel", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jia-Ju Bai", "Julia Lawall", "Wende Tan", "Shi-Min Hu"], "abstract": "For waiting, the Linux kernel offers both sleep-able and non-sleep operations. However, only non-sleep operations can be used in atomic context. Detecting the possibility of execution in atomic context requires a complete inter-procedural flow analysis, often involving function pointers. Developers may thus conservatively use non-sleep operations even outside of atomic context, which may damage system performance, as such operations unproductively monopolize the CPU. Until now, no systematic approach has been proposed to detect such conservative non-sleep (CNS) defects. In this paper, we propose a practical static approach, named DCNS, to automatically detect conservative non-sleep defects in the Linux kernel. DCNS uses a summary-based analysis to effectively identify the code in atomic context and a novel file-connection-based alias analysis to correctly identify the set of functions referenced by a function pointer. We evaluate DCNS on Linux 4.16, and in total find 1629 defects. We manually check 943 defects whose call paths are not so difficult to follow, and find that 890 are real. We have randomly selected 300 of the real defects and sent them to kernel developers, and 251 have been confirmed.", "doi": "10.1145/3297858.3304065", "arxiv_id": "https://doi.org/10.1145/3297858.3304065", "pmid": null, "openalex_id": null, "s2_id": "b03c6c22c6d1b9b25a666c0ca3dc9661a5d2fbeb", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["https://inria.hal.science/hal-02389543v1/document", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304065"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304065", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Baymax: QoS Awareness and Increased Utilization for Non-Preemptive Accelerators in Warehouse Scale Computers", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Quan Chen", "Hailong Yang", "Jason Mars", "Lingjia Tang"], "abstract": "Modern warehouse-scale computers (WSCs) are being outfitted with accelerators to provide the significant compute required by emerging intelligent personal assistant (IPA) workloads such as voice recognition, image classification, and natural language processing. It is well known that the diurnal user access pattern of user-facing services provides a strong incentive to co-locate applications for better accelerator utilization and efficiency, and prior work has focused on enabling co-location on multicore processors. However, interference when co-locating applications on non-preemptive accelerators is fundamentally different than contention on multi-core CPUs and introduces a new set of challenges to reduce QoS violation. To address this open problem, we first identify the underlying causes for QoS violation in accelerator-outfitted servers. Our experiments show that queuing delay for the compute resources and PCI-e bandwidth contention for data transfer are the main two factors that contribute to the long tails of user-facing applications. We then present Baymax, a runtime system that orchestrates the execution of compute tasks from different applications and mitigates PCI-e bandwidth contention to deliver the required QoS for user-facing applications and increase the accelerator utilization. Using DjiNN, a deep neural network service, Sirius, an end-to-end IPA workload, and traditional applications on a Nvidia K40 GPU, our evaluation shows that Baymax improves the accelerator utilization by 91.3% while achieving the desired 99%-ile latency target for for user-facing applications. In fact, Baymax reduces the 99%-ile latency of user-facing applications by up to 195x over default execution.", "doi": "10.1145/2872362.2872368", "arxiv_id": "https://doi.org/10.1145/2872362.2872368", "pmid": null, "openalex_id": null, "s2_id": "b04c9e851ae605592d693aa65f0d753b8af08feb", "cited_by": 167, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872368&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872368"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872368", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 4B: Compiler Optimizations", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248621", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "b0f5fa7a90f033b97436ac0dce83be015864133f", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mingyu Gao", "Xuan Yang", "Jing Pu", "Mark Horowitz", "Christos Kozyrakis"], "abstract": "The use of increasingly larger and more complex neural networks (NNs) makes it critical to scale the capabilities and efficiency of NN accelerators. Tiled architectures provide an intuitive scaling solution that supports both coarse-grained parallelism in NNs: intra-layer parallelism, where all tiles process a single layer, and inter-layer pipelining, where multiple layers execute across tiles in a pipelined manner. This work proposes dataflow optimizations to address the shortcomings of existing parallel dataflow techniques for tiled NN accelerators. For intra-layer parallelism, we develop buffer sharing dataflow that turns the distributed buffers into an idealized shared buffer, eliminating excessive data duplication and the memory access overheads. For inter-layer pipelining, we develop alternate layer loop ordering that forwards the intermediate data in a more fine-grained and timely manner, reducing the buffer requirements and pipeline delays. We also make inter-layer pipelining applicable to NNs with complex DAG structures. These optimizations improve the performance of tiled NN accelerators by 2x and reduce their energy consumption by 45% across a wide range of NNs. The effectiveness of our optimizations also increases with the NN size and complexity.", "doi": "10.1145/3297858.3304014", "arxiv_id": "https://doi.org/10.1145/3297858.3304014", "pmid": null, "openalex_id": null, "s2_id": "b1051e81e527d841f0936c604aa6966c719e876d", "cited_by": 228, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304014", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304014"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304014", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Capuchin: Tensor-based GPU Memory Management for Deep Learning", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xuan Peng", "Xuanhua Shi", "Hulin Dai", "Hai Jin", "Weiliang Ma", "Qian Xiong", "Fan Yang", "Xuehai Qian"], "abstract": "In recent years, deep learning has gained unprecedented success in various domains, the key of the success is the larger and deeper deep neural networks (DNNs) that achieved very high accuracy. On the other side, since GPU global memory is a scarce resource, large models also pose a significant challenge due to memory requirement in the training process. This restriction limits the DNN architecture exploration flexibility. In this paper, we propose Capuchin, a tensor-based GPU memory management module that reduces the memory footprint via tensor eviction/prefetching and recomputation. The key feature of Capuchin is that it makes memory management decisions based on dynamic tensor access pattern tracked at runtime. This design is motivated by the observation that the access pattern to tensors is regular during training iterations. Based on the identified patterns, one can exploit the total memory optimization space and offer the fine-grain and flexible control of when and how to perform memory optimization techniques. We deploy Capuchin in a widely-used deep learning framework, Tensorflow, and show that Capuchin can reduce the memory footprint by up to 85% among 6 state-of-the-art DNNs compared to the original Tensorflow. Especially, for the NLP task BERT, the maximum batch size that Capuchin can outperforms Tensorflow and gradient-checkpointing by 7x and 2.1x, respectively. We also show that Capuchin outperforms vDNN and gradient-checkpointing by up to 286% and 55% under the same memory oversubscription.", "doi": "10.1145/3373376.3378505", "arxiv_id": "https://doi.org/10.1145/3373376.3378505", "pmid": null, "openalex_id": null, "s2_id": "b11c87681ee46ab8c82bf96d97f958bd95b8f0a8", "cited_by": 212, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378505"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378505", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Minotaur: Adapting Software Testing Techniques for Hardware Errors", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Abdulrahman Mahmoud", "Radha Venkatagiri", "Khalique Ahmed", "Sasa Misailovic", "Darko Marinov", "Christopher W. Fletcher", "Sarita V. Adve"], "abstract": "With the end of conventional CMOS scaling, efficient resiliency solutions are needed to address the increased likelihood of hardware errors. Silent data corruptions (SDCs) are especially harmful because they can create unacceptable output without the user's knowledge. Several resiliency analysis techniques have been proposed to identify SDC-causing instructions, but they remain too slow for practical use and/or sacrifice accuracy to improve analysis speed. We develop Minotaur, a novel toolkit to improve the speed and accuracy of resiliency analysis. The key insight behind Minotaur is that modern resiliency analysis has many conceptual similarities to software testing; therefore, adapting techniques from the rich software testing literature can lead to principled and significant improvements in resiliency analysis. Minotaur identifies and adapts four concepts from software testing: 1) it introduces the concept of input quality criteria for resiliency analysis and identifies PC coverage as a simple but effective criterion; 2) it creates (fast) minimized inputs from (slow) standard benchmark inputs, using the input quality criteria to assess the goodness of the created input; 3) it adapts the concept of test case prioritization to prioritize error injections and invoke early termination for a given instruction to speed up error-injection campaigns; and 4) it further adapts test case or input prioritization to accelerate SDC discovery across multiple inputs. We evaluate Minotaur by applying it to Approxilyzer, a state-of-the-art resiliency analysis tool. Minotaur's first three techniques speed up Approxilyzer's resiliency analysis by 10.3X (on average) for the workloads studied. Moreover, they identify 96% (on average) of all SDC-causing instructions explored, compared to 64% identified by Approxilyzer alone. Minotaur's fourth technique (input prioritization) enables identifying all SDC-causing instructions explored across multiple inputs at a speed 2.3X faster (on average) than analyzing each input independently for our workloads.", "doi": "10.1145/3297858.3304050", "arxiv_id": "https://doi.org/10.1145/3297858.3304050", "pmid": null, "openalex_id": null, "s2_id": "b13ae697608b11b9cf25510a22d5419508573f9a", "cited_by": 25, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304050", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304050"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304050", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Sego: Pervasive Trusted Metadata for Efficiently Verified Untrusted System Services", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Youngjin Kwon", "Alan M. Dunn", "Michael Z. Lee", "Owen S. Hofmann", "Yuanzhong Xu", "Emmett Witchel"], "abstract": "Sego is a hypervisor-based system that gives strong privacy and integrity guarantees to trusted applications, even when the guest operating system is compromised or hostile. Sego verifies operating system services, like the file system, instead of replacing them. By associating trusted metadata with user data across all system devices, Sego verifies system services more efficiently than previous systems, especially services that depend on data contents. We extensively evaluate Sego's performance on real workloads and implement a kernel fault injector to validate Sego's file system-agnostic crash consistency and recovery protocol.", "doi": "10.1145/2872362.2872372", "arxiv_id": "https://doi.org/10.1145/2872362.2872372", "pmid": null, "openalex_id": null, "s2_id": "b1c857a3be72dbee8589caff860f32c88a153721", "cited_by": 43, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872372", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872372"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872372", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FirmUp: Precise Static Detection of Common Vulnerabilities in Firmware", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yaniv David", "Nimrod Partush", "Eran Yahav"], "abstract": "We present a static, precise, and scalable technique for finding CVEs (Common Vulnerabilities and Exposures) in stripped firmware images. Our technique is able to efficiently find vulnerabilities in real-world firmware with high accuracy. Given a vulnerable procedure in an executable binary and a firmware image containing multiple stripped binaries, our goal is to detect possible occurrences of the vulnerable procedure in the firmware image. Due to the variety of architectures and unique tool chains used by vendors, as well as the highly customized nature of firmware, identifying procedures in stripped firmware is extremely challenging. Vulnerability detection requires not only pairwise similarity between procedures but also information about the relationships between procedures in the surrounding executable. This observation serves as the foundation for a novel technique that establishes a partial correspondence between procedures in the two binaries. We implemented our technique in a tool called FirmUp and performed an extensive evaluation over 40 million procedures, over 4 different prevalent architectures, crawled from public vendor firmware images. We discovered 373 vulnerabilities affecting publicly available firmware, 147 of them in the latest available firmware version for the device. A thorough comparison of FirmUp to previous methods shows that it accurately and effectively finds vulnerabilities in firmware, while outperforming the detection rate of the state of the art by 45% on average.", "doi": "10.1145/3173162.3177157", "arxiv_id": "https://doi.org/10.1145/3173162.3177157", "pmid": null, "openalex_id": null, "s2_id": "b1ef9380982946089b7d619af1fc0555e2209110", "cited_by": 143, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177157"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177157", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Who’s debugging the debuggers? exposing debug information bugs in optimized binaries", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Giuseppe Antonio Di Luna", "Davide Italiano", "Luca Massarelli", "Sebastian Österlund", "Cristiano Giuffrida", "Leonardo Querzoni"], "abstract": "Despite the advancements in software testing, bugs still plague deployed software and result in crashes in production. When debugging issues —sometimes caused by “heisenbugs”— there is the need to interpret core dumps and reproduce the issue offline on the same binary deployed. This requires the entire toolchain (compiler, linker, debugger) to correctly generate and use debug information. Little attention has been devoted to checking that such information is correctly preserved by modern toolchains’ optimization stages. This is particularly important as managing debug information in optimized production binaries is non-trivial, often leading to toolchain bugs that may hinder post-deployment debugging efforts.", "doi": "10.1145/3445814.3446695", "arxiv_id": "2011.13994", "pmid": null, "openalex_id": null, "s2_id": "b2275c78092cb86975a44a8d6a8f067f64f054ff", "cited_by": 30, "type": "conference", "is_oa": true, "pdf_urls": ["https://research.vu.nl/en/publications/401d8159-b60b-4d84-88e3-b89dd3df4444", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446695"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446695", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Replica: A Wireless Manycore for Communication-Intensive and Approximate Data", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Vimuth Fernando", "Antonio Franques", "Sergi Abadal", "Sasa Misailovic", "Josep Torrellas"], "abstract": "Data access patterns that involve fine-grained sharing, multicasts, or reductions have proved to be hard to scale in shared-memory platforms. Recently, wireless on-chip communication has been proposed as a solution to this problem, but a previous architecture has used it only to speed-up synchronization. An intriguing question is whether wireless communication can be widely effective for ordinary shared data. This paper presents Replica, a manycore that uses wireless communication for communication-intensive ordinary data. To deliver high performance, Replica supports an adaptive wireless protocol and selective message dropping. We describe the computational patterns that leverage wireless communication, programming techniques to restructure applications, and tools that help with automation. Our results show that wireless communication is effective for ordinary data. For 64 cores, Replica obtains a mean speed-up of 1.76x over a conventional machine. The mean speed-up reaches 1.89x if approximate-computing transformations are enabled. The average energy consumption is substantially reduced by 34% (or 38% with approximate transformations), and the area increases only modestly.", "doi": "10.1145/3297858.3304033", "arxiv_id": "https://doi.org/10.1145/3297858.3304033", "pmid": null, "openalex_id": null, "s2_id": "b36dbcc85a3a8fbd2b767ea27f712a3d988b5c6c", "cited_by": 34, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304033", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304033"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304033", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Phoenix: A Substrate for Resilient Distributed Graph Analytics", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Roshan Dathathri", "Gurbinder Gill", "Loc Hoang", "Keshav Pingali"], "abstract": "This paper presents Phoenix, a communication and synchronization substrate that implements a novel protocol for recovering from fail-stop faults when executing graph analytics applications on distributed-memory machines. The standard recovery technique in this space is checkpointing, which rolls back the state of the entire computation to a state that existed before the fault occurred. The insight behind Phoenix is that this is not necessary since it is sufficient to continue the computation from a state that will ultimately produce the correct result. We show that for graph analytics applications, the necessary state adjustment can be specified easily by the programmer using a thin API supported by Phoenix. Phoenix has no observable overhead during fault-free execution, and it is resilient to any number of faults while guaranteeing that the correct answer will be produced at the end of the computation. This is in contrast to other systems in this space which may either have overheads even during fault-free execution or produce only approximate answers when faults occur during execution. We incorporated Phoenix into D-Galois, the state-of-the-art distributed graph analytics system, and evaluated it on two production clusters. Our evaluation shows that in the absence of faults, Phoenix is ~24x faster than GraphX, which provides fault tolerance using the Spark system. Phoenix also outperforms the traditional checkpoint-restart technique implemented in D-Galois: in fault-free execution, Phoenix has no observable overhead, while the checkpointing technique has 31% overhead. Furthermore, Phoenix mostly outperforms checkpointing when faults occur, particularly in the common case when only a small number of hosts fail simultaneously.", "doi": "10.1145/3297858.3304056", "arxiv_id": "https://doi.org/10.1145/3297858.3304056", "pmid": null, "openalex_id": null, "s2_id": "b374376d616eb89255a86fc6ec360b09273243a2", "cited_by": 12, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304056", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304056"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304056", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 3B: Verification and Testing", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248619", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "b3c17800b02fc9522b7323f675989a8ae801d508", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 2A: Memory Management", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252393", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "b56448e5c882488e3cbd65a262fa2b88853e6422", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Failure-Atomic Slotted Paging for Persistent Memory", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jihye Seo", "Wook-Hee Kim", "Woongki Baek", "Beomseok Nam", "Sam H. Noh"], "abstract": "The slotted-page structure is a database page format commonly used for managing variable-length records. In this work, we develop a novel \"failure-atomic slotted page structure\" for persistent memory that leverages byte addressability and durability of persistent memory to minimize redundant write operations used to maintain consistency in traditional database systems. Failure-atomic slotted paging consists of two key elements: (i) in-place commit per page using hardware transactional memory and (ii) slot header logging that logs the commit mark of each page. The proposed scheme is implemented in SQLite and compared against NVWAL, the current state-of-the-art scheme. Our performance study shows that our failure-atomic slotted paging shows optimal performance for database transactions that insert a single record. For transactions that touch more than one database page, our proposed slot-header logging scheme minimizes the logging overhead by avoiding duplicating pages and logging only the metadata of the dirty pages. Overall, we find that our failure-atomic slotted-page management scheme reduces database logging overhead to 1/6 and improves query response time by up to 33% compared to NVWAL.", "doi": "10.1145/3037697.3037737", "arxiv_id": "https://doi.org/10.1145/3037697.3037737", "pmid": null, "openalex_id": null, "s2_id": "b5c4050b086aa5ce350d0cf23359ac03ada4f268", "cited_by": 53, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037737"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037737", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "AvA: Accelerated Virtualization of Accelerators", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Hangchen Yu", "Arthur Michener Peters", "Amogh Akshintala", "Christopher J. Rossbach"], "abstract": "Applications are migrating en masse to the cloud, while accelerators such as GPUs, TPUs, and FPGAs proliferate in the wake of Moore's Law. These trends are in conflict: cloud applications run on virtual platforms, but existing virtualization techniques have not provided production-ready solutions for accelerators. As a result, cloud providers expose accelerators by dedicating physical devices to individual guests. Multi-tenancy and consolidation are lost as a consequence. We present AvA, which addresses limitations of existing virtualization techniques with automated construction of hypervisor-managed virtual accelerator stacks. AvA combines a DSL for describing APIs and sharing policies, device-agnostic runtime components, and a compiler to generate accelerator-specific components such as guest libraries and API servers. AvA uses Hypervisor Interposed Remote Acceleration (HIRA), a new technique to enable hypervisor-enforcement of sharing policies from the specification. We use AvA to virtualize nine accelerators and eleven framework APIs, including six for which no virtualization support has been previously explored. AvA provides near-native performance and can enforce sharing policies that are not possible with current techniques, with orders of magnitude less developer effort than required for hand-built virtualization support.", "doi": "10.1145/3373376.3378466", "arxiv_id": "https://doi.org/10.1145/3373376.3378466", "pmid": null, "openalex_id": null, "s2_id": "b611f54f40f00f143cd01cbae77dfeabb8851b9e", "cited_by": 47, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378466", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378466"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378466", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FlexOS: towards flexible OS isolation", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507759", "arxiv_id": "2112.06566", "pmid": null, "openalex_id": null, "s2_id": "b68fd339f76ddb74d1205f8c54e0c87ae0a9c98c", "cited_by": 43, "type": null, "is_oa": true, "pdf_urls": ["https://pure.manchester.ac.uk/ws/files/223871041/paper.pdf"], "github": ["https://github.com/ukflexos/asplos22-ae", "https://github.com/project-flexos/asplos22-ae"], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Perspective: A Sensible Approach to Speculative Automatic Parallelization", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sotiris Apostolakis", "Ziyang Xu", "Greg Chan", "Simone Campanoni", "David I. August"], "abstract": "The promise of automatic parallelization, freeing programmers from the error-prone and time-consuming process of making efficient use of parallel processing resources, remains unrealized. For decades, the imprecision of memory analysis limited the applicability of non-speculative automatic parallelization. The introduction of speculative automatic parallelization overcame these applicability limitations, but, even in the case of no misspeculation, these speculative techniques exhibit high communication and bookkeeping costs for validation and commit. This paper presents Perspective, a speculative-DOALL parallelization framework that maintains the applicability of speculative techniques while approaching the efficiency of non-speculative ones. Unlike current approaches which subsequently apply speculative techniques to overcome the imprecision of memory analysis, Perspective combines a novel speculation-aware memory analyzer, new efficient speculative privatization methods, and a planning phase to select a minimal-cost set of parallelization-enabling transforms. By reducing speculative parallelization overheads in ways not possible with prior parallelization systems, Perspective obtains higher overall program speedup (23.0x for 12 general-purpose C/C++ programs running on a 28-core shared-memory commodity machine) than Privateer (11.5x), the prior automatic DOALL parallelization system with the highest applicability.", "doi": "10.1145/3373376.3378458", "arxiv_id": "https://doi.org/10.1145/3373376.3378458", "pmid": null, "openalex_id": null, "s2_id": "b6d75f3c326860d3dbde6b949393ee76e9be6b49", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378458", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378458"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378458", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Neural architecture search as program transformation exploration", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jack Turner", "Elliot J. Crowley", "Michael F. P. O'Boyle"], "abstract": "Improving the performance of deep neural networks (DNNs) is important to both the compiler and neural architecture search (NAS) communities. Compilers apply program transformations in order to exploit hardware parallelism and memory hierarchy. However, legality concerns mean they fail to exploit the natural robustness of neural networks. In contrast, NAS techniques mutate networks by operations such as the grouping or bottlenecking of convolutions, exploiting the resilience of DNNs. In this work, we express such neural architecture operations as program transformations whose legality depends on a notion of representational capacity. This allows them to be combined with existing transformations into a unified optimization framework. This unification allows us to express existing NAS operations as combinations of simpler transformations. Crucially, it allows us to generate and explore new tensor convolutions. We prototyped the combined framework in TVM and were able to find optimizations across different DNNs, that significantly reduce inference time - over 3× in the majority of cases. Furthermore, our scheme dramatically reduces NAS search time.", "doi": "10.1145/3445814.3446753", "arxiv_id": "2102.06599", "pmid": null, "openalex_id": null, "s2_id": "b7409969d94ba1e7c96f0abeb6f5bc1bb4319bb2", "cited_by": 23, "type": "conference", "is_oa": true, "pdf_urls": ["https://www.research.ed.ac.uk/en/publications/811a48c7-2300-4c22-bbeb-e2452188e33d", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446753"], "github": ["https://github.com/jack-willturner/nas-as-program-transformation-exploration"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446753", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Language-parametric compiler validation with application to LLVM", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Theodoros Kasampalis", "Daejun Park", "Zhengyao Lin", "Vikram S. Adve", "Grigore Rosu"], "abstract": "We propose a new design for a Translation Validation (TV) system geared towards practical use with modern optimizing compilers, such as LLVM. Unlike existing TV systems, which are custom-tailored for a particular sequence of transformations and a specific, common language for input and output programs, our design clearly separates the transformation-specific components from the rest of the system, and generalizes the transformation-independent components. Specifically, we present Keq, the first program equivalence checker that is parametric to the input and output language semantics and has no dependence on the transformation between the input and output programs. The Keq algorithm is based on a rigorous formalization, namely cut-bisimulation, and is proven correct. We have prototyped a TV system for the Instruction Selection pass of LLVM, being able to automatically prove equivalence for translations from LLVM IR to the MachineIR used in compiling to x86-64. This transformation uses different input and output languages, and as such has not been previously addressed by the state of the art. An experimental evaluation shows that Keq successfully proves correct the translation of over 90% of 4732 supported functions in GCC from SPEC 2006.", "doi": "10.1145/3445814.3446751", "arxiv_id": "https://doi.org/10.1145/3445814.3446751", "pmid": null, "openalex_id": null, "s2_id": "b786cb27b9b45028c42cff856da1afce2a892b49", "cited_by": 25, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446751"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446751", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 7B: Security", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248627", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "b78f5a596929f767b3a283c8fc73f59e1c26edb3", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "IncBricks: Toward In-Network Computation with an In-Network Cache", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ming Liu", "Liang Luo", "Jacob Nelson", "Luis Ceze", "Arvind Krishnamurthy", "Kishore Atreya"], "abstract": "The emergence of programmable network devices and the increasing data traffic of datacenters motivate the idea of in-network computation. By offloading compute operations onto intermediate networking devices (e.g., switches, network accelerators, middleboxes), one can (1) serve network requests on the fly with low latency; (2) reduce datacenter traffic and mitigate network congestion; and (3) save energy by running servers in a low-power mode. However, since (1) existing switch technology doesn't provide general computing capabilities, and (2) commodity datacenter networks are complex (e.g., hierarchical fat-tree topologies, multipath communication), enabling in-network computation inside a datacenter is challenging.", "doi": "10.1145/3037697.3037731", "arxiv_id": "https://doi.org/10.1145/3037697.3037731", "pmid": null, "openalex_id": null, "s2_id": "b85b74e000830d84300b8ccf4708c5bf46ff81e8", "cited_by": 182, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037731&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037731"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037731", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Pallas: Semantic-Aware Checking for Finding Deep Bugs in Fast Path", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jian Huang", "Michael Allen-Bond", "Xuechen Zhang"], "abstract": "Software optimization is constantly a serious concern for developing high-performance systems. To accelerate the workflow execution of a specific functionality, software developers usually define and implement a fast path to speed up the critical and commonly executed functions in the workflow. However, producing a bug-free fast path is nontrivial. Our study on the Linux kernel discloses that a committed fast path can have up to 19 follow-up patches for bug fixing, and most of them are deep semantic bugs, which are difficult to be pinpointed by existing bug-finding tools.", "doi": "10.1145/3037697.3037743", "arxiv_id": "https://doi.org/10.1145/3037697.3037743", "pmid": null, "openalex_id": null, "s2_id": "b907c92ee8029f8943ea9b46901fa9a6a31afd24", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037743"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037743", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Puddle: A Dynamic, Error-Correcting, Full-Stack Microfluidics Platform", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Max Willsey", "Ashley P. Stephenson", "Chris Takahashi", "Pranav Vaid", "Bichlien H. Nguyen", "Michal Piszczek", "Christine Betts", "Sharon Newman", "Sarang Joshi", "Karin Strauss", "Luis Ceze"], "abstract": "Microfluidic devices promise to automate wetlab procedures by manipulating small chemical or biological samples. This technology comes in many varieties, all of which aim to save time, labor, and supplies by performing lab protocol steps typically done by a technician. However, existing microfluidic platforms remain some combination of inflexible, error-prone, prohibitively expensive, and difficult to program. We address these concerns with a full-stack digital microfluidic automation platform. Our main contribution is a runtime system that provides a high-level API for microfluidic manipulations. It manages fluidic resources dynamically, allowing programmers to freely mix regular computation with microfluidics, which results in more expressive programs than previous work. It also provides real-time error correction through a computer vision system, allowing robust execution on cheaper microfluidic hardware. We implement our stack on top of a low-cost droplet microfluidic device that we have developed. We evaluate our system with the fully-automated execution of polymerase chain reaction (PCR) and a DNA sequencing preparation protocol. These protocols demonstrate high-level programs that combine computational and fluidic operations such as input/output of reagents, heating of samples, and data analysis. We also evaluate the impact of automatic error correction on our system's reliability.", "doi": "10.1145/3297858.3304027", "arxiv_id": "https://doi.org/10.1145/3297858.3304027", "pmid": null, "openalex_id": null, "s2_id": "b9bf4ac075a2d1f482d2a996d98cd468f70a4a2c", "cited_by": 41, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304027", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304027"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304027", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Junkyard Computing: Repurposing Discarded Smartphones to Minimize Carbon", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3575693.3575710", "arxiv_id": "2110.06870", "pmid": null, "openalex_id": null, "s2_id": "baacb18ae2377fc3f5781a31f84943c60f9963fe", "cited_by": 78, "type": null, "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3575693.3575710"], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hippocrates: healing persistent memory bugs without doing any harm", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ian Neal", "Andrew Quinn", "Baris Kasikci"], "abstract": "Persistent memory (PM) technologies aim to revolutionize storage systems, providing persistent storage at near-DRAM speeds. Alas, programming PM systems is error-prone, as the misuse or omission of the durability mechanisms (i.e., cache flushes and memory fences) can lead to durability bugs (i.e., unflushed updates in CPU caches that violate crash consistency). PM-specific testing and debugging tools can help developers find these bugs, however even with such tools, fixing durability bugs can be challenging. To determine the reason behind this difficulty, we first study durability bugs and find that although the solution to a durability bug seems simple, the actual reasoning behind the fix can be complicated and time-consuming. Overall, the severity of these bugs coupled with the difficultly of developing fixes for them motivates us to consider automated approaches to fixing durability bugs.", "doi": "10.1145/3445814.3446694", "arxiv_id": "https://doi.org/10.1145/3445814.3446694", "pmid": null, "openalex_id": null, "s2_id": "bab0d48810f7c38b789c975818d2bb167bd14c71", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446694"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446694", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "LATR: Lazy Translation Coherence", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mohan Kumar", "Steffen Maass", "Sanidhya Kashyap", "Ján Veselý", "Zi Yan", "Taesoo Kim", "Abhishek Bhattacharjee", "Tushar Krishna"], "abstract": "We propose LATR-lazy TLB coherence-a software-based TLB shootdown mechanism that can alleviate the overhead of the synchronous TLB shootdown mechanism in existing operating systems. By handling the TLB coherence in a lazy fashion, LATR can avoid expensive IPIs which are required for delivering a shootdown signal to remote cores, and the performance overhead of associated interrupt handlers. Therefore, virtual memory operations, such as free and page migration operations, can benefit significantly from LATR's mechanism. For example, LATR improves the latency of munmap() by 70.8% on a 2-socket machine, a widely used configuration in modern data centers. Real-world, performance-critical applications such as web servers can also benefit from LATR: without any application-level changes, LATR improves Apache by 59.9% compared to Linux, and by 37.9% compared to ABIS, a highly optimized, state-of-the-art TLB coherence technique.", "doi": "10.1145/3173162.3173198", "arxiv_id": "https://doi.org/10.1145/3173162.3173198", "pmid": null, "openalex_id": null, "s2_id": "baf1539001a24d19edd67ef1d233e8d48c351dce", "cited_by": 52, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173198", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173198"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173198", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Sulong, and Thanks for All the Bugs: Finding Errors in C Programs by Abstracting from the Native Execution Model", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Manuel Rigger", "Roland Schatz", "René Mayrhofer", "Matthias Grimmer", "Hanspeter Mössenböck"], "abstract": "In C, memory errors, such as buffer overflows, are among the most dangerous software errors; as we show, they are still on the rise. Current dynamic bug-finding tools that try to detect such errors are based on the low-level execution model of the underlying machine. They insert additional checks in an ad-hoc fashion, which makes them prone to omitting checks for corner cases. To address this, we devised a novel approach to finding bugs during the execution of a program. At the core of this approach is an interpreter written in a high-level language that performs automatic checks (such as bounds, NULL, and type checks). By mapping data structures in C to those of the high-level language, accesses are automatically checked and bugs discovered. We have implemented this approach and show that our tool (called Safe Sulong) can find bugs that state-of-the-art tools overlook, such as out-of-bounds accesses to the main function arguments.", "doi": "10.1145/3173162.3173174", "arxiv_id": "https://doi.org/10.1145/3173162.3173174", "pmid": null, "openalex_id": null, "s2_id": "bbd8f8e111a738dbb4cd9c9fecdf411e4d4a33da", "cited_by": 16, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173174"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173174", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MVEDSUA: Higher Availability Dynamic Software Updates via Multi-Version Execution", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Luís Pina", "Anastasios Andronidis", "Michael Hicks", "Cristian Cadar"], "abstract": "Dynamic Software Updating (DSU) is a technique for patching stateful software without shutting it down, which enables both timely updates and non-stop service. Unfortunately, bugs in the update itself---whether in the changed code or in the way the change is introduced dynamically---may cause the updated software to crash or misbehave. Furthermore, the time taken to dynamically apply the update may be unacceptable if it introduces a long delay in service. This paper makes the key observation that both problems can be addressed by employing Multi-Version Execution (MVE). To avoid delay in service, the update is applied to a forked copy while the original system continues to operate. Once the update completes, the MVE system monitors that the responses of both versions agree for the same inputs. Expected divergences are specified by the programmer using an MVE-specific DSL. Unexpected divergences signal possible errors and roll back the update, which simply means terminating the updated version and reverting to the original version. This is safe because the MVE system keeps the state of both versions in sync. If the new version shows no problems after a warmup period, operators can make it permanent and discard the original version. We have implemented this approach, which we call MVEDSUa, by extending the Kitsune DSU framework with Varan, a state-of-the-art MVE system. We have used MVEDSUa to update several high-performance servers: Redis, Memcached, and VSFTPD. Our results show that MVEDSUa significantly reduces the update-time delay, imposes little overhead in steady state, and easily recovers from a", "doi": "10.1145/3297858.3304063", "arxiv_id": "https://doi.org/10.1145/3297858.3304063", "pmid": null, "openalex_id": null, "s2_id": "bc80b48c1ce503e319542f70ac5f0cc3129b7363", "cited_by": 43, "type": "conference", "is_oa": true, "pdf_urls": ["http://spiral.imperial.ac.uk/bitstream/10044/1/66157/2/mvedsua-asplos19.pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304063"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304063", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": null, "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "bdde33086455b105dd168ceb5683b6012c99172a", "cited_by": 2, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 4A: Code Generation and Synthesis", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252399", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "bde3d1cbb1198bc6ee5869ed9b69f8d7a03923b6", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Statistical robustness of Markov chain Monte Carlo accelerators", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiangyu Zhang", "Ramin Bashizade", "Yicheng Wang", "Sayan Mukherjee", "Alvin R. Lebeck"], "abstract": "Statistical machine learning often uses probabilistic models and algorithms, such as Markov Chain Monte Carlo (MCMC), to solve a wide range of problems. Probabilistic computations, often considered too slow on conventional processors, can be accelerated with specialized hardware by exploiting parallelism and optimizing the design using various approximation techniques. Current methodologies for evaluating correctness of probabilistic accelerators are often incomplete, mostly focusing only on end-point result quality (\"accuracy\"). It is important for hardware designers and domain experts to look beyond end-point \"accuracy\" and be aware of how hardware optimizations impact statistical properties.", "doi": "10.1145/3445814.3446697", "arxiv_id": "https://doi.org/10.1145/3445814.3446697", "pmid": null, "openalex_id": null, "s2_id": "bdf7e25ff8f3d7bb1700961794cbd422bfe0aa59", "cited_by": 14, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446697"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446697", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 5A: Emerging Memory Technologies", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252401", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "bed7354ff778db3dbc9e6caf9e68ace3a0e285c1", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Automatic Hierarchical Parallelization of Linear Recurrences", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sepideh Maleki", "Martin Burtscher"], "abstract": "Linear recurrences encompass many fundamental computations including prefix sums and digital filters. Later result values depend on earlier result values in recurrences, making it a challenge to compute them in parallel. We present a new work- and space-efficient algorithm to compute linear recurrences that is amenable to automatic parallelization and suitable for hierarchical massively-parallel architectures such as GPUs. We implemented our approach in a domain-specific code generator that emits optimized CUDA code. Our evaluation shows that, for standard prefix sums and single-stage IIR filters, the generated code reaches the throughput of memory copy for large inputs, which cannot be surpassed. On higher-order prefix sums, it performs nearly as well as the fastest handwritten code from the literature. On tuple-based prefix sums and digital filters, our automatically parallelized code outperforms the fastest prior implementations.", "doi": "10.1145/3173162.3173168", "arxiv_id": "https://doi.org/10.1145/3173162.3173168", "pmid": null, "openalex_id": null, "s2_id": "bf447034a103a79dfc8c8ad5710308c51355f530", "cited_by": 12, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173168", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173168"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173168", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MERR: Improving Security of Persistent Memory Objects via Efficient Memory Exposure Reduction and Randomization", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yuanchao Xu", "Yan Solihin", "Xipeng Shen"], "abstract": "This paper proposes a new defensive technique for memory, especially useful for long-living objects on Non-Volatile Memory (NVM), or called Persistent Memory objects (PMOs). The method takes a distinctive perspective, trying to reduce memory exposure time by largely shortening the overhead in attaching and detaching PMOs into the memory space. It does it through a novel idea, embedding page table subtrees inside PMOs. The paper discusses the complexities the technique brings, to permission controls and hardware implementations, and provides solutions. Experimental results show that the new technique reduces memory exposure time by 60% with a 5% time overhead (70% with 10.9% overhead). It allows much more frequent address randomizations (shortening the period from seconds to less than 41.4us), offering significant potential for enhancing memory security.", "doi": "10.1145/3373376.3378492", "arxiv_id": "https://doi.org/10.1145/3373376.3378492", "pmid": null, "openalex_id": null, "s2_id": "c0a23e1d72a411d78a650c11c187611649c36660", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378492", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378492"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378492", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Synopsis of the ASPLOS '16 Wild and Crazy Ideas (WACI) Invited-Speakers Session", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dan Tsafrir"], "abstract": "The Wild and Crazy Ideas (WACI) session is a longstanding tradition at ASPLOS, soliciting talks that consist of forward-looking, visionary, inspiring, creative, far out or just plain amazing ideas presented in an exciting way. (Amusing elements in the presentations are tolerated ;-) but are in fact optional.)", "doi": "10.1145/2872362.2876512", "arxiv_id": "https://doi.org/10.1145/2872362.2876512", "pmid": null, "openalex_id": null, "s2_id": "c11bc0965a26af897ab3858176f9848bf9d461d5", "cited_by": 0, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2876512"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2876512", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HEAX: An Architecture for Computing on Encrypted Data", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["M. Sadegh Riazi", "Kim Laine", "Blake Pelton", "Wei Dai"], "abstract": "With the rapid increase in cloud computing, concerns surrounding data privacy, security, and confidentiality also have been increased significantly. Not only cloud providers are susceptible to internal and external hacks, but also in some scenarios, data owners cannot outsource the computation due to privacy laws such as GDPR, HIPAA, or CCPA. Fully Homomorphic Encryption (FHE) is a groundbreaking invention in cryptography that, unlike traditional cryptosystems, enables computation on encrypted data without ever decrypting it. However, the most critical obstacle in deploying FHE at large-scale is the enormous computation overhead. In this paper, we present HEAX, a novel hardware architecture for FHE that achieves unprecedented performance improvements. HEAX leverages multiple levels of parallelism, ranging from ciphertext-level to fine-grained modular arithmetic level. Our first contribution is a new highly-parallelizable architecture for number-theoretic transform (NTT) which can be of independent interest as NTT is frequently used in many lattice-based cryptography systems. Building on top of NTT engine, we design a novel architecture for computation on homomorphically encrypted data. Our implementation on reconfigurable hardware demonstrates 164-268× performance improvement for a wide range of FHE parameters.", "doi": "10.1145/3373376.3378523", "arxiv_id": "1909.09731", "pmid": null, "openalex_id": null, "s2_id": "c15e9a2a208f98bbf17f1946a3ed9646992e8f79", "cited_by": 286, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378523", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378523"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378523", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Quantifying the design-space tradeoffs in autonomous drones", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ramyad Hadidi", "Bahar Asgari", "Sam Jijina", "Adriana Amyette", "Nima Shoghi", "Hyesoon Kim"], "abstract": "With fully autonomous flight capabilities coupled with user-specific applications, drones, in particular quadcopter drones, are becoming prevalent solutions in myriad commercial and research contexts. However, autonomous drones must operate within constraints and design considerations that are quite different from any other compute-based agent. At any given time, a drone must arbitrate among its limited compute, energy, and electromechanical resources. Despite huge technological advances in this area, each of these problems has been approached in isolation and drone systems design-space tradeoffs are largely unknown. To address this knowledge gap, we formalize the fundamental drone subsystems and find how computations impact this design space. We present a design-space exploration of autonomous drone systems and quantify how we can provide productive solutions. As an example, we study widely used simultaneous localization and mapping (SLAM) on various platforms and demonstrate that optimizing SLAM on FPGA is more fruitful for the drones. Finally, to address the lack of publicly available experimental drones, we release our open-source drone that is customizable across the hardware-software stack.", "doi": "10.1145/3445814.3446721", "arxiv_id": "https://doi.org/10.1145/3445814.3446721", "pmid": null, "openalex_id": null, "s2_id": "c1cc538fa16a7c768793efbceb9d4453d64197b1", "cited_by": 44, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446721"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446721", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Pronto: Easy and Fast Persistence for Volatile Data Structures", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amir Saman Memaripour", "Joseph Izraelevitz", "Steven Swanson"], "abstract": "Non-Volatile Main Memories (NVMMs) promise an opportunity for fast, persistent data structures. However, building these data structures is hard because their data must be consistent in the wake of a failure. Existing methods for building persistent data structures require either in-depth code changes to an existing data structure using an NVMM-aware library or rewriting the data structure from scratch. Unfortunately, both of these methods are labor-intensive and error-prone.", "doi": "10.1145/3373376.3378456", "arxiv_id": "https://doi.org/10.1145/3373376.3378456", "pmid": null, "openalex_id": null, "s2_id": "c1ee8f68216732c2eb9ad8ed49e196fecf39cc74", "cited_by": 57, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378456", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378456"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378456", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Current and Projected Needs for High Energy Physics Experiments (with a Particular Eye on CERN LHC)", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tommaso Boccali"], "abstract": "The High Energy Physics (HEP) Experiments at Particle Colliders need complex computing infrastructures in order to extract knowledge from the large datasets collected, with over 1 Exabyte of data stored by the experiments by now. The computing needs from the top world machine, the Large Hadron Collider (LHC) at CERN/Geneva, have seeded the realisation of the large scale GRID R&D and deployment efforts during the first decade of 2000, a posteriori proven to be adequate for the LHC data processing. The upcoming upgrade of the LHC collider, called High Luminosity LHC (HL-LHC) is foreseen to require an increase in computing resources by a factor between 10x and 100x, currently expected to be beyond the scalability of the existing distributed infrastructure. Current lines of R&D are presented and discussed. With the start of big scientific endeavours with a computing complexity similar to HL-LHC (SKA, CTA, Dune, ...) they are expected to be valid for science fields outside HEP.", "doi": "10.1145/3373376.3380612", "arxiv_id": "https://doi.org/10.1145/3373376.3380612", "pmid": null, "openalex_id": null, "s2_id": "c2acb8a9d504bb43915a843b85278cbeb9e3e564", "cited_by": 0, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3380612"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3380612", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Architecture-Adaptive Code Variant Tuning", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Saurav Muralidharan", "Amit Roy", "Mary W. Hall", "Michael Garland", "Piyush Rai"], "abstract": "Code variants represent alternative implementations of a computation, and are common in high-performance libraries and applications to facilitate selecting the most appropriate implementation for a specific execution context (target architecture and input dataset). Automating code variant selection typically relies on machine learning to construct a model during an offline learning phase that can be quickly queried at runtime once the execution context is known. In this paper, we define a new approach called architecture-adaptive code variant tuning, where the variant selection model is learned on a set of source architectures, and then used to predict variants on a new target architecture without having to repeat the training process. We pose this as a multi-task learning problem, where each source architecture corresponds to a task; we use device features in the construction of the variant selection model. This work explores the effectiveness of multi-task learning and the impact of different strategies for device feature selection. We evaluate our approach on a set of benchmarks and a collection of six NVIDIA GPU architectures from three distinct generations. We achieve performance results that are mostly comparable to the previous approach of tuning for a single GPU architecture without having to repeat the learning phase.", "doi": "10.1145/2872362.2872411", "arxiv_id": "https://doi.org/10.1145/2872362.2872411", "pmid": null, "openalex_id": null, "s2_id": "c45981b1526e66d176e5718b9cda8f4cd6e3a536", "cited_by": 48, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872411&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872411"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872411", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Taurus: a data plane architecture for per-packet ML", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3503222.3507726", "arxiv_id": "2002.08987", "pmid": null, "openalex_id": null, "s2_id": "c695e9788af7a0f4a5a5d5e328c81c3fc2a3a8a6", "cited_by": 127, "type": null, "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2002.08987"], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Bolt: I Know What You Did Last Summer... In The Cloud", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Christina Delimitrou", "Christos Kozyrakis"], "abstract": "Cloud providers routinely schedule multiple applications per physical host to increase efficiency. The resulting interference on shared resources often leads to performance degradation and, more importantly, security vulnerabilities. Interference can leak important information ranging from a service's placement to confidential data, like private keys. We present Bolt, a practical system that accurately detects the type and characteristics of applications sharing a cloud platform based on the interference an adversary sees on shared resources. Bolt leverages online data mining techniques that only require 2-5 seconds for detection. In a multi-user study on EC2, Bolt correctly identifies the characteristics of 385 out of 436 diverse workloads. Extracting this information enables a wide spectrum of previously-impractical cloud attacks, including denial of service attacks (DoS) that increase tail latency by 140x, as well as resource freeing (RFA) and co-residency attacks. Finally, we show that while advanced isolation mechanisms, such as cache partitioning lower detection accuracy, they are insufficient to eliminate these vulnerabilities altogether. To do so, one must either disallow core sharing, or only allow it between threads of the same application, leading to significant inefficiencies and performance penalties.", "doi": "10.1145/3037697.3037703", "arxiv_id": "https://doi.org/10.1145/3037697.3037703", "pmid": null, "openalex_id": null, "s2_id": "c6bdeff415fd171fcf7a76673103b73fae12336e", "cited_by": 83, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037703"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037703", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "AsyncClock: Scalable Inference of Asynchronous Event Causality", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chun-Hung Hsiao", "Satish Narayanasamy", "Essam Muhammad Idris Khan", "Cristiano L. Pereira", "Gilles A. Pokam"], "abstract": "Asynchronous programming model is commonly used in mobile systems and Web 2.0 environments. Asynchronous race detectors use algorithms that are an order of magnitude performance and space inefficient compared to conventional data race detectors. We solve this problem by identifying and addressing two important problems in reasoning about causality between asynchronous events.", "doi": "10.1145/3037697.3037712", "arxiv_id": "https://doi.org/10.1145/3037697.3037712", "pmid": null, "openalex_id": null, "s2_id": "c7edf9ab41b71a5336a1653071d56f5a53bcc17d", "cited_by": 13, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037712"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037712", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Minnow: Lightweight Offload Engines for Worklist Management and Worklist-Directed Prefetching", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dan Zhang", "Xiaoyu Ma", "Michael Thomson", "Derek Chiou"], "abstract": "The importance of irregular applications such as graph analytics is rapidly growing with the rise of Big Data. However, parallel graph workloads tend to perform poorly on general-purpose chip multiprocessors (CMPs) due to poor cache locality, low compute intensity, frequent synchronization, uneven task sizes, and dynamic task generation. At high thread counts, execution time is dominated by worklist synchronization overhead and cache misses. Researchers have proposed hardware worklist accelerators to address scheduling costs, but these proposals often harden a specific scheduling policy and do not address high cache miss rates. We address this with Minnow, a technique that augments each core in a CMP with a lightweight Minnow accelerator. Minnow engines offload worklist scheduling from worker threads to improve scalability. The engines also perform worklist-directed prefetching, a technique that exploits knowledge of upcoming tasks to issue nearly perfectly accurate and timely prefetch operations. On a simulated 64-core CMP running a parallel graph benchmark suite, Minnow improves scalability and reduces L2 cache misses from 29 to 1.2 MPKI on average, resulting in 6.01x average speedup over an optimized software baseline for only 1% area overhead.", "doi": "10.1145/3173162.3173197", "arxiv_id": "https://doi.org/10.1145/3173162.3173197", "pmid": null, "openalex_id": null, "s2_id": "c933f69c4afd584924c204e11701b32cf037ffb2", "cited_by": 58, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173197", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173197"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173197", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Effective simulation and debugging for a high-level hardware language using software compilers", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Clément Pit-Claudel", "Thomas Bourgeat", "Stella Lau", "Arvind", "Adam Chlipala"], "abstract": "Rule-based hardware-design languages (RHDLs) promise to enhance developer productivity by offering convenient abstractions. Advanced compiler technology keeps the cost of these abstractions low, generating circuits with excellent area and timing properties.", "doi": "10.1145/3445814.3446720", "arxiv_id": "https://doi.org/10.1145/3445814.3446720", "pmid": null, "openalex_id": null, "s2_id": "c939644bf42876c35db263994bce62d7601b42eb", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446720", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446720"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446720", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Orchestrated trios: compiling for efficient communication in Quantum programs with 3-Qubit gates", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Casey Duckering", "Jonathan M. Baker", "Andrew Litteken", "Frederic T. Chong"], "abstract": "Current quantum computers are especially error prone and require high levels of optimization to reduce operation counts and maximize the probability the compiled program will succeed. These computers only support operations decomposed into one- and two-qubit gates and only two-qubit gates between physically connected pairs of qubits. Typical compilers first decompose operations, then route data to connected qubits. We propose a new compiler structure, Orchestrated Trios, that first decomposes to the three-qubit Toffoli, routes the inputs of the higher-level Toffoli operations to groups of nearby qubits, then finishes decomposition to hardware-supported gates. This significantly reduces communication overhead by giving the routing pass access to the higher-level structure of the circuit instead of discarding it. A second benefit is the ability to now select an architecture-tuned Toffoli decomposition such as the 8-CNOT Toffoli for the specific hardware qubits now known after the routing pass. We perform real experiments on IBM Johannesburg showing an average 35% decrease in two-qubit gate count and 23% increase in success rate of a single Toffoli over Qiskit. We additionally compile many near-term benchmark algorithms showing an average 344% increase in (or 4.44x) simulated success rate on the Johannesburg architecture and compare with other architecture types.", "doi": "10.1145/3445814.3446718", "arxiv_id": "2102.08451", "pmid": null, "openalex_id": null, "s2_id": "ca431f51a25c49a59fd4f7644f772ec2c0d7a4ac", "cited_by": 36, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2102.08451", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446718"], "github": ["https://github.com/cduck/orchestrated-trios"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446718", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fast Fine-Grained Global Synchronization on GPUs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kai Wang", "Don Fussell", "Calvin Lin"], "abstract": "This paper extends the reach of General Purpose GPU programming by presenting a software architecture that supports efficient fine-grained synchronization over global memory. The key idea is to transform global synchronization into global communication so that conflicts are serialized at the thread block level. With this structure, the threads within each thread block can synchronize using low latency, high-bandwidth local scratchpad memory. To enable this architecture, we implement a scalable and efficient message passing library. Using Nvidia GTX 1080 ti GPUs, we evaluate our new software architecture by using it to solve a set of five irregular problems on a variety of workloads. We find that on average, our solutions improve performance over carefully tuned state-of-the-art solutions by 3.6×.", "doi": "10.1145/3297858.3304055", "arxiv_id": "https://doi.org/10.1145/3297858.3304055", "pmid": null, "openalex_id": null, "s2_id": "cae9f45d8e963195bdba77c62d702b3823e03869", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304055", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304055"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304055", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Peacenik: Architecture Support for Not Failing under Fail-Stop Memory Consistency", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Rui Zhang", "Swarnendu Biswas", "Vignesh Balaji", "Michael D. Bond", "Brandon Lucia"], "abstract": "Modern shared-memory systems have erroneous, undefined behavior for programs that are not well synchronized. A promising solution is to provide fail-stop memory consistency, which ensures well-defined behavior for all programs. While fail-stop consistency avoids undefined behavior, it can lead to unexpected failures, imperiling performance or progress. This paper presents architecture support called Peacenik that avoids failures in the context of fail-stop memory consistency. We demonstrate Peacenik by applying Peacenik's general mechanisms to two existing architectures that provide fail-stop consistency. A simulation-based evaluation shows that Peacenik eliminates nearly all of the high costs of fail-stop behavior incurred by the baseline architectures, demonstrating how to get the benefits of fail-stop consistency without incurring most or all of its costs.", "doi": "10.1145/3373376.3378485", "arxiv_id": "https://doi.org/10.1145/3373376.3378485", "pmid": null, "openalex_id": null, "s2_id": "ccffc2b362bd8a7cb54561814abebe361eb27f69", "cited_by": 2, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378485", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378485"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378485", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Atomicity Checking in Linear Time using Vector Clocks", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Umang Mathur", "Mahesh Viswanathan"], "abstract": "Multi-threaded programs are challenging to write. Developers often need to reason about a prohibitively large number of thread interleavings to reason about the behavior of software. A non-interference property like atomicity can reduce this interleaving space by ensuring that any execution is equivalent to an execution where all atomic blocks are executed serially. We consider the well studied notion of conflict serializability for dynamically checking atomicity. Existing algorithms detect violations of conflict serializability by detecting cycles in a graph of transactions observed in a given execution. The number of edges in such a graph can grow quadratically with the length of the trace making the analysis not scalable. In this paper, we present AeroDrome, a novel single pass linear time algorithm that uses vector clocks to detect violations of conflict serializability in an online setting. Experiments show that AeroDrome scales to traces with a large number of events with significant speedup.", "doi": "10.1145/3373376.3378475", "arxiv_id": "2001.04961", "pmid": null, "openalex_id": null, "s2_id": "ce0e6ed3a1ec3889349bb321cf48bbc74c912732", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378475", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378475"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378475", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Hailstorm: Disaggregated Compute and Storage for Distributed LSM-based Databases", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Laurent Bindschaedler", "Ashvin Goel", "Willy Zwaenepoel"], "abstract": "Distributed LSM-based databases face throughput and latency issues due to load imbalance across instances and interference from background tasks such as flushing, compaction, and data migration. Hailstorm addresses these problems by deploying the database storage engines over a distributed filesystem that disaggregates storage from processing, enabling storage pooling and compaction offloading. Hailstorm pools storage devices within a rack, allowing each storage engine to fully utilize the aggregate rack storage capacity and bandwidth. Storage pooling successfully handles load imbalance without the need for resharding. Hailstorm offloads compaction tasks to remote nodes, distributing their impact, and improving overall system throughput and response time. We show that Hailstorm achieves load balance in many MongoDB deployments with skewed workloads, improving the average throughput by 60%, while decreasing tail latency by as much as 5X. In workloads with range queries, Hailstorm provides up to 22X throughput improvements. Hailstorm also enables cost savings of 47-56% in OLTP workloads.", "doi": "10.1145/3373376.3378504", "arxiv_id": "https://doi.org/10.1145/3373376.3378504", "pmid": null, "openalex_id": null, "s2_id": "cedfa662597d405feaaaacfce3f1922272f8de30", "cited_by": 71, "type": "conference", "is_oa": true, "pdf_urls": ["http://infoscience.epfl.ch/record/275475", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378504"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378504", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Game of Threads: Enabling Asynchronous Poisoning Attacks", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jose Rodrigo Sanchez Vicarte", "Benjamin Schreiber", "Riccardo Paccagnella", "Christopher W. Fletcher"], "abstract": "As data sizes continue to grow at an unprecedented rate, machine learning training is being forced to adopt asynchronous algorithms to maintain performance and scalability. In asynchronous training, many threads share and update the model in a racy fashion to avoid costly inter-thread synchronization.", "doi": "10.1145/3373376.3378462", "arxiv_id": "https://doi.org/10.1145/3373376.3378462", "pmid": null, "openalex_id": null, "s2_id": "cee94afe3ebb3a03059611d384722e9c3c714ad7", "cited_by": 22, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378462", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378462"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378462", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "MV-RLU: Scaling Read-Log-Update with Multi-Versioning", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jaeho Kim", "Ajit Mathew", "Sanidhya Kashyap", "Madhava Krishnan Ramanathan", "Changwoo Min"], "abstract": "This paper presents multi-version read-log-update (MV-RLU), an extension of the read-log-update (RLU) synchronization mechanism. While RLU has many merits including an intuitive programming model and excellent performance for read-mostly workloads, we observed that the performance of RLU significantly drops in workloads with more write operations. The core problem is that RLU manages only two versions. To overcome such limitation, we extend RLU to support multi-versioning and propose new techniques to make multi-versioning efficient. At the core of MV-RLU design is concurrent autonomous garbage collection, which prevents reclaiming invisible versions being a bottleneck, and reduces the version traversal overhead the main overhead of multi-version design. We extensively evaluate MV-RLU with the state-of-the-art synchronization mechanisms, including RCU, RLU, software transactional memory (STM), and lock-free approaches, on concurrent data structures and real-world applications (database concurrency control and in-memory key-value store). Our evaluation results show that MV-RLU significantly outperforms other techniques for a wide range of workloads with varying contention levels and data-set size.", "doi": "10.1145/3297858.3304040", "arxiv_id": "https://doi.org/10.1145/3297858.3304040", "pmid": null, "openalex_id": null, "s2_id": "cf6fdb18b28eb5166c8f233d51fc335dadeba60a", "cited_by": 28, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304040&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304040"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304040", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Jamais vu: thwarting microarchitectural replay attacks", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dimitrios Skarlatos", "Zirui Neil Zhao", "Riccardo Paccagnella", "Christopher W. Fletcher", "Josep Torrellas"], "abstract": "Microarchitectural Replay Attacks (MRAs) enable an attacker to eliminate the measurement variation in potentially any microarchitectural side channel—even if the victim instruction is supposed to execute only once. In an MRA, the attacker forces pipeline flushes in order to repeatedly re-execute the victim instruction and denoise the channel. MRAs are not limited to transient execution attacks: the replayed victim can be an instruction that will eventually retire. This paper presents the first technique to thwart MRAs. The technique, called Jamais Vu, detects when an instruction is squashed. Then, as the instruction is re-inserted into the pipeline, Jamais Vu automatically places a fence before it to prevent the attacker from squashing it again. This paper presents several Jamais Vu designs that offer different trade-offs between security, execution overhead, and implementation complexity. One design, called Epoch-Loop-Rem, effectively mitigates MRAs, has an average execution time overhead of 13.8% in benign executions, and only needs counting Bloom filters. An even simpler design, called Clear-on-Retire, has an average execution time overhead of only 2.9%, although it is less secure.", "doi": "10.1145/3445814.3446716", "arxiv_id": "https://doi.org/10.1145/3445814.3446716", "pmid": null, "openalex_id": null, "s2_id": "d01f705624b48b8fda23d054d50cbc5c44d8b3a2", "cited_by": 6, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446716"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446716", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DiAG: a dataflow-inspired architecture for general-purpose processors", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dong Kai Wang", "Nam Sung Kim"], "abstract": "The end of Dennard scaling and decline of Moore's law has prompted the proliferation of hardware accelerators for a wide range of application domains. Yet, at the dawn of an era of specialized computing, left behind the trend is the general-purpose processor that is still most easily programmed and widely used but has seen incremental changes for decades. This work uses an accelerator-inspired approach to rethink CPU microarchitecture to improve its energy efficiency while retaining its generality. We propose DiAG, a dataflow-based general-purpose processor architecture that can minimize latency by exploiting instruction-level parallelism or maximize throughput by exploiting data-level parallelism. DiAG is designed to support any RISC-like instruction set without explicitly requiring specialized languages, libraries, or compilers. Central to this architecture is the abstraction of the register file as register 'lanes' that allow implicit construction of the program's dataflow graph in hardware. At the cost of increased area, DiAG offers three main benefits over conventional out-of-order microarchitectures: reduced front-end overhead, efficient instruction reuse, and thread-level pipelining. We implement a DiAG prototype that supports the RISC-V ISA in SystemVerilog and evaluate its performance, power consumption, and area with EDA tools. In the tested Rodinia and SPEC CPU2017 benchmarks, DiAG configured with 512 PEs achieves a 1.18x speedup and 1.63x improvement in energy efficiency against an aggressive out-of-order CPU baseline.", "doi": "10.1145/3445814.3446703", "arxiv_id": "https://doi.org/10.1145/3445814.3446703", "pmid": null, "openalex_id": null, "s2_id": "d0219c661fa5022fcbdab9b8923c5a21a11547fe", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446703"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446703", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Switches for HIRE: resource scheduling for data center in-network computing", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Marcel Blöcher", "Lin Wang", "Patrick Eugster", "Max Schmidt"], "abstract": "The recent trend towards more programmable switching hardware in data centers opens up new possibilities for distributed applications to leverage in-network computing (INC). Literature so far has largely focused on individual application scenarios of INC, leaving aside the problem of coordinating usage of potentially scarce and heterogeneous switch resources among multiple INC scenarios, applications, and users. The traditional model of resource pools of isolated compute containers does not fit an INC-enabled data center.", "doi": "10.1145/3445814.3446760", "arxiv_id": "https://doi.org/10.1145/3445814.3446760", "pmid": null, "openalex_id": null, "s2_id": "d037f3df7bcad91c18f394855054abf990f7bb40", "cited_by": 40, "type": "conference", "is_oa": true, "pdf_urls": ["https://research.vu.nl/en/publications/763c3646-229d-489a-8dca-57a96d840e44", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446760"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446760", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Mind mappings: enabling efficient algorithm-accelerator mapping space search", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kartik Hegde", "Po-An Tsai", "Sitao Huang", "Vikas Chandra", "Angshuman Parashar", "Christopher W. Fletcher"], "abstract": "Modern day computing increasingly relies on specialization to satiate growing performance and efficiency requirements. A core challenge in designing such specialized hardware architectures is how to perform mapping space search, i.e., search for an optimal mapping from algorithm to hardware. Prior work shows that choosing an inefficient mapping can lead to multiplicative-factor efficiency overheads. Additionally, the search space is not only large but also non-convex and non-smooth, precluding advanced search techniques. As a result, previous works are forced to implement mapping space search using expert choices or sub-optimal search heuristics. This work proposes Mind Mappings, a novel gradient-based search method for algorithm-accelerator mapping space search. The key idea is to derive a smooth, differentiable approximation to the otherwise non-smooth, non-convex search space. With a smooth, differentiable approximation, we can leverage efficient gradient-based search algorithms to find high-quality mappings. We extensively compare Mind Mappings to black-box optimization schemes used in prior work. When tasked to find mappings for two important workloads (CNN and MTTKRP), Mind Mapping finds mappings that achieve an average 1.40×, 1.76×, and 1.29× (when run for a fixed number of steps) and 3.16×, 4.19×, and 2.90× (when run for a fixed amount of time) better energy-delay product (EDP) relative to Simulated Annealing, Genetic Algorithms and Reinforcement Learning, respectively. Meanwhile, Mind Mappings returns mappings with only 5.32× higher EDP than a possibly unachievable theoretical lower-bound, indicating proximity to the global optima.", "doi": "10.1145/3445814.3446762", "arxiv_id": "2103.01489", "pmid": null, "openalex_id": null, "s2_id": "d051b4e5f7e400b6c3fdd05945e6aabf6b33cae1", "cited_by": 122, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2103.01489", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446762"], "github": ["https://github.com/kartik-hegde/mindMappings"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446762", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Durable Transactional Memory Can Scale with Timestone", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Madhava Krishnan Ramanathan", "Jaeho Kim", "Ajit Mathew", "Xinwei Fu", "Anthony Demeri", "Changwoo Min", "Sudarsun Kannan"], "abstract": "Non-volatile main memory (NVMM) technologies promise byte addressability and near-DRAM access that allows developers to build persistent applications with common load and store instructions. However, it is difficult to realize these promises because NVMM software should also provide crash consistency while providing high performance, and scalability. Durable transactional memory (DTM) systems address these challenges. However, none of them scale beyond 16 cores. The poor scalability either stems from the underlying STM layer or from employing limited write parallelism (single writer or dual version). In addition, other fundamental issues with guaranteeing crash consistency are high write amplification and memory footprint in existing approaches. To address these challenges, we propose TimeStone: a highly scalable DTM system with low write amplification and minimal memory footprint. TimeStone uses a novel multi-layered hybrid logging technique, called TOC logging, to guarantee crash consistency. Also, TimeStone further relies on Multi-Version Concurrency Control (MVCC) mechanism to achieve high scalability and to support different isolation levels on the same data set. Our evaluation of TimeStone against the state-of-the-art DTM systems shows that it significantly outperforms other systems for a wide range of workloads with varying data-set size and contention levels, up to 112 hardware threads. In addition, with our TOC logging, TimeStone achieves a write amplification of less than 1, while existing DTM systems suffer from 2×-6× overhead.", "doi": "10.1145/3373376.3378483", "arxiv_id": "https://doi.org/10.1145/3373376.3378483", "pmid": null, "openalex_id": null, "s2_id": "d114abac0ccc02731f31ddd9ab02d07b2ff5044e", "cited_by": 57, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378483"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378483", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ReFlex: Remote Flash ≈ Local Flash", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ana Klimovic", "Heiner Litz", "Christos Kozyrakis"], "abstract": "Remote access to NVMe Flash enables flexible scaling and high utilization of Flash capacity and IOPS within a datacenter. However, existing systems for remote Flash access either introduce significant performance overheads or fail to isolate the multiple remote clients sharing each Flash device. We present ReFlex, a software-based system for remote Flash access, that provides nearly identical performance to accessing local Flash. ReFlex uses a dataplane kernel to closely integrate networking and storage processing to achieve low latency and high throughput at low resource requirements. Specifically, ReFlex can serve up to 850K IOPS per core over TCP/IP networking, while adding 21us over direct access to local Flash. ReFlex uses a QoS scheduler that can enforce tail latency and throughput service-level objectives (SLOs) for thousands of remote clients. We show that ReFlex allows applications to use remote Flash while maintaining their original performance with local Flash.", "doi": "10.1145/3037697.3037732", "arxiv_id": "https://doi.org/10.1145/3037697.3037732", "pmid": null, "openalex_id": null, "s2_id": "d1c20fcde63e757ecfb813b47be6bb8af4b6b7ff", "cited_by": 171, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037732"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037732", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "BOGO: Buy Spatial Memory Safety, Get Temporal Memory Safety (Almost) Free", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tong Zhang", "Dongyoon Lee", "Changhee Jung"], "abstract": "A memory safety violation occurs when a program has an out-of-bound (spatial safety) or use-after-free (temporal safety) memory access. Given its importance as a security vulnerability, recent Intel processors support hardware-accelerated bound checks, called Memory Protection Extensions (MPX). Unfortunately, MPX provides no temporal safety. This paper presents BOGO, a lightweight full memory safety enforcement scheme that transparently guarantees temporal safety on top of MPX's spatial safety. Instead of tracking separate metadata for temporal safety, BOGO reuses the bounds metadata maintained by MPX for both spatial and temporal safety. On free, BOGO scans the MPX bound tables to invalidate the bound of dangling pointers; any following use-after-free error can be detected by MPX as an out-of-bound error. Since scanning the entire MPX bound tables could be expensive, BOGO tracks a small set of hot MPX bound table pages to check on free, and relies on the page fault mechanism to detect any potentially missing dangling pointer, ensuring sound temporal safety protection. Our evaluation shows that BOGO provides full memory safety at 60% runtime overhead and at 36% memory overhead for SPEC CPU 2006 benchmarks. We also show that BOGO incurs reasonable 2.7x slowdown for the worst-case malloc-free intensive benchmarks; and moderate 1.34x overhead for real-world applications.", "doi": "10.1145/3297858.3304017", "arxiv_id": "https://doi.org/10.1145/3297858.3304017", "pmid": null, "openalex_id": null, "s2_id": "d1eca8f50a678beb3a3ab898fb741df6bbeee04b", "cited_by": 68, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304017", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304017"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304017", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chun-Yi Liu", "Jagadish B. Kotra", "Myoungsoo Jung", "Mahmut T. Kandemir", "Chita R. Das"], "abstract": "NAND-based solid-state disks (SSDs) are known for their superior random read/write performance due to the high degrees of multi-chip parallelism they exhibit. Currently, as the chip density increases dramatically, fewer 3D NAND chips are needed to build an SSD compared to the previous generation chips. As a result, SSDs can be made more compact. However, this decrease in the number of chips also results in reduced overall throughput, and prevents 3D NAND high density SSDs from being widely-adopted. We analyzed 600 storage workloads, and our analysis revealed that the small read operations suffer significant performance degradation due to reduced chip-level parallelism in newer 3D NAND SSDs. The main question is whether some of the inter-chip parallelism lost in these new SSDs (due to the reduced chip count) can be won back by enhancing intra-chip parallelism. Motivated by this question, we propose a novel SOML (Single-Operation-Multiple-Location) read operation, which can perform several small intra-chip read operations to different locations simultaneously, so that multiple requests can be serviced in parallel, thereby mitigating the parallelism-related bottlenecks. A corresponding SOML read scheduling algorithm is also proposed to fully utilize the SOML read. Our experimental results with various storage workloads indicate that, the SOML read-based SSD with 8 chips can outperform the baseline SSD with 16 chips.", "doi": "10.1145/3297858.3304035", "arxiv_id": "https://doi.org/10.1145/3297858.3304035", "pmid": null, "openalex_id": null, "s2_id": "d1eedae8f831adbae4451ade1bc76c95795e051b", "cited_by": 54, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304035", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304035"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304035", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "The Computational Sprinting Game", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Songchun Fan", "Seyed Majid Zahedi", "Benjamin C. Lee"], "abstract": "Computational sprinting is a class of mechanisms that boost performance but dissipate additional power. We describe a sprinting architecture in which many, independent chip multiprocessors share a power supply and sprints are constrained by the chips' thermal limits and the rack's power limits. Moreover, we present the computational sprinting game, a multi-agent perspective on managing sprints. Strategic agents decide whether to sprint based on application phases and system conditions. The game produces an equilibrium that improves task throughput for data analytics workloads by 4-6× over prior greedy heuristics and performs within 90% of an upper bound on throughput from a globally optimized policy.", "doi": "10.1145/2872362.2872383", "arxiv_id": "https://doi.org/10.1145/2872362.2872383", "pmid": null, "openalex_id": null, "s2_id": "d2b786a07130aa915b341585410ce9370db4202d", "cited_by": 58, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872383"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872383", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Approximate Storage of Compressed and Encrypted Videos", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Djordje Jevdjic", "Karin Strauss", "Luis Ceze", "Henrique S. Malvar"], "abstract": "The popularization of video capture devices has created strong storage demand for encoded videos. Approximate storage can ease this demand by enabling denser storage at the expense of occasional errors. Unfortunately, even minor storage errors, such as bit flips, can result in major visual damage in encoded videos. Similarly, video encryption, widely employed for privacy and digital rights management, may create long dependencies between bits that show little or no tolerance to storage errors.", "doi": "10.1145/3037697.3037718", "arxiv_id": "https://doi.org/10.1145/3037697.3037718", "pmid": null, "openalex_id": null, "s2_id": "d2d0efd3095aa60c400f8bbbd476af4345067371", "cited_by": 44, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037718"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037718", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Thermostat: Application-transparent Page Management for Two-tiered Main Memory", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Neha Agarwal", "Thomas F. Wenisch"], "abstract": "The advent of new memory technologies that are denser and cheaper than commodity DRAM has renewed interest in two-tiered main memory schemes. Infrequently accessed application data can be stored in such memories to achieve significant memory cost savings. Past research on two-tiered main memory has assumed a 4KB page size. However, 2MB huge pages are performance critical in cloud applications with large memory footprints, especially in virtualized cloud environments, where nested paging drastically increases the cost of 4KB page management. We present Thermostat, an application-transparent huge-page-aware mechanism to place pages in a dual-technology hybrid memory system while achieving both the cost advantages of two-tiered memory and performance advantages of transparent huge pages. We present an online page classification mechanism that accurately classifies both 4KB and 2MB pages as hot or cold while incurring no observable performance overhead across several representative cloud applications. We implement Thermostat in Linux kernel version 4.5 and evaluate its effectiveness on representative cloud computing workloads running under KVM virtualization. We emulate slow memory with performance characteristics approximating near-future high-density memory technology and show that Thermostat migrates up to 50% of application footprint to slow memory while limiting performance degradation to 3%, thereby reducing memory cost up to 30%.", "doi": "10.1145/3037697.3037706", "arxiv_id": "https://doi.org/10.1145/3037697.3037706", "pmid": null, "openalex_id": null, "s2_id": "d2ef7cfbf42ca869c08a1d35ec2f9036e8b3b0a4", "cited_by": 256, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037706"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037706", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "TPC: Target-Driven Parallelism Combining Prediction and Correction to Reduce Tail Latency in Interactive Services", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Myeongjae Jeon", "Yuxiong He", "Hwanju Kim", "Sameh Elnikety", "Scott Rixner", "Alan L. Cox"], "abstract": "In interactive services such as web search, recommendations, games and finance, reducing the tail latency is crucial to provide fast response to every user. Using web search as a driving example, we systematically characterize interactive workload to identify the opportunities and challenges for reducing tail latency. We find that the workload consists of mainly short requests that do not benefit from parallelism, and a few long requests which significantly impact the tail but exhibit high parallelism speedup. This motivates estimating request execution time, using a predictor, to identify long requests and to parallelize them. Prediction, however, is not perfect; a long request mispredicted as short is likely to contribute to the server tail latency, setting a ceiling on the achievable tail latency. We propose TPC, an approach that combines prediction information judiciously with dynamic correction for inaccurate prediction. Dynamic correction increases parallelism to accelerate a long request that is mispredicted as short. TPC carefully selects the appropriate target latencies based on system load and parallelism efficiency to reduce tail latency.", "doi": "10.1145/2872362.2872370", "arxiv_id": "https://doi.org/10.1145/2872362.2872370", "pmid": null, "openalex_id": null, "s2_id": "d2fe3f26505c106cb2f61c86ba0a2dc316b0868f", "cited_by": 33, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872370"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872370", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "StrongBox: Confidentiality, Integrity, and Performance using Stream Ciphers for Full Drive Encryption", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Bernard Dickens III", "Haryadi S. Gunawi", "Ariel J. Feldman", "Henry Hoffmann"], "abstract": "Full-drive encryption (FDE) is especially important for mobile devices because they contain large quantities of sensitive data yet are easily lost or stolen. Unfortunately, the standard approach to FDE-the AES block cipher in XTS mode-is 3--5× slower than unencrypted storage. Authenticated encryption based on stream ciphers is already used as a faster alternative to AES in other contexts, such as HTTPS, but the conventional wisdom is that stream ciphers are unsuitable for FDE. Used naively in drive encryption, stream ciphers are vulnerable to attacks, and mitigating these attacks with on-drive metadata is generally believed to ruin performance. In this paper, we argue that recent developments in mobile hardware invalidate this assumption, making it possible to use fast stream ciphers for FDE. Modern mobile devices employ solid-state storage with Flash Translation Layers (FTL), which operate similarly to Log-structured File Systems (LFS). They also include trusted hardware such as Trusted Execution Environments (TEEs) and secure storage areas. Leveraging these two trends, we propose StrongBox, a stream cipher-based FDE layer that is a drop-in replacement for dm-crypt, the standard Linux FDE module based on AES-XTS. StrongBox introduces a system design and on-drive data structures that exploit LFS»s lack of overwrites to avoid costly rekeying and a counter stored in trusted hardware to protect against attacks. We implement StrongBox on an ARM big.LITTLE mobile processor and test its performance under multiple popular production LFSes. We find that StrongBox improves read performance by as much as 2.36× (1.72× on average) while offering stronger integrity guarantees.", "doi": "10.1145/3173162.3173183", "arxiv_id": "https://doi.org/10.1145/3173162.3173183", "pmid": null, "openalex_id": null, "s2_id": "d3a3f480eaf3b76a4245b7e9abf854962e9053be", "cited_by": 19, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3173162.3173183", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173183"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173183", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 6B: OS Optimizations", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252404", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "d41196788543d04df5067f14ae29b0aae6b1e898", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["WonJun Song", "Gwangsun Kim", "Hyungjoon Jung", "Jongwook Chung", "Jung Ho Ahn", "Jae W. Lee", "John Kim"], "abstract": "NUMA (non-uniform memory access) servers are commonly used in high-performance computing and datacenters. Within each server, a processor-interconnect (e.g., Intel QPI, AMD HyperTransport) is used to communicate between the different sockets or nodes. In this work, we explore the impact of the processor-interconnect on overall performance -- in particular, the performance un- fairness caused by processor-interconnect arbitration. It is well known that locally-fair arbitration does not guarantee globally-fair bandwidth sharing as closer nodes receive more bandwidth in a multi-hop network. However, this work demonstrates that the opposite can occur in a commodity NUMA server where remote nodes receive higher bandwidth (and perform better). We analyze this problem and iden- tify that this occurs because of external concentration used in router micro-architectures for processor-interconnects without globally-aware arbitration. While accessing remote memory can occur in any NUMA system, performance un- fairness (or performance variation) is more critical in cloud computing and virtual machines with shared resources. We demonstrate how this unfairness creates significant performance variation when a workload is executed on the Xen virtualization platform. We then provide analysis using synthetic workloads to better understand the source of unfair- ness and eliminate the impact of other shared resources, including the shared last-level cache and main memory. To provide fairness, we propose a novel, history-based arbitration that tracks the history of arbitration grants made in the previous history window. A weighted arbitration is done based on the history to provide global fairness. Through simulations, we show our proposed history-based arbitration can provide global fairness and minimize the processor- interconnect performance unfairness at low cost.", "doi": "10.1145/3037697.3037753", "arxiv_id": "https://doi.org/10.1145/3037697.3037753", "pmid": null, "openalex_id": null, "s2_id": "d43adde9afd4f1c8da3d88dfcf3170dc520c6529", "cited_by": 6, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037753"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037753", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Fast and Scalable VMM Live Upgrade in Large Cloud Infrastructure", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xiantao Zhang", "Xiao Zheng", "Zhi Wang", "Qi Li", "Junkang Fu", "Yang Zhang", "Yibin Shen"], "abstract": "High availability is the most important and challenging problem for cloud providers. However, virtual machine monitor (VMM), a crucial component of the cloud infrastructure, has to be frequently updated and restarted to add security patches and new features, undermining high availability. There are two existing live update methods to improve the cloud availability: kernel live patching and Virtual Machine (VM) live migration. However, they both have serious drawbacks that impair their usefulness in the large cloud infrastructure: kernel live patching cannot handle complex changes (e.g., changes to persistent data structures); and VM live migration may incur unacceptably long delays when migrating millions of VMs in the whole cloud, for example, to deploy urgent security patches.", "doi": "10.1145/3297858.3304034", "arxiv_id": "https://doi.org/10.1145/3297858.3304034", "pmid": null, "openalex_id": null, "s2_id": "d43fcc14306726da5838c3e8761061798e778fd0", "cited_by": 38, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304034", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304034"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304034", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Swamit S. Tannu", "Moinuddin K. Qureshi"], "abstract": "Existing and near-term quantum computers are not yet large enough to support fault-tolerance. Such systems with few tens to few hundreds of qubits are termed as Noisy Intermediate Scale Quantum computers (NISQ), and these systems can provide benefits for a class of quantum algorithms. In this paper, we study the problems of Qubit-Allocation (mapping of program qubits to machine qubits) and Qubit-Movement (routing qubits from one location to another for entanglement). We observe that there can be variation in the error rates of different qubits and links, which can impact the decisions for qubit movement and qubit allocation. We analyze publicly available characterization data for the IBM-Q20 to quantify the variation and show that there is indeed significant variability in the error rates of the qubits and the links connecting them. We show that the device variability has a significant impact on the overall system reliability. To exploit the variability in error rate, we propose Variation-Aware Qubit Movement (VQM) and Variation-Aware Qubit Allocation (VQA), policies that optimize the movement and allocation of qubits to avoid the weaker qubits and links, and guide more operations towards the stronger qubits and links. Our evaluations, with a simulation-based model of IBM-Q20, show that Variation-Aware policies can improve the system reliability by up to 1.7x. We also evaluate our policies on the IBM-Q5 machine and demonstrate that our proposal significantly improves the reliability of real systems (up to 1.9X).", "doi": "10.1145/3297858.3304007", "arxiv_id": "1805.10224", "pmid": null, "openalex_id": null, "s2_id": "d5a0b04e42b3f8aafe3fcbfeaccb2350d096969f", "cited_by": 456, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304007&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304007"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304007", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "AcMC 2: Accelerating Markov Chain Monte Carlo Algorithms for Probabilistic Models", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Subho S. Banerjee", "Zbigniew T. Kalbarczyk", "Ravishankar K. Iyer"], "abstract": "Probabilistic models (PMs) are ubiquitously used across a variety of machine learning applications. They have been shown to successfully integrate structural prior information about data and effectively quantify uncertainty to enable the development of more powerful, interpretable, and efficient learning algorithms. This paper presents AcMC2, a compiler that transforms PMs into optimized hardware accelerators (for use in FPGAs or ASICs) that utilize Markov chain Monte Carlo methods to infer and query a distribution of posterior samples from the model. The compiler analyzes statistical dependencies in the PM to drive several optimizations to maximally exploit the parallelism and data locality available in the problem. We demonstrate the use of AcMC2 to implement several learning and inference tasks on a Xilinx Virtex-7 FPGA. AcMC2-generated accelerators provide a 47-100× improvement in runtime performance over a 6-core IBM Power8 CPU and a 8-18× improvement over an NVIDIA K80 GPU. This corresponds to a 753-1600× improvement over the CPU and 248-463× over the GPU in performance-per-watt terms.", "doi": "10.1145/3297858.3304019", "arxiv_id": "https://doi.org/10.1145/3297858.3304019", "pmid": null, "openalex_id": null, "s2_id": "d6cf9c6bf88d16c9bc2b35bd2ae87d6437f7212f", "cited_by": 21, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304019", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304019"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304019", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "CoRAL: Confined Recovery in Distributed Asynchronous Graph Processing", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Keval Vora", "Chen Tian", "Rajiv Gupta", "Ziang Hu"], "abstract": "Existing distributed asynchronous graph processing systems employ checkpointing to capture globally consistent snapshots and rollback all machines to most recent checkpoint to recover from machine failures. In this paper we argue that recovery in distributed asynchronous graph processing does not require the entire execution state to be rolled back to a globally consistent state due to the relaxed asynchronous execution semantics. We define the properties required in the recovered state for it to be usable for correct asynchronous processing and develop CoRAL, a lightweight checkpointing and recovery algorithm. First, this algorithm carries out confined recovery that only rolls back graph execution states of the failed machines to affect recovery. Second, it relies upon lightweight checkpoints that capture locally consistent snapshots with a reduced peak network bandwidth requirement. Our experiments using real-world graphs show that our technique recovers from failures and finishes processing 1.5x to 3.2x faster compared to the traditional asynchronous checkpointing and recovery mechanism when failures impact 1 to 6 machines of a 16 machine cluster. Moreover, capturing locally consistent snapshots significantly reduces intermittent high peak bandwidth usage required to save the snapshots -- the average reduction in 99th percentile bandwidth ranges from 22% to 51% while 1 to 6 snapshot replicas are being maintained.", "doi": "10.1145/3037697.3037747", "arxiv_id": "https://doi.org/10.1145/3037697.3037747", "pmid": null, "openalex_id": null, "s2_id": "d700df1ca00147cda45ef0517376e2da8e1e011e", "cited_by": 37, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037747"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037747", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Prolonging 3D NAND SSD lifetime via read latency relaxation", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chun-Yi Liu", "Yunju Lee", "Myoungsoo Jung", "Mahmut Taylan Kandemir", "Wonil Choi"], "abstract": "The adoption of 3D NAND has significantly increased the SSD density; however, 3D NAND density-increasing techniques, such as extensive stacking of cell layers, can amplify read disturbances and shorten SSD lifetime. From our lifetime-impact characterization on 8 state-of-the-art SSDs, we observe that the 3D TLC/QLC SSDs can be worn-out by low read-only workloads within their warranty period since a huge amount of read disturbance-induced rewrites are performed in the background. To understand alternative read disturbance mitigation opportunities, we also conducted read-latency characterizations on 2 other SSDs without the background rewrite mechanism. The collected results indicate that, without the background rewriting, the read latencies of the majority of data become higher, as the number of reads on the data increases. Motivated by these two characterizations, in this paper, we propose to relax the short read latency constraint on the high-density 3D SSDs. Specifically, our proposal relies on the hint information passed from applications to SSDs that specifies the expected read performance. By doing so, the lifetime consumption caused by the read-induced writes can be reduced, thereby prolonging the SSD lifetime. The detailed experimental evaluations show that our proposal can reduce up to 56% of the rewrite-induced spent-lifetime with only 2% lower performance, under a file-server application.", "doi": "10.1145/3445814.3446733", "arxiv_id": "https://doi.org/10.1145/3445814.3446733", "pmid": null, "openalex_id": null, "s2_id": "d725f51ee6eb73f6a638a0e0e9a0c04e6590499d", "cited_by": 39, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446733"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446733", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Aayush Ankit", "Izzat El Hajj", "Sai Rahul Chalamalasetti", "Geoffrey Ndu", "Martin Foltin", "R. Stanley Williams", "Paolo Faraboschi", "Wen-mei W. Hwu", "John Paul Strachan", "Kaushik Roy", "Dejan S. Milojicic"], "abstract": "Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications. We present the Programmable Ultra-efficient Memristor-based Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability. We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores. We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577 GOPS/s/mm 2 and 837~GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.", "doi": "10.1145/3297858.3304049", "arxiv_id": "1901.10351", "pmid": null, "openalex_id": null, "s2_id": "d74bdbc0bce8ff90e815c74368cdac49b0eb4185", "cited_by": 491, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304049"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304049", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Data Center Power Oversubscription with a Medium Voltage Power Plane and Priority-Aware Capping", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Varun Sakalkar", "Vasileios Kontorinis", "David Landhuis", "Shaohong Li", "Darren De Ronde", "Thomas Blooming", "Anand Ramesh", "James Kennedy", "Christopher Malone", "Jimmy Clidaras", "Parthasarathy Ranganathan"], "abstract": "As major web and cloud service providers continue to accelerate the demand for new data center capacity worldwide, the importance of power oversubscription as a lever to reduce provisioning costs has never been greater. Building on insights from Google-scale deployments, we design and deploy a new architecture across hardware and software to improve power oversubscription significantly. Our design includes (1) a new \\em medium voltage power plane to enable larger power sharing domains (across tens of MW of equipment) and (2) a \\em scalable, fast, and robust power capping service coordinating multiple priorities of workload on every node. Over several years of production deployment, our co-design has enabled \\em power oversubscription of 25% or higher, saving hundreds of millions of dollars of data center costs, while preserving the desired availability and performance of all workloads.", "doi": "10.1145/3373376.3378533", "arxiv_id": "https://doi.org/10.1145/3373376.3378533", "pmid": null, "openalex_id": null, "s2_id": "d81a9212ae6c1c0a90ff03d46f2f2e17a036ae29", "cited_by": 79, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378533", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378533"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378533", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Size Zheng", "Yun Liang", "Shuo Wang", "Renze Chen", "Kaiwen Sheng"], "abstract": "Tensor computation plays a paramount role in a broad range of domains, including machine learning, data analytics, and scientific computing. The wide adoption of tensor computation and its huge computation cost has led to high demand for flexible, portable, and high-performance library implementation on heterogeneous hardware accelerators such as GPUs and FPGAs. However, the current tensor library implementation mainly requires programmers to manually design low-level implementation and optimize from the algorithm, architecture, and compilation perspectives. Such a manual development process often takes months or even years, which falls far behind the rapid evolution of the application algorithms. In this paper, we introduce FlexTensor, which is a schedule exploration and optimization framework for tensor computation on heterogeneous systems. FlexTensor can optimize tensor computation programs without human interference, allowing programmers to only work on high-level programming abstraction without considering the hardware platform details. FlexTensor systematically explores the optimization design spaces that are composed of many different schedules for different hardware. Then, FlexTensor combines different exploration techniques, including heuristic method and machine learning method to find the optimized schedule configuration. Finally, based on the results of exploration, customized schedules are automatically generated for different hardware. In the experiments, we test 12 different kinds of tensor computations with totally hundreds of test cases and FlexTensor achieves average 1.83x performance speedup on NVIDIA V100 GPU compared to cuDNN; 1.72x performance speedup on Intel Xeon CPU compared to MKL-DNN for 2D convolution; 1.5x performance speedup on Xilinx VU9P FPGA compared to OpenCL baselines; 2.21x speedup on NVIDIA V100 GPU compared to the state-of-the-art.", "doi": "10.1145/3373376.3378508", "arxiv_id": "https://doi.org/10.1145/3373376.3378508", "pmid": null, "openalex_id": null, "s2_id": "d84e056bc71e98424912a43f04471600f12804aa", "cited_by": 250, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378508"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378508", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amir M. Rahmani", "Bryan Donyanavard", "Tiago Mück", "Kasra Moazzemi", "Axel Jantsch", "Onur Mutlu", "Nikil D. Dutt"], "abstract": "Resource management strategies for many-core systems need to enable sharing of resources such as power, processing cores, and memory bandwidth while coordinating the priority and significance of system- and application-level objectives at runtime in a scalable and robust manner. State-of-the-art approaches use heuristics or machine learning for resource management, but unfortunately lack formalism in providing robustness against unexpected corner cases. While recent efforts deploy classical control-theoretic approaches with some guarantees and formalism, they lack scalability and autonomy to meet changing runtime goals. We present SPECTR, a new resource management approach for many-core systems that leverages formal supervisory control theory (SCT) to combine the strengths of classical control theory with state-of-the-art heuristic approaches to efficiently meet changing runtime goals. SPECTR is a scalable and robust control architecture and a systematic design flow for hierarchical control of many-core systems. SPECTR leverages SCT techniques such as gain scheduling to allow autonomy for individual controllers. It facilitates automatic synthesis of the high-level supervisory controller and its property verification. We implement SPECTR on an Exynos platform containing ARM»s big.LITTLE-based heterogeneous multi-processor (HMP) and demonstrate that SPECTR»s use of SCT is key to managing multiple interacting resources (e.g., chip power and processing cores) in the presence of competing objectives (e.g., satisfying QoS vs. power capping). The principles of SPECTR are easily applicable to any resource type and objective as long as the management problem can be modeled using dynamical systems theory (e.g., difference equations), discrete-event dynamic systems, or fuzzy dynamics.", "doi": "10.1145/3173162.3173199", "arxiv_id": "https://doi.org/10.1145/3173162.3173199", "pmid": null, "openalex_id": null, "s2_id": "d8629e7450f3dadbda1e40621fcec2850fe03fd5", "cited_by": 205, "type": "conference", "is_oa": true, "pdf_urls": ["https://zenodo.org/record/3493702", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173199"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173199", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "True IOMMU Protection from DMA Attacks: When Copy is Faster than Zero Copy", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alex Markuze", "Adam Morrison", "Dan Tsafrir"], "abstract": "Malicious I/O devices might compromise the OS using DMAs. The OS therefore utilizes the IOMMU to map and unmap every target buffer right before and after its DMA is processed, thereby restricting DMAs to their designated locations. This usage model, however, is not truly secure for two reasons: (1) it provides protection at page granularity only, whereas DMA buffers can reside on the same page as other data; and (2) it delays DMA buffer unmaps due to performance considerations, creating a vulnerability window in which devices can access in-use memory. We propose that OSes utilize the IOMMU differently, in a manner that eliminates these two flaws. Our new usage model restricts device access to a set of shadow DMA buffers that are never unmapped, and it copies DMAed data to/from these buffers, thus providing sub-page protection while eliminating the aforementioned vulnerability window. Our key insight is that the cost of interacting with, and synchronizing access to the slow IOMMU hardware---required for zero-copy protection against devices---make copying preferable to zero-copying.", "doi": "10.1145/2872362.2872379", "arxiv_id": "https://doi.org/10.1145/2872362.2872379", "pmid": null, "openalex_id": null, "s2_id": "d896ef2a393eb8022446a7d8951432ac8f424bbd", "cited_by": 68, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872379"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872379", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "BayesPerf: minimizing performance monitoring errors using Bayesian statistics", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Subho S. Banerjee", "Saurabh Jha", "Zbigniew Kalbarczyk", "Ravishankar K. Iyer"], "abstract": "  Hardware performance counters (HPCs) that measure low-level architectural and\nmicroarchitectural events provide dynamic contextual information about the\nstate of the system. However, HPC measurements are error-prone due to non\ndeterminism (e.g., undercounting due to event multiplexing, or OS\ninterrupt-handling behaviors). In this paper, we present BayesPerf, a system\nfor quantifying uncertainty in HPC measurements by using a domain-driven\nBayesian model that captures microarchitectural relationships between HPCs to\njointly infer their values as probability distributions. We provide the design\nand implementation of an accelerator that allows for low-latency and low-power\ninference of the BayesPerf model for x86 and ppc64 CPUs. BayesPerf reduces the\naverage error in HPC measurements from 40.1% to 7.6% when events are being\nmultiplexed. The value of BayesPerf in real-time decision-making is illustrated\nwith a simple example of scheduling of PCIe transfers.\n", "doi": "10.1145/3445814.3446739", "arxiv_id": "2102.10837", "pmid": null, "openalex_id": null, "s2_id": "d9af256258075f2096ac7064337457425bc50844", "cited_by": 19, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2102.10837", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446739"], "github": [], "sources": ["semanticscholar", "papervault", "open-arxiv"], "landing": "https://doi.org/10.1145/3445814.3446739", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems", "journal_ref": "Proceedings of the Twenty-Sixth International Conference on\n  Architectural Support for Programming Languages and Operating Systems (ASPLOS\n  21), 2021", "categories": "cs.DC cs.AI cs.AR cs.PF"}
{"title": "Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jinchun Kim", "Elvira Teran", "Paul V. Gratz", "Daniel A. Jiménez", "Seth H. Pugsley", "Chris Wilkerson"], "abstract": "Data prefetching and cache replacement algorithms have been intensively studied in the design of high performance microprocessors. Typically, the data prefetcher operates in the private caches and does not interact with the replacement policy in the shared Last-Level Cache (LLC). Similarly, most replacement policies do not consider demand and prefetch requests as different types of requests. In particular, program counter (PC)-based replacement policies cannot learn from prefetch requests since the data prefetcher does not generate a PC value. PC-based policies can also be negatively affected by compiler optimizations. In this paper, we propose a holistic cache management technique called Kill-the-PC (KPC) that overcomes the weaknesses of traditional prefetching and replacement policy algorithms. KPC cache management has three novel contributions. First, a prefetcher which approximates the future use distance of prefetch requests based on its prediction confidence. Second, a simple replacement policy provides similar or better performance than current state-of-the-art PC-based prediction using global hysteresis. Third, KPC integrates prefetching and replacement policy into a whole system which is greater than the sum of its parts. Information from the prefetcher is used to improve the performance of the replacement policy and vice-versa. Finally, KPC removes the need to propagate the PC through entire on-chip cache hierarchy while providing a holistic cache management approach with better performance than state-of-the-art PC-, and non-PC-based schemes. Our evaluation shows that KPC provides 8% better performance than the best combination of existing prefetcher and replacement policy for multi-core workloads.", "doi": "10.1145/3037697.3037701", "arxiv_id": "https://doi.org/10.1145/3037697.3037701", "pmid": null, "openalex_id": null, "s2_id": "dae646a11a1132a87261c58a4b9fb0e6e51f9532", "cited_by": 65, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037701&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037701"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037701", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Reducing solid-state drive read latency by optimizing read-retry", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jisung Park", "Myungsuk Kim", "Myoungjun Chun", "Lois Orosa", "Jihong Kim", "Onur Mutlu"], "abstract": "3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly in-crease the read latency of an SSD by introducing multiple retry steps that read the target page again with adjusted read-reference voltage values. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash memory chips, we find new opportunities to reduce the read-retry latency by exploiting two advanced features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ command and 2) strong ECC engine. First, we can reduce the read-retry latency using the advanced CACHE READ command that allows a NAND flash chip to perform consecutive reads in a pipelined manner. Second, there exists a large ECC-capability margin in the final retry step that can be used for reducing the chip-level read latency. Based on our new findings, we develop two new techniques that effectively reduce the read-retry latency: 1) Pipelined Read-Retry (PR²) and 2) Adaptive Read-Retry (AR²). PR² reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR² shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation using twelve real-world workloads shows that our proposal improves SSD response time by up to 31.5% (17% on average)over a state-of-the-art baseline with only small changes to the SSD controller.", "doi": "10.1145/3445814.3446719", "arxiv_id": "2104.09611", "pmid": null, "openalex_id": null, "s2_id": "db2c7eb1bad3ff523d303cf34a16cfa90fec680d", "cited_by": 73, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2104.09611", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446719"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446719", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Logical abstractions for noisy variational Quantum algorithm simulation", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yipeng Huang", "Steven Holtzen", "Todd D. Millstein", "Guy Van den Broeck", "Margaret Martonosi"], "abstract": "Due to the unreliability and limited capacity of existing quantum computer prototypes, quantum circuit simulation continues to be a vital tool for validating next generation quantum computers and for studying variational quantum algorithms, which are among the leading candidates for useful quantum computation. Existing quantum circuit simulators do not address the common traits of variational algorithms, namely: 1) their ability to work with noisy qubits and operations, 2) their repeated execution of the same circuits but with different parameters, and 3) the fact that they sample from circuit final wavefunctions to drive a classical optimization routine. We present a quantum circuit simulation toolchain based on logical abstractions targeted for simulating variational algorithms. Our proposed toolchain encodes quantum amplitudes and noise probabilities in a probabilistic graphical model, and it compiles the circuits to logical formulas that support efficient repeated simulation of and sampling from quantum circuits for different parameters. Compared to state-of-the-art state vector and density matrix quantum circuit simulators, our simulation approach offers greater performance when sampling from noisy circuits with at least eight to 20 qubits and with around 12 operations on each qubit, making the approach ideal for simulating near-term variational quantum algorithms. And for simulating noise-free shallow quantum circuits with 32 qubits, our simulation approach offers a 66× reduction in sampling cost versus quantum circuit simulation techniques based on tensor network contraction.", "doi": "10.1145/3445814.3446750", "arxiv_id": "2103.17226", "pmid": null, "openalex_id": null, "s2_id": "db403ccedcdc86e186af06bd5e059755590df1a5", "cited_by": 26, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446750", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446750"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446750", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Espresso: Brewing Java For More Non-Volatility with Non-volatile Memory", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mingyu Wu", "Ziming Zhao", "Haoyu Li", "Heting Li", "Haibo Chen", "Binyu Zang", "Haibing Guan"], "abstract": "Fast, byte-addressable non-volatile memory (NVM) embraces both near-DRAM latency and disk-like persistence, which has generated considerable interests to revolutionize system software stack and programming models. However, it is less understood how NVM can be combined with managed runtime like Java virtual machine (JVM) to ease persistence management. This paper proposes Espresso, a holistic extension to Java and its runtime, to enable Java programmers to exploit NVM for persistence management with high performance. Espresso first provides a general persistent heap design called Persistent Java Heap (PJH) to manage persistent data as normal Java objects. The heap is then strengthened with a recoverable mechanism to provide crash consistency for heap metadata. Espresso further provides a new abstraction called Persistent Java Object (PJO) to provide an easy-to-use but safe persistence programming model for programmers to persist application data. Evaluation confirms that Espresso significantly outperforms state-of-art NVM support for Java (i.e., JPA and PCJ) while being compatible to data structures in existing Java programs.", "doi": "10.1145/3173162.3173201", "arxiv_id": "1710.09968", "pmid": null, "openalex_id": null, "s2_id": "db57257e6b051e0f97d35209cc5aee0909cde1f1", "cited_by": 60, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173201"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173201", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Debate", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252405", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "dbf59f0fcd4c8faa94aeffb8a4765f57a3467a38", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sagar Karandikar", "Albert J. Ou", "Alon Amid", "Howard Mao", "Randy H. Katz", "Borivoje Nikolic", "Krste Asanovic"], "abstract": "Achieving high-performance when developing specialized hardware/software systems requires understanding and improving not only core compute kernels, but also intricate and elusive system-level bottlenecks. Profiling these bottlenecks requires both high-fidelity introspection and the ability to run sufficiently many cycles to execute complex software stacks, a challenging combination. In this work, we enable agile full-system performance optimization for hardware/software systems with FirePerf, a set of novel out-of-band system-level performance profiling capabilities integrated into the open-source FireSim FPGA-accelerated hardware simulation platform. Using out-of-band call stack reconstruction and automatic performance counter insertion, FirePerf enables introspecting into hardware and software at appropriate abstraction levels to rapidly identify opportunities for software optimization and hardware specialization, without disrupting end-to-end system behavior like traditional profiling tools. We demonstrate the capabilities of FirePerf with a case study that optimizes the hardware/software stack of an open-source RISC-V SoC with an Ethernet NIC to achieve 8x end-to-end improvement in achievable bandwidth for networking applications running on Linux. We also deploy a RISC-V Linux kernel optimization discovered with FirePerf on commercial RISC-V silicon, resulting in up to 1.72x improvement in network performance.", "doi": "10.1145/3373376.3378455", "arxiv_id": "https://doi.org/10.1145/3373376.3378455", "pmid": null, "openalex_id": null, "s2_id": "dd5dd6f8af32e3832682f9ebac839e6580fe06a9", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378455", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378455"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378455", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "VSync: push-button verification and optimization for synchronization primitives on weak memory models", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jonas Oberhauser", "Rafael Lourenco de Lima Chehab", "Diogo Behrens", "Ming Fu", "Antonio Paolillo", "Lilith Oberhauser", "Koustubha Bhat", "Yuzhong Wen", "Haibo Chen", "Jaeho Kim", "Viktor Vafeiadis"], "abstract": "Implementing highly efficient and correct synchronization primitives on modern Weak Memory Model (WMM) architectures, such as ARM and RISC-V, is very difficult even for human experts. We introduce VSync, a framework to assist in optimizing and verifying synchronization primitives on WMM architectures. VSync automatically detects missing and overly-constrained barriers, while ensuring essential safety and liveness properties. VSync relies on two novel techniques: 1) Adaptive Linear Relaxation (ALR), which utilizes barrier monotonicity and speculation to quickly find a correct maximally-relaxed barrier combination; and 2) Await Model Checking (AMC), which for the first time makes it possible to check termination of await loops on WMMs.", "doi": "10.1145/3445814.3446748", "arxiv_id": "https://doi.org/10.1145/3445814.3446748", "pmid": null, "openalex_id": null, "s2_id": "ddf4db6d66a77237d0e6b4f6942d7be4a4b3bc09", "cited_by": 48, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446748", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446748"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446748", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "FCatch: Automatically Detecting Time-of-fault Bugs in Cloud Systems", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Haopeng Liu", "Xu Wang", "Guangpu Li", "Shan Lu", "Feng Ye", "Chen Tian"], "abstract": "It is crucial for distributed systems to achieve high availability. Unfortunately, this is challenging given the common component failures (i.e., faults). Developers often cannot anticipate all the timing conditions and system states under which a fault might occur, and introduce time-of-fault (TOF) bugs that only manifest when a node crashes or a message drops at a special moment. Although challenging, detecting TOF bugs is fundamental to developing highly available distributed systems. Unlike previous work that relies on fault injection to expose TOF bugs, this paper carefully models TOF bugs as a new type of concurrency bugs, and develops FCatch to automatically predict TOF bugs by observing correct execution. Evaluation on representative cloud systems shows that FCatch is effective, accurately finding severe TOF bugs.", "doi": "10.1145/3173162.3177161", "arxiv_id": "https://doi.org/10.1145/3173162.3177161", "pmid": null, "openalex_id": null, "s2_id": "dec04aeee6d8cc8ebdb1bf295d3796bd259f4064", "cited_by": 38, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177161"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177161", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Dirigent: Enforcing QoS for Latency-Critical Tasks on Shared Multicore Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Haishan Zhu", "Mattan Erez"], "abstract": "Latency-critical applications suffer from both average performance degradation and reduced completion time predictability when collocated with batch tasks. Such variation forces the system to overprovision resources to ensure Quality of Service (QoS) for latency-critical tasks, degrading overall system throughput. We explore the causes of this variation and exploit the opportunities of mitigating variation directly to simultaneously improve both QoS and utilization. We develop, implement, and evaluate Dirigent, a lightweight performance-management runtime system that accurately controls the QoS of latency-critical applications at fine time scales, leveraging existing architecture mechanisms. We evaluate Dirigent on a real machine and show that it is significantly more effective than configurations representative of prior schemes.", "doi": "10.1145/2872362.2872394", "arxiv_id": "https://doi.org/10.1145/2872362.2872394", "pmid": null, "openalex_id": null, "s2_id": "df26dfe6268acb3388e65a0762d46441499763ec", "cited_by": 137, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872394"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872394", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "High-Density Image Storage Using Approximate Memory Cells", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Qing Guo", "Karin Strauss", "Luis Ceze", "Henrique S. Malvar"], "abstract": "This paper proposes tailoring image encoding for an approximate storage substrate. We demonstrate that indiscriminately storing encoded images in approximate memory generates unacceptable and uncontrollable quality degradation. The key finding is that errors in the encoded bit streams have non-uniform impact on the decoded image quality. We develop a methodology to determine the relative importance of encoded bits and store them in an approximate storage substrate. The storage cells are optimized to reduce error rate via biasing and are tuned to meet the desired reliability requirement via selective error correction. In a case study with the progressive transform codec (PTC), a precursor to JPEG XR, the proposed approximate image storage system exhibits a 2.7x increase in density of pixels per silicon volume under bounded error rates, and this achievement is additive to the storage savings of PTC compression.", "doi": "10.1145/2872362.2872413", "arxiv_id": "https://doi.org/10.1145/2872362.2872413", "pmid": null, "openalex_id": null, "s2_id": "e05cab870bf877a803be875d0e3bc5b2188892e3", "cited_by": 63, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872413"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872413", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "TxRace: Efficient Data Race Detection Using Commodity Hardware Transactional Memory", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tong Zhang", "Dongyoon Lee", "Changhee Jung"], "abstract": "Detecting data races is important for debugging shared-memory multithreaded programs, but the high runtime overhead prevents the wide use of dynamic data race detectors. This paper presents TxRace, a new software data race detector that leverages commodity hardware transactional memory (HTM) to speed up data race detection. TxRace instruments a multithreaded program to transform synchronization-free regions into transactions, and exploits the conflict detection mechanism of HTM for lightweight data race detection at runtime. However, the limitations of the current best-effort commodity HTMs expose several challenges in using them for data race detection: (1) lack of ability to pinpoint racy instructions, (2) false positives caused by cache line granularity of conflict detection, and (3) transactional aborts for non-conflict reasons (e.g., capacity or unknown). To overcome these challenges, TxRace performs lightweight HTM-based data race detection at first, and occasionally switches to slow yet precise data race detection only for the small fraction of execution intervals in which potential races are reported by HTM. According to the experimental results, TxRace reduces the average runtime overhead of dynamic data race detection from 11.68x to 4.65x with only a small number of false negatives.", "doi": "10.1145/2872362.2872384", "arxiv_id": "https://doi.org/10.1145/2872362.2872384", "pmid": null, "openalex_id": null, "s2_id": "e164be93e107379610c1a5a39f038de69e41ee7a", "cited_by": 35, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872384"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872384", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Sugar: Secure GPU Acceleration in Web Browsers", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhihao Yao", "Zongheng Ma", "Yingtong Liu", "Ardalan Amiri Sani", "Aparna Chandramowlishwaran"], "abstract": "Modern personal computers have embraced increasingly powerful Graphics Processing Units (GPUs). Recently, GPU-based graphics acceleration in web apps (i.e., applications running inside a web browser) has become popular. WebGL is the main effort to provide OpenGL-like graphics for web apps and it is currently used in 53% of the top-100 websites. Unfortunately, WebGL has posed serious security concerns as several attack vectors have been demonstrated through WebGL. Web browsers» solutions to these attacks have been reactive: discovered vulnerabilities have been patched and new runtime security checks have been added. Unfortunately, this approach leaves the system vulnerable to zero-day vulnerability exploits, especially given the large size of the Trusted Computing Base of the graphics plane. We present Sugar, a novel operating system solution that enhances the security of GPU acceleration for web apps by design. The key idea behind Sugar is using a dedicated virtual graphics plane for a web app by leveraging modern GPU virtualization solutions. A virtual graphics plane consists of a dedicated virtual GPU (or vGPU) as well as all the software graphics stack (including the device driver). Sugar enhances the system security since a virtual graphics plane is fully isolated from the rest of the system. Despite GPU virtualization overhead, we show that Sugar achieves high performance. Moreover, unlike current systems, Sugar is able to use two underlying physical GPUs, when available, to co-render the User Interface (UI): one GPU is used to provide virtual graphics planes for web apps and the other to provide the primary graphics plane for the rest of the system. Such a design not only provides strong security guarantees, it also provides enhanced performance isolation.", "doi": "10.1145/3173162.3173186", "arxiv_id": "https://doi.org/10.1145/3173162.3173186", "pmid": null, "openalex_id": null, "s2_id": "e1e540343f87c8d8e8d08c721efae36e899bd7cf", "cited_by": 20, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3173162.3173186", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173186"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173186", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HMC: Model Checking for Hardware Memory Models", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Michalis Kokologiannakis", "Viktor Vafeiadis"], "abstract": "Stateless Model Checking (SMC) is an effective technique for verifying safety properties of a concurrent program by systematically exploring all of its executions. While SMC has been extended to handle hardware memory models like x86-TSO, it does not adequately support models that allow load buffering behaviours, such as the POWER, ARMv7, ARMv8, and RISC-V models. Existing SMC tools either do not consider such behaviours in the name of efficiency, or do not scale so well due to the extra complexity induced by these behaviours.", "doi": "10.1145/3373376.3378480", "arxiv_id": "https://doi.org/10.1145/3373376.3378480", "pmid": null, "openalex_id": null, "s2_id": "e2646b037b24069a0a798aecabae25ad7a1b4835", "cited_by": 43, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378480", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378480"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378480", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "BranchScope: A New Side-Channel Attack on Directional Branch Predictor", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dmitry Evtyushkin", "Ryan Riley", "Nael B. Abu-Ghazaleh", "Dmitry Ponomarev"], "abstract": "We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional branch instruction in a victim program by manipulating the shared directional branch predictor. The directional component of the branch predictor stores the prediction on a given branch (taken or not-taken) and is a different component from the branch target buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional branch predictor, expanding our understanding of the side channel vulnerability of the branch prediction unit. Our attack targets complex hybrid branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.", "doi": "10.1145/3173162.3173204", "arxiv_id": "https://doi.org/10.1145/3173162.3173204", "pmid": null, "openalex_id": null, "s2_id": "e3d8c6cf9109b262d4c5275f2254e2427ee48a88", "cited_by": 338, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173204"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173204", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Keynote: Developing our Quantum Future", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Krysta M. Svore"], "abstract": "In 1981, Richard Feynman proposed a device called a 'quantum computer' to take advantage of the laws of quantum physics to achieve computational speed-ups over classical methods. Quantum computing promises to revolutionize how and what we compute. Over the course of three decades, quantum algorithms have been developed that offer fast solutions to problems in a variety of fields including number theory, optimization, chemistry, physics, and materials science. Quantum devices have also significantly advanced such that components of a scalable quantum computer have been demonstrated; the promise of implementing quantum algorithms is in our near future. I will attempt to explain some of the mysteries of this disruptive, revolutionary computational paradigm and how it will transform our digital age.", "doi": "10.1145/3297858.3320434", "arxiv_id": "https://doi.org/10.1145/3297858.3320434", "pmid": null, "openalex_id": null, "s2_id": "e533536e8a124227eb2b9e4d2918262c08e835e0", "cited_by": 0, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3320434&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3320434"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3320434", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Brain Inspired Computing", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/2980024.2872417", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "e5a91cb62ab5bf153530452ca0bde19bc0b1fec1", "cited_by": 1, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DLibOS: Performance and Protection with a Network-on-Chip", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Stephen Mallon", "Vincent Gramoli", "Guillaume Jourjon"], "abstract": "A long body of research work has led to the conjecture that highly efficient IO processing at user-level would necessarily violate protection. In this paper, we debunk this myth by introducing DLibOS a new paradigm that consists of distributing a library OS on specialized cores to achieve performance and protection at the user-level. Its main novelty consists of leveraging network-on-chip to allow hardware message passing, rather than context switches, for communication between different address spaces. To demonstrate the feasibility of our approach, we implement a driver and a network stack at user-level on a Tilera many-core machine. We define a novel asynchronous socket interface and partition the memory such that the reception, the transmission and the application modify isolated regions. Our high performance results of 4.2 and 3.1 million requests per second obtained on a webserver and the Memcached applications, respectively, confirms the relevance of our design decisions. Finally, we compare DLibOS against a non-protected user-level network stack and show that protection comes at a negligible cost.", "doi": "10.1145/3173162.3173209", "arxiv_id": "https://doi.org/10.1145/3173162.3173209", "pmid": null, "openalex_id": null, "s2_id": "e6554d2bbd27df1f2dc66fa2bd2e010b60193c35", "cited_by": 7, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173209"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173209", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "SpaceJMP: Programming with Multiple Virtual Address Spaces", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Izzat El Hajj", "Alexander Merritt", "Gerd Zellweger", "Dejan S. Milojicic", "Reto Achermann", "Paolo Faraboschi", "Wen-mei W. Hwu", "Timothy Roscoe", "Karsten Schwan"], "abstract": "Memory-centric computing demands careful organization of the virtual address space, but traditional methods for doing so are inflexible and inefficient. If an application wishes to address larger physical memory than virtual address bits allow, if it wishes to maintain pointer-based data structures beyond process lifetimes, or if it wishes to share large amounts of memory across simultaneously executing processes, legacy interfaces for managing the address space are cumbersome and often incur excessive overheads. We propose a new operating system design that promotes virtual address spaces to first-class citizens, enabling process threads to attach to, detach from, and switch between multiple virtual address spaces. Our work enables data-centric applications to utilize vast physical memory beyond the virtual range, represent persistent pointer-rich data structures without special pointer representations, and share large amounts of memory between processes efficiently.", "doi": "10.1145/2872362.2872366", "arxiv_id": "https://doi.org/10.1145/2872362.2872366", "pmid": null, "openalex_id": null, "s2_id": "e68e2c01b67ec9bf88e0cc552cf216e7b87cf5d3", "cited_by": 48, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872366"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872366", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Maciej Besta", "Syed Minhaj Hassan", "Sudhakar Yalamanchili", "Rachata Ausavarungnirun", "Onur Mutlu", "Torsten Hoefler"], "abstract": "Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency and scalability compared to the state-of-the-art. The key idea is to use two concepts from graph and number theory, degree-diameter graphs combined with non-prime finite fields, to enable the smallest number of ports for a given core count. SN is inspired by state-of-the-art off-chip topologies; it identifies and distills their advantages for NoC settings while solving several key issues that lead to significant overheads on-chip. SN provides NoC-specific layouts, which further enhance area/energy efficiency. We show how to augment SN with state-of-the-art router microarchitecture schemes such as Elastic Links, to make the network even more scalable and efficient. Our extensive experimental evaluations show that SN outperforms both traditional low-radix topologies (e.g., meshes and tori) and modern high-radix networks (e.g., various Flattened Butterflies) in area, latency, throughput, and static/dynamic power consumption for both synthetic and real workloads. SN provides a promising direction in scalable and energy-efficient NoC topologies.", "doi": "10.1145/3173162.3177158", "arxiv_id": "2010.10683", "pmid": null, "openalex_id": null, "s2_id": "e7468364fea4e5bf51c562e48197a1e01893a62c", "cited_by": 51, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3177158"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3177158", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Prague: High-Performance Heterogeneity-Aware Asynchronous Decentralized Training", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Qinyi Luo", "Jiaao He", "Youwei Zhuo", "Xuehai Qian"], "abstract": "Distributed deep learning training usually adopts All-Reduce as the synchronization mechanism for data parallel algorithms due to its high performance in homogeneous environment. However, its performance is bounded by the slowest worker among all workers. For this reason, it is significantly slower in heterogeneous settings. AD-PSGD, a newly proposed synchronization method which provides numerically fast convergence and heterogeneity tolerance, suffers from deadlock issues and high synchronization overhead. Is it possible to get the best of both worlds --- designing a distributed training method that has both high performance like All-Reduce in homogeneous environment and good heterogeneity tolerance like AD-PSGD?", "doi": "10.1145/3373376.3378499", "arxiv_id": "https://doi.org/10.1145/3373376.3378499", "pmid": null, "openalex_id": null, "s2_id": "e7dd73e84efa11f0b0bc7654c93f7fc19058f5d0", "cited_by": 82, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378499", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378499"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378499", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Dimensionality-Aware Redundant SIMT Instruction Elimination", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tsung Tai Yeh", "Roland N. Green", "Timothy G. Rogers"], "abstract": "In massively multithreaded architectures, redundantly executing the same instruction with the same operands in different threads is a significant source of inefficiency. This paper introduces Dimensionality-Aware Redundant SIMT Instruction Elimination (DARSIE), a non-speculative instruction skipping mechanism to reduce redundant operations in GPUs. DARSIE uses static markings from the compiler and information obtained at kernel launch time to skip redundant instructions before they are fetched, keeping them out of the pipeline. DARSIE exploits a new observation that there is significant redundancy across warp instructions in multi-dimensional threadblocks.", "doi": "10.1145/3373376.3378520", "arxiv_id": "https://doi.org/10.1145/3373376.3378520", "pmid": null, "openalex_id": null, "s2_id": "ea0bd365abfb84096677f6dabf816e32cda3b764", "cited_by": 17, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378520"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378520", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Exploiting Dynamic Thermal Energy Harvesting for Reusing in Smartphone with Mobile Applications", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yuting Dai", "Tao Li", "Benyong Liu", "Mingcong Song", "Huixiang Chen"], "abstract": "Recently, mobile applications have gradually become performance- and resource- intensive, which results in a massive battery power drain and high surface temperature, and further degrades the user experience. Thus, high power consumption and surface over-heating have been considered as a severe challenge to smartphone design. In this paper, we propose DTEHR, a mobile Dynamic Thermal Energy Harvesting Reusing framework to tackle this challenge. The approach is sustainable in that it generates energy using dynamic Thermoelectric Generators (TEGs). The generated energy not only powers Thermoelectric Coolers (TECs) for cooling down hot-spots, but also recharges micro-supercapacitors (MSCs) for extended smartphone usage. To analyze thermal characteristics and evaluate DTEHR across real-world applications, we build MPPTAT (Multi-comPonent Power and Thermal Analysis Tool), a power and thermal analyzing tool for Android. The result shows that DTEHR reduces the temperature differences between hot areas and cold areas up to 15.4°C (internal) and 7°C (surface). With TEC-based hot-spots cooling, DTEHR reduces the temperature of the surface and internal hot-spots by an average of 8° and 12.8mW respectively. With dynamic TEGs, DTEHR generates 2.7-15mW power, more than hundreds of times of power that TECs need to cool down hot-spots. Thus, extra-generated power can be stored into MSCs to prolong battery life.", "doi": "10.1145/3173162.3173188", "arxiv_id": "https://doi.org/10.1145/3173162.3173188", "pmid": null, "openalex_id": null, "s2_id": "ea47b712d835815e0457297139f072f911e181d3", "cited_by": 11, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3296957.3173188", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173188"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173188", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Gamma: leveraging Gustavson’s algorithm to accelerate sparse matrix multiplication", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Guowei Zhang", "Nithya Attaluri", "Joel S. Emer", "Daniel Sánchez"], "abstract": "Sparse matrix-sparse matrix multiplication (spMspM) is at the heart of a wide range of scientific and machine learning applications. spMspM is inefficient on general-purpose architectures, making accelerators attractive. However, prior spMspM accelerators use inner- or outer-product dataflows that suffer poor input or output reuse, leading to high traffic and poor performance. These prior accelerators have not explored Gustavson's algorithm, an alternative spMspM dataflow that does not suffer from these problems but features irregular memory access patterns that prior accelerators do not support.", "doi": "10.1145/3445814.3446702", "arxiv_id": "https://doi.org/10.1145/3445814.3446702", "pmid": null, "openalex_id": null, "s2_id": "ea76c776b3cd3ad448572999ad3b4323abe47453", "cited_by": 175, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446702", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446702"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446702", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Corundum: statically-enforced persistent memory safety", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Morteza Hoseinzadeh", "Steven Swanson"], "abstract": "Fast, byte-addressable, persistent main memories (PM) make it possible to build complex data structures that can survive system failures. Programming for PM is challenging, not least because it combines well-known programming challenges like locking, memory management, and pointer safety with novel PM-specific bug types. It also requires logging updates to PM to facilitate recovery after a crash. A misstep in any of these areas can corrupt data, leak resources, or prevent successful recovery after a crash. Existing PM libraries in a variety of languages -- C, C++, Java, Go -- simplify some of these problems, but they still require the programmer to learn (and flawlessly apply) complex rules to ensure correctness. Opportunities for data-destroying bugs abound.", "doi": "10.1145/3445814.3446710", "arxiv_id": "https://doi.org/10.1145/3445814.3446710", "pmid": null, "openalex_id": null, "s2_id": "eb35d410273fed8da1d5ff60ef6bfc05b514499a", "cited_by": 31, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446710", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446710"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446710", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Keynote Address II", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248622", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "eb8ae584e8e58e506fc1b7c1c71f8d5959d26895", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "An Event-Triggered Programmable Prefetcher for Irregular Workloads", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sam Ainsworth", "Timothy M. Jones"], "abstract": "Many modern workloads compute on large amounts of data, often with irregular memory accesses. Current architectures perform poorly for these workloads, as existing prefetching techniques cannot capture the memory access patterns; these applications end up heavily memory-bound as a result. Although a number of techniques exist to explicitly configure a prefetcher with traversal patterns, gaining significant speedups, they do not generalise beyond their target data structures. Instead, we propose an event-triggered programmable prefetcher combining the flexibility of a general-purpose computational unit with an event-based programming model, along with compiler techniques to automatically generate events from the original source code with annotations. This allows more complex fetching decisions to be made, without needing to stall when intermediate results are required. Using our programmable prefetching system, combined with small prefetch kernels extracted from applications, we achieve an average 3.0x speedup in simulation for a variety of graph, database and HPC workloads.", "doi": "10.1145/3173162.3173189", "arxiv_id": "https://doi.org/10.1145/3173162.3173189", "pmid": null, "openalex_id": null, "s2_id": "ebf3de9cdeb4db0d481d94a227fb554342b51efb", "cited_by": 75, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.17863/cam.21280", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173189"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173189", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 1A: Multicore", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3252391", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "ec580240e3e291c60da71b206defdddcdcf6bc89", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Nightcore: efficient and scalable serverless computing for latency-sensitive, interactive microservices", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhipeng Jia", "Emmett Witchel"], "abstract": "The microservice architecture is a popular software engineering approach for building flexible, large-scale online services. Serverless functions, or function as a service (FaaS), provide a simple programming model of stateless functions which are a natural substrate for implementing the stateless RPC handlers of microservices, as an alternative to containerized RPC servers. However, current serverless platforms have millisecond-scale runtime overheads, making them unable to meet the strict sub-millisecond latency targets required by existing interactive microservices. We present Nightcore, a serverless function runtime with microsecond-scale overheads that provides container-based isolation between functions. Nightcore’s design carefully considers various factors having microsecond-scale overheads, including scheduling of function requests, communication primitives, threading models for I/O, and concurrent function executions. Nightcore currently supports serverless functions written in C/C++, Go, Node.js, and Python. Our evaluation shows that when running latency-sensitive interactive microservices, Nightcore achieves 1.36×–2.93× higher throughput and up to 69% reduction in tail latency.", "doi": "10.1145/3445814.3446701", "arxiv_id": "https://doi.org/10.1145/3445814.3446701", "pmid": null, "openalex_id": null, "s2_id": "ec590215e04ede80bb98c95fc2d80d36038f697b", "cited_by": 268, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3445814.3446701", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446701"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446701", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "WSMeter: A Performance Evaluation Methodology for Google's Production Warehouse-Scale Computers", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jaewon Lee", "Changkyu Kim", "Kun Lin", "Liqun Cheng", "Rama Govindaraju", "Jangwoo Kim"], "abstract": "Evaluating the comprehensive performance of a warehouse-scale computer (WSC) has been a long-standing challenge. Traditional load-testing benchmarks become ineffective because they cannot accurately reproduce the behavior of thousands of distinct jobs co-located on a WSC. We therefore evaluate WSCs using actual job behaviors in live production environments. From our experience of developing multiple generations of WSCs, we identify two major challenges of this approach: 1) the lack of a holistic metric that incorporates thousands of jobs and summarizes the performance, and 2) the high costs and risks of conducting an evaluation in a live environment. To address these challenges, we propose WSMeter, a cost-effective methodology to accurately evaluate a WSC's performance using a live production environment. We first define a new metric which accurately represents a WSC's overall performance, taking a wide variety of unevenly distributed jobs into account. We then propose a model to statistically embrace the performance variance inherent in WSCs, to conduct an evaluation with minimal costs and risks. We present three real-world use cases to prove the effectiveness of WSMeter. In the first two cases, WSMeter accurately discerns 7% and 1% performance improvements from WSC upgrades using only 0.9% and 6.6% of the machines in the WSCs, respectively. We emphasize that naive statistical comparisons incur much higher evaluation costs (> 4 times) and sometimes even fail to distinguish subtle differences. The third case shows that a cloud customer hosting two services on our WSC quantifies the performance benefits of software optimization (+9.3%) with minimal overheads (2.3% of the service capacity).", "doi": "10.1145/3173162.3173196", "arxiv_id": "https://doi.org/10.1145/3173162.3173196", "pmid": null, "openalex_id": null, "s2_id": "ec7cd4b8be631f2000cf4a4bb059186b6fff85c6", "cited_by": 24, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3173162.3173196", "https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173196"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173196", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "DAMN: Overhead-Free IOMMU Protection for Networking", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alex Markuze", "Igor Smolyar", "Adam Morrison", "Dan Tsafrir"], "abstract": "DMA operations can access memory buffers only if they are \"mapped\" in the IOMMU, so operating systems protect themselves against malicious/errant network DMAs by mapping and unmapping each packet immediately before/after it is DMAed. This approach was recently found to be riskier and less performant than keeping packets non-DMAable and instead copying their content to/from permanently-mapped buffers. Still, the extra copy hampers performance of multi-gigabit networking. We observe that achieving protection at the DMA (un)map boundary is needlessly constraining, as devices must be prevented from changing the data only after the kernel reads it. So there is no real need to switch ownership of buffers between kernel and device at the DMA (un)mapping layer, as opposed to the approach taken by all existing IOMMU protection schemes. We thus eliminate the extra copy by (1)~implementing a new allocator called DMA-Aware Malloc for Networking (DAMN), which (de)allocates packet buffers from a memory pool permanently mapped in the IOMMU; (2)~modifying the network stack to use this allocator; and (3)~copying packet data only when the kernel needs it, which usually morphs the aforementioned extra copy into the kernel's standard copy operation performed at the user-kernel boundary. DAMN thus provides full IOMMU protection with performance comparable to that of an unprotected system.", "doi": "10.1145/3173162.3173175", "arxiv_id": "https://doi.org/10.1145/3173162.3173175", "pmid": null, "openalex_id": null, "s2_id": "f07f33ff150ed48d36fdd1efec302a2a31b9876b", "cited_by": 38, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162.3173175"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3173162.3173175", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Astra: Exploiting Predictability to Optimize Deep Learning", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Muthian Sivathanu", "Tapan Chugh", "Sanjay Sri Vallabh Singapuram", "Lidong Zhou"], "abstract": "We present Astra, a compilation and execution framework that optimizes execution of a deep learning training job. Instead of treating the computation as a generic data flow graph, Astra exploits domain knowledge about deep learning to adopt a custom approach to compiler optimization. The key insight in Astra is to exploit the unique repetitiveness and predictability of a deep learning job, to perform online exploration of the optimization state space in a work-conserving manner while making progress on the training job. This dynamic state space exploration in Astra uses lightweight profiling and indexing of profile data, coupled with several techniques to prune the exploration state space. Effectively, the execution layer custom-wires the infrastructure end-to-end for each job and hardware, while keeping the compiler simple and maintainable. We have implemented Astra in two popular deep learning frameworks, PyTorch and Tensorflow. On state-of-the-art deep learning models, we show that Astra improves end-to-end performance of deep learning training by up to 3x, while approaching the performance of hand-optimized implementations such as cuDNN where available. Astra also significantly outperforms static compilation frameworks such as Tensorflow XLA both in performance and robustness.", "doi": "10.1145/3297858.3304072", "arxiv_id": "https://doi.org/10.1145/3297858.3304072", "pmid": null, "openalex_id": null, "s2_id": "f12557da0cff05914ed4a28d11c8a561e08fbd18", "cited_by": 67, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3304072&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304072"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304072", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Catalyzer: Sub-millisecond Startup for Serverless Computing with Initialization-less Booting", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Dong Du", "Tianyi Yu", "Yubin Xia", "Binyu Zang", "Guanglu Yan", "Chenggang Qin", "Qixuan Wu", "Haibo Chen"], "abstract": "Serverless computing promises cost-efficiency and elasticity for high-productive software development. To achieve this, the serverless sandbox system must address two challenges: strong isolation between function instances, and low startup latency to ensure user experience. While strong isolation can be provided by virtualization-based sandboxes, the initialization of sandbox and application causes non-negligible startup overhead. Conventional sandbox systems fall short in low-latency startup due to their application-agnostic nature: they can only reduce the latency of sandbox initialization through hypervisor and guest kernel customization, which is inadequate and does not mitigate the majority of startup overhead.", "doi": "10.1145/3373376.3378512", "arxiv_id": "https://doi.org/10.1145/3373376.3378512", "pmid": null, "openalex_id": null, "s2_id": "f14446970a5ed7145a6d350e1aff07ca203cece8", "cited_by": 399, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378512"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378512", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "COIN Attacks: On Insecurity of Enclave Untrusted Interfaces in SGX", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mustakimur Rahman Khandaker", "Yueqiang Cheng", "Zhi Wang", "Tao Wei"], "abstract": "Intel SGX is a hardware-based trusted execution environment (TEE), which enables an application to compute on confidential data in a secure enclave. SGX assumes a powerful threat model, in which only the CPU itself is trusted; anything else is untrusted, including the memory, firmware, system software, etc. An enclave interacts with its host application through an exposed, enclave-specific, (usually) bi-directional interface. This interface is the main attack surface of the enclave. The attacker can invoke the interface in any order and inputs. It is thus imperative to secure it through careful design and defensive programming. In this work, we systematically analyze the attack models against the enclave untrusted interfaces and summarized them into the COIN attacks -- Concurrent, Order, Inputs, and Nested. Together, these four models allow the attacker to invoke the enclave interface in any order with arbitrary inputs, including from multiple threads. We then build an extensible framework to test an enclave in the presence of COIN attacks with instruction emulation and concolic execution. We evaluated ten popular open-source SGX projects using eight vulnerability detection policies that cover information leaks, control-flow hijackings, and memory vulnerabilities. We found 52 vulnerabilities. In one case, we discovered an information leak that could reliably dump the entire enclave memory by manipulating the inputs. Our evaluation highlights the necessity of extensively testing an enclave before its deployment.", "doi": "10.1145/3373376.3378486", "arxiv_id": "https://doi.org/10.1145/3373376.3378486", "pmid": null, "openalex_id": null, "s2_id": "f1eff11ce6bf2eb0bcb3a14e5baa13920b4d7bf1", "cited_by": 77, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3373376.3378486", "https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378486"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3378486", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Defensive approximation: securing CNNs using approximate computing", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Amira Guesmi", "Ihsen Alouani", "Khaled N. Khasawneh", "Mouna Baklouti", "Tarek Frikha", "Mohamed Abid", "Nael B. Abu-Ghazaleh"], "abstract": "In the past few years, an increasing number of machine-learning and deep learning structures, such as Convolutional Neural Networks (CNNs), have been applied to solving a wide range of real-life problems. However, these architectures are vulnerable to adversarial attacks: inputs crafted carefully to force the system output to a wrong label. Since machine-learning is being deployed in safety-critical and security-sensitive domains, such attacks may have catastrophic security and safety consequences. In this paper, we propose for the first time to use hardware-supported approximate computing to improve the robustness of machine learning classifiers. We show that our approximate computing implementation achieves robustness across a wide range of attack scenarios. Specifically, we show that successful adversarial attacks against the exact classifier have poor transferability to the approximate implementation. The transferability is even poorer for the black-box attack scenarios, where adversarial attacks are generated using a proxy model. Surprisingly, the robustness advantages also apply to white-box attacks where the attacker has unrestricted access to the approximate classifier implementation: in this case, we show that substantially higher levels of adversarial noise are needed to produce adversarial examples. Furthermore, our approximate computing model maintains the same level in terms of classification accuracy, does not require retraining, and reduces resource utilization and energy consumption of the CNN. We conducted extensive experiments on a set of strong adversarial attacks; We empirically show that the proposed implementation increases the robustness of a LeNet-5 and an Alexnet CNNs by up to 99% and 87%, respectively for strong transferability-based attacks along with up to 50% saving in energy consumption due to the simpler nature of the approximate logic. We also show that a white-box attack requires a remarkably higher noise budget to fool the approximate classifier, causing an average of 4 dB degradation of the PSNR of the input image relative to the images that succeed in fooling the exact classifier.", "doi": "10.1145/3445814.3446747", "arxiv_id": "2006.07700", "pmid": null, "openalex_id": null, "s2_id": "f3340326ca107aa7f8bfd0a392d36db876aac4a6", "cited_by": 49, "type": "conference", "is_oa": true, "pdf_urls": ["http://arxiv.org/pdf/2006.07700", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446747"], "github": ["https://github.com/AG-X09/Defensive-Approximation"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446747", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 6B: Virtualization", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248625", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "f3b6ab0a827a777dc2c275c52ca45395cc1d66e2", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "kMVX: Detecting Kernel Information Leaks with Multi-variant Execution", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sebastian Österlund", "Koen Koning", "Pierre Olivier", "Antonio Barbalace", "Herbert Bos", "Cristiano Giuffrida"], "abstract": "Kernel information leak vulnerabilities are a major security threat to production systems. Attackers can exploit them to leak confidential information such as cryptographic keys or kernel pointers. Despite efforts by kernel developers and researchers, existing defenses for kernels such as Linux are limited in scope or incur a prohibitive performance overhead. In this paper, we present kMVX, a comprehensive defense against information leak vulnerabilities in the kernel by running multiple diversified kernel variants simultaneously on the same machine. By constructing these variants in a careful manner, we can ensure they only show divergences when an attacker tries to exploit bugs present in the kernel. By detecting these divergences we can prevent kernel information leaks. Our kMVX design is inspired by multi-variant execution (MVX). Traditional MVX designs cannot be applied to kernels because of their assumptions on the run-time environment. kMVX, on the other hand, can be applied even to commodity kernels. We show our Linux-based prototype provides powerful protection against information leaks at acceptable performance overhead (20--50% in the worst case for popular server applications).", "doi": "10.1145/3297858.3304054", "arxiv_id": "https://doi.org/10.1145/3297858.3304054", "pmid": null, "openalex_id": null, "s2_id": "f3d42ec5a662645edc489dd6d8ae4efda39a4833", "cited_by": 47, "type": "conference", "is_oa": true, "pdf_urls": ["https://research.vu.nl/en/publications/eaa6fa6c-1324-4ca1-baa3-729216b4de4e", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304054"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304054", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "PMFuzz: test case generation for persistent memory programs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sihang Liu", "Suyash Mahar", "Baishakhi Ray", "Samira Manabi Khan"], "abstract": "The Persistent Memory (PM) technology combines the persistence of storage with the performance approaching that of DRAM. Programs taking advantage of PM must ensure data remains recoverable after a failure (e.g., power outage), and therefore, are susceptible to having crash consistency bugs that lead to incorrect recovery after a failure. Prior works have provided tools, such as Pmemcheck, PMTest, and XFDetector, that detect these bugs by checking whether the trace of PM accesses violates the program’s crash consistency guarantees. However, detection of crash consistency bugs highly depends on test cases—a bug can only be detected if the buggy program path has been executed. Therefore, using a test case generator is necessary to effectively detect crash consistency bugs.", "doi": "10.1145/3445814.3446691", "arxiv_id": "https://doi.org/10.1145/3445814.3446691", "pmid": null, "openalex_id": null, "s2_id": "f41982f7300e0b06fe5441cb90a6b3b2056f5750", "cited_by": 45, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446691"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446691", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Probabilistic profiling of stateful data planes for adversarial testing", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Qiao Kang", "Jiarong Xing", "Yiming Qiu", "Ang Chen"], "abstract": "Recently, there is a flurry of projects that develop data plane systems in programmable switches, and these systems perform far more sophisticated processing than simply deciding a packet's next hop (i.e., traditional forwarding). This presents challenges to existing network program profilers, which are developed primarily to handle stateless forwarding programs.", "doi": "10.1145/3445814.3446764", "arxiv_id": "https://doi.org/10.1145/3445814.3446764", "pmid": null, "openalex_id": null, "s2_id": "f48023a7963e6b315e6e6e14b864da34f65f2bf9", "cited_by": 27, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446764"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446764", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "High-Performance Transactions for Persistent Memories", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Aasheesh Kolli", "Steven Pelley", "Ali G. Saidi", "Peter M. Chen", "Thomas F. Wenisch"], "abstract": "Emerging non-volatile memory (NVRAM) technologies offer the durability of disk with the byte-addressability of DRAM. These devices will allow software to access persistent data structures directly in NVRAM using processor loads and stores, however, ensuring consistency of persistent data across power failures and crashes is difficult. Atomic, durable transactions are a widely used abstraction to enforce such consistency. Implementing transactions on NVRAM requires the ability to constrain the order of NVRAM writes, for example, to ensure that a transaction's log record is complete before it is marked committed. Since NVRAM write latencies are expected to be high, minimizing these ordering constraints is critical for achieving high performance. Recent work has proposed programming interfaces to express NVRAM write ordering constraints to hardware so that NVRAM writes may be coalesced and reordered while preserving necessary constraints. Unfortunately, a straightforward implementation of transactions under these interfaces imposes unnecessary constraints. We show how to remove these dependencies through a variety of techniques, notably, deferring commit until after locks are released. We present a comprehensive analysis contrasting two transaction designs across three NVRAM programming interfaces, demonstrating up to 2.5x speedup.", "doi": "10.1145/2872362.2872381", "arxiv_id": "https://doi.org/10.1145/2872362.2872381", "pmid": null, "openalex_id": null, "s2_id": "f4f9e8d681bdace87c988732d44b61ca163f351f", "cited_by": 200, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=2872381&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872381"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872381", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "AxGames: Towards Crowdsourcing Quality Target Determination in Approximate Computing", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jongse Park", "Emmanuel Amaro", "Divya Mahajan", "Bradley Thwaites", "Hadi Esmaeilzadeh"], "abstract": "Approximate computing trades quality of application output for higher efficiency and performance. Approximation is useful only if its impact on application output quality is acceptable to the users. However, there is a lack of systematic solutions and studies that explore users' perspective on the effects of approximation. In this paper, we seek to provide one such solution for the developers to probe and discover the boundary of quality loss that most users will deem acceptable. We propose AxGames, a crowdsourced solution that enables developers to readily infer a statistical common ground from the general public through three entertaining games. The users engage in these games by betting on their opinion about the quality loss of the final output while the AxGames framework collects statistics about their perceptions. The framework then statistically analyzes the results to determine the acceptable levels of quality for a pair of (application, approximation technique). The three games are designed such that they effectively capture quality requirements with various tradeoffs and contexts. To evaluate AxGames, we examine seven diverse applications that produce user perceptible outputs and cover a wide range of domains, including image processing, optical character recognition, speech to text conversion, and audio processing. We recruit 700 participants/users through Amazon's Mechanical Turk to play the games that collect statistics about their perception on different levels of quality. Subsequently, the AxGames framework uses the Clopper-Pearson exact method, which computes a binomial proportion confidence interval, to analyze the collected statistics for each level of quality. Using this analysis, AxGames can statistically project the quality level that satisfies a given percentage of users. The developers can use these statistical projections to tune the level of approximation based on the user experience. We find that the level of acceptable quality loss significantly varies across applications. For instance, to satisfy 90% of users, the level of acceptable quality loss is 2% for one application (image processing) and 26% for another (audio processing). Moreover, the pattern with which the crowd responds to approximation takes significantly different shape and form depending on the class of applications. These results confirm the necessity of solutions that systematically explore the effect of approximation on the end user experience.", "doi": "10.1145/2872362.2872376", "arxiv_id": "https://doi.org/10.1145/2872362.2872376", "pmid": null, "openalex_id": null, "s2_id": "f4fa4569bd22577994a6d2bd2da1df33186d14b2", "cited_by": 35, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/2872362.2872376?download=true", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872376"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872376", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Speculative interference attacks: breaking invisible speculation schemes", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Mohammad Behnia", "Prateek Sahu", "Riccardo Paccagnella", "Jiyong Yu", "Zirui Neil Zhao", "Xiang Zou", "Thomas Unterluggauer", "Josep Torrellas", "Carlos V. Rozas", "Adam Morrison", "Frank McKeen", "Fangfei Liu", "Ron Gabor", "Christopher W. Fletcher", "Abhishek Basak", "Alaa R. Alameldeen"], "abstract": "Recent security vulnerabilities that target speculative execution (e.g., Spectre) present a significant challenge for processor design. These highly publicized vulnerabilities use speculative execution to learn victim secrets by changing the cache state. As a result, recent computer architecture research has focused on invisible speculation mechanisms that attempt to block changes in cache state due to speculative execution. Prior work has shown significant success in preventing Spectre and other attacks at modest performance costs. In this paper, we introduce speculative interference attacks, which show that prior invisible speculation mechanisms do not fully block speculation-based attacks that use cache state. We make two key observations. First, mis-speculated younger instructions can change the timing of older, bound-to-retire instructions, including memory operations. Second, changing the timing of a memory operation can change the order of that memory operation relative to other memory operations, resulting in persistent changes to the cache state. Using both of these observations, we demonstrate (among other attack variants) that secret information accessed by mis-speculated instructions can change the order of bound-to-retire loads. Load timing changes can therefore leave secret-dependent changes in the cache, even in the presence of invisible speculation mechanisms. We show that this problem is not easy to fix. Speculative interference converts timing changes to persistent cache-state changes, and timing is typically ignored by many cache-based defenses. We develop a framework to understand the attack and demonstrate concrete proof-of-concept attacks against invisible speculation mechanisms. We conclude with a discussion of security definitions that are sufficient to block the attacks, along with preliminary defense ideas based on those definitions.", "doi": "10.1145/3445814.3446708", "arxiv_id": "2007.11818", "pmid": null, "openalex_id": null, "s2_id": "f5121c02da02d874a0acf357779c85a565e93524", "cited_by": 96, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/2007.11818", "https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446708"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446708", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Crossing Guard: Mediating Host-Accelerator Coherence Interactions", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Lena E. Olson", "Mark D. Hill", "David A. Wood"], "abstract": "Specialized hardware accelerators have performance and energy-efficiency advantages over general-purpose processors. To fully realize these benefits and aid programmability, accelerators may share a physical and virtual address space and full cache coherence with the host system. However, allowing accelerators -- particularly those designed by third parties -- to directly communicate with host coherence protocols poses several problems. Host coherence protocols are complex, vary between companies, and may be proprietary, increasing burden on accelerator designers. Bugs in the accelerator implementation may cause crashes and other serious consequences to the host system.", "doi": "10.1145/3037697.3037715", "arxiv_id": "https://doi.org/10.1145/3037697.3037715", "pmid": null, "openalex_id": null, "s2_id": "f7204a1961afa5461d29e979e6c93314bc5348d8", "cited_by": 23, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037715"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037715", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "HCloud: Resource-Efficient Provisioning in Shared Cloud Systems", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Christina Delimitrou", "Christos Kozyrakis"], "abstract": "Cloud computing promises flexibility and high performance for users and cost efficiency for operators. To achieve this, cloud providers offer instances of different sizes, both as long-term reservations and short-term, on-demand allocations. Unfortunately, determining the best provisioning strategy is a complex, multi-dimensional problem that depends on the load fluctuation and duration of incoming jobs, and the performance unpredictability and cost of resources. We first compare the two main provisioning strategies (reserved and on-demand resources) on Google Compute Engine (GCE) using three representative workload scenarios with batch and latency-critical applications. We show that either approach is suboptimal for performance or cost. We then present HCloud, a hybrid provisioning system that uses both reserved and on-demand resources. HCloud determines which jobs should be mapped to reserved versus on-demand resources based on overall load, and resource unpredictability. It also determines the optimal instance size an application needs to satisfy its Quality of Service (QoS) constraints. We demonstrate that hybrid configurations improve performance by 2.1x compared to fully on-demand provisioning, and reduce cost by 46% compared to fully reserved systems. We also show that hybrid strategies are robust to variation in system and job parameters, such as cost and system load.", "doi": "10.1145/2872362.2872365", "arxiv_id": "https://doi.org/10.1145/2872362.2872365", "pmid": null, "openalex_id": null, "s2_id": "f7bf2552d8e45544b7501e982af5ad1544cb1868", "cited_by": 136, "type": "conference", "is_oa": true, "pdf_urls": ["http://infoscience.epfl.ch/record/221888", "https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872365"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/2872362.2872365", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Vectorization for digital signal processors via equality saturation", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alexa VanHattum", "Rachit Nigam", "Vincent T. Lee", "James Bornholt", "Adrian Sampson"], "abstract": "Applications targeting digital signal processors (DSPs) benefit from fast implementations of small linear algebra kernels. While existing auto-vectorizing compilers are effective at extracting performance from large kernels, they struggle to invent the complex data movements necessary to optimize small kernels. To get the best performance, DSP engineers must hand-write and tune specialized small kernels for a wide spectrum of applications and architectures. We present Diospyros, a search-based compiler that automatically finds efficient vectorizations and data layouts for small linear algebra kernels. Diospyros combines symbolic evaluation and equality saturation to vectorize computations with irregular structure. We show that a collection of Diospyros-compiled kernels outperform implementations from existing DSP libraries by 3.1× on average, that Diospyros can generate kernels that are competitive with expert-tuned code, and that optimizing these small kernels offers end-to-end speedup for a DSP application.", "doi": "10.1145/3445814.3446707", "arxiv_id": "https://doi.org/10.1145/3445814.3446707", "pmid": null, "openalex_id": null, "s2_id": "f80e0ee17fb9098d57b19b3642d3cf76103655c6", "cited_by": 72, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446707"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3445814.3446707", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Session details: Session 9B: Data Center Architectures & Power Management", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": null, "doi": "10.1145/3248631", "arxiv_id": null, "pmid": null, "openalex_id": null, "s2_id": "f935fc3118861b39a7758fd75c250504bc562f34", "cited_by": 0, "type": null, "is_oa": false, "pdf_urls": [], "github": [], "sources": ["semanticscholar"], "landing": null, "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Efficient Address Translation for Architectures with Multiple Page Sizes", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Guilherme Cox", "Abhishek Bhattacharjee"], "abstract": "Processors and operating systems (OSes) support multiple memory page sizes. Superpages increase Translation Lookaside Buffer (TLB) hits, while small pages provide fine-grained memory protection. Ideally, TLBs should perform well for any distribution of page sizes. In reality, set-associative TLBs -- used frequently for their energy efficiency compared to fully-associative TLBs -- cannot (easily) support multiple page sizes concurrently. Instead, commercial systems typically implement separate set-associative TLBs for different page sizes. This means that when superpages are allocated aggressively, TLB misses may, counter intuitively, increase even if entries for small pages remain unused (and vice-versa). We invent MIX TLBs, energy-frugal set-associative structures that concurrently support all page sizes by exploiting superpage allocation patterns. MIX TLBs boost the performance (often by 10-30%) of big-memory applications on native CPUs, virtualized CPUs, and GPUs. MIX TLBs are simple and require no OS or program changes.", "doi": "10.1145/3037697.3037704", "arxiv_id": "https://doi.org/10.1145/3037697.3037704", "pmid": null, "openalex_id": null, "s2_id": "f95580b04b6638f7aee4fca0ed30a619c55e7363", "cited_by": 118, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037704"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037704", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ρ: Relaxed Hierarchical ORAM", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chandrasekhar Nagarajan", "Ali Shafiee", "Rajeev Balasubramonian", "Mohit Tiwari"], "abstract": "Applications in the cloud are vulnerable to several attack scenarios. In one possibility, an untrusted cloud operator can examine addresses on the memory bus and use this information leak to violate privacy guarantees, even if data is encrypted. The Oblivious RAM (ORAM) construct was introduced to eliminate such information leak and these frameworks have seen many innovations in recent years. In spite of these innovations, the overhead associated with ORAM is very significant. This paper takes a step forward in reducing ORAM memory bandwidth overheads. We make the case that, similar to a cache hierarchy, a lightweight ORAM that fronts the full-fledged ORAM provides a boost in efficiency. The lightweight ORAM has a smaller capacity and smaller depth, and it can relax some of the many constraints imposed on the full-fledged ORAM. This yields a 2-level hierarchy with a relaxed ORAM and a full ORAM. The relaxed ORAM adopts design parameters that are optimized for efficiency and not capacity. We introduce a novel metadata management technique to further reduce the bandwidth for relaxed ORAM access. Relaxed ORAM accesses preserve the indistinguishability property and are equipped with an integrity verification system. Finally, to eliminate information leakage through LLC and relaxed ORAM hit rates, we introduce a deterministic memory scheduling policy. On a suite of memory-intensive applications, we show that the best Relaxed Hierarchical ORAM (ρ) model yields a performance improvement of 50%, relative to a Freecursive ORAM baseline.", "doi": "10.1145/3297858.3304045", "arxiv_id": "https://doi.org/10.1145/3297858.3304045", "pmid": null, "openalex_id": null, "s2_id": "fa7d5ac6c0ff79a7c2eeb6db4db2e3021d0f3bb4", "cited_by": 14, "type": "conference", "is_oa": true, "pdf_urls": ["https://doi.org/10.1145/3297858.3304045", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304045"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304045", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Methods of Multipliers", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ao Ren", "Tianyun Zhang", "Shaokai Ye", "Jiayu Li", "Wenyao Xu", "Xuehai Qian", "Xue Lin", "Yanzhi Wang"], "abstract": "Model compression is an important technique to facilitate efficient embedded and hardware implementations of deep neural networks (DNNs), a number of prior works are dedicated to model compression techniques. The target is to simultaneously reduce the model storage size and accelerate the computation, with minor effect on accuracy. Two important categories of DNN model compression techniques are weight pruning and weight quantization. The former leverages the redundancy in the number of weights, whereas the latter leverages the redundancy in bit representation of weights. These two sources of redundancy can be combined, thereby leading to a higher degree of DNN model compression. However, a systematic framework of joint weight pruning and quantization of DNNs is lacking, thereby limiting the available model compression ratio. Moreover, the computation reduction, energy efficiency improvement, and hardware performance overhead need to be accounted besides simply model size reduction, and the hardware performance overhead resulted from weight pruning method needs to be taken into consideration. To address these limitations, we present ADMM-NN, the first algorithm-hardware co-optimization framework of DNNs using Alternating Direction Method of Multipliers (ADMM), a powerful technique to solve non-convex optimization problems with possibly combinatorial constraints. The first part of ADMM-NN is a systematic, joint framework of DNN weight pruning and quantization using ADMM. It can be understood as a smart regularization technique with regularization target dynamically updated in each ADMM iteration, thereby resulting in higher performance in model compression than the state-of-the-art. The second part is hardware-aware DNN optimizations to facilitate hardware-level implementations. We perform ADMM-based weight pruning and quantization considering (i) the computation reduction and energy efficiency improvement, and (ii) the hardware performance overhead due to irregular sparsity. The first requirement prioritizes the convolutional layer compression over fully-connected layers, while the latter requires a concept of the break-even pruning ratio, defined as the minimum pruning ratio of a specific layer that results in no hardware performance degradation. Without accuracy loss, ADMM-NN achieves 85× and 24× pruning on LeNet-5 and AlexNet models, respectively, --- significantly higher than the state-of-the-art. The improvements become more significant when focusing on computation reduction. Combining weight pruning and quantization, we achieve 1,910× and 231× reductions in overall model size on these two benchmarks, when focusing on data storage. Highly promising results are also observed on other representative DNNs such as VGGNet and ResNet-50. We release codes and models at https://github.com/yeshaokai/admm-nn.", "doi": "10.1145/3297858.3304076", "arxiv_id": "1812.11677", "pmid": null, "openalex_id": null, "s2_id": "fac7ba9654f32cddab018e2157614aa8d13d99a1", "cited_by": 173, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304076", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304076"], "github": ["https://github.com/yeshaokai/admm-nn", "https://github.com/bowenl0218/bpgan-signal-compression"], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304076", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Big Data of the Past, from Venice to Europe", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Frédéric Kaplan"], "abstract": "In 2012, the Ecole Polytechnique Fédérale de Lausanne (EPFL) and the University Ca'Foscari launched a program called the Venice Time Machine, whose goal was to develop a large-scale digitisation program to transform Venice's heritage into 'Big Data of the Past'. Millions of register pages and photographs have been scanned at the State Archive in Venice and at the Fondazione Giorgio Cini. These documents were analysed using the deep-learning artificial-intelligence methods developed at EPFL's Digital Humanities Laboratory in order to extract their textual and iconographic content and to make the data accessible via a search engine. The project has now expand to a European scale, including more than 500 institutions and 20 new cities jointly constructing a distributed digital information system mapping the social, cultural and geographical evolution of Europe. The project build upon existing platforms such as Europeana, and accelerate their development. While Europeana drives transformation throughout the cultural heritage sector with innovative standards, infrastructure and networks, Time Machine aims to design and implement advanced new digitisation and artificial intelligence technologies to mine Europe's vast cultural heritage, providing fair and free access to information that will support future scientific and technological developments in Europe.", "doi": "10.1145/3373376.3380611", "arxiv_id": "https://doi.org/10.1145/3373376.3380611", "pmid": null, "openalex_id": null, "s2_id": "fb9b573dc8816fcccd8b95b433e17817bd701ee3", "cited_by": 1, "type": "conference", "is_oa": true, "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3380611"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3373376.3380611", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Locality Transformations for Nested Recursive Iteration Spaces", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kirshanthan Sundararajah", "Laith Sakka", "Milind Kulkarni"], "abstract": "There has been a significant amount of effort invested in designing scheduling transformations such as loop tiling and loop fusion that rearrange the execution of dynamic instances of loop nests to place operations that access the same data close together temporally. In recent years, there has been interest in designing similar transformations that operate on recursive programs, but until now these transformations have only considered simple scenarios: multiple recursions to be fused, or a recursion nested inside a simple loop. This paper develops the first set of scheduling transformations for nested recursions: recursive methods that call other recursive methods. These are the recursive analog to nested loops. We present a transformation called recursion twisting that automatically improves locality at all levels of the memory hierarchy, and show that this transformation can yield substantial performance improvements across several benchmarks that exhibit nested recursion.", "doi": "10.1145/3037697.3037720", "arxiv_id": "https://doi.org/10.1145/3037697.3037720", "pmid": null, "openalex_id": null, "s2_id": "fc7577d182417e2013b702cc962b9f06a3115a20", "cited_by": 10, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037720&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037720"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037720", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Sound Loop Superoptimization for Google Native Client", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Berkeley R. Churchill", "Rahul Sharma", "J. F. Bastien", "Alex Aiken"], "abstract": "Software fault isolation (SFI) is an important technique for the construction of secure operating systems, web browsers, and other extensible software. We demonstrate that superoptimization can dramatically improve the performance of Google Native Client, a SFI system that ships inside the Google Chrome Browser. Key to our results are new techniques for superoptimization of loops: we propose a new architecture for superoptimization tools that incorporates both a fully sound verification technique to ensure correctness and a bounded verification technique to guide the search to optimized code. In our evaluation we optimize 13 libc string functions, formally verify the correctness of the optimizations and report a median and average speedup of 25% over the libraries shipped by Google.", "doi": "10.1145/3037697.3037754", "arxiv_id": "https://doi.org/10.1145/3037697.3037754", "pmid": null, "openalex_id": null, "s2_id": "fcefce81c8e810711e87170461ad6462d2f731fa", "cited_by": 32, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037754&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037754"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037754", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Prophet: Precise QoS Prediction on Non-Preemptive Accelerators to Improve Utilization in Warehouse-Scale Computers", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Quan Chen", "Hailong Yang", "Minyi Guo", "Ram Srivatsa Kannan", "Jason Mars", "Lingjia Tang"], "abstract": "Guaranteeing Quality-of-Service (QoS) of latency-sensitive applications while improving server utilization through application co-location is important yet challenging in modern datacenters. The key challenge is that when applications are co-located on a server, performance interference due to resource contention can be detrimental to the application QoS. Although prior work has proposed techniques to identify \"safe\" co-locations where application QoS is satisfied by predicting the performance interference on multicores, no such prediction technique on accelerators such as GPUs.", "doi": "10.1145/3037697.3037700", "arxiv_id": "https://doi.org/10.1145/3037697.3037700", "pmid": null, "openalex_id": null, "s2_id": "fdd4cf09259974aa26a40be24cfbda792cf438c3", "cited_by": 169, "type": "conference", "is_oa": true, "pdf_urls": ["http://dl.acm.org/ft_gateway.cfm?id=3037700&type=pdf", "https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037700"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3037697.3037700", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "A Formal Analysis of the NVIDIA PTX Memory Consistency Model", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Daniel Lustig", "Sameer D. Sahasrabuddhe", "Olivier Giroux"], "abstract": "This paper presents the first formal analysis of the official memory consistency model for the NVIDIA PTX virtual ISA. Like other GPU memory models, the PTX memory model is weakly ordered but provides scoped synchronization primitives that enable GPU program threads to communicate through memory. However, unlike some competing GPU memory models, PTX does not require data race freedom, and this results in PTX using a fundamentally different (and more complicated) set of rules in its memory model. As such, PTX has a clear need for a rigorous and reliable memory model testing and analysis infrastructure. We break our formal analysis of the PTX memory model into multiple steps that collectively demonstrate its rigor and validity. First, we adapt the English language specification from the public PTX documentation into a formal axiomatic model. Second, we derive an up-to-date presentation of an OpenCL-like scoped C++ model and develop a mapping from the synchronization primitives of that scoped C++ model onto PTX. Third, we use the Alloy relational modeling tool to empirically test the correctness of the mapping. Finally, we compile the model and mapping into Coq and build a full machine-checked proof that the mapping is sound for programs of any size. Our analysis demonstrates that in spite of issues in previous generations, the new NVIDIA PTX memory model is suitable as a sound compilation target for GPU programming languages such as CUDA.", "doi": "10.1145/3297858.3304043", "arxiv_id": "https://doi.org/10.1145/3297858.3304043", "pmid": null, "openalex_id": null, "s2_id": "fdeef01187b2a2454ee9ec73fc65a9ab02e3be02", "cited_by": 76, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304043", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304043"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304043", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["H. T. Kung", "Bradley McDanel", "Sai Qian Zhang"], "abstract": "This paper describes a novel approach of packing sparse convolutional neural networks into a denser format for efficient implementations using systolic arrays. By combining multiple sparse columns of a convolutional filter matrix into a single dense column stored in the systolic array, the utilization efficiency of the systolic array can be substantially increased (e.g., 8x) due to the increased density of nonzero weights in the resulting packed filter matrix. In combining columns, for each row, all filter weights but the one with the largest magnitude are pruned. The remaining weights are retrained to preserve high accuracy. We study the effectiveness of this joint optimization for both high utilization efficiency and classification accuracy with ASIC and FPGA designs based on efficient bit-serial implementations of multiplier-accumulators. We demonstrate that in mitigating data privacy concerns the retraining can be accomplished with only fractions of the original dataset (e.g., 10% for CIFAR-10). We present analysis and empirical evidence on the superior performance of our column combining approach against prior arts under metrics such as energy efficiency (3x) and inference latency (12x).", "doi": "10.1145/3297858.3304028", "arxiv_id": "1811.04770", "pmid": null, "openalex_id": null, "s2_id": "fe7ceb03b12c0dbd50290be632dacdccac72af77", "cited_by": 155, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304028", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304028"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304028", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Boosted Race Trees for Low Energy Classification", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Georgios Tzimpragos", "Advait Madhavan", "Dilip Vasudevan", "Dmitri B. Strukov", "Timothy Sherwood"], "abstract": "When extremely low-energy processing is required, the choice of data representation makes a tremendous difference. Each representation (e.g. frequency domain, residue coded, log-scale) comes with a unique set of trade-offs --- some operations are easier in that domain while others are harder. We demonstrate that race logic, in which temporally coded signals are getting processed in a dataflow fashion, provides interesting new capabilities for in-sensor processing applications. Specifically, with an extended set of race logic operations, we show that tree-based classifiers can be naturally encoded, and that common classification tasks can be implemented efficiently as a programmable accelerator in this class of logic. To verify this hypothesis, we design several race logic implementations of ensemble learners, compare them against state-of-the-art classifiers, and conduct an architectural design space exploration. Our proof-of-concept architecture, consisting of 1,000 reconfigurable Race Trees of depth 6, will process 15.2M frames/s, dissipating 613mW in 14nm CMOS.", "doi": "10.1145/3297858.3304036", "arxiv_id": "https://doi.org/10.1145/3297858.3304036", "pmid": null, "openalex_id": null, "s2_id": "fea17f984e2149c9054ec61bc7c156ab66f766a6", "cited_by": 32, "type": "conference", "is_oa": true, "pdf_urls": ["https://dl.acm.org/doi/pdf/10.1145/3297858.3304036", "https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304036"], "github": [], "sources": ["semanticscholar", "papervault"], "landing": "https://doi.org/10.1145/3297858.3304036", "s2_venue": "International Conference on Architectural Support for Programming Languages and Operating Systems"}
{"title": "Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, Atlanta, GA, USA, April 2-6, 2016", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Tom Conte", "Yuanyuan Zhou"], "abstract": "It is my pleasure and privilege to serve as program chair for ASPLOS 2016 -- the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems. This year's conference has set new records in terms of the number of submissions, and reinforces ASPLOS's tradition of encouraging work on innovative multidisciplinary research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking, and applications. The 2016 conference saw a record, 232 submissions with a total of 986 (unique 877) paper authors from 240 institutions spread across at least 21 countries and spanning 5 continents: a clear indication that our community is growing, and that ASPLOS is the premier venue of choice for disseminating high quality interdisciplinary work. There was a wide diversity in topics, ranging from DNA computer storage to human computer interaction, with the most popular being heterogeneous architecture and accelerators, security, reliability and debugging, and memory management. 55 papers self-identified as relating to architecture, 55 to parallelism, 59 to operating systems, 40 to programming models and languages, and 20 to compiler optimizations. Some Notes on the Review Process: All reviewing and discussion, including that at the PC meeting, was double blind. As in past ASPLOS conferences, I used a 2-phase review process, with each paper receiving 3 reviews in round 1, and a minimum of an additional 2 reviews in round 2. In order to improve the quality of review assignment, in conjunction with the paper title and abstract (with sometimes a need to skim the paper directly), I used a combination of topic and interest match with reviewers, and suggestions for reviewers from both the authors and the round 1 reviewers (during the round 2 assignment). I continued to monitor reviews for papers through both rounds 1 and 2 as they came in for quality, substance, and tone, to correct any expertise mismatch, and to find experts in the multiple areas each paper might span, including experts outside of the program and external review committees, a step that is essential for a conference with the breadth that ASPLOS covers. Reviewer feedback in this process was extremely helpful. In keeping with ASPLOS'15 and other conferences, not all papers were moved to round 2. In particular, papers with no round 1 reviews advocating acceptance, and with clear consensus (based both on substantive review content and comment exchange) among the reviewers that the paper did not rise above the acceptance bar for the conference, did not move to round 2. Approximately 35.27% of the papers fell in this category. Each of these decisions involved the active participation of all the reviewers. After the rebuttal phase, each paper was assigned a discussion lead. The discussion lead's job was to carefully read all reviews, the rebuttal, and prior online comments (several papers had extensive online discussions after both rounds 1 and 2), and then initiate a discussion with the goal of reaching a conclusion on whether papers were to be accepted, rejected, or discussed at the PC meeting. The goal of the discussion lead (and my monitoring) was to ensure that every reviewer participated in the discussion after reading the other reviews and the rebuttal. During this process, if new reviewers were considered required based on the rebuttal content, they were sought. The program committee meeting was held at the Chicago O'Hare Hilton on November 7th, 2014. All but four PC members were in attendance, due to medical emergencies or health issues. PC members had access to the reviews for all papers for which they had no declared conflict. Paper authors were not revealed during the PC meeting, and since the discussion continued to be blind, PC papers were not singled out for separate discussion. PC members were asked to leave the room for papers for which they were declared as a conflict (which included any papers they were authors on) prior to revealing the paper title and number being discussed. During the PC meeting, all papers categorized as a preliminary accept (15) were discussed first. The PC also had a chance during and prior to the PC meeting to bring up papers for discussion thatwere classified as tentatively rejected (i.e., all papers were open for discussion at the PC meeting). The majority of the time during the PC meeting was spent on the papers categorized as needing discussion. The result of the extensive reviewing, online discussion, and PC meeting is now in your hands for your reading pleasure, with 53 accepted papers, 16 of which were shepherded. In addition to the decision process, for every paper where the authors chose to provide a rebuttal, the discussion lead, in collaboration with the other reviewers, provided the authors with a summary outlining the main criteria leading to the decision outcome for the paper (whether or not the rebuttal answered reviewer questions or addressed concerns or shortcomings expressed in the reviews), along with feedback for improvement. The Program: In addition to the 53 accepted papers, the conference includes two invited keynote speeches. Richard Stanley Williams, a senior fellow at HP, will talk about memristors and sensible machines. Kathryn McKinley from Microsoft Research will give a talk on how to program uncertain things. We will maintain the tradition of past ASPLOS conferences in convening a Wild and Crazy Ideas (WACI) session, organized by Dan Tsafrir, and a debate session organized by Emmett Witchel. Each of which has a group of inspiring speakers line up to provoke thoughts and discussion among the audience and the whole community. Lightning sessions, each morning, managed by Ding Yuan, will provide a quick introduction to the key ideas that will be presented in the talks that day. The authors also have one more chance in the poster session to present their work and get feedback.", "doi": "10.1145/2872362", "arxiv_id": "https://doi.org/10.1145/2872362", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/2872362"}
{"title": "Programming Uncertain <T>jhings", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kathryn S. McKinley"], "abstract": "Innovation flourishes with good abstractions. For instance, codification of the IEEE Floating Point standard in 1985 was critical to the subsequent success of scientific computing. Programming languages currently lack appropriate abstractions for uncertain data. Applications already use estimates from sensors, machine learning, big data, humans, and approximate algorithms, but most programming languages do not help developers address correctness, programmability, and optimization problems due to estimates.", "doi": "10.1145/2872362.2872416", "arxiv_id": "https://doi.org/10.1145/2872362.2872416", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872416"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/2872362.2872416"}
{"title": "Brain Inspired Computing", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["R. Stanley Williams"], "abstract": "No abstract available.", "doi": "10.1145/2872362.2872417", "arxiv_id": "https://doi.org/10.1145/2872362.2872417", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872417"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/2872362.2872417"}
{"title": "Generating Configurable Hardware from Parallel Patterns", "year": 2016, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Raghu Prabhakar", "David Koeplinger", "Kevin J. Brown", "HyoukJoong Lee", "Christopher De Sa", "Christos Kozyrakis", "Kunle Olukotun"], "abstract": "In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and energy improvements over CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two important optimizations for using parallel patterns to generate efficient hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 39.4× on a set of benchmarks from the data analytics domain.", "doi": "10.1145/2872362.2872415", "arxiv_id": "https://doi.org/10.1145/2872362.2872415", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/2872362.2872415"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/2872362.2872415"}
{"title": "Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yunji Chen", "Olivier Temam", "John Carter"], "abstract": "Welcome! It has been my pleasure and privilege to serve as Program Chair for ASPLOS 2017. We received a record 320 submissions, demonstrating the continued popularity of ASPLOS's focus on multidisciplinary research spanning computer architecture, programming languages, compilers, operating systems, networking, and applications. Reflecting recent trends in systems research, popular topics included memory systems (54 submissions), programming models and languages (50), multicore (47) and heterogeneous (43) architectures, power management (41), security (33), cloud (31), virtualization (28), and GPUs (25). Review Process: All reviewing and discussion, including at the PC meeting, was double blind. As in past ASPLOS conferences, I used a 2-phase review process. In the first phase, each paper received 3 reviews, after which the reviewers discussed the papers online. Papers with at least one review that clearly advocated acceptance or two reviews that were mildly supportive, 162 of the 320 submissions, received at least two additional second round reviews. I monitored reviews to track quality and correct any expertise mismatch. After the second round of reviews were in, all authors were given the opportunity to provide rebuttal feedback. After the rebuttal phase, I assigned each paper a discussion lead to carefully read all the reviews, the rebuttal, and the online comments, and initiate a discussion to decide whether the paper should be accepted, rejected, or discussed at the PC meeting. For a few papers, I solicited post-rebuttal reviews to provide additional insights. The program committee met at the J.J. Pickle Research Center in Austin, Texas on November 7th, 2016. PC members had access to the reviews for all papers for which they had no declared conflict. Paper authors were not revealed during the PC meeting. PC papers were not explicitly identified. Before the title or paper number of any paper being discussed was revealed, conflicted PC members were asked to leave the room. We ultimately accepted a record 53 papers for publication and presentation at this year's ASPLOS, a 16.6% acceptance rate.", "doi": "10.1145/3037697", "arxiv_id": "https://doi.org/10.1145/3037697", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3037697"}
{"title": "Big Data Analytics and Intelligence at Alibaba Cloud", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jingren Zhou"], "abstract": "No abstract available.", "doi": "10.1145/3037697.3037699", "arxiv_id": "https://doi.org/10.1145/3037697.3037699", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037699"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3037697.3037699"}
{"title": "Improving Datacenter Efficiency", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ricardo Bianchini"], "abstract": "Internet companies can improve datacenter efficiency and reduce costs, by minimizing resource waste while avoiding (or limiting) performance degradation. In this talk, I will first overview a few of the efficiency-related efforts we are undertaking at Microsoft, including leveraging workload history to improve resource management. I will then discuss some lessons from deploying these efforts in production and how they relate to academic research.", "doi": "10.1145/3037697.3046426", "arxiv_id": "https://doi.org/10.1145/3037697.3046426", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3046426"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3037697.3046426"}
{"title": "SaberLDA: Sparsity-Aware Learning of Topic Models on GPUs", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kaiwei Li", "Jianfei Chen", "Wenguang Chen", "Jun Zhu"], "abstract": "Latent Dirichlet Allocation (LDA) is a popular tool for analyzing discrete count data such as text and images. Applications require LDA to handle both large datasets and a large number of topics. Though distributed CPU systems have been used, GPU-based systems have emerged as a promising alternative because of the high computational power and memory bandwidth of GPUs. However, existing GPU-based LDA systems cannot support a large number of topics because they use algorithms on dense data structures whose time and space complexity is linear to the number of topics.", "doi": "10.1145/3037697.3037740", "arxiv_id": "https://doi.org/10.1145/3037697.3037740", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3037697.3037740"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3037697.3037740"}
{"title": "Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, ETCD@ASPLOS 2017, Xi'an, China, April 8, 2017", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": [], "abstract": "The most popular in-memory computing framework --- Spark --- has a number of performance-critical configuration parameters. Manually tuning these parameters for optimized performance is not practical because the parameter tuning space is huge. Searching ...", "doi": "10.1145/3129457", "arxiv_id": "https://doi.org/10.1145/3129457", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457"}
{"title": "An Experimental Comparison Between Genetic Algorithm and Particle Swarm Optimization in Spark Performance Tuning", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yuzhao Wang", "Qixiao Liu", "Junqing Yu", "Zhibin Yu"], "abstract": "The most popular in-memory computing framework --- Spark --- has a number of performance-critical configuration parameters. Manually tuning these parameters for optimized performance is not practical because the parameter tuning space is huge. Searching algorithms such as genetic algorithm can be used to automatically search the optimal configurations. However, there are several such algorithms and it is unclear which one is better in the case of Spark configuration parameter tuning.", "doi": "10.1145/3129457.3129494", "arxiv_id": "https://doi.org/10.1145/3129457.3129494", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129494"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129494"}
{"title": "Distributed SAR Image Change Detection with OpenCL-Enabled Spark", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Huming Zhu", "Jianing Kou", "Linyan Qiu", "Yuqi Guo", "Mingwei Niu", "Maoguo Gong", "Licheng Jiao"], "abstract": "Distributed processing framework has been widely used in remote-sensing field. Spark, as a popular distributed computing framework, has been utilized to deal with big remote sensing data. However, it is inefficient due to that the application is not only data intensive but also computation intensive. For example, in Synthetic Aperture Radar (SAR) image change detection, clustering analysis can consume a lot of computing time and memory resources dealing with big remote sensing data. Coprocessors (GPU, MIC, etc.) have a high-compute power, which is able to handle computation intensive tasks. In this paper, we proposed an OpenCL-enabled Spark framework to accelerate Kernel Fuzzy C-Mean (KFCM) algorithm for SAR image change detection. And the computation intensive operations of KFCM are transferred to coprocessors of the cluster through the proposed OpenCL-enabled Spark framework. The experimental results on real SAR image indicate that the implementation on OpenCL-enabled Spark is efficient and scalable.", "doi": "10.1145/3129457.3129495", "arxiv_id": "https://doi.org/10.1145/3129457.3129495", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129495"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129495"}
{"title": "A Study of FPGA Virtualization and Accelerator Scheduling", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Qian Zhao", "Masahiro Iida", "Toshinori Sueyoshi"], "abstract": "Deploying field-programmable gate arrays (FPGAs) on the cloud to accelerate the processing of the explosively growing server workloads is becoming a clear trend today. However, the costs reduction of accelerator design and deployment is still difficult with conventional development methods and tools. In the previous work, we proposed the hCODE platform to simplify the design, share and deployment of FPGA accelerators, which adopted a shell-and-IP design pattern and developed supporting tools to improve the reusability and the portability of accelerator designs. In this paper, based on our previous work, we propose new design methods and tools for FPGA virtualization and scheduling that allowing IPs to be implemented at cluster scale in low cost. With the proposed platform, users can easily deploy multiple accelerators on one FPGA to improve on-chip resources and communication bandwidth utilization.", "doi": "10.1145/3129457.3129503", "arxiv_id": "https://doi.org/10.1145/3129457.3129503", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129503"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129503"}
{"title": "DoCE: Direct Extension of On-Chip Interconnects over Converged Ethernet for Rack-Scale Memory Sharing", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yisong Chang", "Ran Zhao", "Lei Yu", "Ke Zhang"], "abstract": "Novel rack-level interconnects are urgently required to support frequent inter-server communications in emerging large-scale distributed in-memory applications. In this paper, we introduce DoCE, a memory semantic fabric via Direct extension of on-chip interconnect (DEOI) over Converged Ethernet. Based on the architectural support for fine-grained remote memory sharing, DoCE provides a 9.6x speedup for distributed implementation of PageRank algorithm on our dual-node ARM SoC-FPGA prototype versus a conventional TCP/IP based solution. To the best of our knowledge, DoCE is the first implementation and prototype for memory semantic fabric via existing Ethernet infrastructure in ARM ecosystem.", "doi": "10.1145/3129457.3129504", "arxiv_id": "https://doi.org/10.1145/3129457.3129504", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129504"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129504"}
{"title": "Slow or Down?: Seem to Be the Same for Cloud Users", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Laiping Zhao", "Xiaobo Zhou"], "abstract": "Recent years have seen the rapidly growing cloud computing market. A massive enterprise applications, like social networking, e-commerce, video streaming, email, web search, mapreduce, spark, are moving to cloud systems. These applications often require tens or hundreds of tasks or micro-services to complete, and need to deal with billions of visits per day while handling unprecedented volumes of data. At the same time, these applications need to deliver quick and predictable response times to their users.", "doi": "10.1145/3129457.3129496", "arxiv_id": "https://doi.org/10.1145/3129457.3129496", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129496"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129496"}
{"title": "Anomaly Detection in Clouds: Challenges and Practice", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kejiang Ye"], "abstract": "Cloud computing is an important infrastructure for many enterprises. After 10 years of development, cloud computing has achieved a great success, and has greatly changed the economy, society, science and industries. In particular, with the rapid development of mobile Internet and big data technology, almost all of the online services and data services are built on the top of cloud computing, such as the online banking services provided by banks, the electronic services provided by the news media, the government cloud information systems provided by the government departments, the mobile services provided by the communications companies. Besides, tens of thousands of Start-ups rely on the provision of cloud computing services. Therefore, ensuring cloud reliability is very important and essential. However, the reality is that the current cloud systems are not reliable enough.", "doi": "10.1145/3129457.3129497", "arxiv_id": "https://doi.org/10.1145/3129457.3129497", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129497"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129497"}
{"title": "Rethinking the SDN Abstraction", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Chengchen Hu"], "abstract": "Software Defined Networking (SDN) greatly simplifies network management and introduces unprecedented flexibility by decoupling control functions from the network data plane. However, such a decoupling also opens a box of various open questions, which are not well addressed, e.g., scalability issues and security concerns. This talk firstly describes the background of SDN and the abstraction that SDN is possessing now, and secondly presents scalability/security problems and our on-going research progress. In addition, the promising directions will also be discussed in the talk.", "doi": "10.1145/3129457.3129498", "arxiv_id": "https://doi.org/10.1145/3129457.3129498", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129498"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129498"}
{"title": "TCS: FaaS (FPGA as a service)", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jianlin Gao"], "abstract": "This presentation firstly points out the dilemma of traditional FPGA industry, then points out that the flexible and easy-to-use cloud services is a feasible way to solve the difficulties of FPGA. Tencent's architecture try to solve the puzzle of FPGA cloud service auto generation using the idea of API as a service. To achieve the goal, Tencent released HDK, SDK, and Tencent Computing Service (TCS) platform to help developers to automatically convert their APIs to cloud service.", "doi": "10.1145/3129457.3129499", "arxiv_id": "https://doi.org/10.1145/3129457.3129499", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129499"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129499"}
{"title": "Customized Architecture Technology for High Performance Computing", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jingfei Jiang"], "abstract": "Customized Architecture is one of the technical road for exascale high performance computing. We will give an overview about FPGA customized architecture. Research experiences on deep learning algorithms accelerators for data analyzing, footprint and cipher algorithms accelerators for information processing, and matrix processing algorithms accelerators for scientific computing will be discussed.", "doi": "10.1145/3129457.3129500", "arxiv_id": "https://doi.org/10.1145/3129457.3129500", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129500"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129500"}
{"title": "Building the Reconfigurable Cloud Ecosystem", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Paul Chow"], "abstract": "Microsoft has clearly made the case for using FPGAs at scale in the cloud and Intel is committed to leveraging the benefits of hardware acceleration with their acquisition of Altera. However, we still cannot use FPGAs with the same ease we have with software-based systems, let alone do it easily at scale in the cloud. High-level synthesis is necessary for making FPGAs accessible, but it is not sufficient. Making FPGAs easy to use for computation requires more than developing accessible tools for creating hardware targeted for FPGAs. The software computing world has a lot of taken-for-granted, sometimes invisible and good open source infrastructure that is missing for using FPGAs as computing devices. The problem is compounded when we want to use FPGAs at the scale of the cloud. I will present the need for some common infrastructure and abstraction layers to support the use of FPGAs for computing at scale, and describe relevant work at the University of Toronto that can contribute towards the development of an open source framework for the use and deployment of FPGAs at scale.", "doi": "10.1145/3129457.3129501", "arxiv_id": "https://doi.org/10.1145/3129457.3129501", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129501"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129501"}
{"title": "Programming FPGAs Using OpenCL from Performance Model to Application Study", "year": 2017, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yun Liang"], "abstract": "Recent adoption of OpenCL programming model by FPGA vendors has realized the function portability of OpenCL workloads on FPGA. However, the poor performance portability prevents its wide adoption. To harness the power of FPGAs using OpenCL programming model, it is advantageous to design an analytical performance model to estimate the performance of OpenCL workloads on FPGAs and provide insights into the performance bottlenecks of OpenCL model on FPGA architecture. In the first part of the talk, we present FlexCL, an analytical performance model for OpenCL workloads on flexible FPGAs. FlexCL estimates the overall performance by tightly coupling the on chip global memory and on-chip computation models based on the communication mode. Then, we present an application study of mapping stencil applications onto FPGAs using OpenCL programming model.", "doi": "10.1145/3129457.3129502", "arxiv_id": "https://doi.org/10.1145/3129457.3129502", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3129457.3129502"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3129457.3129502"}
{"title": "Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Xipeng Shen", "James Tuck", "Ricardo Bianchini", "Vivek Sarkar"], "abstract": "The ASPLOS'18 program is the result of a thorough evaluation process, which we started by forming the program committee (PC) with 50 members and the external review committee (ERC) with 73 members. Moreover, we split up the PC into two independent sub-PCs while keeping the ERC as a single unit. We carefully assigned the PC members to the two groups, ensuring that (1) each sub-PC would cover all ASPLOS topics and (2) the experts on each topic would be evenly split across the sub-PCs. In response to the call for papers, we received 319 submissions, just one shy of last year's record. (This number includes 18 submissions that were either withdrawn by their authors or desk-rejected for clear violations of the formatting rules.) After receiving reviewing bids from most committee members, we also split the submissions evenly across the two sub-PCs, so that each submission would receive reviews from only one sub-PC. We manually moved submissions across sub-PCs to maximize reviewer expertise, according to the PC members' bids. The review process proceeded in two rounds, followed by an extensive online discussion period. During the first round, all submissions received 3-4 reviews. Based on these reviews, we selected 158 submissions to go through the second round of reviews, which produced 2-4 additional reviews for these submissions. During the review process, we also requested reviews from 52 external experts on a case-by-case basis. Throughout the process, our main goal in assigning reviewers to submissions was to maximize reviewer expertise. Overall, the committees and external experts produced 1,227 reviews. After the online discussion period involving all reviewers, we selected 100 submissions for discussion (15 papers online-tagged tentative-accepts and 85 papers online-tagged discuss-at-meeting) during the PC meeting on November 10, 2017 at Georgia Tech. 47 of the 50 PC members were physically present at the meeting and 2 others participated remotely. The whole committee met together in the morning, and split up into the two independent sub- PCs in the afternoon. We did not set a limit for the number of accepted submissions. During the meeting, we accepted 47 submissions and conditionally accepted (subject to shepherding) 9 others. After carefully addressing the reviewers' comments, all shepherded submissions were ultimately accepted. The acceptance rate of the two sub-PCs was exactly the same: 28/151 and 28/150. To complete the program, we invited two outstanding keynote speakers: Hillery Hunter (IBM Research) and Fred Chong (University of Chicago). We are pleased that the 56 accepted submissions and 2 keynote talks represent an exciting spectrum of traditional and emerging ASPLOS topics.", "doi": "10.1145/3173162", "arxiv_id": "https://doi.org/10.1145/3173162", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3173162"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3173162"}
{"title": "Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, ReQuEST@ASPLOS 2018, Williamsburg, VA, USA, March 24, 2018", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Luis Ceze", "Natalie D. Enright Jerger", "Babak Falsafi", "Grigori Fursin", "Anton Lokhmotov", "Thierry Moreau", "Adrian Sampson", "Phillip Stanley-Marbell"], "abstract": null, "doi": "10.1145/3229762", "arxiv_id": "https://doi.org/10.1145/3229762", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762"}
{"title": "Keynote", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yiran Chen"], "abstract": "Reducing power consumption has been one of the most important goals since the creation of electronic systems. Energy efficiency is increasingly important as battery-powered systems (such as smartphones, drones, and body cameras) are widely used. It is desirable using the on-board computers to recognize objects in the images captured by these cameras. The Low-Power Image Recognition Challenge (LPIRC) is an annual competition started in 2015, aiming to discover the best technology in both image recognition and energy conservation. In this talk, we will explains the rules of the competition and the rationale, summarizes the teams' scores, and describes the lessons learned in the past years. We will also discuss possible improvements of future challenges and collaboration opportunities with other events and competitions like ReQuEST.", "doi": "10.1145/3229762.3233974", "arxiv_id": "https://doi.org/10.1145/3229762.3233974", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3233974"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3233974"}
{"title": "Highly Efficient 8-bit Low Precision Inference of Convolutional Neural Networks with IntelCaffe", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Jiong Gong", "Haihao Shen", "Guoming Zhang", "Xiaoli Liu", "Shane Li", "Ge Jin", "Niharika Maheshwari", "Evarist Fomenko", "Eden Segal"], "abstract": "High throughput and low latency inference of deep neural networks are critical for the deployment of deep learning applications. This paper presents the efficient inference techniques of IntelCaffe, the first Intel(R) optimized deep learning framework that supports efficient 8-bit low precision inference and model optimization techniques of convolutional neural networks on Intel(R) Xeon(R) Scalable Processors. The 8-bit optimized model is automatically generated with a calibration process from FP32 model without the need of fine-tuning or retraining. We show that the inference throughput and latency with ResNet-50, Inception-v3 and SSD are improved by 1.38X-2.9X and 1.35X-3X respectively with neglectable accuracy loss from IntelCaffe FP32 baseline and by 56X-75X and 26X-37X from BVLC Caffe. All these techniques have been open-sourced on IntelCaffe GitHub (https://github.com/intel/caffe), and the artifact is provided to reproduce the result on Amazon AWS Cloud.", "doi": "10.1145/3229762.3229763", "arxiv_id": "https://doi.org/10.1145/3229762.3229763", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3229763"], "github": ["https://github.com/intel/caffe"], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3229763"}
{"title": "Optimizing Deep Learning Workloads on ARM GPU with TVM", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Lanmin Zheng", "Tianqi Chen"], "abstract": "With the great success of deep learning, the demand for deploying deep neural networks to mobile devices is growing rapidly. However, current popular deep learning frameworks are often poorly optimized for mobile devices, especially mobile GPU. In this paper, we follow the pipeline proposed by TVM/NNVM, and optimize both kernel implementations and dataflow graph for ARM Mali GPU. Compared with vendor-provided ARM Compute Library, our kernel implementations and end-to-end pipeline are 1.7x faster on VGG16 and 2.2x faster on mobilenet.", "doi": "10.1145/3229762.3229764", "arxiv_id": "https://doi.org/10.1145/3229762.3229764", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3229764"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3229764"}
{"title": "Real-Time Image Recognition Using Collaborative IoT Devices", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ramyad Hadidi", "Jiashen Cao", "Matthew Woodward", "Michael S. Ryoo", "Hyesoon Kim"], "abstract": "Internet of things (IoT) devices capture and create various forms of sensor data such as images and videos. However, such resource-constrained devices lack the capability to efficiently process data in a timely and real-time manner. Therefore, IoT systems strongly rely on a powerful server (either local or on the cloud) to extract useful information from data. In addition, during communication with servers, unprocessed, sensitive, and private data is transmitted throughout the Internet, a serious vulnerability. What if we were able to harvest the aggregated computational power of already existing IoT devices in our system to locally process this data? In this artifact, we utilize Musical Chair, which enables efficient, localized, and dynamic real-time recognition by harvesting the aggregated computational power of these resource-constrained IoT devices. We apply Musical chair to two well-known image recognition models, AlexNet and VGG16, and implement them on a network of Raspberry PIs (up to 11). We compare inference per second and energy per inference of our systems with Tegra TX2, an embedded low-power platform with a six-core CPU and a GPU. We demonstrate that the collaboration of IoT devices, enabled by Musical Chair, achieves similar real-time performance without the extra costs of maintaining a server.", "doi": "10.1145/3229762.3229765", "arxiv_id": "https://doi.org/10.1145/3229762.3229765", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3229765"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3229765"}
{"title": "Leveraging the VTA-TVM Hardware-Software Stack for FPGA Acceleration of 8-bit ResNet-18 Inference", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Thierry Moreau", "Tianqi Chen", "Luis Ceze"], "abstract": "We present a full-stack design to accelerate deep learning inference with FPGAs. Our contribution is two-fold. At the software layer, we leverage and extend TVM, the end-to-end deep learning optimizing compiler, in order to harness FPGA-based acceleration. At the the hardware layer, we present the Versatile Tensor Accelerator (VTA) which presents a generic, modular, and customizable architecture for TPU-like accelerators. Our results take a ResNet-18 description in MxNet and compiles it down to perform 8-bit inference on a 256-PE accelerator implemented on a low-cost Xilinx Zynq FPGA, clocked at 100MHz. Our full hardware acceleration stack will be made available for the community to reproduce, and build upon at http://github.com/uwsaml/vta.", "doi": "10.1145/3229762.3229766", "arxiv_id": "https://doi.org/10.1145/3229762.3229766", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3229766"], "github": ["http://github.com/uwsaml/vta"], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3229766"}
{"title": "Multi-objective autotuning of MobileNets across the full software/hardware stack", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Anton Lokhmotov", "Nikolay Chunosov", "Flavio Vella", "Grigori Fursin"], "abstract": "We present a customizable Collective Knowledge workflow to study the execution time vs. accuracy trade-offs for the MobileNets CNN family. We use this workflow to evaluate MobileNets on Arm Cortex CPUs using TensorFlow and Arm Mali GPUs using several versions of the Arm Compute Library. Our optimizations for the Arm Bifrost GPU architecture reduce the execution time by 2--3 times, while lying on a Pareto-optimal frontier. We also highlight the challenge of maintaining the accuracy when deploying CNN models across diverse platforms. We make all the workflow components (models, programs, scripts, etc.) publicly available to encourage further exploration by the community.", "doi": "10.1145/3229762.3229767", "arxiv_id": "https://doi.org/10.1145/3229762.3229767", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3229767"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3229767"}
{"title": "PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research", "year": 2018, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Grigori Fursin", "Thierry Moreau", "Hillery C. Hunter", "Yiran Chen", "Charles Qi", "Tianqi Chen"], "abstract": "Discussion is centered around the following questions:", "doi": "10.1145/3229762.3233976", "arxiv_id": "https://doi.org/10.1145/3229762.3233976", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3229762.3233976"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3229762.3233976"}
{"title": "Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Sushant Kondguli", "Michael C. Huang"], "abstract": "Single-thread performance improvement remains a central design goal for general purpose processors. Microarchitectural designs for the core have reached a plateau over the past years. However, we are still far from exhausting the implicit parallelism available in today's programs. One approach is to use a separate thread context to improve data and instruction supply to the main pipeline. Such decoupled look-ahead (DLA) architectures have been shown to be an effective way to improve single-thread performance. However, a default implementation requires an additional core. While an SMT flavor is possible, a naive implementation is inefficient and thus slow. In this paper, we propose an optimized implementation called Bootstrapping that makes DLA just as effective on a single (SMT) core as using two cores. While fusing two cores can improve single-thread performance by 1.22x, Bootstrapping provides a speedup of 1.48 over a broad range of benchmark suites, making it a compelling microarchitectural feature for general-purpose microarchitectures.", "doi": "10.1145/3297858.3304052", "arxiv_id": "https://doi.org/10.1145/3297858.3304052", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3297858.3304052"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3297858.3304052"}
{"title": "Proceedings of the 12th Workshop on General Purpose Processing Using GPUs, GPGPU@ASPLOS 2019, Providence, RI, USA, April 13, 2019", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Adwait Jog", "Onur Kayiran"], "abstract": "Recent works have shown that there exist microarchitectural timing channels in contemporary GPUs, which make table-based cryptographic algorithms like AES vulnerable to side channel timing attacks. Also, table-based cryptographic algorithms have been ...", "doi": "10.1145/3300053", "arxiv_id": "https://doi.org/10.1145/3300053", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053"}
{"title": "Scatter-and-Gather Revisited: High-Performance Side-Channel-Resistant AES on GPUs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Zhen Lin", "Utkarsh Mathur", "Huiyang Zhou"], "abstract": "Recent works have shown that there exist microarchitectural timing channels in contemporary GPUs, which make table-based cryptographic algorithms like AES vulnerable to side channel timing attacks. Also, table-based cryptographic algorithms have been known to be vulnerable to prime-and-probe attacks due to their key-dependent footprint in the data cache. Such analysis casts serious concerns on the feasibility of accelerating table-based cryptographic algorithms on GPUs. In this paper, we revisit the scatter-and-gather (SG) approach and make a case for using this approach to implement table-based cryptographic algorithms on GPUs to achieve both high performance and strong resistance to side channel attacks. Our results show that our SG-based AES achieves both high performance and strong resistance against all the known side channel attacks on these different generations of NVIDIA GPUs. We also reveal unexpected findings on a new timing channel in the L1 data cache (D-cache) on NVIDIA Maxwell and Pascal GPUs.", "doi": "10.1145/3300053.3319415", "arxiv_id": "https://doi.org/10.1145/3300053.3319415", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053.3319415"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053.3319415"}
{"title": "Detailed Characterization of Deep Neural Networks on GPUs and FPGAs", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Aajna Karki", "Chethan Palangotu Keshava", "Spoorthi Mysore Shivakumar", "Joshua Skow", "Goutam Madhukeshwar Hegde", "Hyeran Jeon"], "abstract": "Deep neural networks (DNNs) have been proving the effectiveness in various computing fields. To provide more efficient computing platforms for DNN applications, it is essential to have evaluation environments that include assorted benchmark workloads. Though a few DNN benchmark suites have been recently released, most of them require to install proprietary DNN libraries or resource-intensive DNN frameworks, which can run only on certain architectures. Also, some of the benchmark suites only support a few per-layer functions where the interactions between layers can not be measured. To provide a more scalable evaluation environment, we present a new DNN benchmark suite, Tango, that can run on any platform that supports CUDA and OpenCL. Tango includes the most widely used five convolution neural networks and two recurrent neural networks. We provide in-depth architectural statistics of these networks while running them on an architecture simulator, a server- and a mobile-GPU, and a mobile FPGA.", "doi": "10.1145/3300053.3319418", "arxiv_id": "https://doi.org/10.1145/3300053.3319418", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053.3319418"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053.3319418"}
{"title": "Which Graph Representation to Select for Static Graph-Algorithms on a CUDA-capable GPU", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Thorsten Blaß", "Michael Philippsen"], "abstract": "GPUs seem to be ideal for algorithms that work in parallel. A number of ways to represent graphs in GPU memory are known. But so far there are no guidelines to select the representation that is likely to result in the best performance.", "doi": "10.1145/3300053.3319416", "arxiv_id": "https://doi.org/10.1145/3300053.3319416", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053.3319416"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053.3319416"}
{"title": "KNN-Joins Using a Hybrid Approach: Exploiting CPU/GPU Workload Characteristics", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Michael Gowanlock"], "abstract": "K Nearest Neighbor (KNN) joins are used in many scientific domains for data analysis, and are building blocks of several well-known algorithms. KNN-joins find the KNN of all points in a dataset. However, KNN searches are computationally expensive, and many GPU KNN algorithms focus on the high-dimensional case that plainly gives a performance advantage to the GPU rather than the CPU. Consequently, in this work, we focus on a hybrid CPU/GPU approach for the low-dimensional KNN-join problem. In particular, we utilize a work queue that prioritizes computing data points in high density regions on the GPU, and low density regions on the CPU, thereby taking advantage of each architecture's relative strengths. Our approach, HybridKNN-Join, is shown to effectively augment a state-of-the-art multi-core CPU algorithm. We propose optimizations that (i) maximize GPU query throughput by assigning the GPU larger batches of work than the CPU; (ii) increase workload granularity to optimize GPU resource utilization; and, (iii) limit load imbalance between CPU and GPU architectures. Furthermore, the work queue utilized in our approach shows promise for the general purpose division of work for other hybrid CPU/GPU algorithms.", "doi": "10.1145/3300053.3319417", "arxiv_id": "https://doi.org/10.1145/3300053.3319417", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053.3319417"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053.3319417"}
{"title": "Characterizing CUDA Unified Memory (UM)-Aware MPI Designs on Modern GPU Architectures", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Karthik Vadambacheri Manian", "A. A. Ammar", "Amit Ruhela", "Ching-Hsiang Chu", "Hari Subramoni", "Dhabaleswar K. Panda"], "abstract": "The CUDA Unified Memory (UM) interface enables a significantly simpler programming paradigm and has the potential to fundamentally change the way programmers write CUDA applications in the future. Although UM leads to high productivity in programming using CUDA by simplifying the programmer's view of CPU and GPU memory spaces, initial support for UM in the Kepler series of GPUs lacked in performance necessitating several UM-aware designs in state-of-the-art MPI runtimes such as MVAPICH2-GDR. This has enabled end MPI applications to take advantage of the high productivity promised by UM along with high performance. However, as CUDA runtimes and GPU architectures advance, the performance offered by UM has also improved significantly. Thus, there is a need to re-evaluate the performance characteristics of UM in light of these changes to understand how the UM-aware designs in state-of-the-art MPI runtimes must be adapted. We take up this broad challenge and characterize the performance of UM-aware MPI operations and to gain insights on how MPI runtimes need to deal with UM-based data residing on GPU and CPU for different generations of GPU architectures. Our characterization studies show that UM designs conceived during the Kepler GPU era still stands valid and provide valuable performance improvement on the latest Pascal and Volta GPUs. Furthermore, performance evaluation of optimized UM designs show that they outperform naive designs on MVAPICH2-GDR and Open MPI by 4.2x and 2.8x respectively for Intel systems. Additionally, the DD experiments for pure device transfers also show that MVAPICH2-GDR is up to 12.6x better than OpenMPI (w/ UCX).", "doi": "10.1145/3300053.3319419", "arxiv_id": "https://doi.org/10.1145/3300053.3319419", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053.3319419"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053.3319419"}
{"title": "Quantifying the NUMA Behavior of Partitioned GPGPU Applications", "year": 2019, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Alexander Matz", "Holger Fröning"], "abstract": "While GPU Computing is pervasive in various areas, including scientific-technical computing and machine learning, single GPUs are often insufficient to meet application demand. Furthermore, multi-GPU processing is a promising option to achieve a continuing performance scaling, given that CMOS technology is expected to hit fundamental scaling limits. We observe that a large amount of work has been done regarding characterizing single-GPU applications. However, characterizing GPGPU applications regarding the NUMA effects resulting from distributed execution has been largely overlooked. In this work, we introduce a framework that allows analyzing the internal communication behavior of GPGPU applications, consisting of 1) an open-source memory tracing plugin for Clang/LLVM, 2) a simple communication model based on summaries of a kernel's memory accesses, 3) communication and locality analyses from memory traces. Besides characterizing locality of kernels, it allows reasoning about virtual bandwidth-limited communication paths between NUMA nodes using different partitioning strategies. We then apply this framework for a large variety of applications, report initial results from our analysis, and finally discuss benefits and limitations of this concept.", "doi": "10.1145/3300053.3319420", "arxiv_id": "https://doi.org/10.1145/3300053.3319420", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3300053.3319420"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3300053.3319420"}
{"title": "Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Ji Liu", "Gregory T. Byrd", "Huiyang Zhou"], "abstract": "In this paper, we propose quantum circuits for runtime assertions, which can be used for both software debugging and error detection. Runtime assertion is challenging in quantum computing for two key reasons. First, a quantum bit (qubit) cannot be copied, which is known as the non-cloning theorem. Second, when a qubit is measured, its superposition state collapses into a classical state, losing the inherent parallel information. In this paper, we overcome these challenges with runtime computation through ancilla qubits, which are used to indirectly collect the information of the qubits of interest. We design quantum circuits to assert classical states, entanglement, and superposition states. Our experimental results show that they are effective in debugging as well as improving the success rate for various quantum algorithms on IBM Q quantum computers.", "doi": "10.1145/3373376.3378488", "arxiv_id": "https://doi.org/10.1145/3373376.3378488", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3373376.3378488"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3373376.3378488"}
{"title": "Sage: practical and scalable ML-driven performance debugging in microservices", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Yu Gan", "Mingyu Liang", "Sundar Dev", "David Lo", "Christina Delimitrou"], "abstract": "Cloud applications are increasingly shifting from large monolithic services to complex graphs of loosely-coupled microservices. Despite the advantages of modularity and elasticity microservices offer, they also complicate cluster management and performance debugging, as dependencies between tiers introduce backpressure and cascading QoS violations. Prior work on performance debugging for cloud services either relies on empirical techniques, or uses supervised learning to diagnose the root causes of performance issues, which requires significant application instrumentation, and is difficult to deploy in practice.", "doi": "10.1145/3445814.3446700", "arxiv_id": "https://doi.org/10.1145/3445814.3446700", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446700"], "github": [], "is_oa": true, "sources": ["papervault"], "type": "conference", "landing": "https://doi.org/10.1145/3445814.3446700"}
{"title": "Analytical characterization and design space exploration for optimization of CNNs", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Rui Li", "Yufan Xu", "Aravind Sukumaran-Rajam", "Atanas Rountev", "P. Sadayappan"], "abstract": "  Moving data through the memory hierarchy is a fundamental bottleneck that can\nlimit the performance of core algorithms of machine learning, such as\nconvolutional neural networks (CNNs). Loop-level optimization, including loop\ntiling and loop permutation, are fundamental transformations to reduce data\nmovement. However, the search space for finding the best loop-level\noptimization configuration is explosively large. This paper develops an\nanalytical modeling approach for finding the best loop-level optimization\nconfiguration for CNNs on multi-core CPUs. Experimental evaluation shows that\nthis approach achieves comparable or better performance than state-of-the-art\nlibraries and auto-tuning based optimizers for CNNs.\n", "doi": "10.1145/3445814.3446759", "arxiv_id": "https://doi.org/10.1145/3445814.3446759", "pdf_urls": ["https://arxiv.org/pdf/https://doi.org/10.1145/3445814.3446759", "https://arxiv.org/pdf/2101.09808"], "github": ["https://github.com/HPCRL/ASPLOS_artifact"], "is_oa": true, "sources": ["papervault", "open-arxiv"], "type": "conference", "landing": "https://doi.org/10.1145/3445814.3446759", "journal_ref": "Proceedings of the 26th ACM International Conference on\n  Architectural Support for Programming Languages and Operating Systems, 2021", "categories": "cs.LG", "cited_by": 0}
{"title": "Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy\n  Efficiency and Scalability", "year": 2020, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Maciej Besta", "Syed Minhaj Hassan", "Sudhakar Yalamanchili", "Rachata\n  Ausavarungnirun", "Onur Mutlu", "Torsten Hoefler"], "abstract": "  Emerging chips with hundreds and thousands of cores require networks with\nunprecedented energy/area efficiency and scalability. To address this, we\npropose Slim NoC (SN): a new on-chip network design that delivers significant\nimprovements in efficiency and scalability compared to the state-of-the-art.\nThe key idea is to use two concepts from graph and number theory,\ndegree-diameter graphs combined with non-prime finite fields, to enable the\nsmallest number of ports for a given core count. SN is inspired by\nstate-of-the-art off-chip topologies; it identifies and distills their\nadvantages for NoC settings while solving several key issues that lead to\nsignificant overheads on-chip. SN provides NoC-specific layouts, which further\nenhance area/energy efficiency. We show how to augment SN with state-of-the-art\nrouter microarchitecture schemes such as Elastic Links, to make the network\neven more scalable and efficient. Our extensive experimental evaluations show\nthat SN outperforms both traditional low-radix topologies (e.g., meshes and\ntori) and modern high-radix networks (e.g., various Flattened Butterflies) in\narea, latency, throughput, and static/dynamic power consumption for both\nsynthetic and real workloads. SN provides a promising direction in scalable and\nenergy-efficient NoC topologies.\n", "doi": null, "arxiv_id": "2010.10683", "pdf_urls": ["https://arxiv.org/pdf/2010.10683"], "github": [], "is_oa": true, "sources": ["open-arxiv"], "type": "conference", "journal_ref": "Proceedings of the 23rd ACM International Conference on\n  Architectural Support for Programming Languages and Operating Systems\n  (ASPLOS'18), 2018", "categories": "cs.AR cs.DC cs.NI"}
{"title": "MODC: Resilience for disaggregated memory architectures using task-based\n  programming", "year": 2021, "venue_abbr": "ASPLOS", "venue_name": "International Conference on Architectural Support for Programming Languages and Operating Systems", "authors": ["Kimberly Keeton and Sharad Singhal and Haris Volos and Yupu Zhang and\n  Ramesh Chandra Chaurasiya and Clarete Riana Crasta and Sherin T George and\n  Nagaraju K N and Mashood Abdulla K and Kavitha Natarajan and Porno Shome and\n  Sanish Suresh"], "abstract": "  Disaggregated memory architectures provide benefits to applications beyond\ntraditional scale out environments, such as independent scaling of compute and\nmemory resources. They also provide an independent failure model, where\ncomputations or the compute nodes they run on may fail independently of the\ndisaggregated memory; thus, data that's resident in the disaggregated memory is\nunaffected by the compute failure. Blind application of traditional techniques\nfor resilience (e.g., checkpoints or data replication) does not take advantage\nof these architectures. To demonstrate the potential benefit of these\narchitectures for resilience, we develop Memory-Oriented Distributed Computing\n(MODC), a framework for programming disaggregated architectures that borrows\nand adapts ideas from task-based programming models, concurrent programming\ntechniques, and lock-free data structures. This framework includes a task-based\napplication programming model and a runtime system that provides scheduling,\ncoordination, and fault tolerance mechanisms. We present highlights of our MODC\nprototype and experimental results demonstrating that MODC-style resilience\noutperforms a checkpoint-based approach in the face of failures.\n", "doi": null, "arxiv_id": "2109.05329", "pdf_urls": ["https://arxiv.org/pdf/2109.05329"], "github": [], "is_oa": true, "sources": ["open-arxiv"], "type": "conference", "journal_ref": "Proceedings of 2nd Workshop on Resource Disaggregation and\n  Serverless (WORDS'21), Co-located with ASPLOS'21, April 2021", "categories": "cs.DC"}