diff --git a/.gitattributes b/.gitattributes index bed0738c7eeb449bca98b5d2f33c89a1ee56349a..0acf6967564ad212ff76ec5f6d9cd5d806699bfc 100644 --- a/.gitattributes +++ b/.gitattributes @@ -58,3 +58,21 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text # Video files - compressed *.mp4 filter=lfs diff=lfs merge=lfs -text *.webm filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/reference/amp_004_folded_cascode.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/reference/amp_017_tan_clia.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/reference/amp_019_ti_ldo_error.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/reference/amp_032_ti_ldo_error_selfbias.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/reference/amp_033_ti_ldo_ref_selfbias.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/reference/cmfb_003_5t_nmos_input.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/reference/cmp_001_hyst_diffpair.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/reference/cmp_002_strongarm.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/reference/ldo_002_analoggym_folded_cascode.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/reference/ldo_003_analoggym_simple.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/reference/ldo_004_basic_pmos.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/reference/ldo_005_buffered_ref.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/reference/ldo_007_pmos.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/reference/sup_001_vcm_detector.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/reference/tsn_001_ptat_2t.gds filter=lfs diff=lfs merge=lfs -text +tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/reference/vco.gds filter=lfs diff=lfs merge=lfs -text +tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/reference/DIFF_COMPARATOR.gds filter=lfs diff=lfs merge=lfs -text +tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/reference/two_stage_OTA_layout.gds filter=lfs diff=lfs merge=lfs -text diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..003548475c0b7ab8d586c9e4c4fd2dd50321ebf1 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2026 Layout-Bench contributors + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3fb04bb86ff2735f71c7a9c8eb242cf96d5fbff3 --- /dev/null +++ b/README.md @@ -0,0 +1,204 @@ +--- +language: +- en +tags: +- integrated-circuits +- electronic-design-automation +- benchmark +license: other +license_name: component-specific +license_link: https://huggingface.co/datasets/MAI716/ICLayout-Bench/blob/main/README.md#licensing +configs: +- config_name: default + data_files: + - split: test + path: data.jsonl +--- + +# ICLayout-Bench Dataset + +81 circuit-layout tasks across FreePDK45, GF180MCU and IHP SG13G2, for the +[ICLayout-Bench evaluator](https://github.com/lizhangmai/ICLayout-Bench). +Each task supplies a netlist, layout requirements, test stimuli, scoring contract +and a reference layout. Available on [Hugging Face](https://huggingface.co/datasets/MAI716/ICLayout-Bench). + +## Load and select + +```python +from datasets import load_dataset + +repo_id = "MAI716/ICLayout-Bench" +tasks = load_dataset(repo_id, split="test") # Complete corpus. +core = tasks.filter(lambda task: task["in_core"]) # Current 16-task benchmark. +print(tasks[0]["problem"]) +``` + +`data.jsonl` contains every task, sorted by stable ID. The boolean `in_core` +field is generated from the same field in each `case.toml`; +changing this selection never removes tasks from the corpus. See the +[selection rationale](#core-selection-rationale). Participant experiments can choose +`name = "all"` and a `tasks` filter without changing core. + +Rows contain `id`, `in_core`, `title`, `category`, `summary`, `pdk`, `collection`, `task_kind`, +`status`, `source_url`, `problem`, and relative paths/digests for task files, +netlists, process declarations and licenses. The JSONL table is a generated view; +`case.toml` owns task metadata and requirements. + +For assets, use a local checkout or `huggingface_hub.snapshot_download` with +`repo_type="dataset"`. Pin the table and assets to the same repository commit +using `revision` in both loading calls. A local checkout is also supported. When reloading an edited local checkout directly through +`datasets`, pass `download_mode="reuse_cache_if_exists"` to refresh cached tables. + +## Contents + +```text +tasks// + pdk.toml # Pinned process resources and profiles + README.md # Process scope and limitations, where documented + / + LICENSE # Collection terms + NOTICE # Required attribution, where applicable + cases// + case.toml # Metadata, input identities and evaluation contract + problem.md # Complete participant-facing requirements + materials/ # Netlist, test stimuli and declared presentation assets + reference/ # Reference layout; excluded from standard solver inputs +data.jsonl # Complete corpus with generated in_core membership +``` + +Source attribution is in `case.toml`; process and collection follow the directory +hierarchy. + +## Licensing + +The root [LICENSE](LICENSE) covers original project metadata and documentation. +Task materials retain the terms in each `tasks///LICENSE` and, +where present, `NOTICE`; the table exposes the corresponding license paths. +Terms vary by collection, including noncommercial restrictions for analog-db +materials. Retain applicable licenses, notices, source attribution and modification +notices when redistributing materials. External PDKs and EDA tools have their own +licenses. Technical qualification does not establish redistribution permission. + +## Scope and validation + +The problem and contract specify each task's operating points, physical checks, +measurement definitions and score. Process scope for [GF180MCU](tasks/gf180mcuD/README.md) and +[FreePDK45](tasks/freepdk45/README.md) describes resource assumptions and limitations. These are block-level benchmarks, not +manufacturing signoff or evidence of model performance. + +The current core has passed direct reference evaluation, participant checking, +final submission and numerical repeatability checks. The remaining corpus retains +historical reference observations; these do not claim fresh three-path checks +against the current evaluator. Full reports and acceptance records stay with the +author. References are available for independent verification and are excluded +from standard solver inputs. + +Install the evaluator separately to run a reference: + +```bash +python -m benchmarking.engine.preview --dataset . run \ + --case freepdk45.nangate45-pdk.NAND2_X1 --output build/reference-check +``` + +The command creates local reports under the requested output directory. Setup, +index generation and publication checks are documented in the evaluator's +[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md) +and [task qualification guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tasks.md#qualification). + +## Core selection rationale + +The core is a secondary selection of the complete corpus, chosen for capability +coverage. Its size is not a limit on the available tasks. + +
+Detailed capabilities, alternatives and selection methodology + + +Case-level `in_core` flags and scoring contracts own membership and weights. This document +records the rationale for the secondary core selection from the full Dataset, +independently of engine releases. All accepted tasks remain available in the default `test` table; +being outside core does not mean a task is unfinished or excluded from Dataset. + +### Selected capabilities + +The current set contains 16 cases across three PDKs. Each link gives the full +requirements and coefficient rationale. +Coefficients below are the existing case coefficients, not new selection weights. + +| PDK | Selected case | Coefficient | Distinct contribution | +| --- | --- | ---: | --- | +| FreePDK45 | [NAND2](tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md) | 1 | Basic connectivity, loaded logic levels and timing; an entry-level anchor. | +| FreePDK45 | [SRAM write driver](tasks/freepdk45/OpenRAM/cases/write_driver/problem.md) | 3 | Complementary loaded outputs and enabled/disabled drive states. | +| FreePDK45 | [6T SRAM cell](tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md) | 6 | Storage integrity coupled to read and write access. | +| GF180MCU | [Five-transistor OTA](tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md) | 4 | Compact differential gain and bias, with the declared dummy-device connectivity. | +| GF180MCU | [Scan DFF](tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md) | 5 | Clocked digital state and scan/data selection. | +| GF180MCU | [R-2R DAC](tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md) | 4 | A physical resistor ladder: weighted conversion under zero, one-hot and full-scale codes. | +| GF180MCU | [StrongARM comparator](tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md) | 6 | Regenerative decisions in both polarities at two input common modes, with precharge, delay and slew measurements. | +| GF180MCU | [Classic PTAT](tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md) | 6 | Temperature-dependent bias, isolated body connections and a coupled startup branch. | +| GF180MCU | [Basic PMOS LDO](tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md) | 7 | Intermediate regulation: PSRR, output impedance, dropout and recovery under changing load. | +| GF180MCU | [Four-phase VCO](tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md) | 8 | Self-oscillation, tuning and relative output phases at two control voltages. | +| IHP SG13G2 | [NMOS track-and-hold](tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md) | 5 | Physical charge storage, pedestal, drift, feedthrough and reacquisition across input/temperature conditions. | +| IHP SG13G2 | [Binary capacitor bank](tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/problem.md) | 5 | Physical 1:1:2:4 MIM weighting, eight fixed codes and parasitic-dependent gain/step accuracy. | +| IHP SG13G2 | [SiGe PAM4 driver](tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md) | 4 | Weighted HBT current steering with gain and port-reflection observations extending to 50 GHz. | +| IHP SG13G2 | [Fully differential two-stage OTA](tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md) | 9 | Coupled differential and common-mode control with compensation and transient response. | +| IHP SG13G2 | [Mirror-OTA LDO](tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md) | 9 | Complex regulation combining return-ratio crossings, startup, line/load response and recovery. | +| IHP SG13G2 | [Chopper IA with CMFB](tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md) | 10 | Clock modulation, signal feedback and actual common-mode feedback operating together. | + +The coefficient bands 1–4, 5–7 and 8–10 contain five, seven and four cases, +respectively. Their coefficient sums are 16, 40 and 36. This gives a compact +foundation, substantial intermediate coverage and a smaller demanding tail. +The RF driver remains coefficient 4 because its contract covers a compact +feedforward circuit; its specialized devices and extraction flow do not make +the coefficient an estimate of participant effort. Coefficients are capability +categories, not a measured difficulty scale. + +### Boundaries and alternatives + +The five-transistor OTA and the fully differential OTA form a deliberate +progression from compact gain/bias to interacting signal and common-mode loops. +The two LDOs similarly distinguish intermediate regulation from a broader +startup/return-ratio/recovery contract. Multiple compensated OTA variants and +same-PDK LDO alternatives remain available in the full Dataset: topology diversity alone +does not justify repeatedly weighting similar control objectives in the total. + +NAND2 supplies the basic logic anchor; AOI21 adds less incremental coverage than +controlled drive, scan state and SRAM access. The separate SRAM sense amplifier +overlaps the regenerative-decision capability represented by the StrongARM +comparator. StrongARM is preferred over the other comparator cases for its +explicit precharge, slew and two-common-mode measurements. The standalone +chopper switch overlaps clock modulation in the complete chopper IA; the +track-and-hold remains because retention and reacquisition are different goals. + +The resistor ladder and MIM bank exercise different passive networks. The MIM +bank measures all eight fixed codes but does not evaluate live code switching +or a complete SAR ADC. The resistor ladder samples ten codes, not a full +256-code linearity sweep. Small gain stages, bias/reference cells, variable +resistors, standalone CMFB blocks and simpler temperature cells remain useful +focused exercises; their incremental coverage has lower priority in this core +set than the selected complete circuits and their coupled requirements. + +The SiGe driver supplies explicitly measured high-frequency behavior. In +particular, the case named `DC_to_130_GHz_TIA.design_1` currently measures AC +behavior only through 100 MHz, so its name is not evidence of 130 GHz benchmark +coverage. The selected driver uses KLayout-PEX capacitance extraction; it does +not establish distributed interconnect resistance/inductance, eye quality or +complete RF signoff. Likewise, the VCO contract does not measure phase noise or +jitter. These limits apply when describing benchmark coverage. + +### Evidence and revision + +This selection is a structural coverage judgment grounded in published case +contracts and validation associations. It does not yet establish empirical +participant discrimination. Validate that separately with complete runs from +multiple participants and repeated trials: compare per-case success rates, +score spread, completion cost and correlations between related cases. Separate +tool errors from physical/electrical failures; do not treat unknown scores as +zero. A universally easy or hard case can still serve as an anchor, but it +should not dominate the suite through redundant companions. + +Revisit membership when evidence shows redundant outcomes or a missing +capability. Configuration and task-contract digests identify changes automatically; retain +archived definitions and avoid tuning case coefficients to obtain a preferred +ranking. + +
diff --git a/data.jsonl b/data.jsonl new file mode 100644 index 0000000000000000000000000000000000000000..45506ad93609ecb3f0488da2d015c0117ccae9dd --- /dev/null +++ b/data.jsonl @@ -0,0 +1,81 @@ +{"id":"TO_Apr2025.160GHz_LNA","in_core":false,"title":"TO_Apr2025 160-derived four-stage LNA at 100 MHz","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies voltage through four direct-coupled SiGe HBT stages with emitter degeneration and interstage bias clamps.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/160GHz_LNA/design_data/qucs-s/160GHz_LNA(MAIN).sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Four-Stage SiGe HBT Voltage Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained four-stage direct-coupled\ncommon-emitter voltage amplifier in `LNA160_FOUR_STAGE`. Preserve the circuit\nconnectivity, HBT multiplicities, passive dimensions and five external ports.\nThe submitted top cell must be `LNA160_FOUR_STAGE` and must pass the physical\nchecks and nominal post-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and drawn device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal operating-point and AC testbench |\n\nThe circuit is a four-stage direct-coupled common-emitter amplifier. Four\n`npn13G2` devices (`Nx=1`) form the gain chain. Each collector has an `rppd`\nload to `VDD`, each emitter has an `rsil` resistor to `VSS`, and the three\ninterstage collector nodes have `rppd` clamps to `VBIAS`. The emitter\nresistors are 4 µm wide with lengths 20.00, 20.01, 20.02 and 20.03 µm in\nstage order. An explicit `ptap1` connects the substrate body to `VSS`.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `IN` | Voltage input to the first HBT base |\n| `OUT` | Voltage output from the fourth collector and 50 fF load node |\n| `VDD` | Common collector-load supply, 1.2 V |\n| `VSS` | Common return and substrate-tap reference |\n| `VBIAS` | Interstage clamp-bias supply, 0.76 V |\n\nLVS and simulation use this order exactly. The netlists specify\nfour 0.07 × 0.9 µm drawn `npn13G2` devices, four 2 × 20 µm `rppd` collector\nloads, four stage-specific `rsil` emitter resistors, three 1 × 4 µm `rppd`\ninterstage clamps, and a substrate tap with `A=4 µm²`, `P=8 µm` and finite\nsimulator equivalent `R=81.6666667 Ω`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`; 27 °C |\n| Supplies and DC bias | `VDD=1.2 V`, `VSS=0 V`, `VIN=0.8 V`, `VBIAS=0.76 V` |\n| AC stimulus | 1 V at `VIN` for small-signal gain normalization |\n| Output load | 50 fF from `OUT` to `VSS` |\n| AC sweep | 1 MHz–1 GHz, 40 points per decade; gain measured at 100 MHz |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal input.\nThe deck reports the input bias, output bias, `VDD` current, `VBIAS` current\nand voltage gain; only the metrics in the table below are acceptance\ncriteria.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 10 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe five ports, HBT multiplicities, passive geometry and explicit substrate\ntap. Artifact, DRC, LVS and geometry gates all precede candidate extraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 160 µm and the maximum height is\n90 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Strict LVS\nretains the finite `ptap1` card and the drawn HBT geometry. In the simulator\nexport, the ordinary `npn13G2` model supplies its effective device dimensions\nwhile `Nx=1` and all terminal connections are preserved; the drawn LVS\ndimensions are not silently used as behavioral dimensions. The candidate path\nreconciles the approved SG13G2 substrate body boundary to `VSS` with tap\nextraction disabled. The finite source tap remains in calibration. Only the internal HBT body domain, identified through its physical tap\nreturn, may be reconciled to VSS. Collector, base, emitter, resistor terminals\nand geometry, and top-level ports remain candidate-derived. No other\ninternal-node aliases or simulator global-ground substitutions are permitted.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `gain_db` | AC: Value of `(db(v(out)/v(in))) at=100meg`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `output_bias` | DC operating point: `v(out)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `supply_current` | DC operating point: `-i(vdd)`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **1326.32 um2**. 16 expanded device instances; sum of device/contact envelopes 836.9640 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_db` | 0.688235294117 |\n| `output_bias` | 0.052941176471 |\n| `supply_current` | 0.158823529412 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`LNA160_FOUR_STAGE` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe evaluator uses the submitted snapshot for all physical checks, extraction\nand simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml","case_sha256":"a4f6da41ad22694e6f4a6a3d59aa2a1c186e5c52448168ba8a4800c20c981d65","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/circuit.cdl","netlist_sha256":"26b815aa103d0d81b54e21c661b28860304a5d23be900d17192cbb92100be3c6","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"} +{"id":"TO_Apr2025.40_GHZ_LOW_NOISE_TIA","in_core":false,"title":"TO_Apr2025 40 GHz low-noise single-ended TIA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts input current to voltage through three SiGe HBT stages with resistive feedback and emitter degeneration.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/40_GHZ_LOW_NOISE_TIA/design_data/qucs-s/40_GHz_Low_Noise_TIA.sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Three-Stage SiGe HBT Transimpedance Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained three-stage, single-ended\ntransimpedance amplifier in `FDM_QNC_00_LN_TIA`. Preserve the circuit\nconnectivity, device multiplicities, passive dimensions and six external\nports. The submitted top cell must be `FDM_QNC_00_LN_TIA` and must pass the\nphysical checks and nominal post-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal pre-layout and post-layout operating-point and AC testbench |\n\nThe circuit is a three-stage SiGe HBT transimpedance core. Q1 is the input\ncommon-emitter device (`Nx=5`), Q2 is the intermediate common-collector\ndevice (`Nx=10`), and Q3 is the output common-emitter device (`Nx=10`). The\nresistor network provides collector loads, emitter degeneration and feedback;\nthree `cap_cmim` capacitors decouple the independent supply rails. The\nexplicit `ptap1` connects the substrate body to `VSS`.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `RFin` | Current input and transimpedance sensing node |\n| `RFout` | Voltage output and 50 fF load node |\n| `VSS` | Common return and substrate-tap reference |\n| `vcc1` | Q1 collector-load supply, 1.7 V |\n| `vcc2` | Q2 collector supply, 2.1 V |\n| `vcc3` | Q3 collector-load supply, 2.1 V |\n\nLVS and simulation use this order exactly. The netlists specify\nthree `npn13G2` devices, `rppd` and `rsil` resistors, 30 × 60 µm `cap_cmim`\ndevices with `m=2`, and a substrate tap with `A=25 µm²`, `P=20 µm` and\nfinite simulator equivalent `R=21.7391304348 Ω`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`, `cap_typ`; 26.85 °C |\n| Supplies | `vcc1=1.7 V`, `vcc2=2.1 V`, `vcc3=2.1 V` |\n| Input DC current | −100 µA, 0 A and +100 µA from `VSS` into `RFin` |\n| AC stimulus | 1 A at the zero-volt `VSENSE` source for normalization |\n| Output load | 50 fF from `RFout` to `VSS` |\n| AC sweep | 1 MHz–100 MHz, 40 points per decade |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal 1 A\ninput. Transfer uses the current measured at `VSENSE`, and supply power is\ncalculated from the three independent supply sources.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 32 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe six ports, device multiplicities, passive geometry and explicit substrate\ntap. Artifact, DRC, strict LVS and geometry gates all precede candidate\nextraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 660 µm and the maximum height is\n620 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Drawn emitter\ngeometry is checked against the candidate; effective ordinary `npn13G2`\ndimensions use the simulator model defaults, with the extracted `Nx` retained. The standard\npath disables tap extraction at the approved SG13G2 substrate boundary so\nthe compact-device body can be reconciled to `VSS`; strict LVS still checks\nthe finite `ptap1` card. Device terminals, multiplicities, resistor geometry,\nMIM geometry and top-level connectivity remain candidate-derived. The\nfinite source tap is retained in pre-layout calibration, and the accepted\nmodel boundary is limited to the nominal low-frequency transfer and bias\nmeasurements in this task. No other internal-node aliases are permitted; a simulator global ground\nalias must not replace the explicit source substrate connection.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `transimpedance_low` | AC: Value of `(real(v(RFout)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `transimpedance_high` | AC: Value of `(mag(v(RFout)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `input_bias` | DC operating point: `v(RFin)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `output_bias` | DC operating point: `v(RFout)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `supply_power` | DC operating point: `-v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)-v(vcc3)*i(VCC3)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **18573.26 um2**. 15 expanded device instances; sum of device/contact envelopes 12204.4550 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `transimpedance_high` | 0.344117647059 |\n| `transimpedance_low` | 0.344117647059 |\n| `input_bias` | 0.026470588235 |\n| `output_bias` | 0.026470588235 |\n| `supply_power` | 0.158823529412 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`FDM_QNC_00_LN_TIA` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe explicit submission command is required after the file has been\nvalidated. The evaluator uses the submitted snapshot for all physical checks,\nextraction and simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml","case_sha256":"dc96d8b5faa197829ac8b5f9258b11e647e8c3d406fce9b51a3c2d2238411d7d","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/circuit.cdl","netlist_sha256":"17a094c09698acfbe6a25a50d3a0292ebb82fd82b7e21269442bcdd4fa3c0d45","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"} +{"id":"TO_Apr2025.97_GHZ_LINEAR_TIA","in_core":false,"title":"TO_Apr2025 97-derived multi-stage linear TIA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts input current to voltage using three SiGe HBT stages and active emitter-follower feedback.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/97_GHZ_LINEAR_TIA/design_data/qucs-s/97_GHZ_LINEAR_TIA.sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Linear SiGe HBT Transimpedance Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained multi-stage linear\ntransimpedance amplifier in `FMD_QNC_01_LIN_TIA`. Preserve the circuit\nconnectivity, HBT multiplicities, passive dimensions and six external ports.\nThe submitted top cell must be `FMD_QNC_01_LIN_TIA` and must pass the physical\nchecks and nominal post-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal operating-point, AC and DC-linearity testbench |\n\nThe circuit is a three-stage SiGe HBT transimpedance core with active\nfeedback. Q1 is the input common-emitter device (`Nx=5`), Q2 is the\nintermediate emitter follower (`Nx=10`), Q3 is the output common-emitter\ndevice (`Nx=10`), and Q4 is an active emitter-follower feedback device\n(`Nx=5`) sensing `RFOUT`. `RFB` returns the Q4 feedback signal to the\nQ2/Q3 interstage node. The remaining resistors provide collector loading,\nemitter degeneration and input feedback; three `cap_cmim` devices decouple\nthe independent supply rails. An explicit `ptap1` connects the substrate\nbody to `VSS`.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `RFIN` | Current input and transimpedance sensing node |\n| `RFOUT` | Voltage output and 50 fF load node |\n| `VCC1` | First collector-load supply, 1.7 V |\n| `VCC2` | Q2/Q4 collector supply, 2.1 V |\n| `VCC3` | Q3 collector-load supply, 2.1 V |\n| `VSS` | Common return and substrate-tap reference |\n\nLVS and simulation use this order exactly. The netlists specify\nthe HBT multiplicities, resistor dimensions, 30 × 60 µm `cap_cmim` devices\nwith `m=2`, and a substrate tap with `A=4 µm²`, `P=8 µm` and finite\nsimulator equivalent `R=81.6666667 Ω`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`, `cap_typ`; 26.85 °C |\n| Supplies | `VCC1=1.7 V`, `VCC2=2.1 V`, `VCC3=2.1 V` |\n| Input DC current | −5 µA, 0 A and +5 µA from `VSS` into `RFIN` |\n| AC stimulus | 1 A at the zero-volt `VSENSE` source for normalization |\n| Output load | 50 fF from `RFOUT` to `VSS` |\n| AC sweep | 1 MHz–100 MHz, 40 points per decade |\n| Linearity sweep | 21 DC points from −5 µA to +5 µA in 0.5 µA steps |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal 1 A\ninput. Transfer is normalized by the current measured at `VSENSE`, and\nsupply power is calculated from the three independent supply sources.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 32 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe six ports, device multiplicities, passive geometry and explicit substrate\ntap. Artifact, DRC, strict LVS and geometry gates all precede candidate\nextraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 720 µm and the maximum height is\n620 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Drawn emitter\ngeometry is checked against the candidate; effective ordinary `npn13G2`\ndimensions use the simulator model defaults, with the extracted `Nx` retained. The standard\npath disables tap extraction at the approved SG13G2 substrate boundary so\nthe compact-device body can be reconciled to `VSS`; strict LVS still checks\nthe finite `ptap1` card. Device terminals, multiplicities, resistor geometry,\nMIM geometry and top-level connectivity remain candidate-derived. The\nfinite source tap is retained in pre-layout calibration, and the accepted\nmodel boundary is limited to the nominal transfer, bias, power and linearity\nmeasurements in this task. No other internal-node aliases are permitted; a simulator global ground\nalias must not replace the explicit source substrate connection.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `transimpedance_low` | AC: Value of `(real(v(RFOUT)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `transimpedance_high` | AC: Value of `(mag(v(RFOUT)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `linearity_error_pct` | Maximum absolute deviation of DC RFOUT from the line through the endpoint samples, divided by absolute output span, times 100; IIN sweeps -5 to +5 uA in 0.5 uA steps. | percent | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `input_bias` | DC operating point: `v(RFIN)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `output_bias` | DC operating point: `v(RFOUT)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `supply_power` | DC operating point: `-v(VCC1)*i(VCC1)-v(VCC2)*i(VCC2)-v(VCC3)*i(VCC3)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **18718.54 um2**. 17 expanded device instances; sum of device/contact envelopes 12300.6100 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 53.2%; linearity 20.5%; bias 4.09%; supply cost 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `transimpedance_high` | 0.265909090909 |\n| `transimpedance_low` | 0.265909090909 |\n| `linearity_error_pct` | 0.204545454545 |\n| `input_bias` | 0.020454545455 |\n| `output_bias` | 0.020454545455 |\n| `supply_power` | 0.122727272727 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`FMD_QNC_01_LIN_TIA` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe evaluator uses the submitted snapshot for all physical checks, extraction\nand simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml","case_sha256":"7f46e608f85c1375b19a29ba2ed65c64623fe1338f7a36885ebd559581d49ce4","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/circuit.cdl","netlist_sha256":"150ab19522eecccf2889ed62c07b14e15e29e97a75ce12563fcd95d846be9112","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"} +{"id":"TO_Apr2025.DC_to_130_GHz_TIA.design_1","in_core":false,"title":"Two-stage SiGe HBT TIA with nominal AC/DC requirements","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts input current to voltage through two direct-coupled SiGe HBT stages with first-stage resistive feedback.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/DC_to_130_GHz_TIA/design_1/design_data/qucs-s/DC_to_130_GHz_TIA.sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Two-Stage SiGe HBT Transimpedance Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained two-stage transimpedance\namplifier in `FMD_QNC_03a_TIA_1`. Preserve the circuit connectivity, HBT\nmultiplicities, passive dimensions and five external ports. The submitted top\ncell must be `FMD_QNC_03a_TIA_1` and must pass the physical checks and nominal\npost-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal operating-point and AC testbench |\n\nThe circuit is a two-stage SiGe HBT transimpedance core. Q1 is the first\ncommon-emitter stage (`Nx=5`) and drives Q2, the second common-emitter stage\n(`Nx=4`). `RC1` and `RC2` are independent collector loads, `RRF` provides\nfirst-stage resistive feedback from `DN1` to `INPUT`, and `C1` and `C2`\ndecouple the two supply rails. The explicit `ptap1` has both terminals on\n`VEE`, so it is a same-net substrate tie.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `INPUT` | Current input and transimpedance sensing node |\n| `OUTPUT` | Voltage output and 50 fF load node |\n| `VCC2V` | Q1 collector-load supply, 2 V |\n| `VCC2V1` | Q2 collector-load supply, 2 V |\n| `VEE` | Common return and substrate reference |\n\nLVS and simulation use this order exactly. The netlists specify\n`npn13G2` devices with `Nx=5` and `Nx=4`, `rppd` resistors with dimensions\n15 × 4 µm, 11.5 × 2 µm and 29 × 6.3 µm, two 30 × 30 µm `cap_cmim`\ndevices with `m=1`, and the tap geometry `A=3.6504 µm²`, `P=18.72 µm`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`, `cap_typ`; 26.85 °C |\n| Supplies | `VCC2V=2 V`, `VCC2V1=2 V`, `VEE=0 V` |\n| Input DC current | −100 µA, 0 A and +100 µA from the return into `INPUT` |\n| AC stimulus | 1 A at the zero-volt `VSENSE` source for normalization |\n| Output load | 50 fF from `OUTPUT` to the simulator return |\n| External loads | No external resistive input or output load |\n| AC sweep | 1 MHz–100 MHz, 40 points per decade |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal 1 A\ninput. The shunt anchors DC-floating capacitive islands while retaining their\nAC coupling. Transfer is normalized by the current measured at `VSENSE`, and\nsupply power is calculated from the two independent supply sources.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 32 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe five ports, device multiplicities, passive geometry and the same-net\nsubstrate tap. Artifact, DRC, LVS and geometry gates all precede candidate\nextraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 720 µm and the maximum height is\n860 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Drawn emitter\ngeometry is checked against the candidate; effective ordinary `npn13G2`\ndimensions use the simulator model defaults, with the extracted `Nx` retained. It preserves\ndevice terminals, resistor and MIM geometry, top-level connectivity and the\nsame-net substrate boundary. The simulator export represents the tap with\nits finite PDK equivalent `R=43.80789 Ω`; because both tap terminals are\n`VEE`, this element has no DC voltage drop. The `rshunt` conditioning and\nsubstrate boundary are numerical model choices and do not add an external\nport or change the maintained circuit.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `transimpedance_low` | AC: Value of `(real(v(output)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `transimpedance_high` | AC: Value of `(mag(v(output)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `input_bias` | DC operating point: `v(input)`. | V | target / target | 0 … 2.0 | 2.0 | bias |\n| `output_bias` | DC operating point: `v(output)`. | V | target / target | 0 … 2.0 | 2.0 | bias |\n| `supply_power` | DC operating point: `-v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **3852.28 um2**. 8 expanded device instances; sum of device/contact envelopes 2487.4228 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `transimpedance_high` | 0.344117647059 |\n| `transimpedance_low` | 0.344117647059 |\n| `input_bias` | 0.026470588235 |\n| `output_bias` | 0.026470588235 |\n| `supply_power` | 0.158823529412 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`FMD_QNC_03a_TIA_1` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe evaluator uses the submitted snapshot for all physical checks, extraction\nand simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml","case_sha256":"14aae4dca4c95dbe6ec8c9e6afa48112cba35b8993ad40207511749810fffd14","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/circuit.cdl","netlist_sha256":"41054606cd4c4845149df6c9a38a7d38d45ae4ba22afb5ff588d33051aaf06f3","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"} +{"id":"freepdk45.OpenRAM.cell_6t","in_core":true,"title":"Six-Transistor SRAM Bitcell","pdk":"freepdk45","category":"Logic & memory","summary":"Stores one bit using cross-coupled inverters and wordline-controlled access transistors.","source_url":"https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/cell_6t.sp","status":"qualified","collection":"OpenRAM","task_kind":"netlist_to_gds","problem":"# Six-Transistor SRAM Bitcell Layout Task\n\n## Objective\n\nImplement the supplied six-transistor SRAM bitcell, including cross-coupled storage, complementary bitlines and a common wordline. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `cell_6t`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `bl br wl vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nEach bitline has 10 fF. Ideal external switches (10 ohm on, 1e12 ohm off) implement write and precharge. Write BL=0/BR=1 during 0–500 ps, then precharge and read at 1 ns and 2 ns; write the opposite value at 4–4.5 ns, then read at 5 ns and 6 ns. Sample differential bitline voltage 110 ps after each read starts. Wordline transitions take 10 ps; read pulses last 300 ps. The second read checks retention after a nondestructive read and idle interval. The supplied deck gives every switch edge. Power includes DUT supply current and the precharge supply over 0–7 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `read0` | `find par('v(br)-v(bl)') at=1110p` | V | functional check | 0.3 … +∞ | — |\n| `repeat0` | `find par('v(br)-v(bl)') at=2110p` | V | functional check | 0.3 … +∞ | — |\n| `read1` | `find par('v(bl)-v(br)') at=5110p` | V | functional check | 0.3 … +∞ | — |\n| `repeat1` | `find par('v(bl)-v(br)') at=6110p` | V | functional check | 0.3 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=7n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `read_delay` | WL rising through 0.5 V to signed bitline difference reaching 0.1 V, for read edges at 1, 2, 5 and 6 ns (distinct from the 0.3 V sampled-level requirement). | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **1.46 um2**. 6 expanded device instances; sum of device/contact envelopes 0.6670 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSRAM cell: read delay 64%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.2 |\n| `read_delay` | 0.640000000000 |\n| `supply` | 0.160000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml","case_sha256":"6c2679fb5cb32d7cd00408e7808ee42dbc1da3e896cea43ed2737f606383d15f","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md","netlist_path":"tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice","netlist_sha256":"18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488","license_path":"tasks/freepdk45/OpenRAM/LICENSE"} +{"id":"freepdk45.OpenRAM.sense_amp","in_core":false,"title":"Clocked SRAM Sense Amplifier","pdk":"freepdk45","category":"Logic & memory","summary":"Resolves a small bitline voltage difference into a clocked digital decision.","source_url":"https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/sense_amp.sp","status":"qualified","collection":"OpenRAM","task_kind":"netlist_to_gds","problem":"# Clocked SRAM Sense Amplifier Layout Task\n\n## Objective\n\nImplement the supplied clocked regenerative sense amplifier. A lower sampled BL than BR must produce a low Dout; the opposite differential must produce a high Dout. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `sense_amp`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `bl br dout sclk vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nBL/BR are 0.8/1.0 V for the first decision and 1.0/0.8 V for the second. SCLK is low while sampling and rises at 500 ps and 1500 ps with 10 ps edges; it stays high for 480 ps. Dout drives 0.5 fF. Sample Dout at 610 ps and 1610 ps. Average supply power over 0–2 ns. This is a 200 mV differential, loaded decision task; 50 mV sensitivity is not specified.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `low` | `find v(dout) at=610p` | V | functional check | −∞ … 0.1 | — |\n| `high` | `find v(dout) at=1610p` | V | functional check | 0.9 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `decision_delay_fall` | SCLK 50% to Dout 50% decision delay; see testbench window. | s | minimize / ratio | 0.0 … +∞ | — |\n\nArea reference: **2.82 um2**. 7 expanded device instances; sum of device/contact envelopes 1.4529 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `decision_delay_fall` | 0.680000000000 |\n| `supply` | 0.170000000000 |\n\nOnly the falling output decision delay contributes to timing quality. Both\ndecision polarities must satisfy their sampled final-level checks; rising\ndecision timing is outside this task's measured objective.\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml","case_sha256":"8328dbb68781a7494f950d373dc294d519ddfe7115bc9f11ad7b4d0d02c7fb8a","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md","netlist_path":"tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice","netlist_sha256":"f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f","license_path":"tasks/freepdk45/OpenRAM/LICENSE"} +{"id":"freepdk45.OpenRAM.write_driver","in_core":true,"title":"Complementary SRAM Write Driver","pdk":"freepdk45","category":"Logic & memory","summary":"Drives complementary bitlines during a write and releases them when disabled.","source_url":"https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/write_driver.sp","status":"qualified","collection":"OpenRAM","task_kind":"netlist_to_gds","problem":"# Complementary SRAM Write Driver Layout Task\n\n## Objective\n\nImplement the supplied complementary tri-state write driver: WEN=1 drives BL=DIN and BR=NOT DIN; WEN=0 disables both outputs. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `write_driver`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `din bl br wen vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nBL and BR each drive 10 fF and a 100 kohm resistor to 0.5 V. DIN starts low, rises at 500 ps and falls at 1 ns, with 10 ps edges and a 1 ns period. WEN is high until 2 ns and falls over 10 ps. Sample the enabled complementary outputs at 300 ps and 710 ps, and both disabled outputs at 11.9 ns. The passive midpoint loads test high impedance without accessing internal nodes. Average DUT supply power over 0–2 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `bl_low` | `find v(bl) at=300p` | V | functional check | −∞ … 0.1 | — |\n| `br_high` | `find v(br) at=300p` | V | functional check | 0.9 … +∞ | — |\n| `bl_high` | `find v(bl) at=710p` | V | functional check | 0.9 … +∞ | — |\n| `br_low` | `find v(br) at=710p` | V | functional check | −∞ … 0.1 | — |\n| `z_bl` | `find v(bl) at=11.9n` | V | functional check | 0.45 … 0.55 | — |\n| `z_br` | `find v(br) at=11.9n` | V | functional check | 0.45 … 0.55 | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `data_delay` | DIN rising through 0.5 V after 0.5 ns to BL rising or BR falling through 0.5 V; both arcs are source-paired. | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **3.36 um2**. 12 expanded device instances; sum of device/contact envelopes 1.7748 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **3**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `data_delay` | 0.680000000000 |\n| `supply` | 0.170000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/OpenRAM/cases/write_driver/case.toml","case_sha256":"344c861ca5e70437c468459eb92ecca2682a2025c4ff1fa304260a1ae34ebdd4","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/OpenRAM/cases/write_driver/problem.md","netlist_path":"tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice","netlist_sha256":"40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4","license_path":"tasks/freepdk45/OpenRAM/LICENSE"} +{"id":"freepdk45.nangate45-pdk.AOI21_X1","in_core":false,"title":"AND-OR-Invert Gate","pdk":"freepdk45","category":"Logic & memory","summary":"Implements AND-OR-invert logic in a fixed-height standard cell.","source_url":"https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/AOI21_X1.spi","status":"qualified","collection":"nangate45-pdk","task_kind":"netlist_to_gds","problem":"# AND-OR-Invert Gate Layout Task\n\n## Objective\n\nImplement ZN = NOT (A OR (B1 AND B2)) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `AOI21_X1`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `A B1 B2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nZN drives 5 fF. Apply the three-bit Gray cycle 000, 001, 011, 010, 110, 111, 101, 100, 000 and then its reverse to A/B1/B2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This covers the truth table and both directions of every transition in that cycle. Average DUT supply power over 0–8.4 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n\nThe standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.\n\n- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_4` | `find v(ZN) at=2.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_5` | `find v(ZN) at=2.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_7` | `find v(ZN) at=3.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_9` | `find v(ZN) at=4.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_10` | `find v(ZN) at=5.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_11` | `find v(ZN) at=5.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_12` | `find v(ZN) at=6.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_13` | `find v(ZN) at=6.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_14` | `find v(ZN) at=7.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_15` | `find v(ZN) at=7.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_16` | `find v(ZN) at=8.110n` | V | functional check | 0.9 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=8.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `propagation_delay` | Worst paired quality over: delay_b1_fall_2, delay_b2_rise_3, delay_a_fall_4, delay_a_rise_8, delay_a_fall_9, delay_a_rise_13, delay_b2_fall_14, delay_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — |\n| `output_transition` | Worst paired quality over: transition_b1_fall_2, transition_b2_rise_3, transition_a_fall_4, transition_a_rise_8, transition_a_fall_9, transition_a_rise_13, transition_b2_fall_14, transition_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **2.0049 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.23 by 1.63 um = 2.0049 um2. Reference SHA-256: 1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94. This footprint includes the maintained explicit taps and routing.\n\nThe capability coefficient remains **2**; it is independent of\nthe reference-relative task score.\n\n### Standard-cell design guidance\n\nPlan the device rows, power rails and signal access before routing. Represent\npull-up and pull-down connectivity as transistor-edge graphs; explore compatible\nEuler trails and alternative orderings to share diffusion and reduce breaks.\nChoose among legal orderings using routing length, parasitic loading and signal\naccess, rather than diffusion sharing alone. Preserve the fixed netlist sizes,\nmodels and connectivity; size optimization is outside this task.\n\nUse the task's declared row height, grid and rail geometry. Keep local routes\ncompact, leave signal pins accessible, and avoid consuming extra routing layers\nwithout benefit. Check DRC and named-port LVS, then extract the candidate and\ncompare both transition directions and power with the source simulation. Iterate\non measured parasitic effects rather than visual compactness alone. These are\noptional techniques, not a mandated algorithm or reference placement.\n\nAdapted from Xu et al., *Standard Cell Library Design and Optimization Methodology\nfor ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,\ntrack counts and process-specific dimensions do not apply to this task.\n\n\n### Score weights\n\nStandard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.2 |\n| `propagation_delay` | 0.480000000000 |\n| `output_transition` | 0.160000000000 |\n| `supply` | 0.160000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml","case_sha256":"d9ce43cffb98fa1756ef7ba34c343716a1f413f55bef095b6f6dce04a4344ce5","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md","netlist_path":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice","netlist_sha256":"07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e","license_path":"tasks/freepdk45/nangate45-pdk/LICENSE"} +{"id":"freepdk45.nangate45-pdk.NAND2_X1","in_core":true,"title":"Two-Input NAND","pdk":"freepdk45","category":"Logic & memory","summary":"Implements two-input NAND logic in a fixed-height standard cell.","source_url":"https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/NAND2_X1.spi","status":"qualified","collection":"nangate45-pdk","task_kind":"netlist_to_gds","problem":"# Two-Input NAND Layout Task\n\n## Objective\n\nImplement ZN = NOT (A1 AND A2) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `NAND2_X1`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `A1 A2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nZN drives 5 fF. Apply 00, 01, 11, 10, 00, 10, 11, 01, 00 to A1/A2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This visits the full truth table and both directions of each single-input transition. Average DUT supply power over 0–4.4 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n\nThe standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.\n\n- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_4` | `find v(ZN) at=2.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_5` | `find v(ZN) at=2.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_7` | `find v(ZN) at=3.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=4.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `propagation_delay` | Worst paired quality over: delay_a1_fall_2, delay_a2_rise_3, delay_a2_fall_6, delay_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — |\n| `output_transition` | Worst paired quality over: transition_a1_fall_2, transition_a2_rise_3, transition_a2_fall_6, transition_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **1.6789 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.03 by 1.63 um = 1.6789 um2. Reference SHA-256: d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f. This footprint includes the maintained explicit taps and routing.\n\nThe capability coefficient remains **1**; it is independent of\nthe reference-relative task score.\n\n### Standard-cell design guidance\n\nPlan the device rows, power rails and signal access before routing. Represent\npull-up and pull-down connectivity as transistor-edge graphs; explore compatible\nEuler trails and alternative orderings to share diffusion and reduce breaks.\nChoose among legal orderings using routing length, parasitic loading and signal\naccess, rather than diffusion sharing alone. Preserve the fixed netlist sizes,\nmodels and connectivity; size optimization is outside this task.\n\nUse the task's declared row height, grid and rail geometry. Keep local routes\ncompact, leave signal pins accessible, and avoid consuming extra routing layers\nwithout benefit. Check DRC and named-port LVS, then extract the candidate and\ncompare both transition directions and power with the source simulation. Iterate\non measured parasitic effects rather than visual compactness alone. These are\noptional techniques, not a mandated algorithm or reference placement.\n\nAdapted from Xu et al., *Standard Cell Library Design and Optimization Methodology\nfor ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,\ntrack counts and process-specific dimensions do not apply to this task.\n\n\n### Score weights\n\nStandard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.2 |\n| `propagation_delay` | 0.480000000000 |\n| `output_transition` | 0.160000000000 |\n| `supply` | 0.160000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml","case_sha256":"c3ac5b9c510046ebbca1312d025e605fd5e29b72f4208e34da04cac1078f5aeb","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md","netlist_path":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice","netlist_sha256":"1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0","license_path":"tasks/freepdk45/nangate45-pdk/LICENSE"} +{"id":"gf180mcuD.2AMLogic-sar-adc.track_switch","in_core":false,"title":"Dummy-Compensated Track Switch","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Tracks an analog input through a transmission gate with dummy compensation.","source_url":"https://github.com/2AMLogic/gf180-sar-adc/tree/c32c8da53e52fbb7d75f6f628b8cc9f6f45a13fc/design/adc-top/adc_top.spice","status":"qualified","collection":"2AMLogic-sar-adc","task_kind":"netlist_to_gds","problem":"# Dummy-Compensated Track Switch Layout Task\n\n## Objective\n\nImplement `adc_tgate_dum` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Complementary-clock tracking, settling and hold feedthrough for 0.5 V / 2.5 V steps and a 1 pF output capacitor.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `vin, vout, clk, clkb, vdd, vss`.\nvin: signal input; vout: sampled output; clk/clkb: complementary track control; vdd/vss: supply and device body connections.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C with a 1 pF capacitor from vout to vss. Vin begins at 0.5 V, rises to 2.5 V at 5.1 ns, falls to 0.5 V at 30.1 ns and rises to 2.5 V at 55.1 ns. Track initially (clk=3.3 V, clkb=0 V), hold from 20.1 to 45 ns and resume tracking at 45.1 ns. All transitions take 0.1 ns. Simulate to 70 ns with a 0.01 ns requested step. The four MOS widths are fixed to the upstream default values: 40, 80, 17.5 and 35 um; every channel length is 0.28 um. vss is the explicit form of the original global ground connection.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `adc_tgate_dum` and at most 10485760 bytes. Its functional bounding box must not exceed 160 by 160 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `high` | vout at 19 and 69 ns. | V | functional check | 2.48 … 2.52 | — |\n| `low` | vout at 54 ns, after tracking resumes with vin=0.5 V. | V | functional check | 0.48 … 0.52 | — |\n| `hold` | Maximum absolute vout-2.5 V over 21–44 ns, including the vin transition while the switch is open. | V | minimize / ratio | 0 … 3.3 | 0.02 |\n| `settling` | First vin rising 1.5 V crossing to vout reaching 2.48 V. | s | minimize / ratio | 0 … +∞ | 1e-15 |\n\nThe tracking checks define a 1% settling-accuracy task: 20 mV is 1% of\nthe declared 2 V input step. Both sampled tracking levels must meet that\naccuracy; the settling measurement uses the same high-level boundary.\nThis is an explicit sampled acquisition requirement, not a tolerance fitted\nto the reference layout. Hold error remains continuous quality, with q=(source_error+0.02 V)/\n(candidate_error+0.02 V), so reducing absolute error always improves quality.\nThe 20 mV floor uses the declared acquisition-accuracy scale and keeps\nnear-zero source error well-conditioned; it is not a hold-error pass threshold.\n\nArea reference: **702.46 um2**. 4 expanded device instances; sum of device/contact envelopes 411.5400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTrack/hold switches: acquisition 39.4%; hold fidelity 50.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `settling` | 0.393750000000 |\n| `hold` | 0.506250000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml","case_sha256":"f286c12fd475fce7956745d2e16ead5fac4babe3bcf335db0029bd3cbe4ba314","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md","netlist_path":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice","netlist_sha256":"24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd","license_path":"tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE"} +{"id":"gf180mcuD.Chipathon2023_ADC.comparator","in_core":false,"title":"Dynamic Comparator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Compares two input voltages using a clocked regenerative decision.","source_url":"https://github.com/ishi-kai/Chipathon2023_ADC/tree/3dce439b2125a9d628e43be40c65cf8fce5d795c/gitefu/comp_20240331/comp_20240331.sch","status":"qualified","collection":"Chipathon2023_ADC","task_kind":"netlist_to_gds","problem":"# Dynamic Comparator Layout Task\n\n## Objective\n\nImplement `comp_20240331` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Clocked differential decisions for both signs of a 20 mV input difference at 1.65 V common mode, 50 MHz and 50 fF per output.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `VDD, CLK, VOUTP, VOUTN, VINP, VINN, VSS`.\nVDD/VSS: supply/return; CLK: clock; VINP/VINN: differential inputs; VOUTP/VOUTN: directional differential outputs.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C. The clock begins rising at 10 ns and repeats every 20 ns, with 0.1 ns rise/fall and 10 ns high time. Each output has 50 fF to ground. Evaluate polarity = -1 and +1 separately: VINP = 1.65 + polarity*0.01 V and VINN = 1.65 - polarity*0.01 V. Simulate to 100 ns with a 0.01 ns requested step.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `comp_20240331` and at most 10485760 bytes. Its functional bounding box must not exceed 200 by 100 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `decision` | polarity*(VOUTP-VOUTN) at 99 ns. | V | functional check | 2.97 … +∞ | — |\n| `delay` | Final clock rising 1.65 V crossing after 80 ns to the corresponding directional output crossing 2.97 V. | s | minimize / ratio | 0 … +∞ | — |\n| `supply` | Average power delivered by VDD over 20–100 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **301.49 um2**. 15 expanded device instances; sum of device/contact envelopes 164.1600 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nClocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `delay` | 0.710526315789 |\n| `supply` | 0.189473684211 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml","case_sha256":"38d81022f3034a87f5450f6d6c148a6aeb851c21ac5d4ab3f6ef3f6e3eeb5826","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/problem.md","netlist_path":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice","netlist_sha256":"0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d","license_path":"tasks/gf180mcuD/Chipathon2023_ADC/LICENSE"} +{"id":"gf180mcuD.Jianxun-OTA.ota_5t","in_core":true,"title":"Five-Transistor OTA with Bias and Dummies","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies a differential input with a compact five-transistor OTA core and bias network.","source_url":"https://github.com/Jianxun/iic-osic-tools-project-template/tree/178a401d847ce7a602d0ce70a1ba90a15b5f9536/designs/libs/core_analog/ota_5t/ota_5t.spice","status":"qualified","collection":"Jianxun-OTA","task_kind":"netlist_to_gds","problem":"# Five-Transistor OTA with Bias and Dummies Layout Task\n\n## Objective\n\nImplement `ota_5t` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Small-signal differential gain and unity frequency at 1.65 V common mode, 10 uA bias and 1 pF load.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `vdd, out, in_p, in_n, i_bias, vss`.\nvdd/vss: supply/return; out: single-ended output; in_p/in_n: differential inputs; i_bias: current-bias input.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C, a 10 uA current from vdd into i_bias, input common mode 1.65 V and 1 pF from out to ground. The differential AC excitation is 1 V (in_p: +0.5 V; in_n: -0.5 V). Measure the DC output and supply power, then sweep 10 Hz to 1 GHz at 40 points/decade.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `ota_5t` and at most 10485760 bytes. Its functional bounding box must not exceed 320 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `gain` | 20 log10 of the single-ended differential voltage gain at 10 Hz. | dB | maximize / db20 | −∞ … +∞ | — |\n| `unity` | First falling 0 dB gain crossing in the declared AC sweep. | Hz | maximize / ratio | 0 … +∞ | — |\n| `output_bias` | DC operating-point voltage at out. | V | target / target | 0 … 3.3 | 3.3 |\n| `supply` | DC power delivered by the 3.3 V source, including the bias-current branch. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **510.1 um2**. 16 expanded device instances; sum of device/contact envelopes 291.8400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 36%; bandwidth 30%; operating points 6%; power 18%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain` | 0.360000000000 |\n| `unity` | 0.300000000000 |\n| `output_bias` | 0.060000000000 |\n| `supply` | 0.180000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml","case_sha256":"a1a3a8a82fbbaabf2bb6863d59a97ac3b653abe614f6bf611d3afaed9f8f3781","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md","netlist_path":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice","netlist_sha256":"fe6966f64eb3bc72880adca79dac070e0c0e2ea05cdc46c83f49616611d36fac","license_path":"tasks/gf180mcuD/Jianxun-OTA/LICENSE"} +{"id":"gf180mcuD.analog-db.amp_004_folded_cascode","in_core":false,"title":"Externally Biased PMOS-Input Folded-Cascode OTA","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies differential inputs with an externally biased PMOS folded-cascode stage across three supply voltages.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_004_folded_cascode","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Externally Biased PMOS-Input Folded-Cascode OTA Layout Task\n\n## Objective\n\nImplement the fixed `amp_004_folded_cascode` circuit in GF180MCU D and submit self-contained GDS.\nFourteen MOS entries (17 instances after multiplicity expansion) form a PMOS-input folded-cascode OTA with a bias mirror and cascode branches. The two ideal internal voltage sources become explicit vb1/vb2 ports. Total MOS widths, lengths and multiplicities are retained; the maintained devices use single-finger geometry instead of the upstream nf settings. Source and extracted simulation both represent this maintained implementation.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vinn vinp vout vdd ibias vss vb1 vb2`.\nIn order, these are: Negative input, positive input, output, supply, PMOS reference-current sink, return, NMOS cascode bias, and PMOS cascode bias.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVSS = 0 V; VDD = 2.7, 3.0 and 3.3 V; a 20 uA sink from ibias to VSS; VB1 = 1.2 V and VB2 = 1.95 V; external 1 pF output load. VINP has DC 1.65 V and AC +0.5 V. A 1 TH output-to-VINN inductor closes DC feedback; a 1 F coupling capacitor injects AC -0.5 V at VINN. The open-loop transfer is V(vout)/(V(vinp)-V(vinn)). These large L/C elements are external measurement apparatus. At 2.7 V the reduced headroom lowers gain and shifts the DC operating point.\n\nAC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is\nV(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp)\nfor unit differential excitation; the OTA transfer is defined above.\n\n## Physical Requirements\n\nSubmit top cell `amp_004_folded_cascode` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 400 by 340 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThe case measures small-signal unity-crossing phase margin with the declared load. Startup, large-signal settling, other loads, mismatch, noise, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — |\n| `unity_hz` | First falling 0 dB crossing of open-loop transfer | Hz | maximize / ratio | 0 … +∞ | — |\n| `phase_margin` | 180 degrees plus unwrapped transfer phase at the unity crossing | deg | target / target | 0 … 180 | 180 |\n\nArea reference: **5150.02 um2**. 17 expanded device instances; sum of device/contact envelopes 3278.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_db` | 0.270000000000 |\n| `bandwidth_hz` | 0.112500000000 |\n| `unity_hz` | 0.112500000000 |\n| `phase_margin` | 0.225000000000 |\n| `bias_v` | 0.022500000000 |\n| `output_v` | 0.022500000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml","case_sha256":"93601b6cde701068f87a90c9a7042ecbb858146278ff4b26ee44c142f94e0f68","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice","netlist_sha256":"0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.amp_017_tan_clia","in_core":false,"title":"Tan CLIA Three-Stage Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with current inversion and physical R/C compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_017_tan_clia","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Tan CLIA Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_017_tan_clia` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded NMOS branches drive voutn/net050. XM70 and XM71/XM72 form the current-inversion path through net3/net5; XM61 and the DM_1-controlled XM73 bias this path. XM68/XM69 drive the output. The 889198 ohm resistor from net5 to net2, 0.61268 pF net2-to-vss capacitor and 1.07905 pF net8-to-vout capacitor all remain.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 512 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout net1`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net1`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nGF180MCU D, nominal TT/typical, 27 C, supply 1.8 V, input reference 0.3 V,\nexternal current sink 2.32803e-06 A to vss, and 10 pF output load. Use the fixed GF180 3.3 V device binding at its authored 1.8 V operating rail; round W/L to the 5 nm manufacturing grid.\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 20 us (100 ns rise/fall, 80 us high duration), and runs to 200 us with\n10 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 80–100 and 180–200 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_017_tan_clia`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nGF180 native standalone-block DRC includes FEOL, BEOL, connectivity, manufacturing grid, antenna and dummy fill, with chip-level density and seal-ring closure outside scope. Native MIM-B uses M4/M5 and 2 fF/um2; resistors use 1 kohm/square unsilicided poly. The model boundary excludes distributed substrate resistance. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.8 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 20–200 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.8 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=88555.19 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 2 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1000 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 7: Multistage compensation includes a resistively isolated capacitor and a current-inversion output-drive path.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed GF180MCU D resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml","case_sha256":"b61b6d19f1ef1fd31d784c357c32d4e4ea511820d47c06927ea369a1df462362","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl","netlist_sha256":"59a4d962ade70da8bbdc21dffc81adf077c84baa2057b100deaed0c5f34e7dc2","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.amp_018_telescopic_cascode","in_core":false,"title":"Tail-Referenced Telescopic Cascode Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies differential inputs with an NMOS telescopic cascode and tail-referenced bias across three capacitive loads.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_018_telescopic_cascode","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Tail-Referenced Telescopic Cascode Amplifier Layout Task\n\n## Objective\n\nImplement `amp_018_telescopic_cascode` in gf180mcuD and submit self-contained GDS. Ten MOS devices form an NMOS-input telescopic cascode amplifier. Fixed upstream W/L/m are retained, including the single finger of XM5. The two ideal internal sources become external bias connections: VDD minus gate_pc is 1.143 V, and casc_n minus tail is 0.917 V. Exposing tail preserves the second source's relative bias instead of replacing it with an absolute ground-referenced voltage.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is the authoritative physical circuit. The same netlist is used for source calibration. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `vdd vout vinp vinn ibias vss gate_pc casc_n tail`. In order: Supply, output, positive input, negative input, reference-current input, return, PMOS cascode bias, NMOS cascode bias, and accessible tail node.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical GF180 3.3 V MOS and high-resistance poly models, statistical variation disabled. The substrate is not a distributed silicon resistance network.\n\nVDD = 3.3 V; VSS = 0 V; a 20 uA current source from VDD into ibias. VINP is 1.65 V DC with AC amplitude +0.5 V; VINN has DC output feedback through a 1 TH inductor and AC -0.5 V through a 1 F coupling capacitor. These ideal measurement elements are external apparatus. Output loads are 1, 3 and 5 pF. AC uses 100 points/decade from 1 Hz to 1 GHz and transfer V(vout)/(V(vinp)-V(vinn)).\n\n## Physical Requirements\n\nTop cell `amp_018_telescopic_cascode`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, GF180 variant-D DRC including antenna, with chip-level density and seal-ring closure outside scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 140 by 100 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. The declared bias gives about 15 dB gain; this is not a high-gain OTA qualification. Large-signal settling, noise, mismatch, other biases and PVT are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output/control voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `tail_v` | DC V(tail) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD; telescopic also includes both external voltage-bias sources | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(differential transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `unity_hz` | First falling 0 dB crossing | Hz | maximize / ratio | 0 … +∞ | — |\n| `phase_margin` | 180 degrees plus unwrapped transfer phase at unity crossing | deg | target / target | 0 … 180 | 180 |\n\nArea reference: **544.15 um2**. 10 expanded device instances; sum of device/contact envelopes 312.9250 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_db` | 0.270000000000 |\n| `unity_hz` | 0.225000000000 |\n| `phase_margin` | 0.225000000000 |\n| `bias_v` | 0.015000000000 |\n| `output_v` | 0.015000000000 |\n| `tail_v` | 0.015000000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml","case_sha256":"c5b3dac4ccb6d500333d24ac98fc8304ea009082629b2e93fb0fa11e31fdceaf","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice","netlist_sha256":"6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.amp_019_ti_ldo_error","in_core":false,"title":"Externally Biased TI-Architecture Error Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies a differential error signal using external bias, level shifting and series Miller compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_019_ti_ldo_error","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Externally Biased TI-Architecture Error Amplifier Layout Task\n\n## Objective\n\nImplement `amp_019_ti_ldo_error` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. All twelve MOS remain, including the externally driven NMOS reference diode, four sinks, NMOS differential pair, level-shift branch and PMOS output stage. RND connects na to nd; all 500 kohm remains. Rz/Cc remain in series between nb and vout. No servo is inside the DUT. Four parallel native resistors implement 470 ohm; 32 parallel MIM units implement 25 pF. Native 6 V PMOS lengths become 0.55 um; other dimensions and multiplicities retain the fixed GF180 binding.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vdd vout vinp vinn ibias vss`. `vinp` is the non-inverting input and `vinn` the inverting input, verified by follower response. The ideal 1 mA source from vdd to ibias is external and included in supply power. The feedback wire connects vout to vinn externally.\n\n## Operating Conditions\n\n3.3 V supply, 1 mA external bias; common-mode inputs 1.4, 1.6 and 1.8 V with 10 pF output load, plus 1.6 V with 1 pF. Direct follower in DC, AC and transient. AC input is 1 V and the reported gain is **closed-loop follower transfer**, never open-loop gain or loop margin. The input rises 10 mV at 20 us with 10 ns edges and returns after 40 us; simulate through 100 us with maximum 10 ns steps. Start at the DC operating point. No extra output resistance, solver shunt, feedback isolation L/C, forced initial conditions or stability claim. Windows are 10–20, 50–60 and 90–100 us.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `amp_019_ti_ldo_error`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[5, 0], [11, 17], [11, 39], [12, 0], [13, 17], [21, 0], [22, 0], [22, 4], [24, 0], [24, 5], [30, 0], [30, 4], [31, 0], [32, 0], [33, 0], [34, 0], [34, 3], [34, 4], [34, 5], [35, 0], [36, 0], [36, 3], [36, 4], [36, 5], [37, 0], [38, 0], [40, 0], [41, 0], [42, 0], [42, 3], [42, 4], [42, 5], [46, 0], [46, 3], [46, 4], [46, 5], [49, 0], [53, 0], [53, 3], [53, 4], [53, 5], [55, 0], [62, 0], [75, 0], [80, 5], [81, 0], [81, 3], [81, 4], [81, 5], [82, 0], [86, 17], [88, 17], [96, 1], [100, 5], [100, 7], [100, 8], [108, 5], [110, 5], [110, 11], [110, 12], [110, 13], [110, 14], [110, 15], [110, 16], [111, 5], [112, 1], [115, 5], [116, 5], [117, 5], [117, 10], [118, 5], [119, 5], [122, 5], [123, 5], [124, 5], [125, 5], [127, 5], [128, 17], [137, 5], [151, 5], [152, 5], [153, 51], [166, 5], [167, 5], [173, 5], [178, 0], [183, 0], [184, 0], [185, 0], [204, 0], [210, 0], [220, 0], [226, 0], [227, 0], [241, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. The GF180 model boundary retains physical poly substrate and MIM geometry.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 6 reflects the complete two-stage compensated feedback circuit. It does not claim verified open-loop gain, phase margin, noise, PVT or settling time. Late variation is a finite-window observation. The bias sink ratios are geometric ratios, not promises of saturated current mirrors.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | DC direct-follower output | bias / target; scale 3.3 | lower=0; upper=3.3 |\n| `power_w` | W | Total 3.3 V supply power including external 1 mA bias | supply / ratio; scale 1e-12 | lower=0 |\n| `gain_1hz` | 1 | Closed-loop follower magnitude at 1 Hz | response / target; scale 1 | Finite measurement |\n| `gain_1mhz` | 1 | Closed-loop follower magnitude at 1 MHz | response / target; scale 1 | Finite measurement |\n| `tracking_error_v` | V | Mean absolute tracking error, 20–100 us | response / ratio; scale 0.001 | lower=0 |\n| `ripple_v` | V | Finite-window peak-to-peak output, 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `step_response_v` | V | Mean output 50–60 us minus 10–20 us | unscored / functional | lower=0 |\n| `kcl_a` | A | External DC KCL residual | diagnostic; unscored | Producer validity guard; see below |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **63700 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (58 units, sum 31829.640000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **6**.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `tracking_error_v` | 0.360000000000 |\n| `ripple_v` | 0.225000000000 |\n| `gain_1hz` | 0.090000000000 |\n| `gain_1mhz` | 0.090000000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml","case_sha256":"c661845add976c09b3d919b6bbf1ef9fa5cf495d38e52b5c83235f092d83c4ca","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl","netlist_sha256":"3af8b547c72e7e34d0f919ace84d1eafff32f9c4b7f1b6a0e60ca6d45bab8fcc","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.amp_032_ti_ldo_error_selfbias","in_core":false,"title":"Self-Biased LDO Error Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies an error signal with a self-biased two-stage core, level-shifted mirror and Miller compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_032_ti_ldo_error_selfbias","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Biased LDO Error Amplifier Layout Task\n\n## Objective\n\nImplement `amp_032_ti_ldo_error_selfbias` as a GF180MCU D layout. Eleven MOS devices form the fixed upstream two-stage amplifier, with a level-shifted PMOS mirror, its 500 kohm gate-rail tie, diode-connected self-bias and series Miller compensation. The direct common-source output stage is the revision present in the pinned netlist; the retired stacked stage is not used.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority. `materials/circuit.spice`\ncontains the corresponding native simulator wrappers; `materials/testbench.spice`\ndefines all measurements. Ordered ports: `vdd vout vinp vinn vss`.\n`vdd/vss` are supply/return, `vinp/vinn` are differential inputs, and `vout` is the output.\nNo external bias current is required. Preserve connectivity and total device dimensions;\nparallel equivalent fingers are permitted. Do not substitute a different amplifier.\n\n## Operating Conditions\n\nTypical native GF180 6 V MOS models, 3.3 V supply, 27 C, statistics disabled.\nInput common mode is 1.6 V. Both 1 pF and 10 pF output loads are evaluated.\nDC uses unity feedback. AC uses a 1 TH feedback inductor and 1 F input shunt\nfrom 1 Hz to 1 GHz, 100 points/decade. Transient replaces these fixture elements\nwith 1 pH and 1 aF: the input rises 10 mV at 1 us and falls at 3 us, each in\n10 ns. The simulation ends at 5 us, with a 1 ns requested step.\nThese ideal fixture elements are external test apparatus, outside the DUT.\n\n## Physical Requirements\n\nGDS database unit 0.001 um; maximum 10 MiB; top cell `amp_032_ti_ldo_error_selfbias`.\nNative standalone DRC includes geometry, connectivity, manufacturing grid,\ndummy fill and antenna rules; chip density and seal-ring closure are excluded.\nNative LVS must match devices, parameters and every named port. All device,\nwell, implant, contact, passive-marker and routing layers listed in the runtime\noutline form the functional bounding rectangle; text annotations are excluded.\nMaximum outline is 5000 by 1000 um. Labels belong on native Metal1 text.\n\nThe 6 V minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS.\nUpstream dimensions are rounded to 5 nm, with only subminimum lengths raised.\nPhysical passives use 1 kohm/square poly and MIM-B, 2 fF/um2, between M4/M5.\nLong resistors are series segmented; capacitors are parallel tiled. Nominal\nvalues are implemented by geometry; source and candidate use the same native\nprocess models. MOS diffusion areas/perimeters and interconnect parasitics are\ncandidate-derived. Magic extracts nominal coupling capacitance and distributed\nresistance using zero omission thresholds. Ideal well/substrate connections\nexclude distributed substrate noise; no inductance, RF/EM or statistical claim\nis made. Finite source and candidate observations must be available. Every declared\noperating point must satisfy its functional checks; incomplete evaluation cannot\nestablish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | bias | target |\n| `power_w` | DC supply power: -VDD*I(VDD) | W | supply | ratio |\n| `gain_db` | Open-loop magnitude at 10 Hz in dB | dB | response | db20 |\n| `unity_hz` | First falling unity-gain crossing | Hz | response | ratio |\n| `phase_margin` | 180 degrees plus unwrapped phase at unity crossing | deg | response | target |\n| `tracking_error_v` | Mean absolute unity-buffer tracking error over 1–5 us | V | response | ratio |\n| `step_response_v` | Mean output at 2–3 us minus mean output at 4–5 us; nonnegative sign-domain check (zero is allowed) | V | functional | unscored |\n\nDC output must remain between the rails, power and absolute tracking error must\nbe nonnegative, and the signed output-step observation must be nonnegative (zero is allowed). These\nbounds express physical domains and buffer function. Every required measurement\nmust be finite; failed or missing measurements are evaluation errors, not poor\nperformance. No upstream data-sheet target is an acceptance gate. Phase margin\nis measured and continuously compared, without importing an upstream threshold.\n\nEach quality observation is paired with an independent source simulation using\nthe identical deck, load, supply, temperature and models. `target` uses scale\n3.3 V for output and 180 degrees for phase; ratio floors are 1 pW for power\nand 1 mV for tracking error. These are normalization units, not tolerances.\n\n\nArea target: **19112.51 um2**. Device/contact envelopes sum to 12143.285500 um2,\nusing `(W+2)*(L+2)` per expanded MOS, resistor segment and capacitor tile\nin micrometers. The estimate adds 50% routing plus a 2 um outer margin:\n`ceil(100*(1.5*envelope_sum+8*sqrt(envelope_sum)+16))/100`.\nThis engineering anchor is independent of the witness footprint and is not a\nfoundry minimum. Coefficient **6** reflects a complete compensated two-stage\nloop with self-bias and load-dependent transient response.\n\n\n### Score weights\n\nSelf-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `tracking_error_v` | 0.360000000000 |\n| `phase_margin` | 0.225000000000 |\n| `gain_db` | 0.090000000000 |\n| `unity_hz` | 0.090000000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json` for the frozen task, reviewed PDK and harness.\nKLayout checks physical validity, Magic extracts the submitted layout and\nngspice performs measurements. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml","case_sha256":"8f8de97eaf47a1393e176354f75fd7929374b58a93bbee14337d8870179d55e7","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl","netlist_sha256":"9e9cb685378e09c43bf827a69c0189e83fb9ef47b6d96655c466e1bfa411b7d1","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.amp_033_ti_ldo_ref_selfbias","in_core":false,"title":"Self-Biased LDO Reference Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Buffers a reference through a self-biased two-stage Miller amplifier under external unity feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_033_ti_ldo_ref_selfbias","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Biased LDO Reference Amplifier Layout Task\n\n## Objective\n\nImplement `amp_033_ti_ldo_ref_selfbias` as a GF180MCU D layout. Nine MOS devices form the fixed upstream two-stage Miller amplifier, with a matched PMOS mirror and diode-connected self-bias. External unity feedback tests the reference-buffer function; no ideal internal amplifier or bias servo is inserted.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority. `materials/circuit.spice`\ncontains the corresponding native simulator wrappers; `materials/testbench.spice`\ndefines all measurements. Ordered ports: `vdd vout vinp vinn vss`.\n`vdd/vss` are supply/return, `vinp/vinn` are differential inputs, and `vout` is the output.\nNo external bias current is required. Preserve connectivity and total device dimensions;\nparallel equivalent fingers are permitted. Do not substitute a different amplifier.\n\n## Operating Conditions\n\nTypical native GF180 6 V MOS models, 3.3 V supply, 27 C, statistics disabled.\nInput common mode is 0.8 V. Both 1 pF and 10 pF output loads are evaluated.\nDC uses unity feedback. AC uses a 1 TH feedback inductor and 1 F input shunt\nfrom 1 Hz to 1 GHz, 100 points/decade. Transient replaces these fixture elements\nwith 1 pH and 1 aF: the input rises 10 mV at 1 us and falls at 3 us, each in\n10 ns. The simulation ends at 5 us, with a 1 ns requested step.\nThese ideal fixture elements are external test apparatus, outside the DUT.\n\n## Physical Requirements\n\nGDS database unit 0.001 um; maximum 10 MiB; top cell `amp_033_ti_ldo_ref_selfbias`.\nNative standalone DRC includes geometry, connectivity, manufacturing grid,\ndummy fill and antenna rules; chip density and seal-ring closure are excluded.\nNative LVS must match devices, parameters and every named port. All device,\nwell, implant, contact, passive-marker and routing layers listed in the runtime\noutline form the functional bounding rectangle; text annotations are excluded.\nMaximum outline is 5000 by 1000 um. Labels belong on native Metal1 text.\n\nThe 6 V minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS.\nUpstream dimensions are rounded to 5 nm, with only subminimum lengths raised.\nPhysical passives use 1 kohm/square poly and MIM-B, 2 fF/um2, between M4/M5.\nLong resistors are series segmented; capacitors are parallel tiled. Nominal\nvalues are implemented by geometry; source and candidate use the same native\nprocess models. MOS diffusion areas/perimeters and interconnect parasitics are\ncandidate-derived. Magic extracts nominal coupling capacitance and distributed\nresistance using zero omission thresholds. Ideal well/substrate connections\nexclude distributed substrate noise; no inductance, RF/EM or statistical claim\nis made. Finite source and candidate observations must be available. Every declared\noperating point must satisfy its functional checks; incomplete evaluation cannot\nestablish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | bias | target |\n| `power_w` | DC supply power: -VDD*I(VDD) | W | supply | ratio |\n| `gain_db` | Open-loop magnitude at 10 Hz in dB | dB | response | db20 |\n| `unity_hz` | First falling unity-gain crossing | Hz | response | ratio |\n| `phase_margin` | 180 degrees plus unwrapped phase at unity crossing | deg | response | target |\n| `tracking_error_v` | Mean absolute unity-buffer tracking error over 1–5 us | V | response | ratio |\n| `step_response_v` | Mean output at 2–3 us minus mean output at 4–5 us; nonnegative sign-domain check (zero is allowed) | V | functional | unscored |\n\nDC output must remain between the rails, power and absolute tracking error must\nbe nonnegative, and the signed output-step observation must be nonnegative (zero is allowed). These\nbounds express physical domains and buffer function. Every required measurement\nmust be finite; failed or missing measurements are evaluation errors, not poor\nperformance. No upstream data-sheet target is an acceptance gate. Phase margin\nis measured and continuously compared, without importing an upstream threshold.\n\nEach quality observation is paired with an independent source simulation using\nthe identical deck, load, supply, temperature and models. `target` uses scale\n3.3 V for output and 180 degrees for phase; ratio floors are 1 pW for power\nand 1 mV for tracking error. These are normalization units, not tolerances.\n\n\nArea target: **6223.21 um2**. Device/contact envelopes sum to 3808.978200 um2,\nusing `(W+2)*(L+2)` per expanded MOS, resistor segment and capacitor tile\nin micrometers. The estimate adds 50% routing plus a 2 um outer margin:\n`ceil(100*(1.5*envelope_sum+8*sqrt(envelope_sum)+16))/100`.\nThis engineering anchor is independent of the witness footprint and is not a\nfoundry minimum. Coefficient **6** reflects a complete compensated two-stage\nloop with self-bias and load-dependent transient response.\n\n\n### Score weights\n\nSelf-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `tracking_error_v` | 0.360000000000 |\n| `phase_margin` | 0.225000000000 |\n| `gain_db` | 0.090000000000 |\n| `unity_hz` | 0.090000000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json` for the frozen task, reviewed PDK and harness.\nKLayout checks physical validity, Magic extracts the submitted layout and\nngspice performs measurements. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml","case_sha256":"b94fe14867a4a6bf3d550499f65139d32a5ef878d957ed09c0b6f2a7cef169cf","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl","netlist_sha256":"9b965341e7687a517833fa3ffa030c708a3bcb2622a922f5edb74e959bbff646","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.cmfb_003_5t_nmos_input","in_core":false,"title":"Segmented-Resistor NMOS Common-Mode Controller","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Controls common-mode voltage using an NMOS-input core and segmented resistors.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_003_5t_nmos_input","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Segmented-Resistor NMOS Common-Mode Controller Layout Task\n\n## Objective\n\nImplement `cmfb_003_5t_nmos_input` in gf180mcuD and submit self-contained GDS. Seven MOS devices form an NMOS-input common-mode error amplifier and self-bias network. Each ideal 5 Mohm sense arm is implemented as twenty series GF180 ppolyf_u_1k segments, each 2 um wide and 500 um long: 5,000 squares per arm. The segmentation, substrate terminals and intermediate nodes are part of the maintained circuit. The independent witness uses compact rows connected by metal; it retains both complete resistance chains.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is the authoritative physical circuit. The same netlist is used for source calibration. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `vinp vinn vcmfb vref vdd vss`. In order: Positive sensed output, negative sensed output, control output, common-mode reference, supply, and return.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical GF180 3.3 V MOS and high-resistance poly models, statistical variation disabled. The substrate is not a distributed silicon resistance network.\n\nVDD = 3.3 V; VSS = 0 V; VREF = 1.65 V. The external first-order inverting plant has drive = 3.3 V - V(vcmfb), followed by 100 kohm and 100 nF to common mode. V(vinp/vinn) = plant output + disturbance +/- d, where d = 0, 0.1 and 0.2 V in separate conditions. Disturbance is 0 through 10 ms, +0.1 V at 10.01 ms through 30 ms, -0.1 V at 30.01 ms through 50 ms, and 0 at 50.01 ms through 70 ms. A 10 pF external capacitor loads vcmfb. Transient output/max step is 10 us. This plant is test apparatus, not an internal ideal servo or a claimed transistor amplifier. Recovery windows are 25–29 ms and 45–49 ms for the positive/negative disturbances; error is measured at the average sensed inputs against VREF. Controller power excludes the external plant.\n\n## Physical Requirements\n\nTop cell `cmfb_003_5t_nmos_input`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, GF180 variant-D DRC including antenna, with chip-level density and seal-ring closure outside scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 1100 by 280 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. Qualification covers recovery with this specified external plant, not stability with arbitrary amplifiers. The long physical sense chains retain candidate-derived parasitics. Startup, mismatch, noise, PVT and a complete differential amplifier are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output/control voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `error_v` | Absolute DC sensed common-mode minus VREF | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `recovery_up_v` | Maximum absolute recovered error over the upward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `recovery_down_v` | Maximum absolute recovered error over the downward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `recovery_zero_v` | Maximum absolute sensed common-mode minus VREF over 65–69 ms | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `peak_error_v` | Maximum absolute sensed common-mode minus VREF over 10–70 ms | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the complete transient | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **122380.96 um2**. 47 expanded device instances; sum of device/contact envelopes 80826.5000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCommon-mode sensing/controllers: recovery and error 62.3%; output bias 6.92%; power 20.8%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `error_v` | 0.124615384617 |\n| `peak_error_v` | 0.124615384615 |\n| `recovery_down_v` | 0.124615384615 |\n| `recovery_up_v` | 0.124615384615 |\n| `recovery_zero_v` | 0.124615384615 |\n| `output_v` | 0.069230769231 |\n| `mean_power_w` | 0.103846153846 |\n| `power_w` | 0.103846153846 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml","case_sha256":"ac03814e40b31b14631ab6f61e76846a0280f9943c6a377718379926b3d500b8","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice","netlist_sha256":"ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.cmp_001_hyst_diffpair","in_core":false,"title":"Resistive-Feedback Hysteretic Comparator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Produces distinct rising and falling switching thresholds through resistive hysteresis.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_001_hyst_diffpair","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Resistive-Feedback Hysteretic Comparator Layout Task\n\n## Objective\n\nImplement the fixed `cmp_001_hyst_diffpair` circuit in GF180MCU D and submit self-contained GDS.\nA differential input stage, resistive positive feedback and three output inverters form a hysteretic comparator. Twelve MOS entries expand to 28 physical instances. The physical ppolyf_u_1k resistors are width 2 um: two 600 um feedback devices (300 squares) and one 12 um tail device (6 squares). MOS sizes and multiplicities are retained; ideal resistors become substrate-connected process devices.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd vout vinp vinn vss`.\nIn order, these are: Supply, digital output, swept positive input, fixed negative input, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVDD = 3.3 V, VSS = 0 V, VINN = 1.65 V. VINP stays at 1.45 V through 0.1 ms, ramps to 1.85 V at 1.1 ms, holds through 1.2 ms, ramps back to 1.45 V at 2.2 ms, then holds through 2.3 ms. Each ramp magnitude is 0.4 V/ms. Evaluate external loads of 1, 5 and 10 pF separately with a 0.2 us transient output step. The transient starts from its DC operating point.\n\n## Physical Requirements\n\nSubmit top cell `cmp_001_hyst_diffpair` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 1300 by 200 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThresholds include this finite ramp rate and output load. Offset is intentional and is not zero-centered about VINN. Metastability, fast decision delay, startup, noise, statistical offset, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `rising_input` | Interpolated VINP at the first rising VOUT = 1.65 V crossing | V | target / target | 0 … 3.3 | 3.3 |\n| `falling_input` | Interpolated VINP at the first falling VOUT = 1.65 V crossing | V | target / target | 0 … 3.3 | 3.3 |\n| `hysteresis_v` | Rising-input threshold minus falling-input threshold | V | target / target | 0 … 3.3 | 3.3 |\n| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the full 0–2.3 ms transient | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `low_v` | Maximum VOUT over 0.02–0.08 ms | V | functional check | 0 … 0.1 | — |\n| `high_v` | Minimum VOUT over 1.12–1.18 ms | V | functional check | 3.2 … 3.31 | — |\n\nArea reference: **8386.58 um2**. 31 expanded device instances; sum of device/contact envelopes 5392.5600 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nHysteretic comparator: switching thresholds 49.5%; hysteresis 27%; supply power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `falling_input` | 0.247500000000 |\n| `rising_input` | 0.247500000000 |\n| `hysteresis_v` | 0.270000000000 |\n| `mean_power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml","case_sha256":"bc8505f1bb608ddd79d74f941a65dc7fbf782cfd0ae168173a1b6a8f89d65a84","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice","netlist_sha256":"cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.cmp_002_strongarm","in_core":true,"title":"StrongARM Dynamic Comparator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Makes clocked differential decisions with a StrongARM regenerative latch.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_002_strongarm","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# StrongARM Dynamic Comparator Layout Task\n\n## Objective\n\nImplement `cmp_002_strongarm` as a GF180MCU D layout. Fifteen upstream MOS instances implement the clocked StrongARM latch: differential input pair, clocked tail, cross-coupled regenerative devices, four precharge devices and two output inverters. The input pair multiplicities expand the physical circuit to seventeen devices. The maintained GF180 3.3 V binding uses the fixed sizing defaults and authored ties from the pinned accession.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice`\ncontains matching native simulator wrappers. `materials/testbench.spice` defines\nall measurements. Ordered ports: `vdd voutp voutn vinp vinn clk vss`.\n\n`vdd/vss`: supply and return; `vinp/vinn`: differential inputs; `clk`: evaluate high, precharge low; `voutp/voutn`: buffered differential outputs. Positive input difference produces positive output difference. Supply, clock, input drivers and output loads are external apparatus. No offset-trim variant or proprietary process deck is included.\n\n## Operating Conditions\n\nTypical GF180 3.3 V MOS models at 3.3 V supply and 27 C, statistics disabled. Differential input is +20 or -20 mV at common modes 1.2 and 1.65 V, all four combinations. Each output has a 50 fF load. The 50 MHz clock first rises at 10 ns, uses 100 ps edges and 10 ns pulse width. Simulate to 100 ns at 10 ps requested steps; timing uses the fifth evaluation edge near 90 ns.\n\n## Physical Requirements\n\nGDS database unit 0.001 um, maximum 10 MiB, top cell `cmp_002_strongarm`.\nNative standalone DRC covers geometry, connectivity, manufacturing grid, dummy\nfill and antenna; chip-level density and seal-ring closure are excluded.\nLVS must match all devices, parameters and named ports. Metal1 labels identify\nports. The functional bounding rectangle includes the device, well, implant,\ncontact, passive and complete routing layers enumerated in the runtime outline;\ntext annotations are excluded. Maximum outline is 5000 by 1000 um.\n\nKeep the 3.3 V models, 0.28 um channel length, fixed widths and multiplicities. Parallel equivalent fingers are permitted. All MOS dimensions lie on the native 5 nm construction grid. Body/well connections are explicit, with native guard-ring/tap geometry. The IHP binding has the same topology but different process sizing; it is not mixed into this GF180 task.\n\nCandidate-derived native Magic coupling capacitance and distributed wire\nresistance feed post-layout simulation, with zero omission thresholds.\nPhysical MOS diffusion areas/perimeters come from the layout. Substrate/well\nconnections are ideal: distributed substrate resistance/noise and inductance\nare not represented. Four nominal input-polarity/common-mode combinations, reset, decision delay/slew and average supply power. Coefficient 6 reflects regenerative decisions with clocked reset and buffered loads. Offset distribution, metastability statistics, noise, PVT and RF/EM are outside this declared scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `delay_s` | Clock 1.65 V crossing to signed output difference 1.65 V, fifth rising edge | s | response | ratio |\n| `slew_s` | Signed differential output rise from 0.33 to 2.97 V, fifth decision | s | response | ratio |\n| `power_w` | Mean supply power over 20–100 ns | W | supply | ratio |\n| `decision_v` | Input-polarity-adjusted output difference at 99 ns | V | bias | target |\n| `reset_p_v` | Positive output at 89 ns in precharge | V | functional | unscored |\n| `reset_n_v` | Negative output at 89 ns in precharge | V | functional | unscored |\n\nSigned decision must be 1.65–3.3 V; both reset outputs must be 0–1.65 V. Half-supply separates the required resolved/reset logic states, independent of any upstream speed target. Delay, slew and mean supply power must be nonnegative. Timing has no hard upper bound beyond the declared observation window; a missing crossing is an invalid measurement.\nEvery condition must complete; missing, nonfinite or wrong-unit observations\nproduce an evaluation error. Upstream advertised performance is not a\nqualification requirement.\n\nScored observations pair with independent source jobs using the identical\nstimuli, parameters, models and backend. Target scales are 3.3 V; ratio floors\nuse 1 pW for power. These are normalization units, not allowed degradation.\nDelay/slew ratios have no floor.\n\nArea anchor **490.86 um2** uses a 234.840000 um2 sum of expanded\n`(W+2)*(L+2)` device/contact envelopes, a 50% routing allowance and 2 um outer\nmargin: `ceil(100*(1.5*sum+8*sqrt(sum)+16))/100`. It is independent of witness\narea and is an engineering estimate, not a foundry minimum. Coefficient **6**\nis independent of this score.\n\n\n### Score weights\n\nClocked comparators: decision delay 61.4%; output transition 8.18%; decision amplitude 4.09%; supply power 16.4%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `delay_s` | 0.613636363637 |\n| `slew_s` | 0.081818181818 |\n| `decision_v` | 0.040909090909 |\n| `power_w` | 0.163636363636 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRead `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. KLayout performs physical checks, Magic extracts the\ncandidate, and ngspice measures it. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit using\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml","case_sha256":"2a2e079b46db026858622975af955aefaf7f3e134282079fc257261a30befb62","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl","netlist_sha256":"5b80e3a40ab19415481d51b8e6b4e4bcf45c4517ccc5071aa1b342038c94e14c","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.dp_001_resistive_load","in_core":false,"title":"Resistively Loaded Differential Pair","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Produces differential gain with resistive loads and a fixed input pair.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/dp_001_resistive_load","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Resistively Loaded Differential Pair Layout Task\n\n## Objective\n\nImplement the fixed `dp_001_resistive_load` circuit in GF180MCU D and submit self-contained GDS.\nFour NMOS devices form a differential input pair and tail-current mirror. Two physical GF180 ppolyf_u_1k loads each have width 2 um and length 44 um (22 squares, nominally 22 kohm). MOS dimensions and the resistor ratio follow the fixed binding; the ideal source resistors become process devices with substrate terminals at VSS.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd voutp voutn vinp vinn ibias vss`.\nIn order, these are: Supply, output on the vinp branch, output on the vinn branch, positive input, negative input, NMOS reference-current input, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVDD = 3.3 V, VSS = 0 V; 20 uA from VDD into ibias; input common mode = 1.2, 1.65 and 2.1 V; external 1 pF on each output. The input differential signal is split +0.5/-0.5 around common mode. AC differential amplitude is 1 V. DC transfer sweeps differential input from -10.1 to +10.1 mV in 0.1 mV increments; requirements use only -10 to +10 mV. Output differential voltage is V(voutn)-V(voutp).\n\nAC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is\nV(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp)\nfor unit differential excitation; the OTA transfer is defined above.\n\n## Physical Requirements\n\nSubmit top cell `dp_001_resistive_load` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 160 by 160 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThe output has a high common-mode level; it is not a rail-to-rail amplifier. Transient settling, mismatch, noise, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage; average of both outputs for the differential pair | V | target / target | 0 … 3.3 | 3.3 |\n| `imbalance_v` | Absolute DC difference between the two outputs | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — |\n| `linearity_v` | Maximum absolute differential-output deviation from the line joining the -10/+10 mV samples | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `slope` | Differential-output endpoint difference divided by 20 mV | V/V | target / target | −∞ … +∞ | 5 |\n\nArea reference: **925.98 um2**. 6 expanded device instances; sum of device/contact envelopes 552.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 38.6%; bandwidth 11.6%; balance and linearity 19.3%; operating points 3.86%; power 11.6%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `gain_db` | 0.193181818182 |\n| `slope` | 0.193181818182 |\n| `bandwidth_hz` | 0.115909090909 |\n| `imbalance_v` | 0.096590909091 |\n| `linearity_v` | 0.096590909091 |\n| `bias_v` | 0.019318181818 |\n| `output_v` | 0.019318181818 |\n| `power_w` | 0.115909090909 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml","case_sha256":"3731b97781f49826538972a11873f565a6888789bb4c0710206cd90234436ec7","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice","netlist_sha256":"15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.gs_001_cascode_cs","in_core":false,"title":"Self-Biased Cascode Common-Source Gain Stage","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Provides voltage gain through a self-biased cascode common-source stage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/gs_001_cascode_cs","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Biased Cascode Common-Source Gain Stage Layout Task\n\n## Objective\n\nImplement the fixed `gs_001_cascode_cs` circuit in GF180MCU D and submit self-contained GDS.\nNine MOS devices form a cascode common-source stage with PMOS and NMOS bias ladders. An external 20 uA sink biases the PMOS ladder. Total widths, lengths and multiplicities follow the fixed GF180 binding. Physical body contacts and an independently constructed reference complete the circuit.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd vout vin ibias vss`.\nIn order, these are: Supply, output, signal input, PMOS reference-current sink, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVSS = 0 V; VDD = 2.7, 3.0 and 3.3 V; external 20 uA sink from ibias to VSS; external 1 pF output load. A 1 TH external inductor connects output to input for the DC trip-point solve. A 1 F external coupling capacitor injects a unit AC input through acin while isolating the DC fixture. This measures open-loop small-signal gain at each self-biased trip point; it does not prescribe a fixed DC input voltage.\n\nAC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is\nV(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp)\nfor unit differential excitation; the OTA transfer is defined above.\n\n## Physical Requirements\n\nSubmit top cell `gs_001_cascode_cs` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 220 by 120 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nTransient settling, fixed-input bias robustness, noise, mismatch, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — |\n\nArea reference: **394.4 um2**. 9 expanded device instances; sum of device/contact envelopes 220.6500 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 50%; bandwidth 15%; operating points 5%; power 15%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `gain_db` | 0.500000000000 |\n| `bandwidth_hz` | 0.150000000000 |\n| `bias_v` | 0.025000000000 |\n| `output_v` | 0.025000000000 |\n| `power_w` | 0.150000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml","case_sha256":"bab2233575478f0fcbebc4d4993224829c772207aa1cbba15eb1dcdb6d6d31d6","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice","netlist_sha256":"59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.ldo_002_analoggym_folded_cascode","in_core":false,"title":"Folded-Cascode LDO","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_002_analoggym_folded_cascode","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Folded-Cascode LDO Layout Task\n\n## Objective\n\nImplement `ldo_002_analoggym_folded_cascode` as a GDS layout preserving the complete declared circuit. Nine-MOS folded-cascode error amplifier and a PMOS pass array, with direct output feedback, series RZ/CC and the physical minimum-load bleed. The fixed GF180 6 V binding expands to 259 MOS, three 2 fF/um2 MIM units, one nulling resistor and two series bleed segments. VB1, VB2 and VREF remain external sources; the original 0 V VLP measurement marker becomes a wire.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/startup.spice`: startup observations.\n- `materials/regulation.spice`: regulation observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vdd vout vss vb1 vb2 vref`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\nNominal supply 2.0 V, external reference 1.8 V, VB1=1.0 V and VB2=0.025 V; 27 C, typical GF180 models with statistical variation disabled. Native 6 V DRC requires NMOS L>=0.70 um and PMOS L>=0.55 um; only undersized lengths are increased to those physical minima. All default widths and the 250-fold 10 um pass-device multiplier are retained. R_bleed is 100 kohm inside the physical DUT and consumes Vout^2/R power; external 1/2 mA load currents are additional, not replacements. CC=2 pF and RZ=3 kohm retain their original connections. External output capacitance is 1 nF with 0.1 ohm series ESR. Evaluate no disturbance, 1-to-2 mA load pulse, and +0.1 V input pulse, plus independent DC points at nominal+0.1 V/1 mA and nominal/2 mA. Pulses start at 100 us, have 1 us edges and 100 us high width; restoration finishes at 202 us. Observe 0–400 us with 10 ns maximum step; pre-step/high/recovery windows are 80–100/180–200/380–400 us. Supply rejection is measured at 1 kHz from a 1 V AC supply input (100 samples/decade, 1 Hz–100 MHz). Ascending DC sweeps cover nominal supply to nominal+0.1 V in 10 mV increments at 1 mA and 1–2 mA load in 0.1 mA increments at nominal supply; adjustment metrics are absolute endpoint slopes. These are finite ranges, not dropout measurements. Startup ramps VDD from zero to nominal in 10 us with fixed external references and a resistive 1 mA nominal load (target voltage/1 mA); it uses the ordinary initial DC solution, no UIC or forced initial output, and observes through 400 us. Startup extrema and late-window output/ripple are diagnostics. No dropout, loop gain or phase margin is claimed. Source and candidate use identical decks and parameters; no numerical shunt is used.\n\n## Physical Requirements\n\nGF180MCU D native standalone-block FEOL/BEOL, connectivity, grid, dummy and antenna rules; chip density/seal-ring rules are outside this block boundary. Named-port LVS and candidate-derived distributed Magic RC are required. Functional area includes active/poly, passives and all routing metal/vias. Capacitor substrate and resistor terminal models follow the frozen PDK profile. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 20000 by 2000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_v | V | DC output | bias; target (scale 1.8) |\n| regulation_error_v | V | Absolute DC setpoint error | response; ratio (scale 0.001) |\n| power_w | W | Total input rail DC power, including physical bleed/divider and external current bias | supply; ratio (scale 1e-12) |\n| psrr_db | dB | Input supply rejection at 1 kHz | response; db20 |\n| quiet_ripple_v | V | Peak-to-peak pre-perturbation output 80–100 us | response; ratio (scale 0.001) |\n| recovery_ripple_v | V | Peak-to-peak recovered output 380–400 us | response; ratio (scale 0.001) |\n| excursion_v | V | Full output range 100–400 us | response; ratio (scale 0.001) |\n| late_error_v | V | Mean absolute setpoint error 380–400 us | response; ratio (scale 0.001) |\n| mean_power_w | W | Mean input rail power 0–400 us | supply; ratio (scale 1e-12) |\n| quiet_v | V | Finite-window quiet_v | diagnostic; unscored |\n| high_v | V | Finite-window high_v | diagnostic; unscored |\n| recovery_v | V | Finite-window recovery_v | diagnostic; unscored |\n| startup_final_v | V | 10 us input ramp with resistive load: startup_final_v | diagnostic; unscored |\n| startup_ripple_v | V | 10 us input ramp with resistive load: startup_ripple_v | diagnostic; unscored |\n| startup_min_v | V | 10 us input ramp with resistive load: startup_min_v | diagnostic; unscored |\n| startup_max_v | V | 10 us input ramp with resistive load: startup_max_v | diagnostic; unscored |\n| line_reg_v_per_v | V/V | Absolute ascending supply-sweep endpoint slope, nominal to nominal + 0.1 V, 1 mA load | response; ratio (scale 0.001) |\n| load_reg_ohm | ohm | Absolute ascending load-sweep endpoint slope, 1 to 2 mA, nominal supply | response; ratio (scale 1) |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 29211.12 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. For ordinary GF180 resistors this envelope conservatively uses the sheet-only length before contact correction; the explicit parallel 1-ohm bank uses its native dimensions. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 7 covers regulation, frequency response and recovery across loads. The provenance chain distinguishes the Apache-2.0 sky130_ldo_rl netlist from the BSD-3-Clause AnalogGym sizing/testbench; the actual circuit is the pinned MacAnalog GF180 binding, not another reference implementation.\n\n\n### Score weights\n\nGF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_reg_v_per_v` | 0.075000000000 |\n| `load_reg_ohm` | 0.075000000000 |\n| `output_v` | 0.075000000000 |\n| `regulation_error_v` | 0.075000000000 |\n| `excursion_v` | 0.149999999999 |\n| `late_error_v` | 0.150000000000 |\n| `psrr_db` | 0.066666666667 |\n| `quiet_ripple_v` | 0.066666666667 |\n| `recovery_ripple_v` | 0.066666666667 |\n| `mean_power_w` | 0.050000000000 |\n| `power_w` | 0.050000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `ldo_002_analoggym_folded_cascode`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml","case_sha256":"119e94e34c41cc595db48ab20b807dec4a9cbc7d055d5c285617970609dd0bd4","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl","netlist_sha256":"7463ac0a1cc09ec1f522693a4e4e03b348a693a698cdfb71cade504ca6ff4681","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.ldo_003_analoggym_simple","in_core":false,"title":"Simple Unity-Feedback LDO","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_003_analoggym_simple","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Simple Unity-Feedback LDO Layout Task\n\n## Objective\n\nImplement `ldo_003_analoggym_simple` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. A five-transistor NMOS-input error amplifier drives the PMOS pass device, with direct output feedback, the complete 3 kohm/1 pF series compensation and physical 100 kohm bleed. The pass transistor expands to 360 parallel units; the complete core has 365 MOS. GF180 6 V NMOS lengths obey the native 0.70 um minimum and PMOS lengths the 0.55 um minimum. The external bias remains 1.2 V and reference 1.8 V from the fixed binding.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/startup.spice`, `materials/sweep.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vdd vout vss vb vref`. VB and VREF are external ideal sources; the upstream zero-volt VLP feedback marker becomes a physical wire. The bleed is inside the DUT and counted in its input power, in addition to the explicitly stated fixture load. At 1.8 V it draws approximately 18 uA. The independent source baseline contains the same physical bleed, compensation and process adaptations.\n\n## Operating Conditions\n\nTT, 27 C. Main runs use 2.0 V supply and 1 mA external load, independently applying either no disturbance, a +0.1 V line step, or a +4 mA load step. A separate quiet condition uses 2.1 V/5 mA. Edges are 100 ns, disturbances start at 20 us and last 40 us. Output load is 50 pF behind 0.1 ohm ESR. Transient maximum step 2 ns, duration 100 us, initialized from DC. Upward DC supply sweep: 1.9–2.2 V in 5 mV steps at 1 mA; report the 2.0–2.1 V endpoint slope. Upward load sweep: 1–5 mA in 0.1 mA steps at 2.0 V. PSRR is -20 log10 of output response to a unit AC supply at 1 kHz, reference/bias AC grounded. Startup separately ramps supply/reference/bias together from zero over 10 us into a 1.8 kohm external resistive load; no negative-voltage ideal current load is applied during startup. No solver shunt, isolation L/C or imposed output state.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `ldo_003_analoggym_simple`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 20000/2000 um. The complete functional layer set is `[[5, 0], [11, 17], [11, 39], [12, 0], [13, 17], [21, 0], [22, 0], [22, 4], [24, 0], [24, 5], [30, 0], [30, 4], [31, 0], [32, 0], [33, 0], [34, 0], [34, 3], [34, 4], [34, 5], [35, 0], [36, 0], [36, 3], [36, 4], [36, 5], [37, 0], [38, 0], [40, 0], [41, 0], [42, 0], [42, 3], [42, 4], [42, 5], [46, 0], [46, 3], [46, 4], [46, 5], [49, 0], [53, 0], [53, 3], [53, 4], [53, 5], [55, 0], [62, 0], [75, 0], [80, 5], [81, 0], [81, 3], [81, 4], [81, 5], [82, 0], [86, 17], [88, 17], [96, 1], [100, 5], [100, 7], [100, 8], [108, 5], [110, 5], [110, 11], [110, 12], [110, 13], [110, 14], [110, 15], [110, 16], [111, 5], [112, 1], [115, 5], [116, 5], [117, 5], [117, 10], [118, 5], [119, 5], [122, 5], [123, 5], [124, 5], [125, 5], [127, 5], [128, 17], [137, 5], [151, 5], [152, 5], [153, 51], [166, 5], [167, 5], [173, 5], [178, 0], [183, 0], [184, 0], [185, 0], [204, 0], [210, 0], [220, 0], [226, 0], [227, 0], [241, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. The GF180 model boundary retains physical poly substrate and MIM geometry.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 7 reflects compensated regulation, line/load recovery and coordinated startup. No dropout number, loop margin, unlimited load range, PVT or product specification is claimed. Regulation slopes describe the declared finite intervals. Final error/ripple describe 90–100 us, not a proof of asymptotic settling. Input power includes the bleed, delivered load and bias/reference source contributions.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | DC output | bias / target; scale 1.8 | lower=0; upper=2.1 |\n| `power_w` | W | DC rail/reference/bias input power including bleed | supply / ratio; scale 1e-12 | lower=0 |\n| `regulation_error_v` | V | Absolute DC output error relative to 1.8 V | response / ratio; scale 0.001 | lower=0 |\n| `psrr_db` | dB | Supply rejection at 1 kHz | response / db20 | Finite measurement |\n| `quiet_ripple_v` | V | Output variation 10–20 us | response / ratio; scale 0.001 | lower=0 |\n| `recovery_ripple_v` | V | Output variation 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `excursion_v` | V | Output excursion 20–100 us | response / ratio; scale 0.001 | lower=0 |\n| `late_error_v` | V | Mean absolute output error 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `kcl_a` | A | External DC KCL residual | diagnostic; unscored | Producer validity guard; see below |\n| `startup_error_v` | V | Mean final startup error, 90–100 us, 10 us coordinated source ramps | response / ratio; scale 0.001 | lower=0 |\n| `startup_ripple_v` | V | Final startup variation, 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `line_reg_v_per_v` | V/V | Absolute endpoint slope, upward 2.0–2.1 V at 1 mA | response / ratio; scale 0.001 | lower=0 |\n| `load_reg_ohm` | ohm | Absolute endpoint slope, upward 1–5 mA at 2.0 V | response / ratio; scale 0.01 | lower=0 |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **169100 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (370 units, sum 84512.210000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **7**.\n\n\n### Score weights\n\nGF180 line/load regulators: regulation 25.7%; load and line recovery 25.7%; ripple and rejection 17.1%; startup 12.9%; power 8.57%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_reg_v_per_v` | 0.064285714286 |\n| `load_reg_ohm` | 0.064285714286 |\n| `output_v` | 0.064285714286 |\n| `regulation_error_v` | 0.064285714286 |\n| `excursion_v` | 0.128571428570 |\n| `late_error_v` | 0.128571428571 |\n| `psrr_db` | 0.057142857143 |\n| `quiet_ripple_v` | 0.057142857143 |\n| `recovery_ripple_v` | 0.057142857143 |\n| `startup_error_v` | 0.064285714286 |\n| `startup_ripple_v` | 0.064285714286 |\n| `power_w` | 0.085714285714 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml","case_sha256":"74cdf0ae82fb0e29a765b85696f96cd241b2ef1764589d0c10c2bfae03bb5690","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl","netlist_sha256":"b3ed893165850ba59c078460a0c50ca3d808d92aeef5f73d166600b54f2cc176","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.ldo_004_basic_pmos","in_core":true,"title":"Externally Biased 1.8 V PMOS Regulator Core","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_004_basic_pmos","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Externally Biased 1.8 V PMOS Regulator Core Layout Task\n\n## Objective\n\nImplement the fixed `ldo_004_basic_pmos` regulator core in GF180MCU D and submit\nself-contained GDS. The circuit contains an error amplifier, a PMOS pass array\nand a physical feedback divider. Reference and tail-current generation are\nexternal to this core.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration.\n`materials/testbench.spice`, `materials/transient.spice` and\n`materials/dropout.spice` define the DC/AC, load-step and dropout measurements.\nThe ordered ports are `vdd vout vref ibias vss`: input supply, regulated output,\nreference-voltage input, error-amplifier tail node, and return. An external\n200 uA sink connects `ibias` to VSS; this is not a voltage-bias input.\n\nRetain the two NMOS input devices at W/L = 46/0.5 um, two PMOS mirror devices\nat 50/0.5 um, and the PMOS pass device at 10/0.3 um with multiplicity 100.\nEach feedback resistor is `ppolyf_u_1k`, width 2 um and length 200 um, giving\n100 squares of nominal 1 kohm/square poly. Preserve connectivity, dimensions\nand body connections. Placement, routing and electrically equivalent device\nsplitting/source-drain interchange are allowed only as accepted by the declared\nLVS checks. Provide physical well/substrate contacts to the declared rails.\nNo statistical matching or common-centroid constraint is scored.\n\n## Operating Conditions\n\nUse typical 3.3 V MOS and poly-resistor models at 27 C, with statistical\nvariation disabled, VSS = 0 V, external VREF = 0.9 V and a 200 uA tail sink.\nThe external output capacitor is an ideal 1 uF, without added ESR. All nine\ncombinations of VDD = 2.2, 2.7, 3.3 V and load = 0.1, 1, 5 mA are required.\nDC measurements follow the operating-point solve. AC uses 60 points per decade\nfrom 1 Hz to 100 MHz. Supply rejection drives VDD with 1 V AC and zero AC load;\noutput impedance drives the load sink with 1 A AC and zero AC supply.\n\nAt each of the three supplies, the transient starts from the DC operating point\nat 0.1 mA load. Load rises to 5 mA between 1 and 1.0001 ms, then falls to 0.1 mA\nbetween 2 and 2.0001 ms. Run to 3 ms with a 200 ns output step. Evaluate peak\nabsolute output error relative to 1.8 V over 0.9 to 3 ms, high-load settled error\nover 1.2 to 1.9 ms, low-load settled error over 2.2 to 3 ms, and minimum tail\nvoltage over 0.9 to 3 ms. The recovery windows start 200 us after each load-step onset. Their errors\nare continuous quality metrics with no upper acceptance bound; they do not\nestablish a recovery-time limit.\n\nThe separate dropout sweep uses 5 mA load and sweeps VDD from 1.6 to 2.4 V\nin 5 mV steps. Dropout is the supply voltage at the first rising crossing of\nVOUT = 1.75 V, minus 1.75 V, using interpolated crossing measurement.\nAll ideal supplies, sinks and the output capacitor are testbench apparatus.\n\n## Physical Requirements\n\nSubmit top cell `ldo_004_basic_pmos` with all five named electrical ports,\nresolved hierarchy and a maximum file size of 10 MiB. Artifact, GF180 variant-D\nDRC including antenna checks, strict named-port LVS and geometry must pass.\nThere are no DRC waivers. Chip-level density and seal-ring closure are outside\nthe standalone-block check scope.\n\nThe functional bounding box must fit within 800 by 400 um. Area includes all\nprocess device and routing drawing layers listed in the runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation text and pin-purpose shapes are excluded; functional routing must\nuse drawing layers.\n\nThe judge extracts distributed interconnect RC from the submitted GDS and uses\nthat extracted DUT in every simulation. MOS and physical resistor geometry are\ncandidate-derived. The model boundary retains external body connections but\ndoes not include a distributed silicon substrate network. Qualification covers\nnominal DC, AC supply rejection/output impedance and these load steps; it does\nnot establish full loop phase margin, startup, PVT, statistical mismatch, noise,\nEM/current-density limits, thermal behavior or fabrication signoff.\n\n## Electrical Requirements and Scoring\n\nEvery required observation must be finite and satisfy its inclusive band;\naggregation cannot hide a failing operating point. A missing dropout crossing\nor incomplete extraction/simulation cannot establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 3.3 | 3.3 | bias |\n| `tail_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 3.3 | 3.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-i(VLOAD)`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)-v(vref)*i(VREF)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `psrr_db` | AC: Value of `(-db(v(vout))) at=1k`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `peaking_db` | AC: `20*log10((max (mag(v(vout))) from=1 to=100meg)/(find (mag(v(vout))) at=1))`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `peak_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=0.9m to=3m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `high_settled_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=1.2m to=1.9m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `low_settled_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=2.2m to=3m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `tail_min_v` | TRAN: Minimum of `v(ibias) from=0.9m to=3m`. | V | target / target | 0 … 3.3 | 3.3 | bias |\n| `dropout_v` | DC sweep: `(when v(vout)=1.75 rise=1)-1.75`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n\nArea reference: **7597.32 um2**. 106 expanded device instances; sum of device/contact envelopes 4876.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nGF180 compact regulator variants: regulation and recovery 36%; rejection and peaking 18%; dropout 18%; quiescent current 9%; internal bias 1.8%; power 7.2%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `high_settled_error_v` | 0.090000000000 |\n| `low_settled_error_v` | 0.090000000000 |\n| `output_v` | 0.090000000000 |\n| `peak_error_v` | 0.090000000000 |\n| `peaking_db` | 0.090000000000 |\n| `psrr_db` | 0.090000000000 |\n| `dropout_v` | 0.180000000000 |\n| `quiescent_a` | 0.090000000000 |\n| `tail_min_v` | 0.009000000000 |\n| `tail_v` | 0.009000000000 |\n| `power_w` | 0.072000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 PDK/EDA resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the active harness. If `process-feedback`\nis exposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit the snapshot with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml","case_sha256":"ce81b0be63953d3451a1ca61a2079a2ac2c7b9f5c88b9ab2d7d8246562237dcd","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice","netlist_sha256":"c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.ldo_005_buffered_ref","in_core":false,"title":"Buffered-Reference LDO","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_005_buffered_ref","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Buffered-Reference LDO Layout Task\n\n## Objective\n\nImplement `ldo_005_buffered_ref` as a GF180MCU D layout. The fixed upstream GF180 6 V circuit combines its self-biased reference amplifier, gain-two reference divider, RC low-pass filter, self-biased error amplifier, PMOS pass device, bleeder and on-die output capacitor. The two inlined amplifiers retain this LDO accession's own dimensions and compensation values; they are not replaced by the standalone amplifier cases.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice`\ncontains matching native simulator wrappers. `materials/testbench.spice` defines\nall measurements. Ordered ports: `vdd vout vss vref`.\n\n`vdd/vss`: supply and return; `vout`: regulated output; `vref`: external 0.8 V reference. The upstream ideal VREF becomes test apparatus at this explicit port. Its zero-volt VLP loop marker becomes a wire to the output; no physical functional element is removed. The reference divider, RC filter, bleeder and four internal capacitors remain inside the DUT. External load and output capacitor remain test apparatus.\n\n## Operating Conditions\n\nTypical native models at 27 C, statistics disabled. All four combinations of 3.0/3.3 V supply and 50/200 uA DC load are evaluated, with a 0.8 V external reference and 1 uF external output load. AC supply injection spans 1 Hz–1 MHz, 80 points/decade. The load doubles at 100 us and returns after 100 us, with 1 us edges; transient evaluation ends at 500 us with 0.1 us requested steps. This is steady-state load-step characterization, not cold-start or dropout qualification.\n\n## Physical Requirements\n\nGDS database unit 0.001 um, maximum 10 MiB, top cell `ldo_005_buffered_ref`.\nNative standalone DRC covers geometry, connectivity, manufacturing grid, dummy\nfill and antenna; chip-level density and seal-ring closure are excluded.\nLVS must match all devices, parameters and named ports. Metal1 labels identify\nports. The functional bounding rectangle includes the device, well, implant,\ncontact, passive and complete routing layers enumerated in the runtime outline;\ntext annotations are excluded. Maximum outline is 5000 by 1000 um.\n\n6 V MOS minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS. Only subminimum lengths are raised, and dimensions are quantized to 5 nm. Passives use 1 kohm/square poly, with series segmentation, and 2 fF/um2 MIM-B on M4/M5, with parallel tiling. Source and extracted candidates use the same native layer-specific capacitor models. Geometry, parasitic effects and physical values are authoritative; no ideal R/C replacements are made during post-layout simulation.\n\nCandidate-derived native Magic coupling capacitance and distributed wire\nresistance feed post-layout simulation, with zero omission thresholds.\nPhysical MOS diffusion areas/perimeters come from the layout. Substrate/well\nconnections are ideal: distributed substrate resistance/noise and inductance\nare not represented. Nominal DC regulation, 1 kHz supply rejection and load-step excursion/recovery across four supply/load points. Coefficient 7 reflects interacting regulation stages and recovery across loads. Noise, loop return-ratio, cold start, dropout, PVT and statistical yield are outside this declared scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `output_v` | DC regulated output | V | bias | target |\n| `regulation_error_v` | Absolute DC error relative to 1.6 V | V | response | ratio |\n| `psrr_db` | Negative 20 log10 magnitude of supply-to-output response at 1 kHz | dB | response | db20 |\n| `excursion_v` | Output maximum minus minimum over 90–500 us | V | response | ratio |\n| `recovery_v` | Mean output over 400–500 us after the load returns | V | bias | target |\n| `power_w` | DC supply power -VDD*I(VDD) | W | supply | ratio |\n| `minimum_v` | Minimum transient output over 90–500 us | V | functional | unscored |\n| `maximum_v` | Maximum transient output over 90–500 us | V | functional | unscored |\n\nOutput and recovered output must be in 0–3.3 V; the transient minimum must be nonnegative and the maximum at most 3.3 V. Supply power and absolute/range errors must be nonnegative. These are supply-domain and physical measurement constraints. Accuracy, rejection and recovery differences enter continuous scoring; no upstream regulation target is a hard gate.\nEvery condition must complete; missing, nonfinite or wrong-unit observations\nproduce an evaluation error. Upstream advertised performance is not a\nqualification requirement.\n\nScored observations pair with independent source jobs using the identical\nstimuli, parameters, models and backend. Target scales are 3.3 V; ratio floors\nare 1 pW for power and 1 mV for error/excursion. These are normalization units,\nnot allowed degradation. `db20` compares\namplitude ratios.\n\nArea anchor **29565.16 um2** uses a 18964.964200 um2 sum of expanded\n`(W+2)*(L+2)` device/contact envelopes, a 50% routing allowance and 2 um outer\nmargin: `ceil(100*(1.5*sum+8*sqrt(sum)+16))/100`. It is independent of witness\narea and is an engineering estimate, not a foundry minimum. Coefficient **7**\nis independent of this score.\n\n\n### Score weights\n\nGF180 compact regulator variants: regulation and recovery 52.9%; rejection and peaking 26.5%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `excursion_v` | 0.132352941176 |\n| `output_v` | 0.132352941176 |\n| `recovery_v` | 0.132352941176 |\n| `regulation_error_v` | 0.132352941176 |\n| `psrr_db` | 0.264705882355 |\n| `power_w` | 0.105882352941 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRead `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. KLayout performs physical checks, Magic extracts the\ncandidate, and ngspice measures it. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit using\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml","case_sha256":"72472f50517883b49724573e7b61dd3b7f3272f0b9a9e2d0b24b46bccc29f8f4","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl","netlist_sha256":"1e1c14a91036bf5d0069bcc2a22f99e65c5f6a0a963377cc1e0ff2120293c9ff","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.ldo_006_stub","in_core":false,"title":"Divider-Biased NMOS Source Follower","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Tracks an input bias with a divider-biased NMOS source follower.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_006_stub","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Divider-Biased NMOS Source Follower Layout Task\n\n## Objective\n\nA single fixed 50/0.5 um nfet_03v3 (m=1) forms a source follower. Its drain connects to vdd, source to vout, body to vss, and gate to the midpoint of the internal 100 kohm/100 kohm supply divider. Each resistor uses two native ppolyf_u_1k segments, totaling 99995.18 ohm at TT/27 C. There is no control input, external reference, error amplifier or closed-loop regulator. Target top cell: `ldo_006_stub`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (drain and divider supply), vout (source output), vss (body/divider return).\n\n## Operating Conditions\n\nGF180 TT, 27 C. Supply is independently 1.2 or 1.5 V; output load is independently 100 kohm or 1 Mohm, in parallel with 10 pF. A 1 uA sink turns on at 2 us with a 20 ns edge and stays on throughout the 10 us run. Maximum step is 2 ns. The initial state has zero additional sink current and is computed by DC OP. A separate loaded DC OP with a 1 uA sink is compared with the 8–10 us transient endpoint. Supply power includes the divider, transistor and resistive load.\n\n## Physical Requirements\n\nUse GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | DC loaded source-follower output | 0 to 1.5 | bias: target, target, scale=0.1 |\n| `power_w` | W | DC power including internal 100k/100k divider | 0 to unbounded | supply: ratio, minimize, scale=1e-12 |\n| `step_shift_v` | V | Mean output at 8–10 us minus initial output | unbounded to unbounded | response: target, target, scale=0.1 |\n| `ripple_v` | V | Peak-to-peak output over final 2 us | 0 to unbounded | diagnostic / functional only |\n\nOnly output operating point, finite load-step shift and actual supply loss are scored. Late-window ripple is an unscored diagnostic; sub-nanovolt ripple is below numerical voltage resolution. No regulation accuracy, PSRR, dropout or loop-margin claim is made. The model guide includes 50 um width as a pseudo-device scaling boundary, not a directly measured width sample.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 1200 um2 = 50 × 6 um2 pass-device/contact envelope + 4 × 55 × 2 um2 resistor/contact/isolation envelopes + 460 um2 routing/guard-ring allowance. It is a compact engineering estimate independent of witness sparsity. Coefficient 3: local analog bias/transfer and controlled load response. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nRegulator stub: loaded operating point 34%; load response 34%; power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `output_v` | 0.340000000000 |\n| `step_shift_v` | 0.340000000000 |\n| `power_w` | 0.170000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml","case_sha256":"3a47bf05ab107c1f351121652575a3e1687eb0ea83580f2ac8a13a35f0548534","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl","netlist_sha256":"b2cbf5b0cf0497af8ad62bded31556d61ed2d15ff665966e7e8e5e7772a58aa3","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.ldo_007_pmos","in_core":false,"title":"PMOS LDO with Feedforward Compensation","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_007_pmos","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# PMOS LDO with Feedforward Compensation Layout Task\n\n## Objective\n\nImplement `ldo_007_pmos` as a GDS layout preserving the complete declared circuit. Five-transistor error amplifier, NMOS bias diode and PMOS pass array with complete resistive feedback divider, feedforward CFF across the upper divider, and series RZ/CC across the pass stage. Seven bound MOS expand to 146 units. The 0 V VLP feedback marker becomes a wire; ideal reference and current bias remain external apparatus.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/startup.spice`: startup observations.\n- `materials/regulation.spice`: regulation observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vdd vout vss ebias vref`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\nNominal supply 1.8 V, external reference 1.05 V and 60 uA from VDD into ebias; 27 C, typical GF180 3.3 V models with statistics disabled. Rtop=5 kohm and Rbottom=35 kohm set nominal output 1.2 V. The 140-fold pass array retains 20 um width and 0.5 um length per unit. CFF=60 pF, CC=0.05 pF and RZ=1 ohm are retained. RZ uses twelve parallel native high-poly units (L=1 um, W=97.21 um), nominal 1.000096 ohm at 27 C, to avoid an impossible sub-grid resistor length. No compensation is deleted. External reference-generation and current-source implementation losses are excluded; the 60 uA drawn from VDD and physical divider are included in rail power. External output capacitance is 1 nF with 0.1 ohm series ESR. Evaluate no disturbance, 1-to-2 mA load pulse, and +0.1 V input pulse, plus independent DC points at nominal+0.1 V/1 mA and nominal/2 mA. Pulses start at 100 us, have 1 us edges and 100 us high width; restoration finishes at 202 us. Observe 0–400 us with 10 ns maximum step; pre-step/high/recovery windows are 80–100/180–200/380–400 us. Supply rejection is measured at 1 kHz from a 1 V AC supply input (100 samples/decade, 1 Hz–100 MHz). Ascending DC sweeps cover nominal supply to nominal+0.1 V in 10 mV increments at 1 mA and 1–2 mA load in 0.1 mA increments at nominal supply; adjustment metrics are absolute endpoint slopes. These are finite ranges, not dropout measurements. Startup ramps VDD from zero to nominal in 10 us with fixed external references and a resistive 1 mA nominal load (target voltage/1 mA); it uses the ordinary initial DC solution, no UIC or forced initial output, and observes through 400 us. Startup extrema and late-window output/ripple are diagnostics. No dropout, loop gain or phase margin is claimed. Source and candidate use identical decks and parameters; no numerical shunt is used.\n\n## Physical Requirements\n\nGF180MCU D native standalone-block FEOL/BEOL, connectivity, grid, dummy and antenna rules; chip density/seal-ring rules are outside this block boundary. Named-port LVS and candidate-derived distributed Magic RC are required. Functional area includes active/poly, passives and all routing metal/vias. Capacitor substrate and resistor terminal models follow the frozen PDK profile. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 20000 by 2000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_v | V | DC output | bias; target (scale 1.2) |\n| regulation_error_v | V | Absolute DC setpoint error | response; ratio (scale 0.001) |\n| power_w | W | Total input rail DC power, including physical bleed/divider and external current bias | supply; ratio (scale 1e-12) |\n| psrr_db | dB | Input supply rejection at 1 kHz | response; db20 |\n| quiet_ripple_v | V | Peak-to-peak pre-perturbation output 80–100 us | response; ratio (scale 0.001) |\n| recovery_ripple_v | V | Peak-to-peak recovered output 380–400 us | response; ratio (scale 0.001) |\n| excursion_v | V | Full output range 100–400 us | response; ratio (scale 0.001) |\n| late_error_v | V | Mean absolute setpoint error 380–400 us | response; ratio (scale 0.001) |\n| mean_power_w | W | Mean input rail power 0–400 us | supply; ratio (scale 1e-12) |\n| quiet_v | V | Finite-window quiet_v | diagnostic; unscored |\n| high_v | V | Finite-window high_v | diagnostic; unscored |\n| recovery_v | V | Finite-window recovery_v | diagnostic; unscored |\n| startup_final_v | V | 10 us input ramp with resistive load: startup_final_v | diagnostic; unscored |\n| startup_ripple_v | V | 10 us input ramp with resistive load: startup_ripple_v | diagnostic; unscored |\n| startup_min_v | V | 10 us input ramp with resistive load: startup_min_v | diagnostic; unscored |\n| startup_max_v | V | 10 us input ramp with resistive load: startup_max_v | diagnostic; unscored |\n| line_reg_v_per_v | V/V | Absolute ascending supply-sweep endpoint slope, nominal to nominal + 0.1 V, 1 mA load | response; ratio (scale 0.001) |\n| load_reg_ohm | ohm | Absolute ascending load-sweep endpoint slope, 1 to 2 mA, nominal supply | response; ratio (scale 1) |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 98448.9 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. For ordinary GF180 resistors this envelope conservatively uses the sheet-only length before contact correction; the explicit parallel 1-ohm bank uses its native dimensions. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 7 covers regulation, frequency response and recovery across loads. No on-chip reference/bias generator is claimed. No loop-gain measurement is used, so CFF cannot bypass a purported loop break. The native resistor model includes terminal resistance in both source and candidate.\n\n\n### Score weights\n\nGF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_reg_v_per_v` | 0.075000000000 |\n| `load_reg_ohm` | 0.075000000000 |\n| `output_v` | 0.075000000000 |\n| `regulation_error_v` | 0.075000000000 |\n| `excursion_v` | 0.149999999999 |\n| `late_error_v` | 0.150000000000 |\n| `psrr_db` | 0.066666666667 |\n| `quiet_ripple_v` | 0.066666666667 |\n| `recovery_ripple_v` | 0.066666666667 |\n| `mean_power_w` | 0.050000000000 |\n| `power_w` | 0.050000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `ldo_007_pmos`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml","case_sha256":"2c6a1875c4327f5b25fa89eadd2bc7eab6c5a7e0a0c1eeaed625b9e5a09185f7","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl","netlist_sha256":"4b3f01ca7600933022e7730cc7cfb614b7abcc2808f7ef777b0019b27514382a","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.sup_001_vcm_detector","in_core":false,"title":"Passive Resistive Common-Mode Averager","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Averages two input voltages through a passive resistive common-mode network.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sup_001_vcm_detector","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Passive Resistive Common-Mode Averager Layout Task\n\n## Objective\n\nTwo matched 1 Mohm resistors join vinp to vcm_out and vcm_out to vinn. This is a passive average detector, without a buffer, amplifier or CMFB controller. The fixed IHP binding contains ideal R cards, not process-specific resistor models; the maintained physical adaptation uses forty native GF180 ppolyf_u_1k segments (twenty per branch), totaling 999951.8 ohm per branch at TT/27 C. The extra vss port grounds their physical substrate; it is not a functional supply. Target top cell: `sup_001_vcm_detector`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vcm_out (sense output), vinp (positive input), vinn (negative input), vss (physical substrate).\n\n## Operating Conditions\n\n27 C, TT. External ideal drivers are 0.8 V and 0.4 V, each followed by 1 kohm source resistance. The output has 1 pF and either 1 Mohm or 1 Gohm to ground. Each load uses common-mode AC (both drivers +1 V) and differential AC (+1/-1 V), 1 Hz–10 MHz at 40 points/decade. Both drivers increase by 0.1 V at 1 us, with 10 ns edges, and stay high through the 5 us observation. Maximum transient step is 2 ns. The initial state is the same biased DC operating point for source and candidate. A 1 Gohm load is a finite high-impedance observation, not an unloaded claim. The analytic DC limit is Vcm*RL/(RL+500.5 kohm), tending to Vcm only as RL tends to infinity. Both input-source powers are included; no zero-power claim follows from the absence of a supply pin.\n\n## Physical Requirements\n\nUse GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | Loaded DC sense voltage | 0 to 0.8 | bias: target, target, scale=0.1 |\n| `power_w` | W | Net delivered power from both external input sources | 0 to unbounded | supply: ratio, minimize, scale=1e-12 |\n| `gain` | 1 | Output magnitude at 1 Hz for declared common/differential input | unbounded to unbounded | response: target, target, scale=1 |\n| `gain_10khz` | 1 | Output magnitude at 10 kHz | unbounded to unbounded | response: target, target, scale=1 |\n| `step_error_v` | V | Mean absolute error from settled DC target over 2–4 us | 0 to unbounded | response: ratio, minimize, scale=1e-06 |\n\nThe 2–4 us average absolute step error is a finite-window quantity. Common and differential AC magnitudes use a 1 V half-input normalization; the differential residual is not divided by a near-zero source result. Nominal deterministic matching does not establish statistical mismatch or noise.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 6000 um2 = 40 × 55 × 2 um2 resistor/contact/isolation envelopes + 1600 um2 routing allowance. Each envelope accommodates the approximately 48.44 um resistor, end contacts and lateral spacing; the estimate permits folding. It is independent of the long, sparse witness. Coefficient 4: coupled matching, physical passive network, finite loading and parasitic dynamics. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nCommon-mode sensing/controllers: recovery and error 40.5%; signed transfer 31.5%; output bias 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `step_error_v` | 0.405000000000 |\n| `gain` | 0.157500000000 |\n| `gain_10khz` | 0.157500000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml","case_sha256":"d55e2d90c82eb4a446b13abeca2375c30aa7bea68a78fd683cce8f4af4104670","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl","netlist_sha256":"c0cdf0e12dbdbfc2e7d1fd9fe3c061a29f745efd8656e1a85e100036489db523","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.tsn_001_ptat_2t","in_core":false,"title":"Two-NMOS Temperature-Response Core","pdk":"gf180mcuD","category":"Power & references","summary":"Produces a temperature-dependent response whose slope and curvature are measured across the declared range.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_001_ptat_2t","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Two-NMOS Temperature-Response Core Layout Task\n\n## Objective\n\nThe fixed GF180 binding contains eight parallel 8/0.28 um upper NMOS with gates tied to their sources, and eight parallel 4/1 um diode-connected lower NMOS. Both groups have grounded bodies. This is a two-group temperature-response core; neither its PTAT name nor a successful simulator exit establishes a useful slope or a converged extracted operating point. Target top cell: `tsn_001_ptat_2t`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/temperature.spice` supplies the shared external fixture and bidirectional temperature sweep. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (supply), vout (sense voltage), vss (both bodies and return).\n\n## Operating Conditions\n\nGF180 nfet_03v3 TT, fixed 1.2 V supply, 1 Tohm probe resistance and 1 pF to ground. No external current bias changes with temperature. Ascending and descending temperature sweeps use 5 C steps. Output and power at -20 through 120 C in 10 C steps are sampled from the same ascending sweep used for slope and curvature. The fixed 50 mV nodeset is a Newton initial guess, not a voltage source or a per-temperature bias adjustment. Sparse 1.3, pivtol=1e-30 S, pivrel=0.001, reltol=1e-7, abstol=1e-18 A, vntol=1e-10 V and gmin=1e-18 S are explicit for both circuits; no rshunt is used.\n\n## Physical Requirements\n\nUse GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | Independent DC temperature-response output | 0 to 1.2 | bias: target, target, scale=0.1 |\n| `power_w` | W | DC supply power at fixed 1.2 V | 0 to unbounded | supply: ratio, minimize, scale=1e-15 |\n| `slope_v_c` | V/C | Endpoint temperature slope over -20 to 120 C | unbounded to unbounded | response: target, target, scale=0.001 |\n| `curvature_v` | V | Maximum deviation from endpoint secant over -20 to 120 C | 0 to unbounded | response: ratio, minimize, scale=1e-06 |\n\nThe simulator uses an explicit branch-current formulation for constant parasitic resistors: a zero-volt current sensor and a current-controlled voltage source impose V=R*I exactly. Every resistance, terminal and extracted capacitance is retained. This avoids loss of tiny node conductances when added to the much larger metal conductance in conventional nodal stamping. The original extraction and the effective simulation netlist are both retained as evidence. Source and candidate use the same backend setting. This deterministic formulation does not model resistor thermal noise; noise is outside this task's scope. KCL and measurement-validity checks remain mandatory. No self-startup, precision temperature sensing or linear PTAT behavior is assumed.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 1600 um2 = 8 × 10 × 10 um2 upper-device/contact envelopes + 8 × 6 × 8 um2 lower-device/contact envelopes + 416 um2 routing/body-contact allowance, independent of witness area. Coefficient 3: local analog temperature-dependent bias and transfer. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nTemperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `slope_v_c` | 0.423529411764 |\n| `curvature_v` | 0.317647058824 |\n| `output_v` | 0.052941176471 |\n| `power_w` | 0.105882352941 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml","case_sha256":"ae46695ccced40bea2ff56991b625536b0e5f297958c5f450d761d54b11135c6","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl","netlist_sha256":"534d2b4bdfe4354bd80c0db81495c5d60a73fe20912ba79f3ccb749fadaf7efc","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.tsn_002_ptat_classic","in_core":true,"title":"Self-Starting Isolated-Body PTAT Core","pdk":"gf180mcuD","category":"Power & references","summary":"Produces a temperature-dependent response whose slope and curvature are measured across the declared range.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_002_ptat_classic","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Starting Isolated-Body PTAT Core Layout Task\n\n## Objective\n\nImplement `tsn_002_ptat_classic` in GF180MCU D and submit self-contained GDS.\nThe resistor-degenerated four-MOS source core has a positive temperature slope;\ncandidate slope is measured and source-paired without a positive-slope acceptance bound.\nA maintained three-MOS startup branch establishes its operating state after\npower-up. Supply sensitivity remains: this is not a precision temperature\nreference or a calibrated thermometer.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical LVS authority;\n`materials/circuit.spice` is its simulator representation.\n`materials/testbench.spice` defines stimuli and observations. This problem is\nthe description input. Ordered ports are `vdd vout vss`: supply,\ntemperature-dependent output and return.\n\nRetain all device dimensions, multiplicities and four-terminal connections.\nThe 8/1 um core NMOS has both source and body on `vout`; its body must remain\nisolated from VSS. The physical primitive `MM0 ... nfet_03v3_dn` maps to\n`XM0 ... nfet_03v3` in the simulator, with the same D/G/S/B and W/L/m.\nUse an isolated P-well inside a supply-tied deep N-well, with explicit\nN-well enclosure and physical well/substrate contacts. Extraction must retain\nthe separation between the output body and substrate return. No body-to-VSS\nsubstitution is permitted. The core resistor is physical 1 kohm/square poly,\nW=2 um, L=40 um, nominal 20 kohm.\n\nThe added startup devices have W/L of 0.42/20 um (weak PMOS pull-up),\n2/0.28 um (NMOS detector) and 0.42/1 um (NMOS injector). The detector reduces\nthe startup control voltage after bias is established, turning off the\ninjection path. The weak pull-up/detector branch still draws static current;\nall DUT supply power is measured. Preserve this branch as part of the DUT.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No statistical matching\nor placement style is scored. External stimulus and the output load belong to\nthe testbench and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse typical GF180 3.3 V MOS and poly models with statistical variation disabled.\nVSS is 0 V. Evaluate all 18 combinations of VDD = 2.7/3.0/3.3 V,\ntemperature = -20/27/100 C and supply rise time = 0.1/10 us.\nEach condition measures its DC operating point and a -20 to 100 C sweep in\n1 C steps. The temperature is then restored to the selected value before\nstartup simulation. The external output capacitance is exactly 100 fF.\n\nFor startup, ramp VDD linearly from 0 to its selected value, then hold it.\nUse a zero-initial-state `uic` transient through 100 us with no internal\ninitial-condition bias or auxiliary startup source. Gear order 2 and a\nmaximum timestep of 1 ns are declared. Measure final error, ripple and average\npower over 90–100 us. These are finite-window error and ripple observations with no settling-error\nacceptance threshold; they do not establish settling time or bound overshoot.\n\n## Physical Requirements\n\nSubmit top cell `tsn_002_ptat_classic`, all named electrical ports, resolved\nhierarchy and at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass with no DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 220 by 65 um. Its area includes\nall declared device and routing drawing layers: wells (including deep N-well\nand isolated P-well), implants, active, poly, contacts, metals/vias and device\nmarkers. Annotation and pin-purpose shapes are excluded. All functional\nrouting must use drawing layers. `/protocol/task.json` freezes the layer set.\n\nIndependent candidate extraction retains MOS and resistor geometry and adds\ndistributed wiring RC. All scored simulation consumes that extracted DUT.\nThis does not include a distributed silicon substrate model. Larger output\nloads are unqualified and can cause oscillation; this is not a pF-load output\nbuffer. Brownout/restart, arbitrary supply ramps, process/statistical corners,\nnoise, absolute temperature accuracy, supply rejection, EM and fabrication\nsignoff are outside scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output at the selected supply and temperature | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC delivered supply power, -V(vdd)*I(VDD), including startup bias | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `cold_v` | Output at -20 C | V | target / target | 0 … 3.3 | 3.3 |\n| `hot_v` | Output at 100 C | V | target / target | 0 … 3.3 | 3.3 |\n| `slope_v_per_c` | (hot_v - cold_v)/120 C | V/C | target / target | −∞ … +∞ | 0.00047 |\n| `curvature_v` | Maximum absolute deviation from the endpoint line at all 121 temperatures | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `minimum_slope` | Minimum ngspice deriv(output) over temperature | V/C | target / target | −∞ … +∞ | 0.00055 |\n| `maximum_slope` | Maximum ngspice deriv(output) over temperature | V/C | target / target | −∞ … +∞ | 0.00055 |\n| `peak_power_w` | Maximum delivered supply power over temperature | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `startup_error_v` | Maximum absolute output error against the selected DC operating point during 90–100 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `ripple_v` | Maximum minus minimum output during 90–100 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `final_power_w` | Time-average delivered supply power during 90–100 us | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **529.13 um2**. 8 expanded device instances; sum of device/contact envelopes 303.6200 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTemperature-slope cores: temperature slope 36%; curvature 27%; startup 13.5%; output endpoints 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `maximum_slope` | 0.120000000000 |\n| `minimum_slope` | 0.120000000000 |\n| `slope_v_per_c` | 0.120000000000 |\n| `curvature_v` | 0.270000000000 |\n| `ripple_v` | 0.067500000000 |\n| `startup_error_v` | 0.067500000000 |\n| `cold_v` | 0.015000000000 |\n| `hot_v` | 0.015000000000 |\n| `output_v` | 0.015000000000 |\n| `final_power_w` | 0.030000000000 |\n| `peak_power_w` | 0.030000000000 |\n| `power_w` | 0.030000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources in `/protocol/resources.json`. KLayout checks\nphysical validity and geometry, Magic extracts RC and ngspice simulates the\ncircuit. `/protocol/task.json` provides frozen requirements and\n`/protocol/harness.json` describes the harness. When `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then submit with `python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml","case_sha256":"7e55370aaf8b7af565f5184681e6716ec83d8a276446c05c92522b4eb3b10114","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl","netlist_sha256":"1efc6b4da14d95c12ff19bd3a1e8a10a8c986a97befff37dadb44ce6f10ef5ea","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.analog-db.tsn_003_ptat_4t_xcoupled","in_core":false,"title":"Four-Transistor Positive-Temperature-Slope Core","pdk":"gf180mcuD","category":"Power & references","summary":"Produces a temperature-dependent response whose slope and curvature are measured across the declared range.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_003_ptat_4t_xcoupled","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Four-Transistor Positive-Temperature-Slope Core Layout Task\n\n## Objective\n\nImplement the fixed `tsn_003_ptat_4t_xcoupled` circuit in GF180MCU D and submit self-contained GDS.\nTwo NMOS and two PMOS devices form a resistorless temperature-dependent voltage core with cross-coupled bias connections. The fixed GF180 sizes are retained. The output increases with temperature under each declared supply, but both voltage and slope depend strongly on supply. This is a temperature-slope layout task, not a precision reference or calibrated thermometer.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd vout vss`.\nIn order, these are: Supply, unloaded temperature-dependent output, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVSS = 0 V; VDD = 2.7, 3.0 and 3.3 V. Measure the operating point at 27 C, then sweep temperature from -20 to 100 C inclusive in 1 C steps at each supply. The output is unloaded except for the measurement probe. No ideal internal source or passive is added.\n\n## Physical Requirements\n\nSubmit top cell `tsn_003_ptat_4t_xcoupled` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 120 by 60 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThe temperature sweep is a nominal model sweep, not process-corner or statistical qualification. Startup, output drive, absolute temperature accuracy, supply rejection, mismatch, noise and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `cold_v` | Output at -20 C | V | target / target | 0 … 3.3 | 3.3 |\n| `hot_v` | Output at 100 C | V | target / target | 0 … 3.3 | 3.3 |\n| `slope_v_per_c` | (Output at 100 C - output at -20 C)/120 C | V/C | target / target | −∞ … +∞ | 0.00036 |\n| `curvature_v` | Maximum deviation from the endpoint line over all 121 temperature samples | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `minimum_slope` | Minimum ngspice deriv(output) over the temperature sweep | V/C | target / target | −∞ … +∞ | 0.00024 |\n| `maximum_slope` | Maximum ngspice deriv(output) over the temperature sweep | V/C | target / target | −∞ … +∞ | 0.00036 |\n| `peak_power_w` | Maximum -V(vdd)*I(VDD) over the full temperature sweep | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **168.38 um2**. 4 expanded device instances; sum of device/contact envelopes 85.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **3**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTemperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `maximum_slope` | 0.141176470588 |\n| `minimum_slope` | 0.141176470588 |\n| `slope_v_per_c` | 0.141176470588 |\n| `curvature_v` | 0.317647058822 |\n| `cold_v` | 0.017647058824 |\n| `hot_v` | 0.017647058824 |\n| `output_v` | 0.017647058824 |\n| `peak_power_w` | 0.052941176471 |\n| `power_w` | 0.052941176471 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml","case_sha256":"8576bf939c13cb0a1cedb4855f4e09a92ba6a5811af0ab7552b30e35461dcb8e","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice","netlist_sha256":"f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09","license_path":"tasks/gf180mcuD/analog-db/LICENSE"} +{"id":"gf180mcuD.gf-r2r-dac.r2r","in_core":true,"title":"Eight-Bit R-2R DAC Core","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Converts an eight-bit digital code into an analog voltage through an R-2R network.","source_url":"https://github.com/mattvenn/gf-r2r-dac/tree/1c5c8ddec54fc4e70ce03a19510d4d7461b919e9/xschem/simulation/r2r.spice","status":"qualified","collection":"gf-r2r-dac","task_kind":"netlist_to_gds","problem":"# Eight-Bit R-2R DAC Core Layout Task\n\n## Objective\n\nImplement `r2r` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Eight-bit passive voltage conversion with ideal external bit drivers and a 1 pF output load; zero, eight one-hot codes and full scale.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `b7, b1, b0, b2, b3, b4, b5, b6, out, VGND`.\nb0–b7: ideal-driver bit inputs (b0 is LSB); out: analog output; VGND: substrate and ladder return.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V bit-driver levels and 27 C, with 1 pF from out to VGND. Evaluate codes 0, 1, 2, 4, 8, 16, 32, 64, 128 and 255 separately. bit0 is the least significant bit. Each bit starts at 0 V and changes from 10 ns to 10.1 ns to 3.3*bitN V. Simulate through 2 us with a 1 ns requested step. The expected settled voltage is 3.3*code/256 V. The external drivers and load are testbench components, outside the required passive circuit.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `r2r` and at most 10485760 bytes. Its functional bounding box must not exceed 200 by 200 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `accuracy` | Absolute difference between output at 1.9 us and 3.3*code/256, checked independently for each declared code. | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `settling` | Absolute difference between output at 1 us and 3.3*code/256 after the 10 ns input transition. | V | minimize / ratio | 0 … +∞ | 1e-06 |\n\nArea reference: **8727.76 um2**. 27 expanded device instances; sum of device/contact envelopes 5616.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nPassive R-2R DAC: conversion accuracy 63%; dynamic residual 27%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `accuracy` | 0.630000000000 |\n| `settling` | 0.270000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml","case_sha256":"4b8fa1f0e83dc6d5b3a65e1c8a04e59f6a00e66df24f61477013ab7a3335bed2","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md","netlist_path":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice","netlist_sha256":"64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957","license_path":"tasks/gf180mcuD/gf-r2r-dac/LICENSE"} +{"id":"gf180mcuD.tt_tnt_gf_vco.vco","in_core":true,"title":"Quadrature Voltage-Controlled Oscillator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Generates quadrature oscillation with a voltage-controlled tuning response.","source_url":"https://github.com/smunaut/tt_tnt_gf_vco/tree/897b3ec12ed693161fb56f4205d1b19dc5e56c1a/xschem/vco.sch","status":"qualified","collection":"tt_tnt_gf_vco","task_kind":"netlist_to_gds","problem":"# Quadrature Voltage-Controlled Oscillator Layout Task\n\n## Objective\n\nImplement `vco` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Four-phase oscillation, quadrature and frequency tuning at control voltages 1.65 V and 2.10 V, with 50 fF on each output.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `GND, VDD, ctrl, out_0, out_90, out_180, out_270`.\nGND/VDD: return/supply; ctrl: tuning voltage; out_0/out_90/out_180/out_270: quadrature outputs.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 27 C and two independent copies of the submitted circuit at ctrl = 1.65 V and 2.10 V. Each copy has its own ideal supply ramping from 0 V at 0 ns to 3.3 V at 1 ns and 50 fF from each output to ground. Simulate through 600 ns with a 0.02 ns requested step. Characterize steady oscillation over 400–600 ns. Each operating point must meet every applicable requirement; their supply powers are checked individually.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `vco` and at most 10485760 bytes. Its functional bounding box must not exceed 700 by 240 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `low_control_frequency` | Inverse period between the first two out_0 rising 1.65 V crossings after 400 ns at ctrl=1.65 V. | Hz | target / target | 0 … +∞ | 150000000.0 |\n| `high_control_frequency` | The same frequency measurement at ctrl=2.10 V. | Hz | target / target | 0 … +∞ | 300000000.0 |\n| `tuning` | Frequency at 2.10 V divided by frequency at 1.65 V. | 1 | maximize / ratio | 0 … +∞ | — |\n| `quadrature90` | First out_90 versus out_0 rising-crossing displacement after 400 ns, divided by period and reduced modulo one cycle. | 1 | target / target | −∞ … +∞ | 1.0 |\n| `quadrature180` | The same phase measurement for out_180. | 1 | target / target | −∞ … +∞ | 1.0 |\n| `quadrature270` | The same phase measurement for out_270. | 1 | target / target | −∞ … +∞ | 1.0 |\n| `low` | Minimum voltage on each output over 400–600 ns at each control voltage. | V | functional check | −∞ … 0.33 | — |\n| `high` | Maximum voltage on each output over 400–600 ns at each control voltage. | V | functional check | 2.97 … +∞ | — |\n| `supply` | Average delivered supply power over 400–600 ns, separately for each control voltage. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **907.08 um2**. 47 expanded device instances; sum of device/contact envelopes 540.0800 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nQuadrature VCO: frequency targets 31.5%; tuning 18%; quadrature 27%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `high_control_frequency` | 0.157500000000 |\n| `low_control_frequency` | 0.157500000000 |\n| `tuning` | 0.180000000000 |\n| `quadrature180` | 0.090000000000 |\n| `quadrature270` | 0.090000000000 |\n| `quadrature90` | 0.090000000000 |\n| `supply` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml","case_sha256":"0216ce13ab17e57ba9f49bea65d267a15b41c8dedf27f6769ba9fad6c1d851b0","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md","netlist_path":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice","netlist_sha256":"021943933973e205dfb533131232917d18d1ffe8b24bedc5e45534992e2a1615","license_path":"tasks/gf180mcuD/tt_tnt_gf_vco/LICENSE"} +{"id":"gf180mcuD.voidwalkers-scandff.scan_dff","in_core":true,"title":"Scan D Flip-Flop with Active-Low Reset","pdk":"gf180mcuD","category":"Logic & memory","summary":"Stores a clocked bit with scan selection and asynchronous active-low reset.","source_url":"https://github.com/radityankn/voidwalkers-scandff-gf180mcu/tree/b136150cdcfd55a9568fe14a825c214c3af5dde4/designs/cells/gf180mcu_voidwalkers_sc_sdffrnq_4/sch/gf180mcu_voidwalkers_sc_sdffrnq_4.sch","status":"qualified","collection":"voidwalkers-scandff","task_kind":"netlist_to_gds","problem":"# Scan D Flip-Flop with Active-Low Reset Layout Task\n\n## Objective\n\nImplement `gf180mcu_voidwalkers_sc_sdffrnq_4` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Functional data and scan selection, rising-edge storage, asynchronous active-low reset, and 50 MHz operation with 50 fF load.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `S, VDD, Q, B, CLK, A, RN, VSS`.\nVDD/VSS: supply/return; A: functional data; B: scan data; S: select (0=A, 1=B); CLK: rising-edge clock; RN: active-low asynchronous reset; Q: stored output.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C, a 50 fF Q load and the same 50 MHz clock throughout (first rise 10 ns, rise/fall 0.1 ns, high time 10 ns). Select A initially; select B at 40.1 ns; return to A at 80.1 ns. A rises at 20.1 ns, falls at 60.1 ns, rises at 100.1 ns and falls at 120.1 ns. B rises at 60.1 ns. RN starts low, releases at 5.1 ns, asserts at 85.1 ns and releases at 95.1 ns. All data/reset transitions take 0.1 ns, as specified in the testbench. Simulate through 140 ns.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `gf180mcu_voidwalkers_sc_sdffrnq_4` and at most 10485760 bytes. Its functional bounding box must not exceed 80 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n\nThe standard-cell functional frame has fixed height 6.35 um and width on a 0.005 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.\n\n- `VDD`: centre y = 6 um, thickness at least 0.23 um, from left + 0 um to right − 0 um.\n- `VSS`: centre y = 0.35 um, thickness at least 0.23 um, from left + 0 um to right − 0 um.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `low` | Q at 19, 59, 89, 99 and 139 ns; the 89 ns sample checks asynchronous reset before the next rising clock. | V | functional check | −∞ … 0.33 | — |\n| `high` | Q at 39, 79 and 119 ns, exercising functional and scan data. | V | functional check | 2.97 … +∞ | — |\n| `propagation_delay` | Worst paired quality over: delay_data_rise, delay_data_fall, delay_scan_rise, delay_scan_fall, delay_reset_fall. | s | minimize / ratio | 0 … +∞ | — |\n| `output_transition` | Worst paired quality over: slew_data_rise, slew_data_fall, slew_scan_rise, slew_scan_fall, slew_reset_fall. | s | minimize / ratio | 0 … +∞ | — |\n| `supply` | Average VDD power over 20–140 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **175.5775 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 27.65 by 6.35 um = 175.577 um2. Reference SHA-256: ffd6654d5505bf6340acbb3061ad81fab36951badda45b3bd3a8448be0fa00ab. This footprint includes the maintained explicit taps and routing.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n### Standard-cell design guidance\n\nPlan the device rows, power rails and signal access before routing. Represent\npull-up and pull-down connectivity as transistor-edge graphs; explore compatible\nEuler trails and alternative orderings to share diffusion and reduce breaks.\nChoose among legal orderings using routing length, parasitic loading and signal\naccess, rather than diffusion sharing alone. Preserve the fixed netlist sizes,\nmodels and connectivity; size optimization is outside this task.\n\nUse the task's declared row height, grid and rail geometry. Keep local routes\ncompact, leave signal pins accessible, and avoid consuming extra routing layers\nwithout benefit. Check DRC and named-port LVS, then extract the candidate and\ncompare both transition directions and power with the source simulation. Iterate\non measured parasitic effects rather than visual compactness alone. These are\noptional techniques, not a mandated algorithm or reference placement.\n\nAdapted from Xu et al., *Standard Cell Library Design and Optimization Methodology\nfor ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,\ntrack counts and process-specific dimensions do not apply to this task.\n\n\n### Score weights\n\nScan flip-flop: clock-to-output delay 51%; output transition 17%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `propagation_delay` | 0.510000000000 |\n| `output_transition` | 0.170000000000 |\n| `supply` | 0.170000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml","case_sha256":"fe6e95a3b09be67897fb5e30546a601dfdbf4498ebcd13ffa82f4ec00259f4ad","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md","netlist_path":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice","netlist_sha256":"659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58","license_path":"tasks/gf180mcuD/voidwalkers-scandff/LICENSE"} +{"id":"ihp-sg13g2.analog-db.adc_001_inv1b","in_core":false,"title":"CMOS Inverter Threshold Core","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Characterizes an inverter switching threshold, output swing and timing.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/adc_001_inv1b","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# CMOS Inverter Threshold Core Layout Task\n\n## Objective\n\nThe fixed binding is a CMOS inverter: one 1/0.13 um NMOS and one 2.5/0.13 um PMOS, each m=1. Bodies connect to their respective rails through native physical contacts. It provides a threshold decision core; there is no sampling, independent reference, encoding or complete ADC. Target top cell: `adc_001_inv1b`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (1.2 V rail), vin (gate input), vout (drain output), vss (return).\n\n## Operating Conditions\n\nIHP LV MOS TT, 27 C, VDD=1.2 V. Input driver impedance is 50 ohm; output capacitance is 20 fF. DC input sweeps 0–1.2 V in 1 mV steps. The transient driver starts at 0 V, rises at 10 ns, falls at 20.1 ns, has 100 ps edges and a 20 ns period. The initial DC output is high. The 31 ns run uses a maximum 1 ps step. Power is the net energy from supply and input driver divided by the 10–30 ns window.\n\n## Physical Requirements\n\nUse IHP native KLayout main and maximum rule decks and named-interface LVS; Magic full RC extraction. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `threshold_v` | V | Unique DC output=0.6 V crossing | unbounded to unbounded | response: target, target, scale=0.6 |\n| `delay_s` | s | Worst 50% input to opposite 50% output delay | 0 to unbounded | response: ratio, minimize, scale=1e-12 |\n| `transition_s` | s | Worst output 10–90% or 90–10% transition | 0 to unbounded | response: ratio, minimize, scale=1e-12 |\n| `power_w` | W | Mean net supply and input-driver power from 10–30 ns | 0 to unbounded | supply: ratio, minimize, scale=1e-12 |\n| `swing_v` | V | DC high minus low output; meaningful logic transition | 0.6 to unbounded | diagnostic / functional only |\n\nThe DC threshold is the unique output=0.6 V crossing, not a scan endpoint. Delay is the worse input 50% to opposite output 50% delay. Transition is the worse output 10–90% rise or 90–10% fall. Guards reject missing or multiple DC/transition crossings; independent audits require the intended 10–15 ns and 20–25 ns windows and correct ordering. DC high/low output uses actual endpoint samples, with a minimum 0.6 V swing establishing a meaningful logic transition. This is nominal loaded characterization, not Liberty/PVT or ADC accuracy.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 120 um2 = 20 um2 NMOS contact envelope + 30 um2 PMOS/well envelope + 20 um2 body-contact/isolation allowance + 50 um2 routing. These envelopes follow the fixed widths and contact/isolation needs, not the witness bounding box. Coefficient 1: a single logic stage with loaded transitions and connectivity. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nInverter threshold element: switching threshold 25.5%; delay 34%; transition 12.8%; power 12.8%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `threshold_v` | 0.255000000000 |\n| `delay_s` | 0.340000000000 |\n| `transition_s` | 0.127500000000 |\n| `power_w` | 0.127500000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml","case_sha256":"15a45dfb0015daf6001fe5b5ef6f14c368245cfcfca8bed74fbf773f49575cb4","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl","netlist_sha256":"ac17dacdee7c373b47d4038a7318a7b0fedc024031b06f93011f8eaab684caf4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_001_5t","in_core":false,"title":"Five-Transistor OTA Core with Bias Mirror","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies a differential input using an NMOS pair, PMOS mirror load and a separate bias reference.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_001_5t","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Five-Transistor OTA Core with Bias Mirror Layout Task\n\n## Objective\n\nImplement the fixed six-MOS `amp_001_5t` circuit in IHP SG13G2 and submit a\nself-contained GDS. The circuit consists of a five-transistor OTA core and a\nsixth, diode-connected bias-reference MOS. Device dimensions are fixed.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is authoritative for physical LVS;\n`materials/circuit.spice` is its simulator representation.\n`materials/testbench.spice` defines the AC/DC measurements. Port order is\n`vdd vout vinp vinn ibias vss`: supply, single-ended output, non-inverting input,\ninverting input, reference-current input, and return. Supply 20 uA from `vdd`\ninto `ibias`; it is not an ideal voltage-bias input.\n\nThe NMOS input pair has W/L = 10/10 um; the PMOS mirror pair 10/7 um;\nthe NMOS tail and reference devices 3.8/1 um, all with multiplicity 1.\nThe CDL also declares substrate and well taps. Retain all electrical connections,\nbody connections, sizes and tap devices. Placement and routing are free; normal\nsource/drain equivalence and electrically equivalent device splitting are allowed\nonly when the declared LVS checks accept them. No additional common-centroid or\nstatistical matching requirement is scored.\n\n## Operating Conditions\n\nThe pinned `mos_tt`/`res_typ` models run at 27 C, with VDD = 1.5 V, VSS = 0 V,\n20 uA reference current, 0.8 V non-inverting input bias, and an external 10 pF\noutput load. The 4 GH/4 GF feedback network closes the DC loop and opens the AC\nloop. It is testbench apparatus, not part of the submitted layout. AC sweeps\n1 Hz to 100 MHz at 100 points per decade. The power measurement includes the\nreference-current branch supplied from VDD. The 1e12 ohm numerical shunt is\npart of the declared simulation setup.\n\n## Physical Requirements\n\nSubmit top cell `amp_001_5t`, with all six named electrical ports, no unresolved\nhierarchy, and at most 10 MiB. Artifact, DRC, strict named-port LVS and geometry\nchecks must pass. DRC uses the pinned main and extra/maximal rules without\nwaivers; density and antenna are outside this standalone-block scope.\n\nThe functional bounding box must fit within 120 by 70 um. Its area includes all\nprocess device and routing drawing layers enumerated in the published runtime\nconstraints, including wells, taps, implants, active, poly, contacts, all routing\nmetals/vias and passive/device markers. Annotation text and pin-purpose shapes\nare excluded from area; functional routing must use drawing layers.\n\nThe judge extracts distributed RC from the submitted GDS and simulates that\nextracted DUT. Physical LVS retains explicit taps. Magic models the body\nconnection through its extracted network without the separate compact `ptap1`\nand `ntap1` devices; source calibration records the effect of this boundary.\nThis task covers nominal deterministic AC/DC behavior, not statistical mismatch,\nPVT, noise, distortion, transient settling, EM or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vinp)-v(vinn))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vinp)-v(vinn)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin` | AC: `180+(find (180*cph((v(vout)/(v(vinp)-v(vinn))))/pi) when (db((v(vout)/(v(vinp)-v(vinn)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `bias_voltage` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **1198.35 um2**. 8 expanded device instances; sum of device/contact envelopes 754.0020 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `low_frequency_gain` | 0.270000000000 |\n| `unity_gain_bandwidth` | 0.225000000000 |\n| `phase_margin` | 0.225000000000 |\n| `bias_voltage` | 0.022500000000 |\n| `output_bias` | 0.022500000000 |\n| `supply_power` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed IHP PDK/EDA resources exposed through `/protocol/resources.json`;\nKLayout and Magic support layout checking and extraction, and ngspice supports\nsimulation. `/protocol/task.json` provides the frozen constraints and evaluation\nrequirements; `/protocol/harness.json` describes the active harness.\nIf `process-feedback` is exposed, use its published helper for interim checks.\nWrite `/workspace/output/final.gds`, then explicitly submit it with\n`python -I /protocol/submit.py`. The final judge evaluates the submitted snapshot.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml","case_sha256":"dde3348d36bcf3ff96a8c0ae663883f63be4bf2ddf5cefed06e059520f2ca531","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/circuit.cdl","netlist_sha256":"55016e668fdcbc3087c98af6d92f196225fd586da3a9a8e049200fd0419c119f","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_002_alfio_raffc","in_core":false,"title":"Current-Buffer and Active-Feedforward OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with current-buffered compensation and an active feedforward path to the output.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_002_alfio_raffc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Current-Buffer and Active-Feedforward OTA Layout Task\n\n## Objective\n\nLay out `amp_002_alfio_raffc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS common-source stage\ndrives `net013`, then a PMOS stage and NMOS mirror at `net043` drive the\noutput NMOS. An active feedforward path drives the output PMOS directly\nfrom `net050`. One capacitor connects output to `net063`, the source side\nof the first-stage NMOS cascode; the second connects `net050` to `net013`.\nThe current-buffer compensation terminal and the additional active path\nare real connection differences from the dual-capacitor and shared-resistor\nrepresentatives. This case is not counted from a changed circuit name or size.\n\nThe maintained circuit retains all 24 source MOS groups as 89 physical\nfingers, 4 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. The original W=18/20/30 um devices use 2×9/2×10/3×10 um parallel fingers; the resulting short-width model behavior is calibrated independently.\nThe source's 14.3293 uA sink is external through `net1`. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net1`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net1`\nconnects the external 14.3293 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net063` → `vout`, 3 parallel `cap_cmim` unit(s), each 43.46 × 43.46 um; nominal total 8.520333 pF.\n- `c1`: `net050` → `net013`, 1 parallel `cap_cmim` unit(s), each 36.515 × 36.515 um; nominal total 2.0058602 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_002_alfio_raffc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 1500 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **20690.01 um2**. 96 expanded device instances; sum of device/contact envelopes 13605.7469 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml","case_sha256":"7677b61845c2e61f53047c9ea7b71153fd50135ccc327cf8e9fb62c41d98dbce","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/circuit.cdl","netlist_sha256":"da8813082f4c6fb73b07d677efa730e1f1c250c9ebd438233f3f725346ac88f9","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_003_fan_smc","in_core":false,"title":"Single-Capacitor Three-Stage Feedforward OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with a single compensation capacitor and active feedforward.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_003_fan_smc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Single-Capacitor Three-Stage Feedforward OTA Layout Task\n\n## Objective\n\nLay out `amp_003_fan_smc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; the PMOS stage at `net043`\nand its NMOS mirror drive `net049`, which controls the NMOS output device.\nAn active feedforward path drives the output PMOS directly from `net050`.\nA single physical capacitor branch connects `net050` to output. This is the\nsingle-capacitor representative: there is no second `net049` capacitor or\nseries nulling resistor. The large retained mirror multiplicities and coupled\nthree-stage/feedforward paths require their own loaded recovery calibration.\n\nThe maintained circuit retains all 24 source MOS groups as 412 physical\nfingers, 2 MIM units and 0 high-poly segments. All MOS dimensions/multiplicities are retained exactly.\nThe maintained 3 uA sink is external through `net013`.\nThe source value was 60 uA; the maintained 3 uA bias is a deliberate headroom calibration, not an unchanged upstream operating point. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 3 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `vout`, 2 parallel `cap_cmim` unit(s), each 40.825 × 40.825 um; nominal total 5.0131059 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_003_fan_smc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 2800 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **20940.39 um2**. 417 expanded device instances; sum of device/contact envelopes 13771.5365 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml","case_sha256":"0b4b04cb2457d60b37725c6f3a041541f36de8c315917b83f22d3ae3cddf0460","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/circuit.cdl","netlist_sha256":"5c0aa44f171b64424a7dc717a4d76f332bc9da6b39923f4ae527433622c43601","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_005_hoilee_affc","in_core":false,"title":"Current-Buffered Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a folded input stage and two current-buffered compensation paths.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_005_hoilee_affc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Current-Buffered Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_005_hoilee_affc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS/diode/mirror stage\ndrives `net049`, followed by the NMOS output stage. A parallel path drives\nthe output PMOS directly from `net050`. One capacitor connects `net049` to\noutput. The other connects output to `net1`, the source terminal of an\nadditional common-gate NMOS returning current to `net050`. Six additional\nMOS (XM59–XM64) form this biased current-buffer branch; these devices and\nthe low-impedance compensation terminal distinguish it from direct Miller\nand shared-resistor compensation.\n\nThe maintained circuit retains all 30 source MOS groups as 276 physical\nfingers, 7 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. All source multiplicities are retained.\nThe maintained 3.15498 uA sink is external through `net013`.\nThe external bias is deliberately calibrated to 0.3 times the source current; this is not an unchanged upstream operating point. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 3.15498 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net049` → `vout`, 4 parallel `cap_cmim` unit(s), each 44.775 × 44.775 um; nominal total 12.05746 pF.\n- `c1`: `vout` → `net1`, 3 parallel `cap_cmim` unit(s), each 49.965 × 49.965 um; nominal total 11.258239 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_005_hoilee_affc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 3300 × 140 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **42066.41 um2**. 286 expanded device instances; sum of device/contact envelopes 27776.6506 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml","case_sha256":"bb422bdb3dbdea32fa479906b6aa1c05a91d351148a8dd5dbd10ab10b5d606f6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/materials/circuit.cdl","netlist_sha256":"d16b4edb2bff902499a0519b595961ad69cf940221b11f12a423ef2863685757","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_006_leung_dfcfc1","in_core":false,"title":"Output-Controlled Auxiliary Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with dual compensation paths and an output-controlled auxiliary stage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_006_leung_dfcfc1","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Output-Controlled Auxiliary Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_006_leung_dfcfc1`, retaining the complete folded PMOS-input stage,\nthree-stage signal path, direct output feedforward, and auxiliary compensation.\nThe folded stage drives `net050`, which drives the output PMOS and the\nPMOS/diode/mirror path to `net049`. That node drives both the output NMOS\nand an auxiliary common-source NMOS whose drain is `net1`; a biased PMOS\nloads this auxiliary drain. C0 connects `net050` to output, while C1 connects\n`net049` to `net1`. The auxiliary branch therefore acts on the NMOS output\ncontrol node. In contrast, the separate AMP007 case's auxiliary PMOS senses\n`net050` and its compensation terminates at `net2`.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical device graph.\n- `materials/circuit.spice`: matching simulator representation with finite taps.\n- `materials/testbench.spice`: public bias, bilateral AC and step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD supply,\nVINN/VINP the inverting/noninverting inputs, VOUT output, and `net013` the\nexternal bias-sink connection. Input PMOS bodies connect to the separate\n`net31` source-tied well; other PMOS use the VDD well and NMOS use the VSS\nsubstrate contact. Preserve all 26 MOS groups, 675 physical fingers, W/L/m,\nbody connections, and both internal capacitive branches. Native equivalent\nparallel fingering is allowed only when all physical and electrical checks pass.\n\nThe maintained MOS dimensions are rounded to the actual 10 nm PyCell grid;\nthe 1,413 rounded source fingers are regrouped within their original MOS\ngroups using integer factors, with <=10 um single width. Each group retains\nexactly its rounded total W and L; individual W/m and diffusion perimeter\nchange. Every body connection remains intact. Distributed 2 x 2 um body\ncontacts at <=20 um pitch replace continuous tap strips. All capacitors are physical `cap_cmim`:\n\n- `c0`: `net050` (top plate) to `vout` (bottom plate), 8 parallel 48.935 × 48.935 um MIM units.\n- `c1`: `net049` (top plate) to `net1` (bottom plate), 3 parallel 50.94 × 50.94 um MIM units.\n\nThese are internal compensation devices, distinct from the external load.\nThe normalized source's 27.4754 uA bias is deliberately calibrated to\n6.86885 uA, improving headroom and finite tracking at the declared signal\nlevels. No ideal output servo or internal numerical damping element is added.\n\n## Operating Conditions\n\nUse typical IHP LV MOS/MIM/poly models at 27 C and VDD=1.2 V, with an external\n6.86885 uA sink from `net013` to VSS. Every combination of 5/10/20 pF output\nload and 0.5/0.7 V DC input must pass. A zero-volt source from VINN (`vm`) to\nVOUT closes unity feedback. VINP is AC ground. The two DC input levels\nindependently check operating-point error and the complete sampled return ratio.\n\nAt the closed input/output boundary, inject a series AC voltage with zero\nparallel AC current, then zero series voltage and unit current into `vm`.\nBoth injections retain the original circuit and loading. With first-run\n`b=-I(VPROBE)`, `d=V(vm)` and second-run `a=-I(VPROBE)`, `c=V(vm)`, define\n`delta=a*d-b*c` and the bilateral return ratio\n`T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian et al., Eq. 30).\nThe deck exports both injections' voltages/currents for independent two-port\nadmittance reconstruction. This is a finite external-loop measurement,\nnot a certificate for every internal pole or a complete Nyquist proof.\n\nSweep 0.01 Hz–10 GHz at 300 points/decade. Use continuous phase starting\non its natural low-frequency branch, without a phase-offset correction.\nCheck both first and final descending unity crossings, minimum sampled\n`abs(1+T)`, maximum absolute continuous phase of `1+T` across the entire sweep,\nand maximum gain over 2–10 GHz. Missing crossings or invalid measurements\nare evaluator errors; both first and final phase margins must lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nobservations affect continuous quality and do not establish a stability certificate.\n\nFor each condition, VINP's pulse starts at 0.5 V, rises to 0.7 V at\n2–2.02 us and falls at 10.02–10.04 us, with a 16 us period. Transient uses\nits own pulse-start operating point, independently of the AC DC-input setting.\nSimulate 0–18 us with the KLU linear solver and Gear order 2, 2 ns maximum step, `itl4=1000`,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-12`, and `vntol=1e-8`.\nThe numerical shunt is not a physical device. The maintained 1 pA absolute\ncurrent tolerance is checked at 0.1 pA with tenfold tighter relative/voltage\ntolerances and a 1e13 ohm shunt. Initial experimental 10 fA/1 fA current\ntolerances produced excessive iteration cost in the extracted low-resistance\nnetwork. This numerical-floor calibration preserves every electrical bound\nand all physical/parasitic elements; half-step and trapezoidal controls\nindependently check the observable dynamics. PVT, mismatch, noise,\ndistortion, supply startup, rail-to-rail operation and arbitrary-load stability\nare outside this contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_006_leung_dfcfc1`, at most 32 MiB. Pass native\nIHP main/maximal DRC without waivers (standalone scope, density/antenna off),\nstrict named-interface LVS with explicit taps, and a 6400 × 130 um functional\nenvelope. Every device/contact/interconnect drawing layer listed in the\nruntime `outline` constraint contributes to area; annotation/pin-purpose\nlayers do not. Labels alone do not establish electrical connectivity.\n\nPost-layout simulation uses the submitted GDS's complete Magic RC, with\nphysical MIM devices and interconnect resistances/capacitances. Half-grid\nimport is explicit. Magic retains only Metal3 interface labels in its isolated\nextraction copy to avoid repeated internal well-name aliases, while native LVS\nchecks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics.\nMagic idealizes well/substrate taps, whereas source simulation uses finite\nphysical tap models. Distributed substrate resistance/noise and fabrication\nsignoff remain unqualified. The long independent witness is a feasibility\nlayout, not an area optimum.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_error_v` | DC operating point: `abs(v(vout)-v(vp))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 10g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 10g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=2g to=10g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **82915.92 um2**. 1164 expanded device instances; sum of device/contact envelopes 54901.4182 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nMultiple-crossing feedback amplifiers: loaded recovery 28.6%; loop stability 24.5%; gain and bandwidth 12.3%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `output_error_v` | 0.095454545449 |\n| `recovery_down_v` | 0.095454545455 |\n| `recovery_up_v` | 0.095454545455 |\n| `final_phase_margin_deg` | 0.061363636364 |\n| `minimum_return_distance` | 0.061363636364 |\n| `phase_margin_deg` | 0.061363636364 |\n| `return_phase_excursion_deg` | 0.061363636364 |\n| `dc_gain_db` | 0.030681818182 |\n| `final_unity_hz` | 0.030681818182 |\n| `hf_gain_db` | 0.030681818182 |\n| `unity_hz` | 0.030681818182 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied\nIHP primitives with KLayout, Magic and ngspice. Write\n`/workspace/output/final.gds` and explicitly submit via the harness protocol.\nHost configuration, source records and reference answers are outside solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml","case_sha256":"f1fc328337ea9dc61bf86ec17f7c68052f869111bd9fbd3f03aeaac87f89969b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl","netlist_sha256":"0bfae437fa4eb43463b0ddab03b7d1c9edbe3d7f08fde84a418d30cb3cc137b2","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_007_leung_dfcfc2","in_core":false,"title":"Auxiliary-Stage Miller Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with active feedforward and a separate auxiliary Miller-compensation stage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_007_leung_dfcfc2","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Auxiliary-Stage Miller Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_007_leung_dfcfc2` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; the PMOS/diode/mirror path\ndrives `net049` and then the NMOS output stage. Direct feedforward drives\nthe output PMOS from `net050`. A separate PMOS common-source branch has\ngate `net050`, drain `net2` and an NMOS bias sink. C1 connects `net050` to\noutput; C2 connects `net050` to `net2`, across the auxiliary stage. This\ncompensation branch is distinct from output-to-current-buffer injection and\nfrom the `net049`-controlled auxiliary termination in the other cases.\n\nThe maintained circuit retains all 26 source MOS groups as 440 physical\nfingers, 10 MIM units and 0 high-poly segments. All MOS dimensions/multiplicities are retained exactly.\nThe maintained 20 uA sink is external through `net1`.\nThe source bias-current value is retained. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net1`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net1`\nconnects the external 20 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c1`: `net050` → `vout`, 5 parallel `cap_cmim` unit(s), each 47.61 × 47.61 um; nominal total 17.038429 pF.\n- `c2`: `net050` → `net2`, 5 parallel `cap_cmim` unit(s), each 47.61 × 47.61 um; nominal total 17.038429 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\nThe transient nonlinear iteration ceiling is explicitly `itl4=1000`, with\nunchanged accuracy tolerances. This allows the retained high-multiplicity\nmirror/auxiliary network to converge; it is not a relaxed acceptance limit.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_007_leung_dfcfc2`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 3500 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **52764.97 um2**. 453 expanded device instances; sum of device/contact envelopes 34876.8788 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml","case_sha256":"d13548cc4035967c3e16d35c71b714287fecd68580111da54af663c47ef9733b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/materials/circuit.cdl","netlist_sha256":"3e1d203a196d5cf5f13d15a6c347fcf8c2a907ccddd8b352a845f0fbeff664c0","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_008_leung_nmcf","in_core":false,"title":"Dual-Capacitor Three-Stage OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with two compensation capacitors and output feedforward.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_008_leung_nmcf","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Dual-Capacitor Three-Stage OTA Layout Task\n\n## Objective\n\nLay out `amp_008_leung_nmcf` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS stage at `net043`\nand its NMOS mirror drive `net049`, which controls the NMOS output device.\nA parallel feedforward path drives the output PMOS directly from `net050`.\nTwo capacitive paths connect `net050` to output and `net049` to output.\nThese couple two internal gain nodes to the load, unlike the maintained\ntwo-stage OTA's single Miller path.\n\nThe maintained circuit retains all 24 source MOS groups as 236 physical\nfingers, 3 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. All source multiplicities are retained.\nThe source's 7.52942 uA sink is external through `net013`. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 7.52942 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `vout`, 2 parallel `cap_cmim` unit(s), each 46.95 × 46.95 um; nominal total 6.6279315 pF.\n- `c1`: `net049` → `vout`, 1 parallel `cap_cmim` unit(s), each 30.75 × 30.75 um; nominal total 1.4232638 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_008_leung_nmcf`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 1700 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **17797.36 um2**. 242 expanded device instances; sum of device/contact envelopes 11690.9447 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml","case_sha256":"9a48c600d5c6530833f21513f58bb8c80c1d5562cc3024fbc0a367545c56cc61","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/materials/circuit.cdl","netlist_sha256":"8e12afdcc86858f64dc3dab7effa448ef1cb877a1c235001b3db1406d36d132a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_009_leung_nmcnr","in_core":false,"title":"Shared-Nulling-Resistor Three-Stage OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages whose compensation capacitors share a nulling resistor.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_009_leung_nmcnr","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Shared-Nulling-Resistor Three-Stage OTA Layout Task\n\n## Objective\n\nLay out `amp_009_leung_nmcnr` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; the PMOS stage at `net043`\nand its NMOS mirror drive `net049`, which controls the NMOS output device.\nThe output PMOS gate connects to the bias mirror, not to `net050`.\nTwo capacitors connect `net050` and `net049` to a common `net044` node;\na physical high-poly resistor connects that junction to output. The shared\nresistance and bias-controlled output PMOS distinguish this circuit from\nboth the dual-capacitor feedforward OTA and the two-stage series-R/C OTA.\n\nThe maintained circuit retains all 24 source MOS groups as 272 physical\nfingers, 3 MIM units and 1 high-poly segments. All MOS dimensions/multiplicities are retained exactly.\nThe source's 3 uA sink is external through `net013`. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 3 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `net044`, 2 parallel `cap_cmim` unit(s), each 40.825 × 40.825 um; nominal total 5.0131059 pF.\n- `c1`: `net044` → `net049`, 1 parallel `cap_cmim` unit(s), each 44.72 × 44.72 um; nominal total 3.0069728 pF.\n- `r0`: `net044` → `vout`, 1 series `rhigh` segment(s), each W=1 um / L=6.94 um, m=1 and b=0; body through the VSS substrate tap.\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_009_leung_nmcnr`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 2050 × 330 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **18158.97 um2**. 279 expanded device instances; sum of device/contact envelopes 11930.2526 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml","case_sha256":"6e86a09e63e8fc29cefd2776238309c67d68befb9547f4bb8fb7c0b1f9cccd67","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/materials/circuit.cdl","netlist_sha256":"68c55b7866f4dd6640069867385394c0ed2c9b8c026a215df0b2dd381faab6ef","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_010_peng_acbc","in_core":false,"title":"Auxiliary-Branch Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with feedforward and a compensated auxiliary branch.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_010_peng_acbc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Auxiliary-Branch Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_010_peng_acbc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS/diode/mirror stage\ndrives `net049`, followed by the NMOS output stage. The output PMOS also\nreceives feedforward drive from `net050`. C0 connects `net050` to output,\nwhile C1 connects `net049` to `net1`. The auxiliary node has a bias-fed PMOS,\na diode-connected PMOS and an NMOS controlled by `net043`; this three-device\nbranch creates a distinct active compensation termination. It is neither a\nsecond output-connected Miller capacitor nor the six-MOS current-buffer\nbranch of the other representative.\n\nThe maintained circuit retains all 27 source MOS groups as 237 physical\nfingers, 6 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. All source multiplicities are retained.\nThe maintained 1.80825 uA sink is external through `net013`.\nThe external bias is deliberately calibrated to 0.1 times the source current; this is not an unchanged upstream operating point. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 1.80825 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `vout`, 4 parallel `cap_cmim` unit(s), each 50.405 × 50.405 um; nominal total 15.276243 pF.\n- `c1`: `net049` → `net1`, 2 parallel `cap_cmim` unit(s), each 38.31 × 38.31 um; nominal total 4.4152275 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 20–20.1 us and falls at 100.1–100.2 us, repeating\nevery 160 us. Simulate 0–180 us with Gear order 2, 10 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_010_peng_acbc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 2100 × 140 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=50u to=95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=130u to=175u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=90u to=95u)-(avg v(vout) from=170u to=175u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=20u to=180u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=20u to=100u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=100.2u to=180u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **32926.15 um2**. 246 expanded device instances; sum of device/contact envelopes 21714.0299 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml","case_sha256":"7f37a4c2c0a3922d3b837b9535a5a4e4ff68c0fb822cb09216d32f609b622343","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/materials/circuit.cdl","netlist_sha256":"e8fcd5473160b4dd336813dfb86122e023e06285c6878100e717abe9a4f6aa6f","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_011_peng_iac","in_core":false,"title":"Peng IAC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with cascoded bias and auxiliary current paths.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_011_peng_iac","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Peng IAC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_011_peng_iac` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded branches feed voutn/voutp. The PMOS bias mirror is cascoded with vb2, generated by XM65/XM63/XM64. XM10 drives net043; XM67/XM68 and XM70 retain the auxiliary current path, with XM69 driving net10 against XM66. XM11/XM23 drive vout. Compensation retains 1.95593 pF between voutp and vout, and 4.33595 pF between net10 and net4 with 1.46466 Mohm from net4 to vss.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 505 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout vb1`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `vb1`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nIHP SG13G2, nominal TT/typical, 27 C, supply 1.5 V, input reference 0.24 V,\nexternal current sink 7.11568e-07 A to vss, and 10 pF output load. Use the fixed IHP LV binding at 1.5 V, adapting the authored 1.8 V stimulus to the LV process rail; retain its bias current and input reference. Round W/L to 10 nm so half-gate contacts remain on grid.\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 2 us (100 ns rise/fall, 18 us high duration), and runs to 40 us with\n2 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nA disconnected timing marker forces exact integration-window endpoints.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 15–20 and 35–40 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 GH inductor and AC-isolates its bias node with 1 kF to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. Both decks use rshunt=1e12 ohm to regularize\notherwise floating extracted nodes; this numerical conductance is applied equally\nto source and candidate and is not a DUT compensation branch. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_011_peng_iac`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nIHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.5 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 2–40 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.5 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=30926.75 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 1.5 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1360 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 8: Active auxiliary current feedback, cascoded bias, and two interacting compensation paths affect finite-window recovery and frequency response.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed IHP SG13G2 resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml","case_sha256":"6a3084040055da18f94c36d2e394ba1614007d8a14df2d9367223caa7eda2e70","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl","netlist_sha256":"3d202284343734913c74c1436446a7dab16631757da8c617aaae8e6f67a2db15","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_012_peng_tcfc","in_core":false,"title":"Auxiliary Source-Driven Output-Control OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a folded input stage and an auxiliary source-driven output-control path.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_012_peng_tcfc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Auxiliary Source-Driven Output-Control OTA Layout Task\n\n## Objective\n\nLay out `amp_012_peng_tcfc` with its complete transistor signal and bias paths.\nThe PMOS-input folded stage produces `voutp`, driving the output PMOS and\n`net043` branch. The large PMOS path through `net049` feeds `net10`, while\n`net043` controls its NMOS pulldown. `net10` drives the output NMOS. Preserve\nboth original compensation branches and the added local output-control MIM.\nUnlike a direct `net050/net049` output stage, this circuit includes the\nsource-driven auxiliary PMOS and a separate `net10` control node.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical graph.\n- `materials/circuit.spice`: equivalent simulator graph with finite body taps.\n- `materials/testbench.spice`: DC, bilateral-loop and sustained-step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout vb1`. VSS/VDD are return/supply;\nVINN/VINP are inverting/noninverting inputs; VOUT is output; `vb1`\nconnects to the external bias sink. Input PMOS bodies use the separate\n`net31` source-tied well; other PMOS use VDD and NMOS use the VSS substrate.\nPreserve all 32 MOS groups, 108 physical fingers,\nW/L/m, every body connection and all physical passive devices.\n\nMOS dimensions are rounded to the 10 nm physical grid. Parallel regrouping\nwithin each original group preserves its rounded total W and L, with at most\n10 um single-finger width; individual width/multiplicity and diffusion perimeter\nchange. Distributed 2 × 2 um body contacts have at most 20 um pitch.\nAll internal capacitors use `cap_cmim`:\n\n- `c0`: `voutp` (top) to `vout` (bottom), 1 parallel 35.325 × 35.325 um MIM units.\n- `c1`: `net049` (top) to `vout` (bottom), 1 parallel 41.2 × 41.2 um MIM units.\n- `clocal`: `net10` (top) to `vout` (bottom), 1 parallel 51.64 × 51.64 um MIM units.\n\nThe raw 1.29849 uA sink is calibrated to 0.16231125 uA. A real approximately\n4 pF `net10–vout` MIM is added to suppress the internal output-control\noscillation. Both original 1.87196 pF `voutp–vout` and 2.54606 pF\n`net049–vout` branches remain. There is no added output-to-ground capacitor.\nNo ideal servo, diagnostic clamp or hidden damping element is part of this DUT.\n\n## Operating Conditions\n\nUse typical IHP LV MOS/MIM/poly models at 27 C and VDD=1.2 V, with a\n0.162311 uA sink from `vb1` to VSS. All combinations of external\n5/10/15 pF load and 0.5/0.7 V DC input must pass. These external loads are\nadditional to every internal capacitor above.\n\nA zero-volt source connects VINN (`vm`) to VOUT. VINP is AC ground.\nUse series voltage and parallel current injection at that boundary, retaining\nthe complete DUT and loading. With voltage-injection `b=-I(VPROBE)`,\n`d=V(vm)` and current-injection `a=-I(VPROBE)`, `c=V(vm)`, set\n`delta=a*d-b*c` and `T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian Eq. 30).\nBoth raw injections are exported for independent Y-matrix reconstruction.\nSweep 0.01 Hz–10 GHz at 300 points/decade. Continuous phase uses its natural\nlow-frequency branch without an offset correction. Check first and final\ndescending unity crossings, minimum sampled `abs(1+T)`, maximum absolute\ncontinuous phase of `1+T` across the entire sweep, and gain over 2–10 GHz.\nA good first crossover alone cannot establish acceptance.\n\nVINP pulses 0.5→0.7→0.5 V with 20 ns edges, rising at 2 us and falling\nat 20.02 us, period 100 us. Transient starts at its own pulse-start operating\npoint, independently of the AC DC-input setting. Simulate 0–40 us with Gear2,\n2 ns maximum step, KLU, `itl4=1000`, `rshunt=1e12`, `reltol=1e-5`,\n`abstol=1e-12`, `vntol=1e-8`. The numerical shunt is not a physical device.\nQualification also checks half step, tighter tolerances/dense AC, trapezoidal\nintegration, long tails and finite stimulus/load boundaries.\nThese are finite external-loop and observable-recovery requirements, not an\ninternal pole inventory, arbitrary-load stability, PVT, noise, mismatch,\ndistortion, rail-to-rail behavior or supply-startup qualification.\n\nFirst and final crossing phase margins must both lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nmetrics affect continuous quality without adding a stability acceptance screen.\nMissing crossings or invalid observations are evaluator errors.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_012_peng_tcfc`, at most 32 MiB. Native IHP main/maximal DRC\nmust pass without waivers (standalone scope, density/antenna off), together\nwith strict named-interface LVS and a 1400 × 160 um functional envelope.\nAll device/contact/interconnect drawing layers in the runtime `outline`\nconstraint contribute to area; annotation/pin-purpose layers do not.\nPost-layout simulation uses the submitted GDS's complete Magic RC, with\nphysical MIM devices and interconnect resistances/capacitances. Half-grid\nimport is explicit. Magic retains only Metal3 interface labels in its isolated\nextraction copy to avoid repeated internal well-name aliases, while native LVS\nchecks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics.\nMagic idealizes well/substrate taps, whereas source simulation uses finite\nphysical tap models. Distributed substrate resistance/noise and fabrication\nsignoff remain unqualified. The long independent witness is a feasibility\nlayout, not an area optimum.\n\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_error_v` | DC operating point: `abs(v(vout)-v(vp))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | bias |\n| `bias_v` | DC operating point: `v(vb1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 10g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 10g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=2g to=10g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=15u to=19u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=30u to=39u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=18u to=19u)-(avg v(vout) from=38u to=39u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=40u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=20u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=20.04u to=40u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **14710.04 um2**. 180 expanded device instances; sum of device/contact envelopes 9648.5648 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nMultiple-crossing feedback amplifiers: loaded recovery 28.6%; loop stability 24.5%; gain and bandwidth 12.3%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `output_error_v` | 0.095454545449 |\n| `recovery_down_v` | 0.095454545455 |\n| `recovery_up_v` | 0.095454545455 |\n| `final_phase_margin_deg` | 0.061363636364 |\n| `minimum_return_distance` | 0.061363636364 |\n| `phase_margin_deg` | 0.061363636364 |\n| `return_phase_excursion_deg` | 0.061363636364 |\n| `dc_gain_db` | 0.030681818182 |\n| `final_unity_hz` | 0.030681818182 |\n| `hf_gain_db` | 0.030681818182 |\n| `unity_hz` | 0.030681818182 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Host configuration, source records\nand reference answers remain outside solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml","case_sha256":"207646009d3117d253c8f92935ff90e4e7fe6c555f6729a251f59252b9cf5237","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl","netlist_sha256":"5d1695a711afd0ce2ecc5a85c10c5c4cb632b5771cc6b7963d4993e28a1edba9","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_013_qu2017_azc","in_core":false,"title":"Qu AZC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through a three-stage network with auxiliary output-control branches.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_013_qu2017_azc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Qu AZC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_013_qu2017_azc` without changing the declared circuit. XM9/XM10 form the PMOS input pair with their bodies tied to the common source net019. XM14–XM17 form the active NMOS load around DM_2/net063; XM4/XM5 convert this to net050. XM11 drives net094 and XM12 with the XM6/XM7 mirror drives net057. XM23/XM24 drive net049; XM13/XM18 drive VOUT. The active compensation retains C0 (net063–VOUT), C1 (net051–vss), C2 (net043–vss), both resistors from net078 to net077/net082, and both resistors from net057 to net051/net043. The entire bias tree and all body relationships remain.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vss vdd vinn vinp vout vb1`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nThe integer-micrometre MOS dimensions are unchanged. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.5 V supply, 0.3 V input reference, 10 pF output load. The external current sink is i0 vb1 vss 1e-06. A direct unity follower receives a 100 mV step at 2 us with 100 ns edges and 8 us high width; falling starts at 10.1 us and completes at 10.2 us. Observe 0–20 us with 0.5 ns maximum step. Report high-window statistics at 8–10 us and return-window statistics at 18–20 us, not a settling time. The rail is adapted from the authored 1.8 V analysis to the actual IHP LV binding; no transistor sizing campaign is performed.\n\nThe transient deck directly connects vinn to vout. The frequency deck closes DC feedback through 1 TH, shunts its remote end by 1 F and injects +0.5/−0.5 V AC at the inputs. This isolates the DC feedback at every measured AC frequency. Residual AC common mode and DC feedback mismatch must each be at most 1 uV; open gain is never inferred from a nearly zero closed-loop input error.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e12 (1 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 10 TOhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_013_qu2017_azc`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `output_v` | V | DC follower output | bias; target |\n| `power_w` | W | DC rail power, -VDD*I(VDD); external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `late_error_v` | V | Mean absolute follower tracking error, 8–10 us | response; ratio; 0 ≤ value |\n| `return_error_v` | V | Mean absolute follower tracking error, 18–20 us | response; ratio; 0 ≤ value |\n| `ripple_v` | V | Full output peak-to-peak range, 8–10 us | response; ratio; 0 ≤ value |\n| `return_ripple_v` | V | Full output peak-to-peak range, 18–20 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted rail power over 2–20 us; external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `bias_v` | V | External current-bias port DC voltage | diagnostic; unscored |\n| `high_v` | V | Mean follower output, 8–10 us | diagnostic; unscored |\n| `low_v` | V | Mean follower output, 18–20 us | diagnostic; unscored |\n| `output_min_v` | V | Minimum output over 0–20 us | diagnostic; unscored |\n| `output_max_v` | V | Maximum output over 0–20 us | diagnostic; unscored |\n| `fixture_cm_max` | V | Residual common-mode excitation in the differential AC fixture | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | DC voltage mismatch across the external feedback inductor | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\nDC bias, 1 Hz/10 kHz differential gain, 10 kHz closed response, tracking error, output range and rail power are distinct observations.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 8079.11 um2 / functional area. The bias scale is 1.5 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 1 mV (1% of the 100 mV step); power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 8 reflects multistage analog routing, active compensation/body connectivity and physical passive matching.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml","case_sha256":"b94ea2bb1b84e7949c8d3f8259e9c11efef6cf4cceacf67eec120736b7961491","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl","netlist_sha256":"482f6b9455334bd331c08b6de22220b5256182a28ee463283da40ab2867df6a6","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_014_ramos_pfc","in_core":false,"title":"Ramos PFC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through a cascoded input and mirror stages into a single-ended output.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_014_ramos_pfc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Ramos PFC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_014_ramos_pfc` with the supplied fixed topology and dimensions. The PMOS input pair drives the cascoded NMOS branches at dm_2/net063; the voutn mirror produces net050. XM10 and the XM21/XM22 mirror drive net049, while XM11/XM23 drive the single-ended output. Both compensation paths remain: 63 pF from net050 to vout and 25 pF from net050 to net049. The vb3/vb4 bias network is retained.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 2583 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout net1`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net1`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nIHP SG13G2, nominal TT/typical, 27 C, supply 1.5 V, input reference 0.4 V,\nexternal current sink 2.4e-05 A to vss, and 10 pF output load. Use the fixed IHP LV binding at 1.5 V, adapting the authored 1.8 V stimulus to the LV process rail; retain its bias current and input reference. Round W/L to 5 nm (the supplied integer-micrometre sizes are unchanged).\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 20 us (100 ns rise/fall, 80 us high duration), and runs to 200 us with\n10 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 80–100 and 180–200 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_014_ramos_pfc`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nIHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.5 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 20–200 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.5 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=190064.1 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 1.5 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1360 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 7: Multistage compensation couples the first-stage node, current-inversion path and output response.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed IHP SG13G2 resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml","case_sha256":"00752bcb24eae77fe9856f4c5f9fbebff3f02938dcb5a2c4f35567c917e1c378","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl","netlist_sha256":"397c4c086e2c70372a03c3e1e0be1323519379a0f9ea38be34814434aff0122c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_015_sau_cfcc","in_core":false,"title":"Input-Driven Active-Feedforward OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a folded input stage and direct input-driven active feedforward.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_015_sau_cfcc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Input-Driven Active-Feedforward OTA Layout Task\n\n## Objective\n\nLay out `amp_015_sau_cfcc` with its complete transistor signal and bias paths.\nThe PMOS-input folded stage produces `voutn`, controlling the mirror at\n`net050` and the auxiliary PMOS at `net049`. The `net050 → net043 → net049`\npath and direct input-driven PMOS feedforward jointly drive the output\nPMOS/NMOS at `net050/net049`. Preserve the original `net063–vout` compensation\nand both explicitly added physical capacitor arrays.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical graph.\n- `materials/circuit.spice`: equivalent simulator graph with finite body taps.\n- `materials/testbench.spice`: DC, bilateral-loop and sustained-step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS/VDD are return/supply;\nVINN/VINP are inverting/noninverting inputs; VOUT is output; `net013`\nconnects to the external bias sink. Input PMOS bodies use the separate\n`net31` source-tied well; other PMOS use VDD and NMOS use the VSS substrate.\nPreserve all 24 MOS groups, 225 physical fingers,\nW/L/m, every body connection and all physical passive devices.\n\nMOS dimensions are rounded to the 10 nm physical grid. Parallel regrouping\nwithin each original group preserves its rounded total W and L, with at most\n10 um single-finger width; individual width/multiplicity and diffusion perimeter\nchange. Distributed 2 × 2 um body contacts have at most 20 um pitch.\nAll internal capacitors use `cap_cmim`:\n\n- `c0`: `net063` (top) to `vout` (bottom), 1 parallel 51.3 × 51.3 um MIM units.\n- `clocal`: `net050` (top) to `vout` (bottom), 4 parallel 51.64 × 51.64 um MIM units.\n- `cout`: `vout` (top) to `vss` (bottom), 12 parallel 51.64 × 51.64 um MIM units.\n\nThe raw 10.0474 uA sink is calibrated to 1.255925 uA. The original\n3.94789 pF `net063–vout` compensation remains. Approximately 16 pF is added\nat `net050–vout` and another 48 pF at `vout–vss`. These are physical\ncompensation/output-storage devices, included in the netlist, area and\nextracted simulation. This maintained circuit is explicitly not capless.\nNo ideal servo, diagnostic clamp or hidden damping element is part of this DUT.\n\n## Operating Conditions\n\nUse typical IHP LV MOS/MIM/poly models at 27 C and VDD=1.2 V, with a\n1.25592 uA sink from `net013` to VSS. All combinations of external\n5/10/15 pF load and 0.5/0.7 V DC input must pass. These external loads are\nadditional to every internal capacitor above.\n\nA zero-volt source connects VINN (`vm`) to VOUT. VINP is AC ground.\nUse series voltage and parallel current injection at that boundary, retaining\nthe complete DUT and loading. With voltage-injection `b=-I(VPROBE)`,\n`d=V(vm)` and current-injection `a=-I(VPROBE)`, `c=V(vm)`, set\n`delta=a*d-b*c` and `T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian Eq. 30).\nBoth raw injections are exported for independent Y-matrix reconstruction.\nSweep 0.01 Hz–10 GHz at 300 points/decade. Continuous phase uses its natural\nlow-frequency branch without an offset correction. Check first and final\ndescending unity crossings, minimum sampled `abs(1+T)`, maximum absolute\ncontinuous phase of `1+T` across the entire sweep, and gain over 2–10 GHz.\nA good first crossover alone cannot establish acceptance.\n\nVINP pulses 0.5→0.7→0.5 V with 20 ns edges, rising at 2 us and falling\nat 20.02 us, period 100 us. Transient starts at its own pulse-start operating\npoint, independently of the AC DC-input setting. Simulate 0–40 us with Gear2,\n2 ns maximum step, KLU, `itl4=1000`, `rshunt=1e12`, `reltol=1e-5`,\n`abstol=1e-12`, `vntol=1e-8`. The numerical shunt is not a physical device.\nQualification also checks half step, tighter tolerances/dense AC, trapezoidal\nintegration, long tails and finite stimulus/load boundaries.\nThese are finite external-loop and observable-recovery requirements, not an\ninternal pole inventory, arbitrary-load stability, PVT, noise, mismatch,\ndistortion, rail-to-rail behavior or supply-startup qualification.\n\nFirst and final crossing phase margins must both lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nmetrics affect continuous quality without adding a stability acceptance screen.\nMissing crossings or invalid observations are evaluator errors.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_015_sau_cfcc`, at most 32 MiB. Native IHP main/maximal DRC\nmust pass without waivers (standalone scope, density/antenna off), together\nwith strict named-interface LVS and a 3600 × 150 um functional envelope.\nAll device/contact/interconnect drawing layers in the runtime `outline`\nconstraint contribute to area; annotation/pin-purpose layers do not.\nPost-layout simulation uses the submitted GDS's complete Magic RC, with\nphysical MIM devices and interconnect resistances/capacitances. Half-grid\nimport is explicit. Magic retains only Metal3 interface labels in its isolated\nextraction copy to avoid repeated internal well-name aliases, while native LVS\nchecks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics.\nMagic idealizes well/substrate taps, whereas source simulation uses finite\nphysical tap models. Distributed substrate resistance/noise and fabrication\nsignoff remain unqualified. The long independent witness is a feasibility\nlayout, not an area optimum.\n\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_error_v` | DC operating point: `abs(v(vout)-v(vp))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 10g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 10g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=2g to=10g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=15u to=19u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=30u to=39u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=18u to=19u)-(avg v(vout) from=38u to=39u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=40u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=20u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=20.04u to=40u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **84393.45 um2**. 364 expanded device instances; sum of device/contact envelopes 55883.1016 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nMultiple-crossing feedback amplifiers: loaded recovery 28.6%; loop stability 24.5%; gain and bandwidth 12.3%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `output_error_v` | 0.095454545449 |\n| `recovery_down_v` | 0.095454545455 |\n| `recovery_up_v` | 0.095454545455 |\n| `final_phase_margin_deg` | 0.061363636364 |\n| `minimum_return_distance` | 0.061363636364 |\n| `phase_margin_deg` | 0.061363636364 |\n| `return_phase_excursion_deg` | 0.061363636364 |\n| `dc_gain_db` | 0.030681818182 |\n| `final_unity_hz` | 0.030681818182 |\n| `hf_gain_db` | 0.030681818182 |\n| `unity_hz` | 0.030681818182 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Host configuration, source records\nand reference answers remain outside solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml","case_sha256":"9417f8541247b88cd15964c6ae5121bc7191045b9865491c9012d7387ebd2315","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl","netlist_sha256":"9934cbb25b0b85a604e0e3a453094d54a55c9ea1edfc8d66e6eb3b4fce0a0190","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_016_song_dacfc","in_core":false,"title":"Song DACFC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a primary signal path and a separately biased auxiliary input pair.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_016_song_dacfc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Song DACFC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_016_song_dacfc` with the supplied fixed topology and dimensions. The primary PMOS input pair feeds the cascoded voutn/net4 path. The separate XM57/XM58 input pair, biased by XM59, feeds net043/net049 directly; XM7 also feeds net049 from voutn. XM60/XM61 retain the main cascodes, while XM62/XM63, XM68/XM69 and XM64/XM65/XM70/XM71 retain the auxiliary net70 feedback network. XM11/XM23 drive vout. Both compensation capacitors remain: 1.5 pF from vout to net70 and 0.7 pF from net4 to vss.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 472 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout net013`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net013`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nIHP SG13G2, nominal TT/typical, 27 C, supply 1.5 V, input reference 0.3 V,\nexternal current sink 5e-06 A to vss, and 10 pF output load. Use the fixed IHP LV binding at 1.5 V, adapting the authored 1.8 V stimulus to the LV process rail; retain its bias current and input reference. Round W/L to 5 nm (the supplied integer-micrometre sizes are unchanged).\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 2 us (100 ns rise/fall, 18 us high duration), and runs to 40 us with\n2 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nA disconnected timing marker forces exact integration-window endpoints.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 15–20 and 35–40 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_016_song_dacfc`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nIHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.5 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 2–40 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.5 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=18074.4 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 1.5 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1360 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 8: An auxiliary differential feed-forward path and active net70 compensation interact with the main amplifier and output dynamics.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed IHP SG13G2 resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml","case_sha256":"3ed55b713b9b4dca398869cc7de076adb42fa553862db5d6b2af0066ab05a11c","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl","netlist_sha256":"cc7cee55037a3aa08fbbc4323632ff893f435beea53209e451e1e948293363a4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_021_yan_az","in_core":false,"title":"Yan AZ Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through a cascoded input stage and separate mirror-driven internal branches.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_021_yan_az","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Yan AZ Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_021_yan_az` without changing the declared circuit. XM9/XM10 form the PMOS input pair with bodies tied to net019. XM14/XM15 are the cascoded load branches controlled by XM16/XM17 and the net078 resistive network; XM4/XM5 produce net050. XM11/XM22 drive net094, while XM23 and the distinct XM67 mirror branch drive net057. XM13/XM18 drive VOUT. C0 connects net063 to VOUT, C1 shunts net051, and R2 connects net094 to net051; both net078 load resistors remain. AZ denotes the authored active compensation network, not auto-zero clocks.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vss vdd vinn vinp vout vb1`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nW/L are rounded to 10 nm for centred contacts on the 5 nm grid. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.5 V supply, 0.3 V input reference, 10 pF output load. The external current sink is i0 vb1 vss 1.0981e-05. A direct unity follower receives a 100 mV step at 2 us with 100 ns edges and 8 us high width; falling starts at 10.1 us and completes at 10.2 us. Observe 0–20 us with 0.5 ns maximum step. Report high-window statistics at 8–10 us and return-window statistics at 18–20 us, not a settling time. The rail is adapted from the authored 1.8 V analysis to the actual IHP LV binding; no transistor sizing campaign is performed.\n\nThe transient deck directly connects vinn to vout. The frequency deck closes DC feedback through 1 TH, shunts its remote end by 1 F and injects +0.5/−0.5 V AC at the inputs. This isolates the DC feedback at every measured AC frequency. Residual AC common mode and DC feedback mismatch must each be at most 1 uV; open gain is never inferred from a nearly zero closed-loop input error.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e12 (1 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 10 TOhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_021_yan_az`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `output_v` | V | DC follower output | bias; target |\n| `power_w` | W | DC rail power, -VDD*I(VDD); external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `late_error_v` | V | Mean absolute follower tracking error, 8–10 us | response; ratio; 0 ≤ value |\n| `return_error_v` | V | Mean absolute follower tracking error, 18–20 us | response; ratio; 0 ≤ value |\n| `ripple_v` | V | Full output peak-to-peak range, 8–10 us | response; ratio; 0 ≤ value |\n| `return_ripple_v` | V | Full output peak-to-peak range, 18–20 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted rail power over 2–20 us; external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `bias_v` | V | External current-bias port DC voltage | diagnostic; unscored |\n| `high_v` | V | Mean follower output, 8–10 us | diagnostic; unscored |\n| `low_v` | V | Mean follower output, 18–20 us | diagnostic; unscored |\n| `output_min_v` | V | Minimum output over 0–20 us | diagnostic; unscored |\n| `output_max_v` | V | Maximum output over 0–20 us | diagnostic; unscored |\n| `fixture_cm_max` | V | Residual common-mode excitation in the differential AC fixture | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | DC voltage mismatch across the external feedback inductor | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\nDC bias, 1 Hz/10 kHz differential gain, 10 kHz closed response, tracking error, output range and rail power are distinct observations.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 24054.76 um2 / functional area. The bias scale is 1.5 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 1 mV (1% of the 100 mV step); power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 8 reflects multistage analog routing, active compensation/body connectivity and physical passive matching.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml","case_sha256":"fff4c6f88be23227dd9a60fb1afd4fa0e2afee8f581454c1a37b053c47893f16","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl","netlist_sha256":"490cbd376da9905b4a78527ec19101306e5a21c01822906a68d15a5cc974394c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_022_fer_two_stage","in_core":false,"title":"Fer Two-Stage Miller Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a PMOS input pair, common-source second stage and Miller capacitor.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_022_fer_two_stage","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fer Two-Stage Miller Amplifier Layout Task\n\n## Objective\n\nImplement `amp_022_fer_two_stage` as a GDS layout preserving the complete declared circuit. PMOS differential input pair, NMOS mirror load, NMOS common-source second stage and PMOS current-source load, retaining Miller CC and the complete NMOS-to-PMOS bias mirror. The 10 bound MOS expand to 63 physical units; CC is a 36.46 um square native MIM (1.999831 pF).\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/ac.spice`: frequency observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vdd vout vinp vinn ibias vss`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\n1.5 V, 27 C, TT LV MOS and typical passives; external 20 uA flows from VDD into ibias. The NMOS diode/mirror drives the PMOS diode: bias/tail/output-load multiplicities are 3:3:17; input-pair multiplicities are 5 each, NMOS load 2 each, and second-stage NMOS 24. The PMOS input bodies remain VDD. vinp is noninverting. The unity follower ties vinn directly to vout. Input is 0.6 V with a +0.2 V pulse at 2 us, 100 ns edges, 8 us high width; falling completes at 10.2 us. The load is 10 pF, maximum transient step 0.5 ns, total window 20 us. High/return statistics use 8–10/18–20 us. Balanced AC uses +0.5/-0.5 V excitation and a 1 TH/1 F DC-feedback isolation network over 1 Hz–1 GHz (200 points/decade). Residual AC common mode and DC feedback mismatch must be at most 1 uV.\n\n## Physical Requirements\n\nIHP native standalone-block DRC, named-port LVS and distributed Magic RC extraction. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. The functional footprint includes active/poly, passives, all routed metals and vias, excluding text and nonfunctional boundary markers. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 2000 by 1000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_v | V | DC follower output | bias; target (scale 1.5) |\n| power_w | W | DC rail power, -VDD*I(VDD); includes external reference current drawn from VDD | supply; ratio (scale 1e-12) |\n| gain_db | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| gain_10khz_db | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| closed_gain_10khz_db | dB | Direct follower output/signal AC gain at 10 kHz | response; target (scale 6) |\n| late_error_v | V | Mean absolute follower tracking error, 8–10 us | response; ratio (scale 0.001) |\n| return_error_v | V | Mean absolute follower tracking error, 18–20 us | response; ratio (scale 0.001) |\n| ripple_v | V | Full output peak-to-peak range, 8–10 us | response; ratio (scale 0.001) |\n| return_ripple_v | V | Full output peak-to-peak range, 18–20 us | response; ratio (scale 0.001) |\n| mean_power_w | W | Time-weighted rail power over 2–20 us; includes external reference current drawn from VDD | supply; ratio (scale 1e-12) |\n| bias_v | V | External current-bias port DC voltage | diagnostic; unscored |\n| high_v | V | Mean follower output, 8–10 us | diagnostic; unscored |\n| low_v | V | Mean follower output, 18–20 us | diagnostic; unscored |\n| output_min_v | V | Minimum output over 0–20 us | diagnostic; unscored |\n| output_max_v | V | Maximum output over 0–20 us | diagnostic; unscored |\n| fixture_cm_max | V | Residual common-mode excitation in the differential AC fixture | diagnostic; unscored |\n| dc_feedback_error_v | V | DC voltage mismatch across the external feedback inductor | diagnostic; unscored |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 7022.72 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 6 covers a complete compensated feedback loop with direct-follower recovery. No numerical node shunt is used. No phase margin, unity-gain crossing, noise or settling-time claim is made.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `amp_022_fer_two_stage`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml","case_sha256":"01e6ec6e7364722ccaf64fa089fdcfea8ba0a6c31fdf47b13b7c14aa9491a2b3","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl","netlist_sha256":"2376cfd1faf596940cbb75f9c842a71c603ab59107c0e88575b03a351e5550dc","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_023_fer_fd2s","in_core":true,"title":"Two-Stage Fully Differential OTA with RC Common-Mode Feedback","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies fully differential signals with two output stages, physical R/C compensation and transistor common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_023_fer_fd2s","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Two-Stage Fully Differential OTA with RC Common-Mode Feedback Layout Task\n\n## Objective\n\nImplement `amp_023_fer_fd2s`: an NMOS-input folded first stage, two NMOS\ncommon-source output stages, dual series R/C compensation and transistor\ncommon-mode feedback sensing both outputs through physical R/C arms. Preserve\nall device groups and validate both differential and common-mode behavior in\nthe specified unity differential feedback connection.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit for native LVS.\n- `materials/circuit.spice`: equivalent process-model simulator representation.\n- `materials/testbench.spice`: declared stimuli, differential feedback and measurements.\n\nOrdered ports are `vinp vinn voutp voutn vdd vss ibias vcmr`.\nVINP/VINN are differential inputs; VOUTP/VOUTN are differential outputs;\nVDD/VSS are supply/return; IBIAS receives 20 uA from VDD; VCMR receives the\ncommon-mode reference relative to VSS. The bias mirrors and common-mode\ncontroller stay in the DUT. Do not replace the internal controller with an\nideal servo or omit physical passive devices.\n\nRetain all 28 MOS groups' fixed W/L/m (50 individual transistors), models and\nconnectivity. Equivalent parallel fingering/native merging is allowed if all\nchecks pass. NMOS and resistor bodies connect through the explicit substrate\ntap to VSS; PMOS bodies connect through the well tap to VDD. Keep supplies,\nbody connections and ordered ports faithful to the circuit.\n\nEach output compensation path has a W=1 um, L=0.96 um `rhigh` (nominally\n1.52 kohm at 27 C) between `o1a`/`o1b` and `za`/`zb`, followed by two parallel\n25.85 × 25.85 um `cap_cmim` units to the corresponding output (2.01294 pF).\nEach output-to-`vsen` sensing arm contains eight series W=1 um, L=18 um\n`rhigh` segments (nominally 205.28 kohm total), in parallel with a\n9.95 × 9.95 um MIM (150.096 fF). Resistors use m=1, b=0. These internal\ndevices are separate from external output loads; they must be physically\nimplemented with the same terminal mapping. Internal nodes are not bias ports.\n\n## Operating Conditions\n\nUse typical MOS, capacitor and resistor models, 27 C, 1.2 V supply, 20 uA\nfrom VDD to IBIAS, and input common mode 0.5 V. Each output has an external\n1, 5 or 10 pF load. For each load, evaluate paired positive and negative\nstimuli: `step_v` is +0.1 or −0.1 V and `kick_a` is respectively +100 or\n−100 uA. All six conditions must pass.\n\nDefine `d=VOUTP−VOUTN` and `c=(VOUTP+VOUTN)/2`. The external differential\nfeedback apparatus drives `VINP=0.5+(VSIG−d)/2` and\n`VINN=0.5−(VSIG−d)/2`, through zero-volt series probes. It holds input\ncommon mode and closes differential unity feedback. It does not force output\ncommon mode: the actual DUT controller, its two R/C sense arms and actual\noutput stages close that loop.\n\nAt DC, VSIG=0 and VCMR=0.75 V. Differential AC uses opposite +0.5/−0.5 V\nseries probe excitations and sweeps 1 Hz–1 GHz at 150 points/decade. Measure\n`A=d/(VINP−VINN)`; its sign is retained. Low-frequency gain is dB magnitude\nat 1 Hz; unity frequency is the first falling 0 dB crossing; phase margin is\n180 degrees plus continuous phase there, without subtracting an arbitrary\nphase offset. A missing crossing is an error. This voltage-injection return\nratio is scoped to the high-impedance input and declared unity feedback.\n\nCommon-mode AC sets both series probe AC magnitudes to zero and VCMR AC=1 V,\nkeeping differential feedback closed. Sweep 1 Hz–1 GHz at 100 points/decade.\nMeasure `abs(c/VCMR)` at 1 Hz and its maximum over the complete sweep.\nThis is closed-loop common-mode tracking/peaking, not an internal common-mode\nloop phase-margin measurement.\n\nThe transient sequence runs 0–8 us using Gear order 2 with maximum step 1 ns.\nUse `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-13`, `vntol=1e-8`.\nVSIG rises from zero to `step_v` during 1–1.005 us, holds for 4 us, and\nreturns during 5.005–5.010 us. VCMR rises 0.75→0.8 V during 3–3.005 us,\nholds for 1 us, and returns during 4.005–4.010 us. Thus reference tracking\nis tested while a nonzero differential output is present. Equal current\nsources inject `kick_a` into both outputs during a 6–6.060 us pulse:\n5 ns rise, 50 ns hold and 5 ns fall. Negative `kick_a` withdraws current.\nThe pulse periods are 20 us; only this finite 8 us sequence is measured.\nNo startup initialization is imposed; transient starts from the solved DC point.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_023_fer_fd2s`, at most 10 MiB. Pass native IHP\nmain/maximal DRC without waivers (standalone scope, density/antenna disabled),\nstrict named-port LVS with physical taps, and a 1200 × 400 um functional\noutline. Include all device, contact and routing drawing layers enumerated by\nthe runtime outline constraint. Pin-purpose and annotation layers do not\ncontribute to bounding-box area and cannot conceal functional geometry.\n\nPost-layout measurements must consume the candidate-derived Magic RC netlist,\nincluding physical passives, transistor junction geometry and interconnect.\nThe extraction configuration subdivides Magic's initial grid by two before\nGDS import and imports its isolated copy with `gds_readonly=false`; the submitted\nGDS remains immutable. No extraction error is waived. Device parameters,\ngeometry and port connectivity must survive extraction. Magic idealizes\nwell/substrate taps; source simulation retains their finite process models.\nDistributed substrate resistance/noise and fabrication signoff are outside scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_cm_v` | DC operating point: `(v(outp)+v(outn))/2`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_dm_v` | DC operating point: `v(outp)-v(outn)`. | V | target / target | −∞ … +∞ | 1.2 | bias |\n| `bias_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dm_gain_db` | AC: Value of `(db(((v(outp)-v(outn))/(v(inp)-v(inn))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db(((v(outp)-v(outn))/(v(inp)-v(inn)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph(((v(outp)-v(outn))/(v(inp)-v(inn))))/pi) when (db(((v(outp)-v(outn))/(v(inp)-v(inn)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `cm_gain_vv` | AC: Value of `(mag(((v(outp)+v(outn))/2))) at=1`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `cm_peak_vv` | AC: Maximum of `(mag(((v(outp)+v(outn))/2)))`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `dm_up_error_v` | TRAN: Maximum of `(abs((v(outp)-v(outn))-v(sig))) from=1.5u to=1.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `dm_down_error_v` | TRAN: Maximum of `(abs((v(outp)-v(outn))-v(sig))) from=5.5u to=5.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_up_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=3.5u to=3.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_down_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=4.5u to=5.9u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_kick_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=6.5u to=7.9u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_kick_peak_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=6u to=6.5u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `dm_peak_v` | TRAN: Maximum of `(abs((v(outp)-v(outn)))) from=1u to=5u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=0 to=8u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dm_cm_error_v` | TRAN: Maximum of `(abs((v(outp)-v(outn))-v(sig))) from=3.5u to=3.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_dm_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=1.5u to=1.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `dm_high_v` | TRAN: Mean of `(v(outp)-v(outn)) from=1.8u to=1.95u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `cm_high_v` | TRAN: Mean of `((v(outp)+v(outn))/2) from=3.8u to=3.95u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n\nArea reference: **8435.0 um2**. 76 expanded device instances; sum of device/contact envelopes 5503.6687 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **9**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nDifferential amplifier with CMFB: differential recovery 22.5%; common-mode recovery 22.5%; cross-coupling 9%; loop margin 13.5%; AC transfer 9%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `dm_down_error_v` | 0.075000000000 |\n| `dm_peak_v` | 0.075000000000 |\n| `dm_up_error_v` | 0.075000000000 |\n| `cm_down_error_v` | 0.056250000000 |\n| `cm_kick_error_v` | 0.056250000000 |\n| `cm_kick_peak_v` | 0.056250000000 |\n| `cm_up_error_v` | 0.056250000000 |\n| `cm_dm_error_v` | 0.045000000000 |\n| `dm_cm_error_v` | 0.045000000000 |\n| `phase_margin_deg` | 0.135000000000 |\n| `cm_gain_vv` | 0.022500000000 |\n| `cm_peak_vv` | 0.022500000000 |\n| `dm_gain_db` | 0.022500000000 |\n| `unity_hz` | 0.022500000000 |\n| `bias_v` | 0.015000000000 |\n| `output_cm_v` | 0.015000000000 |\n| `output_dm_v` | 0.015000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover task inputs, frozen requirements, reviewed resources and harness\nfeedback through `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the supplied IHP primitives and KLayout, Magic\nand ngspice. Write `/workspace/output/final.gds` and explicitly submit using\nthe harness protocol. Reference GDS, source records and host configuration\nremain outside standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml","case_sha256":"9d100090b3a7df8bad339688f9f705251ab92674b7f974b87053bdd944576885","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/circuit.cdl","netlist_sha256":"4c52bdbbe491a400eff644efb33e0e97af38d50073ccb1a5a5a76964931f569c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_024_smcnr","in_core":false,"title":"Series-Nulling-Resistor Two-Stage OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through two stages with a physical series nulling resistor in the Miller path.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_024_smcnr","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Series-Nulling-Resistor Two-Stage OTA Layout Task\n\n## Objective\n\nLay out `amp_024_smcnr`, a PMOS-input two-stage OTA with series R/C Miller\ncompensation, for stable loaded unity-feedback response. Preserve the eight\nMOS groups' fixed W/L/m, physical compensation network and explicit bias interface.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model simulation representation.\n- `materials/testbench.spice`: nominal bias, loop-gain and finite-step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout ibias`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is the output, and IBIAS\nconnects an external 100 nA current sink to VSS. The bias mirror remains inside\nthe DUT. No ideal source is a layout device. NMOS and resistor bodies connect\nthrough the explicit substrate tap to VSS; PMOS bodies connect through the\nwell tap to VDD. Preserve device models and total W/L/m; equivalent parallel\nMOS fingers and native resistor merging are allowed when LVS and all other\nrequirements pass. Supply and return must remain distinct.\n\nThe internal compensation path is `outn` → two parallel MIM units → `nzo` →\nfour series high-poly segments → `vout`. Each `cap_cmim` is 25.85 × 25.85 um,\nnominally 1.00647 pF; each `rhigh` is W=1 um, L=18 um, m=1, b=0, giving\napproximately 100 kohm for the chain with the process model. These are DUT\ndevices, separately from the external load. Do not delete or replace them with\nideal parasitic annotations. Internal nodes are not extra bias ports.\n\n## Operating Conditions\n\nUse typical MOS, capacitor and resistor models at 27 C, 1.2 V supply and a\n100 nA external bias sink. External output loads are 5, 10 and 20 pF. All\nthree conditions must pass. Qualification is nominal and does not cover PVT,\nmismatch, rail-to-rail operation or arbitrary output loads.\n\nAt DC, VINP=0.5 V and VOUT feeds VINN through the zero-volt probe. AC uses a\n1 V series injection at this feedback connection, VINP AC=0, and\n`T=-V(vout)/V(vm)`. Sweep 0.01 Hz–100 MHz at 150 points/decade. Gain is\n`20 log10(abs(T))`; phase is its continuous phase without subtracting a fitted\nlow-frequency offset. Unity frequency is the first descending 0 dB crossing;\nphase margin is 180 degrees plus phase there. Missing crossings are errors.\nThis voltage-injection measurement uses the high-impedance MOS input boundary.\n\nTransient keeps the zero-volt feedback connection. VINP rises 0.5→0.7 V from\n20 to 20.1 us, falls from 100.1 to 100.2 us, and repeats every 160 us. Simulate\n0–180 us using Gear order 2 with 50 ns maximum step. Use `rshunt=1e12`,\n`reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`. This weak numerical shunt is\npart of the declared simulator boundary, not a physical bias or startup source.\n\n## Physical Requirements\n\nSubmit GDSII with top cell `amp_024_smcnr`, at most 10 MiB. Pass native IHP\nmain plus maximal DRC (standalone scope, density/antenna disabled), strict\nnamed-port LVS with physical taps, and a 650 × 80 um functional envelope.\nThere are no case DRC waivers. All functional devices, contacts and routing\nmust lie on the drawing layers listed in the runtime `outline` constraint;\nannotation/pin-purpose layers do not contribute to its bounding-box area.\n\nPost-layout simulation must consume the candidate's Magic RC extraction,\nincluding physical R/C devices and extracted interconnect. Well/substrate taps\nare ideal connections in this extractor, rather than the finite source tap\nmodels; this is not a distributed substrate or substrate-noise model. The\nOSDI resistor model and MOS/MIM model resources must be available.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=50u to=95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=130u to=175u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=90u to=95u)-(avg v(vout) from=170u to=175u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=20u to=180u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=20u to=100u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=100.2u to=180u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **5869.81 um2**. 35 expanded device instances; sum of device/contact envelopes 3813.4378 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover task, inputs, resources and harness feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives and KLayout, Magic and ngspice tools. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml","case_sha256":"b88a4f25693448653662ea6fe34a6a5d65c57a1f1e81e11e63be837ff2633ab8","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/materials/circuit.cdl","netlist_sha256":"0b9a0afed61b6479a3c7cb1b8c6581ab8ad8623db88c3d5515137be83de4399c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_026_fan_chopper_ota","in_core":false,"title":"Fan Two-Stage OTA with Static Output Chopper","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a two-stage core and an output chopper held in its straight-through state.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_026_fan_chopper_ota","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Two-Stage OTA Layout Task\n\n## Objective\n\nImplement the supplied 23-MOS, two-capacitor two-stage OTA with its statically straight-through output chopper. Preserve all devices, connections and dimensions. The cross branches remain present and off; no CMFB exists or may be added. Four MIM units realize the two 6 pF compensation capacitors (44.67 um square each).\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4`. Preserve these named connections.\n\nThe native CDL and simulator SPICE describe the same circuit. VINP/VINN are\nthe differential inputs; VOUTP/VOUTN are outputs; VDD/VSS are supply/return;\nVB1 through VB4 are bias ports. Independent bias sources are outside the physical core. Physical well/substrate taps are included.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode 0.6 V; vb1/vb2/vb3/vb4=0.3983759766/0.65/0.45/0.55 V. Loads are 1 and 10 pF per output. Differential steps are ±50 mV at 10 us, returning at 40.02 us; 5 uA per output common-mode injection runs from 60 to 61.02 us. Maximum transient step is 2 ns, duration 100 us. An external ideal differential unity-feedback fixture drives the signal test; it does not sense or regulate output common mode. AC transfer divides the output difference by the actual input difference.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and strict named-interface LVS must pass. Keep the supplied tap geometry and compact-device parameters consistent. Functional device, well, contact and routing layers define area; annotation layers do not. The bounding rectangle must fit 5000 by 1000 um. No DRC waivers apply.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nAll declared measurements must be finite and use the extracted candidate. Gain and phase at 10 Hz/100 kHz, output bias, supply power, small differential step response, common-mode kick and recovery are observed by the supplied deck. Step response subtracts 8–9 us baseline from 38–39 us response. The common-mode baseline is 58–59 us; kick peak is 60–62 us and residual is 98–99 us. Continuous quality uses independently simulated same-condition source observations. The physical-domain checks are nonnegative supplied power and nonnegative absolute errors; they are not upstream specifications.\n\nQ is 14924.75 um2 divided by functional area. The anchor sums (W+2.4)(L+2.4) for each MOS and 3.2² um2 for each local tap and one global tap, adds four (44.67+2.4)² um2 MIM envelopes, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (50 mV scale), with common-mode kick/recovery retained as unscored diagnostics because this core has no common-mode regulator; bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 7 reflects multistage compensation and loaded differential response; common-mode drift and kick response remain observations, not proof of regulation. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `cm_bias_v` | `(v(outp)+v(outn))/2` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `dm_bias_v` | `v(outp)-v(outn)` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `power_w` | `-v(vdd)*i(VDD)-v(vb1)*i(VB1)-v(vb2)*i(VB2)-v(vb3)*i(VB3)-v(vb4)*i(VB4)` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `gain_db` | `find gain at=10` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `gain_100khz_db` | `find gain at=100k` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `phase_100khz_deg` | `find phase_deg at=100k` | deg | target / target / response | −∞ … +∞ | 180 |\n| `step_response_v` | `dm_high_v-dm_before_v` | V | target / target / response | −∞ … +∞ | 0.05 |\n| `cm_before_v` | `avg cm from=58u to=59u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_kick_v` | `max cm_delta from=60u to=62u` | V | functional check | 0 … +∞ | — |\n| `cm_recovery_v` | `max cm_delta from=98u to=99u` | V | functional check | 0 … +∞ | — |\n| `cm_min_v` | `min cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\n\n\n### Score weights\n\nDifferential OTA cores: differential response 66%; bias 6%; power 18%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_100khz_db` | 0.165000000000 |\n| `gain_db` | 0.165000000000 |\n| `phase_100khz_deg` | 0.165000000000 |\n| `step_response_v` | 0.165000000000 |\n| `cm_bias_v` | 0.030000000000 |\n| `dm_bias_v` | 0.030000000000 |\n| `power_w` | 0.180000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the reviewed IHP resources. Submit only the GDS with top cell amp_026_fan_chopper_ota. Evaluation runs native DRC/LVS, area, candidate-derived Magic RC extraction and ngspice post-layout observations. The source circuit is independently simulated for scoring.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml","case_sha256":"6b14c7474639d3bf338882eb43da15b4fb4e756e135b88c6ef88d53de44b29fe","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl","netlist_sha256":"232e765fe36c1fdd781bd26c556b0418f9bd53f3e39011fd244d67fd463e52c4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_027_fan_rrl_ota","in_core":false,"title":"Fan Telescopic OTA with Transistor DDA-CMFB","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a telescopic core with transistor common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_027_fan_rrl_ota","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Telescopic OTA Layout Task\n\n## Objective\n\nImplement the supplied 16-MOS telescopic OTA with its transistor DDA-CMFB. Preserve all devices, connections and dimensions. This task contains only the OTA core.\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4`. Preserve these named connections.\n\nThe native CDL and simulator SPICE describe the same circuit. VINP/VINN are\nthe differential inputs; VOUTP/VOUTN are outputs; VDD/VSS are supply/return;\nVB1 through VB4 are bias ports. Independent bias sources are outside the physical core. Physical well/substrate taps are included.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode 0.6 V; vb1/vb2/vb3/vb4=0.45/0.75/0.55/0.6 V. Loads are 1 and 10 pF per output. Differential steps are ±20 uV at 10 us, returning at 40.02 us; 5 uA per output common-mode injection runs from 60 to 61.02 us. Maximum transient step is 2 ns, duration 100 us. This is an open-loop signal test with the internal CMFB operating.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and strict named-interface LVS must pass. Keep the supplied tap geometry and compact-device parameters consistent. Functional device, well, contact and routing layers define area; annotation layers do not. The bounding rectangle must fit 5000 by 1000 um. No DRC waivers apply.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nAll declared measurements must be finite and use the extracted candidate. Gain and phase at 10 Hz/100 kHz, output bias, supply power, small differential step response, common-mode kick and recovery are observed by the supplied deck. Step response subtracts 8–9 us baseline from 38–39 us response. The common-mode baseline is 58–59 us; kick peak is 60–62 us and residual is 98–99 us. Continuous quality uses independently simulated same-condition source observations. The physical-domain checks are nonnegative supplied power and nonnegative absolute errors; they are not upstream specifications.\n\nQ is 1035.78 um2 divided by functional area. The anchor sums (W+2.4)(L+2.4) for each MOS and 3.2² um2 for each local tap and one global tap, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (1 mV scale), and inverse absolute common-mode error (1 uV floor); bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 6 reflects the complete signal amplifier coupled to a transistor common-mode recovery loop. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `cm_bias_v` | `(v(outp)+v(outn))/2` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `dm_bias_v` | `v(outp)-v(outn)` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `power_w` | `-v(vdd)*i(VDD)-v(vb1)*i(VB1)-v(vb2)*i(VB2)-v(vb3)*i(VB3)-v(vb4)*i(VB4)` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `gain_db` | `find gain at=10` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `gain_100khz_db` | `find gain at=100k` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `phase_100khz_deg` | `find phase_deg at=100k` | deg | target / target / response | −∞ … +∞ | 180 |\n| `step_response_v` | `dm_high_v-dm_before_v` | V | target / target / response | −∞ … +∞ | 0.001 |\n| `cm_before_v` | `avg cm from=58u to=59u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_kick_v` | `max cm_delta from=60u to=62u` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `cm_recovery_v` | `max cm_delta from=98u to=99u` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `cm_min_v` | `min cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\n\n\n### Score weights\n\nDifferential OTA cores: differential response 49.5%; common-mode recovery 22.5%; bias 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_100khz_db` | 0.123750000000 |\n| `gain_db` | 0.123750000000 |\n| `phase_100khz_deg` | 0.123750000000 |\n| `step_response_v` | 0.123750000000 |\n| `cm_kick_v` | 0.112500000000 |\n| `cm_recovery_v` | 0.112500000000 |\n| `cm_bias_v` | 0.022500000000 |\n| `dm_bias_v` | 0.022500000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the reviewed IHP resources. Submit only the GDS with top cell amp_027_fan_rrl_ota. Evaluation runs native DRC/LVS, area, candidate-derived Magic RC extraction and ngspice post-layout observations. The source circuit is independently simulated for scoring.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml","case_sha256":"d7a5554c046d4b527e851cabc1929099f376234d0cc452cdea4c3cca4f94bbdc","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl","netlist_sha256":"afb6faf1d0f260f490f7bd748612c8d10ebbef233154362b853c867b9012b33e","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_029_two_stage_miller_comp","in_core":false,"title":"Differential Two-Stage Miller Amplifier Without CMFB","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies fully differential signals through two Miller-compensated stages without common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_029_two_stage_miller_comp","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Differential Two-Stage Miller Amplifier Without CMFB Layout Task\n\n## Objective\n\nImplement `amp_029_two_stage_miller_comp` as a GDS layout preserving the complete declared circuit. Fully differential NMOS-input two-stage Miller amplifier without CMFB. Ten physical MOS retain both PMOS first-stage current sources, both PMOS common-source output drivers, NMOS reference/tail/output sinks, and both series R/C Miller branches. VBL and the 20 uA reference source are external apparatus.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/ac.spice`: frequency observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vinp vinn voutp voutn vdd vss ref vbl`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\n1.2 V, 27 C, TT LV MOS and typical passives; inputs have 0.6 V common mode, VBL=0.7087 V and 20 uA flows from VDD into ref. Each output has 10 pF to ground. The fixed binding uses 30 kohm and 0.4 pF per Miller branch, represented by native rhigh/MIM. Open AC drives +0.5/-0.5 V at 1 Hz–1 GHz, 200 points/decade, with no DC or AC common-mode feedback. The separate closed test uses external differential feedback vp=0.6+(signal-voutp+voutn)/2 and vm=0.6-(signal-voutp+voutn)/2. It fixes input common mode only; it neither senses nor servos output common mode. A 10 mV signal pulse starts at 2 us with 100 ns edges and 8 us high width. Maximum transient step is 1 ns through 20 us. Report 8–10 and 18–20 us windows. Closed and open DC differential offsets may differ because one fixture closes differential feedback; their input common mode and external bias are identical.\n\n## Physical Requirements\n\nIHP native standalone-block DRC, named-port LVS and distributed Magic RC extraction. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. The functional footprint includes active/poly, passives, all routed metals and vias, excluding text and nonfunctional boundary markers. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 2000 by 1000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_cm_v | V | DC output common mode | bias; target (scale 1.2) |\n| offset_v | V | DC differential output offset | bias; target (scale 0.01) |\n| power_w | W | DC rail power including external current bias | supply; ratio (scale 1e-12) |\n| gain_db | dB | Balanced open differential AC gain at 1 Hz | response; db20 |\n| gain_10khz_db | dB | Balanced open differential AC gain at 10 kHz | response; db20 |\n| late_error_v | V | Mean absolute differential tracking error 8–10 us | response; ratio (scale 0.001) |\n| return_error_v | V | Mean absolute differential tracking error 18–20 us | response; ratio (scale 0.001) |\n| ripple_v | V | Differential peak-to-peak output 8–10 us | response; ratio (scale 0.001) |\n| fixture_cm_max | V | fixture_cm_max | diagnostic; unscored |\n| high_v | V | high_v | diagnostic; unscored |\n| low_v | V | low_v | diagnostic; unscored |\n| cm_min_v | V | cm_min_v | diagnostic; unscored |\n| cm_max_v | V | cm_max_v | diagnostic; unscored |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 2278.38 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 6 covers the compensated differential feedback experiment. No CMFB is added. Miller capacitors are open at DC and provide no DC common-mode feedback. A large parasitic-induced common-mode shift and reduced differential response are continuous quality losses. These finite-window measurements do not certify robust biasing, settling, phase margin or useful product gain. No numerical node shunt is used.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `ripple_v` | 0.225000000000 |\n| `gain_10khz_db` | 0.090000000000 |\n| `gain_db` | 0.090000000000 |\n| `offset_v` | 0.022500000000 |\n| `output_cm_v` | 0.022500000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `amp_029_two_stage_miller_comp`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml","case_sha256":"bfd0997869c87d352f280ef91aa2dfead89c6876e5ae19bf4d362a19a4620ca6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl","netlist_sha256":"7f89e7956013c5963092250563b16713f48f9a31dd350503d0e5fb7d7d408923","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_034_fan_chopper_cmfb","in_core":false,"title":"Fan Output CMFB OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a folded first stage, static output chopper and output common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_034_fan_chopper_cmfb","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Output CMFB OTA Layout Task\n\n## Objective\n\nImplement `amp_034_fan_chopper_cmfb` without changing the declared circuit. The fixed upstream flattened composite contains a PMOS input pair, folded-cascode first stage, statically straight-through transmission-gate output chopper and common-source second stage. Its own seven-transistor PMOS-input CMFB detects the output mean through two 1 MOhm resistors and drives vb4o, exclusively controlling XM8O/XM9O. The tail and folded PMOS sources retain the separate external core__vb4 bias. Both 6 pF Miller branches and the 1 fF vb4o compensation branch remain. This is the upstream composite itself, not a servo added during Bench integration.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm core__out1_p core__out1_n vb4o`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nW/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. The subminimum 1 fF CCM is realized by seven series 7.016 fF MIM units (2.11 um sides), approximately 1.002 fF equivalent. Intermediate nodes and their physical parasitics are retained in both source and candidate models. The branch is never omitted. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.2 V supply, 0.6 V input common mode, 10 pF on each output. The external voltage sources are vb1_core core__vb1 vss dc 0.3983759766; vb2_core core__vb2 vss dc 0.65; vb3_core core__vb3 vss dc 0.45; vb4_core core__vb4 vss dc 0.55; vrefcm vref_cm vss dc 0.5. Both the no-disturbance condition and the following combined sequence run for 150 us with a 2 ns maximum step. The differential command rises from 0 to 10 mV at 10 us and returns after 10 us; equal +20 uA currents enter both outputs at 30 us for 2 us. The output reference rises by 25 mV at 50 us for 15 us; input common mode rises by 25 mV at 75 us for 15 us. The stage-1 reference is not an interface of this circuit. All edges are 20 ns. Pulse widths are measured after the rising edge, so falling edges start one edge duration after nominal delay plus width. The unperturbed condition sets every step and kick amplitude to zero. The two CMFB loops, where present, remain connected throughout. Monitor ports are unloaded; their extraction and routing parasitics remain. No external clock is applied: straight-through chopper gates stay tied to their actual rails, and crossed paths stay off.\n\nThe external fixture enforces inp = icm + (signal − (outp−outn))/2 and inn = icm − (signal − (outp−outn))/2. It closes only the differential measurement loop; the DUT transistors close common-mode feedback. The frequency deck retains this DC feedback, isolates each feedback branch with 1 TH/1 F low-pass elements and injects +0.5/−0.5 V AC. The actual differential excitation remains 1 V and residual common-mode must be at most 1 uV.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e12 (1 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 10 TOhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_034_fan_chopper_cmfb`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `cm_quiet_v` | V | avg cm, 5–9 us | bias; target |\n| `cm_pre_kick_v` | V | avg cm, 28–29 us | bias; target |\n| `cm_recovery_v` | V | avg cm, 45–49 us | bias; target |\n| `cm_ref_v` | V | avg cm, 60–64 us | bias; target |\n| `cm_input_cm_v` | V | avg cm, 85–89 us | bias; target |\n| `cm_stage_ref_v` | V | avg cm, 120–124 us | bias; target |\n| `cm_late_v` | V | avg cm, 145–149 us | bias; target |\n| `cm_quiet_pp_v` | V | pp cm, 5–9 us | response; ratio; 0 ≤ value |\n| `cm_late_pp_v` | V | pp cm, 145–149 us | response; ratio; 0 ≤ value |\n| `cm_kick_v` | V | max cm_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `cm_recovery_error_v` | V | avg cm_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `s1_quiet_v` | V | avg s1, 5–9 us | bias; target |\n| `s1_pre_kick_v` | V | avg s1, 28–29 us | bias; target |\n| `s1_recovery_v` | V | avg s1, 45–49 us | bias; target |\n| `s1_ref_v` | V | avg s1, 60–64 us | bias; target |\n| `s1_input_cm_v` | V | avg s1, 85–89 us | bias; target |\n| `s1_stage_ref_v` | V | avg s1, 120–124 us | bias; target |\n| `s1_late_v` | V | avg s1, 145–149 us | bias; target |\n| `s1_quiet_pp_v` | V | pp s1, 5–9 us | response; ratio; 0 ≤ value |\n| `s1_late_pp_v` | V | pp s1, 145–149 us | response; ratio; 0 ≤ value |\n| `s1_kick_v` | V | max s1_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `s1_recovery_error_v` | V | avg s1_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `dm_high_error_v` | V | avg dmerror, 18–19 us | response; ratio; 0 ≤ value |\n| `dm_return_error_v` | V | avg dmerror, 25–29 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted delivered power over the declared transient window | supply; ratio; 0 ≤ value |\n| `cm_bias_v` | V | DC cm_bias_v | bias; target |\n| `s1_bias_v` | V | DC s1_bias_v | bias; target |\n| `dm_bias_v` | V | DC dm_bias_v | bias; target |\n| `power_w` | W | DC delivered power from DUT supply and declared external bias/reference sources | supply; ratio; 0 ≤ value |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `fixture_cm_max` | V | Fixture validity fixture_cm_max | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | Fixture validity dc_feedback_error_v | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\n`cm` is the output mean and `s1` is the first-stage mean. Quiet/pre-kick/recovery/reference/input-CM/stage-reference/late windows are 5–9, 28–29, 45–49, 60–64, 85–89, 120–124 and 145–149 us. Recovery is relative to each run’s pre-kick mean; it is not a claim of asymptotic settling. All window values are evaluated for both zero-stimulus and disturbed conditions.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 20711.65 um2 / functional area. The bias scale is 1.2 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 0.1 mV for differential error (1% of the 10 mV step) and 1 mV for common-mode excursions; power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 8 reflects the folded multistage differential core, transistor common-mode control and physical compensation.\n\n\n### Score weights\n\nOne/two-loop CMFB amplifier assemblies: output common-mode dynamics 33.8%; stage-1 common-mode dynamics 5.62%; differential tracking 22.5%; AC transfer 11.2%; common-mode operating points 5.62%; power 11.2%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `cm_kick_v` | 0.084375000000 |\n| `cm_late_pp_v` | 0.084375000000 |\n| `cm_quiet_pp_v` | 0.084375000000 |\n| `cm_recovery_error_v` | 0.084375000000 |\n| `s1_kick_v` | 0.014062500000 |\n| `s1_late_pp_v` | 0.014062500000 |\n| `s1_quiet_pp_v` | 0.014062500000 |\n| `s1_recovery_error_v` | 0.014062500000 |\n| `dm_high_error_v` | 0.112500000007 |\n| `dm_return_error_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.037500000000 |\n| `gain_10khz_db` | 0.037500000000 |\n| `gain_db` | 0.037500000000 |\n| `cm_bias_v` | 0.003308823529 |\n| `cm_input_cm_v` | 0.003308823529 |\n| `cm_late_v` | 0.003308823529 |\n| `cm_pre_kick_v` | 0.003308823529 |\n| `cm_quiet_v` | 0.003308823529 |\n| `cm_recovery_v` | 0.003308823529 |\n| `cm_ref_v` | 0.003308823529 |\n| `cm_stage_ref_v` | 0.003308823529 |\n| `dm_bias_v` | 0.003308823529 |\n| `s1_bias_v` | 0.003308823529 |\n| `s1_input_cm_v` | 0.003308823529 |\n| `s1_late_v` | 0.003308823529 |\n| `s1_pre_kick_v` | 0.003308823529 |\n| `s1_quiet_v` | 0.003308823529 |\n| `s1_recovery_v` | 0.003308823529 |\n| `s1_ref_v` | 0.003308823529 |\n| `s1_stage_ref_v` | 0.003308823529 |\n| `mean_power_w` | 0.056250000000 |\n| `power_w` | 0.056250000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml","case_sha256":"0987c00cb47a0baa86dcee578ed4c9ad0252ab81190f5ad0dd65ff9f419ae416","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl","netlist_sha256":"1898e7ade5f22a3a7785fcc52bb04bce6a9405a9b63a01f0b01da6ad316e00a3","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.amp_035_fan_chopper_cmfb_dual","in_core":false,"title":"Fan Dual CMFB OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a static output chopper and separate stage/output common-mode feedback loops.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_035_fan_chopper_cmfb_dual","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Dual CMFB OTA Layout Task\n\n## Objective\n\nImplement `amp_035_fan_chopper_cmfb_dual` without changing the declared circuit. The independently frozen flattened composite contains the PMOS input/folded-cascode first stage, static straight-through output chopper and common-source second stage. One seven-transistor CMFB detects the output mean through two 1 MOhm resistors and drives XM8O/XM9O on vb4o. A second seven-transistor CMFB detects stg1_p/stg1_n through two 50 MOhm resistors and drives vb4_ctl, controlling the first-stage tail and folded PMOS sources. The 50 MOhm override, distinct 0.3265 V stage reference, 100 pF inner-loop compensation and both 6 pF Miller capacitors remain. Neither loop is replaced or independently opened to infer joint stability.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 vref_out vref_s1 stg1_p stg1_n vb4o vb4_ctl`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nW/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.2 V supply, 0.6 V input common mode, 10 pF on each output. The external voltage sources are vb1_core core__vb1 vss dc 0.3983759766; vb2_core core__vb2 vss dc 0.65; vb3_core core__vb3 vss dc 0.45; vrefout vref_out vss dc 0.5; vrefs1 vref_s1 vss dc 0.3265. Both the no-disturbance condition and the following combined sequence run for 150 us with a 2 ns maximum step. The differential command rises from 0 to 10 mV at 10 us and returns after 10 us; equal +20 uA currents enter both outputs at 30 us for 2 us. The output reference rises by 25 mV at 50 us for 15 us; input common mode rises by 25 mV at 75 us for 15 us. The stage-1 reference rises by 10 mV at 110 us for 15 us. All edges are 20 ns. Pulse widths are measured after the rising edge, so falling edges start one edge duration after nominal delay plus width. The unperturbed condition sets every step and kick amplitude to zero. The two CMFB loops, where present, remain connected throughout. Monitor ports are unloaded; their extraction and routing parasitics remain. No external clock is applied: straight-through chopper gates stay tied to their actual rails, and crossed paths stay off.\n\nThe external fixture enforces inp = icm + (signal − (outp−outn))/2 and inn = icm − (signal − (outp−outn))/2. It closes only the differential measurement loop; the DUT transistors close common-mode feedback. The frequency deck retains this DC feedback, isolates each feedback branch with 1 TH/1 F low-pass elements and injects +0.5/−0.5 V AC. The actual differential excitation remains 1 V and residual common-mode must be at most 1 uV.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e14 (100 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 1 POhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with pivtol=1e-18, below the numerical shunt conductance, and the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_035_fan_chopper_cmfb_dual`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `cm_quiet_v` | V | avg cm, 5–9 us | bias; target |\n| `cm_pre_kick_v` | V | avg cm, 28–29 us | bias; target |\n| `cm_recovery_v` | V | avg cm, 45–49 us | bias; target |\n| `cm_ref_v` | V | avg cm, 60–64 us | bias; target |\n| `cm_input_cm_v` | V | avg cm, 85–89 us | bias; target |\n| `cm_stage_ref_v` | V | avg cm, 120–124 us | bias; target |\n| `cm_late_v` | V | avg cm, 145–149 us | bias; target |\n| `cm_quiet_pp_v` | V | pp cm, 5–9 us | response; ratio; 0 ≤ value |\n| `cm_late_pp_v` | V | pp cm, 145–149 us | response; ratio; 0 ≤ value |\n| `cm_kick_v` | V | max cm_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `cm_recovery_error_v` | V | avg cm_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `s1_quiet_v` | V | avg s1, 5–9 us | bias; target |\n| `s1_pre_kick_v` | V | avg s1, 28–29 us | bias; target |\n| `s1_recovery_v` | V | avg s1, 45–49 us | bias; target |\n| `s1_ref_v` | V | avg s1, 60–64 us | bias; target |\n| `s1_input_cm_v` | V | avg s1, 85–89 us | bias; target |\n| `s1_stage_ref_v` | V | avg s1, 120–124 us | bias; target |\n| `s1_late_v` | V | avg s1, 145–149 us | bias; target |\n| `s1_quiet_pp_v` | V | pp s1, 5–9 us | response; ratio; 0 ≤ value |\n| `s1_late_pp_v` | V | pp s1, 145–149 us | response; ratio; 0 ≤ value |\n| `s1_kick_v` | V | max s1_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `s1_recovery_error_v` | V | avg s1_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `dm_high_error_v` | V | avg dmerror, 18–19 us | response; ratio; 0 ≤ value |\n| `dm_return_error_v` | V | avg dmerror, 25–29 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted delivered power over the declared transient window | supply; ratio; 0 ≤ value |\n| `cm_bias_v` | V | DC cm_bias_v | bias; target |\n| `s1_bias_v` | V | DC s1_bias_v | bias; target |\n| `dm_bias_v` | V | DC dm_bias_v | bias; target |\n| `power_w` | W | DC delivered power from DUT supply and declared external bias/reference sources | supply; ratio; 0 ≤ value |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `fixture_cm_max` | V | Fixture validity fixture_cm_max | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | Fixture validity dc_feedback_error_v | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\n`cm` is the output mean and `s1` is the first-stage mean. Quiet/pre-kick/recovery/reference/input-CM/stage-reference/late windows are 5–9, 28–29, 45–49, 60–64, 85–89, 120–124 and 145–149 us. Recovery is relative to each run’s pre-kick mean; it is not a claim of asymptotic settling. All window values are evaluated for both zero-stimulus and disturbed conditions.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 361466.3 um2 / functional area. The bias scale is 1.2 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 0.1 mV for differential error (1% of the 10 mV step) and 1 mV for common-mode excursions; power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 9 reflects two interacting transistor CM loops, high-impedance sensing and large physical passive networks.\n\n\n### Score weights\n\nOne/two-loop CMFB amplifier assemblies: output common-mode dynamics 27%; stage-1 common-mode dynamics 22.5%; differential tracking 18%; AC transfer 9%; common-mode operating points 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `cm_kick_v` | 0.067500000000 |\n| `cm_late_pp_v` | 0.067500000000 |\n| `cm_quiet_pp_v` | 0.067500000000 |\n| `cm_recovery_error_v` | 0.067500000000 |\n| `s1_kick_v` | 0.056250000000 |\n| `s1_late_pp_v` | 0.056250000000 |\n| `s1_quiet_pp_v` | 0.056250000000 |\n| `s1_recovery_error_v` | 0.056250000000 |\n| `dm_high_error_v` | 0.089999999992 |\n| `dm_return_error_v` | 0.090000000000 |\n| `closed_gain_10khz_db` | 0.030000000000 |\n| `gain_10khz_db` | 0.030000000000 |\n| `gain_db` | 0.030000000000 |\n| `cm_bias_v` | 0.002647058824 |\n| `cm_input_cm_v` | 0.002647058824 |\n| `cm_late_v` | 0.002647058824 |\n| `cm_pre_kick_v` | 0.002647058824 |\n| `cm_quiet_v` | 0.002647058824 |\n| `cm_recovery_v` | 0.002647058824 |\n| `cm_ref_v` | 0.002647058824 |\n| `cm_stage_ref_v` | 0.002647058824 |\n| `dm_bias_v` | 0.002647058824 |\n| `s1_bias_v` | 0.002647058824 |\n| `s1_input_cm_v` | 0.002647058824 |\n| `s1_late_v` | 0.002647058824 |\n| `s1_pre_kick_v` | 0.002647058824 |\n| `s1_quiet_v` | 0.002647058824 |\n| `s1_recovery_v` | 0.002647058824 |\n| `s1_ref_v` | 0.002647058824 |\n| `s1_stage_ref_v` | 0.002647058824 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml","case_sha256":"d6ca987ce5e07f0cbae536f0db86b9f6a21d5a85966fdf885a02101fdf3fe3ef","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl","netlist_sha256":"70db9a09e47cfaf6dc9aecb394d7300c2d6125f26d16252ff1ba67688085165c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.buf_001_super_follower","in_core":false,"title":"MIM-Compensated Local-Feedback Source Follower","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Buffers a signal with local feedback and physical MIM compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/buf_001_super_follower","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# MIM-Compensated Local-Feedback Source Follower Layout Task\n\n## Objective\n\nImplement `buf_001_super_follower` in ihp-sg13g2 and submit self-contained GDS. Six MOS entries expand to 17 physical MOS instances in a local-feedback source follower. Fixed IHP W/L/m are retained. The internal na-to-VSS 250 fF compensation is implemented as a 12.85 by 12.85 um cap_cmim (nominally 249.74 fF at 27 C, including model perimeter capacitance); it is not removed or moved to the output. Explicit physical taps and the MIM dimensions are common to LVS, source simulation and extracted simulation.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit. `materials/circuit.spice` is its equivalent simulator model-call representation. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `vdd vout vin ibias vss`. In order: Supply, output, signal input, reference-current input, and return.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical IHP low-voltage MOS and resistor models and typical capacitor models; explicit finite physical tap models and a 1e12 ohm ngspice numerical shunt at each node. Candidate Magic RC is extracted with zero coupling-capacitance threshold.\n\nVDD = 1.5 V; VSS = 0 V; a 20 uA current source from VDD into ibias. VIN = 0.55 V DC, AC amplitude 1 V. External output loads are 5, 10 and 20 pF. AC uses 100 points/decade from 1 Hz to 1 GHz. VIN stays at 0.55 V through 1 us, ramps to 0.65 V at 1.001 us, holds through 3 us, ramps back at 3.001 us and holds through 5 us. Transient output/max step is 0.2 ns. Recovered errors compare output to its 2.5 us and 0.5 us samples, over 1.5–2.9 us and 3.5–4.9 us respectively.\n\n## Physical Requirements\n\nTop cell `buf_001_super_follower`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, IHP main and maximal DRC, with density and antenna outside this standalone scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 160 by 45 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. This is a level-shifting source follower with about 0.84 small-signal gain, not a unity-gain rail-to-rail buffer. Qualification is restricted to the stated low-input range; higher input bias compresses the gain. Noise, mismatch, other input levels, PVT and RF/EM are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output/control voltage | V | target / target | 0 … 1.5 | 1.5 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 1.5 | 1.5 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_vv` | Magnitude V(vout) at 10 Hz with unit AC input | V/V | target / target | −∞ … +∞ | 1.0 |\n| `bandwidth_hz` | First falling 3 dB crossing relative to the 10 Hz gain | Hz | maximize / ratio | 0 … +∞ | — |\n| `step_gain` | (Vout at 2.5 us - Vout at 0.5 us) / 0.1 V | V/V | target / target | −∞ … +∞ | 1.0 |\n| `recovery_up_v` | Maximum absolute recovered error over the upward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `recovery_down_v` | Maximum absolute recovered error over the downward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the complete transient | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **1242.88 um2**. 20 expanded device instances; sum of device/contact envelopes 782.8540 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSuper source follower: loaded recovery 36%; source-follower transfer 27%; bandwidth 13.5%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.180000000000 |\n| `recovery_up_v` | 0.180000000000 |\n| `gain_vv` | 0.135000000000 |\n| `step_gain` | 0.135000000000 |\n| `bandwidth_hz` | 0.135000000000 |\n| `bias_v` | 0.022500000000 |\n| `output_v` | 0.022500000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml","case_sha256":"9791170a62118768f8f4cc2a9def54e1334a2aea69723fbd1e886cf372c326a7","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/circuit.cdl","netlist_sha256":"2f617c485f1bd1d94d47a1fc21c6c1e815fb9f4a4278ee93c2a1eb80b80a4404","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.cmfb_002_5t_pmos_input","in_core":false,"title":"PMOS-Input Common-Mode Detector and Controller","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Detects and controls common-mode voltage with a PMOS-input feedback core.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_002_5t_pmos_input","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# PMOS-Input Common-Mode Detector and Controller Layout Task\n\n## Objective\n\nImplement `cmfb_002_5t_pmos_input` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. Seven MOS implement a PMOS-input five-transistor OTA plus the PMOS/NMOS diode bias branch. Two 1 Mohm sensing arms each use four series physical high-poly units. The pinned IHP widths/lengths are quantized to the 10 nm drawing grid, including the 0.29 um bias NMOS. Bodies and all sensing/bias devices are retained.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vinp vinn vcmfb vref vdd vss`. The resistor midpoint senses input common mode. Reference and input sources are external. This is a standalone detector/controller; it contains neither a controlled amplifier nor a complete common-mode feedback loop. Fixture dependent voltage sources only establish specified input voltages and are outside the DUT.\n\n## Operating Conditions\n\n1.5 V supply; 0.5 and 0.7 V input common mode and equal reference. Output has 1 pF to ground and 10 Mohm to the common-mode source. At each bias, separate unit AC common-mode, reference and balanced differential excitations cover 1 Hz–100 MHz. Verify zero differential component in common-mode excitation and zero common-mode component in differential excitation. Centered 2 mV DC sweeps separately vary the common-mode or reference source. Separate 1 mV common-mode/reference or 100 mV differential steps start at 20 us, have 100 ns edges and last 40 us. The 100 us transient starts at DC, maximum step 20 ns. Rail power includes both diode bias devices, but excludes fixture driver losses. No external plant/servo, solver shunt or forced state.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `cmfb_002_5t_pmos_input`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. Magic uses ideal well/substrate tap connections; source simulation retains native finite tap models. This boundary does not establish distributed substrate resistance or substrate-noise accuracy.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 4 covers a compact gain/bias/passive network. Nonnegative common-mode and nonpositive reference DC slopes are functional sign-domain constraints. Both include zero and do not establish a minimum response magnitude. Reported response/ripple windows do not certify a closed-loop CM regulator or upstream optimization claims.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | Natural loaded output with zero CM error | bias / target; scale 1.5 | lower=0; upper=1.5 |\n| `power_w` | W | Rail power including dual-diode bias | supply / ratio; scale 1e-12 | lower=0 |\n| `signed_gain` | 1 | Real transfer at 1 Hz, selected CM/reference/differential input | response / target; scale 1 | Finite measurement |\n| `gain_1khz` | 1 | Magnitude at 1 kHz, selected excitation | response / target; scale 1 | Finite measurement |\n| `gain_100khz` | 1 | Magnitude at 100 kHz, selected excitation | response / target; scale 1 | Finite measurement |\n| `step_response_v` | V | Mean response 50–60 us minus 10–20 us | response / target; scale 0.01 | Finite measurement |\n| `ripple_v` | V | Recovery window output variation | response / ratio; scale 0.0001 | lower=0 |\n| `dc_cm_slope` | 1 | Centered 2 mV DC output slope for dc_cm_slope | response / target; scale 1 | lower=0 |\n| `dc_ref_slope` | 1 | Centered 2 mV DC output slope for dc_ref_slope | response / target; scale 1 | upper=0 |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; current-validity and KCL bounds distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **10500 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (15 units, sum 5245.926900 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **4**.\n\n\n### Score weights\n\nCommon-mode sensing/controllers: signed transfer 45%; ripple 19.3%; output bias 6.43%; power 19.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `dc_cm_slope` | 0.075000000000 |\n| `dc_ref_slope` | 0.075000000000 |\n| `gain_100khz` | 0.075000000000 |\n| `gain_1khz` | 0.075000000000 |\n| `signed_gain` | 0.075000000000 |\n| `step_response_v` | 0.075000000000 |\n| `ripple_v` | 0.192857142857 |\n| `output_v` | 0.064285714286 |\n| `power_w` | 0.192857142857 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml","case_sha256":"e7c7ec054ba2113ab41ab9c43a845ac046c5c90136a5c3a3cb533254145e0435","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl","netlist_sha256":"9d0cf10dd16c7a3e2e929dc7fe72dbfb0dd5f4d53f52574e92414e293c903d45","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.cmfb_004_output_switched_cap","in_core":false,"title":"MIM Switched-Capacitor Common-Mode Sampler","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Samples common-mode voltage using clocked switches and physical MIM capacitors.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_004_output_switched_cap","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# MIM Switched-Capacitor Common-Mode Sampler Layout Task\n\n## Objective\n\nImplement `cmfb_004_output_switched_cap` in IHP SG13G2 and submit a self-contained GDS. Sixteen minimum-size MOS (W/L = 0.15/0.13 um) implement eight transmission paths. Four internal MIM capacitors retain the original connections: two separate vbias-to-vcm capacitors and two floating control-to-sense capacitors. Each is a 25.85 by 25.85 um cap_cmim, nominally about 1.00647 pF. Explicit physical substrate and well taps are included. The output samples common-mode displacement; this is a switched-capacitor sensing network with driven inputs, not a complete closed-loop amplifier or a loop-stability qualification.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` supplies measurement apparatus. This problem is the description input. The ordered ports are `vinp vinn vcmfb vcm vbias clk_phi clk_phi_not vdd vss`: sensed positive/negative inputs, sampled control output, common-mode reference, control reference, two independent clock nets, supply and return.\n\nPreserve connectivity, MOS W/L/m, capacitor dimensions and unit multiplicities, and body/tap connections. Placement and routing are free. Device splitting/combination and source/drain interchange are allowed only when accepted by the declared native LVS equivalences. No common-centroid or statistical matching requirement is scored. All specified ideal external sources, loads and measurement apparatus belong outside the DUT.\n\n## Operating Conditions\n\nTypical IHP low-voltage MOS, typical resistor and capacitor models at 27 C; VDD = 1.5 V and VSS = 0 V. Each node has the declared 1e12 ohm numerical shunt. Transient integration uses Gear order 2 with a 1 ns output and maximum step. Physical taps have finite source-model resistance; Magic treats well/substrate ties ideally. Distributed silicon substrate resistance, statistical mismatch, PVT, noise and RF/EM are outside scope.\n\nVcm = 0.75 V; Vbias = 0.6 V. Each condition starts with input common mode 0.75 V. It changes linearly over 40–40.1 us to common_v, then holds through 100 us. Inputs are common mode +/- diff_v. The five (common_v, diff_v) pairs in volts are (0.65,0), (0.65,0.1), (0.75,0.1), (0.85,0), (0.85,0.1). Phi starts high, falls after 1 us, and alternates with its complementary independent clock; rise/fall times are 2 ns, low width 5 us and period 10 us. Phi high precharges the floating capacitors; phi low couples them to the sensed inputs and output. Finite complementary slopes permit overlap. An external 1 pF loads vcmfb; stop time is 100 us. The target after repeated transfers is 0.6 V + common_v - 0.75 V.\n\n## Physical Requirements\n\nThe GDS top cell is `cmfb_004_output_switched_cap`, with a 10 MiB maximum file size. Provide physical, correctly connected and accessible labeled interface metal; retain every named port. Pass IHP main and maximal DRC (density and antenna excluded for this standalone block), strict named-interface LVS and a functional bounding box no larger than 320 by 70 um. No DRC waivers are used. The functional footprint includes device, passive, implant, well and complete routing layers; excludes annotations/pin text and nonfunctional markers. Its explicit GDS layer/datatype set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. The area is the bounding-box area of those layers, not summed metal area.\n\nThe candidate GDS must pass artifact, DRC, LVS and hard geometry before extraction. Magic candidate-derived distributed interconnect resistance and capacitance, with zero coupling-capacitance threshold, feed the supplied testbench. Internal MIM devices remain in candidate extraction. Source simulation alone cannot establish acceptance. This is nominal block qualification, not fabrication signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | V(out) at 95 us | V | target / target | 0 … 1.5 | 1.5 |\n| `sample_error_v` | Maximum absolute V(out) minus [0.6 V + (V(vinp)+V(vinn))/2 - 0.75 V], over 92–95 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `hold_drift_v` | Maximum absolute V(out) minus its 95 us sample, over 96.1–99 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `clock_power_w` | Mean of max(0,-V(phi) I(VPH)) + max(0,-V(phin) I(VPL)), over 80–100 us; returned energy is not credited | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **5263.8 um2**. 22 expanded device instances; sum of device/contact envelopes 3414.7414 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCommon-mode sampler: sample accuracy 45%; hold drift 27%; output bias 4.5%; clock power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `sample_error_v` | 0.450000000000 |\n| `hold_drift_v` | 0.270000000000 |\n| `output_v` | 0.045000000000 |\n| `clock_power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed SG13G2 device/rule/model resources supplied through `/protocol/resources.json` and the task definitions in `/protocol/task.json`. KLayout supplies layout and physical checks; Magic supplies candidate RC; ngspice consumes the declared deck. Discover available feedback through the runtime harness protocol. Write `output/final.gds` in the workspace and explicitly submit that GDS through the submission protocol. Reference layouts, source checkouts and authoring scripts are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml","case_sha256":"285e435bc587d2d15059a5ca420ffba031121c3bccde510802bb3088f55f1725","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/circuit.cdl","netlist_sha256":"3a3ca59eef1a93dd54f0e78087fccb7e250f354833ec52950e1b0f425daef481","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.drv_001_pam4_sige_dac","in_core":true,"title":"Upstream broadband SiGe PAM4 current-steering driver","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Combines weighted current-steering cells into a SiGe PAM4 driver.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/drv_001_pam4_sige_dac","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Broadband SiGe PAM4 Driver Layout Task\n\n## Objective\n\nLay out the upstream inductorless, three-cell current-steering PAM4 driver as\n`pam4drv_pam4_lay`. One LSB cell and two parallel MSB cells contain twelve\nthree-finger `npn13G2` HBTs, twelve physical `rsil` resistors and three physical\nMIM degeneration capacitors. Preserve the supplied topology and dimensions.\nThe task coefficient is 4.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the native LVS authority;\n`materials/circuit.spice` is its simulator representation;\n`materials/testbench.spice` defines the electrical measurements.\n\nOrdered ports: `lsbp lsbn msbp msbn outp outn vcc vcasc vcmb tmsb0 tlsb0 tmsb1 sub`.\nThe first four ports are differential LSB/MSB inputs, `outp/outn` are differential\noutputs, `vcc` is the supply, `vcasc` biases the cascode bases, `vcmb` is the input\ntermination reference, the three tail ports connect to external current sinks,\nand `sub` is the ideal substrate reference. The three testbench VCCS tails are\nexternal bias apparatus, not missing physical transistors.\n\n## Operating Conditions\n\nUse the upstream **layout signoff point**, not its separate static sizing point:\n4 V supply, 3.35 V cascode bias, 1.9 V input common mode and 15 mA per cell.\nThe nominal corners are `hbt_typ`, `res_typ` and `cap_typ` at 27 °C. HBTs have\n`Nx=3`. Physical dimensions are fixed by the netlists; the nominal targets are\n50 Ω collector loads, 48 Ω input terminations, 3.2 Ω degeneration and 16 fF\nbridging capacitance. PDK geometry models determine their actual values.\n\nBoth RF ports use 50 Ω per side (100 Ω differential). AC gain is differential\npower-wave S21 = `2*Vout/Vsrc`, measured at 1 GHz; bandwidth is checked by the\n50 GHz gain relative to 1 GHz. S11 is evaluated at **32 GHz**, and S22 at\n**50 GHz**, using the testbench's 20 points/decade sweep and interpolation.\nDo not substitute the preceding sweep samples for these endpoints.\n\nThe large-signal test drives LSB and MSB in phase at 1 GHz through the same\nsource impedances, with ±0.8 V per source around 1.9 V. Supplies and bias ramp\nfrom zero over 8 ns; sine excitation starts at 9 ns. The 16–21 ns measurement\nwindow contains five periods. Swing is twice the fundamental phasor amplitude\nusing the exported transient samples, rather than raw peak-to-peak excursion.\n\n## Physical Requirements\n\nSubmit GDS with the exact top-cell name, all thirteen labeled ports, and at most\n10 MiB. Native SG13G2 DRC checks main and extra maximal rules without density or\nantenna; no marker waivers apply. Native LVS compares devices, dimensions,\nconnectivity and named ports. Functional width/height must not exceed 160/120 µm.\nThe published `outline` layer list covers HBT, resistor, MIM, substrate-contact,\nseven-metal and via geometry; pin/text and presentation layers are excluded.\n\nPost-layout simulation uses KPEX 0.3.12 nominal 2.5D **coupling capacitance** from\nthe submitted GDS. Native extracted devices are checked against the candidate's\nindependent LVS database. MIM devices retain extracted endpoints and `w/l/m`;\nno MIM layers are stripped and no source devices are reinserted. The process\nreference plane is tied to `sub`. Distributed wire resistance, inductance,\npads/package, statistical yield and process-corner robustness are not claimed\nby this upstream CC characterization contract. Finite substrate/tail-generator\ncircuits are outside the physical core. A PAM4 eye/RLM result is not established\nby these tone and small-signal checks.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nAll measurements and their paired source observations must be finite and usable.\nPerformance is scored continuously against the same-condition source circuit;\nupstream data-sheet targets are not acceptance thresholds. Supply consumption\nand output swing must be nonnegative; zero or otherwise unusable ratio baselines\ncannot establish a score. Physical checks remain mandatory.\n\n| Metric | Definition | Unit | Quality rule | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `lsb_gain_db` | LSB S21 at 1 GHz | dB | maximize / db20 | none |\n| `msb_gain_db` | MSB S21 at 1 GHz | dB | maximize / db20 | none |\n| `dac_weight_db` | MSB minus LSB gain | dB | source target | none |\n| `lsb_rel50_db` | LSB S21(50 GHz) minus S21(1 GHz) | dB | maximize / db20 | none |\n| `msb_rel50_db` | MSB S21(50 GHz) minus S21(1 GHz) | dB | maximize / db20 | none |\n| `s11_32g_db` | MSB input reflection coefficient, 20 log10(abs(S11)), at 32 GHz | dB | minimize / db20 | none |\n| `s22_50g_db` | Output reflection coefficient, 20 log10(abs(S22)), at 50 GHz | dB | minimize / db20 | none |\n| `power_mw` | Power drawn from the 4 V rail at OP | mW | minimize / ratio | ≥ 0 |\n| `swing_vpp` | Differential output fundamental swing | V | maximize / ratio | ≥ 0 |\n\nIndependent source simulation uses the same deck, conditions and models.\nResponse quality uses `db20` for gain,\nrelative bandwidth and reflection-coefficient dB, and a maximizing ratio for swing. Binary\nweight uses target normalization to its source value with a `20*log10(2)` dB scale, the ideal binary amplitude-weight interval. Supply quality uses a minimizing\npower ratio. Area quality is `Q = 10000 µm² / functional_area`. The frozen compact\nallowance is 4500 µm² for device rows + 2000 µm² for terminations/loads +\n3500 µm² for routing, vias and substrate contacts. Reflection-coefficient dB\nis the negative of positive return loss, so smaller values improve quality. Physical or electrical rejection scores zero; incomplete evaluation\ncannot establish success. The area target is a compact sizing allowance,\nnot the area of a qualified reference.\n\n\n### Score weights\n\nPAM4 SiGe driver: binary weighting 22.5%; high-frequency transfer 22.5%; port matching 18%; gain and swing 18%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `dac_weight_db` | 0.225000000000 |\n| `lsb_rel50_db` | 0.112500000000 |\n| `msb_rel50_db` | 0.112500000000 |\n| `s11_32g_db` | 0.090000000000 |\n| `s22_50g_db` | 0.090000000000 |\n| `lsb_gain_db` | 0.060000000000 |\n| `msb_gain_db` | 0.060000000000 |\n| `swing_vpp` | 0.060000000000 |\n| `power_mw` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **4 hours**.\n\nUse the reviewed SG13G2 resources and the runtime task/protocol metadata.\nNgspice must be ≥45 with `ngbehavior=hsa`, compiled R3_CMC support and the\nspecified HBT/capacitor models. The toolchain provides native KLayout checks,\ncandidate-derived KPEX capacitance and ngspice feedback. Write\n`/workspace/output/final.gds` and explicitly submit it through the runtime\nsubmission interface. Reference and maintainer material is not a solver input.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml","case_sha256":"f09f7966d5b3a9e727670b252db9e476e15ad0b10cf64b326897054b23acfdbe","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/circuit.cdl","netlist_sha256":"310d1f67d5d237cfc88525f26568c5bcf45680bb2e8141982600669ee81a2ead","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.ia_002_fan_chopper_simple","in_core":false,"title":"Fan Clocked Capacitive Instrumentation Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Processes differential signals with a clocked, capacitively coupled instrumentation amplifier.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_002_fan_chopper_simple","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Clocked Capacitive Instrumentation Amplifier Layout Task\n\n## Objective\n\nImplement the supplied 39 MOS, 2 R, 6 C circuit. Preserve the running input, feedback and output choppers. There is no CMFB. Do not add a servo, remove or disable signal/feedback branches, or change the fixed transistor sizing and bias contract.\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n`. Preserve these named connections.\n\nThe CDL and simulator netlist are equivalent physical representations. Use their exact ordered interface. Bias sources and clocks are external. Additional inch, fbch, g2 and summing-node ports are high-impedance monitors, with no external drives or loads. Every ideal upstream passive is implemented with physical MIM or high-poly primitives; no case requires another case's circuit or development source.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode and vref=0.6 V; vb1/vb2/vb3/vb4=0.5/0.75/0.45/0.55 V. Each complementary clock pair runs synchronously at 5 kHz with 50 ns rise/fall, 99.95 us pulse width and 200 us period. All positive phases align. Differential sinusoidal input is 10 mV peak at 100 and 200 Hz; load is 50 fF per output. Maximum timestep is 200 ns with adaptive edge resolution. The test runs 40 ms; 0–20 ms is discarded. The 20–40 ms observation spans 100 chop cycles and two/four signal cycles. Adjacent 20–30/30–40 ms windows report transfer variation. This is a finite-window observation of the full clocked circuit, not a claim of asymptotic periodic stability.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and named-interface LVS must pass without waivers. The functional bounding rectangle includes device, well, contact and complete routing layers, excluding annotations, and must fit 5000 by 1000 um. Native physical taps and all passive units are part of the contract.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nUse the supplied transient testbench on the extracted candidate. Time-weighted sine/cosine integrals give complex differential transfer and input admittance. Full-precision cumulative integrals at the 20/30/40 ms clock breakpoints avoid cancellation of rounded measurement averages. The summed endpoint error must not exceed 1 ps; this is measurement validity, not a circuit performance gate. Input impedance is the magnitude of differential voltage divided by differential source current, where input current is -(i(VP)-i(VN))/2. Residual RMS removes the measured DC and fundamental; full output peak-to-peak also includes signal and all ripple. It must not be represented as switching ripple alone. Input and feedback modulation errors compare clock-demodulated branch voltages to the associated external signals. Raw monitor waveforms support independent checking of the switching paths. Ordinary DC/AC does not replace these measurements.\n\nEvery measurement must be finite. Magnitudes, RMS values and total consumed supply/clock power have nonnegative physical domains. No paper gain, input-impedance boost or ripple specification is a hard gate. Slow common-mode excursions and finite-window variation are reported and scored, not suppressed with a CMFB. The source uses the identical physical devices, clocks, loads and observation windows in an independent simulation. No PAC/PNoise, PSS, noise, mismatch, PVT or supply-startup capability is claimed.\n\nArea quality is Q=71369.42 um2/functional area. The compact estimate sums MOS (W+2.4)(L+2.4), a 3.2² local tap envelope per MOS and one global tap, each MIM (side+2.4)², and forty (.5+2.4)(84.45+2.4) resistor envelopes per bias arm, then adds 50% routing allowance. It is independent of the witness. Gain and input-impedance magnitudes use source ratios; phase is diagnostic to avoid angular-wrap scoring; residual and window variation use inverse ratios with 1 uV floor; output bias uses 1.2 V target scale; power uses inverse ratios with 1 pW floor. Other observations are diagnostics. Coefficient 8 reflects clock modulation coupled to a compensated capacitive signal-feedback loop; no common-mode regulation is assumed.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `gain_vv` | `2*sqrt(dsmean^2+dcmean^2)/amplitude` | V/V | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `phase_deg` | `180*ph(dsmean+j(dcmean))/pi` | deg | diagnostic | −∞ … +∞ | — |\n| `zin_ohm` | `amplitude/(2*sqrt(ismean^2+icmean^2))` | ohm | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `admittance_real_s` | `-2*ismean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `admittance_imag_s` | `-2*icmean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `dm_mean_v` | `avg dm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `residual_rms_v` | `rms residual from=20m to=40m` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `ripple_pp_v` | `pp dm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_mean_v` | `avg cm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `cm_min_v` | `min cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `window_change_v` | `2*sqrt((dsfirst-dslast)^2+(dcfirst-dclast)^2)` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `modulation_error_rms_v` | `rms modulation_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `feedback_error_rms_v` | `rms feedback_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `power_w` | `avg supplied from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `clock_power_w` | `avg clocks from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `boundary_error_s` | `abs(time[i20]-20m)+abs(time[i30]-30m)+abs(time[i40]-40m)` | s | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\nThe 1 ps endpoint alignment check aborts simulation with a nonzero exit\nbefore invalid integrals are reported. Its residual is diagnostic; a failed\nvalidity check produces an evaluator error and unknown score, not electrical failure.\n\n\n### Score weights\n\nClocked instrumentation amplifiers: signal fidelity 31.3%; drift and ripple 19.6%; input impedance 15.7%; common-mode behavior 15.7%; supply and clock power 7.83%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_vv` | 0.156521739130 |\n| `residual_rms_v` | 0.156521739130 |\n| `window_change_v` | 0.195652173914 |\n| `zin_ohm` | 0.156521739130 |\n| `cm_mean_v` | 0.078260869565 |\n| `dm_mean_v` | 0.078260869565 |\n| `clock_power_w` | 0.039130434783 |\n| `power_w` | 0.039130434783 |\n\n## Tools and Submission\n\nSolve budget: **10 hours**.\n\nSubmit GDS top cell ia_002_fan_chopper_simple. Evaluation runs native DRC/LVS, geometry, Magic candidate-derived RC extraction and ngspice transient measurement using reviewed resources. Reference materials and source checkouts are not solver inputs.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml","case_sha256":"345627f61d37dc99db2d9b5010c2f0e22aa14f64075a0f9ccf78c9e870b5e688","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl","netlist_sha256":"97f83b5e7f5fb018b9212759ab77f039f748e14d2ef15280b1e4fc7730ba8afb","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.ia_003_fan_chopper_pf","in_core":false,"title":"Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Combines clocked capacitive instrumentation amplification with positive feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_003_fan_chopper_pf","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback Layout Task\n\n## Objective\n\nImplement the supplied 47 MOS, 2 R, 8 C circuit. Preserve the running input, feedback and output choppers, including the positive-feedback chopper and capacitors. There is no CMFB. Do not add a servo, remove or disable signal/feedback branches, or change the fixed transistor sizing and bias contract.\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not clk_chpf clk_chpf_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n pfch_p pfch_n`. Preserve these named connections.\n\nThe CDL and simulator netlist are equivalent physical representations. Use their exact ordered interface. Bias sources and clocks are external. Additional inch, fbch, g2 and summing-node and pfch ports are high-impedance monitors, with no external drives or loads. Every ideal upstream passive is implemented with physical MIM or high-poly primitives; no case requires another case's circuit or development source.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode and vref=0.6 V; vb1/vb2/vb3/vb4=0.5/0.75/0.45/0.55 V. Each complementary clock pair runs synchronously at 5 kHz with 50 ns rise/fall, 99.95 us pulse width and 200 us period. All positive phases align. Differential sinusoidal input is 10 mV peak at 100 and 200 Hz; load is 50 fF per output. Maximum timestep is 200 ns with adaptive edge resolution. The test runs 40 ms; 0–20 ms is discarded. The 20–40 ms observation spans 100 chop cycles and two/four signal cycles. Adjacent 20–30/30–40 ms windows report transfer variation. This is a finite-window observation of the full clocked circuit, not a claim of asymptotic periodic stability.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and named-interface LVS must pass without waivers. The functional bounding rectangle includes device, well, contact and complete routing layers, excluding annotations, and must fit 5000 by 1000 um. Native physical taps and all passive units are part of the contract.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nUse the supplied transient testbench on the extracted candidate. Time-weighted sine/cosine integrals give complex differential transfer and input admittance. Full-precision cumulative integrals at the 20/30/40 ms clock breakpoints avoid cancellation of rounded measurement averages. The summed endpoint error must not exceed 1 ps; this is measurement validity, not a circuit performance gate. Input impedance is the magnitude of differential voltage divided by differential source current, where input current is -(i(VP)-i(VN))/2. Residual RMS removes the measured DC and fundamental; full output peak-to-peak also includes signal and all ripple. It must not be represented as switching ripple alone. Input and feedback and positive-feedback modulation errors compare clock-demodulated branch voltages to the associated external signals. Raw monitor waveforms support independent checking of the switching paths. Ordinary DC/AC does not replace these measurements.\n\nEvery measurement must be finite. Magnitudes, RMS values and total consumed supply/clock power have nonnegative physical domains. No paper gain, input-impedance boost or ripple specification is a hard gate. Slow common-mode excursions and finite-window variation are reported and scored, not suppressed with a CMFB. The source uses the identical physical devices, clocks, loads and observation windows in an independent simulation. No PAC/PNoise, PSS, noise, mismatch, PVT or supply-startup capability is claimed.\n\nArea quality is Q=73567.47 um2/functional area. The compact estimate sums MOS (W+2.4)(L+2.4), a 3.2² local tap envelope per MOS and one global tap, each MIM (side+2.4)², and forty (.5+2.4)(84.45+2.4) resistor envelopes per bias arm, then adds 50% routing allowance. It is independent of the witness. Gain and input-impedance magnitudes use source ratios; phase is diagnostic to avoid angular-wrap scoring; residual and window variation use inverse ratios with 1 uV floor; output bias uses 1.2 V target scale; power uses inverse ratios with 1 pW floor. Other observations are diagnostics. Coefficient 9 reflects interacting positive/negative signal feedback and impedance control under clock modulation; no common-mode regulation is assumed.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `gain_vv` | `2*sqrt(dsmean^2+dcmean^2)/amplitude` | V/V | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `phase_deg` | `180*ph(dsmean+j(dcmean))/pi` | deg | diagnostic | −∞ … +∞ | — |\n| `zin_ohm` | `amplitude/(2*sqrt(ismean^2+icmean^2))` | ohm | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `admittance_real_s` | `-2*ismean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `admittance_imag_s` | `-2*icmean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `dm_mean_v` | `avg dm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `residual_rms_v` | `rms residual from=20m to=40m` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `ripple_pp_v` | `pp dm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_mean_v` | `avg cm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `cm_min_v` | `min cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `window_change_v` | `2*sqrt((dsfirst-dslast)^2+(dcfirst-dclast)^2)` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `modulation_error_rms_v` | `rms modulation_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `feedback_error_rms_v` | `rms feedback_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `power_w` | `avg supplied from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `clock_power_w` | `avg clocks from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `pf_error_rms_v` | `rms pf_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `boundary_error_s` | `abs(time[i20]-20m)+abs(time[i30]-30m)+abs(time[i40]-40m)` | s | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\nThe 1 ps endpoint alignment check aborts simulation with a nonzero exit\nbefore invalid integrals are reported. Its residual is diagnostic; a failed\nvalidity check produces an evaluator error and unknown score, not electrical failure.\n\n\n### Score weights\n\nClocked instrumentation amplifiers: signal fidelity 31.3%; drift and ripple 19.6%; input impedance 15.7%; common-mode behavior 15.7%; supply and clock power 7.83%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_vv` | 0.156521739130 |\n| `residual_rms_v` | 0.156521739130 |\n| `window_change_v` | 0.195652173914 |\n| `zin_ohm` | 0.156521739130 |\n| `cm_mean_v` | 0.078260869565 |\n| `dm_mean_v` | 0.078260869565 |\n| `clock_power_w` | 0.039130434783 |\n| `power_w` | 0.039130434783 |\n\n## Tools and Submission\n\nSolve budget: **10 hours**.\n\nSubmit GDS top cell ia_003_fan_chopper_pf. Evaluation runs native DRC/LVS, geometry, Magic candidate-derived RC extraction and ngspice transient measurement using reviewed resources. Reference materials and source checkouts are not solver inputs.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml","case_sha256":"0a8fe01b64575b18ec2f8ff36e376afd21c9db605c347689aaf31998b81c4cb6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl","netlist_sha256":"870cd5a0b88e0e29454c43f5d4c2e7c555b0ec9dd9f609f9c1e19f6b9258d71a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.ia_006_fan_chopper_cmfb","in_core":true,"title":"Clocked Capacitive Instrumentation Amplifier with Transistor CMFB","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Combines clocked capacitive instrumentation amplification with transistor common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_006_fan_chopper_cmfb","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Clocked Capacitive Instrumentation Amplifier with CMFB Layout Task\n\n## Objective\n\nImplement `ia_006_fan_chopper_cmfb`: a complete capacitively coupled differential\ninstrumentation amplifier with input, feedback and interstage/output chopping,\na two-stage amplifier and transistor common-mode feedback (CMFB). Preserve the\nphysical signal/feedback capacitors, both bias-return paths, compensation and\nthe actual common-mode controller. Validate operation with all clocks running.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit for native LVS.\n- `materials/circuit.spice`: equivalent process-model simulator representation.\n- `materials/testbench.spice`: independent bias, clocks, loads and measurements.\n\nThe ordered interface is:\n\n```text\nvinp vinn voutp voutn vref\nclk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not\nvdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm\ncore__vsum_p core__vsum_n\n```\n\nVINP/VINN and VOUTP/VOUTN are the differential input and output. VREF biases\nthe summing nodes through physical high-poly return arms; VREF_CM is the\nreference for the actual transistor common-mode controller. The four CORE__VB\nports supply the declared core bias voltages. The final two ports are\nhigh-impedance summing-node monitors: the testbench observes them without\napplying voltage/current drive, a servo or an external load. Keep these named\nconnections; they also distinguish the symmetric native LVS branches.\n\nUse the fixed models, dimensions, multiplicities and connections in the\nnetlist. The 46 source MOS groups have a maintained 61-finger implementation;\nparallel fingering/merging is allowed when all checks pass. Core matching pairs\nhave fixed total W*m/L and on-grid finger dimensions; do not replace them with\nunqualified model widths. NMOS and resistor bodies connect to SUB through the\nexplicit VSS substrate tap, and PMOS bodies to WELL through the VDD well tap.\nDo not drive the internal CMFB actuator VB4O externally.\n\nPhysical passive requirements are:\n\n| Branch | Physical implementation | Nominal value at TT, 27 C |\n| --- | --- | --- |\n| Each input arm | Four parallel 51.6 × 51.6 um `cap_cmim` units | 16.008384 pF |\n| Each capacitive feedback arm | One 23.11 × 23.11 um `cap_cmim` | 0.80480575 pF |\n| Each differential Miller path | One 51.6 × 51.6 um `cap_cmim` | 4.002096 pF |\n| CMFB actuator to VSS | One 25.85 × 25.85 um `cap_cmim` | 1.00646975 pF |\n| Each summing-node return to VREF | 41 series `rhigh` segments, W=1 um, L=180 um, m=1, b=0 | 10.46156 Mohm |\n| Each output-to-common-mode-sense arm | Four of the same high-poly segments | 1.02064 Mohm |\n\nThe input/feedback capacitor ratio is approximately 19.891. All internal\npassives are physical DUT devices, distinct from external output loads. Preserve\nMIM plate orientation. The maintained compensation is deliberately retuned for\nthe physical combined loop; the source's ideal 1 pF Miller / 1 fF controller\nvalues do not define this task.\n\n## Operating Conditions\n\nUse TT MOS/capacitor/resistor models at 27 C and VDD/VSS=1.2/0 V. VREF and\nVREF_CM are both 0.6 V. Relative to VSS, CORE__VB1/2/3/4 are respectively\n0.5/0.75/0.45/0.589 V. There is no ideal external output-common-mode or\ndifferential-feedback servo. Each output has a 1 pF or 5 pF external load.\nAt each load, run both signs of a 10 mV differential input step: four conditions.\n\nThe input common mode stays at 0.6 V. Both inputs initially equal 0.6 V.\nDuring 500–501 us they move to `0.6+step_v/2` and `0.6-step_v/2`, hold\nfor 500 us, then return during 1001–1002 us. `step_v` is +0.01 or −0.01 V.\nThe pulse period is 10 ms; only the finite 0–1.5 ms sequence is measured.\n\nAll three true/complement clock pairs run synchronously at 20 kHz between\n0 and 1.2 V. True clocks begin high, fall during 25–25.05 us, hold low for\n24.95 us, then rise during 50–50.05 us; the 50 us pattern repeats. Complement\nclocks have exactly opposite levels with the same 50 ns edges. Finite\ncomplementary slopes may produce overlap or dead intervals according to device\nthresholds; no ideal break-before-make behavior is assumed. Input, feedback and\noutput/interstage clocks all switch; frozen-clock gain is not an acceptance test.\n\nTransient starts from the solved DC operating point. Use Gear order 2, the\nKLU solver, maximum time step 500 ns, `rshunt=1e13`, `reltol=1e-5`,\n`abstol=1e-13` and `vntol=1e-8`. Save the declared port voltages and source\ncurrents. The settled observation windows contain integer clock periods;\nstartup from a zero-supply state is not covered.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ia_006_fan_chopper_cmfb`, no larger than 10 MiB.\nPass native IHP main/maximal DRC without waivers (standalone scope with\ndensity/antenna disabled), strict named-interface LVS including taps, and a\n3000 × 700 um functional outline. Device, contact and complete routing layers\nare enumerated by the runtime outline constraint. Pin/annotation layers are\nexcluded from area and cannot conceal functional geometry.\n\nThe submitted layout must provide the actual capacitors, resistor segments and\nmatching-aware core. Post-layout simulation consumes candidate-derived Magic\nRC with device junction geometry and interconnect. Extraction subdivides the\ninitial Magic grid by two and uses `gds_readonly=false` on an isolated import;\nthe submitted GDS remains immutable. No extraction diagnostic is waived.\nMagic idealizes the explicit tap devices while retaining its extracted RC\nnetwork; the source simulator includes finite tap models. Distributed substrate\nnoise and manufacturing signoff are not qualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `gain_vv` | Transient: `((avg (v(voutp)-v(voutn)) from=900u to=1m)-(avg (v(voutp)-v(voutn)) from=400u to=500u))/(2*((avg v(vinp) from=900u to=1m)-.6))`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `baseline_error_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=400u to=500u))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `return_error_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=1.4m to=1.5m)-(avg (v(voutp)-v(voutn)) from=400u to=500u))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `high_drift_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=950u to=1m)-(avg (v(voutp)-v(voutn)) from=900u to=950u))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `return_drift_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=1.45m to=1.5m)-(avg (v(voutp)-v(voutn)) from=1.4m to=1.45m))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `ripple_rms_v` | Transient: `sqrt((avg (((v(voutp)-v(voutn))-(avg (v(voutp)-v(voutn)) from=900u to=1m))^2) from=900u to=1m))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `ripple_pp_v` | Transient: `(max (v(voutp)-v(voutn)) from=900u to=1m)-(min (v(voutp)-v(voutn)) from=900u to=1m)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_mean_v` | TRAN: Mean of `((v(voutp)+v(voutn))/2) from=900u to=1m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `cm_min_v` | TRAN: Minimum of `((v(voutp)+v(voutn))/2) from=400u to=1.5m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `cm_max_v` | TRAN: Maximum of `((v(voutp)+v(voutn))/2) from=400u to=1.5m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `sum_cm_v` | TRAN: Mean of `((v(monp)+v(monn))/2) from=900u to=1m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `sum_error_v` | Transient: `abs((avg ((v(monp)-v(monn))*(v(clk_chin)/.6-1)) from=900u to=1m))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-1.2*i(VDD)) from=400u to=1.5m`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `clock_power_w` | Mean sum of positive delivered power from all six chopper clock sources over 900 us–1 ms; negative (returned) power from each source is clipped to zero before summation. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_cm_v` | DC operating point: `(v(voutp)+v(voutn))/2`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `dc_dm_v` | DC operating point: `v(voutp)-v(voutn)`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `baseline_v` | TRAN: Mean of `(v(voutp)-v(voutn)) from=400u to=500u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `plateau_v` | TRAN: Mean of `(v(voutp)-v(voutn)) from=900u to=1m`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `return_v` | TRAN: Mean of `(v(voutp)-v(voutn)) from=1.4m to=1.5m`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `dc_power_w` | DC operating point: `-1.2*i(VDD)`. | W | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n\nArea reference: **102216.79 um2**. 166 expanded device instances; sum of device/contact envelopes 67727.1707 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **10**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nClocked instrumentation amplifiers: signal fidelity 37.9%; drift and ripple 23.7%; common-mode behavior 18.9%; supply and clock power 9.47%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `baseline_error_v` | 0.126315789472 |\n| `gain_vv` | 0.126315789474 |\n| `return_error_v` | 0.126315789474 |\n| `high_drift_v` | 0.059210526316 |\n| `return_drift_v` | 0.059210526316 |\n| `ripple_pp_v` | 0.059210526316 |\n| `ripple_rms_v` | 0.059210526316 |\n| `cm_max_v` | 0.037894736842 |\n| `cm_mean_v` | 0.037894736842 |\n| `cm_min_v` | 0.037894736842 |\n| `sum_cm_v` | 0.037894736842 |\n| `sum_error_v` | 0.037894736842 |\n| `clock_power_w` | 0.047368421053 |\n| `mean_power_w` | 0.047368421053 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover frozen task inputs, requirements, reviewed resources and harness\nfeedback in `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the supplied IHP primitives and KLayout, Magic\nand ngspice. Write `/workspace/output/final.gds` and explicitly submit through\nthe harness protocol. Source records, reference GDS and host configuration\nremain outside standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml","case_sha256":"7ca1dc67f774b163a585dd222d9cc95f30cd5f15085f5bb2d30ab8a403ce83f2","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/circuit.cdl","netlist_sha256":"e5049836e133e951c36c34dd5eed0fe1c2492f1671930153c97cf4ccae786f1d","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.ldo_001_analoggym_basic","in_core":false,"title":"Multistage Error-Amplifier PMOS Regulator","pdk":"ihp-sg13g2","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_001_analoggym_basic","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Multistage Error-Amplifier PMOS Regulator Layout Task\n\n## Objective\n\nLay out `ldo_001_analoggym_basic`: a PMOS pass regulator with a folded\nPMOS-input error amplifier, cascoded bias branches, mirrored loads and an\nadditional PMOS/NMOS intermediate branch driving the pass-gate node `net1`.\nThe auxiliary PMOS source and body connect to `net1`; the input pair has a\nseparate source-tied `net20` well. Internal compensation connects `net106`\nto output and the 3:1 physical divider returns one quarter of output voltage.\nThis complete multistage error amplifier and its internal pass-gate drive\nare distinct from the simpler 5T and mirror-OTA regulator cases.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical circuit.\n- `materials/circuit.spice`: matching simulator circuit with finite taps.\n- `materials/testbench.spice`: bilateral loop and current-load recovery.\n- `materials/startup.spice`: synchronized zero-state resistive startup.\n- `materials/sweeps.spice`: line/load and downward headroom sweeps.\n\nOrdered ports: `vdd vout vss ib vref vfb sense`. VDD/VSS are supply/return,\nVOUT output, IB connects an external current sink to VSS, and VREF is the\nexternal reference. VFB is the physical divider midpoint and SENSE is the\ninverting error-amplifier input. Connect them only through the testbench's\nzero-volt injection link; no additional servo or feedback element is permitted.\nThe source's zero-volt output measurement link is collapsed into VOUT and\nrelocated to this explicitly declared divider/input boundary.\n\nRetain all 24 source MOS groups. Integer regrouping converts 1,168 source\nfingers into 831 physical fingers with <=10 um individual width, preserving\neach original group's total W, L and body connection exactly. Individual W/m\nand diffusion perimeter change, so the maintained simulator and extracted\ncandidate are qualified independently. Other PMOS bodies use the VDD well;\nNMOS bodies and physical high-poly backplates use the VSS substrate contact.\nExplicit 2 x 2 um substrate/well taps use <=20 um pitch. Preserve the current\nnative circuit's dimensions and total multiplicities; equivalent parallel\nfingering requires all physical and electrical checks to pass.\n\nAll internal passives are physical DUT elements:\n\n- Three parallel 42.685 × 42.685 um `cap_cmim` units: top `net106`, bottom VOUT;\n approximately 8.22 pF total, retaining the source's approximately 8.2 pF branch.\n- One 51.64 × 51.64 um `cap_cmim`: top `net10`, bottom VOUT, approximately\n 4 pF. This added physical local compensation closes the internal dynamic mode.\n- Twelve series `rhigh` segments from VOUT to VFB and four from VFB to VSS,\n each W=1 um, L=17.465 um, b=0: approximately 300/100 kohm total.\n\nThere is no additional external output capacitor, but the compensation is\nreal output-connected storage. Do not delete or idealize any internal passive.\n\n## Operating Conditions\n\nThe loop/load testbench allows 1000 DC operating-point iterations (`itl1=1000`)\nfor both source and extracted simulations. Error tolerances and physical stimuli\nare unchanged; this is a convergence setting, not added circuit damping.\n\nUse typical IHP LV MOS/MIM/poly models at 27 C. VDD is 1.2 or 1.3 V,\nVREF=0.225 V, and the external IB-to-VSS sink is 8 uA. The reference is\nexplicitly changed from the normalized source's 0.4 V: the 3:1 divider then\nhas a 0.9 V ideal output target, within the LV supply. The 8 uA bias and\nall original total MOS widths/lengths are retained. This is a bounded\nregulator core, not a precision reference, PVT or manufacturing-signoff task.\n\nMain measurements cover both supplies and initial current loads 0.2/0.5 mA.\nAfter an operating point, the load doubles at 2–2.2 us, remains high for\n8 us, and returns at 10.2–10.4 us; the period is 16 us. Simulate 0–18 us\nwith KLU, Gear order 2, maximum step 1 ns, `rshunt=1e12`, `reltol=1e-5`,\n`abstol=1e-12` and `vntol=1e-8`. The numerical shunt is not a physical\nbias or startup device. Explicit `.save` lists retain all measured vectors;\nevery extracted circuit element still participates in the solve.\n\nMeasure the bilateral return ratio at the actual divider/input boundary:\nfirst inject unit series AC voltage from SENSE to VFB, with zero parallel\ncurrent; then use zero series voltage and unit current into SENSE. With\nfirst-run `b=-I(VPROBE)`, `d=V(SENSE)` and second-run `a=-I(VPROBE)`,\n`c=V(SENSE)`, define `delta=a*d-b*c` and\n`T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian et al., Eq. 30).\nBoth injections retain divider, input and reverse-path loading. Exported\nvoltages/currents permit an independent two-port admittance calculation.\nSweep 0.01 Hz–1 GHz at 300 points/decade, using continuous natural phase\nwithout an arbitrary low-frequency offset. Check first/final descending\nunity crossings, minimum sampled `abs(1+T)`, full sampled return-difference\nphase and maximum 200 MHz–1 GHz gain. This finite external-loop contract\nis not an exhaustive proof of all internal poles.\n\nSweep load 0.2–1 mA in 10 uA steps at each supply. Downward VDD sweeps\n1.3–0.8 V in 1 mV steps at 0.2/1 mA measure the first 30 mV output-error\ncrossing. The line span uses both endpoints of 1.2–1.3 V. The regulation\nfloor includes amplifier headroom and is not a pass-resistance-only dropout\nrating. These DC sweeps do not extend dynamic stability to every intermediate\nsupply/load combination.\n\nStartup uses `uic` with supply, reference and bias ramping together from zero\nin 10 or 20 us. For both supplies, use 900/4500 ohm resistive loads (nominally\n1/0.2 mA at 0.9 V), maximum step 2 ns, and simulate to 50 us. This does not\nqualify arbitrary sequencing or a constant-current load imposed at zero supply.\nFaster 1 us startup and 20 ns current-load edges are outside qualification: they\nproduce excessive peaks in the same extracted circuit. The README provides\nrunnable failure probes. The maintained contract explicitly narrows the\ninitial development stimuli without relaxing the voltage-excursion bounds.\nLoads below 0.2 mA are outside the qualified dynamic range.\n\nFirst and final crossing phase margins must both lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nmetrics affect continuous quality without adding a stability acceptance screen.\nMissing crossings or invalid observations are evaluator errors.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ldo_001_analoggym_basic`, at most 32 MiB. Pass native\nIHP main/maximal DRC without waivers (standalone density/antenna disabled),\nstrict named-interface LVS with explicit taps, and a 5500 × 360 um functional\nenvelope. All device/contact/interconnect drawing layers in the runtime\n`outline` contribute to area; annotation and pin-purpose layers do not.\n\nCandidate-derived Magic RC includes both capacitor plates, every poly segment,\nMOS and interconnect parasitic. Half-grid import and zero parasitic thresholds\nare explicit. Native LVS checks the original GDS's tap labels; the Magic\nextraction copy retains only Metal3 interface text, avoiding internal well-name\naliases without altering geometry. Magic idealizes well/substrate taps while\nsource simulation includes their finite models. Distributed substrate\nresistance/noise and fabrication signoff remain unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `bias_v` | DC operating point: `v(ib)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-@iload[current]`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 1g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 1g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=200meg to=1g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `minimum_v` | TRAN: Minimum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_v` | TRAN: Maximum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `recovery_load_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_release_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `loaded_ripple_v` | Transient: `(max v(vout) from=9u to=9.5u)-(min v(vout) from=9u to=9.5u)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `released_ripple_v` | Transient: `(max v(vout) from=17u to=17.5u)-(min v(vout) from=17u to=17.5u)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_error_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=40u to=49u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_peak_v` | TRAN: Maximum of `v(vout) from=0 to=50u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `startup_minimum_v` | TRAN: Minimum of `v(vout) from=0 to=50u`. | V | target / target | −∞ … +∞ | 1.3 | response |\n| `regulation_floor_v` | DC: Crossing coordinate where `(abs(v(vout)-0.9))=0.03 rise=1`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `headroom_v` | DC sweep: `(when (abs(v(vout)-0.9))=0.03 rise=1)-(find v(vout) when (abs(v(vout)-0.9))=0.03 rise=1)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n\nArea reference: **42364.42 um2**. 1240 expanded device instances; sum of device/contact envelopes 27974.3733 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **9**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nIHP regulators: regulation and headroom 22.5%; load recovery 22.5%; startup 13.5%; loop stability 13.5%; AC transfer and extrema 4.5%; internal bias 1.8%; quiescent current 7.2%; power 4.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `headroom_v` | 0.045000000000 |\n| `line_span_v` | 0.045000000000 |\n| `load_span_v` | 0.045000000000 |\n| `output_v` | 0.045000000000 |\n| `regulation_floor_v` | 0.045000000000 |\n| `loaded_ripple_v` | 0.056250000000 |\n| `recovery_load_v` | 0.056250000000 |\n| `recovery_release_v` | 0.056250000000 |\n| `released_ripple_v` | 0.056250000000 |\n| `startup_error_v` | 0.045000000000 |\n| `startup_minimum_v` | 0.045000000000 |\n| `startup_peak_v` | 0.045000000000 |\n| `final_phase_margin_deg` | 0.033750000000 |\n| `minimum_return_distance` | 0.033750000000 |\n| `phase_margin_deg` | 0.033750000000 |\n| `return_phase_excursion_deg` | 0.033750000000 |\n| `dc_gain_db` | 0.007500000000 |\n| `final_unity_hz` | 0.007500000000 |\n| `hf_gain_db` | 0.007500000000 |\n| `maximum_v` | 0.007500000000 |\n| `minimum_v` | 0.007500000000 |\n| `unity_hz` | 0.007500000000 |\n| `bias_v` | 0.018000000000 |\n| `quiescent_a` | 0.072000000000 |\n| `mean_power_w` | 0.022500000000 |\n| `power_w` | 0.022500000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover task/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied\nIHP primitives and KLayout/Magic/ngspice. Write `/workspace/output/final.gds`\nand explicitly submit via the harness protocol. Host configuration, source\nrecords and reference answers are excluded from standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml","case_sha256":"53db61a2e3fbe8b58aaf94ca5228beb06b42fe8688ff538676485d51ede6fca6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl","netlist_sha256":"eebb188d9aa510eb1d03395ad2a4fe8b12ca6e4e16d4172dbd4d72bad3d0d79b","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.ldo_008_fer_mirror_ota","in_core":true,"title":"Mirror-OTA Regulator with Bilateral Return-Ratio Measurements","pdk":"ihp-sg13g2","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_008_fer_mirror_ota","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Mirror-OTA Regulator with Bilateral Return-Ratio Measurements Layout Task\n\n## Objective\n\nImplement `ldo_008_fer_mirror_ota`: a mirror-loaded NMOS-input error amplifier,\ndiode/tail bias network, PMOS pass device, feedback divider and series R/C\ncompensation. Preserve all seven source MOS groups as 81 physical fingers,\n40 MIM units and three high-poly resistors, with explicit substrate/well taps.\nThe internal compensation and divider remain part of the DUT.\n\nMOS dimensions and multiplicities are unchanged from the fixed IHP binding.\nThe source 160 pF capacitor becomes forty 51.64 um square MIM units, nominally\n160.331872 pF total. The source 2 kohm compensation resistor becomes one\nW=1 um / L=1.325 um `rhigh`; each source 9 kohm divider resistor becomes one\nW=1 um / L=6.235 um `rhigh`, with m=1 and b=0. Source capacitor PLUS is\n`czero`, MINUS is `vout`; the series resistor connects `egate` to `czero`.\nDivider upper/lower connect `vout–fb` and `fb–vss`. Every passive stays physical.\n\nThe external source bias is unchanged at 20 uA from VDD to NBIAS. The external\nreference is deliberately changed from the source 0.6 V to **0.5 V**, giving\na nominal 1.0 V output and defined headroom at 1.2/1.3 V supply. There is no\nseparate internal or external COUT; compensation still provides physical\noutput-connected capacitance. This is not a claim of zero internal storage.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: equivalent simulator representation.\n- `materials/testbench.spice`: DC bias, bilateral loop measurements and load steps.\n- `materials/startup.spice`: zero-state resistive-load startup.\n- `materials/sweeps.spice`: DC line/load and regulation-headroom sweeps.\n- `materials/fast.spice`: short, finely resolved load-impulse response.\n\nOrdered ports: `vdd vout vss nbias vref fb sense`. VDD/VSS are supply/return;\nVOUT is output; NBIAS receives the supply-fed current; VREF receives the 0.5 V\nreference. FB is the physical divider junction and SENSE is the amplifier's\nfeedback-input gate. Connect SENSE externally to FB through the zero-volt\nmeasurement source. This external link replaces the raw VLP's measurement role;\nit is not a manufactured voltage source. The relocated break exposes the\nactual input/divider boundary; the upper divider still connects to output.\nPMOS bodies connect through the VDD well tap; NMOS/poly bodies through the VSS\ntap. Preserve every W/L/m, body connection and physical passive. Equivalent\nparallel finger arrangements require native LVS and every other check to pass.\n\n## Operating Conditions\n\nUse typical IHP LV MOS, MIM and resistor models at 27 C. Main conditions are\nall combinations of VDD=1.2/1.3 V and initial load 0.1/0.5 mA. The current\nload doubles at 2–2.02 us and returns at 10.02–10.04 us. Run to 18 us with\n1 ns maximum step, Gear order 2, `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`\nand `vntol=1e-8`. Startup and fast tests use the same accuracy tolerances.\n\nFor AC, independent supply/reference/load sources have no AC excitation.\nPerform two sweeps, 0.01 Hz–1 GHz at 300 points/decade, at the same operating\npoint. VPROBE is oriented SENSE→FB and IINJ from ground→SENSE. Both have\nzero DC value and are ordinary external test sources. First set VPROBE AC=1 V,\nIINJ AC=0; second set VPROBE AC=0, IINJ AC=1 A. The 1 A is only a normalized\nlinear AC excitation, not a physical large-signal load.\n\nLet B=−I(VPROBE)/1 V and D=V(SENSE)/1 V from the first sweep; A=−I(VPROBE)/1 A\nand C=V(SENSE)/1 A from the second. With delta=AD−BC, define\n`T=(2*delta−A+D)/(1−2*delta+A−D)`. This bilateral two-port return ratio includes\nboth directional transmissions and port loading. The old voltage-only\n`−V(FB)/V(SENSE)` is not the accepted loop metric. Reset the circuit before\ntransient analysis; neither AC experiment changes its DC or transient topology.\n\nThis measures the declared external feedback loop with the internal circuit\nretained. It is not an exhaustive pole proof for all internal device loops or\nan RF/model-validity claim beyond the declared tests. Both first and final crossing phase margins must lie in [0, 180] degrees.\nThe full-sweep return-distance and return-phase metrics have only nonnegative\ndomain bounds; high-frequency gain is unbounded. They affect continuous\nquality without adding a stability acceptance screen.\n\nStartup uses 1/10 kohm loads and simultaneous linear supply/reference/bias\nramps from zero over 1/10 us: eight combinations including both supplies.\nRun with `uic`, no internal-node initial conditions, to 30 us with 2 ns\nmaximum step. Startup qualification is resistive-load and synchronized-ramp\nonly, not arbitrary reference sequencing or constant-current startup.\n\nDC sweeps: supply decreases from 1.3 to 0.8 V by 1 mV at 0.1/1 mA; line\nspan is measured over 1.2–1.3 V. Regulation floor is the first increasing\ncrossing of `abs(VOUT−1.0)=0.03 V`. Headroom is supply **minus actual output at\nthat crossing**, not supply minus the nominal target. The lower supply sweep\nis a boundary probe, not an extended qualified operating range. Separately\nsweep load 0.1–1 mA by 10 uA at each qualified supply, retaining both endpoints.\n\nFast conditions use the four main DC biases and a +1 uA load pulse beginning\nat 1 ns, 5 ps rise/fall and 1 ns high time. Run 100 ns with 5 ps maximum step.\nIt probes fast recovery around the solved operating point without modifying\ncompensation, adding an output capacitor or clamping an internal node.\n\nTransient extrema and AC sweep screens use the saved in-window samples;\nDC crossing locations and mean power use interpolation/integration. Numerical\nqualification also checks interpolated recovery-window endpoints.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ldo_008_fer_mirror_ota`, at most 10 MiB. Native main/maximal\nDRC has no waivers (standalone scope, density/antenna disabled). Strict named-port\nLVS includes physical taps. Functional outline is at most 3350 × 310 um and\nincludes all device, passive, contact and routing drawing layers; annotation\nand pin-purpose layers do not contribute. Magic candidate RC must preserve\nall physical MOS/MIM/poly and interconnect parasitics. Half-grid import is\nexplicit; extraction idealizes taps whereas source simulation uses their finite\nmodels. Distributed substrate resistance, PVT, mismatch, noise, fabrication\nsignoff and arbitrary-load stability are outside qualification.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `bias_v` | DC operating point: `v(nbias)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-@iload[current]`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 1g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 1g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=200meg to=1g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `minimum_v` | TRAN: Minimum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_v` | TRAN: Maximum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `recovery_load_v` | TRAN: Maximum of `(abs(v(vout)-1.0)) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_release_v` | TRAN: Maximum of `(abs(v(vout)-1.0)) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `startup_error_v` | TRAN: Maximum of `(abs(v(vout)-1.0)) from=25u to=30u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_peak_v` | TRAN: Maximum of `v(vout) from=0 to=30u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `startup_minimum_v` | TRAN: Minimum of `v(vout) from=0 to=30u`. | V | target / target | −∞ … +∞ | 1.3 | response |\n| `regulation_floor_v` | DC: Crossing coordinate where `(abs(v(vout)-1.0))=0.03 rise=1`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `headroom_v` | DC sweep: `(when (abs(v(vout)-1.0))=0.03 rise=1)-(find v(vout) when (abs(v(vout)-1.0))=0.03 rise=1)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `fast_peak_v` | Maximum absolute deviation of transient VOUT from its initial DC operating-point value over 0–100 ns in the fast load-pulse deck. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `fast_tail_v` | The same absolute deviation from initial DC VOUT over 80–100 ns. | V | target / target | 0 … 1.3 | 1.3 | response |\n\nArea reference: **172708.78 um2**. 126 expanded device instances; sum of device/contact envelopes 114596.5905 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **9**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nIHP regulators: regulation and headroom 22.5%; load recovery 22.5%; startup 13.5%; loop stability 13.5%; AC transfer and extrema 4.5%; internal bias 1.8%; quiescent current 7.2%; power 4.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `headroom_v` | 0.045000000000 |\n| `line_span_v` | 0.045000000000 |\n| `load_span_v` | 0.045000000000 |\n| `output_v` | 0.045000000000 |\n| `regulation_floor_v` | 0.045000000000 |\n| `recovery_load_v` | 0.112500000000 |\n| `recovery_release_v` | 0.112500000000 |\n| `startup_error_v` | 0.045000000000 |\n| `startup_minimum_v` | 0.045000000000 |\n| `startup_peak_v` | 0.045000000000 |\n| `final_phase_margin_deg` | 0.033750000000 |\n| `minimum_return_distance` | 0.033750000000 |\n| `phase_margin_deg` | 0.033750000000 |\n| `return_phase_excursion_deg` | 0.033750000000 |\n| `dc_gain_db` | 0.005625000000 |\n| `fast_peak_v` | 0.005625000000 |\n| `fast_tail_v` | 0.005625000000 |\n| `final_unity_hz` | 0.005625000000 |\n| `hf_gain_db` | 0.005625000000 |\n| `maximum_v` | 0.005625000000 |\n| `minimum_v` | 0.005625000000 |\n| `unity_hz` | 0.005625000000 |\n| `bias_v` | 0.018000000000 |\n| `quiescent_a` | 0.072000000000 |\n| `mean_power_w` | 0.022500000000 |\n| `power_w` | 0.022500000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use supplied IHP\nprimitives, KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Source records, host configuration\nand reference layouts stay outside standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml","case_sha256":"0112b24633297076d0939a9aa711cb2221e1205f570acd15f48196bc31f04326","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/circuit.cdl","netlist_sha256":"810d7fc0b63340bbd097f338e2a5c7fed29aaa5a51370abe30fc28b80297e1db","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.ldo_009_fer_5t_pass","in_core":false,"title":"Unity-Feedback Regulator with Internal Output Storage","pdk":"ihp-sg13g2","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_009_fer_5t_pass","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Unity-Feedback Regulator with Internal Output Storage Layout Task\n\n## Objective\n\nLay out `ldo_009_fer_5t_pass` with the complete physical error amplifier, pass array,\ncompensation, output storage, bleeder and reference path.\n\nA five-transistor NMOS-input error amplifier drives a PMOS pass array;\nan on-chip diode-connected NMOS biases the tail mirror. The maintained circuit\nretains all seven source MOS groups (29 physical fingers), the output bleeder,\nreference-series resistor, Miller path and internal output capacitor. Unity\nfeedback senses output directly; there is no feedback divider. This adds\nphysical output storage, a reference impedance, explicit return ratio and\nzero-state startup to the existing externally loaded regulator coverage.\n\nThe original 2 pF Miller compensation is deliberately retuned to five physical\n36.515 um square units, nominally 10.0293 pF. Thirteen 50.635 um square MIM\nunits retain the approximately 50 pF internal COUT. Four physical high-poly\nsegments implement the approximately 100 kohm bleeder and one implements\napproximately 10 kohm reference resistance. MOS dimensions and multiplicities\nare unchanged; explicit substrate/well taps are added. The 20 uA bias source\nand 0.9 V reference are external. The raw zero-volt loop measurement source\nbecomes an external zero-volt link between distinct output and sense ports;\nit is not a manufactured voltage-source device or an ideal common-mode servo.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model representation.\n- `materials/testbench.spice`: operating point, return ratio and load steps.\n- `materials/startup.spice`: distinct zero-state resistive-load startup deck.\n- `materials/sweeps.spice`: distinct DC line/load and headroom sweeps.\n\nOrdered ports: `vdd vout vss nbias ref0 sense`. VDD/VSS are supply/return;\nVOUT is regulated output; NBIAS receives an external 20 uA source **from VDD**;\nREF0 receives an external 0.9 V reference; SENSE connects externally to VOUT\nthrough the zero-volt probe. Preserve this explicit high-impedance feedback\ninterface. No other drive is permitted on SENSE, and no extra internal servo\nor reference generator is part of the DUT. PMOS bodies connect to the VDD\nwell through its tap; NMOS/poly bodies connect through the VSS substrate tap.\nPreserve all W/L/m and internal connectivity; equivalent parallel fingers\nare permitted only when native LVS and all measurements pass.\n\nAll following passives remain physical DUT devices, not external loads or\nparasitic annotations:\n\n- `cmil`: `vout` to `otao`, 5 parallel 36.515 × 36.515 um MIM units, nominal total 10.029301 pF.\n- `cout`: `vout` to `vss`, 13 parallel 50.635 × 50.635 um MIM units, nominal total 50.101434 pF.\n- `rbld`: `vout` to `vss`, 4 series high-poly segments, each W=1 um / L=17.465 um, m=1 and b=0.\n- `rref`: `ref0` to `vref`, 1 series high-poly segments, each W=1 um / L=6.94 um, m=1 and b=0.\n\n## Operating Conditions\n\nUse typical LV MOS, MIM and resistor models at 27 C. Qualification uses\nVDD=1.2/1.3 V and REF0=0.9 V. The main deck starts from a solved operating\npoint with 0.1/0.5 mA constant-current loads; each doubles at 2–2.02 us and\nreturns at 10.02–10.04 us. Run to 18 us with 1 ns maximum step, Gear order 2,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThere is no external output capacitor: internal COUT remains in candidate RC.\n\nAC injects 1 V in series with the zero-volt output-to-SENSE link. Reference,\nsupply and current sources have zero AC drive. At the high-impedance MOS input\nboundary, `T=-V(vout)/V(sense)` defines return ratio. Sweep 0.01 Hz–1 GHz\nat 150 points/decade. Gain uses `20 log10(abs(T))`; continuous phase has no\nfitted offset. Unity frequency is the first descending 0 dB crossing and phase\nmargin is 180 degrees plus phase there. Missing crossings are errors.\n\nStartup separately uses 900/9000 ohm output loads, with supply, reference and\nbias ramped linearly together from zero over 1/10 us. Use `uic`, no internal\nnode initial conditions and 2 ns maximum step to 30 us. The load is resistive\nthroughout startup; this is not constant-current startup qualification. All\neight supply/load/ramp combinations must pass. After startup, the main deck's\nconstant-current load contract and its finite recovery windows apply separately.\n\nDC sweeps use the same numerical tolerances. Sweep supply downward from 1.3\nto 0.8 V in 1 mV steps at 0.1/1 mA; measure line span only over 1.2–1.3 V.\nThe **regulation floor** is the first rising crossing of\n`abs(VOUT−0.9)=0.03 V` on that downward sweep. `headroom_v` is this supply\nminus 0.9 V. This includes error-amplifier headroom or pass-device limitation;\nit is not a pass-resistance-only dropout rating. The sweep below the floor is\na boundary probe and is not a qualified low-supply operating range. Separately,\nsweep load 0.1–1 mA in 10 uA steps at each qualified supply for load span.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ldo_009_fer_5t_pass`, at most 10 MiB. Pass native main/maximal\nDRC with no waivers (standalone scope, density/antenna disabled), strict\nnamed-interface LVS including taps, and a 1600 × 330 um functional envelope.\nThe runtime outline includes complete device/contact/routing drawing layers;\nannotation and pin-purpose layers do not contribute to bounding-box area.\nCandidate Magic RC must retain all physical MOS/MIM/poly and interconnect\nparasitics. Half-grid GDS import is explicit. Magic idealizes tap connections;\nsource simulation uses finite contact models. Distributed substrate resistance,\nnoise, PVT, mismatch, arbitrary startup/reference sequencing, brownout and\nfabrication signoff remain unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `bias_v` | DC operating point: `v(nbias)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-@iload[current]`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(sense)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(sense))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(sense)))/pi) when (db((-v(vout)/v(sense))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_v` | TRAN: Minimum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_v` | TRAN: Maximum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `recovery_load_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_release_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `startup_error_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=25u to=30u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_peak_v` | TRAN: Maximum of `v(vout) from=0 to=30u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `startup_minimum_v` | TRAN: Minimum of `v(vout) from=0 to=30u`. | V | target / target | −∞ … +∞ | 1.3 | response |\n| `regulation_floor_v` | DC: Crossing coordinate where `(abs(v(vout)-0.9))=0.03 rise=1`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `headroom_v` | DC sweep: `(when (abs(v(vout)-0.9))=0.03 rise=1)-0.9`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n\nArea reference: **65470.09 um2**. 54 expanded device instances; sum of device/contact envelopes 43312.7759 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nIHP regulators: regulation and headroom 22.5%; load recovery 22.5%; startup 13.5%; loop stability 13.5%; AC transfer and extrema 4.5%; internal bias 1.8%; quiescent current 7.2%; power 4.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `headroom_v` | 0.045000000000 |\n| `line_span_v` | 0.045000000000 |\n| `load_span_v` | 0.045000000000 |\n| `output_v` | 0.045000000000 |\n| `regulation_floor_v` | 0.045000000000 |\n| `recovery_load_v` | 0.112500000000 |\n| `recovery_release_v` | 0.112500000000 |\n| `startup_error_v` | 0.045000000000 |\n| `startup_minimum_v` | 0.045000000000 |\n| `startup_peak_v` | 0.045000000000 |\n| `phase_margin_deg` | 0.135000000000 |\n| `dc_gain_db` | 0.011250000000 |\n| `maximum_v` | 0.011250000000 |\n| `minimum_v` | 0.011250000000 |\n| `unity_hz` | 0.011250000000 |\n| `bias_v` | 0.018000000000 |\n| `quiescent_a` | 0.072000000000 |\n| `mean_power_w` | 0.022500000000 |\n| `power_w` | 0.022500000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives, KLayout, Magic and ngspice. Write `/workspace/output/final.gds` and\nexplicitly submit it through the harness. Host configuration, source records\nand reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml","case_sha256":"774402d4f540f236c7e54b4eb60eba62f666693a84801777e06517d2eaeefcee","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/circuit.cdl","netlist_sha256":"1788fa17f1811dd7e6596e6edc5c2edde837c878b590084fd239855c89ba50a4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.smp_001_nmos_th","in_core":true,"title":"Physical NMOS Sample-and-Hold: Headroom and Retention","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Samples and holds a voltage with an NMOS switch and an internal storage capacitor.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/smp_001_nmos_th","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Physical NMOS Sample-and-Hold Layout Task\n\n## Objective\n\nImplement `smp_001_nmos_th`: a single-NMOS sampling switch with an internal\nphysical storage capacitor. Preserve the switch and stored-charge node, and\nmeet acquisition, turn-off pedestal, isolated-input feedthrough, hold drift\nand reacquisition requirements at the specified input and temperature points.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical circuit.\n- `materials/circuit.spice`: equivalent simulator representation.\n- `materials/testbench.spice`: independent stimuli and measurements.\n\nThe ordered interface is `vin clk vout vss`. VIN is driven through an external\n1 kohm source resistance; CLK receives the external clock; VOUT is the storage\nnode. The source's unused VDD port is removed. There is no DUT supply-current\nmetric or added artificial supply connection. Tie VSS to ground.\n\nRetain the `sg13_lv_nmos` with W=2 um, L=0.13 um, m=1 and drain/gate/source\nconnected to VIN/CLK/VOUT. Its body connects through the explicit VSS substrate\ntap. One `cap_cmim` with W=L=18.2 um connects its top plate to VOUT and bottom\nplate to VSS, nominally 499.772 fF at TT, 27 C. Preserve plate orientation.\nThe capacitor is internal physical storage, not a testbench load or an ideal\nreplacement. The native and simulator circuits include the same explicit tap.\n\nPreserve models, sizes and connectivity. Equivalent parallel fingering is\npermitted only when all physical and electrical checks pass. Do not add a\nbuffer, complementary switch, dummy cancellation device, hold-node servo,\nexternal storage capacitor or other topology change.\n\n## Operating Conditions\n\nUse typical MOS and capacitor models at 27 and 85 C. CLK is externally driven\nbetween 0 and 1.2 V, with 2 ns linear transitions. The ideal signal source SRC\ndrives VIN through 1 kohm. Qualify four sampled levels, `sample_v` = 0.1, 0.4,\n0.6 and 0.7 V, at both temperatures. At each point the off-state input is\nseparately driven to `hold_v` = 0 or 1.2 V: sixteen conditions. These are\nspecified sample points, not rail-to-rail or continuous-range qualification.\n\nThe finite sequence starts from a solved DC operating point with SRC=0 and\nCLK=1.2 V. SRC moves to `sample_v` during 20–22 ns. CLK falls during\n200–202 ns, isolating the storage node. SRC moves to `hold_v` during\n400–402 ns while CLK remains zero. SRC returns to `sample_v` during\n11.2–11.202 us; CLK rises during 11.4–11.402 us. Stop at 11.7 us.\nNo output load, DC bias source or discharge resistor is attached to VOUT.\n\nUse Gear order 2, KLU, maximum time step 2 ns, `gmin=1e-15`,\n`rshunt=1e15`, `reltol=1e-6`, `abstol=1e-15` and `vntol=1e-9`.\nThe numerical shunt is not a specified physical retention load. Save SRC,\nVIN, CLK, VOUT and both ideal voltage-source currents.\n\n## Physical Requirements\n\nSubmit GDSII top cell `smp_001_nmos_th`, at most 10 MiB, within an 80 × 80 um\nfunctional outline. Pass native IHP main/maximal DRC without waivers\n(standalone scope with density/antenna disabled), strict named-port LVS,\nfunctional geometry and candidate-derived Magic RC extraction. Functional\narea includes the complete device/contact/routing layers enumerated by the\nruntime outline; annotation and pin layers do not count.\n\nPost-layout simulation must consume the submitted layout's extracted NMOS,\nphysical MIM, junction geometry and interconnect RC. The isolated Magic import\nuses half-grid subdivision and `gds_readonly=false`; the submitted GDS remains\nimmutable. No diagnostic is waived. Source simulation retains the finite tap\nmodel; Magic idealizes the tap connection. Distributed substrate noise and\nfabrication signoff are outside this contract.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `track_error_v` | Maximum absolute VOUT minus target over 80–190 ns; target is VSRC sampled at 180 ns. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `pedestal_abs_v` | Absolute difference between VOUT at 220 ns and 180 ns (held minus tracked sample). | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `feedthrough_peak_v` | Maximum absolute VOUT minus its 390 ns sample over 400–450 ns, during the input transition in hold. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `hold_drift_v` | Absolute difference between VOUT at 11 us and 1 us. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `hold_error_v` | Maximum absolute VOUT minus target over 220 ns–11 us; target is VSRC at 180 ns. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `reacquire_error_v` | Maximum absolute VOUT minus target over 11.48–11.69 us; target is VSRC at 180 ns. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `clock_energy_j` | Integral of max(-V(CLK)*I(VCLK), 0) over 0–11.7 us; returned clock energy is excluded. | J | minimize / ratio | 0 … +∞ | 1e-21 | supply |\n| `target` | TRAN: Value of `v(src) at=180n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `track_v` | TRAN: Value of `v(vout) at=180n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `held_v` | TRAN: Value of `v(vout) at=220n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `before_input_v` | TRAN: Value of `v(vout) at=390n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `after_input_v` | TRAN: Value of `v(vout) at=450n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `hold_start_v` | TRAN: Value of `v(vout) at=1u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `hold_end_v` | TRAN: Value of `v(vout) at=11u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `reacquired_v` | TRAN: Value of `v(vout) at=11.65u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `pedestal_v` | Signed VOUT(220 ns) − VOUT(180 ns). | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `feedthrough_v` | Signed VOUT(450 ns) − VOUT(390 ns). | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `drift_v` | Signed VOUT(11 us) − VOUT(1 us). | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n\nArea reference: **661.39 um2**. 3 expanded device instances; sum of device/contact envelopes 407.6560 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTrack/hold switches: acquisition 35%; hold fidelity 45%; clock energy 10%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `reacquire_error_v` | 0.175000000000 |\n| `track_error_v` | 0.175000000000 |\n| `feedthrough_peak_v` | 0.112500000000 |\n| `hold_drift_v` | 0.112500000000 |\n| `hold_error_v` | 0.112500000000 |\n| `pedestal_abs_v` | 0.112500000000 |\n| `clock_energy_j` | 0.100000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`\nfor the frozen inputs, requirements, reviewed IHP primitives and harness\nfeedback. Work with the supplied KLayout, Magic and ngspice resources.\nWrite `/workspace/output/final.gds` and explicitly submit through the harness.\nReference GDS, source records and host configuration are not standard inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml","case_sha256":"1be1c1ee7e3f211added229b308a5fcb1b07d2610bf187ef2d0c2606b7285fae","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/circuit.cdl","netlist_sha256":"846cb6797fae4bca4b793d23239e778299f46ec0b3342e44d2a014ca5d6b3802","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.sw_001_transmission_gate_pair","in_core":false,"title":"Bidirectional CMOS Transmission Gate","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Transfers analog signals bidirectionally through a CMOS transmission gate.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_001_transmission_gate_pair","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Bidirectional CMOS Transmission Gate Layout Task\n\n## Objective\n\nImplement `sw_001_transmission_gate_pair` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. The fixed IHP binding has one NMOS and one PMOS, each W=2 um, L=0.13 um, m=1. Both connect the bidirectional signal terminals, with the NMOS body at vss and PMOS body at vdd. No internal clock generator is added.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/forward.spice`, `materials/reverse.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `port_a port_b vctl vctl_not vdd vss`. The fixture supplies complementary controls externally. Both signal/control ports stay within 0–1.5 V. Native body taps remain physically checked; finite well/substrate resistances are outside the Magic RC compact-model boundary.\n\n## Operating Conditions\n\n1.5 V supply. DC on/off conditions use signal common modes 0.15, 0.75 and 1.35 V and both signs of a 10 mV port difference. On controls are 1.5/0 V; off controls are 0/1.5 V. Ron is the absolute port drop divided by actual port-source current, accepted only above 1 nA and independently checked for the correct current direction. Off leakage uses held voltages at both terminals. Dynamic tests drive each direction separately through 100 ohm, with a 1 pF receiving load and 1 Mohm resistor to the selected common mode. Signal steps are common-mode ±50 mV with 1 ns edges starting at 20 ns; separate static-input runs isolate control feedthrough. Complementary controls turn off at 70 ns for 60 ns, with matched 1 ns edges, no extra overlap/dead interval. Runs start from DC and end at 180 ns with maximum 50 ps steps. The finite receiving resistance defines the off-node behavior physically. The isolated window-marker source only schedules exact time breakpoints; it connects to no DUT terminal.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `sw_001_transmission_gate_pair`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. Magic uses ideal well/substrate tap connections; source simulation retains native finite tap models. This boundary does not establish distributed substrate resistance or substrate-noise accuracy.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 3 covers local bidirectional analog conduction and loaded control transitions. Tracking error is integrated over exactly 20–60 ns; control-edge excursion uses the inclusive 69–75 ns sample window; held mean shift compares 90–100 ns with 65–69 ns. These are loaded feedthrough/hold observations, not an intrinsic charge-injection constant or perfect floating-node retention. No energy score is claimed: body-rail current alone cannot measure control and signal-driver energy.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `ron_ohm` | ohm | 10 mV DC port drop divided by measured port current | response / ratio; scale 1 | lower=0 |\n| `on_current_a` | A | Absolute DC on current; excludes numerical-noise division | unscored / functional | lower=1e-09 |\n| `leakage_a` | A | Off-state current with both ports held at defined voltages | bias / ratio; scale 1e-12 | lower=0 |\n| `kcl_a` | A | External KCL including control and body sources | diagnostic; unscored | Producer validity guard; see below |\n| `tracking_error_v` | V | Mean loaded dynamic tracking error, 20–60 ns | response / ratio; scale 0.0001 | lower=0 |\n| `feedthrough_v` | V | Output excursion during turn-off, 69–75 ns | response / ratio; scale 0.0001 | lower=0 |\n| `hold_shift_v` | V | Finite loaded hold mean 90–100 ns minus 65–69 ns | response / target; scale 0.1 | Finite measurement |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **300 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (2 units, sum 130.080000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **3**.\n\n\n### Score weights\n\nTransmission/chopper switches: on-state conduction 21.4%; off-state leakage 17.1%; transfer fidelity 25.7%; switching disturbance 25.7%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `ron_ohm` | 0.214285714286 |\n| `leakage_a` | 0.171428571429 |\n| `tracking_error_v` | 0.257142857143 |\n| `feedthrough_v` | 0.128571428571 |\n| `hold_shift_v` | 0.128571428571 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-09 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml","case_sha256":"1b1360f0bb6680a736fdc9041626be634b9b576aa5cfc8c85e6c0b41321ec7a7","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl","netlist_sha256":"541f878fd2a9d6f0eab4f125d64563a2a2e56b0deb4fa7adef4d2db88adc11cf","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.sw_002_chopper_diff","in_core":false,"title":"Differential Polarity-Commutating Switch","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Commutates differential signal polarity with a clock-controlled switch network.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_002_chopper_diff","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Differential Polarity-Commutating Switch Layout Task\n\n## Objective\n\nImplement `sw_002_chopper_diff` in ihp-sg13g2 and submit self-contained GDS. Eight MOS devices form four transmission paths that connect a differential input directly or with reversed polarity. The two complementary clock nets are independent layout ports. Fixed IHP W/L/m are retained; explicit substrate/well taps are included in both maintained circuit representations.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit. `materials/circuit.spice` is its equivalent simulator model-call representation. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `va_p va_n vb_p vb_n vctl vctl_not vdd vss`. In order: Positive input, negative input, positive output, negative output, direct-path clock, complementary clock, supply, and return.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical IHP low-voltage MOS and resistor models; explicit finite physical tap models and a 1e12 ohm ngspice numerical shunt at each node. Candidate Magic RC is extracted with zero coupling-capacitance threshold.\n\nVDD = 1.5 V; VSS = 0 V; input common mode = 0.75 V; differential input = -0.2 or +0.2 V. Each output has an external 10 kohm resistor to common mode and 1 pF to ground. DC checks both clock states (vctl = 0 or 1.5 V), giving four conditions. Transient clocks are complementary 0/1.5 V pulses, delay 1 us, rise/fall 2 ns, high width 5 us and period 10 us; output/max step is 0.1 ns with Gear order 2, stop time 12 us. A second transient sets both inputs to 0.75 V to separate clock feedthrough/injection from signal reversal. The finite clock slopes deliberately permit overlap; non-overlap operation is not claimed.\n\n## Physical Requirements\n\nTop cell `sw_002_chopper_diff`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, IHP main and maximal DRC, with density and antenna outside this standalone scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 90 by 40 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. Ron includes the declared terminal loading and common mode. Injection is net terminal charge integrated under driven equal inputs, not stored charge on a disconnected sampler. Noise, chopping an amplifier, RF/EM, mismatch and other clock rates are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 4 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `ron_p` | Absolute (selected positive-output input minus V(vb_p)) / current through its 10 kohm load | ohm | minimize / ratio | 0 … +∞ | 1e-06 |\n| `ron_n` | Absolute (selected negative-output input minus V(vb_n)) / current through its 10 kohm load | ohm | minimize / ratio | 0 … +∞ | 1e-06 |\n| `transfer` | DC output differential divided by the selected signed input differential | V/V | target / target | −∞ … +∞ | 1.0 |\n| `common_error_v` | Absolute DC output common-mode minus 0.75 V | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `straight_gain` | Output differential / input differential at 4 us | V/V | target / target | −∞ … +∞ | 1.0 |\n| `crossed_gain` | Output differential / input differential at 9 us | V/V | target / target | −∞ … +∞ | 1.0 |\n| `common_glitch_v` | Maximum absolute output common-mode minus 0.75 V over 1–1.1 us with equal inputs | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `differential_glitch_v` | Maximum absolute output differential over 1–1.1 us with equal inputs | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `input_charge_c` | Absolute integral of I(VAP)+I(VAN) over 1–1.1 us with equal inputs | C | minimize / ratio | 0 … +∞ | 1e-21 |\n| `clock_power_w` | Average positive supplied power from both clock sources over 2–12 us with equal inputs; returned energy is not credited | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **459.68 um2**. 10 expanded device instances; sum of device/contact envelopes 278.7760 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTransmission/chopper switches: on-state conduction 23.7%; transfer fidelity 28.4%; switching disturbance 28.4%; clock power 9.47%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `ron_n` | 0.118421052632 |\n| `ron_p` | 0.118421052632 |\n| `common_error_v` | 0.071052631579 |\n| `crossed_gain` | 0.071052631579 |\n| `straight_gain` | 0.071052631579 |\n| `transfer` | 0.071052631579 |\n| `common_glitch_v` | 0.094736842105 |\n| `differential_glitch_v` | 0.094736842105 |\n| `input_charge_c` | 0.094736842105 |\n| `clock_power_w` | 0.094736842105 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml","case_sha256":"684990b80dc0182f03f2ab08b93f9e005165274c0db7e444ab00845b3b618a4b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/circuit.cdl","netlist_sha256":"e0b1c58cdd6e35af46612beae826db9d950ca0e83ddb0297ee224699fd9c3c7a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.sw_003_binary_capbank","in_core":true,"title":"Three-Bit MIM Capacitive Transfer Bank","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Selects capacitive transfer using a three-bit bank of physical MIM capacitors.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_003_binary_capbank","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Three-Bit MIM Capacitive Transfer Bank Layout Task\n\n## Objective\n\nImplement `sw_003_binary_capbank` in IHP SG13G2 and submit a self-contained GDS. Twelve minimum-size MOS (W/L = 0.15/0.13 um) select the bottom plates of a 1:1:2:4 MIM capacitor bank between vinp and VCM. Eight identical 25.85 by 25.85 um cap_cmim units implement those weights, each nominally about 1.00647 pF. Explicit physical substrate and well taps are included. For code k, the ideal capacitive transfer is (1+k)/8. Qualification covers all eight static codes and bipolar input steps at each fixed code; live code transitions, ADC conversion, charge redistribution after a code change and mismatch linearity are outside scope.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` supplies measurement apparatus. This problem is the description input. The ordered ports are `vinp vout VCM VDD VSS V_D0 V_D0_NOT V_D1 V_D1_NOT V_D2 V_D2_NOT`: signal input, floating output, common-mode reference, supply/return and three independent pairs of complementary code controls. SPICE names are case-insensitive; preserve these physical labels.\n\nPreserve connectivity, MOS W/L/m, capacitor dimensions and unit multiplicities, and body/tap connections. Placement and routing are free. Device splitting/combination and source/drain interchange are allowed only when accepted by the declared native LVS equivalences. No common-centroid or statistical matching requirement is scored. All specified ideal external sources, loads and measurement apparatus belong outside the DUT.\n\n## Operating Conditions\n\nTypical IHP low-voltage MOS, typical resistor and capacitor models at 27 C; VDD = 1.5 V and VSS = 0 V. Each node has the declared 1e12 ohm numerical shunt. Transient integration uses Gear order 2 with a 1 ns output and maximum step. Physical taps have finite source-model resistance; Magic treats well/substrate ties ideally. Distributed silicon substrate resistance, statistical mismatch, PVT, noise and RF/EM are outside scope.\n\nAll eight binary codes are separate required conditions. Bit k is driven by 1.5*bk V and its complement by 1.5*(1-bk) V; controls remain static. VCM = 0.75 V. VINP has DC 0.65 V and unit AC amplitude. AC uses 50 points/decade from 1 kHz to 100 MHz; acceptance measurements are at 10 kHz. VINP stays at 0.65 V through 10 us, rises to 0.85 V at 10.002 us, holds through 30 us, returns to 0.65 V at 30.002 us and holds through 50 us. Vout has an external 1e12 ohm return to ground, in addition to the numerical shunt; no ideal external holding capacitor is added. Absolute output DC is not a retained sample requirement: measurements compare increments. The testbench expected-value voltage source is measurement apparatus only.\n\n## Physical Requirements\n\nThe GDS top cell is `sw_003_binary_capbank`, with a 10 MiB maximum file size. Provide physical, correctly connected and accessible labeled interface metal; retain every named port. Pass IHP main and maximal DRC (density and antenna excluded for this standalone block), strict named-interface LVS and a functional bounding box no larger than 460 by 75 um. No DRC waivers are used. The functional footprint includes device, passive, implant, well and complete routing layers; excludes annotations/pin text and nonfunctional markers. Its explicit GDS layer/datatype set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. The area is the bounding-box area of those layers, not summed metal area.\n\nThe candidate GDS must pass artifact, DRC, LVS and hard geometry before extraction. Magic candidate-derived distributed interconnect resistance and capacitance, with zero coupling-capacitance threshold, feed the supplied testbench. Internal MIM devices remain in candidate extraction. Source simulation alone cannot establish acceptance. This is nominal block qualification, not fabrication signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `gain_vv` | Magnitude V(out)/V(vinp) at 10 kHz, unit AC input | V/V | target / target | −∞ … +∞ | 1.0 |\n| `phase_deg` | Phase of V(out)/V(vinp) at 10 kHz, in degrees | deg | target / target | −∞ … +∞ | 180 |\n| `input_cap_f` | Imaginary part of -I(VI), divided by 2 pi f at 10 kHz, unit AC input | F | minimize / ratio | 0 … +∞ | 1e-21 |\n| `gain_error` | Absolute gain_vv minus (1+code)/8 | V/V | minimize / ratio | 0 … +∞ | 1e-09 |\n| `step_gain` | [V(out) at 29 us minus V(out) at 9 us] / 0.2 V | V/V | target / target | −∞ … +∞ | 1.0 |\n| `step_error` | Absolute step_gain minus (1+code)/8 | V/V | minimize / ratio | 0 … +∞ | 1e-09 |\n| `return_error_v` | Absolute V(out) at 49 us minus V(out) at 9 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `settling_error_v` | Maximum absolute V(out) minus its 29 us value, over 20–29 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n\nArea reference: **9532.78 um2**. 22 expanded device instances; sum of device/contact envelopes 6227.9559 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nBinary capacitor bank: code transfer accuracy 54%; recovery 27%; phase 9%; area 10%. Each objective's weight is divided equally among its metrics. Redundant transfer and loading observations are retained with zero weight; their measurement validity and bounds still apply.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_error` | 0.270000000000 |\n| `step_error` | 0.270000000000 |\n| `return_error_v` | 0.135000000000 |\n| `settling_error_v` | 0.135000000000 |\n| `phase_deg` | 0.090000000000 |\n| `gain_vv` | 0 |\n| `input_cap_f` | 0 |\n| `step_gain` | 0 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed SG13G2 device/rule/model resources supplied through `/protocol/resources.json` and the task definitions in `/protocol/task.json`. KLayout supplies layout and physical checks; Magic supplies candidate RC; ngspice consumes the declared deck. Discover available feedback through the runtime harness protocol. Write `output/final.gds` in the workspace and explicitly submit that GDS through the submission protocol. Reference layouts, source checkouts and authoring scripts are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml","case_sha256":"0a972bb98c65bf095dda4123587fecb7a0e3ff15be1e8692216a0a64ae098123","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/circuit.cdl","netlist_sha256":"dec8a6b73b1345482fdf6cf69f3065c000b7cf50ddebe04ee1738603f0b24c77","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.trm_001_vcr","in_core":false,"title":"Resistor-Pullup NMOS Shunt Trim","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Controls a resistor-pulled output using an NMOS shunt driven by an analog voltage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/trm_001_vcr","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Resistor-Pullup NMOS Shunt Trim Layout Task\n\n## Objective\n\nImplement `trm_001_vcr`, a voltage-controlled NMOS shunt with a physical\napproximately 200 kohm supply pullup. Preserve the source W=2 um / L=0.5 um\nNMOS, eight series high-poly segments and explicit substrate tap. Qualification\nmeasures loaded trim range, monotonic control, operating-point conductance,\ntemperature/load sensitivity and finite control-step recovery. This is an\nunbuffered nonlinear control node, not an ideal programmable resistor or DAC.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model representation.\n- `materials/testbench.spice`: control sweeps, conductance and loaded recovery.\n\nOrdered ports: `vdd vcode vout vss`. VDD is supply, VCODE controls the shunt\nMOS gate, VOUT is the pullup/shunt junction and VSS is return. The NMOS source\nand substrate connect through the explicit VSS tap; the physical poly body\nuses the same substrate. Eight series `rhigh` segments connect VDD to VOUT,\neach W=1 um / L=17.465 um, m=1 and b=0. They replace the source ideal 200 kohm\nresistor and remain inside the DUT. Preserve device models, dimensions and\nconnectivity; native equivalent resistor merging is allowed only when LVS and\nall other checks pass. There are no internal ideal sources or extra bias ports.\n\n## Operating Conditions\n\nTypical IHP LV MOS/poly models, all eight combinations of supplies 1.1/1.3 V,\ntemperatures 27/85 C and external output loads 500 kohm/1 Mohm. A 1 pF output\nload is external test apparatus. DC operating point uses VCODE=0.4 V.\nSweep VCODE from 0.2 to 0.8 V in 2 mV increments; every sampled slope must\nsatisfy maximum_slope <= 0 V/V: increasing NMOS gate control must not\nincrease the pullup/shunt output voltage. This is the declared sampled sweep,\nnot a proof of global monotonicity beyond the control interval.\n\nFor transient, VCODE rises 0.3→0.5 V at 2–2.02 us and falls at\n10.02–10.04 us, repeating every 16 us. Run to 18 us with 2 ns maximum step,\nGear order 2, `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nNo output clamp, feedback servo or ideal storage is internal to the DUT.\n\n## Physical Requirements\n\nSubmit GDSII top cell `trm_001_vcr`, at most 10 MiB. Pass native main/maximal DRC\nwithout waivers (standalone scope, density/antenna disabled), strict named-port\nLVS with explicit tap and a 110 × 80 um functional outline. The runtime\noutline includes complete device, resistor, contact and routing drawing layers;\nannotation/pin-purpose layers do not contribute to its area.\nCandidate Magic RC must preserve physical MOS/poly and interconnect parasitics.\nThe extractor idealizes the substrate contact; source simulation includes the\nfinite tap model. Distributed substrate effects, PVT, mismatch, noise,\nprecision trimming and fabrication signoff remain outside qualification.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `high_v` | DC VOUT at VCODE=0.2 V. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `low_v` | DC VOUT at VCODE=0.8 V. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `knee_code_v` | First VCODE value where VOUT falls through 0.2 V during the 0.2–0.8 V code sweep (2 mV steps). | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_slope` | Maximum sampled derivative dVOUT/dVCODE over 0.2–0.8 V; nonpositive is the declared sign-domain bound. | V/V | target / target | −∞ … 0 | 0.1 | response |\n| `span_v` | VOUT at VCODE=0.2 V minus VOUT at VCODE=0.8 V. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `conductance_04_s` | Shunt conductance [-I(VDD) − VOUT/RLOAD]/VOUT at VCODE=0.4 V; subtract external load current. | S | target / target | −∞ … +∞ | 0.00015 | response |\n| `conductance_06_s` | The same shunt-conductance definition at VCODE=0.6 V. | S | target / target | −∞ … +∞ | 0.0005 | response |\n| `conductance_ratio` | conductance_06_s / conductance_04_s, using the same load and temperature. | 1 | target / target | −∞ … +∞ | 5 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-(avg v(vout) from=9u to=9.5u))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-(avg v(vout) from=17u to=17.5u))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `step_span_v` | Transient: `(avg v(vout) from=17u to=17.5u)-(avg v(vout) from=9u to=9.5u)`. | V | target / target | 0 … 1.3 | 1.3 | response |\n\nHigh/low endpoints are continuous source-paired quality observations. Their\n0–1.3 V bounds express the nonnegative, supply-limited output domain; shunt-control function does not require a narrower absolute endpoint range.\n\nArea reference: **636.57 um2**. 10 expanded device instances; sum of device/contact envelopes 391.7515 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nVoltage-controlled trim element: control characteristic 36%; conductance 22.5%; loaded recovery 18%; operating range 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `knee_code_v` | 0.090000000000 |\n| `maximum_slope` | 0.090000000000 |\n| `span_v` | 0.090000000000 |\n| `step_span_v` | 0.090000000000 |\n| `conductance_04_s` | 0.075000000000 |\n| `conductance_06_s` | 0.075000000000 |\n| `conductance_ratio` | 0.075000000000 |\n| `recovery_down_v` | 0.090000000000 |\n| `recovery_up_v` | 0.090000000000 |\n| `high_v` | 0.015000000000 |\n| `low_v` | 0.015000000000 |\n| `output_v` | 0.015000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Host configuration, source records\nand reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml","case_sha256":"9a9d46760b695a72297235a62f694c4bf1ff8cb8f2f63cd37846f37aa659c587","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/circuit.cdl","netlist_sha256":"ed94062ae8c8856ffe51593d5134a9926c266e6620767f13d491a21ad288136a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"ihp-sg13g2.analog-db.vref_001_vgs","in_core":false,"title":"Mixed LV/HV VGS Reference with Picoampere Load and Zero-State Recovery","pdk":"ihp-sg13g2","category":"Power & references","summary":"Establishes a voltage reference using a mixed low/high-voltage two-transistor core.","source_url":"https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/raw/vref_001_vgs/ihp-sg13g2/_dut.spice","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Mixed LV/HV VGS Reference Layout Task\n\n## Objective\n\nImplement the two-transistor `vref_001_vgs` reference with its original device\nsizes and connections. An upper LV NMOS has gate and source at VREF; a lower\nHV NMOS is diode-connected. The maintained function is a high-impedance,\napproximately 0.36 V reference for picoampere loads. It is not a bandgap,\nprecision reference, buffered supply or temperature sensor.\n\n## Inputs and Interface\n\nThe declared inputs are this description, `materials/circuit.cdl` for native\nLVS, the equivalent `materials/circuit.spice`, and `materials/testbench.spice`.\nOrdered ports are `vdd vref vss`: positive supply, reference output, and return.\nThe LV NMOS has W/L=2.5/2 um, D=VDD, G=S=VREF, B=VSS. The HV NMOS has\nW/L=1/2 um, D=G=VREF, S=B=VSS. Both multiplicities are one.\n\nRetain the explicit 40 × 2 um marked substrate tap (A=80 um², P=84 um),\nwith both terminals on VSS. An unmarked substrate contact establishes that\nsame-net body boundary. Additional legal same-net contacts are permitted\nonly when native LVS and the declared checks pass. Do not replace the HV\ndevice with an LV device or change either gate/source connection. The source\nsimulator represents the marked tap with its finite 5.9756097561 ohm PDK\nequivalent; its two terminals are the same net. Parallel fingering is allowed\nonly if total dimensions, multiplicity, body mapping and all checks agree.\n\n## Operating Conditions\n\nUse the pinned IHP typical LV/HV PSP models. Nine jobs combine VDD=1.0,\n1.2 and 1.5 V with temperatures −20, 27 and 85 °C. The only external\ncapacitance is 100 fF from VREF to VSS. No numerical `rshunt` is added.\nUse `gmin=1e-16 S`, `reltol=1e-6`, `abstol=1e-18 A`, `vntol=1e-10 V`,\nGear order two and maximum transient step 1 us. These small currents require\nthe specified numerical conditioning; default simulator tolerances do not\nestablish this contract.\n\nFor each job, the DC operating point has the declared supply and zero load.\nThe separate transient starts with VREF=0 and otherwise zero stored charge\n(`uic`). VDD rises linearly from zero to its declared value over 100 us.\nThe run ends at 50 ms. ILOAD is positive when withdrawing current from VREF:\n0→+1 pA during 10–10.01 ms, +1→0 pA during 20–20.01 ms,\n0→−1 pA during 30–30.01 ms, and −1→0 pA during 40–40.01 ms.\nIt holds each value between edges. Negative load is an external current\ninjection, not on-chip power generation.\n\nEach job also sweeps supply 1.0–1.5 V in 10 mV increments at its declared\ntemperature, load −1–+1 pA in 0.1 pA increments at its declared supply and\ntemperature, and temperature −20–85 °C in 5 °C increments at its declared\nsupply. DC sweeps have no time-varying stimulus; line and temperature sweeps\nuse zero load. All endpoints participate. These are finite sampled conditions,\nnot process-corner, mismatch or arbitrary temperature/load guarantees.\nThe DC load sweep uses a −1–+1 V external control in 0.1 V increments and\na 1 pA/V transconductance stimulus; it avoids a tiny-current sweep endpoint\ntolerance without changing the DUT or its actual −1–+1 pA load range.\n\n## Physical Requirements\n\nSubmit a GDSII with top cell `vref_001_vgs`, at most 1 MiB. It must pass\nnative main/maximal SG13G2 DRC without waivers, strict named-port LVS, and a\n100 × 100 um functional outline. Density and antenna checks are outside\nthe declared standalone DRC scope. The footprint includes every device,\ncontact and routing drawing layer enumerated in the runtime constraints;\nannotation and pin-purpose layers cannot conceal functional geometry.\n\nCandidate-derived Magic distributed RC must retain both LV/HV model calls,\ntheir dimensions and their actual junction/interconnect loading. Extraction\nidealizes well/substrate contacts and does not establish distributed substrate\nresistance or noise. Only Metal3 text layer 30/25 supplies extraction labels;\nnative DRC/LVS still inspect the complete original GDS and physical taps.\nThe external 100 fF load is additional to candidate capacitance.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `reference_v` | Unloaded DC VREF | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `supply_a` | Unloaded DC −I(VDD) | A | minimize / ratio | 0 … +∞ | 1e-12 | bias |\n| `power_w` | Unloaded DC −VDD·I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `startup_error_v` | Maximum absolute reference error, 8–9 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_error_v` | Same, 18–19 ms under +1 pA | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `release_error_v` | Same, 28–29 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `injection_error_v` | Same, 38–39 ms under −1 pA | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `return_error_v` | Same, 48–49 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `minimum_v` | Minimum VREF over the full 0–50 ms startup/load transient. | V | target / target | −∞ … +∞ | 1.5 | bias |\n| `maximum_v` | Maximum VREF over the full 0–50 ms startup/load transient. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `line_min_v` | DC sweep: `vecmin(v(vref))`; sweep `VDD 1.0 1.5 .01`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `line_max_v` | DC sweep: `vecmax(v(vref))`; sweep `VDD 1.0 1.5 .01`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `line_span_v` | Supply-sweep maximum minus minimum | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `temperature_min_v` | DC sweep: `vecmin(v(vref))`; sweep `temp -20 85 5`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `temperature_max_v` | DC sweep: `vecmax(v(vref))`; sweep `temp -20 85 5`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `temperature_span_v` | Temperature-sweep maximum minus minimum | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `output_resistance_ohm` | (Unloaded DC VREF − DC VREF at +1 pA)/1 pA | ohm | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `loaded_reference_v` | DC VREF at +1 pA | V | target / target | 0 … 1.5 | 1.5 | bias |\n\nArea reference: **210.61 um2**. 3 expanded device instances; sum of device/contact envelopes 121.7863 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nVGS reference: line and temperature drift 31.5%; load regulation 22.5%; startup and disturbance recovery 18%; reference and extrema 9%; supply cost 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_span_v` | 0.157500000001 |\n| `temperature_span_v` | 0.157500000000 |\n| `load_error_v` | 0.056250000000 |\n| `loaded_reference_v` | 0.056250000000 |\n| `output_resistance_ohm` | 0.056250000000 |\n| `release_error_v` | 0.056250000000 |\n| `injection_error_v` | 0.060000000000 |\n| `return_error_v` | 0.060000000000 |\n| `startup_error_v` | 0.060000000000 |\n| `line_max_v` | 0.012857142857 |\n| `line_min_v` | 0.012857142857 |\n| `maximum_v` | 0.012857142857 |\n| `minimum_v` | 0.012857142857 |\n| `reference_v` | 0.012857142857 |\n| `temperature_max_v` | 0.012857142857 |\n| `temperature_min_v` | 0.012857142857 |\n| `power_w` | 0.045000000000 |\n| `supply_a` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the supplied task, process resources and runtime protocol. Write\n`/workspace/output/final.gds` and submit it through `python -I /protocol/submit.py`.\nThe evaluator independently checks the frozen submitted GDS. Collection\nlicenses, reference layouts, research files and host configuration are not\nsolver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml","case_sha256":"a50bb930f1a93a259d15f9c8896d7324d8ffb61787533e72b6868a1ce65f47af","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/circuit.cdl","netlist_sha256":"4352aeb85c2a7bfb00181738a742d0ccbd5033b422393bafa6a82bd84c1e84b9","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"} +{"id":"module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA","in_core":false,"title":"IHP AnalogAcademy full_OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a two-stage CMOS OTA.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# Two-Stage CMOS OTA Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `two_stage_OTA_layout` two-stage CMOS\noperational transconductance amplifier. Preserve the MOS and MIM devices,\ndimensions, connectivity, well and substrate connections, and six-port\ninterface in the authoritative materials. The submitted GDS must pass the\nphysical checks, fit the functional outline, and meet the nominal DC-bias and\nAC-response limits after candidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `two_stage_OTA_layout` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal bias, feedback fixture, AC sweep, and measurements |\n\nUse one external label on each distinct conductor. Internal nodes must not be\ndeclared as external ports.\n\n| Port | Function | Nominal connection |\n|---|---|---|\n| `v-` | Inverting input | DC feedback from `vout`; AC feedback fixture return |\n| `v+` | Non-inverting input | 0.6 V DC and unit AC excitation |\n| `vss` | Ground and substrate supply | 0 V |\n| `vdd` | Positive supply | 1.2 V |\n| `iout` | Bias-current node | Ideal 80 µA sink to ground |\n| `vout` | Single-ended output | 500 fF load to ground |\n\nThe extraction port order is `v- v+ vss vdd iout vout`.\n\n## Operating Conditions\n\nThe pre-layout and candidate-derived simulations use the supplied deck and the\nsame nominal model and fixture.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `cap_typ`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V`, `VSS = 0 V` |\n| Input DC level | `V+ = 0.6 V` |\n| Bias and load | 80 µA sink at `iout`; 500 fF from `vout` to ground |\n| Feedback fixture | 4 GH inductor from `vout` to `v-`; 4 GF capacitor from `v-` to ground |\n| AC sweep | 100 points/decade from 1 Hz through 10 MHz |\n| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout |\n\nThe feedback fixture closes the DC loop while opening the AC loop for transfer\nmeasurement. Supply power is `-V(vdd) × I(VDD)` at the operating point and\nexcludes external input and bias-source power.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `two_stage_OTA_layout` top cell. The\nfile must be at most 10 MiB (10,485,760 bytes) and must contain the complete\nhierarchy needed by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; every declared port must stay on its own conductor with\nthe declared connectivity and device parameters. Port names are matched\ncase-insensitively.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 80 µm and the maximum height is\n50 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; explicit taps remain in the\nphysical LVS netlist but are not emitted as extracted tap elements. Substrate\nsheet and tap resistance as extracted quantities, body coupling, and noise are\noutside the declared scope. The finite source tap elements are covered by the\nsame-condition source calibration and are not treated as additional post-layout\nrequirements.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vp)-v(vm))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vp)-v(vm)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin` | AC: `180+(find (180*cph((v(vout)/(v(vp)-v(vm))))/pi) when (db((v(vout)/(v(vp)-v(vm)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n\nArea reference: **2936.48 um2**. 24 expanded device instances; sum of device/contact envelopes 1887.1830 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `low_frequency_gain` | 0.270000000000 |\n| `unity_gain_bandwidth` | 0.225000000000 |\n| `phase_margin` | 0.225000000000 |\n| `output_bias` | 0.045000000000 |\n| `supply_power` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRuntime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside\nthe supplied testbench, with the model paths and settings exposed by the runtime\nresource bundle. For the submitted layout, the evaluator supplies the\ncandidate-derived extracted netlist. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml","case_sha256":"e8c96270684e41df167d5a346b0c0834c0a8a9d1804848c2d75fb571debcb348","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl","netlist_sha256":"b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"} +{"id":"module_1_bandgap_reference.part_3_layout.OTA_layout.input_pair","in_core":false,"title":"IHP AnalogAcademy input_pair","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts a differential input into a balanced response using a matched PMOS pair.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# PMOS Differential Input Pair Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `input_common_centroid` matched PMOS\ndifferential input pair. Preserve the device topology, dimensions, dummy\ndevices, explicit well and substrate connections, and six-port interface in the\nauthoritative materials. The submitted GDS must pass the physical checks, fit\nthe functional outline, and meet the nominal differential-response limits after\ncandidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `input_common_centroid` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Bias, load, AC sweep, and public measurement expressions |\n\nUse one external label on each distinct conductor. Internal nodes must not be\ndeclared as external ports.\n\n| Port | Function | Nominal connection |\n|---|---|---|\n| `v-` | Inverting PMOS gate | Differential input |\n| `v+` | Non-inverting PMOS gate | Differential input |\n| `vdd` | PMOS well and dummy-device supply | 1.2 V supply |\n| `dn3`, `dn4` | Differential drain outputs | 50 kΩ loads to ground |\n| `tail` | Shared source and dummy-drain node | 20 µA source current from `vdd` |\n\nThe extraction port order is `v- v+ vdd dn3 dn4 tail`.\n\n## Operating Conditions\n\nThe pre-layout and candidate-derived simulations use the supplied deck and the\nsame nominal model and parameter values.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V` |\n| Bias | 20 µA current source from `vdd` to `tail` |\n| Input DC level | `v- = v+ = 0.5 V` common mode |\n| Input AC stimulus | Equal and opposite small-signal inputs, −0.5 V and +0.5 V |\n| Drain loads | 50 kΩ from each of `dn3` and `dn4` to ground |\n| AC sweep | 40 points/decade from 1 Hz through 1 GHz |\n| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout |\n\nSupply power is `-V(vdd) × I(VDD)` at the DC operating point. The evaluator\nchecks the 1 MHz and 100 MHz differential gain observations from the sweep.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `input_common_centroid` top cell.\nThe file must be at most 10 MiB (10,485,760 bytes) and must contain the complete\nhierarchy needed by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; every declared port must stay on its own conductor\nwith the declared connectivity and device parameters. Port names are matched\ncase-insensitively.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 45 µm and the maximum height is\n40 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; the explicit tap is checked\nby physical LVS but is not emitted as an extracted tap element. Well/substrate\nsheet resistance, tap resistance as an extracted quantity, body coupling, and\nnoise are outside the declared scope. The finite source tap is used only in source calibration.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `differential_gain` | AC: Value of `(abs(((v(dn3)-v(dn4))/(v(vp)-v(vm))))) at=1meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `differential_gain_high` | AC: Value of `(abs(((v(dn3)-v(dn4))/(v(vp)-v(vm))))) at=100meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `tail_voltage` | DC operating point: `v(tail)`. | V | target / target | −∞ … +∞ | 1.2 | bias |\n| `common_drain` | DC operating point: `(v(dn3)+v(dn4))/2`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `drain_balance` | DC operating point: `v(dn3)-v(dn4)`. | V | target / target | −∞ … +∞ | 1.2 | bias |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **1236.14 um2**. 13 expanded device instances; sum of device/contact envelopes 778.4891 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **3**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 44.7%; balance and linearity 22.4%; operating points 4.47%; power 13.4%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `differential_gain` | 0.223684210526 |\n| `differential_gain_high` | 0.223684210526 |\n| `drain_balance` | 0.223684210526 |\n| `common_drain` | 0.022368421053 |\n| `tail_voltage` | 0.022368421053 |\n| `supply_power` | 0.134210526316 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRuntime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside\nthe supplied testbench. The evaluator generates `parameters.spice` from the\nper-job values in `/protocol/task.json` and supplies the model paths and settings\nthrough the runtime resource bundle. For the submitted layout, the evaluator\nsupplies the candidate-derived extracted netlist. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml","case_sha256":"3599b501cc1fbc77ef71218e592580de85311c0af6f96fa7c8e2b3703b87d253","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl","netlist_sha256":"25456f0316c22ee5586ad3e306f0d513fd35e48f32ee67ce9cb0dc373d306f3d","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"} +{"id":"module_1_bandgap_reference.part_3_layout.OTA_layout.output_stage","in_core":false,"title":"IHP AnalogAcademy output_stage","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Provides the loaded output response of a two-stage CMOS OTA.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# CMOS OTA Output Stage Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `output_stage` output stage of a two-stage\nCMOS operational transconductance amplifier. Preserve the device topology,\ndimensions, compensation capacitor, explicit well and substrate connections,\nand five-port interface in the authoritative materials. The submitted GDS must\npass the physical checks, fit the functional outline, and meet the nominal\noutput-response limits after candidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `output_stage` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Bias, load, AC sweep, and public measurement expressions |\n\nUse one external label on each distinct conductor. Internal nodes must not be\ndeclared as external ports.\n\n| Port | Function | Nominal connection |\n|---|---|---|\n| `vdd` | PMOS supply and n-well reference | 1.2 V supply |\n| `iout` | Bias replica/control node | 20 µA current sink to ground |\n| `vout` | Single-ended output | 100 kΩ and 500 fF loads to ground |\n| `vss` | NMOS supply and substrate reference | Ground |\n| `dn4` | NMOS gate and compensation-capacitor node | 0.33 V DC with 1 V AC |\n\nThe extraction port order is `vdd iout vout vss dn4`.\n\nThe circuit contains the PMOS output current source `MM5`, diode-connected bias\nreplica `MM9`, long-channel NMOS pull-down `MM6`, MIM compensation capacitor\n`CC2`, and explicit tap devices `RR4` and `RR5`.\n\n## Operating Conditions\n\nThe pre-layout and candidate-derived simulations use the supplied deck and the\nsame nominal model and parameter values.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `cap_typ`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V`, `VSS = 0 V` |\n| Bias | 20 µA current sink at `iout` |\n| Input stimulus | `dn4 = 0.33 V` DC with 1 V AC small signal |\n| Output load | 100 kΩ resistor and 500 fF capacitor to ground |\n| AC sweep | 40 points/decade from 1 Hz through 1 GHz |\n| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout |\n\nSupply power is `-V(vdd) × I(VDD)` at the DC operating point.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `output_stage` top cell. The file\nmust be at most 10 MiB (10,485,760 bytes) and must contain the complete\nhierarchy needed by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; every declared port must stay on its own conductor\nwith the declared connectivity and device parameters. Port names are matched\ncase-insensitively.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 55 µm and the maximum height is\n45 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; explicit taps remain in the\nphysical LVS netlist but are not emitted as extracted tap elements. Substrate\nsheet and tap resistance as extracted quantities, body coupling, and noise are\noutside the declared scope. The finite source taps are used only in source calibration.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_gain` | AC: Value of `(abs((-v(vout)/v(dn4)))) at=1meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `output_gain_high` | AC: Value of `(abs((-v(vout)/v(dn4)))) at=100meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **2292.35 um2**. 6 expanded device instances; sum of device/contact envelopes 1466.0063 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 60.7%; operating points 6.07%; power 18.2%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `output_gain` | 0.303571428572 |\n| `output_gain_high` | 0.303571428571 |\n| `output_bias` | 0.060714285714 |\n| `supply_power` | 0.182142857143 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRuntime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside\nthe supplied testbench. The evaluator generates `parameters.spice` from the\nper-job values in `/protocol/task.json` and supplies the model paths and settings\nthrough the runtime resource bundle. For the submitted layout, the evaluator\nsupplies the candidate-derived extracted netlist. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml","case_sha256":"24e04f3a64bd2477b89dbbef2c7789208eaa798e4e8e7b8efd60d080a80fa6fb","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/circuit.cdl","netlist_sha256":"81620ebba529edccd1beddbcb1349c0e3e7ee58b9e3749d8235433610bd98ad5","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"} +{"id":"module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator","in_core":false,"title":"IHP AnalogAcademy comparator","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Compares two input voltages using a clocked regenerative decision.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/tree/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# Dynamic Comparator Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `DIFF_COMPARATOR` dynamic differential\ncomparator. Preserve the topology, device parameters, explicit well and\nsubstrate connections, and eight-port interface in the authoritative materials.\nThe submitted GDS must pass the physical checks, fit the functional outline, and\nmeet the clocked decision requirements after candidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `DIFF_COMPARATOR` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Clock stimulus and public measurement expressions |\n\nUse one distinct external conductor for each ordered port. Internal nodes must\nnot be exposed as ports.\n\n| Port | Function |\n|---|---|\n| `vdd` | Positive supply |\n| `gnd` | Ground and substrate reference |\n| `V+`, `V-` | Differential input pair |\n| `clk` | Dynamic latch clock |\n| `out-`, `out+` | Complementary decision outputs |\n| `vbias` | Bias input |\n\nThe extraction port order is `vdd gnd V+ V- clk out- out+ vbias`.\n\n## Operating Conditions\n\nThe supplied deck evaluates the pre-layout and candidate-derived netlists with\nthe same model and stimulus definitions.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V` |\n| Input reference and bias | `V- = vbias = 0.6 V` |\n| Differential input | `V+ − V- = −5, −3, +3, +5 mV`, tested separately |\n| Clock | 100 MHz, 1.2 V swing, 500 ps rise and fall, 5 ns high time |\n| Output load | 50 fF on each output |\n| Transient analysis | 100 ns duration, 10 ps maximum time step |\n| Measurements | Skip the first two cycles and evaluate the next eight cycles |\n\nThe testbench excludes power consumed by the external clock, input, and bias\ndrivers from the reported supply-power measurement.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `DIFF_COMPARATOR` top cell. The file\nmust be at most 10 MiB (10,485,760 bytes) and must contain the complete hierarchy\nneeded by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; port names are matched case-insensitively, while every\ndeclared port must remain on its own conductor with the declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 45 µm and the maximum height is\n45 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; explicit taps remain part\nof physical LVS but are not emitted as extracted tap elements. Substrate sheet\nand tap resistance as extracted quantities, body coupling, and noise are outside\nthe declared scope. The source and post-layout runs use the same nominal\nstimuli and models; a finite-source-tap versus ideal-body calibration bounds this\nextraction choice.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `worst_delay` | Clock falling through 0.6 V to polarity-correct output difference reaching 1 V in cycles 2–9 (trigger delays 20–90 ns; target search starts 5.75 ns later). Every cycle and input condition is paired; the worst quality is scored. | s | minimize / ratio | 0 … +∞ | — | response |\n| `decision_margin` | Minimum polarity*(V(OUTP)-V(OUTM)) in each 1 ns decision window, 28.75–29.75 ns through 98.75–99.75 ns; all eight cycles and four signed input conditions must pass. | V | functional check | 1.0 … +∞ | — | functional check |\n| `supply_power` | Mean delivered VDD power, -V(VDD)*I(VDD), over 20–100 ns, independently for each signed input condition. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **502.96 um2**. 24 expanded device instances; sum of device/contact envelopes 306.3377 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nClocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `worst_delay` | 0.710526315789 |\n| `supply_power` | 0.189473684211 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nThe runtime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice`\nbeside the supplied testbench and use the per-job values exposed in\n`/protocol/task.json`. For the submitted layout, the evaluator supplies the\nnetlist produced by candidate-derived RC extraction. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml","case_sha256":"d553f9e09dd960a229e184f1feff7247c57d2d7cc8ae117ad712cecabf6aae9b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl","netlist_sha256":"0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"} diff --git a/tasks/freepdk45/OpenRAM/LICENSE b/tasks/freepdk45/OpenRAM/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..94a9ed024d3859793618152ea559a168bbcbb5e2 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/tasks/freepdk45/OpenRAM/NOTICE b/tasks/freepdk45/OpenRAM/NOTICE new file mode 100644 index 0000000000000000000000000000000000000000..07d042e1dba0165d44a6810ec585d322df63981f --- /dev/null +++ b/tasks/freepdk45/OpenRAM/NOTICE @@ -0,0 +1,28 @@ +OpenRAM FreePDK45 circuit notices + +Source: https://github.com/ferdous313/OpenRAM/tree/420a33e731d7d80bf9c7cd54ffbeec3603259847 +Selected circuit: technology/freepdk45/sp_lib/cell_6t.sp (cell_6t) +The accompanying LICENSE is the source repository's GPL-3.0 license. +Layout-Bench netlist modification: none to the SPICE bytes. +The candidate reference GDS is a selected-cell export of technology/freepdk45/gds_lib/cell_6t.gds; Geometry and netlist are unchanged. +No model files, Cadence technology files or Calibre SVRF are distributed here. +FreePDK45 process collateral has separate upstream terms; the repository license +must not be treated as a license grant for separately sourced PDK assets. + +Source: https://github.com/ferdous313/OpenRAM/tree/420a33e731d7d80bf9c7cd54ffbeec3603259847 +Selected circuit: technology/freepdk45/sp_lib/sense_amp.sp (sense_amp) +The accompanying LICENSE is the source repository's GPL-3.0 license. +Layout-Bench netlist modification: none to the SPICE bytes. +The candidate reference GDS is a selected-cell export of technology/freepdk45/gds_lib/sense_amp.gds; Six overlapping duplicate contacts are removed; transistor geometry and circuit parameters are unchanged. +No model files, Cadence technology files or Calibre SVRF are distributed here. +FreePDK45 process collateral has separate upstream terms; the repository license +must not be treated as a license grant for separately sourced PDK assets. + +Source: https://github.com/ferdous313/OpenRAM/tree/420a33e731d7d80bf9c7cd54ffbeec3603259847 +Selected circuit: technology/freepdk45/sp_lib/write_driver.sp (write_driver) +The accompanying LICENSE is the source repository's GPL-3.0 license. +Layout-Bench netlist modification: none to the SPICE bytes. +The candidate reference GDS is a selected-cell export of technology/freepdk45/gds_lib/write_driver.gds; The enable label is wen, matching the authoritative SPICE port; conductor and transistor geometry are unchanged. +No model files, Cadence technology files or Calibre SVRF are distributed here. +FreePDK45 process collateral has separate upstream terms; the repository license +must not be treated as a license grant for separately sourced PDK assets. diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml b/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..0b89b2622f006f36040f9c09d5c211f10d59e491 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml @@ -0,0 +1,592 @@ +in_core = true +kind = "layout_case" +id = "freepdk45.OpenRAM.cell_6t" +title = "Six-Transistor SRAM Bitcell" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "38ce484f184eaac9f1ec0de9455efc1e4ef2b6ef27cd0e8a9176cebb9bc47329" + +[[assets]] +path = "reference/cell_6t.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "400d0f5640f07266e4b17b4d3d765ca04ffbabe03dd1122195f277e5ea558fdc" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "freepdk45_cell_6t" +coefficient = 6 +environment = "freepdk45-nominal-predictive-rc" + +[task.inputs.description] +path = "problem.md" +sha256 = "89d9934e6f3bca7303ae3d06d6bd78f4aaf5791e9cf28be79888e6ffc4050e02" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.spice" +sha256 = "18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488" +format = "spice" +subcircuit = "cell_6t" + +[task.inputs.performance] +path = "materials/testbench.spice" +format = "spice" +sha256 = "bc0034d4bde558134f21b5ad453623f4cd93862d8fe7761a1a8752ba21051006" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 2, + 0, + ], + [ + 3, + 0, + ], + [ + 4, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 9, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 12, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 15, + 0, + ], + [ + 16, + 0, + ], + [ + 17, + 0, + ], + [ + 18, + 0, + ], + [ + 19, + 0, + ], + [ + 20, + 0, + ], + [ + 21, + 0, + ], + [ + 22, + 0, + ], + [ + 23, + 0, + ], + [ + 24, + 0, + ], + [ + 25, + 0, + ], + [ + 26, + 0, + ], + [ + 27, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], +] +max_width_um = 100 +max_height_um = 100 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "cell_6t" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "bl", + "br", + "wl", + "vdd", + "gnd", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.jobs.parameters.measurements] +read0 = "V" +repeat0 = "V" +read1 = "V" +repeat1 = "V" +supply = "W" +read_delay_0_1 = "s" +read_delay_0_2 = "s" +read_delay_1_5 = "s" +read_delay_1_6 = "s" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "read0" +category = "performance" +observations = [ + "nominal:read0", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.3 + +[[task.evaluation.metrics]] +id = "repeat0" +category = "performance" +observations = [ + "nominal:repeat0", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.3 + +[[task.evaluation.metrics]] +id = "read1" +category = "performance" +observations = [ + "nominal:read1", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.3 + +[[task.evaluation.metrics]] +id = "repeat1" +category = "performance" +observations = [ + "nominal:repeat1", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.3 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:supply", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_nominal:supply", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "read_delay" +category = "performance" +observations = [ + "nominal:read_delay_0_1", + "nominal:read_delay_0_2", + "nominal:read_delay_1_5", + "nominal:read_delay_1_6", +] +baseline = [ + "source_nominal:read_delay_0_1", + "source_nominal:read_delay_0_2", + "source_nominal:read_delay_1_5", + "source_nominal:read_delay_1_6", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +normalization = "ratio" +lower = 0.0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 1.46 +rationale = "SRAM cell: read delay 64%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.2 +read_delay = 0.64 +supply = 0.16 + +[task.evaluation.pre_layout] +source_report_sha256 = "6910725e38dfe44770306a9966be0dd2bf875ecba4f0800cc29753c831e398d2" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +read0 = "V" +repeat0 = "V" +read1 = "V" +repeat1 = "V" +supply = "W" +read_delay_0_1 = "s" +read_delay_0_2 = "s" +read_delay_1_5 = "s" +read_delay_1_6 = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "bc0034d4bde558134f21b5ad453623f4cd93862d8fe7761a1a8752ba21051006" +dut = "18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.read0] +value = 0.7858571 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.read1] +value = 0.7858571 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_0_1] +value = 1.317565e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_0_2] +value = 1.317565e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_1_5] +value = 1.317565e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_1_6] +value = 1.317565e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.repeat0] +value = 0.7858571 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.repeat1] +value = 0.7858571 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply] +value = 5.942012e-06 +unit = "W" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 120 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "strict-lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 60 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-magic-vtg" +technology = "freepdk45.tech" +tech_name = "freepdk45" +style = "spice3(sim)" +gds_readonly = false +case_insensitive_ports = true +label_layers = [ + [ + 9, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 15, + 0, + ], + [ + 17, + 0, + ], + [ + 19, + 0, + ], + [ + 21, + 0, + ], + [ + 23, + 0, + ], + [ + 25, + 0, + ], + [ + 27, + 0, + ], + [ + 29, + 0, + ], +] +timeout_seconds = 120 + +[toolchain.backends.rc.support_profiles] +support = "magic-vtg" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-models" +timeout_seconds = 120 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[qualification] +reference = "reference/cell_6t.gds" + +[origin] +url = "https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/cell_6t.sp" + +[presentation] +category = "Logic & memory" +summary = "Stores one bit using cross-coupled inverters and wordline-controlled access transistors." diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..6b1be024ce15aa3d47d40c64fa4974b5c1c9c118 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice @@ -0,0 +1,10 @@ + +.SUBCKT cell_6t bl br wl vdd gnd +MM3 bl wl net10 gnd NMOS_VTG W=135.00n L=50n +MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n +MM1 net10 net4 gnd gnd NMOS_VTG W=205.00n L=50n +MM0 net4 net10 gnd gnd NMOS_VTG W=205.00n L=50n +MM5 net10 net4 vdd vdd PMOS_VTG W=90n L=50n +MM4 net4 net10 vdd vdd PMOS_VTG W=90n L=50n +.ENDS cell_6t + diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/schematic.svg b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..4b6a260f6d9316c360eb316aeaf41b04ebe2b1b2 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/schematic.svg @@ -0,0 +1 @@ +cell_6t{"format": "iclayout-schematic", "case_id": "freepdk45.OpenRAM.cell_6t", "netlist_sha256": "18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488", "project_sha256": "d6e39d9517c5113d939365fcc3a7633817380f7eb0d7400f86ed6cc5d63f6952", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/freepdk45/OpenRAM/", "sheets": ["cell_6t"], "banks": [], "source_netlist": "tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}cell_6tblnet10brnet4wlvddgndnet10net4blbrwlvddgndcell_6tfreepdk45 · OpenRAM | W/L in µm · display rounded to 3 significant figures01 Cross-coupled storage invertersMM50.09/0.05MM40.09/0.05MM10.205/0.05MM00.205/0.05P bulk → vddN bulk → gnd02 Word-line access devicesMM30.135/0.05MM20.135/0.05N bulk → gndModels: NMOS_VTG · PMOS_VTG \ No newline at end of file diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/testbench.spice b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..b73633846d8b7e6e5bd7e119ad6a563649f74825 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/testbench.spice @@ -0,0 +1,41 @@ +* cell_6t nominal characterization +.include /workspace/support/models.spice +.include dut.spice +.temp 27 +Vdd vdd 0 1 +Xdut BL BR WL vdd gnd cell_6t +.model sw SW(Ron=10 Roff=1e12 Vt=.5 Vh=0) +Cbl bl 0 10f +Cbr br 0 10f +Vdata data 0 PWL(0 0 4n 0 4.01n 1) +Bbar bar 0 v=1-v(data) +Vwrite wr 0 PWL(0 1 500p 1 510p 0 4n 0 4.01n 1 4.5n 1 4.51n 0) +Swl bl data wr 0 sw +Swr br bar wr 0 sw +Vpre pre 0 PWL(0 0 600p 0 610p 1 990p 1 1n 0 1.5n 0 1.51n 1 1.99n 1 2n 0 4.6n 0 4.61n 1 4.99n 1 5n 0 5.5n 0 5.51n 1 5.99n 1 6n 0) +Spl bl vdd pre 0 sw +Spr br vdd pre 0 sw +Vwl wl 0 PWL(0 1 490p 1 500p 0 1n 0 1.01n 1 1.3n 1 1.31n 0 2n 0 2.01n 1 2.3n 1 2.31n 0 4n 0 4.02n 1 4.49n 1 4.5n 0 5n 0 5.01n 1 5.3n 1 5.31n 0 6n 0 6.01n 1 6.3n 1 6.31n 0) +Bdiff0 diff0 0 v=v(br)-v(bl) +Bdiff1 diff1 0 v=v(bl)-v(br) +.tran 1p 7n +.meas tran read0 find par('v(br)-v(bl)') at=1110p +.meas tran repeat0 find par('v(br)-v(bl)') at=2110p +.meas tran read1 find par('v(bl)-v(br)') at=5110p +.meas tran repeat1 find par('v(bl)-v(br)') at=6110p +.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=7n + +.meas tran read_delay_0_1 trig v(wl) val=.5 rise=1 td=1n targ v(diff0) val=.1 rise=1 td=1n + +.meas tran read_delay_0_2 trig v(wl) val=.5 rise=1 td=2n targ v(diff0) val=.1 rise=1 td=2n + +.meas tran read_delay_1_5 trig v(wl) val=.5 rise=1 td=5n targ v(diff1) val=.1 rise=1 td=5n + +.meas tran read_delay_1_6 trig v(wl) val=.5 rise=1 td=6n targ v(diff1) val=.1 rise=1 td=6n + +.control +run +write waveform.raw v(bl) v(br) v(wl) v(vdd) i(Vdd) +quit +.endc +.end diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md b/tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..1660917ece2b19b45c7d3a864ee7bc9428848799 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md @@ -0,0 +1,85 @@ +# Six-Transistor SRAM Bitcell Layout Task + +## Objective + +Implement the supplied six-transistor SRAM bitcell, including cross-coupled storage, complementary bitlines and a common wordline. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `cell_6t`. + +## Inputs and Interface + +Ordered SPICE ports: `bl br wl vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs. + +## Operating Conditions + +Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist. + +Each bitline has 10 fF. Ideal external switches (10 ohm on, 1e12 ohm off) implement write and precharge. Write BL=0/BR=1 during 0–500 ps, then precharge and read at 1 ns and 2 ns; write the opposite value at 4–4.5 ns, then read at 5 ns and 6 ns. Sample differential bitline voltage 110 ps after each read starts. Wordline transitions take 10 ps; read pulses last 300 ps. The second read checks retention after a nondestructive read and idle interval. The supplied deck gives every switch edge. Power includes DUT supply current and the precharge supply over 0–7 ns. + +The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff. + +## Physical Requirements + +Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck. + +The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction. + +Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections. + +## Electrical Requirements and Scoring + +Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `read0` | `find par('v(br)-v(bl)') at=1110p` | V | functional check | 0.3 … +∞ | — | +| `repeat0` | `find par('v(br)-v(bl)') at=2110p` | V | functional check | 0.3 … +∞ | — | +| `read1` | `find par('v(bl)-v(br)') at=5110p` | V | functional check | 0.3 … +∞ | — | +| `repeat1` | `find par('v(bl)-v(br)') at=6110p` | V | functional check | 0.3 … +∞ | — | +| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=7n` | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `read_delay` | WL rising through 0.5 V to signed bitline difference reaching 0.1 V, for read edges at 1, 2, 5 and 6 ns (distinct from the 0.3 V sampled-level requirement). | s | minimize / ratio | 0 … +∞ | — | + +Area reference: **1.46 um2**. 6 expanded device instances; sum of device/contact envelopes 0.6670 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **6**; it is independent of +the reference-relative task score. + + +### Score weights + +SRAM cell: read delay 64%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.2 | +| `read_delay` | 0.640000000000 | +| `supply` | 0.160000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions. diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/reference/cell_6t.gds b/tasks/freepdk45/OpenRAM/cases/cell_6t/reference/cell_6t.gds new file mode 100644 index 0000000000000000000000000000000000000000..a84fca6db3b5abaa776bd8c5c2a887f94a44a901 Binary files /dev/null and b/tasks/freepdk45/OpenRAM/cases/cell_6t/reference/cell_6t.gds differ diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml b/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..fa80725172598e812e81141520c846343bd73875 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml @@ -0,0 +1,535 @@ +in_core = false +kind = "layout_case" +id = "freepdk45.OpenRAM.sense_amp" +title = "Clocked SRAM Sense Amplifier" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "a1d1470e1bc4f21f8e205ff75a416e5aaedd678159f003c35e9fdc10a098ce4e" + +[[assets]] +path = "reference/sense_amp.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "07b246b1f11d26f2bb268c6f60f2f93b90b91228d479c7af3fa831431df8ffaa" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "freepdk45_sense_amp" +coefficient = 5 +environment = "freepdk45-nominal-predictive-rc" + +[task.inputs.description] +path = "problem.md" +sha256 = "4d05195bfe1882c03fd03769b23822a985e73985f95227f93e213a6887980ac4" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.spice" +sha256 = "f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f" +format = "spice" +subcircuit = "sense_amp" + +[task.inputs.performance] +path = "materials/testbench.spice" +format = "spice" +sha256 = "1d96a4f3ff79ab3e154911210b637de1419e5572e31aabe6e98550f381edb761" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 2, + 0, + ], + [ + 3, + 0, + ], + [ + 4, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 9, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 12, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 15, + 0, + ], + [ + 16, + 0, + ], + [ + 17, + 0, + ], + [ + 18, + 0, + ], + [ + 19, + 0, + ], + [ + 20, + 0, + ], + [ + 21, + 0, + ], + [ + 22, + 0, + ], + [ + 23, + 0, + ], + [ + 24, + 0, + ], + [ + 25, + 0, + ], + [ + 26, + 0, + ], + [ + 27, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], +] +max_width_um = 100 +max_height_um = 100 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "sense_amp" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "bl", + "br", + "dout", + "sclk", + "vdd", + "gnd", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.jobs.parameters.measurements] +low = "V" +high = "V" +supply = "W" +decision_delay_fall = "s" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "low" +category = "performance" +observations = [ + "nominal:low", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.1 + +[[task.evaluation.metrics]] +id = "high" +category = "performance" +observations = [ + "nominal:high", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:supply", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_nominal:supply", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "decision_delay_fall" +category = "performance" +observations = [ + "nominal:decision_delay_fall", +] +baseline = [ + "source_nominal:decision_delay_fall", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +normalization = "ratio" +lower = 0.0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 2.82 +rationale = "SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +decision_delay_fall = 0.68 +supply = 0.17 + +[task.evaluation.pre_layout] +source_report_sha256 = "092e85048c56d9acc523fdb6eb8b64acff106fcd5fb777345c691b5dede84ef7" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +low = "V" +high = "V" +supply = "W" +decision_delay_fall = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "1d96a4f3ff79ab3e154911210b637de1419e5572e31aabe6e98550f381edb761" +dut = "f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.decision_delay_fall] +value = 1.248627e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.high] +value = 0.999996 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.low] +value = 2.338873e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply] +value = 1.395456e-06 +unit = "W" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 120 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "strict-lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 60 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-magic-vtg" +technology = "freepdk45.tech" +tech_name = "freepdk45" +style = "spice3(sim)" +gds_readonly = false +case_insensitive_ports = true +label_layers = [ + [ + 9, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 15, + 0, + ], + [ + 17, + 0, + ], + [ + 19, + 0, + ], + [ + 21, + 0, + ], + [ + 23, + 0, + ], + [ + 25, + 0, + ], + [ + 27, + 0, + ], + [ + 29, + 0, + ], +] +timeout_seconds = 120 + +[toolchain.backends.rc.support_profiles] +support = "magic-vtg" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-models" +timeout_seconds = 120 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[qualification] +reference = "reference/sense_amp.gds" + +[origin] +url = "https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/sense_amp.sp" + +[presentation] +category = "Logic & memory" +summary = "Resolves a small bitline voltage difference into a clocked digital decision." diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..112d96f91d06e071867b28a2314117f93d9593e5 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice @@ -0,0 +1,11 @@ + +.SUBCKT sense_amp bl br dout sclk vdd gnd +M_1 dout net_1 vdd vdd pmos_vtg w=540.0n l=50.0n +M_3 net_1 dout vdd vdd pmos_vtg w=540.0n l=50.0n +M_2 dout net_1 net_2 gnd nmos_vtg w=270.0n l=50.0n +M_8 net_1 dout net_2 gnd nmos_vtg w=270.0n l=50.0n +M_5 bl sclk dout vdd pmos_vtg w=720.0n l=50.0n +M_6 br sclk net_1 vdd pmos_vtg w=720.0n l=50.0n +M_7 net_2 sclk gnd gnd nmos_vtg w=270.0n l=50.0n +.ENDS sense_amp + diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/schematic.svg b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..b235ad47d0946277b7bf289b071b87037dec2d14 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/schematic.svg @@ -0,0 +1 @@ +sense_amp{"format": "iclayout-schematic", "case_id": "freepdk45.OpenRAM.sense_amp", "netlist_sha256": "f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f", "project_sha256": "c288280f41ff885c96afd2fb13cc3aeb09b107995f6e47e19e1f2e8c0dace0f6", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/freepdk45/OpenRAM/", "sheets": ["sense_amp"], "banks": [], "source_netlist": "tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}sense_ampbldoutbrnet_1sclksclkgndvddnet_2doutnet_1blbrdoutsclkvddgndsense_ampfreepdk45 · OpenRAM | W/L in µm · display rounded to 3 significant figures01 Regenerative latchM_10.54/0.05M_30.54/0.05M_20.27/0.05M_80.27/0.05M_70.27/0.05P bulk → vddN bulk → gnd02 Bit-line inputsM_50.72/0.05M_60.72/0.05P bulk → vddModels: pmos_vtg · nmos_vtg \ No newline at end of file diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/testbench.spice b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..4fa6bdff31b7625013004edb7aaa6dd26b00da45 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/testbench.spice @@ -0,0 +1,24 @@ +* sense_amp nominal characterization +.include /workspace/support/models.spice +.include dut.spice +.temp 27 +Vdd vdd 0 1 +Xdut BL BR Dout SCLK vdd gnd sense_amp +Vbl bl 0 PWL(0 .8 1n .8 1.01n 1) +Vbr br 0 PWL(0 1 1n 1 1.01n .8) +Vs sclk 0 PULSE(0 1 500p 10p 10p 480p 1n) +Cl dout 0 .5f +.tran 0.5p 2n +.meas tran low find v(dout) at=610p +.meas tran high find v(dout) at=1610p +.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=2n + +.meas tran decision_delay_fall trig v(sclk) val=.5 rise=1 td=0.5n targ v(dout) val=.5 fall=1 td=0.5n + + +.control +run +write waveform.raw v(bl) v(br) v(dout) v(sclk) v(vdd) i(Vdd) +quit +.endc +.end diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md b/tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..3163c245572eda51bed2dca5f6988f78587693dd --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md @@ -0,0 +1,87 @@ +# Clocked SRAM Sense Amplifier Layout Task + +## Objective + +Implement the supplied clocked regenerative sense amplifier. A lower sampled BL than BR must produce a low Dout; the opposite differential must produce a high Dout. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `sense_amp`. + +## Inputs and Interface + +Ordered SPICE ports: `bl br dout sclk vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs. + +## Operating Conditions + +Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist. + +BL/BR are 0.8/1.0 V for the first decision and 1.0/0.8 V for the second. SCLK is low while sampling and rises at 500 ps and 1500 ps with 10 ps edges; it stays high for 480 ps. Dout drives 0.5 fF. Sample Dout at 610 ps and 1610 ps. Average supply power over 0–2 ns. This is a 200 mV differential, loaded decision task; 50 mV sensitivity is not specified. + +The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff. + +## Physical Requirements + +Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck. + +The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction. + +Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections. + +## Electrical Requirements and Scoring + +Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `low` | `find v(dout) at=610p` | V | functional check | −∞ … 0.1 | — | +| `high` | `find v(dout) at=1610p` | V | functional check | 0.9 … +∞ | — | +| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `decision_delay_fall` | SCLK 50% to Dout 50% decision delay; see testbench window. | s | minimize / ratio | 0.0 … +∞ | — | + +Area reference: **2.82 um2**. 7 expanded device instances; sum of device/contact envelopes 1.4529 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **5**; it is independent of +the reference-relative task score. + + +### Score weights + +SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.15 | +| `decision_delay_fall` | 0.680000000000 | +| `supply` | 0.170000000000 | + +Only the falling output decision delay contributes to timing quality. Both +decision polarities must satisfy their sampled final-level checks; rising +decision timing is outside this task's measured objective. + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions. diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/reference/sense_amp.gds b/tasks/freepdk45/OpenRAM/cases/sense_amp/reference/sense_amp.gds new file mode 100644 index 0000000000000000000000000000000000000000..e727f1df3fe32350f48b0c4be8a152c1bf691b08 Binary files /dev/null and b/tasks/freepdk45/OpenRAM/cases/sense_amp/reference/sense_amp.gds differ diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml b/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..290a68b1af75519466d76cbfe1e0eadf26a55086 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml @@ -0,0 +1,613 @@ +in_core = true +kind = "layout_case" +id = "freepdk45.OpenRAM.write_driver" +title = "Complementary SRAM Write Driver" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "651fc9f4dbffb8f1512c92cee69ff3c7dc9ae4513e2fab8e092949c527287b0d" + +[[assets]] +path = "reference/write_driver.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "2465c2b5293b138226ebc396cc13dd19bca4b8aba3268dfead8f83893316ba78" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "freepdk45_write_driver" +coefficient = 3 +environment = "freepdk45-nominal-predictive-rc" + +[task.inputs.description] +path = "problem.md" +sha256 = "c107911cb0ae72200a1aaa9baa1cda5c3ff12f89fba4e4ffba1a146a33be1e3d" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.spice" +sha256 = "40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4" +format = "spice" +subcircuit = "write_driver" + +[task.inputs.performance] +path = "materials/testbench.spice" +format = "spice" +sha256 = "a07fc802d7506c35db325b6aa8256ec558c5d606003547a22e9e8b5236a98ecf" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 2, + 0, + ], + [ + 3, + 0, + ], + [ + 4, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 9, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 12, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 15, + 0, + ], + [ + 16, + 0, + ], + [ + 17, + 0, + ], + [ + 18, + 0, + ], + [ + 19, + 0, + ], + [ + 20, + 0, + ], + [ + 21, + 0, + ], + [ + 22, + 0, + ], + [ + 23, + 0, + ], + [ + 24, + 0, + ], + [ + 25, + 0, + ], + [ + 26, + 0, + ], + [ + 27, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], +] +max_width_um = 100 +max_height_um = 100 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "write_driver" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "din", + "bl", + "br", + "wen", + "vdd", + "gnd", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.jobs.parameters.measurements] +bl_low = "V" +br_high = "V" +bl_high = "V" +br_low = "V" +z_bl = "V" +z_br = "V" +supply = "W" +data_delay_bl = "s" +data_delay_br = "s" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "bl_low" +category = "performance" +observations = [ + "nominal:bl_low", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.1 + +[[task.evaluation.metrics]] +id = "br_high" +category = "performance" +observations = [ + "nominal:br_high", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "bl_high" +category = "performance" +observations = [ + "nominal:bl_high", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "br_low" +category = "performance" +observations = [ + "nominal:br_low", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.1 + +[[task.evaluation.metrics]] +id = "z_bl" +category = "performance" +observations = [ + "nominal:z_bl", +] +unit = "V" +direction = "target" +aggregation = "max" +lower = 0.45 +upper = 0.55 + +[[task.evaluation.metrics]] +id = "z_br" +category = "performance" +observations = [ + "nominal:z_br", +] +unit = "V" +direction = "target" +aggregation = "max" +lower = 0.45 +upper = 0.55 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:supply", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_nominal:supply", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "data_delay" +category = "performance" +observations = [ + "nominal:data_delay_bl", + "nominal:data_delay_br", +] +baseline = [ + "source_nominal:data_delay_bl", + "source_nominal:data_delay_br", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +normalization = "ratio" +lower = 0.0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 3.36 +rationale = "SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +data_delay = 0.68 +supply = 0.17 + +[task.evaluation.pre_layout] +source_report_sha256 = "4c7f16eb4faca05c47621e31e3a9511f8fa6bd470ad784766c7eb76c0adbfd1f" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +bl_low = "V" +br_high = "V" +bl_high = "V" +br_low = "V" +z_bl = "V" +z_br = "V" +supply = "W" +data_delay_bl = "s" +data_delay_br = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "a07fc802d7506c35db325b6aa8256ec558c5d606003547a22e9e8b5236a98ecf" +dut = "40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.bl_high] +value = 0.9860666 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.bl_low] +value = 0.0150365 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.br_high] +value = 0.9886259 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.br_low] +value = 0.02670905 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.data_delay_bl] +value = 5.409058e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.data_delay_br] +value = 6.295051e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply] +value = 2.174283e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.z_bl] +value = 0.5015592 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.z_br] +value = 0.502349 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 120 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "strict-lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 60 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-magic-vtg" +technology = "freepdk45.tech" +tech_name = "freepdk45" +style = "spice3(sim)" +gds_readonly = false +case_insensitive_ports = true +label_layers = [ + [ + 9, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 15, + 0, + ], + [ + 17, + 0, + ], + [ + 19, + 0, + ], + [ + 21, + 0, + ], + [ + 23, + 0, + ], + [ + 25, + 0, + ], + [ + 27, + 0, + ], + [ + 29, + 0, + ], +] +timeout_seconds = 120 + +[toolchain.backends.rc.support_profiles] +support = "magic-vtg" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-models" +timeout_seconds = 120 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[qualification] +reference = "reference/write_driver.gds" + +[origin] +url = "https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/write_driver.sp" + +[presentation] +category = "Logic & memory" +summary = "Drives complementary bitlines during a write and releases them when disabled." diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..8f1a551fb733283d2e14649a5cd506542188f48e --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice @@ -0,0 +1,21 @@ + +.SUBCKT write_driver din bl br wen vdd gnd +*inverters for enable and data input +minP bl_bar din vdd vdd pmos_vtg w=360.000000n l=50.000000n +minN bl_bar din gnd gnd nmos_vtg w=180.000000n l=50.000000n +moutP wen_bar wen vdd vdd pmos_vtg w=360.000000n l=50.000000n +moutN wen_bar wen gnd gnd nmos_vtg w=180.000000n l=50.000000n + +*tristate for BL +mout0P int1 bl_bar vdd vdd pmos_vtg w=360.000000n l=50.000000n +mout0P2 bl wen_bar int1 vdd pmos_vtg w=360.000000n l=50.000000n +mout0N bl wen int2 gnd nmos_vtg w=180.000000n l=50.000000n +mout0N2 int2 bl_bar gnd gnd nmos_vtg w=180.000000n l=50.000000n + +*tristate for BR +mout1P int3 din vdd vdd pmos_vtg w=360.000000n l=50.000000n +mout1P2 br wen_bar int3 vdd pmos_vtg w=360.000000n l=50.000000n +mout1N br wen int4 gnd nmos_vtg w=180.000000n l=50.000000n +mout1N2 int4 din gnd gnd nmos_vtg w=180.000000n l=50.000000n +.ENDS write_driver + diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/materials/schematic.svg b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..99bf0ea27d3383f72a92a0d917d66de20d4d24ca --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/schematic.svg @@ -0,0 +1 @@ +write_driver{"format": "iclayout-schematic", "case_id": "freepdk45.OpenRAM.write_driver", "netlist_sha256": "40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4", "project_sha256": "0b7d8672d13d8887a90862ce4d7a2f51460595e6aa1282c78c8de464ecf6dec4", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/freepdk45/OpenRAM/", "sheets": ["write_driver"], "banks": [], "source_netlist": "tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}write_driverint1bl_barvddint3dinblwen_barbrwenint2int4gndbl_bardinvddwen_barwengnddinblbrwenvddgndwrite_driverfreepdk45 · OpenRAM | W/L in µm · display rounded to 3 significant figures01 Input and enable invertersminP0.36/0.05moutP0.36/0.05minN0.18/0.05moutN0.18/0.05P bulk → vddN bulk → gnd02 Complementary bit-line driversmout0P0.36/0.05mout1P0.36/0.05mout0P20.36/0.05mout1P20.36/0.05mout0N0.18/0.05mout1N0.18/0.05mout0N20.18/0.05mout1N20.18/0.05P bulk → vddN bulk → gndModels: pmos_vtg · nmos_vtg \ No newline at end of file diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/materials/testbench.spice b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..4af93a99c05464932ffd2c82121ff6ab3e1c7789 --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/testbench.spice @@ -0,0 +1,32 @@ +* write_driver nominal characterization +.include /workspace/support/models.spice +.include dut.spice +.temp 27 +Vdd vdd 0 1 +Xdut din BL BR wen vdd gnd write_driver +Vdin din 0 PULSE(0 1 500p 10p 10p 490p 1n) +Ven wen 0 PWL(0 1 2n 1 2.01n 0) +Cl bl 0 10f +Cr br 0 10f +Vmid mid 0 .5 +Rl bl mid 100k +Rr br mid 100k +.tran 1p 12n +.meas tran bl_low find v(bl) at=300p +.meas tran br_high find v(br) at=300p +.meas tran bl_high find v(bl) at=710p +.meas tran br_low find v(br) at=710p +.meas tran z_bl find v(bl) at=11.9n +.meas tran z_br find v(br) at=11.9n +.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=2n + +.meas tran data_delay_bl trig v(din) val=.5 rise=1 td=.5n targ v(bl) val=.5 rise=1 td=.5n + +.meas tran data_delay_br trig v(din) val=.5 rise=1 td=.5n targ v(br) val=.5 fall=1 td=.5n + +.control +run +write waveform.raw v(din) v(bl) v(br) v(wen) v(vdd) i(Vdd) +quit +.endc +.end diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/problem.md b/tasks/freepdk45/OpenRAM/cases/write_driver/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..d1eb95b95ed1a1461e9c4a0c0b6665a83e82468e --- /dev/null +++ b/tasks/freepdk45/OpenRAM/cases/write_driver/problem.md @@ -0,0 +1,87 @@ +# Complementary SRAM Write Driver Layout Task + +## Objective + +Implement the supplied complementary tri-state write driver: WEN=1 drives BL=DIN and BR=NOT DIN; WEN=0 disables both outputs. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `write_driver`. + +## Inputs and Interface + +Ordered SPICE ports: `din bl br wen vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs. + +## Operating Conditions + +Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist. + +BL and BR each drive 10 fF and a 100 kohm resistor to 0.5 V. DIN starts low, rises at 500 ps and falls at 1 ns, with 10 ps edges and a 1 ns period. WEN is high until 2 ns and falls over 10 ps. Sample the enabled complementary outputs at 300 ps and 710 ps, and both disabled outputs at 11.9 ns. The passive midpoint loads test high impedance without accessing internal nodes. Average DUT supply power over 0–2 ns. + +The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff. + +## Physical Requirements + +Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck. + +The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction. + +Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections. + +## Electrical Requirements and Scoring + +Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `bl_low` | `find v(bl) at=300p` | V | functional check | −∞ … 0.1 | — | +| `br_high` | `find v(br) at=300p` | V | functional check | 0.9 … +∞ | — | +| `bl_high` | `find v(bl) at=710p` | V | functional check | 0.9 … +∞ | — | +| `br_low` | `find v(br) at=710p` | V | functional check | −∞ … 0.1 | — | +| `z_bl` | `find v(bl) at=11.9n` | V | functional check | 0.45 … 0.55 | — | +| `z_br` | `find v(br) at=11.9n` | V | functional check | 0.45 … 0.55 | — | +| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `data_delay` | DIN rising through 0.5 V after 0.5 ns to BL rising or BR falling through 0.5 V; both arcs are source-paired. | s | minimize / ratio | 0 … +∞ | — | + +Area reference: **3.36 um2**. 12 expanded device instances; sum of device/contact envelopes 1.7748 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **3**; it is independent of +the reference-relative task score. + + +### Score weights + +SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.15 | +| `data_delay` | 0.680000000000 | +| `supply` | 0.170000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions. diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/reference/write_driver.gds b/tasks/freepdk45/OpenRAM/cases/write_driver/reference/write_driver.gds new file mode 100644 index 0000000000000000000000000000000000000000..7373ff70f96d1bc3941bd7a9af95daa779e1fd8b Binary files /dev/null and b/tasks/freepdk45/OpenRAM/cases/write_driver/reference/write_driver.gds differ diff --git a/tasks/freepdk45/README.md b/tasks/freepdk45/README.md new file mode 100644 index 0000000000000000000000000000000000000000..932896f300a1969a57783f584de0b5a7c8a7e784 --- /dev/null +++ b/tasks/freepdk45/README.md @@ -0,0 +1,58 @@ +# FreePDK45 Process Scope + +Process manifests pin resources; each case contract defines its operating conditions. +For installation, caching and reference execution, use the evaluator +[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). + +The selected FreePDK45 tasks cover NAND logic, SRAM storage and write drive. +References use the nominal predictive BSIM4 models and candidate-derived Magic +RC under the conditions declared by each case. The +[process manifest](pdk.toml) owns pinned resources and profiles. + +Each problem is self-contained. Its configuration owns the exact devices, loads, +stimuli, observation times, bounds, dimensions and area anchors. Source simulation defines the electrical scoring baseline. Standard-cell area +uses the reference layout; other areas use the frozen compact estimate. Witnesses +are excluded from standard solver inputs. + +## Physical and extraction scope + +The KLayout profile enables all implemented DRC, manufacturing-grid and antenna +checks without waivers. The community deck's POLY.3 spacing is 50 nm, as documented +upstream for Nangate compatibility. The source deck explicitly lacks its different-potential +well-spacing check, so a pass is not complete manufacturing signoff. Strict LVS +flattens an isolated candidate copy with its labels, removes library-specific +`cheat` blocks and implicit/global rail joins, and compares models, W/L, named +ports and real well/tap connectivity. The upstream audit profile is separate and +retains the original library assumptions; it is not the task judge. + +The functional footprint includes drawing layers 1/0 through 29/0, including all +ten routing metals and nine vias. The same layer set supplies the hard 100 by +100 um envelope and scored bounding-box area. Annotation and pin-purpose shapes +are excluded; the contract requires functional routing on drawing layers. + +Magic imports the candidate on its exact DBU grid, filters electrical text to +poly/metal drawing layers and aliases case-insensitive SPICE port names. It +extracts resistances and capacitances from the GDS, with no schematic replacement. +Independent LVS selects the applicable VTG or VTL model class first. The native +RC topology is checked during qualification against the source after removing +capacitors and collapsing parasitic resistors. Simulation always uses the full, +unchanged extracted RC network. + +The predictive extraction uses the community Magic technology's estimated +resistance/capacitance coefficients and its native placement of coupling and +ground capacitance, with nominal VTG/VTL ngspice models at 27 C. Wells and substrate +are lumped connections. This is not calibrated field-solver extraction or a +foundry signoff claim; process variation, substrate noise and RF/EM are outside scope. + +Use `/resources/support/magic-vtg/freepdk45.tech` or the `magic-vtl` counterpart +for evaluation-equivalent extraction, as specified by the case problem. The unified +PDK directory retains the upstream views; reviewed profiles include the adaptations. + +The explicit manifest adaptations map MOS extraction to the LVS-selected model +class, import threshold/annotation markers as non-electrical comments, and correct +`lambda` from 0.025 to **2.5**. Magic expresses this length in centimicrons, so 2.5 +represents the technology's 25 nm internal grid; the upstream value otherwise +extracts a 50 nm gate as 0.5 nm. Upstream coefficients are retained. Qualification +checks the selected published layouts through the complete extraction and simulation +path. This does not establish stream-out equivalence between Magic and KLayout; +the community repository documents known via/metal stream-out differences. diff --git a/tasks/freepdk45/nangate45-pdk/LICENSE b/tasks/freepdk45/nangate45-pdk/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..f433b1a53f5b830a205fd2df78e2b34974656c7b --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/LICENSE @@ -0,0 +1,177 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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For avoidance of doubt, any portions of the Contribution consisting of source code or software are contributed pursuant to the Apache 2.0 license accompanying such material. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + +Documentation is contributed pursuant to the Creative Commons License, Version 4.0 (CCL-4.0). + +This work is licensed under the Creative Common Attribution 4.0 International License. +To view a copy of this license visit: https://creativecommons.org/licenses/by/4.0/ +or send a letter to Creative Commons PO Box 1866, Mountainview CA 94042, USA. + + +Under the terms of this Contribution, the materials are to be posted to Si2’s website (www.si2.org) and made available to members and Universities for download and use at no charge. Non-members may visit https://silvaco.com/services/library-design/ for further information on obtaining the Library. + +Retained source declarations +---------------------------- +This collection retains generated upstream copyright headers, including legacy +proprietary wording, alongside the Apache license and Silvaco/Si2 notice from the +pinned upstream publication. Preserve these declarations together; source URLs +are recorded in the case manifests. diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..a1f775351365d60659cf24ce9565a5a0bce2a2b8 --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml @@ -0,0 +1,1073 @@ +in_core = false +kind = "layout_case" +id = "freepdk45.nangate45-pdk.AOI21_X1" +title = "AND-OR-Invert Gate" +status = "qualified" + +[[assets]] +path = "reference/AOI21_X1.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "bd3f9998b37ef9ed17592ce028beb4b0dd2de95e3f8118eddb4133d66141c3a7" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "freepdk45_aoi21_x1" +coefficient = 2 +environment = "freepdk45-nominal-predictive-rc" + +[task.inputs.description] +path = "problem.md" +sha256 = "4ace260ca69cbe7c09224a583aaffcde13d68ad6fd81ad5bcb2ee9554fe19311" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.spice" +sha256 = "07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e" +format = "spice" +subcircuit = "AOI21_X1" + +[task.inputs.performance] +path = "materials/testbench.spice" +sha256 = "f8401ddcc740853f48b867b25e5bbf895409a9d1df90dfd5b013f31d236aa6b8" +format = "spice" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 2, + 0, + ], + [ + 3, + 0, + ], + [ + 4, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 9, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 12, + 0, + ], + [ + 13, + 0, + ], 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Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +state_0 = "V" +state_1 = "V" +state_2 = "V" +state_3 = "V" +state_4 = "V" +state_5 = "V" +state_6 = "V" +state_7 = "V" +state_8 = "V" +state_9 = "V" +state_10 = "V" +state_11 = "V" +state_12 = "V" +state_13 = "V" +state_14 = "V" +state_15 = "V" +state_16 = "V" +supply = "W" +delay_b1_fall_2 = "s" +transition_b1_fall_2 = "s" +delay_b2_rise_3 = "s" +transition_b2_rise_3 = "s" +delay_a_fall_4 = "s" +transition_a_fall_4 = "s" +delay_a_rise_8 = "s" +transition_a_rise_8 = "s" +delay_a_fall_9 = "s" +transition_a_fall_9 = "s" +delay_a_rise_13 = "s" +transition_a_rise_13 = "s" +delay_b2_fall_14 = "s" +transition_b2_fall_14 = "s" +delay_b1_rise_15 = "s" +transition_b1_rise_15 = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "f8401ddcc740853f48b867b25e5bbf895409a9d1df90dfd5b013f31d236aa6b8" +dut = "07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_fall_4] +value = 1.163873e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_fall_9] +value = 1.228236e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_rise_13] +value = 1.992426e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_rise_8] +value = 1.523821e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b1_fall_2] +value = 1.536536e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b1_rise_15] +value = 1.536857e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b2_fall_14] +value = 1.620396e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b2_rise_3] +value = 1.698568e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_0] +value = 0.999952 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_1] +value = 0.9998967 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_10] +value = 0.0003069374 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_11] +value = 1.216504e-06 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_12] +value = 7.794863e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_13] +value = 0.99935 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_14] +value = 0.0001950317 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_15] +value = 0.9998362 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_16] +value = 0.9997699 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_2] +value = 0.0001918556 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_3] +value = 0.9994024 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_4] +value = 0.0004865273 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_5] +value = 1.239731e-06 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_6] +value = 8.142936e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_7] +value = -3.673975e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_8] +value = 0.9998379 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_9] +value = 0.0004804343 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply] +value = 4.305193e-06 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_fall_4] +value = 1.3624e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_fall_9] +value = 1.274633e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_rise_13] +value = 2.079778e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_rise_8] +value = 1.548592e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b1_fall_2] +value = 1.762384e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b1_rise_15] +value = 1.878498e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b2_fall_14] +value = 1.762316e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b2_rise_3] +value = 2.078537e-11 +unit = "s" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 120 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "strict-lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 60 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-magic-vtl" +technology = "freepdk45.tech" +tech_name = "freepdk45" +style = "spice3(sim)" +gds_readonly = false +case_insensitive_ports = true +label_layers = [ + [ + 9, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 15, + 0, + ], + [ + 17, + 0, + ], + [ + 19, + 0, + ], + [ + 21, + 0, + ], + [ + 23, + 0, + ], + [ + 25, + 0, + ], + [ + 27, + 0, + ], + [ + 29, + 0, + ], +] +timeout_seconds = 120 + +[toolchain.backends.rc.support_profiles] +support = "magic-vtl" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-models" +timeout_seconds = 120 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[qualification] +reference = "reference/AOI21_X1.gds" + +[origin] +url = "https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/AOI21_X1.spi" + +[presentation] +category = "Logic & memory" +summary = "Implements AND-OR-invert logic in a fixed-height standard cell." diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..fc0845ec240e318b670bd8a69e86a18aaa2deb7d --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice @@ -0,0 +1,58 @@ +* +* ****************************************************************************** +* * * +* * Copyright (C) 2004-2010, Nangate Inc. * +* * All rights reserved. * +* * * +* * Nangate and the Nangate logo are trademarks of Nangate Inc. * +* * * +* * All trademarks, logos, software marks, and trade names (collectively the * +* * "Marks") in this program are proprietary to Nangate or other respective * +* * owners that have granted Nangate the right and license to use such Marks. * +* * You are not permitted to use the Marks without the prior written consent * +* * of Nangate or such third party that may own the Marks. * +* * * +* * This file has been provided pursuant to a License Agreement containing * +* * restrictions on its use. This file contains valuable trade secrets and * +* * proprietary information of Nangate Inc., and is protected by U.S. and * +* * international laws and/or treaties. * +* * * +* * The copyright notice(s) in this file does not indicate actual or intended * +* * publication of this file. * +* * * +* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * +* * * +* ****************************************************************************** +* +* +* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). +* Local time is now Fri, 3 Dec 2010, 19:18:00. +* Main process id is 28034. +* +******************************************************************************** +* * +* Cellname: AOI21_X1. * +* * +* Technology: NCSU FreePDK 45nm. * +* Format: Cdl. * +* * +* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * +* at 19:18:00 on Fri, 3 Dec 2010. * +* * +******************************************************************************** +.SUBCKT AOI21_X1 A B1 B2 ZN VDD VSS +*.PININFO A:I B1:I B2:I ZN:O VDD:P VSS:G +*.EQN ZN=!(A + (B1 * B2)) +M_i_1 net_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U +M_i_0 ZN B1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U +M_i_2 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U +M_i_4 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U +M_i_3 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U +M_i_5 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U +.ENDS + +******************************************************************************** +* +* END +* +******************************************************************************** diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/schematic.svg b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..4e5f0015a21942f0ec3a8c89a31febe058f02fde --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/schematic.svg @@ -0,0 +1 @@ +{"format": "iclayout-schematic", "case_id": "freepdk45.nangate45-pdk.AOI21_X1", "netlist_sha256": "07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e", "project_sha256": "5535b59b0dd6c2adde43fbb69c9f4831a61857aea91cd58861bb8d96869dc53e", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Ordered source ports, exact transistor terminals, model and parameter preservation; project schema and editor check", "license": "See collection LICENSE and NOTICE", "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}, "sheets": ["AOI21_X1"], "banks": [], "source_netlist": "tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice", "known_editor_diagnostics": {}}AOI21_X1VSSB2VDDZNB1AM_i_0M_i_1M_i_2M_i_3M_i_4M_i_5AOI21_X1 / AND-OR-InvertZN = NOT (A OR (B1 AND B2))FreePDK45 · Nangate45 · Transistor-level schematicBulk: PMOS → VDD; NMOS → VSS. W/L in µm; display rounded to 3 significant figures.0.415/0.050.415/0.050.415/0.050.63/0.050.63/0.050.63/0.05 diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/testbench.spice b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..e6b126001968fce1b05d01b7696bd86571ad5779 --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/testbench.spice @@ -0,0 +1,52 @@ +* AOI21_X1: exhaustive Gray sequence and reversed sequence +.include /workspace/support/models.spice +.include dut.spice +.temp 27 +Vdd vdd 0 1 +Vss vss 0 0 +Xdut A B1 B2 ZN VDD VSS AOI21_X1 +Cl ZN 0 5f +VA A 0 PWL(0 0 0.500n 0 0.510n 0 1.000n 0 1.010n 0 1.500n 0 1.510n 0 2.000n 0 2.010n 1 2.500n 1 2.510n 1 3.000n 1 3.010n 1 3.500n 1 3.510n 1 4.000n 1 4.010n 0 4.500n 0 4.510n 1 5.000n 1 5.010n 1 5.500n 1 5.510n 1 6.000n 1 6.010n 1 6.500n 1 6.510n 0 7.000n 0 7.010n 0 7.500n 0 7.510n 0 8.000n 0 8.010n 0) +VB1 B1 0 PWL(0 0 0.500n 0 0.510n 0 1.000n 0 1.010n 1 1.500n 1 1.510n 1 2.000n 1 2.010n 1 2.500n 1 2.510n 1 3.000n 1 3.010n 0 3.500n 0 3.510n 0 4.000n 0 4.010n 0 4.500n 0 4.510n 0 5.000n 0 5.010n 0 5.500n 0 5.510n 1 6.000n 1 6.010n 1 6.500n 1 6.510n 1 7.000n 1 7.010n 1 7.500n 1 7.510n 0 8.000n 0 8.010n 0) +VB2 B2 0 PWL(0 0 0.500n 0 0.510n 1 1.000n 1 1.010n 1 1.500n 1 1.510n 0 2.000n 0 2.010n 0 2.500n 0 2.510n 1 3.000n 1 3.010n 1 3.500n 1 3.510n 0 4.000n 0 4.010n 0 4.500n 0 4.510n 0 5.000n 0 5.010n 1 5.500n 1 5.510n 1 6.000n 1 6.010n 0 6.500n 0 6.510n 0 7.000n 0 7.010n 1 7.500n 1 7.510n 1 8.000n 1 8.010n 0) +.tran 0.5p 8.500n +.meas tran state_0 find v(ZN) at=0.110n +.meas tran state_1 find v(ZN) at=0.610n +.meas tran state_2 find v(ZN) at=1.110n +.meas tran state_3 find v(ZN) at=1.610n +.meas tran state_4 find v(ZN) at=2.110n +.meas tran state_5 find v(ZN) at=2.610n +.meas tran state_6 find v(ZN) at=3.110n +.meas tran state_7 find v(ZN) at=3.610n +.meas tran state_8 find v(ZN) at=4.110n +.meas tran state_9 find v(ZN) at=4.610n +.meas tran state_10 find v(ZN) at=5.110n +.meas tran state_11 find v(ZN) at=5.610n +.meas tran state_12 find v(ZN) at=6.110n +.meas tran state_13 find v(ZN) at=6.610n +.meas tran state_14 find v(ZN) at=7.110n +.meas tran state_15 find v(ZN) at=7.610n +.meas tran state_16 find v(ZN) at=8.110n +.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=8.400n +.meas tran delay_b1_fall_2 trig v(B1) val=0.5 rise=1 td=1n targ v(ZN) val=0.5 fall=1 td=1n +.meas tran transition_b1_fall_2 trig v(ZN) val=0.8 fall=1 td=1n targ v(ZN) val=0.2 fall=1 td=1n +.meas tran delay_b2_rise_3 trig v(B2) val=0.5 fall=1 td=1.5n targ v(ZN) val=0.5 rise=1 td=1.5n +.meas tran transition_b2_rise_3 trig v(ZN) val=0.2 rise=1 td=1.5n targ v(ZN) val=0.8 rise=1 td=1.5n +.meas tran delay_a_fall_4 trig v(A) val=0.5 rise=1 td=2n targ v(ZN) val=0.5 fall=1 td=2n +.meas tran transition_a_fall_4 trig v(ZN) val=0.8 fall=1 td=2n targ v(ZN) val=0.2 fall=1 td=2n +.meas tran delay_a_rise_8 trig v(A) val=0.5 fall=1 td=4n targ v(ZN) val=0.5 rise=1 td=4n +.meas tran transition_a_rise_8 trig v(ZN) val=0.2 rise=1 td=4n targ v(ZN) val=0.8 rise=1 td=4n +.meas tran delay_a_fall_9 trig v(A) val=0.5 rise=1 td=4.5n targ v(ZN) val=0.5 fall=1 td=4.5n +.meas tran transition_a_fall_9 trig v(ZN) val=0.8 fall=1 td=4.5n targ v(ZN) val=0.2 fall=1 td=4.5n +.meas tran delay_a_rise_13 trig v(A) val=0.5 fall=1 td=6.5n targ v(ZN) val=0.5 rise=1 td=6.5n +.meas tran transition_a_rise_13 trig v(ZN) val=0.2 rise=1 td=6.5n targ v(ZN) val=0.8 rise=1 td=6.5n +.meas tran delay_b2_fall_14 trig v(B2) val=0.5 rise=1 td=7n targ v(ZN) val=0.5 fall=1 td=7n +.meas tran transition_b2_fall_14 trig v(ZN) val=0.8 fall=1 td=7n targ v(ZN) val=0.2 fall=1 td=7n +.meas tran delay_b1_rise_15 trig v(B1) val=0.5 fall=1 td=7.5n targ v(ZN) val=0.5 rise=1 td=7.5n +.meas tran transition_b1_rise_15 trig v(ZN) val=0.2 rise=1 td=7.5n targ v(ZN) val=0.8 rise=1 td=7.5n +.control +run +write waveform.raw v(A) v(B1) v(B2) v(ZN) v(VDD) i(Vdd) +quit +.endc +.end diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..a73d93003c20e28b15b71169f394d09679c397f2 --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md @@ -0,0 +1,126 @@ +# AND-OR-Invert Gate Layout Task + +## Objective + +Implement ZN = NOT (A OR (B1 AND B2)) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `AOI21_X1`. + +## Inputs and Interface + +Ordered SPICE ports: `A B1 B2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs. + +## Operating Conditions + +Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist. + +ZN drives 5 fF. Apply the three-bit Gray cycle 000, 001, 011, 010, 110, 111, 101, 100, 000 and then its reverse to A/B1/B2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This covers the truth table and both directions of every transition in that cycle. Average DUT supply power over 0–8.4 ns. + +The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff. + +## Physical Requirements + +Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck. + +The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction. + +Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections. + + +The standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply. + +- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um. +- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um. + +## Electrical Requirements and Scoring + +Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — | +| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — | +| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — | +| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — | +| `state_4` | `find v(ZN) at=2.110n` | V | functional check | −∞ … 0.1 | — | +| `state_5` | `find v(ZN) at=2.610n` | V | functional check | −∞ … 0.1 | — | +| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — | +| `state_7` | `find v(ZN) at=3.610n` | V | functional check | −∞ … 0.1 | — | +| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — | +| `state_9` | `find v(ZN) at=4.610n` | V | functional check | −∞ … 0.1 | — | +| `state_10` | `find v(ZN) at=5.110n` | V | functional check | −∞ … 0.1 | — | +| `state_11` | `find v(ZN) at=5.610n` | V | functional check | −∞ … 0.1 | — | +| `state_12` | `find v(ZN) at=6.110n` | V | functional check | −∞ … 0.1 | — | +| `state_13` | `find v(ZN) at=6.610n` | V | functional check | 0.9 … +∞ | — | +| `state_14` | `find v(ZN) at=7.110n` | V | functional check | −∞ … 0.1 | — | +| `state_15` | `find v(ZN) at=7.610n` | V | functional check | 0.9 … +∞ | — | +| `state_16` | `find v(ZN) at=8.110n` | V | functional check | 0.9 … +∞ | — | +| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=8.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `propagation_delay` | Worst paired quality over: delay_b1_fall_2, delay_b2_rise_3, delay_a_fall_4, delay_a_rise_8, delay_a_fall_9, delay_a_rise_13, delay_b2_fall_14, delay_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — | +| `output_transition` | Worst paired quality over: transition_b1_fall_2, transition_b2_rise_3, transition_a_fall_4, transition_a_rise_8, transition_a_fall_9, transition_a_rise_13, transition_b2_fall_14, transition_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — | + +Area reference: **2.0049 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.23 by 1.63 um = 2.0049 um2. Reference SHA-256: 1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94. This footprint includes the maintained explicit taps and routing. + +The capability coefficient remains **2**; it is independent of +the reference-relative task score. + +### Standard-cell design guidance + +Plan the device rows, power rails and signal access before routing. Represent +pull-up and pull-down connectivity as transistor-edge graphs; explore compatible +Euler trails and alternative orderings to share diffusion and reduce breaks. +Choose among legal orderings using routing length, parasitic loading and signal +access, rather than diffusion sharing alone. Preserve the fixed netlist sizes, +models and connectivity; size optimization is outside this task. + +Use the task's declared row height, grid and rail geometry. Keep local routes +compact, leave signal pins accessible, and avoid consuming extra routing layers +without benefit. Check DRC and named-port LVS, then extract the candidate and +compare both transition directions and power with the source simulation. Iterate +on measured parasitic effects rather than visual compactness alone. These are +optional techniques, not a mandated algorithm or reference placement. + +Adapted from Xu et al., *Standard Cell Library Design and Optimization Methodology +for ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing, +track counts and process-specific dimensions do not apply to this task. + + +### Score weights + +Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.2 | +| `propagation_delay` | 0.480000000000 | +| `output_transition` | 0.160000000000 | +| `supply` | 0.160000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions. diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/reference/AOI21_X1.gds b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/reference/AOI21_X1.gds new file mode 100644 index 0000000000000000000000000000000000000000..900da841bd9546223550747c202919e442539021 Binary files /dev/null and b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/reference/AOI21_X1.gds differ diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..48eadb852e491402f7c4bf6d8c025ca076a8bde1 --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml @@ -0,0 +1,872 @@ +in_core = true +kind = "layout_case" +id = "freepdk45.nangate45-pdk.NAND2_X1" +title = "Two-Input NAND" +status = "qualified" + +[[assets]] +path = "reference/NAND2_X1.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "b01b8aa3a1ff8bbe322d92979d9d59e897d655c9e002c7f50b83916ae96b19da" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "freepdk45_nand2_x1" +coefficient = 1 +environment = "freepdk45-nominal-predictive-rc" + +[task.inputs.description] +path = "problem.md" +sha256 = "26feeab7c4edda1754cfed7055c6507b8a04b5383401b55b1761c1dc8f76d454" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.spice" +sha256 = "1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0" +format = "spice" +subcircuit = "NAND2_X1" + +[task.inputs.performance] +path = "materials/testbench.spice" +sha256 = "389d2d09f05913f740d0b776e0fe2d4382057b2bc8a23564f4150adae920e4c9" +format = "spice" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 2, + 0, + ], + [ + 3, + 0, + ], + [ + 4, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 9, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 12, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 15, + 0, + ], + [ + 16, + 0, + ], + [ + 17, + 0, + ], + [ + 18, + 0, + ], + [ + 19, + 0, + ], + [ + 20, + 0, + ], + [ + 21, + 0, + ], + [ + 22, + 0, + ], + [ + 23, + 0, + ], + [ + 24, + 0, + ], + [ + 25, + 0, + ], + [ + 26, + 0, + ], + [ + 27, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], +] +max_width_um = 100 +max_height_um = 100 + +[[task.constraints.hard]] +id = "cell_frame" +type = "cell_frame" +functional_layers = [ + [ + 1, + 0, + ], + [ + 2, + 0, + ], + [ + 3, + 0, + ], + [ + 4, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 9, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 12, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 15, + 0, + ], + [ + 16, + 0, + ], + [ + 17, + 0, + ], + [ + 18, + 0, + ], + [ + 19, + 0, + ], + [ + 20, + 0, + ], + [ + 21, + 0, + ], + [ + 22, + 0, + ], + [ + 23, + 0, + ], + [ + 24, + 0, + ], + [ + 25, + 0, + ], + [ + 26, + 0, + ], + [ + 27, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], +] +height_um = 1.6300000000000001 +width_grid_um = 0.01 + +[[task.constraints.hard.rails]] +name = "VDD" +layer = [ + 11, + 0, +] +connectivity_layer = "metal1" +y_um = 1.5150000000000001 +thickness_um = 0.07 +left_um = 0.115 +right_um = 0.030000000000000002 + +[[task.constraints.hard.rails]] +name = "VSS" +layer = [ + 11, + 0, +] +connectivity_layer = "metal1" +y_um = 0.115 +thickness_um = 0.07 +left_um = 0.115 +right_um = 0.030000000000000002 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "NAND2_X1" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "A1", + "A2", + "ZN", + "VDD", + "VSS", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.jobs.parameters.measurements] +state_0 = "V" +state_1 = "V" +state_2 = "V" +state_3 = "V" +state_4 = "V" +state_5 = "V" +state_6 = "V" +state_7 = "V" +state_8 = "V" +supply = "W" +delay_a1_fall_2 = "s" +transition_a1_fall_2 = "s" +delay_a2_rise_3 = "s" +transition_a2_rise_3 = "s" +delay_a2_fall_6 = "s" +transition_a2_fall_6 = "s" +delay_a1_rise_7 = "s" +transition_a1_rise_7 = "s" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "state_0" +category = "performance" +observations = [ + "nominal:state_0", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "state_1" +category = "performance" +observations = [ + "nominal:state_1", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "state_2" +category = "performance" +observations = [ + "nominal:state_2", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.1 + +[[task.evaluation.metrics]] +id = "state_3" +category = "performance" +observations = [ + "nominal:state_3", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "state_4" +category = "performance" +observations = [ + "nominal:state_4", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "state_5" +category = "performance" +observations = [ + "nominal:state_5", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "state_6" +category = "performance" +observations = [ + "nominal:state_6", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.1 + +[[task.evaluation.metrics]] +id = "state_7" +category = "performance" +observations = [ + "nominal:state_7", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "state_8" +category = "performance" +observations = [ + "nominal:state_8", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.9 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:supply", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_nominal:supply", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "propagation_delay" +category = "performance" +observations = [ + "nominal:delay_a1_fall_2", + "nominal:delay_a2_rise_3", + "nominal:delay_a2_fall_6", + "nominal:delay_a1_rise_7", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +baseline = [ + "source_nominal:delay_a1_fall_2", + "source_nominal:delay_a2_rise_3", + "source_nominal:delay_a2_fall_6", + "source_nominal:delay_a1_rise_7", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "output_transition" +category = "performance" +observations = [ + "nominal:transition_a1_fall_2", + "nominal:transition_a2_rise_3", + "nominal:transition_a2_fall_6", + "nominal:transition_a1_rise_7", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +baseline = [ + "source_nominal:transition_a1_fall_2", + "source_nominal:transition_a2_rise_3", + "source_nominal:transition_a2_fall_6", + "source_nominal:transition_a1_rise_7", +] +normalization = "ratio" +lower = 0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 1.6789 +rationale = "Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.2 +propagation_delay = 0.48 +output_transition = 0.16 +supply = 0.16 + +[task.evaluation.pre_layout] +source_report_sha256 = "76a86a4f03264579807d0206b09e5d64b666842b96240cc4a582b1fc7bf5bf5a" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +state_0 = "V" +state_1 = "V" +state_2 = "V" +state_3 = "V" +state_4 = "V" +state_5 = "V" +state_6 = "V" +state_7 = "V" +state_8 = "V" +supply = "W" +delay_a1_fall_2 = "s" +transition_a1_fall_2 = "s" +delay_a2_rise_3 = "s" +transition_a2_rise_3 = "s" +delay_a2_fall_6 = "s" +transition_a2_fall_6 = "s" +delay_a1_rise_7 = "s" +transition_a1_rise_7 = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "389d2d09f05913f740d0b776e0fe2d4382057b2bc8a23564f4150adae920e4c9" +dut = "1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a1_fall_2] +value = 1.430693e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a1_rise_7] +value = 9.335134e-12 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a2_fall_6] +value = 1.515943e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a2_rise_3] +value = 1.022087e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_0] +value = 0.9999975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_1] +value = 0.9999739 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_2] +value = 0.0001741408 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_3] +value = 0.9998214 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_4] +value = 0.999999 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_5] +value = 0.9999582 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_6] +value = 0.0001756712 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_7] +value = 0.9999739 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_8] +value = 0.9999406 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply] +value = 3.425277e-06 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a1_fall_2] +value = 1.658675e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a1_rise_7] +value = 9.668356e-12 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a2_fall_6] +value = 1.658596e-11 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a2_rise_3] +value = 1.080812e-11 +unit = "s" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 120 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 120 +support = "build/support/freepdk45-klayout" +profile = "strict-lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 60 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-magic-vtl" +technology = "freepdk45.tech" +tech_name = "freepdk45" +style = "spice3(sim)" +gds_readonly = false +case_insensitive_ports = true +label_layers = [ + [ + 9, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 15, + 0, + ], + [ + 17, + 0, + ], + [ + 19, + 0, + ], + [ + 21, + 0, + ], + [ + 23, + 0, + ], + [ + 25, + 0, + ], + [ + 27, + 0, + ], + [ + 29, + 0, + ], +] +timeout_seconds = 120 + +[toolchain.backends.rc.support_profiles] +support = "magic-vtl" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/freepdk45-models" +timeout_seconds = 120 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[qualification] +reference = "reference/NAND2_X1.gds" + +[origin] +url = "https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/NAND2_X1.spi" + +[presentation] +category = "Logic & memory" +summary = "Implements two-input NAND logic in a fixed-height standard cell." diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..f9a9227cc4bed4be8c97bf6078983e4aeaf7b614 --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice @@ -0,0 +1,56 @@ +* +* ****************************************************************************** +* * * +* * Copyright (C) 2004-2010, Nangate Inc. * +* * All rights reserved. * +* * * +* * Nangate and the Nangate logo are trademarks of Nangate Inc. * +* * * +* * All trademarks, logos, software marks, and trade names (collectively the * +* * "Marks") in this program are proprietary to Nangate or other respective * +* * owners that have granted Nangate the right and license to use such Marks. * +* * You are not permitted to use the Marks without the prior written consent * +* * of Nangate or such third party that may own the Marks. * +* * * +* * This file has been provided pursuant to a License Agreement containing * +* * restrictions on its use. This file contains valuable trade secrets and * +* * proprietary information of Nangate Inc., and is protected by U.S. and * +* * international laws and/or treaties. * +* * * +* * The copyright notice(s) in this file does not indicate actual or intended * +* * publication of this file. * +* * * +* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * +* * * +* ****************************************************************************** +* +* +* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). +* Local time is now Fri, 3 Dec 2010, 19:22:54. +* Main process id is 28034. +* +******************************************************************************** +* * +* Cellname: NAND2_X1. * +* * +* Technology: NCSU FreePDK 45nm. * +* Format: Cdl. * +* * +* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * +* at 19:22:54 on Fri, 3 Dec 2010. * +* * +******************************************************************************** +.SUBCKT NAND2_X1 A1 A2 ZN VDD VSS +*.PININFO A1:I A2:I ZN:O VDD:P VSS:G +*.EQN ZN=!(A1 * A2) +M_i_1 net_0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U +M_i_0 ZN A1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U +M_i_3 ZN A2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U +M_i_2 VDD A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U +.ENDS + +******************************************************************************** +* +* END +* +******************************************************************************** diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/schematic.svg b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..90c3950f40ed1bb15bbdbc76f1df7b6b32a0862d --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/schematic.svg @@ -0,0 +1 @@ +{"format": "iclayout-schematic", "case_id": "freepdk45.nangate45-pdk.NAND2_X1", "netlist_sha256": "1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0", "project_sha256": "a121482bae0f047de3299bddc4307660a7d8a636be910d96130e311ed5b12232", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Ordered source ports, exact transistor terminals, model and parameter preservation; project schema and editor check", "license": "See collection LICENSE and NOTICE", "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}, "sheets": ["NAND2_X1"], "banks": [], "source_netlist": "tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice", "known_editor_diagnostics": {}}NAND2_X1A2VDDA1ZNVSSM_i_0M_i_1M_i_2M_i_3NAND2_X1 / Two-input NANDZN = NOT (A1 AND A2)FreePDK45 · Nangate45 · Transistor-level schematicBulk: PMOS → VDD; NMOS → VSS. W/L in µm; display rounded to 3 significant figures.0.415/0.050.415/0.050.63/0.050.63/0.05 diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/testbench.spice b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..514741578709d166f28546d289b7c636ebf4c5dd --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/testbench.spice @@ -0,0 +1,35 @@ +* NAND2_X1: exhaustive Gray sequence and reversed sequence +.include /workspace/support/models.spice +.include dut.spice +.temp 27 +Vdd vdd 0 1 +Vss vss 0 0 +Xdut A1 A2 ZN VDD VSS NAND2_X1 +Cl ZN 0 5f +VA1 A1 0 PWL(0 0 0.500n 0 0.510n 0 1.000n 0 1.010n 1 1.500n 1 1.510n 1 2.000n 1 2.010n 0 2.500n 0 2.510n 1 3.000n 1 3.010n 1 3.500n 1 3.510n 0 4.000n 0 4.010n 0) +VA2 A2 0 PWL(0 0 0.500n 0 0.510n 1 1.000n 1 1.010n 1 1.500n 1 1.510n 0 2.000n 0 2.010n 0 2.500n 0 2.510n 0 3.000n 0 3.010n 1 3.500n 1 3.510n 1 4.000n 1 4.010n 0) +.tran 0.5p 4.500n +.meas tran state_0 find v(ZN) at=0.110n +.meas tran state_1 find v(ZN) at=0.610n +.meas tran state_2 find v(ZN) at=1.110n +.meas tran state_3 find v(ZN) at=1.610n +.meas tran state_4 find v(ZN) at=2.110n +.meas tran state_5 find v(ZN) at=2.610n +.meas tran state_6 find v(ZN) at=3.110n +.meas tran state_7 find v(ZN) at=3.610n +.meas tran state_8 find v(ZN) at=4.110n +.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=4.400n +.meas tran delay_a1_fall_2 trig v(A1) val=0.5 rise=1 td=1n targ v(ZN) val=0.5 fall=1 td=1n +.meas tran transition_a1_fall_2 trig v(ZN) val=0.8 fall=1 td=1n targ v(ZN) val=0.2 fall=1 td=1n +.meas tran delay_a2_rise_3 trig v(A2) val=0.5 fall=1 td=1.5n targ v(ZN) val=0.5 rise=1 td=1.5n +.meas tran transition_a2_rise_3 trig v(ZN) val=0.2 rise=1 td=1.5n targ v(ZN) val=0.8 rise=1 td=1.5n +.meas tran delay_a2_fall_6 trig v(A2) val=0.5 rise=1 td=3n targ v(ZN) val=0.5 fall=1 td=3n +.meas tran transition_a2_fall_6 trig v(ZN) val=0.8 fall=1 td=3n targ v(ZN) val=0.2 fall=1 td=3n +.meas tran delay_a1_rise_7 trig v(A1) val=0.5 fall=1 td=3.5n targ v(ZN) val=0.5 rise=1 td=3.5n +.meas tran transition_a1_rise_7 trig v(ZN) val=0.2 rise=1 td=3.5n targ v(ZN) val=0.8 rise=1 td=3.5n +.control +run +write waveform.raw v(A1) v(A2) v(ZN) v(VDD) i(Vdd) +quit +.endc +.end diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..50cde32c4b01c1db23c47cdce78a3eff9340e717 --- /dev/null +++ b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md @@ -0,0 +1,118 @@ +# Two-Input NAND Layout Task + +## Objective + +Implement ZN = NOT (A1 AND A2) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `NAND2_X1`. + +## Inputs and Interface + +Ordered SPICE ports: `A1 A2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs. + +## Operating Conditions + +Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist. + +ZN drives 5 fF. Apply 00, 01, 11, 10, 00, 10, 11, 01, 00 to A1/A2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This visits the full truth table and both directions of each single-input transition. Average DUT supply power over 0–4.4 ns. + +The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff. + +## Physical Requirements + +Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck. + +The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction. + +Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections. + + +The standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply. + +- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um. +- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um. + +## Electrical Requirements and Scoring + +Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — | +| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — | +| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — | +| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — | +| `state_4` | `find v(ZN) at=2.110n` | V | functional check | 0.9 … +∞ | — | +| `state_5` | `find v(ZN) at=2.610n` | V | functional check | 0.9 … +∞ | — | +| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — | +| `state_7` | `find v(ZN) at=3.610n` | V | functional check | 0.9 … +∞ | — | +| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — | +| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=4.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `propagation_delay` | Worst paired quality over: delay_a1_fall_2, delay_a2_rise_3, delay_a2_fall_6, delay_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — | +| `output_transition` | Worst paired quality over: transition_a1_fall_2, transition_a2_rise_3, transition_a2_fall_6, transition_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — | + +Area reference: **1.6789 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.03 by 1.63 um = 1.6789 um2. Reference SHA-256: d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f. This footprint includes the maintained explicit taps and routing. + +The capability coefficient remains **1**; it is independent of +the reference-relative task score. + +### Standard-cell design guidance + +Plan the device rows, power rails and signal access before routing. Represent +pull-up and pull-down connectivity as transistor-edge graphs; explore compatible +Euler trails and alternative orderings to share diffusion and reduce breaks. +Choose among legal orderings using routing length, parasitic loading and signal +access, rather than diffusion sharing alone. Preserve the fixed netlist sizes, +models and connectivity; size optimization is outside this task. + +Use the task's declared row height, grid and rail geometry. Keep local routes +compact, leave signal pins accessible, and avoid consuming extra routing layers +without benefit. Check DRC and named-port LVS, then extract the candidate and +compare both transition directions and power with the source simulation. Iterate +on measured parasitic effects rather than visual compactness alone. These are +optional techniques, not a mandated algorithm or reference placement. + +Adapted from Xu et al., *Standard Cell Library Design and Optimization Methodology +for ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing, +track counts and process-specific dimensions do not apply to this task. + + +### Score weights + +Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.2 | +| `propagation_delay` | 0.480000000000 | +| `output_transition` | 0.160000000000 | +| `supply` | 0.160000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions. diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/reference/NAND2_X1.gds b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/reference/NAND2_X1.gds new file mode 100644 index 0000000000000000000000000000000000000000..f27f90c18acc0f3f21c70209d343532f9cff89b1 Binary files /dev/null and b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/reference/NAND2_X1.gds differ diff --git a/tasks/freepdk45/pdk.toml b/tasks/freepdk45/pdk.toml new file mode 100644 index 0000000000000000000000000000000000000000..0d52b429efc3c9bc40792e74271741422a54afd9 --- /dev/null +++ b/tasks/freepdk45/pdk.toml @@ -0,0 +1,353 @@ +[agent] +id = "freepdk45" +support_profiles = [ + "models", + "klayout", + "magic-vtg", + "magic-vtl", +] +checks = [ + [ + "python", + "-c", + "import pya; t=pya.Technology(); t.load('/resources/pdks/freepdk45/libs.tech/klayout/tech/freepdk45/freepdk45.lyt'); assert t.name; print('FreePDK45 technology loaded:', t.name)", + ], +] + +[agent.sources.freepdk45] +installation = true +path = "freepdk45" + +[agent.environment] +ICLAYOUT_BENCH_PDK = "freepdk45" +PDK_ROOT = "/resources/pdks" +PDK_PATH = "/resources/pdks/freepdk45" +KLAYOUT_PATH = "/resources/pdks/freepdk45/libs.tech/klayout" + +[source] +repository = "https://github.com/rjordans/freepdk45-open-pdks.git" +commit = "ab8b395503e5b6149f76549abfd375e7cbb156cc" +license = "Component licenses in libs.tech/klayout/LICENSE and libs.tech/ngspice/APACHE-LICENSE-2.0.txt" + +[profiles.klayout.files."upstream/drc.lydrc"] +path = "freepdk45/libs.tech/klayout/tech/freepdk45/drc/drc_freepdk45.lydrc" +format = "text" + +[profiles.klayout.files."upstream/lvs.lylvs"] +path = "freepdk45/libs.tech/klayout/tech/freepdk45/lvs/lvs_freepdk45.lylvs" +format = "text" + +[profiles.klayout.generated."freepdk45.drc"] +content = """ +# ICLayout-Bench CLI adapter; original rules and switches are unchanged. +$output = $report +eval(RBA::Macro.new(\"/workspace/support/upstream/drc.lydrc\").text, binding) +""" +format = "text" + +[profiles.klayout.generated."strict.lvs"] +content = """ +# ICLayout-Bench strict candidate LVS; modified from the pinned BSD-3-Clause macro. +# Preserve device extraction and physical connectivity. Require real body taps, +# exact model/width/length and named ports; no cell-name shortcuts or pin swaps. +code = RBA::Macro.new(\"/workspace/support/upstream/lvs.lylvs\").text +# Promote geometry AND text labels through wrappers before reading DSL layers. +# The immutable original candidate remains available to all other gates. +flat_layout = RBA::Layout.new +flat_layout.read($input) +flat_layout.cell($topcell).flatten(true) +flat_layout.write(\"/workspace/flat-candidate.gds\") +code = code.sub(\"source($input)\", 'source(\"/workspace/flat-candidate.gds\", $topcell)') +code = code.sub(\"report($report)\", \"report_lvs($report)\") +# Flatten for candidate checks so an electrically empty wrapper cannot hide its child. +code = code.sub(\"\\ndeep\\n\", \"\\n\") +code = code.sub(/cheat\\([^ +]+\\) \\{\\s* +/, \"\") +code = code.sub(\"\\n}\\n\\n# Define connectivity\", \"\\n# Define connectivity\") +code = code.sub(/# Global.*?# Actually performs the extraction/m, \"schematic.simplify\\n# Actually performs the extraction\") +code = code.sub(/# Tolerances for.*?max_branch_complexity/m, \"max_branch_complexity\") +raise \"Unexpected upstream shortcut remains\" if code.match?(/connect_global|connect_explicit|connect_implicit|equivalent_pins|cheat\\(/) +metal1 = nil +eval(code, binding) +""" +format = "text" + +[profiles.klayout.generated."drc.json"] +content = """ +{ + \"deck\": \"freepdk45.drc\", + \"variables\": {}, + \"scope\": \"All upstream DRC, antenna and off-grid checks; no waivers.\", + \"required_categories\": [ + \"'WELL.1'\", + \"'WELL.3'\", + \"'WELL.4'\", + \"'VT.1'\", + \"'POLY.1'\", + \"'POLY.3'\", + \"'POLY.4'\", + \"'POLY.5'\", + \"'POLY.6'\", + \"'ACTIVE.1'\", + \"'ACTIVE.2'\", + \"'ACTIVE.3'\", + \"'ACTIVE.4'\", + \"'IMPLANT.1'\", + \"'IMPLANT.2'\", + \"'IMPLANT.3'\", + \"'IMPLANT.4'\", + \"'IMPLANT.5'\", + \"'CONTACT.1'\", + \"'CONTACT.2'\", + \"'CONTACT.3'\", + \"'CONTACT.4'\", + \"'CONTACT.5'\", + \"'CONTACT.6'\", + \"'METAL1.1'\", + \"'METAL1.2'\", + \"'METAL1.3'\", + \"'METAL1.4'\", + \"'METAL1.5'\", + \"'METAL1.6'\", + \"'METAL1.7'\", + \"'METAL1.8'\", + \"'METAL1.9'\", + \"'VIA1.1'\", + \"'VIA1.2'\", + \"'VIA1.3'\", + \"'VIA1.4'\", + \"'METAL2.1'\", + \"'METAL2.2'\", + \"'METAL2.3'\", + \"'METAL2.4'\", + \"'METAL2.5'\", + \"'METAL2.6'\", + \"'METAL2.7'\", + \"'METAL2.8'\", + \"'METAL2.9'\", + \"'VIA2.1'\", + \"'VIA2.2'\", + \"'VIA2.3'\", + \"'VIA2.4'\", + \"'METAL3.1'\", + \"'METAL3.2'\", + \"'METAL3.3'\", + \"'METAL3.4'\", + \"'METAL3.5'\", + \"'METAL3.6'\", + \"'METAL3.7'\", + \"'METAL3.8'\", + \"'METAL3.9'\", + \"'VIA3.1'\", + \"'VIA3.2'\", + \"'VIA3.3'\", + \"'VIA3.4'\", + \"'METAL4.1'\", + \"'METAL4.2'\", + \"'METAL4.6'\", + \"'METAL4.7'\", + \"'METAL4.8'\", + \"'VIA4.1'\", + \"'VIA4.2'\", + \"'VIA4.3'\", + \"'VIA4.4'\", + \"'METAL5.1'\", + \"'METAL5.2'\", + \"'METAL5.6'\", + \"'METAL5.7'\", + \"'METAL5.8'\", + \"'VIA5.1'\", + \"'VIA5.2'\", + \"'VIA5.3'\", + \"'VIA5.4'\", + \"'METAL6.1'\", + \"'METAL6.2'\", + \"'METAL6.6'\", + \"'METAL6.7'\", + \"'METAL6.8'\", + \"'VIA6.1'\", + \"'VIA6.2'\", + \"'VIA6.3'\", + \"'VIA6.4'\", + \"'METAL7.1'\", + \"'METAL7.2'\", + \"'METAL7.7'\", + \"'METAL7.8'\", + \"'METAL7.9'\", + \"'VIA7.3'\", + \"'VIA7.4'\", + \"'METAL8.1'\", + \"'METAL8.2'\", + \"'METAL8.7'\", + \"'METAL8.8'\", + \"'METAL8.9'\", + \"'VIA8.1'\", + \"'VIA8.2'\", + \"'VIA8.3'\", + \"'VIA8.4'\", + \"'METAL9.1'\", + \"'METAL9.2'\", + \"'METAL9.7'\", + \"'METAL9.8'\", + \"'METAL9.9'\", + \"'VIA9.1'\", + \"'VIA9.2'\", + \"'VIA9.3'\", + \"'VIA9.4'\", + \"'METAL10.1'\", + \"'METAL10.2'\", + \"'METAL10.7'\", + \"'METAL10.8'\", + \"'METAL10.9'\", + \"'GRID: vertexes on layer well not on grid of 0.0025'\", + \"'GRID: vertexes on layer active not on grid of 0.0025'\", + \"'GRID: vertexes on layer vtg not on grid of 0.0025'\", + \"'GRID: vertexes on layer vth not on grid of 0.0025'\", + \"'GRID: vertexes on layer pplus not on grid of 0.0025'\", + \"'GRID: vertexes on layer nplus not on grid of 0.0025'\", + \"'GRID: vertexes on layer poly not on grid of 0.0025'\", + \"'GRID: vertexes on layer thkox not on grid of 0.0025'\", + \"'GRID: vertexes on layer cont not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal1 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via1 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal2 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via2 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal3 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via3 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal4 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via4 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal5 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via5 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal6 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via6 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal7 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via7 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal8 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via8 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal9 not on grid of 0.0025'\", + \"'GRID: vertexes on layer via9 not on grid of 0.0025'\", + \"'GRID: vertexes on layer metal10 not on grid of 0.0025'\", + \"METAL1_ANTENNA\", + \"METAL2_ANTENNA\", + \"METAL3_ANTENNA\", + \"METAL4_ANTENNA\", + \"METAL5_ANTENNA\", + \"METAL6_ANTENNA\", + \"METAL7_ANTENNA\", + \"METAL8_ANTENNA\", + \"METAL9_ANTENNA\", + \"METAL10_ANTENNA\" + ] +} +""" +format = "json" + +[profiles.klayout.generated."strict-lvs.json"] +content = """ +{ + \"deck\": \"strict.lvs\", + \"layer_names\": {\"metal1\": \"metal1\"}, + \"variables\": {}, + \"scope\": \"Physical well/tap connectivity, no global or implicit connections, no cell-name cheat blocks, exact MOS W/L, named ports.\" +} +""" +format = "json" + +[profiles.models] +check = [ + "python", + "/resources/pdk-check.py", + "models", + "NMOS_VTL", + "models.spice", + "--length", + "50n", + "--width", + "200n", +] + +[profiles.models.files."NMOS_VTG.inc"] +path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/NMOS_VTG.inc" +format = "text" + +[profiles.models.files."PMOS_VTG.inc"] +path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/PMOS_VTG.inc" +format = "text" + +[profiles.models.files."NMOS_VTL.inc"] +path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/NMOS_VTL.inc" +format = "text" + +[profiles.models.files."PMOS_VTL.inc"] +path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/PMOS_VTL.inc" +format = "text" + +[profiles.models.generated."models.spice"] +format = "spice" +content = """ +.include /workspace/support/NMOS_VTG.inc +.include /workspace/support/PMOS_VTG.inc +.include /workspace/support/NMOS_VTL.inc +.include /workspace/support/PMOS_VTL.inc +""" + +[profiles.magic-vtg.files."freepdk45.tech"] +path = "freepdk45/libs.tech/magic/freepdk45.tech" +format = "text" + +[[profiles.magic-vtg.files."freepdk45.tech".replace]] +old = "device msubcircuit pmos pfet *pdiff *pdiff nwell error l=l w=w" +new = "device mosfet PMOS_VTG pfet pdiff,pdc nwell" + +[[profiles.magic-vtg.files."freepdk45.tech".replace]] +old = "device msubcircuit nmos nfet *ndiff *ndiff psub,space/w error l=l w=w" +new = "device mosfet NMOS_VTG nfet ndiff,ndc psub,space/w" + +[[profiles.magic-vtg.files."freepdk45.tech".replace]] +old = " calma TEXT 63 63" +new = """ + calma TEXT 63 63 + calma VTG 6 0 + calma VTH 7 0 + calma THKOX 8 0 + calma ANNOTATION 239 0 + calma BOUNDARY230 230 0""" + +[[profiles.magic-vtg.files."freepdk45.tech".replace]] +old = " layer comment TEXT" +new = " layer comment TEXT,VTG,VTH,THKOX,ANNOTATION,BOUNDARY230" + +[[profiles.magic-vtg.files."freepdk45.tech".replace]] +old = " lambda 0.025" +new = " lambda 2.5" + +[profiles.magic-vtl.files."freepdk45.tech"] +path = "freepdk45/libs.tech/magic/freepdk45.tech" +format = "text" + +[[profiles.magic-vtl.files."freepdk45.tech".replace]] +old = "device msubcircuit pmos pfet *pdiff *pdiff nwell error l=l w=w" +new = "device mosfet PMOS_VTL pfet pdiff,pdc nwell" + +[[profiles.magic-vtl.files."freepdk45.tech".replace]] +old = "device msubcircuit nmos nfet *ndiff *ndiff psub,space/w error l=l w=w" +new = "device mosfet NMOS_VTL nfet ndiff,ndc psub,space/w" + +[[profiles.magic-vtl.files."freepdk45.tech".replace]] +old = " calma TEXT 63 63" +new = """ + calma TEXT 63 63 + calma VTG 6 0 + calma VTH 7 0 + calma THKOX 8 0 + calma ANNOTATION 239 0 + calma BOUNDARY230 230 0""" + +[[profiles.magic-vtl.files."freepdk45.tech".replace]] +old = " layer comment TEXT" +new = " layer comment TEXT,VTG,VTH,THKOX,ANNOTATION,BOUNDARY230" + +[[profiles.magic-vtl.files."freepdk45.tech".replace]] +old = " lambda 0.025" +new = " lambda 2.5" diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE b/tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..57dfbb28ac6228969f83f32ceb3e58342f054043 --- /dev/null +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE @@ -0,0 +1,202 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2026 2AM Logic + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..d7819c12bb2e38e8cf71e03df56fffdce1fa01d7 --- /dev/null +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml @@ -0,0 +1,775 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.2AMLogic-sar-adc.track_switch" +title = "Dummy-Compensated Track Switch" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "e5f06c8b3160abc3605f55603d74694c7f96faf76ec2eab893cfcbb0eafc2a07" + +[[assets]] +path = "reference/adc_tgate_dum.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "ac42852033a1e1372d70dbd6fab92e35c668fda8c2ede932e71ef47511cc9db2" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_track_switch" +coefficient = 4 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "61dad99299cb63987ff9252905cf3c0b7db5b8d24d74c07b27a2b0f962346c87" + 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+] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vin", + "vout", + "clk", + "clkb", + "vdd", + "vss", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +track_high = "V" +track_again = "V" +track_low = "V" +hold_error_v = "V" +settle_s = "s" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "high" +category = "performance" +observations = [ + "nominal:track_high", + "nominal:track_again", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 2.48 +upper = 2.52 + +[[task.evaluation.metrics]] +id = "low" +category = "performance" +observations = [ + "nominal:track_low", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0.48 +upper = 0.52 + +[[task.evaluation.metrics]] +id = "hold" +category = "performance" +observations = [ + "nominal:hold_error_v", +] +unit = "V" +direction = "minimize" +aggregation = "max" +dimension = "response" +baseline = [ + "source_nominal:hold_error_v", +] +normalization = "ratio" +scale = 0.02 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "settling" +category = "performance" +observations = [ + "nominal:settle_s", +] +unit = "s" +direction = "minimize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:settle_s", +] +normalization = "ratio" +lower = 0 +scale = 1e-15 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 702.46 +rationale = "Track/hold switches: acquisition 39.4%; hold fidelity 50.6%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +settling = 0.39375 +hold = 0.50625 + +[task.evaluation.pre_layout] +source_report_sha256 = "226b4e1cf76a5bf2e7fd15531853087715beec009c901ae6d2fd68c87c68f287" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +track_high = "V" +track_again = "V" +track_low = "V" +hold_error_v = "V" +settle_s = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.values] + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "35039b03b178d1954f4a5caf712b05ecf0780f12128b6d0028db9ea9ead924c5" +dut = "24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.hold_error_v] +value = 0.003106877 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.settle_s] +value = 4.361648e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.track_again] +value = 2.5 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.track_high] +value = 2.5 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.track_low] +value = 0.5 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/2AMLogic/gf180-sar-adc/tree/c32c8da53e52fbb7d75f6f628b8cc9f6f45a13fc/design/adc-top/adc_top.spice" + +[qualification] +reference = "reference/adc_tgate_dum.gds" + +[presentation] +category = "Mixed-signal" +summary = "Tracks an analog input through a transmission gate with dummy compensation." diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..514e2bd206823cb989aa1919e8fdabcfd7feb418 --- /dev/null +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice @@ -0,0 +1,7 @@ +* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed. +.subckt adc_tgate_dum vin vout clk clkb vdd vss +XN vin clk vout vss nfet_03v3 w=40u l=0.28u +XP vin clkb vout vdd pfet_03v3 w=80u l=0.28u +XDN vout clkb vout vss nfet_03v3 w=17.5u l=0.28u +XDP vout clk vout vdd pfet_03v3 w=35u l=0.28u +.ends adc_tgate_dum diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/schematic.svg b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..0a234ca5b5a9f52a85819522cab34efe9df42b9f --- /dev/null +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/schematic.svg @@ -0,0 +1 @@ +track_switch{"format": "iclayout-schematic", "case_id": "gf180mcuD.2AMLogic-sar-adc.track_switch", "netlist_sha256": "24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd", "project_sha256": "a98f22d7060564d6b3fe83b9bd0292a9b1a8cb3831c4cad1f62ba49cd7fea544", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/2AMLogic-sar-adc/", "sheets": ["adc_tgate_dum"], "banks": [], "source_netlist": "tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}adc_tgate_dumclkbclkvinvoutclkclkbvoutvinvoutclkclkbvddvsstrack_switchgf180mcuD · 2AMLogic-sar-adc | W/L in µm · display rounded to 3 significant figures01 Transmission gateXP80/0.28XN40/0.28P bulk → vddN bulk → vss02 Charge-injection dummiesXDP35/0.28XDN17.5/0.28P bulk → vddN bulk → vssModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/testbench.spice b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..a7fff390fa87aba294853b4ec3e765bca9c0a102 --- /dev/null +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/testbench.spice @@ -0,0 +1,24 @@ +* GF180MCU nominal characterization: 3.3 V, 27 C, typical models. +.include "support/models.spice" +.include "dut.spice" +.include "parameters.spice" +.temp 27 +VDD vdd 0 3.3 +VIN vin 0 PWL(0 .5 5n .5 5.1n 2.5 30n 2.5 30.1n .5 55n .5 55.1n 2.5) +VCLK clk 0 PWL(0 3.3 20n 3.3 20.1n 0 45n 0 45.1n 3.3) +VCLKB clkb 0 PWL(0 0 20n 0 20.1n 3.3 45n 3.3 45.1n 0) +CLOAD out 0 1p +XDUT vin out clk clkb vdd 0 adc_tgate_dum +.control +tran .01n 70n +meas tran track_high find v(out) at=19n +meas tran hold_high find v(out) at=44n +meas tran track_low find v(out) at=54n +meas tran track_again find v(out) at=69n +meas tran settle_s trig v(vin) val=1.5 rise=1 targ v(out) val=2.48 rise=1 +let hold_error=abs(v(out)-2.5) +meas tran hold_error_v max hold_error from=21n to=44n +write waveform.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..c4aaa7b8698c32823201c9bdbff75ae39b9dfb57 --- /dev/null +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md @@ -0,0 +1,97 @@ +# Dummy-Compensated Track Switch Layout Task + +## Objective + +Implement `adc_tgate_dum` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Complementary-clock tracking, settling and hold feedthrough for 0.5 V / 2.5 V steps and a 1 pF output capacitor. + +## Inputs and Interface + +The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration. + +Ordered subcircuit and GDS interface: `vin, vout, clk, clkb, vdd, vss`. +vin: signal input; vout: sampled output; clk/clkb: complementary track control; vdd/vss: supply and device body connections. + +Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together. + +## Operating Conditions + +Use 3.3 V and 27 C with a 1 pF capacitor from vout to vss. Vin begins at 0.5 V, rises to 2.5 V at 5.1 ns, falls to 0.5 V at 30.1 ns and rises to 2.5 V at 55.1 ns. Track initially (clk=3.3 V, clkb=0 V), hold from 20.1 to 45 ns and resume tracking at 45.1 ns. All transitions take 0.1 ns. Simulate to 70 ns with a 0.01 ns requested step. The four MOS widths are fixed to the upstream default values: 40, 80, 17.5 and 35 um; every channel length is 0.28 um. vss is the explicit form of the original global ground connection. + +Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope. + +## Physical Requirements + +Submit a nonempty GDS with top cell `adc_tgate_dum` and at most 10485760 bytes. Its functional bounding box must not exceed 160 by 160 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is: + +`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`. + +Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block. + +LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `high` | vout at 19 and 69 ns. | V | functional check | 2.48 … 2.52 | — | +| `low` | vout at 54 ns, after tracking resumes with vin=0.5 V. | V | functional check | 0.48 … 0.52 | — | +| `hold` | Maximum absolute vout-2.5 V over 21–44 ns, including the vin transition while the switch is open. | V | minimize / ratio | 0 … 3.3 | 0.02 | +| `settling` | First vin rising 1.5 V crossing to vout reaching 2.48 V. | s | minimize / ratio | 0 … +∞ | 1e-15 | + +The tracking checks define a 1% settling-accuracy task: 20 mV is 1% of +the declared 2 V input step. Both sampled tracking levels must meet that +accuracy; the settling measurement uses the same high-level boundary. +This is an explicit sampled acquisition requirement, not a tolerance fitted +to the reference layout. Hold error remains continuous quality, with q=(source_error+0.02 V)/ +(candidate_error+0.02 V), so reducing absolute error always improves quality. +The 20 mV floor uses the declared acquisition-accuracy scale and keeps +near-zero source error well-conditioned; it is not a hold-error pass threshold. + +Area reference: **702.46 um2**. 4 expanded device instances; sum of device/contact envelopes 411.5400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **4**; it is independent of +the reference-relative task score. + + +### Score weights + +Track/hold switches: acquisition 39.4%; hold fidelity 50.6%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `settling` | 0.393750000000 | +| `hold` | 0.506250000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/reference/adc_tgate_dum.gds b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/reference/adc_tgate_dum.gds new file mode 100644 index 0000000000000000000000000000000000000000..2670e1040c5e43841baa9e73b46e6449a3d3808e Binary files /dev/null and b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/reference/adc_tgate_dum.gds differ diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/LICENSE b/tasks/gf180mcuD/Chipathon2023_ADC/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..1d36b303b17a1fb426660c058a4c2bd4040b02f1 --- /dev/null +++ b/tasks/gf180mcuD/Chipathon2023_ADC/LICENSE @@ -0,0 +1,231 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + +GF180 primitive symbol export expressions in materials/circuit.spice +================================================================== +Copyright 2022 GlobalFoundries PDK Authors. Licensed under Apache-2.0. +Source: gf180mcu_fd_pr/cells/xschem/symbols; exported MOS geometry expressions. +# This is the list of GlobalFoundries PDK's significant contributors. +# +# This does not necessarily list everyone who has contributed code, +# especially since many employees of one corporation may be contributing. +# To see the full list of contributors, see the revision history in +# source control. + +# Companies +Google LLC +GlobalFoundries +Efabless Corporation +Mabrains LLC + +# Individuals +tansell@google.com, me@mith.ro (Tim 'mithro' Ansell) +proppy@google.com (Johan 'proppy' Euphrosine) +tim@efabless.com (Tim Edwards) +mkk@efabless.com (Mohamed Kassem) +stefan.schippers@gmail.com (Stefan Schippers) +amro_tork@mabrains.com (Amro Tork) +farag_agoor@mabrains.com (Farag Agoor) +mohanad_mohamed@mabrains.com (Mohanad Mohammed) + +The Apache-2.0 license text above also applies to these expressions. diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml 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C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_negative] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_negative.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_negative.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_negative.parameters.measurements] +decision_v = "V" +delay_s = "s" +power_w = "W" + +[task.evaluation.pre_layout.jobs.source_negative.parameters.values] +polarity = -1 + +[task.evaluation.pre_layout.jobs.source_negative.parameters.exports] +waveform = "waveform.raw" + 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+[task.evaluation.pre_layout.jobs.source_positive.parameters.values] +polarity = 1 + +[task.evaluation.pre_layout.jobs.source_positive.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_positive.input_sha256] +deck = "f291cfa28ac8a9c0d85d36712ffbee761dab2793167b829908212de24738b809" +dut = "0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d" + +[task.evaluation.pre_layout.jobs.source_positive.measurements.decision_v] +value = 3.299999 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive.measurements.delay_s] +value = 1.228056e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive.measurements.power_w] +value = 9.475911e-05 +unit = "W" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/ishi-kai/Chipathon2023_ADC/tree/3dce439b2125a9d628e43be40c65cf8fce5d795c/gitefu/comp_20240331/comp_20240331.sch" + +[qualification] +reference = "reference/comp_20240331.gds" + +[presentation] +category = "Mixed-signal" +summary = "Compares two input voltages using a clocked regenerative decision." diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..34844bb9eeb22afdcd3dbe8e765bacc57845872b --- /dev/null +++ b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice @@ -0,0 +1,41 @@ +* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed. +.subckt comp_20240331 VDD CLK VOUTP VOUTN VINP VINN VSS + +*.ipin VDD +*.ipin CLK +*.ipin VINP +*.ipin VINN +*.ipin VSS +*.opin VOUTP +*.opin VOUTN +XM1 net3 CLK VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 net1 VINP net3 VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net1 CLK VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 net4 net1 VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 VOUTP VOUTN net4 VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 net4 net1 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 VOUTP net1 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 VOUTP VOUTN VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 net2 VINN net3 VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 net2 CLK VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 net5 net2 VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 VOUTN VOUTP net5 VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net5 net2 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 VOUTN net2 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM15 VOUTN VOUTP VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/schematic.svg b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..8039b2316fcca6b460707ecf0f580cb6a39abd92 --- /dev/null +++ b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/schematic.svg @@ -0,0 +1 @@ +comparator{"format": "iclayout-schematic", "case_id": "gf180mcuD.Chipathon2023_ADC.comparator", "netlist_sha256": "0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d", "project_sha256": "4bba04aa8a869770c9c5cb56e04c973b4350107cc010ff8c85b9f9e0b138a4b3", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/Chipathon2023_ADC/", "sheets": ["comp_20240331"], "banks": [], "source_netlist": "tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}comp_20240331net1net2net4VDDnet5VSSVOUTPVOUTNnet4net5VOUTPVOUTNnet1net2VSSVINPVINNVSSnet1VDDnet2CLKnet3VDDCLKVOUTPVOUTNVINPVINNVSScomparatorgf180mcuD · Chipathon2023_ADC | W/L in µm · display rounded to 3 significant figures01 Clocked input pairXM42.8/0.28XM52.8/0.28XM22.8/0.28XM32.8/0.28XM12.8/0.28P bulk → VDDN bulk → VSS02 Regenerative output latchXM62.8/0.28XM112.8/0.28XM72.8/0.28XM122.8/0.28XM102.8/0.28XM152.8/0.28P bulk → VDDN bulk → VSS03 Output pull-down pathsXM82.8/0.28XM132.8/0.28XM92.8/0.28XM142.8/0.28N bulk → VSSModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/testbench.spice b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..81b18565fbd8a4dda4ad0f514f07676589742a59 --- /dev/null +++ b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/testbench.spice @@ -0,0 +1,24 @@ +* GF180MCU nominal characterization: 3.3 V, 27 C, typical models. +.include "support/models.spice" +.include "dut.spice" +.include "parameters.spice" +.temp 27 +VPOL pol 0 {polarity} +VDD vdd 0 3.3 +VCLK clk 0 PULSE(0 3.3 10n .1n .1n 10n 20n) +VP inp 0 {1.65+polarity*.01} +VN inn 0 {1.65-polarity*.01} +CP op 0 50f +CN on 0 50f +XDUT vdd clk op on inp inn 0 comp_20240331 +.control +tran .01n 100n +let decision=(v(pol))*(v(op)-v(on)) +meas tran decision_v find decision at=99n +let pwr=-3.3*i(vdd) +meas tran power_w avg pwr from=20n to=100n +meas tran delay_s trig v(clk) val=1.65 rise=1 td=80n targ decision val=2.97 rise=1 td=80n +write waveform.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/problem.md b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..1a42259b38b11a28ca00c9f042c18d06b1342842 --- /dev/null +++ b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/problem.md @@ -0,0 +1,87 @@ +# Dynamic Comparator Layout Task + +## Objective + +Implement `comp_20240331` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Clocked differential decisions for both signs of a 20 mV input difference at 1.65 V common mode, 50 MHz and 50 fF per output. + +## Inputs and Interface + +The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration. + +Ordered subcircuit and GDS interface: `VDD, CLK, VOUTP, VOUTN, VINP, VINN, VSS`. +VDD/VSS: supply/return; CLK: clock; VINP/VINN: differential inputs; VOUTP/VOUTN: directional differential outputs. + +Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together. + +## Operating Conditions + +Use 3.3 V and 27 C. The clock begins rising at 10 ns and repeats every 20 ns, with 0.1 ns rise/fall and 10 ns high time. Each output has 50 fF to ground. Evaluate polarity = -1 and +1 separately: VINP = 1.65 + polarity*0.01 V and VINN = 1.65 - polarity*0.01 V. Simulate to 100 ns with a 0.01 ns requested step. + +Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope. + +## Physical Requirements + +Submit a nonempty GDS with top cell `comp_20240331` and at most 10485760 bytes. Its functional bounding box must not exceed 200 by 100 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is: + +`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`. + +Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block. + +LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `decision` | polarity*(VOUTP-VOUTN) at 99 ns. | V | functional check | 2.97 … +∞ | — | +| `delay` | Final clock rising 1.65 V crossing after 80 ns to the corresponding directional output crossing 2.97 V. | s | minimize / ratio | 0 … +∞ | — | +| `supply` | Average power delivered by VDD over 20–100 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **301.49 um2**. 15 expanded device instances; sum of device/contact envelopes 164.1600 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **6**; it is independent of +the reference-relative task score. + + +### Score weights + +Clocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `delay` | 0.710526315789 | +| `supply` | 0.189473684211 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/reference/comp_20240331.gds b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/reference/comp_20240331.gds new file mode 100644 index 0000000000000000000000000000000000000000..86304f053dbe83402f2985707a969175b2fcb13d Binary files /dev/null and b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/reference/comp_20240331.gds differ diff --git a/tasks/gf180mcuD/Jianxun-OTA/LICENSE b/tasks/gf180mcuD/Jianxun-OTA/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..909f864adb3be87213f211e220bfb48a3399493f --- /dev/null +++ b/tasks/gf180mcuD/Jianxun-OTA/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2025 Jianxun Zhu + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..04f1d0eb11b488efb92494f5b5abb764e342306a --- /dev/null +++ b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml @@ -0,0 +1,777 @@ +in_core = true +kind = "layout_case" +id = "gf180mcuD.Jianxun-OTA.ota_5t" +title = "Five-Transistor OTA with Bias and Dummies" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "e0cb36185bb1c30f23e23a53ed943bc83687c8901f83fc87d6e3b3035a68f388" + +[[assets]] +path = "reference/ota_5t.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "5a8f97494c2bdda14f186f9ea1cb21b65d86b70cd89886684eea3941b4ae23cf" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_ota_5t" +coefficient = 4 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "5853d081d83aa7341666f0d168a814acb189d55936f6ddca0e61a108aeefbae1" + +[task.inputs.netlist] +path = "materials/circuit.spice" +format = "spice" +sha256 = "fe6966f64eb3bc72880adca79dac070e0c0e2ea05cdc46c83f49616611d36fac" +subcircuit = "ota_5t" + +[task.inputs.performance] +path = "materials/testbench.spice" +format = "spice" +sha256 = "457a8a230c6f579fcb9152ea15f9f93bab53310efe2485a8b1e01dc04b69d452" + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "ota_5t" +max_bytes = 10485760 + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" 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+max_width_um = 320 +max_height_um = 80 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "out", + "in_p", + "in_n", + "i_bias", + "vss", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +gain_db = "dB" +unity_hz = "Hz" +bias_v = "V" +power_w = "W" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "gain" +category = "performance" +observations = [ + "nominal:gain_db", +] +unit = "dB" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:gain_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "unity" +category = "performance" +observations = [ + "nominal:unity_hz", +] +unit = "Hz" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:unity_hz", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "output_bias" +category = "performance" +observations = [ + "nominal:bias_v", +] +unit = "V" +direction = "target" +aggregation = "min" +dimension = "bias" +baseline = [ + "source_nominal:bias_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:power_w", +] +unit = "W" +direction = "minimize" +aggregation = "min" +dimension = "supply" +baseline = [ + "source_nominal:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 510.1 +rationale = "Small-signal OTAs: gain 36%; bandwidth 30%; operating points 6%; power 18%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +gain = 0.36 +unity = 0.3 +output_bias = 0.06 +supply = 0.18 + +[task.evaluation.pre_layout] +source_report_sha256 = "4c98033e163329e9de320892a982a51c08d27ecc22de5b9533f16e05cf212086" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +gain_db = "dB" +unity_hz = "Hz" +bias_v = "V" +power_w = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.values] + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "457a8a230c6f579fcb9152ea15f9f93bab53310efe2485a8b1e01dc04b69d452" +dut = "fe6966f64eb3bc72880adca79dac070e0c0e2ea05cdc46c83f49616611d36fac" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.bias_v] +value = 2.526216 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.gain_db] +value = 24.42387 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.power_w] +value = 0.0001074716 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.unity_hz] +value = 26352120.0 +unit = "Hz" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/Jianxun/iic-osic-tools-project-template/tree/178a401d847ce7a602d0ce70a1ba90a15b5f9536/designs/libs/core_analog/ota_5t/ota_5t.spice" + +[qualification] +reference = "reference/ota_5t.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies a differential input with a compact five-transistor OTA core and bias network." diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..06a2dbf12a707a2adcc4707aa0fc409ab07c9ac4 --- /dev/null +++ b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice @@ -0,0 +1,12 @@ +* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed. +.subckt ota_5t vdd out in_p in_n i_bias vss +*.PININFO in_p:I in_n:I i_bias:I vdd:I vss:I out:O +M1 net2 i_bias vss vss nfet_03v3 L=0.28u W=6u nf=2 m=2 +M2 i_bias i_bias vss vss nfet_03v3 L=0.28u W=6u nf=2 m=1 +M3 net1 in_p net2 vss nfet_03v3 L=0.28u W=6u nf=2 m=1 +M4 out in_n net2 vss nfet_03v3 L=0.28u W=6u nf=2 m=1 +M5 out net1 vdd vdd pfet_03v3 L=0.28u W=6u nf=2 m=3 +M6 net1 net1 vdd vdd pfet_03v3 L=0.28u W=6u nf=2 m=3 +M7 vss vss vss vss nfet_03v3 L=0.28u W=6u nf=2 m=3 +M8 vdd vdd vdd vdd pfet_03v3 L=0.28u W=6u nf=2 m=2 +.ends diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/schematic.svg b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..82e9b2236a7473307c9121763e0a8a4314a7cc14 --- /dev/null +++ b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/schematic.svg @@ -0,0 +1 @@ +ota_5t{"format": "iclayout-schematic", "case_id": "gf180mcuD.Jianxun-OTA.ota_5t", "netlist_sha256": "fe6966f64eb3bc72880adca79dac070e0c0e2ea05cdc46c83f49616611d36fac", "project_sha256": "6520554897975d3d626db73b9545776fc2c0df08943ccfa4c83bd9026cb439b2", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/Jianxun-OTA/", "sheets": ["ota_5t"], "banks": [], "source_netlist": "tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}ota_5tvssi_biasvssvddin_pin_ni_biasvssvddoutnet2net1vddoutin_pin_ni_biasvssota_5tgf180mcuD · Jianxun-OTA | W/L in µm · display rounded to 3 significant figures01 Differential pair and active loadM66/0.28 ×3 NF=2M56/0.28 ×3 NF=2M36/0.28 NF=2M46/0.28 NF=2M16/0.28 ×2 NF=2P bulk → vddN bulk → vss02 Bias referenceM26/0.28 NF=2N bulk → vss03 Edge dummiesM76/0.28 ×3 NF=2M86/0.28 ×2 NF=2N bulk → vssP bulk → vddModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/testbench.spice b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..40c197409ed823960aa7038fc9fab497e94bcd15 --- /dev/null +++ b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/testbench.spice @@ -0,0 +1,25 @@ +* GF180MCU nominal characterization: 3.3 V, 27 C, typical models. +.include "support/models.spice" +.include "dut.spice" +.include "parameters.spice" +.temp 27 +VDD vdd 0 3.3 +IBIAS vdd ib 10u +VP inp 0 DC 1.65 AC .5 +VN inn 0 DC 1.65 AC -.5 +CLOAD out 0 1p +XDUT vdd out inp inn ib 0 ota_5t +.control +op +let power_w=-v(vdd)*i(vdd) +print power_w +let bias_v=v(out) +print bias_v +ac dec 40 10 1G +let db_gain=vdb(out) +meas ac gain_db find db_gain at=10 +meas ac unity_hz when db_gain=0 fall=1 +write waveform.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..30400318f14f8d02fe13b6a0a65e34974247a3e3 --- /dev/null +++ b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md @@ -0,0 +1,90 @@ +# Five-Transistor OTA with Bias and Dummies Layout Task + +## Objective + +Implement `ota_5t` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Small-signal differential gain and unity frequency at 1.65 V common mode, 10 uA bias and 1 pF load. + +## Inputs and Interface + +The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration. + +Ordered subcircuit and GDS interface: `vdd, out, in_p, in_n, i_bias, vss`. +vdd/vss: supply/return; out: single-ended output; in_p/in_n: differential inputs; i_bias: current-bias input. + +Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together. + +## Operating Conditions + +Use 3.3 V and 27 C, a 10 uA current from vdd into i_bias, input common mode 1.65 V and 1 pF from out to ground. The differential AC excitation is 1 V (in_p: +0.5 V; in_n: -0.5 V). Measure the DC output and supply power, then sweep 10 Hz to 1 GHz at 40 points/decade. + +Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope. + +## Physical Requirements + +Submit a nonempty GDS with top cell `ota_5t` and at most 10485760 bytes. Its functional bounding box must not exceed 320 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is: + +`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`. + +Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block. + +LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `gain` | 20 log10 of the single-ended differential voltage gain at 10 Hz. | dB | maximize / db20 | −∞ … +∞ | — | +| `unity` | First falling 0 dB gain crossing in the declared AC sweep. | Hz | maximize / ratio | 0 … +∞ | — | +| `output_bias` | DC operating-point voltage at out. | V | target / target | 0 … 3.3 | 3.3 | +| `supply` | DC power delivered by the 3.3 V source, including the bias-current branch. | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **510.1 um2**. 16 expanded device instances; sum of device/contact envelopes 291.8400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **4**; it is independent of +the reference-relative task score. + + +### Score weights + +Small-signal OTAs: gain 36%; bandwidth 30%; operating points 6%; power 18%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `gain` | 0.360000000000 | +| `unity` | 0.300000000000 | +| `output_bias` | 0.060000000000 | +| `supply` | 0.180000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/reference/ota_5t.gds b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/reference/ota_5t.gds new file mode 100644 index 0000000000000000000000000000000000000000..fa18797e2f172aac1c9fc5391e04d8c990a5fbc3 Binary files /dev/null and b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/reference/ota_5t.gds differ diff --git a/tasks/gf180mcuD/README.md b/tasks/gf180mcuD/README.md new file mode 100644 index 0000000000000000000000000000000000000000..56255512d60b5f8be62680c68034c5d33ecdf5bd --- /dev/null +++ b/tasks/gf180mcuD/README.md @@ -0,0 +1,47 @@ +# GF180MCU Process Scope + +Process manifests pin resources; each case contract defines its operating conditions. +For installation, caching and reference execution, use the evaluator +[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). + +The GF180 cases use the explicit operating conditions and frozen scoring anchors +in their task contracts. Core membership is defined by [`benchmark.toml`](../../benchmark.toml), and +[selection rationale](../../README.md#core-selection-rationale) describes the represented circuit capabilities. + +The PDK manifest ([pdk.toml](pdk.toml)) binds `models`, `physical` and +`magic` profiles to one open-pdks installation. `models` uses nominal primitive +ngspice files; `physical` uses the qualified official KLayout rules for variant D, +including geometric/connectivity/off-grid DRC and antenna checks; `magic` uses the +upstream technology built for five metals, 1.1 um top metal and 1 kOhm/square poly. +The prebuilt release and library selection are explicit in the manifest. +The rule files and extraction coefficients come from that release; only the +SPICE reader adapter below modifies an upstream file. DRC runs all rule groups +except chip-level density, including dummy fill and 0.001 um database-unit checks. +The upstream isolated-worker mode keeps antenna connectivity changes separate +from the geometry/connectivity rule groups. +The KLayout reader adapter recognizes the official `nfet_03v3`, +`pfet_03v3` and `ppolyf_u_1k` X wrappers using their actual SI dimensions and MOS +total width. Named top-level pin correspondence is required independently of +KLayout's topology match. + +The Magic profile uses nominal `ngspice()` extraction and a 10-way subdivision +of its 0.05 um internal grid before GDS import. This preserves 5 nm geometry and +port locations during resistance extraction. Candidate-derived MOS/passive +parameters, coupled capacitance and distributed interconnect resistance feed the +same published testbench used for source calibration. Physically distinct +source/body nodes must remain distinct; the model boundary does not include a +distributed silicon substrate network. The standalone-block scope excludes +chip-level density and seal-ring closure, statistical yield and RF/EM analysis. +The isolated-body PTAT uses a physical `nfet_03v3_dn` primitive for native LVS, +with its corresponding four-terminal `nfet_03v3` simulator call. Its independent +witness retains an output-tied isolated P-well, supply-tied deep N-well and an +explicit N-well annulus. The annulus keeps Magic's extresist substrate filling +from joining that body to the outer substrate return. This is a validated +layout route with the existing decks, not a change to PDK extraction rules. +The case additionally qualifies zero-state startup at its declared 100 fF load, +temperatures and supply ramps; larger loads are not covered. + +StrongARM uses its declared 3.3 V CMOS binding and dynamic timing/decision +measurements. Other model families, such as GF180 BJTs, are outside these +published contracts. Use a compatible tool image as specified by the +[evaluator tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). diff --git a/tasks/gf180mcuD/analog-db/LICENSE b/tasks/gf180mcuD/analog-db/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..416a162ee01e3d4542fd0dce757df5d67bf01194 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/LICENSE @@ -0,0 +1,411 @@ +Copyright 2026 Danial Noori Zadeh + +Required Notice: Copyright 2026 Danial Noori Zadeh + +# PolyForm Noncommercial License 1.0.0 + + + +## Acceptance + +In order to get any license under these terms, you must agree +to them as both strict obligations and conditions to all +your licenses. + +## Copyright License + +The licensor grants you a copyright license for the +software to do everything you might do with the software +that would otherwise infringe the licensor's copyright +in it for any permitted purpose. However, you may +only distribute the software according to [Distribution +License](#distribution-license) and make changes or new works +based on the software according to [Changes and New Works +License](#changes-and-new-works-license). + +## Distribution License + +The licensor grants you an additional copyright license +to distribute copies of the software. Your license +to distribute covers distributing the software with +changes and new works permitted by [Changes and New Works +License](#changes-and-new-works-license). + +## Notices + +You must ensure that anyone who gets a copy of any part of +the software from you also gets a copy of these terms or the +URL for them above, as well as copies of any plain-text lines +beginning with `Required Notice:` that the licensor provided +with the software. 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Its circuit.yaml manifests record +Arcadia-1/ferrosim (imported via netlist-crawler), designer Token Zhang, and +license: MIT for the following entries: + +- https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/gs_001_cascode_cs/circuit.yaml +- https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/dp_001_resistive_load/circuit.yaml +- https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_001_hyst_diffpair/circuit.yaml +- https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_002_strongarm/circuit.yaml + +The dp_001 designer field additionally records the mirror-tail adaptation +for open-PDK promotion. + +This attribution follows the direct source's declarations. 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The entry's +provenance metadata separately refers to an MIT source architecture; this +collection does not assume that metadata relicenses the normalized database +material. It is not covered as a whole by the framework's MIT license. + +Layout-Bench changes: expose the reference and error-amplifier tail interfaces; +retain the GF180 MOS dimensions and pass-device multiplicity; replace the ideal +divider by GF180 1 kohm/square poly devices; remove the internal loop-probe source; +use a 0.9 V external reference for a nominal 1.8 V output; independently construct +the physical witness. Testbenches are separately identified as MIT. +Retain LICENSE and these notices with distributions of these materials. + +Batch additions at the same fixed analog-db commit +------------------------------------------------- +amp_004_folded_cascode: first-party SpiceXplorer / CORA-benchmark material, +identified as such by the database NOTICE. The provenance MIT label does not +relicense the normalized material. Layout-Bench exposes vb1/vb2, retains total +W/L and multiplicity and uses single-finger MOS instances with physical bodies. + +gs_001_cascode_cs, dp_001_resistive_load, cmp_001_hyst_diffpair: manifests +attribute the source topology to Token Zhang, Arcadia-1/ferrosim, MIT. +Layout-Bench retains MOS W/L and multiplicity, binds physical poly loads or +feedback/tail resistors where applicable, and authors independent witnesses. +The supplied attribution and standard component terms are retained in LICENSE. + +tsn_003_ptat_4t_xcoupled: source topology attributed to CODA-Team AnalogGym +Sensing Front End, BSD-3-Clause. Copyright (c) 2024, CODA-Team. The supplied +component license is reproduced in LICENSE. Layout-Bench fixes the GF180 +circuit and independently authors a physical witness and temperature contract. + +All five normalized circuit derivatives retain the database PolyForm +Noncommercial terms and Required Notice: Copyright 2026 Danial Noori Zadeh. +New measurement decks are independently authored Layout-Bench code under MIT. +Physical witnesses are distributed with the corresponding circuit terms. +Upstream proprietary-process reference decks, generators, DSL, optimization +traces and scoreboard are not included in these maintained case materials. + +Additional fixed-snapshot cases +------------------------------- +amp_018_telescopic_cascode: the database NOTICE identifies original first-party +SpiceXplorer / CORA-benchmark material. Layout-Bench retains W/L/m and exposes +gate_pc, casc_n and tail to preserve both relative external voltage biases. + +cmfb_003_5t_nmos_input: original normalized analog-db material. Layout-Bench +retains the seven MOS and implements each 5 Mohm sense arm as twenty series +250-kohm physical poly segments, with explicit substrate terminals. + +These derivatives and their independent witnesses retain PolyForm Noncommercial +1.0.0 and Required Notice: Copyright 2026 Danial Noori Zadeh. Independently +authored measurement decks are separately MIT. + +Isolated-body PTAT at the same fixed snapshot +-------------------------------------------- +tsn_002_ptat_classic: source topology attributed to CODA-Team AnalogGym Sensing +Front End, BSD-3-Clause. Copyright (c) 2024, CODA-Team. Applicable component +terms are retained in LICENSE. Layout-Bench preserves the four core MOS W/L/m +and output-connected body, implements the 20 kohm resistor with physical poly, +and adds three MOS for startup. The independently authored witness uses an +isolated P-well, deep N-well and explicit N-well enclosure. The normalized +derivative and witness retain PolyForm Noncommercial 1.0.0 and Required Notice: +Copyright 2026 Danial Noori Zadeh. The independent measurement deck is MIT. + +Self-biased amplifiers, buffered LDO and StrongARM at the fixed snapshot +--------------------------------------------------------------------- +amp_032_ti_ldo_error_selfbias, amp_033_ti_ldo_ref_selfbias and +ldo_005_buffered_ref retain the first-party MacAnalog GF180-native circuit +implementations and their distinct sizing defaults. Layout-Bench quantizes +geometry to 5 nm, raises subminimum 6 V PMOS lengths to 0.55 um, and implements +R/C with native poly/MIM primitives. The LDO exposes the ideal reference as an +external port and replaces its zero-volt loop-probe marker with a wire. + +cmp_002_strongarm is attributed by the fixed manifest to Token Zhang, +Arcadia-1/ferrosim, MIT. The applicable component terms in LICENSE also apply to +this topology. Layout-Bench selects the fixed GF180 binding, expands MOS +multiplicity and independently constructs the physical witness and test fixture. + +All four normalized derivatives and witnesses retain PolyForm Noncommercial +1.0.0 and Required Notice: Copyright 2026 Danial Noori Zadeh. Independently +authored measurement decks are separately identified as MIT. Retain this NOTICE +and LICENSE with source and static material distributions. + +Faithful compensated amplifier additions +---------------------------------------- +amp_017_tan_clia retains its own process binding, sizing defaults, +explicit multiplicity ratios and full compensation network from MacAnalog +spicexplorer-release commit 263d0322f8900dc331536fbbe6c0e804514fc454. +The upstream manifests identify CODA-Team AnalogGym, BSD-3-Clause; retain +Copyright (c) 2024, CODA-Team and its component terms in LICENSE, alongside +PolyForm Noncommercial 1.0.0 and Required Notice: Copyright 2026 Danial Noori Zadeh. +Adaptations externalize the independent bias current, quantize geometry to the +process grid, add physical contacts and implement all R/C with native primitives. +The independent reference layouts preserve the core topology and device ratios. +Independently authored measurement decks are separately MIT. + +Externally biased amplifier, standalone CMFB, simple LDO and transmission gate +---------------------------------------------------------------------------- +amp_019_ti_ldo_error retains the fixed MacAnalog GF180 binding of the original +first-party TI-architecture error amplifier. The fixed database NOTICE and its +reference README identify the authored source and rights; the TI architecture +reference does not license TI figures or certify a particular TI product. No TI +figure is redistributed. The historical schematic's placeholder geometry is not +the maintained sizing. All twelve MOS, na-to-nd RND and series Rz/Cc are retained. + +ldo_003_analoggym_simple pairs the ChrisZonghaoLi/sky130_ldo_rl netlist +(Apache-2.0) with CODA-Team/AnalogGym variable/testbench provenance +(BSD-3-Clause; Copyright (c) 2024, CODA-Team). The fixed MacAnalog corpus +PROVENANCE.md and both actual component license texts are retained in Designs. +The applicable component terms are already reproduced in this LICENSE. +Layout-Bench externalizes VB/VREF and replaces only the zero-volt loop marker +with a wire. It retains the 360-fold pass device, compensation and physical bleed. + +Both GF180 circuits apply native minimum lengths, quantize dimensions, map +passives to native poly/MIM, and use independently authored witnesses and fixtures. +The normalized derivatives retain PolyForm Noncommercial 1.0.0 and +Required Notice: Copyright 2026 Danial Noori Zadeh. New measurement decks are MIT. + +Passive detector, two-NMOS temperature core and source-follower stub +----------------------------------------------------------------- +sup_001_vcm_detector, tsn_001_ptat_2t and ldo_006_stub retain independent +snapshots of MacAnalog/spicexplorer-release commit +263d0322f8900dc331536fbbe6c0e804514fc454. SUP001 is Noorizadeh's authored +resistive leaf after Hsu et al.; only its ideal two-resistor binding is used, +implemented in native GF180 poly resistors with an explicit substrate port. +TSN001 identifies CODA-Team AnalogGym BSD-3-Clause provenance, Copyright (c) +2024, CODA-Team; it uses the fixed GF180 two-group NMOS binding. LDO006 is +a first-party SpiceXplorer divider/source-follower stub, not a full LDO. +Native contacts, routing and series resistor realizations are independently +authored. Core connectivity, total MOS dimensions and explicit multiplicities +remain. Database derivatives and witnesses retain PolyForm Noncommercial 1.0.0 +and Required Notice: Copyright 2026 Danial Noori Zadeh, with applicable +component terms in LICENSE. New observation decks and diagnostics are MIT. + + +Direct-source notice and manifest scope +======================================= + +The upstream analog-db NOTICE is reproduced verbatim below from: +https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/NOTICE +The upstream LICENSE is retained verbatim within this collection's LICENSE: +https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/LICENSE + +In the notice below, circuits/ferrosim_* refers to reference-only pointer entries. +The concrete entries listed in the ferrosim attribution section of our LICENSE +have their own circuit.yaml manifests at the same commit. Those manifests describe +promoted device-generic circuits and open-PDK bindings and retain the ferrosim +source attribution and MIT label. Bench uses those analog-db circuit materials; +this does not import the proprietary-process reference decks mentioned by the +manifests. The text below describes upstream's repository, not Bench's file tree. +Our case-specific adaptations are recorded above and in each case's task materials. + +----- BEGIN UPSTREAM analog-db/NOTICE ----- +spicexplorer-analog-db +====================== + +This repository contains the SpiceXplorer analog circuit database (the canonical +topology/circuit registry + the tiered `verify` harness) and is part of the SpiceXplorer +platform. The harness code (`src/`) and the original circuit definitions are licensed under +the PolyForm Noncommercial License 1.0.0 (see LICENSE), Copyright 2026 Danial Noori Zadeh. + +Provenance of derived circuit artifacts +--------------------------------------- +Some circuits are normalized from upstream open-source corpora. Their abstract netlists, +sizing, datasheets and schematic provenance are derived works; the upstream licenses apply to +the upstream material and are acknowledged here: + +* circuits/amp_001_5t (formerly circuits/5t_ota) — derived from IIC-JKU / Harald Pretl + `analog-circuit-design` (https://github.com/iic-jku/analog-circuit-design), Apache License 2.0. + The datasheet is modeled on that project's CACE `voltage-buffer-ota.yaml`; the canonical + schematic.svg and the xschem provenance are from that project. + +* The **verifiable AnalogGym amplifier imports** — the 16 `amp_*` circuits whose `circuit.yaml` + records `provenance.source: AnalogGym` (currently amp_002, amp_003, amp_005–amp_017 and amp_021) + — normalized from CODA-Team `AnalogGym` (https://github.com/CODA-Team/AnalogGym), BSD 3-Clause + License. These 3-stage amplifiers are lowered to open PDKs and simulated by this DB. This is + **not** a contiguous id range — amp_004 is a CORA design and amp_018/amp_019 are original / + template designs (see below). Reference snapshots of two un-imported AnalogGym amplifiers are + kept at `_shared/references/analoggym/`. + +* circuits/ldo_001_analoggym_basic, ldo_002_analoggym_folded_cascode, ldo_003_analoggym_simple — + the **verifiable AnalogGym LDO imports**. ldo_001 normalizes AnalogGym's `Basic_LDO` + (BSD 3-Clause); ldo_002 and ldo_003 pair AnalogGym testbenches + design-variable lists + (BSD 3-Clause) with subcircuit netlists from `ChrisZonghaoLi/sky130_ldo_rl` + (https://github.com/ChrisZonghaoLi/sky130_ldo_rl, Apache License 2.0). The full upstream→DB file + mapping and both license texts are in corpora/analoggym-ldo/PROVENANCE.md. + +* circuits/amp_004_folded_cascode (provenance.source: CORA), amp_018_telescopic_cascode, + amp_019_ti_ldo_error, and ldo_004_basic_pmos / ldo_005_buffered_ref + / ldo_006_stub / ldo_007_pmos — original first-party SpiceXplorer / CORA-benchmark designs + (ldo_004/ldo_005 + amp_019 are + first-party MacAnalog material modeled on a TI application-note LDO architecture, GF180-native, + kept verbatim under each circuit's reference/). The NEWCAS 2026 research traces under + circuits/amp_018_telescopic_cascode/artifacts/newcas2026/ are preserved verbatim. + +* circuits/ferrosim_* (kind: reference, plan D-9) — POINTER entries for reference circuits from + `Arcadia-1/ferrosim` (https://github.com/Arcadia-1/ferrosim), authored by Token Zhang, under the + MIT License (some noted upstream as "ported from circuit-bench"). Each entry records upstream + repository, designer, license, and classification ONLY — the upstream netlists and testbenches + are NOT redistributed here, NOT lowered to an open PDK, and NOT simulated by this database. + See corpora/ferrosim/README.md for the corpus-level pointer. + +* circuits/sfe_* (kind: reference, plan D-9) — POINTER entries for the "Sensing Front End" + category of CODA-Team `AnalogGym` (https://github.com/CODA-Team/AnalogGym), BSD 3-Clause + License. Each entry records upstream provenance and classification ONLY — the upstream decks + and testbenches are NOT redistributed here, NOT lowered to an open PDK, and NOT simulated by + this database. The upstream→DB mapping is in corpora/analoggym-sensing-fe/PROVENANCE.md. + +PDK corner libraries are NOT vendored here (plan D-6): circuits reference them by +`lib_file` + `section`; the database clones and runs its PDK-free tiers without any PDK. +----- END UPSTREAM analog-db/NOTICE ----- + + +Attribution scope +----------------- +Upstream MIT, BSD or Apache attribution does not remove the retained PolyForm +terms from distributed analog-db derivatives and corresponding reference layouts. +Independently authored measurement decks use the root MIT license where identified +above. For ferrosim-derived entries, the direct source is the pinned analog-db +release: its circuit manifests supply attribution and the MIT label retained in +LICENSE. These records do not add a substitute ferrosim license or claim an +independent license grant from the indirect source. Technical qualification does +not independently verify copyright ownership or permission. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..73b8ce486cc4b3ca52b4c757d0c32cdaecfa7f1a --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml @@ -0,0 +1,1062 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.amp_004_folded_cascode" +title = "Externally Biased PMOS-Input Folded-Cascode OTA" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "4c8a4e0bdc34c98915c33b3579bd6b031dfecfe4661dbdc2259e1f7c909e61d3" + +[[assets]] +path = "reference/amp_004_folded_cascode.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = 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+max_height_um = 340 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vinn", + "vinp", + "vout", + "vdd", + "ibias", + "vss", + "vb1", + "vb2", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "bias_v" +category = "performance" +observations = [ + "condition_0:bias_v", + "condition_1:bias_v", + "condition_2:bias_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:bias_v", + "source_condition_1:bias_v", + "source_condition_2:bias_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "gain_db" +category = "performance" +observations = [ + "condition_0:gain_db", + "condition_1:gain_db", + "condition_2:gain_db", +] +unit = "dB" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:gain_db", + "source_condition_1:gain_db", + "source_condition_2:gain_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "bandwidth_hz" +category = "performance" +observations = [ + "condition_0:bandwidth_hz", + "condition_1:bandwidth_hz", + "condition_2:bandwidth_hz", +] +unit = "Hz" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:bandwidth_hz", + "source_condition_1:bandwidth_hz", + "source_condition_2:bandwidth_hz", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "unity_hz" +category = "performance" +observations = [ + "condition_0:unity_hz", + "condition_1:unity_hz", + "condition_2:unity_hz", +] +unit = "Hz" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:unity_hz", + "source_condition_1:unity_hz", + "source_condition_2:unity_hz", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "phase_margin" +category = "performance" +observations = [ + "condition_0:phase_margin", + "condition_1:phase_margin", + "condition_2:phase_margin", +] +unit = "deg" +dimension = "response" +direction = "target" +aggregation = "min" +baseline = [ + "source_condition_0:phase_margin", + "source_condition_1:phase_margin", + "source_condition_2:phase_margin", +] +normalization = "target" +scale = 180 +lower = 0 +upper = 180 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 5150.02 +rationale = "Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +gain_db = 0.27 +bandwidth_hz = 0.1125 +unity_hz = 0.1125 +phase_margin = 0.225 +bias_v = 0.0225 +output_v = 0.0225 +power_w = 0.135 + +[task.evaluation.pre_layout] +source_report_sha256 = "d9a250a782d31c5ac00a24b35ea05e2950ea7fe5c1a456a144f1eb3ffeb2d508" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 2.7 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "1e583451d0ffe7a59cba3f92af6fe77f8eb2caa90ea72f62a4e81ce20ce1cea9" +dut = "0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bandwidth_hz] +value = 55221.54 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] +value = 1.849119484415 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] +value = 45.95764 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.592655342455 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin] +value = 88.43546 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001925478244366 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] +value = 11028510.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "1e583451d0ffe7a59cba3f92af6fe77f8eb2caa90ea72f62a4e81ce20ce1cea9" +dut = "0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bandwidth_hz] +value = 1954.145 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] +value = 2.149119484415 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 83.3776 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 1.6500370596 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin] +value = 64.479 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0002428722902554 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] +value = 26500280.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "1e583451d0ffe7a59cba3f92af6fe77f8eb2caa90ea72f62a4e81ce20ce1cea9" +dut = "0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bandwidth_hz] +value = 1516.815 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] +value = 2.449119484415 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_db] +value = 85.67452 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 1.650052756276 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_margin] +value = 64.9432 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.0002680622941304 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.unity_hz] +value = 26921560.0 +unit = "Hz" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_004_folded_cascode" + +[qualification] +reference = "reference/amp_004_folded_cascode.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies differential inputs with an externally biased PMOS folded-cascode stage across three supply voltages." diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..fe99d05a28c4c0c20e4e89dee6aa82bac3e73026 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice @@ -0,0 +1,19 @@ +* Derived from analog-db amp_004_folded_cascode, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: external vb1/vb2 ports; single-finger MOS with retained total W/L and m. +.subckt amp_004_folded_cascode vinn vinp vout vdd ibias vss vb1 vb2 +XM0 tail ibias vdd vdd pfet_03v3 w=60u l=1u m=2 +XM1 foldp vinp tail vdd pfet_03v3 w=96u l=0.5u m=1 +XM10 s10 cascp vdd vdd pfet_03v3 w=82u l=1u m=1 +XM11 ibias ibias vdd vdd pfet_03v3 w=60u l=1u m=2 +XM12 nbias ibias vdd vdd pfet_03v3 w=60u l=1u m=2 +XM13 nbias nbias vss vss nfet_03v3 w=60u l=1u m=1 +XM2 foldn vinn tail vdd pfet_03v3 w=96u l=0.5u m=1 +XM3 foldp nbias vss vss nfet_03v3 w=60u l=1u m=1 +XM4 foldn nbias vss vss nfet_03v3 w=60u l=1u m=1 +XM5 cascp vb1 foldp vss nfet_03v3 w=30u l=0.5u m=1 +XM6 vout vb1 foldn vss nfet_03v3 w=30u l=0.5u m=1 +XM7 cascp vb2 s9 vdd pfet_03v3 w=88u l=0.5u m=1 +XM8 vout vb2 s10 vdd pfet_03v3 w=88u l=0.5u m=1 +XM9 s9 cascp vdd vdd pfet_03v3 w=82u l=1u m=1 +.ends amp_004_folded_cascode diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..59e33765b1a2b22a38962c33a478b4bb09f36504 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/schematic.svg @@ -0,0 +1 @@ +amp_004_folded_cascode{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.amp_004_folded_cascode", "netlist_sha256": "0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df", "project_sha256": "80f83527f79b9334bf13c05f1d864f44b44a0ff48fcbd34b3d86df8a923dbb7f", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["amp_004_folded_cascode"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}amp_004_folded_cascodefoldpfoldns9vdds10vb2voutvb1cascpvssvddibiasnbiasibiasvddvinpvinnfoldpfoldnnbiasvsstailvinnvinpvoutvddibiasvssvb1vb2amp_004_folded_cascodegf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 PMOS input pairXM060/1 ×2XM196/0.5XM296/0.5XM360/1XM460/1P bulk → vddN bulk → vss02 Folded cascode output branchesXM982/1XM1082/1XM788/0.5XM888/0.5XM530/0.5XM630/0.5P bulk → vddN bulk → vss03 Bias generationXM1160/1 ×2XM1260/1 ×2XM1360/1P bulk → vddN bulk → vssModels: pfet_03v3 · nfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..a6ec180f01103a4eb7eb133a85e8633eb6655a94 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/testbench.spice @@ -0,0 +1,40 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 DC {supply_v} +IB ibias 0 20u +* External bias fixture: DC output feedback, AC-isolated input injection. +LFB vout vinn 1T +VCM vinp 0 DC 1.65 AC 0.5 +VB1 vb1 0 1.2 +VB2 vb2 0 1.95 +VIN acin 0 DC 0 AC 0.5 180 +CIN acin vinn 1 +CL vout 0 1p +XDUT vinn vinp vout vdd ibias 0 vb1 vb2 amp_004_folded_cascode +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let bias_v=v(ibias) +let power_w=-v(vdd)*i(vdd) +print output_v bias_v power_w +write op.raw v(vdd) v(vout) v(vinn) v(ibias) i(vdd) +ac dec 100 1 1G +let transfer=v(vout)/(v(vinp)-v(vinn)) +let response_db=db(transfer) +meas ac gain_db find response_db at=10 +let drop_db=db(transfer)-gain_db +meas ac bandwidth_hz when drop_db=-3 fall=1 +let phase_deg=180*cph(transfer)/pi +meas ac unity_hz when response_db=0 fall=1 +meas ac phase_unity find phase_deg when response_db=0 fall=1 +let phase_margin=180+phase_unity +print phase_margin +write ac.raw frequency v(vout) v(vinn) v(vinp) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/problem.md b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..1315300b290adb196de6e113044167431414ad7c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/problem.md @@ -0,0 +1,126 @@ +# Externally Biased PMOS-Input Folded-Cascode OTA Layout Task + +## Objective + +Implement the fixed `amp_004_folded_cascode` circuit in GF180MCU D and submit self-contained GDS. +Fourteen MOS entries (17 instances after multiplicity expansion) form a PMOS-input folded-cascode OTA with a bias mirror and cascode branches. The two ideal internal voltage sources become explicit vb1/vb2 ports. Total MOS widths, lengths and multiplicities are retained; the maintained devices use single-finger geometry instead of the upstream nf settings. Source and extracted simulation both represent this maintained implementation. + +## Inputs and Interface + +`materials/circuit.spice` is authoritative for LVS and source calibration; +`materials/testbench.spice` defines every electrical measurement. This problem +is the description input. Ordered ports: `vinn vinp vout vdd ibias vss vb1 vb2`. +In order, these are: Negative input, positive input, output, supply, PMOS reference-current sink, return, NMOS cascode bias, and PMOS cascode bias. + +Preserve the netlist's device connectivity, dimensions, multiplicities and body +connections. Provide physical well/substrate contacts to the declared rails. +Placement, routing, splitting and source/drain interchange are permitted only +where accepted by the declared LVS equivalence rules. No common-centroid or +statistical matching requirement is scored. Ideal external stimulus, bias and +load devices remain testbench apparatus and must not be placed inside the DUT. + +## Operating Conditions + +Use the typical GF180 3.3 V MOS models and physical poly models where present, +with statistical variation disabled. Unless swept explicitly, temperature is 27 C. +VSS = 0 V; VDD = 2.7, 3.0 and 3.3 V; a 20 uA sink from ibias to VSS; VB1 = 1.2 V and VB2 = 1.95 V; external 1 pF output load. VINP has DC 1.65 V and AC +0.5 V. A 1 TH output-to-VINN inductor closes DC feedback; a 1 F coupling capacitor injects AC -0.5 V at VINN. The open-loop transfer is V(vout)/(V(vinp)-V(vinn)). These large L/C elements are external measurement apparatus. At 2.7 V the reduced headroom lowers gain and shifts the DC operating point. + +AC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is +V(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp) +for unit differential excitation; the OTA transfer is defined above. + +## Physical Requirements + +Submit top cell `amp_004_folded_cascode` with every named electrical port, resolved hierarchy +and a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna, +strict named-port LVS and geometry must pass, without DRC waivers. Chip-level +density and seal-ring closure are outside this standalone-block scope. + +The functional bounding box must fit within 400 by 340 um. Area includes all +process device and routing drawing layers listed in runtime constraints: +wells, implants, active, poly, contacts, metals/vias and passive/device markers. +Annotation and pin-purpose shapes are excluded; all functional routing must use +drawing layers. The complete layer list is frozen in `/protocol/task.json`. + +The judge independently extracts distributed wiring resistance and capacitance +from the submitted GDS, retaining candidate-derived MOS/passive geometry and +external body connections. Every scored simulation consumes that extracted DUT. +This model boundary does not include a distributed silicon substrate network. +The case measures small-signal unity-crossing phase margin with the declared load. Startup, large-signal settling, other loads, mismatch, noise, PVT and EM are outside scope. Manufacturing signoff is not claimed. + +## Electrical Requirements and Scoring + +All three operating conditions must complete and every observation must be finite +and meet its inclusive band. Aggregation cannot hide a failing condition; +missing crossings or incomplete extraction/simulation cannot establish success. +Saved waveforms provide the inputs for independently reconstructing observations. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 | +| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 | +| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — | +| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — | +| `unity_hz` | First falling 0 dB crossing of open-loop transfer | Hz | maximize / ratio | 0 … +∞ | — | +| `phase_margin` | 180 degrees plus unwrapped transfer phase at the unity crossing | deg | target / target | 0 … 180 | 180 | + +Area reference: **5150.02 um2**. 17 expanded device instances; sum of device/contact envelopes 3278.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **5**; it is independent of +the reference-relative task score. + + +### Score weights + +Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `gain_db` | 0.270000000000 | +| `bandwidth_hz` | 0.112500000000 | +| `unity_hz` | 0.112500000000 | +| `phase_margin` | 0.225000000000 | +| `bias_v` | 0.022500000000 | +| `output_v` | 0.022500000000 | +| `power_w` | 0.135000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 resources listed in `/protocol/resources.json`. +KLayout checks the layout, Magic extracts RC and ngspice simulates the circuit. +`/protocol/task.json` provides frozen constraints and evaluation requirements; +`/protocol/harness.json` describes the harness. If `process-feedback` is +exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/reference/amp_004_folded_cascode.gds b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/reference/amp_004_folded_cascode.gds new file mode 100644 index 0000000000000000000000000000000000000000..38c0d3cfed00ea89832ee4b564bf7c0adef1b85a --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/reference/amp_004_folded_cascode.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3082df564abe04d514b98c8bd799eec3d1bda5091153bff9873cc67fd696c5e2 +size 437420 diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..fe59361071f23808def07dc0112461b317eea4e0 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml @@ -0,0 +1,1101 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.amp_017_tan_clia" +title = "Tan CLIA Three-Stage Amplifier" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "a951dfbb8729aac6058013c7428b2f44baa758700b970a4fc661356f61a428ae" + +[[assets]] +path = "reference/amp_017_tan_clia.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "e259ca768f777240880af2ab5cb2222971638349b504800f32d53f69bff1a302" + +[task] +hours = 8 +kind = "netlist_to_gds" +family = "multistage_compensated_ota" +coefficient = 7 +environment = "gf180mcuD-mos-rc-tt" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "913320192baa29ccab642c3689f1b96b720e8049bdad4a76c9cc7243c0ea1c89" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +format = "spice" +sha256 = "59a4d962ade70da8bbdc21dffc81adf077c84baa2057b100deaed0c5f34e7dc2" +subcircuit = "amp_017_tan_clia" + +[task.inputs.simulation] +path = "materials/circuit.spice" +format = "spice" +sha256 = "2432efcec874fc55326016d1151de89251a450a6f5b654aff6b18cd47feca69d" + +[task.inputs.performance] +path = "materials/testbench.spice" +format = "spice" +sha256 = "6e9ff310acb6dc07da0557c4d3354e723584a4cbfe8ea56858c0d77706d3b25f" + +[task.inputs.frequency] +path = "materials/ac.spice" +format = "spice" +sha256 = "34e2a72ec59709b055bd2741b77fcbc1b7a25a6094224bc02c85f833c468371d" + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "amp_017_tan_clia" +max_bytes = 67108864 + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 5, + 0, + ], + [ + 11, + 17, + ], + [ + 11, + 39, + ], + [ + 12, + 0, + ], + [ + 13, + 17, + ], + [ + 21, + 0, + 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"layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vss", + "vdd", + "vinn", + "vinp", + "vout", + "net1", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 1e-11 +step_v = 0.1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +closed_gain_10khz_db = "dB" +late_error_v = "V" +return_error_v = "V" +ripple_v = "V" +return_ripple_v = "V" +mean_power_w = "W" +bias_v = "V" +high_v = "V" +low_v = "V" +output_min_v = "V" +output_max_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:frequency" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 1e-11 + +[task.evaluation.jobs.parameters.measurements] +gain_db = "dB" +gain_10khz_db = "dB" +fixture_cm_max = "V" +dc_feedback_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +dimension = "bias" +normalization = "target" +direction = "target" +aggregation = "max" +scale = 1.8 +category = "performance" +observations = [ + "condition_0:output_v", +] +baseline = [ + "source_condition_0:output_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +normalization = "ratio" +direction = "minimize" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", +] +baseline = [ + "source_condition_0:power_w", +] + +[[task.evaluation.metrics]] +id = "gain_db" +unit = "dB" +dimension = "response" +normalization = "db20" +direction = "maximize" +aggregation = "min" +category = "performance" +observations = [ + "condition_1:gain_db", +] +baseline = [ + "source_condition_1:gain_db", +] + +[[task.evaluation.metrics]] +id = "gain_10khz_db" +unit = "dB" +dimension = "response" +normalization = "db20" +direction = "maximize" +aggregation = "min" +category = "performance" +observations = [ + "condition_1:gain_10khz_db", +] +baseline = [ + "source_condition_1:gain_10khz_db", +] + +[[task.evaluation.metrics]] +id = "closed_gain_10khz_db" +unit = "dB" +dimension = "response" +normalization = "target" +direction = "target" +aggregation = "max" +scale = 6 +category = "performance" +observations = [ + "condition_0:closed_gain_10khz_db", +] +baseline = [ + "source_condition_0:closed_gain_10khz_db", +] + +[[task.evaluation.metrics]] +id = "late_error_v" +unit = "V" +dimension = "response" +normalization = "ratio" +direction = "minimize" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:late_error_v", +] +baseline = [ + "source_condition_0:late_error_v", +] + +[[task.evaluation.metrics]] +id = "return_error_v" +unit = "V" +dimension = "response" +normalization = "ratio" +direction = "minimize" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:return_error_v", +] +baseline = [ + "source_condition_0:return_error_v", +] + +[[task.evaluation.metrics]] +id = "ripple_v" +unit = "V" +dimension = "response" +normalization = "ratio" +direction = "minimize" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:ripple_v", +] +baseline = [ + "source_condition_0:ripple_v", +] + +[[task.evaluation.metrics]] +id = "return_ripple_v" +unit = "V" +dimension = "response" +normalization = "ratio" +direction = "minimize" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:return_ripple_v", +] +baseline = [ + "source_condition_0:return_ripple_v", +] + +[[task.evaluation.metrics]] +id = "mean_power_w" +unit = "W" +dimension = "supply" +normalization = "ratio" +direction = "minimize" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:mean_power_w", +] +baseline = [ + "source_condition_0:mean_power_w", +] + +[[task.evaluation.metrics]] +id = "bias_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:bias_v", +] + +[[task.evaluation.metrics]] +id = "high_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:high_v", +] + +[[task.evaluation.metrics]] +id = "low_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:low_v", +] + +[[task.evaluation.metrics]] +id = "output_min_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:output_min_v", +] + +[[task.evaluation.metrics]] +id = "output_max_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:output_max_v", +] + +[[task.evaluation.metrics]] +id = "fixture_cm_max" +unit = "V" +direction = "minimize" +aggregation = "max" +lower = 0 +upper = 1e-06 +category = "performance" +observations = [ + "condition_1:fixture_cm_max", +] + +[[task.evaluation.metrics]] +id = "dc_feedback_error_v" +unit = "V" +direction = "minimize" +aggregation = "max" +lower = 0 +upper = 1e-06 +category = "performance" +observations = [ + "condition_1:dc_feedback_error_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 88555.19 +rationale = "Finite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +late_error_v = 0.18 +return_error_v = 0.18 +return_ripple_v = 0.1125 +ripple_v = 0.1125 +closed_gain_10khz_db = 0.06 +gain_10khz_db = 0.06 +gain_db = 0.06 +output_v = 0.045 +mean_power_w = 0.045 +power_w = 0.045 + +[task.evaluation.pre_layout] +source_report_sha256 = "68fb00d670218de19e948587492d2c7bfe8fae9e5fa49c7195a59e5b470f2e21" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +load_f = 1e-11 +step_v = 0.1 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +closed_gain_10khz_db = "dB" +late_error_v = "V" +return_error_v = "V" +ripple_v = "V" +return_ripple_v = "V" +mean_power_w = "W" +bias_v = "V" +high_v = "V" +low_v = "V" +output_min_v = "V" +output_max_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "6e9ff310acb6dc07da0557c4d3354e723584a4cbfe8ea56858c0d77706d3b25f" +dut = "2432efcec874fc55326016d1151de89251a450a6f5b654aff6b18cd47feca69d" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] +value = 0.8723333817708518 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] +value = -0.00120918 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] +value = 0.3999944 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] +value = 5.625202e-06 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] +value = 0.3000086 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] +value = 0.0001799124 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] +value = 0.433605 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] +value = 0.28487 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.3000085580684345 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001664939552239932 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] +value = 8.558068e-06 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] +value = 4.42979e-13 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] +value = 5.50282e-13 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:frequency" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +gain_db = "dB" +gain_10khz_db = "dB" +fixture_cm_max = "V" +dc_feedback_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "34e2a72ec59709b055bd2741b77fcbc1b7a25a6094224bc02c85f833c468371d" +dut = "2432efcec874fc55326016d1151de89251a450a6f5b654aff6b18cd47feca69d" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] +value = 7.415006396257425e-11 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] +value = 54.70374 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 75.43526 +unit = "dB" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_017_tan_clia" + +[qualification] +reference = "reference/amp_017_tan_clia.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies differential signals through three stages with current inversion and physical R/C compensation." diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/ac.spice b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/ac.spice new file mode 100644 index 0000000000000000000000000000000000000000..97a89ac70949717d45fc3022569a3b658b0a1219 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/ac.spice @@ -0,0 +1,42 @@ +* Same-condition finite-window amplifier observations. SPDX-License-Identifier: MIT +.include support/models.spice +.include parameters.spice +.include dut.spice +.temp 27 +.save v(vdd) v(vout) v(vp) v(vm) v(net1) i(VDD) +.option klu reltol=1e-5 abstol=1e-12 vntol=1e-8 method=gear maxord=2 itl4=1000 +VDD vdd 0 1.8 +VIN vp 0 dc 0.3 ac 0.5 +IBIAS net1 0 2.32803e-06 +LFB vout basem 1T +CFB basem 0 1 +VNEG vm basem dc 0 ac 0.5 180 +XDUT 0 vdd vm vp vout net1 amp_017_tan_clia +CLOAD vout 0 {load_f} +.control +set noaskquit +set num_threads=1 +set numdgt=15 +op +let dc_feedback_error_v=abs(v(vout)-v(vm)) +print dc_feedback_error_v +if dc_feedback_error_v > 1e-6 + echo Error: invalid DC feedback operating point + quit 1 +end +write op.raw all +ac dec 200 1 1g +let transfer=v(vout)/(v(vp)-v(vm)) +let gain_db_vec=db(transfer) +let fixture_cm_max=vecmax(mag((v(vp)+v(vm))/2)) +meas ac gain_db find gain_db_vec at=1 +meas ac gain_10khz_db find gain_db_vec at=10k +print fixture_cm_max +if fixture_cm_max > 1e-6 + echo Error: invalid differential AC excitation + quit 1 +end +write ac.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..05be23be61fceef19e772774aaabed920cd7d8a8 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl @@ -0,0 +1,537 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt amp_017_tan_clia vss vdd vinn vinp vout net1 +C0_0 net2 vss cap_mim_2f0fF w=10u l=30.635u +C1_0 net8 vout cap_mim_2f0fF w=20u l=13.49u +C1_1 net8 vout cap_mim_2f0fF w=20u l=13.49u +R0_0 net5 R0_seg1 vss ppolyf_u_1k w=1u l=49.4u +R0_1 R0_seg1 R0_seg2 vss ppolyf_u_1k w=1u l=49.4u +R0_2 R0_seg2 R0_seg3 vss ppolyf_u_1k w=1u l=49.4u +R0_3 R0_seg3 R0_seg4 vss ppolyf_u_1k w=1u l=49.4u +R0_4 R0_seg4 R0_seg5 vss ppolyf_u_1k w=1u l=49.4u +R0_5 R0_seg5 R0_seg6 vss ppolyf_u_1k w=1u l=49.4u +R0_6 R0_seg6 R0_seg7 vss ppolyf_u_1k w=1u l=49.4u +R0_7 R0_seg7 R0_seg8 vss ppolyf_u_1k w=1u l=49.4u +R0_8 R0_seg8 R0_seg9 vss ppolyf_u_1k w=1u l=49.4u +R0_9 R0_seg9 R0_seg10 vss ppolyf_u_1k w=1u l=49.4u +R0_10 R0_seg10 R0_seg11 vss ppolyf_u_1k w=1u l=49.4u +R0_11 R0_seg11 R0_seg12 vss ppolyf_u_1k w=1u l=49.4u +R0_12 R0_seg12 R0_seg13 vss ppolyf_u_1k w=1u l=49.4u +R0_13 R0_seg13 R0_seg14 vss ppolyf_u_1k w=1u l=49.4u +R0_14 R0_seg14 R0_seg15 vss ppolyf_u_1k w=1u l=49.4u +R0_15 R0_seg15 R0_seg16 vss ppolyf_u_1k w=1u l=49.4u +R0_16 R0_seg16 R0_seg17 vss ppolyf_u_1k w=1u l=49.4u +R0_17 R0_seg17 net2 vss ppolyf_u_1k w=1u l=49.4u +Mm0_0 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_1 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_2 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_3 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_4 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_5 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_6 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_7 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_8 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_9 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_10 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_11 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_12 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_13 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_14 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_15 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_16 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_17 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_18 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_19 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_20 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_21 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_22 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_23 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_24 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_25 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_26 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_27 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_28 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_29 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_30 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_31 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_32 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_33 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_34 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_35 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_36 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_37 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_38 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm0_39 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_0 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_1 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_2 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_3 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_4 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_5 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_6 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_7 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_8 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_9 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_10 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_11 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_12 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_13 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_14 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_15 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_16 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_17 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_18 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_19 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_20 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_21 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_22 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_23 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_24 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_25 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_26 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_27 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_28 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_29 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_30 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_31 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_32 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_33 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_34 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_35 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_36 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_37 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_38 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm1_39 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm12_0 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Mm12_1 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Mm12_2 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Mm12_3 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Mm13_0 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Mm13_1 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Mm13_2 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Mm13_3 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Mm14_0 vb3 vb3 vss vss nfet_03v3 w=15u l=3.695u +Mm15_0 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_1 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_2 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_3 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_4 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_5 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_6 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm15_7 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Mm16_0 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_1 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_2 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_3 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_4 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_5 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_6 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm16_7 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Mm17_0 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm17_1 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm17_2 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm17_3 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm18_0 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm18_1 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm18_2 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm18_3 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_0 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_1 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_2 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_3 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_4 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_5 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_6 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_7 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_8 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_9 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_10 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm19_11 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm2_0 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_1 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_2 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_3 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_4 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_5 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_6 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_7 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_8 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_9 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_10 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_11 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_12 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_13 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_14 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_15 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_16 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_17 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_18 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_19 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_20 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_21 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_22 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_23 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_24 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_25 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_26 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_27 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_28 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_29 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_30 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_31 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_32 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_33 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_34 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_35 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_36 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_37 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_38 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm2_39 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm20_0 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_1 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_2 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_3 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_4 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_5 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_6 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_7 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_8 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_9 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_10 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm20_11 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm3_0 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_1 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_2 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_3 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_4 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_5 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_6 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_7 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_8 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_9 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_10 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_11 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_12 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_13 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_14 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_15 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_16 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_17 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_18 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_19 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_20 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_21 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_22 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_23 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_24 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_25 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_26 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_27 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_28 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_29 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_30 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_31 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_32 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_33 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_34 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_35 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_36 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_37 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_38 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm3_39 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_0 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_1 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_2 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_3 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_4 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_5 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_6 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_7 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_8 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_9 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_10 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_11 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_12 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_13 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_14 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_15 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_16 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_17 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_18 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_19 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_20 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_21 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_22 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_23 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_24 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_25 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_26 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_27 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_28 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_29 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_30 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_31 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_32 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_33 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_34 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_35 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_36 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_37 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_38 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_39 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_40 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_41 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_42 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_43 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_44 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_45 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_46 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_47 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_48 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_49 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_50 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_51 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_52 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_53 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_54 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_55 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_56 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_57 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_58 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_59 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_60 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_61 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_62 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_63 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_64 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_65 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_66 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_67 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_68 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_69 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_70 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_71 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_72 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_73 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_74 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_75 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_76 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_77 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_78 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm4_79 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm5_0 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_1 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_2 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_3 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_4 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_5 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_6 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_7 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_8 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_9 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_10 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_11 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_12 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_13 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_14 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_15 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_16 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_17 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_18 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_19 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_20 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_21 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_22 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_23 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm5_24 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_0 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_1 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_2 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_3 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_4 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_5 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_6 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_7 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_8 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_9 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_10 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_11 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_12 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_13 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_14 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_15 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_16 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_17 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_18 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_19 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_20 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_21 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_22 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_23 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm6_24 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Mm61_0 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm61_1 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm61_2 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm61_3 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm61_4 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm61_5 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Mm68_0 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Mm68_1 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Mm68_2 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Mm68_3 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Mm68_4 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Mm68_5 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Mm69_0 vout net5 vss vss nfet_03v3 w=4.83u l=8.94u +Mm69_1 vout net5 vss vss nfet_03v3 w=4.83u l=8.94u +Mm69_2 vout net5 vss vss nfet_03v3 w=4.83u l=8.94u +Mm70_0 net3 net050 vdd vdd pfet_03v3 w=26.39u l=6.515u +Mm70_1 net3 net050 vdd vdd pfet_03v3 w=26.39u l=6.515u +Mm71_0 net3 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Mm72_0 net5 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Mm72_1 net5 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Mm72_2 net5 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Mm73_0 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_1 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_2 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_3 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_4 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_5 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_6 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_7 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_8 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_9 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_10 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_11 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_12 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_13 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_14 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_15 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_16 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_17 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_18 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_19 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_20 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_21 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_22 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_23 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_24 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_25 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_26 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_27 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_28 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_29 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_30 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_31 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_32 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_33 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_34 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_35 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_36 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_37 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_38 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_39 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_40 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_41 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_42 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_43 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_44 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_45 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_46 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_47 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_48 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_49 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_50 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_51 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_52 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_53 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_54 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_55 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_56 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_57 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_58 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_59 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_60 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_61 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_62 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_63 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_64 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_65 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_66 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_67 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_68 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_69 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_70 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_71 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_72 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_73 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_74 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_75 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_76 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_77 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_78 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_79 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_80 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_81 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_82 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_83 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_84 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_85 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_86 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_87 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_88 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_89 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_90 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_91 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_92 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_93 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_94 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_95 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_96 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_97 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_98 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_99 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_100 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_101 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_102 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_103 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_104 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_105 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_106 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_107 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_108 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_109 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_110 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_111 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_112 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_113 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_114 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_115 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_116 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_117 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_118 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm73_119 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Mm8_0 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_1 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_2 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_3 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_4 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_5 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_6 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_7 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_8 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_9 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_10 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm8_11 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_0 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_1 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_2 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_3 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_4 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_5 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_6 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_7 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_8 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_9 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_10 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Mm9_11 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +.ends amp_017_tan_clia diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..d9a1126559e823c657548e0c66759106327ca4d2 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.spice @@ -0,0 +1,537 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt amp_017_tan_clia vss vdd vinn vinp vout net1 +XC0_0 net2 vss cap_mim_2f0_m4m5_noshield c_width=10u c_length=30.635u +XC1_0 net8 vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=13.49u +XC1_1 net8 vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=13.49u +XR0_0 net5 R0_seg1 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_1 R0_seg1 R0_seg2 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_2 R0_seg2 R0_seg3 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_3 R0_seg3 R0_seg4 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_4 R0_seg4 R0_seg5 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_5 R0_seg5 R0_seg6 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_6 R0_seg6 R0_seg7 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_7 R0_seg7 R0_seg8 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_8 R0_seg8 R0_seg9 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_9 R0_seg9 R0_seg10 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_10 R0_seg10 R0_seg11 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_11 R0_seg11 R0_seg12 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_12 R0_seg12 R0_seg13 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_13 R0_seg13 R0_seg14 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_14 R0_seg14 R0_seg15 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_15 R0_seg15 R0_seg16 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_16 R0_seg16 R0_seg17 vss ppolyf_u_1k r_width=1u r_length=49.4u +XR0_17 R0_seg17 net2 vss ppolyf_u_1k r_width=1u r_length=49.4u +Xm0_0 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_1 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_2 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_3 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_4 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_5 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_6 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_7 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_8 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_9 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_10 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_11 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_12 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_13 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_14 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_15 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_16 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_17 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_18 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_19 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_20 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_21 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_22 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_23 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_24 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_25 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_26 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_27 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_28 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_29 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_30 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_31 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_32 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_33 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_34 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_35 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_36 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_37 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_38 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm0_39 net1 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_0 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_1 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_2 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_3 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_4 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_5 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_6 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_7 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_8 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_9 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_10 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_11 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_12 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_13 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_14 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_15 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_16 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_17 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_18 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_19 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_20 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_21 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_22 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_23 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_24 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_25 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_26 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_27 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_28 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_29 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_30 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_31 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_32 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_33 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_34 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_35 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_36 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_37 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_38 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm1_39 vb4 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm12_0 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Xm12_1 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Xm12_2 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Xm12_3 vb4 vb3 net6 vss nfet_03v3 w=15u l=3.695u +Xm13_0 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Xm13_1 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Xm13_2 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Xm13_3 dm_1 vb3 net7 vss nfet_03v3 w=15u l=3.695u +Xm14_0 vb3 vb3 vss vss nfet_03v3 w=15u l=3.695u +Xm15_0 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_1 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_2 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_3 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_4 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_5 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_6 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm15_7 voutn vb3 dm_2 vss nfet_03v3 w=15u l=3.695u +Xm16_0 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_1 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_2 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_3 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_4 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_5 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_6 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm16_7 net050 vb3 net8 vss nfet_03v3 w=15u l=3.695u +Xm17_0 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm17_1 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm17_2 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm17_3 net6 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm18_0 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm18_1 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm18_2 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm18_3 net7 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_0 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_1 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_2 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_3 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_4 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_5 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_6 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_7 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_8 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_9 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_10 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm19_11 dm_2 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm2_0 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_1 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_2 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_3 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_4 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_5 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_6 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_7 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_8 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_9 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_10 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_11 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_12 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_13 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_14 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_15 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_16 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_17 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_18 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_19 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_20 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_21 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_22 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_23 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_24 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_25 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_26 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_27 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_28 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_29 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_30 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_31 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_32 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_33 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_34 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_35 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_36 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_37 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_38 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm2_39 dm_1 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm20_0 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_1 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_2 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_3 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_4 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_5 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_6 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_7 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_8 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_9 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_10 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm20_11 net8 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm3_0 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_1 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_2 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_3 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_4 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_5 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_6 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_7 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_8 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_9 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_10 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_11 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_12 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_13 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_14 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_15 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_16 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_17 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_18 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_19 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_20 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_21 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_22 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_23 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_24 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_25 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_26 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_27 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_28 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_29 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_30 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_31 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_32 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_33 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_34 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_35 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_36 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_37 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_38 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm3_39 vb3 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_0 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_1 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_2 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_3 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_4 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_5 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_6 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_7 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_8 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_9 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_10 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_11 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_12 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_13 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_14 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_15 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_16 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_17 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_18 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_19 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_20 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_21 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_22 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_23 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_24 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_25 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_26 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_27 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_28 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_29 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_30 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_31 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_32 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_33 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_34 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_35 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_36 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_37 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_38 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_39 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_40 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_41 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_42 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_43 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_44 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_45 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_46 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_47 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_48 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_49 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_50 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_51 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_52 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_53 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_54 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_55 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_56 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_57 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_58 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_59 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_60 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_61 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_62 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_63 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_64 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_65 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_66 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_67 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_68 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_69 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_70 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_71 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_72 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_73 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_74 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_75 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_76 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_77 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_78 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm4_79 net31 net1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm5_0 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_1 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_2 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_3 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_4 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_5 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_6 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_7 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_8 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_9 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_10 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_11 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_12 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_13 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_14 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_15 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_16 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_17 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_18 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_19 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_20 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_21 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_22 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_23 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm5_24 voutn voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_0 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_1 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_2 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_3 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_4 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_5 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_6 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_7 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_8 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_9 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_10 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_11 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_12 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_13 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_14 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_15 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_16 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_17 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_18 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_19 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_20 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_21 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_22 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_23 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm6_24 net050 voutn vdd vdd pfet_03v3 w=40u l=8.62u +Xm61_0 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm61_1 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm61_2 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm61_3 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm61_4 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm61_5 net3 vb4 vss vss nfet_03v3 w=15u l=3.695u +Xm68_0 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Xm68_1 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Xm68_2 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Xm68_3 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Xm68_4 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Xm68_5 vout net050 vdd vdd pfet_03v3 w=69.225u l=0.365u +Xm69_0 vout net5 vss vss nfet_03v3 w=4.83u l=8.94u +Xm69_1 vout net5 vss vss nfet_03v3 w=4.83u l=8.94u +Xm69_2 vout net5 vss vss nfet_03v3 w=4.83u l=8.94u +Xm70_0 net3 net050 vdd vdd pfet_03v3 w=26.39u l=6.515u +Xm70_1 net3 net050 vdd vdd pfet_03v3 w=26.39u l=6.515u +Xm71_0 net3 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Xm72_0 net5 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Xm72_1 net5 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Xm72_2 net5 net3 vss vss nfet_03v3 w=77.77u l=6.915u +Xm73_0 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_1 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_2 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_3 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_4 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_5 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_6 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_7 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_8 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_9 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_10 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_11 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_12 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_13 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_14 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_15 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_16 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_17 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_18 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_19 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_20 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_21 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_22 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_23 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_24 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_25 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_26 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_27 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_28 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_29 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_30 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_31 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_32 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_33 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_34 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_35 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_36 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_37 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_38 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_39 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_40 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_41 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_42 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_43 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_44 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_45 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_46 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_47 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_48 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_49 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_50 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_51 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_52 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_53 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_54 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_55 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_56 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_57 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_58 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_59 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_60 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_61 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_62 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_63 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_64 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_65 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_66 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_67 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_68 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_69 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_70 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_71 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_72 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_73 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_74 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_75 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_76 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_77 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_78 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_79 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_80 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_81 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_82 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_83 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_84 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_85 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_86 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_87 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pfet_03v3 w=0.865u l=6.06u +Xm73_106 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_107 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_108 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_109 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_110 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_111 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_112 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_113 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_114 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_115 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_116 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_117 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_118 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm73_119 net5 dm_1 vdd vdd pfet_03v3 w=0.865u l=6.06u +Xm8_0 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_1 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_2 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_3 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_4 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_5 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_6 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_7 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_8 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_9 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_10 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm8_11 dm_2 vinn net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_0 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_1 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_2 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_3 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_4 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_5 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_6 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_7 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_8 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_9 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_10 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +Xm9_11 net8 vinp net31 net31 pfet_03v3 w=61.11u l=1.585u +.ends amp_017_tan_clia diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..bcd76729a56c5606400b5f75c9b7966c9839742e --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/schematic.svg @@ -0,0 +1,2 @@ +amp_017_tan_clia{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_017_tan_clia","source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl","netlist_sha256":"59a4d962ade70da8bbdc21dffc81adf077c84baa2057b100deaed0c5f34e7dc2","project_sha256":"a2800bf4aeb1257a95d7e93685e10bed6d332d8022568dae6ff114abffb7c441","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"flat-cdl-project: independent source/project flattened device comparison, schema parse, symbol resolution and netlist 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Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":18},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_017_tan_clia"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/schematic/amp_017_tan_clia.icproj.json"}}Main-sheet overview; 25 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_017_tan_cliavddnet1net31vdddm_1vddnet1vssnet8vb3net050vddnet1vb4vinpnet8net31vddvoutnnet050vssnet8vb4vssvb4dm_2vssvb4net3vssvb3dm_1net7vinndm_2net31vssvb4vb3net6vssnet2net5vddvoutnvssvb3voutndm_2vssvb4net6vssvb4net7vddnet1vb3vddnet5dm_1vddvoutnet050voutnet5vssvssvoutnet2net5vddvddnet050net3vddvddnet050net3vssvssnet3net3vssvoutvssnet5net3vssvssnet5net3vssvssnet8net5net3vddnet1vddnet1vb4vssvb4vb3net6vssvb3dm_1voutnet7vssvb3voutndm_2vssnet8vb3net050net8vssvb4net6vssvb4net7vssvb4dm_2vdddm_1vssnet8vb4vssvddnet1vb3vddnet1net31vddvoutnvddvssvoutnnet050vssvb4net3vddvoutnet050vb3vddnet5dm_1vinndm_2net31vinpnet8net31vb3vssnet2net5vssvddvinnvinpvoutnet1vssvssvssvoutnet5vssvssamp_017_tan_cliaEqual net labels connect. All source devices and exact parameters are retained.C0_0cap_mim_2f0fFw=10u l=30.635uC1_0cap_mim_2f0fFw=20u l=13.49uC1_1cap_mim_2f0fFw=20u l=13.49uMm14_0nfet_03v3w=15u l=3.695uMm69_0nfet_03v3w=4.83u l=8.94uMm69_1nfet_03v3w=4.83u l=8.94uMm69_2nfet_03v3w=4.83u l=8.94uMm70_0pfet_03v3w=26.39u l=6.515uMm70_1pfet_03v3w=26.39u l=6.515uMm71_0nfet_03v3w=77.77u l=6.915uMm72_0nfet_03v3w=77.77u l=6.915uMm72_1nfet_03v3w=77.77u l=6.915uMm72_2nfet_03v3w=77.77u l=6.915uXMm0_bank1Mm0_bank1XMm1_bank2Mm1_bank2XMm12_bank3Mm12_bank3XMm13_bank4Mm13_bank4XMm15_bank5Mm15_bank5XMm16_bank6Mm16_bank6XMm17_bank7Mm17_bank7XMm18_bank8Mm18_bank8XMm19_bank9Mm19_bank9XMm2_bank10Mm2_bank10XMm20_bank11Mm20_bank11XMm3_bank12Mm3_bank12XMm4_bank13Mm4_bank13XMm5_bank14Mm5_bank14XMm6_bank15Mm6_bank15XMm61_bank16Mm61_bank16XMm68_bank17Mm68_bank17XMm73_bank18Mm73_bank18XMm8_bank19Mm8_bank19XMm9_bank20Mm9_bank20XXR0_bank21XR0_bank21 +Main-sheet overview; 25 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..9f53760c12aaa02733b8c1a88cbf29d416ca4cee --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/testbench.spice @@ -0,0 +1,43 @@ +* Same-condition finite-window amplifier observations. SPDX-License-Identifier: MIT +.include support/models.spice +.include parameters.spice +.include dut.spice +.temp 27 +.save v(vdd) v(vout) v(vp) v(net1) i(VDD) +.option klu reltol=1e-5 abstol=1e-12 vntol=1e-8 method=gear maxord=2 itl4=1000 +VDD vdd 0 1.8 +VIN vp 0 dc 0.3 ac 1 pulse(0.3 { 0.3+step_v } 20u 100n 100n 80u 200u) +IBIAS net1 0 2.32803e-06 +XDUT 0 vdd vout vp vout net1 amp_017_tan_clia +CLOAD vout 0 {load_f} +.control +set noaskquit +set num_threads=1 +set numdgt=15 +set measdgt=15 +op +let output_v=v(vout) +let bias_v=v(net1) +let power_w=-v(vdd)*i(VDD) +print output_v bias_v power_w +write op.raw all +ac dec 200 1 1g +let closed_gain_db=db(v(vout)) +meas ac closed_gain_10khz_db find closed_gain_db at=10k +write ac.raw all +tran 10n 200u 0 10n +let error_v=abs(v(vout)-v(vp)) +let supply=-v(vdd)*i(VDD) +meas tran late_error_v avg error_v from=80u to=100u +meas tran return_error_v avg error_v from=180u to=200u +meas tran high_v avg v(vout) from=80u to=100u +meas tran low_v avg v(vout) from=180u to=200u +meas tran ripple_v pp v(vout) from=80u to=100u +meas tran return_ripple_v pp v(vout) from=180u to=200u +meas tran mean_power_w avg supply from=20u to=200u +meas tran output_min_v min v(vout) from=0 to=200u +meas tran output_max_v max v(vout) from=0 to=200u +write transient.raw v(vout) v(vp) i(VDD) error_v supply +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/problem.md b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..9e8ed9baabbe6e413936ed39a028a129e11f28c9 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/problem.md @@ -0,0 +1,140 @@ +# Tan CLIA Three-Stage Amplifier Layout Task + +## Objective + +Implement `amp_017_tan_clia` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded NMOS branches drive voutn/net050. XM70 and XM71/XM72 form the current-inversion path through net3/net5; XM61 and the DM_1-controlled XM73 bias this path. XM68/XM69 drive the output. The 889198 ohm resistor from net5 to net2, 0.61268 pF net2-to-vss capacitor and 1.07905 pF net8-to-vout capacitor all remain. +Do not replace the circuit, delete compensation, or add a servo. The physical core +contains 512 MOS after expanding explicit upstream multiplicities. Each PMOS +input body remains tied to its own tail node through its physical well contact. + +## Inputs and Interface + +`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its +matching simulator representation. `materials/testbench.spice` defines closed-loop +observations and `materials/ac.spice` defines balanced differential AC excitation. +Ordered ports: `vss vdd vinn vinp vout net1`. `vss` is ground, `vdd` supply, +`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net1` +the external bias-current sink. Bias, input drivers, feedback wiring and load are +external test apparatus; taps and all internal R/C are physical DUT elements. + +## Operating Conditions + +GF180MCU D, nominal TT/typical, 27 C, supply 1.8 V, input reference 0.3 V, +external current sink 2.32803e-06 A to vss, and 10 pF output load. Use the fixed GF180 3.3 V device binding at its authored 1.8 V operating rail; round W/L to the 5 nm manufacturing grid. +The closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse +starting at 20 us (100 ns rise/fall, 80 us high duration), and runs to 200 us with +10 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV. +Transient starts from the solved DC point; this is not a zero-state supply-ramp +startup test. High and return windows are 80–100 and 180–200 us. + +AC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output +feedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground; +vinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual +input common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures, +not physical compensation. The separate closed-loop deck measures actual follower +response. No voltage-transfer estimate is labeled a loop return ratio. + +## Physical Requirements + +Supply a GDS <=64 MiB with top cell `amp_017_tan_clia`, within 20000 by 2000 um +(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS +and functional-area measurement must pass; no marker waivers apply. Preserve +MOS dimensions, multiplicities, body connections, all physical R/C and tap geometry. +Functional layers in the published task include active, implant, wells, gates, +contacts, passive plates, vias and routing; annotation/text-only layers are excluded. +GF180 native standalone-block DRC includes FEOL, BEOL, connectivity, manufacturing grid, antenna and dummy fill, with chip-level density and seal-ring closure outside scope. Native MIM-B uses M4/M5 and 2 fF/um2; resistors use 1 kohm/square unsilicided poly. The model boundary excludes distributed substrate resistance. Candidate-derived Magic distributed RC feeds every post-layout job. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition | Unit | Treatment | +| --- | --- | --- | --- | +| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize | +| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale | +| output_v | DC follower output | V | Bias target, 1.8 V scale | +| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor | +| mean_power_w | Mean supply power over 20–200 us | W | Supply, inverse ratio, 1 pW floor | +| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor | +| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor | +| high_v, low_v | Window means | V | Diagnostic | +| bias_v | External bias port DC voltage | V | Diagnostic | +| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic | +| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV | +| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV | + +All measurements must be finite and complete. Nonnegative supply power and +absolute-error/range values follow their physical domains. The common-mode fixture +bound verifies the differential excitation, not DUT common-mode regulation. The +DC feedback bound rejects a failed bias-isolation solve. Both checks fail the +source or candidate simulation before scoring. These +are the only electrical hard bounds; upstream paper targets are not gates. +Window errors and ripple do not assert settled operation or periodic steady state. +No phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed. + +Quality uses independently simulated same-condition source observations. For gain, +q=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale); +inverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds +to a factor-of-two amplitude change; 1.8 V is the bias normalization and 1 mV is +1% of the 100 mV test step, preventing numerical zero error from dominating quality. +Area quality is Q=88555.19 um2/functional_area. + +The compact-area anchor is independent of any reference layout: sum +m*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density +for capacitors (density 2 fF/um2) and 2*R/sheet_resistance um2 +for resistor contact/routing envelopes (sheet resistance 1000 ohm), +then apply a 50% global routing allowance. This is an engineering estimate, not a +foundry minimum. Coefficient 7: Multistage compensation includes a resistively isolated capacitor and a current-inversion output-drive path. + + +### Score weights + +Finite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `late_error_v` | 0.180000000000 | +| `return_error_v` | 0.180000000000 | +| `return_ripple_v` | 0.112500000000 | +| `ripple_v` | 0.112500000000 | +| `closed_gain_10khz_db` | 0.060000000000 | +| `gain_10khz_db` | 0.060000000000 | +| `gain_db` | 0.060000000000 | +| `output_v` | 0.045000000000 | +| `mean_power_w` | 0.045000000000 | +| `power_w` | 0.045000000000 | + +## Tools and Submission + +Solve budget: **8 hours**. + +Use the reviewed GF180MCU D resources and the ngspice 45 tools environment. +The runtime `/protocol/task.json` supplies frozen requirements and resource bindings. +Submit `/workspace/output/final.gds` through the session's explicit submission tool; +writing a file alone does not submit it. Evaluation performs artifact, native +DRC/LVS, geometry, candidate RC, independent source and post-layout simulation. +The source baseline, witness and authoring repository are not solver inputs. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/reference/amp_017_tan_clia.gds b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/reference/amp_017_tan_clia.gds new file mode 100644 index 0000000000000000000000000000000000000000..6dc06fb19638fc482d3124a036b4f363540ca3b9 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/reference/amp_017_tan_clia.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e259ca768f777240880af2ab5cb2222971638349b504800f32d53f69bff1a302 +size 7088754 diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..c08a8c7a4b50e8406c403d980adab03d59a3a4e3 --- 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+requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vinp", + "vinn", + "ibias", + "vss", + "gate_pc", + "casc_n", + "tail", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_f = 1e-12 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +bias_v = "V" +tail_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_f = 3e-12 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +bias_v = "V" +tail_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_f = 5e-12 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +bias_v = "V" +tail_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "bias_v" +category = "performance" +observations = [ + "condition_0:bias_v", + "condition_1:bias_v", + "condition_2:bias_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:bias_v", + "source_condition_1:bias_v", + "source_condition_2:bias_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "tail_v" +category = "performance" +observations = [ + "condition_0:tail_v", + "condition_1:tail_v", + "condition_2:tail_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:tail_v", + "source_condition_1:tail_v", + "source_condition_2:tail_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "gain_db" +category = "performance" +observations = [ + "condition_0:gain_db", + "condition_1:gain_db", + "condition_2:gain_db", +] +unit = "dB" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:gain_db", + "source_condition_1:gain_db", + "source_condition_2:gain_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "unity_hz" +category = "performance" +observations = [ + "condition_0:unity_hz", + "condition_1:unity_hz", + "condition_2:unity_hz", +] +unit = "Hz" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:unity_hz", + "source_condition_1:unity_hz", + "source_condition_2:unity_hz", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "phase_margin" +category = "performance" +observations = [ + "condition_0:phase_margin", + "condition_1:phase_margin", + "condition_2:phase_margin", +] +unit = "deg" +dimension = "response" +direction = "target" +aggregation = "min" +baseline = [ + "source_condition_0:phase_margin", + "source_condition_1:phase_margin", + "source_condition_2:phase_margin", +] +normalization = "target" +scale = 180 +lower = 0 +upper = 180 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 544.15 +rationale = "Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +gain_db = 0.27 +unity_hz = 0.225 +phase_margin = 0.225 +bias_v = 0.015 +output_v = 0.015 +tail_v = 0.015 +power_w = 0.135 + +[task.evaluation.pre_layout] +source_report_sha256 = "119d16685e4416d97cbc4e7bb76489e666ab92e0c3de72ff2fd5688b0e531707" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 3.3 +load_f = 1e-12 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +bias_v = "V" +tail_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "f0bc0845cbb8d4b8f5928a32f6934ea5105942584f04ce7d522b85b29f448ee3" +dut = "6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] +value = 0.7937301727429 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] +value = 15.53969 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.745929058319 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin] +value = 99.22954 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001046444908045 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.tail_v] +value = 0.5770777934068 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] +value = 503431.9 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.3 +load_f = 3e-12 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +bias_v = "V" +tail_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "f0bc0845cbb8d4b8f5928a32f6934ea5105942584f04ce7d522b85b29f448ee3" +dut = "6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] +value = 0.7937301727429 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 15.53969 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 1.745929058319 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin] +value = 99.48987 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0001046444908045 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.tail_v] +value = 0.5770777934068 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] +value = 168564.6 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 +load_f = 5e-12 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +bias_v = "V" +tail_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "f0bc0845cbb8d4b8f5928a32f6934ea5105942584f04ce7d522b85b29f448ee3" +dut = "6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] +value = 0.7937301727429 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_db] +value = 15.53969 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 1.745929058319 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_margin] +value = 99.5422 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.0001046444908045 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.tail_v] +value = 0.5770777934068 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.unity_hz] +value = 101230.5 +unit = "Hz" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_018_telescopic_cascode" + +[qualification] +reference = "reference/amp_018_telescopic_cascode.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies differential inputs with an NMOS telescopic cascode and tail-referenced bias across three capacitive loads." diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..cd141f10e3f2562c73fc83814c9abcf3e3487565 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice @@ -0,0 +1,15 @@ +* Derived from analog-db amp_018_telescopic_cascode, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: External gate_pc/casc_n/tail ports preserve both relative bias sources. +.subckt amp_018_telescopic_cascode vdd vout vinp vinn ibias vss gate_pc casc_n tail +XM1 d1 vinp tail vss nfet_03v3 w=23.3u l=1u m=1 +XM1C gate_p casc_n d1 vss nfet_03v3 w=5.7u l=0.5u m=1 +XM2 d2 vinn tail vss nfet_03v3 w=23.3u l=1u m=1 +XM2C vout casc_n d2 vss nfet_03v3 w=5.7u l=0.5u m=1 +XM3 s3 gate_p vdd vdd pfet_03v3 w=4.7u l=0.5u m=1 +XM3C gate_p gate_pc s3 vdd pfet_03v3 w=7.2u l=0.5u m=1 +XM4 s4 gate_p vdd vdd pfet_03v3 w=4.7u l=0.5u m=1 +XM4C vout gate_pc s4 vdd pfet_03v3 w=7.2u l=0.5u m=1 +XM5 tail ibias vss vss nfet_03v3 w=4.95u l=0.5u m=1 +XM6 ibias ibias vss vss nfet_03v3 w=8.3u l=0.5u m=1 +.ends amp_018_telescopic_cascode diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..130c4993c902116ba5a7ba89e40462694a02e7c6 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/schematic.svg @@ -0,0 +1 @@ +amp_018_telescopic_cascode{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.amp_018_telescopic_cascode", "netlist_sha256": "6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa", "project_sha256": "f70d9481d5aae84770a6e4af7e66132c76db5e5f52bc6c44c74e89190739dac8", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["amp_018_telescopic_cascode"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}amp_018_telescopic_cascodevinpvinnibiasvsss3vdds4gate_pcvoutcasc_nd1d2tailgate_pvssibiasvddvoutvinpvinnibiasvssgate_pccasc_ntailamp_018_telescopic_cascodegf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Telescopic differential stageXM34.7/0.5XM44.7/0.5XM3C7.2/0.5XM4C7.2/0.5XM1C5.7/0.5XM2C5.7/0.5XM123.3/1XM223.3/1XM54.95/0.5P bulk → vddN bulk → vss02 Tail-bias referenceXM68.3/0.5N bulk → vssModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..39a0918f615abfa43e25ae2ff60a8d89e14d69a2 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/testbench.spice @@ -0,0 +1,38 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 {supply_v} +IB vdd ibias 20u +VPC vdd gate_pc 1.143 +VNC casc_n tail 0.917 +VP vinp 0 DC 1.65 AC 0.5 +VN acn 0 DC 1.65 AC 0.5 180 +LFB vout vinn 1T +CIN acn vinn 1 +CL vout 0 {load_f} +XD vdd vout vinp vinn ibias 0 gate_pc casc_n tail amp_018_telescopic_cascode +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let bias_v=v(ibias) +let tail_v=v(tail) +let power_w=-v(vdd)*i(vdd)-(v(vdd)-v(gate_pc))*i(vpc)-(v(casc_n)-v(tail))*i(vnc) +print output_v bias_v tail_v power_w +write op.raw all +ac dec 100 1 1G +let transfer=v(vout)/(v(vinp)-v(vinn)) +let gain_curve=db(transfer) +let phase_curve=180/PI*cph(transfer) +meas ac gain_db find gain_curve at=10 +meas ac unity_hz when gain_curve=0 fall=1 +meas ac phase_deg find phase_curve when gain_curve=0 fall=1 +let phase_margin=180+phase_deg +print phase_margin +write ac.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/problem.md b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..57b28e22c0c99c0201fa2a6813d27b9a97313c45 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/problem.md @@ -0,0 +1,92 @@ +# Tail-Referenced Telescopic Cascode Amplifier Layout Task + +## Objective + +Implement `amp_018_telescopic_cascode` in gf180mcuD and submit self-contained GDS. Ten MOS devices form an NMOS-input telescopic cascode amplifier. Fixed upstream W/L/m are retained, including the single finger of XM5. The two ideal internal sources become external bias connections: VDD minus gate_pc is 1.143 V, and casc_n minus tail is 0.917 V. Exposing tail preserves the second source's relative bias instead of replacing it with an absolute ground-referenced voltage. + +## Inputs and Interface + +`materials/circuit.spice` is the authoritative physical circuit. The same netlist is used for source calibration. `materials/testbench.spice` defines measurements, and this problem is the description input. +Ordered ports: `vdd vout vinp vinn ibias vss gate_pc casc_n tail`. In order: Supply, output, positive input, negative input, reference-current input, return, PMOS cascode bias, NMOS cascode bias, and accessible tail node. + +Preserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT. + +## Operating Conditions + +Temperature is 27 C. Typical GF180 3.3 V MOS and high-resistance poly models, statistical variation disabled. The substrate is not a distributed silicon resistance network. + +VDD = 3.3 V; VSS = 0 V; a 20 uA current source from VDD into ibias. VINP is 1.65 V DC with AC amplitude +0.5 V; VINN has DC output feedback through a 1 TH inductor and AC -0.5 V through a 1 F coupling capacitor. These ideal measurement elements are external apparatus. Output loads are 1, 3 and 5 pF. AC uses 100 points/decade from 1 Hz to 1 GHz and transfer V(vout)/(V(vinp)-V(vinn)). + +## Physical Requirements + +Top cell `amp_018_telescopic_cascode`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, GF180 variant-D DRC including antenna, with chip-level density and seal-ring closure outside scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 140 by 100 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers. + +Every scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. The declared bias gives about 15 dB gain; this is not a high-gain OTA qualification. Large-signal settling, noise, mismatch, other biases and PVT are outside scope. Fabrication signoff is not claimed. + +## Electrical Requirements and Scoring + +All 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output/control voltage | V | target / target | 0 … 3.3 | 3.3 | +| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 | +| `tail_v` | DC V(tail) | V | target / target | 0 … 3.3 | 3.3 | +| `power_w` | DC power delivered by VDD; telescopic also includes both external voltage-bias sources | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `gain_db` | 20 log10(abs(differential transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — | +| `unity_hz` | First falling 0 dB crossing | Hz | maximize / ratio | 0 … +∞ | — | +| `phase_margin` | 180 degrees plus unwrapped transfer phase at unity crossing | deg | target / target | 0 … 180 | 180 | + +Area reference: **544.15 um2**. 10 expanded device instances; sum of device/contact envelopes 312.9250 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **5**; it is independent of +the reference-relative task score. + + +### Score weights + +Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `gain_db` | 0.270000000000 | +| `unity_hz` | 0.225000000000 | +| `phase_margin` | 0.225000000000 | +| `bias_v` | 0.015000000000 | +| `output_v` | 0.015000000000 | +| `tail_v` | 0.015000000000 | +| `power_w` | 0.135000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/reference/amp_018_telescopic_cascode.gds b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/reference/amp_018_telescopic_cascode.gds new file mode 100644 index 0000000000000000000000000000000000000000..db5201dd3ca487bcc270aa5be2d590f0e09808b1 Binary files /dev/null and b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/reference/amp_018_telescopic_cascode.gds differ diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..93214160ffb70d867fbd4ae9510c47e456dc72de --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml @@ -0,0 +1,1218 @@ +in_core = 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"artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vinp", + "vinn", + "ibias", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +common_v = 1.4 +load_f = 1e-11 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +common_v = 1.6 +load_f = 1e-11 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +common_v = 1.8 +load_f = 1e-11 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + 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"V" +aggregation = "max" +direction = "target" +dimension = "bias" +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", + "condition_3:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", + "source_condition_3:output_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +aggregation = "max" +direction = "minimize" +dimension = "supply" +normalization = "ratio" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", + "condition_3:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", + "source_condition_3:power_w", +] + +[[task.evaluation.metrics]] +id = "gain_1hz" +unit = "1" +aggregation = "max" +direction = "target" +dimension = "response" +normalization = "target" +scale = 1 +category = "performance" +observations = [ + "condition_0:gain_1hz", + "condition_1:gain_1hz", + "condition_2:gain_1hz", + "condition_3:gain_1hz", +] +baseline = [ + "source_condition_0:gain_1hz", + "source_condition_1:gain_1hz", + "source_condition_2:gain_1hz", + "source_condition_3:gain_1hz", +] + +[[task.evaluation.metrics]] +id = "gain_1mhz" +unit = "1" +aggregation = "max" +direction = "target" +dimension = "response" +normalization = "target" +scale = 1 +category = "performance" +observations = [ + "condition_0:gain_1mhz", + "condition_1:gain_1mhz", + "condition_2:gain_1mhz", + "condition_3:gain_1mhz", +] +baseline = [ + "source_condition_0:gain_1mhz", + "source_condition_1:gain_1mhz", + "source_condition_2:gain_1mhz", + "source_condition_3:gain_1mhz", +] + +[[task.evaluation.metrics]] +id = "tracking_error_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:tracking_error_v", + "condition_1:tracking_error_v", + "condition_2:tracking_error_v", + "condition_3:tracking_error_v", +] +baseline = [ + "source_condition_0:tracking_error_v", + "source_condition_1:tracking_error_v", + "source_condition_2:tracking_error_v", + "source_condition_3:tracking_error_v", +] + +[[task.evaluation.metrics]] +id = "ripple_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:ripple_v", + "condition_1:ripple_v", + "condition_2:ripple_v", + "condition_3:ripple_v", +] +baseline = [ + "source_condition_0:ripple_v", + "source_condition_1:ripple_v", + "source_condition_2:ripple_v", + "source_condition_3:ripple_v", +] + +[[task.evaluation.metrics]] +id = "step_response_v" +unit = "V" +aggregation = "max" +direction = "minimize" +lower = 0 +category = "performance" +observations = [ + "condition_0:step_response_v", + "condition_1:step_response_v", + "condition_2:step_response_v", + "condition_3:step_response_v", +] + +[[task.evaluation.metrics]] +id = "kcl_a" +unit = "A" +aggregation = "max" +direction = "minimize" +category = "performance" +observations = [ + "condition_0:kcl_a", + "condition_1:kcl_a", + "condition_2:kcl_a", + "condition_3:kcl_a", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 63700 +rationale = "Finite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +tracking_error_v = 0.36 +ripple_v = 0.225 +gain_1hz = 0.09 +gain_1mhz = 0.09 +output_v = 0.045 +power_w = 0.09 + +[task.evaluation.pre_layout] +source_report_sha256 = "919d82b3c42b86667450225728b06ecdbbbf046fc92a68378191aecd2b71661b" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +common_v = 1.4 +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "c981752c1761e6d68a2fcb6996ac8da1391bced942c069335ad2f02d82a46063" +dut = "ec3a97de4fb8f781d5a42035ff95bb7c910c14ea2ab5cd49e0000485b0f487b9" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_1hz] +value = 1.004626 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_1mhz] +value = 0.9971075 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] +value = 8.630249292984615e-17 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.46096640957429 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.007822675145510596 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] +value = 2.797762e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_response_v] +value = 0.01005000000000011 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.tracking_error_v] +value = 0.06099132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +common_v = 1.6 +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "c981752c1761e6d68a2fcb6996ac8da1391bced942c069335ad2f02d82a46063" +dut = "ec3a97de4fb8f781d5a42035ff95bb7c910c14ea2ab5cd49e0000485b0f487b9" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_1hz] +value = 1.014118 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_1mhz] +value = 1.008181 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.kcl_a] +value = 1.040834085586084e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 1.662950751767129 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.008246945589011458 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.ripple_v] +value = 2.375877e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_response_v] +value = 0.01014299999999979 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.tracking_error_v] +value = 0.06302233 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +common_v = 1.8 +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "c981752c1761e6d68a2fcb6996ac8da1391bced942c069335ad2f02d82a46063" +dut = "ec3a97de4fb8f781d5a42035ff95bb7c910c14ea2ab5cd49e0000485b0f487b9" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_1hz] +value = 1.018821 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_1mhz] +value = 1.013682 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.kcl_a] +value = 1.101549407245273e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 1.866308076787991 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.008602854416168928 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.ripple_v] +value = 2.398082e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_response_v] +value = 0.010189 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.tracking_error_v] +value = 0.06640274 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +common_v = 1.6 +load_f = 1e-12 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +power_w = "W" +gain_1hz = "1" +gain_1mhz = "1" +tracking_error_v = "V" +ripple_v = "V" +step_response_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "c981752c1761e6d68a2fcb6996ac8da1391bced942c069335ad2f02d82a46063" +dut = "ec3a97de4fb8f781d5a42035ff95bb7c910c14ea2ab5cd49e0000485b0f487b9" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain_1hz] +value = 1.014118 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain_1mhz] +value = 1.006561 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.kcl_a] +value = 1.040834085586084e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 1.662950751767129 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 0.008246945589011458 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.ripple_v] +value = 2.375877e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_response_v] +value = 0.01014299999999979 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.tracking_error_v] +value = 0.06302233 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_019_ti_ldo_error" + +[qualification] +reference = "reference/amp_019_ti_ldo_error.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies a differential error signal using external bias, level shifting and series Miller compensation." diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..19fc0b869f7c66a9aea56df877e5d299d831a7e3 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl @@ -0,0 +1,62 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt amp_019_ti_ldo_error vdd vout vinp vinn ibias vss +CC_0 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_1 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_2 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_3 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_4 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_5 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_6 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_7 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_8 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_9 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_10 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_11 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_12 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_13 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_14 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_15 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_16 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_17 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_18 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_19 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_20 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_21 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_22 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_23 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_24 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_25 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_26 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_27 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_28 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_29 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_30 ncz vout cap_mim_2f0fF w=20u l=19.53u +CC_31 ncz vout cap_mim_2f0fF w=20u l=19.53u +RND_0 na RND_seg1 vss ppolyf_u_1k w=1u l=48.44u +RND_1 RND_seg1 RND_seg2 vss ppolyf_u_1k w=1u l=48.44u +RND_2 RND_seg2 RND_seg3 vss ppolyf_u_1k w=1u l=48.44u +RND_3 RND_seg3 RND_seg4 vss ppolyf_u_1k w=1u l=48.44u +RND_4 RND_seg4 RND_seg5 vss ppolyf_u_1k w=1u l=48.44u +RND_5 RND_seg5 RND_seg6 vss ppolyf_u_1k w=1u l=48.44u +RND_6 RND_seg6 RND_seg7 vss ppolyf_u_1k w=1u l=48.44u +RND_7 RND_seg7 RND_seg8 vss ppolyf_u_1k w=1u l=48.44u +RND_8 RND_seg8 RND_seg9 vss ppolyf_u_1k w=1u l=48.44u +RND_9 RND_seg9 nd vss ppolyf_u_1k w=1u l=48.44u +MM1_0 na vinn tail vss nfet_06v0 w=40u l=0.7u +MM2_0 nb vinp tail vss nfet_06v0 w=40u l=0.7u +MM3_0 na nd vdd vdd pfet_06v0 w=100u l=0.55u +MM4_0 nlev na nd vdd pfet_06v0 w=10u l=0.55u +MM5_0 nb nd vdd vdd pfet_06v0 w=100u l=0.55u +MM6_0 vout ne vdd vdd pfet_06v0 w=100u l=0.55u +MM7_0 ne ne nb vdd pfet_06v0 w=40u l=0.55u +MMB0_0 ibias ibias vss vss nfet_06v0 w=10u l=2u +MMBC_0 tail ibias vss vss nfet_06v0 w=10u l=2u +MMBE_0 ne ibias vss vss nfet_06v0 w=0.4u l=2u +MMBF_0 nlev ibias vss vss nfet_06v0 w=5u l=2u +MMBO_0 vout ibias vss vss nfet_06v0 w=10u l=2u +RZ0_0 nb ncz vss ppolyf_u_1k w=1u l=1.66u +RZ1_0 nb ncz vss ppolyf_u_1k w=1u l=1.66u +RZ2_0 nb ncz vss ppolyf_u_1k w=1u l=1.66u +RZ3_0 nb ncz vss ppolyf_u_1k w=1u l=1.66u +.ends amp_019_ti_ldo_error diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..93751c320d8907dc015b44c3b8fecd4bce3879c2 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.spice @@ -0,0 +1,62 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt amp_019_ti_ldo_error vdd vout vinp vinn ibias vss +XCC_0 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_1 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_2 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_3 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_4 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_5 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_6 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_7 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_8 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_9 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_10 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_11 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_12 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_13 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_14 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_15 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_16 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_17 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_18 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_19 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_20 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_21 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_22 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_23 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_24 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_25 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_26 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_27 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_28 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_29 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_30 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XCC_31 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.53u +XRND_0 na RND_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_1 RND_seg1 RND_seg2 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_2 RND_seg2 RND_seg3 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_3 RND_seg3 RND_seg4 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_4 RND_seg4 RND_seg5 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_5 RND_seg5 RND_seg6 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_6 RND_seg6 RND_seg7 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_7 RND_seg7 RND_seg8 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_8 RND_seg8 RND_seg9 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRND_9 RND_seg9 nd vss ppolyf_u_1k r_width=1u r_length=48.44u +XM1_0 na vinn tail vss nfet_06v0 w=40u l=0.7u +XM2_0 nb vinp tail vss nfet_06v0 w=40u l=0.7u +XM3_0 na nd vdd vdd pfet_06v0 w=100u l=0.55u +XM4_0 nlev na nd vdd pfet_06v0 w=10u l=0.55u +XM5_0 nb nd vdd vdd pfet_06v0 w=100u l=0.55u +XM6_0 vout ne vdd vdd pfet_06v0 w=100u l=0.55u +XM7_0 ne ne nb vdd pfet_06v0 w=40u l=0.55u +XMB0_0 ibias ibias vss vss nfet_06v0 w=10u l=2u +XMBC_0 tail ibias vss vss nfet_06v0 w=10u l=2u +XMBE_0 ne ibias vss vss nfet_06v0 w=0.4u l=2u +XMBF_0 nlev ibias vss vss nfet_06v0 w=5u l=2u +XMBO_0 vout ibias vss vss nfet_06v0 w=10u l=2u +XRZ0_0 nb ncz vss ppolyf_u_1k r_width=1u r_length=1.66u +XRZ1_0 nb ncz vss ppolyf_u_1k r_width=1u r_length=1.66u +XRZ2_0 nb ncz vss ppolyf_u_1k r_width=1u r_length=1.66u +XRZ3_0 nb ncz vss ppolyf_u_1k r_width=1u r_length=1.66u +.ends amp_019_ti_ldo_error diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..26bcfbd6799f2706228610d45894968ec809b7e8 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/schematic.svg @@ -0,0 +1,2 @@ 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Equal net labels connect.amp_019_ti_ldo_errorvoutnczvssnandvddvddndnbvddvddvssvoutnevddnbneneibiasibiasvssnavssibiasvssvsstailibiasvssvsstailneibiasvssvssnlevvoutibiasvssvssncznbncznbvinpncznbncznbvoutnczvssnavssndvddvoutvinpvinnibiasvsstailnbvddvddnandvddvinnnandnlevamp_019_ti_ldo_errorEqual net labels connect. All source devices and exact parameters are retained.MM1_0nfet_06v0w=40u l=0.7uMM2_0nfet_06v0w=40u l=0.7uMM3_0pfet_06v0w=100u l=0.55uMM4_0pfet_06v0w=10u l=0.55uMM5_0pfet_06v0w=100u l=0.55uMM6_0pfet_06v0w=100u l=0.55uMM7_0pfet_06v0w=40u l=0.55uMMB0_0nfet_06v0w=10u l=2uMMBC_0nfet_06v0w=10u l=2uMMBE_0nfet_06v0w=0.4u l=2uMMBF_0nfet_06v0w=5u l=2uMMBO_0nfet_06v0w=10u l=2uRZ0_0ppolyf_u_1kw=1u l=1.66uSubstrate: B=vssRZ1_0ppolyf_u_1kw=1u l=1.66uSubstrate: B=vssRZ2_0ppolyf_u_1kw=1u l=1.66uSubstrate: B=vssRZ3_0ppolyf_u_1kw=1u l=1.66uSubstrate: B=vssXXCC_bank1XCC_bank1XXRND_bank2XRND_bank2 +Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..6e5001810c334b34e02126783bd443906d84545b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/testbench.spice @@ -0,0 +1,46 @@ +* Independently authored Bench measurements; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 3.3 +VSS vss 0 0 +VIN vinp 0 dc {common_v} ac 1 pulse({common_v} {common_v+.01} 20u 10n 10n 40u 200u) +IB vdd ibias 1m +CL vout vss {load_f} +XDUT vdd vout vinp vout ibias vss amp_019_ti_ldo_error +.control +set numdgt=15 +set measdgt=15 +op +let output_v=v(vout) +let power_w=-v(vdd)*i(vdd) +let kcl_a=abs(i(vdd)+i(vss)+i(vin)) +* Current conservation validates the observation, not circuit performance. +if kcl_a > 1e-08 + echo Invalid DC current conservation: kcl_a exceeds 1e-08 A + quit 1 +end +print output_v power_w kcl_a +write op.raw all +ac dec 100 1 100Meg +let gain=mag(v(vout)) +meas ac gain_1hz find gain at=1 +meas ac gain_1mhz find gain at=1Meg +write ac.raw all +tran 10n 100u 0 10n +let err=abs(v(vout)-v(vinp)) +let pw=-v(vdd)*i(vdd) +meas tran quiet_v avg v(vout) from=10u to=20u +meas tran high_v avg v(vout) from=50u to=60u +meas tran recovery_v avg v(vout) from=90u to=100u +meas tran ripple_v pp v(vout) from=90u to=100u +meas tran tracking_error_v avg err from=20u to=100u +meas tran mean_power_w avg pw from=20u to=100u +let step_response_v=high_v-quiet_v +print step_response_v +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/problem.md b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..395cf990bf59ee0eecbe91cea85ea9f6e9556c5f --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/problem.md @@ -0,0 +1,93 @@ +# Externally Biased TI-Architecture Error Amplifier Layout Task + +## Objective + +Implement `amp_019_ti_ldo_error` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. All twelve MOS remain, including the externally driven NMOS reference diode, four sinks, NMOS differential pair, level-shift branch and PMOS output stage. RND connects na to nd; all 500 kohm remains. Rz/Cc remain in series between nb and vout. No servo is inside the DUT. Four parallel native resistors implement 470 ohm; 32 parallel MIM units implement 25 pF. Native 6 V PMOS lengths become 0.55 um; other dimensions and multiplicities retain the fixed GF180 binding. + +## Inputs and Interface + +`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vdd vout vinp vinn ibias vss`. `vinp` is the non-inverting input and `vinn` the inverting input, verified by follower response. The ideal 1 mA source from vdd to ibias is external and included in supply power. The feedback wire connects vout to vinn externally. + +## Operating Conditions + +3.3 V supply, 1 mA external bias; common-mode inputs 1.4, 1.6 and 1.8 V with 10 pF output load, plus 1.6 V with 1 pF. Direct follower in DC, AC and transient. AC input is 1 V and the reported gain is **closed-loop follower transfer**, never open-loop gain or loop margin. The input rises 10 mV at 20 us with 10 ns edges and returns after 40 us; simulate through 100 us with maximum 10 ns steps. Start at the DC operating point. No extra output resistance, solver shunt, feedback isolation L/C, forced initial conditions or stability claim. Windows are 10–20, 50–60 and 90–100 us. + +All source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold. + +## Physical Requirements + +Submit a valid GDSII containing top cell `amp_019_ti_ldo_error`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[5, 0], [11, 17], [11, 39], [12, 0], [13, 17], [21, 0], [22, 0], [22, 4], [24, 0], [24, 5], [30, 0], [30, 4], [31, 0], [32, 0], [33, 0], [34, 0], [34, 3], [34, 4], [34, 5], [35, 0], [36, 0], [36, 3], [36, 4], [36, 5], [37, 0], [38, 0], [40, 0], [41, 0], [42, 0], [42, 3], [42, 4], [42, 5], [46, 0], [46, 3], [46, 4], [46, 5], [49, 0], [53, 0], [53, 3], [53, 4], [53, 5], [55, 0], [62, 0], [75, 0], [80, 5], [81, 0], [81, 3], [81, 4], [81, 5], [82, 0], [86, 17], [88, 17], [96, 1], [100, 5], [100, 7], [100, 8], [108, 5], [110, 5], [110, 11], [110, 12], [110, 13], [110, 14], [110, 15], [110, 16], [111, 5], [112, 1], [115, 5], [116, 5], [117, 5], [117, 10], [118, 5], [119, 5], [122, 5], [123, 5], [124, 5], [125, 5], [127, 5], [128, 17], [137, 5], [151, 5], [152, 5], [153, 51], [166, 5], [167, 5], [173, 5], [178, 0], [183, 0], [184, 0], [185, 0], [204, 0], [210, 0], [220, 0], [226, 0], [227, 0], [241, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor. + +Post-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. The GF180 model boundary retains physical poly substrate and MIM geometry. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +Coefficient 6 reflects the complete two-stage compensated feedback circuit. It does not claim verified open-loop gain, phase margin, noise, PVT or settling time. Late variation is a finite-window observation. The bias sink ratios are geometric ratios, not promises of saturated current mirrors. + +Every required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores. + +| Metric | Unit | Definition | Dimension / normalization | Functional bounds | +| --- | --- | --- | --- | --- | +| `output_v` | V | DC direct-follower output | bias / target; scale 3.3 | lower=0; upper=3.3 | +| `power_w` | W | Total 3.3 V supply power including external 1 mA bias | supply / ratio; scale 1e-12 | lower=0 | +| `gain_1hz` | 1 | Closed-loop follower magnitude at 1 Hz | response / target; scale 1 | Finite measurement | +| `gain_1mhz` | 1 | Closed-loop follower magnitude at 1 MHz | response / target; scale 1 | Finite measurement | +| `tracking_error_v` | V | Mean absolute tracking error, 20–100 us | response / ratio; scale 0.001 | lower=0 | +| `ripple_v` | V | Finite-window peak-to-peak output, 90–100 us | response / ratio; scale 0.001 | lower=0 | +| `step_response_v` | V | Mean output 50–60 us minus 10–20 us | unscored / functional | lower=0 | +| `kcl_a` | A | External DC KCL residual | diagnostic; unscored | Producer validity guard; see below | + +Target normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff. + +The area anchor is **63700 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (58 units, sum 31829.640000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **6**. + + +### Score weights + +Finite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `tracking_error_v` | 0.360000000000 | +| `ripple_v` | 0.225000000000 | +| `gain_1hz` | 0.090000000000 | +| `gain_1mhz` | 0.090000000000 | +| `output_v` | 0.045000000000 | +| `power_w` | 0.090000000000 | + +## Tools and Submission + +Solve budget: **8 hours**. + +Use the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs. + +The source and extracted-candidate decks require absolute external DC current +conservation residual `kcl_a <= 1e-08 A`. A larger residual aborts +simulation and produces an evaluator error with unknown score, rather than a +functional rejection. The reported residual is an unscored diagnostic. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/reference/amp_019_ti_ldo_error.gds b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/reference/amp_019_ti_ldo_error.gds new file mode 100644 index 0000000000000000000000000000000000000000..7ac15c675a87bed62132f8e8d6256360a03860b6 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/reference/amp_019_ti_ldo_error.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b94ac18804e2de2c634cf48ee7e37318d3604af497145b5c29771ba5bfaa948f +size 1918444 diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..f85f6d81afe725874ba0945c1e4358da4d315ac5 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml @@ -0,0 +1,960 @@ +in_core = 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+[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", +] + +[[task.evaluation.metrics]] +id = "gain_db" +unit = "dB" +dimension = "response" +direction = "maximize" +normalization = "db20" +aggregation = "max" +category = "performance" +observations = [ + "condition_0:gain_db", + "condition_1:gain_db", +] +baseline = [ + "source_condition_0:gain_db", + "source_condition_1:gain_db", +] + +[[task.evaluation.metrics]] +id = "unity_hz" +unit = "Hz" +dimension = "response" +direction = "maximize" +normalization = "ratio" +aggregation = "max" +lower = 0 +category = "performance" +observations = [ + "condition_0:unity_hz", + "condition_1:unity_hz", +] +baseline = [ + "source_condition_0:unity_hz", + "source_condition_1:unity_hz", +] + +[[task.evaluation.metrics]] +id = "phase_margin" +unit = "deg" +dimension = "response" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 180 +category = "performance" +observations = [ + "condition_0:phase_margin", + "condition_1:phase_margin", +] +baseline = [ + "source_condition_0:phase_margin", + "source_condition_1:phase_margin", +] + +[[task.evaluation.metrics]] +id = "tracking_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:tracking_error_v", + "condition_1:tracking_error_v", +] +baseline = [ + "source_condition_0:tracking_error_v", + "source_condition_1:tracking_error_v", +] + +[[task.evaluation.metrics]] +id = "step_response_v" +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0 +category = "performance" +observations = [ + "condition_0:step_response_v", + "condition_1:step_response_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 19112.51 +rationale = "Self-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +tracking_error_v = 0.36 +phase_margin = 0.225 +gain_db = 0.09 +unity_hz = 0.09 +output_v = 0.045 +power_w = 0.09 + +[task.evaluation.pre_layout] +source_report_sha256 = "6231851680f7057b72512cb8a7cdb06510093f842886e7c1c7722149b1d2870e" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" +tracking_error_v = "V" +step_response_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "39a08918a60bc34252e8f29ab0d6b72ab8ba050ed50ca0933b688e3a7a21ee21" +dut = "a4588c07e691e659295ea2c802bf5795511f4d5c17b5590ca0855de92c6e8a6d" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] +value = 73.20742 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.594238840543 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin] +value = 72.0628 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0005963680391366 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_response_v] +value = 0.009986 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.tracking_error_v] +value = 0.005769709 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] +value = 19343220.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +load_f = 1e-12 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" +tracking_error_v = "V" +step_response_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "39a08918a60bc34252e8f29ab0d6b72ab8ba050ed50ca0933b688e3a7a21ee21" +dut = "a4588c07e691e659295ea2c802bf5795511f4d5c17b5590ca0855de92c6e8a6d" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 73.20744 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 1.594238840543 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin] +value = 53.0322 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0005963680391366 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_response_v] +value = 0.009986 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.tracking_error_v] +value = 0.005767942 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] +value = 101642600.0 +unit = "Hz" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_032_ti_ldo_error_selfbias" + +[qualification] +reference = "reference/amp_032_ti_ldo_error_selfbias.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies an error signal with a self-biased two-stage core, level-shifted mirror and Miller compensation." diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..7b6ae041c3fa5b4f5edeb363391bc8d5153b8674 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl @@ -0,0 +1,45 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt amp_032_ti_ldo_error_selfbias vdd vout vinp vinn vss +CC_0 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_1 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_2 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_3 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_4 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_5 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_6 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_7 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_8 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_9 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_10 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_11 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_12 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_13 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_14 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_15 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_16 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_17 ncz vout cap_mim_2f0fF w=20u l=19.735u +CC_18 ncz vout cap_mim_2f0fF w=20u l=19.735u +RND_0 na RND_seg1 vss ppolyf_u_1k w=1u l=50u +RND_1 RND_seg1 RND_seg2 vss ppolyf_u_1k w=1u l=50u +RND_2 RND_seg2 RND_seg3 vss ppolyf_u_1k w=1u l=50u +RND_3 RND_seg3 RND_seg4 vss ppolyf_u_1k w=1u l=50u +RND_4 RND_seg4 RND_seg5 vss ppolyf_u_1k w=1u l=50u +RND_5 RND_seg5 RND_seg6 vss ppolyf_u_1k w=1u l=50u +RND_6 RND_seg6 RND_seg7 vss ppolyf_u_1k w=1u l=50u +RND_7 RND_seg7 RND_seg8 vss ppolyf_u_1k w=1u l=50u +RND_8 RND_seg8 RND_seg9 vss ppolyf_u_1k w=1u l=50u +RND_9 RND_seg9 nd vss ppolyf_u_1k w=1u l=50u +RZ_0 nb ncz vss ppolyf_u_1k w=1u l=10u +MM1_0 na vinn tail vss nfet_06v0 w=68.54u l=0.7u +MM2_0 nb vinp tail vss nfet_06v0 w=68.54u l=0.7u +MM3_0 na nd vdd vdd pfet_06v0 w=69.545u l=0.55u +MM4_0 nlev na nd vdd pfet_06v0 w=10u l=0.55u +MM5_0 nb nd vdd vdd pfet_06v0 w=69.545u l=0.55u +MM6_0 vout nb vdd vdd pfet_06v0 w=60u l=1u +MMB0_0 ibias ibias vss vss nfet_06v0 w=34.535u l=2u +MMBC_0 tail ibias vss vss nfet_06v0 w=34.535u l=2u +MMBF_0 nlev ibias vss vss nfet_06v0 w=5u l=2u +MMBO_0 vout ibias vss vss nfet_06v0 w=34.535u l=2u +MMBP_0 ibias ibias vdd vdd pfet_06v0 w=6.31u l=2u +.ends amp_032_ti_ldo_error_selfbias diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..134f06dc9607c316833010fd80d508fa3410852e --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.spice @@ -0,0 +1,45 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt amp_032_ti_ldo_error_selfbias vdd vout vinp vinn vss +XCC_0 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_1 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_2 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_3 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_4 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_5 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_6 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_7 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_8 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_9 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_10 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_11 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_12 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_13 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_14 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_15 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_16 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_17 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XCC_18 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.735u +XRND_0 na RND_seg1 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_1 RND_seg1 RND_seg2 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_2 RND_seg2 RND_seg3 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_3 RND_seg3 RND_seg4 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_4 RND_seg4 RND_seg5 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_5 RND_seg5 RND_seg6 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_6 RND_seg6 RND_seg7 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_7 RND_seg7 RND_seg8 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_8 RND_seg8 RND_seg9 vss ppolyf_u_1k r_width=1u r_length=50u +XRND_9 RND_seg9 nd vss ppolyf_u_1k r_width=1u r_length=50u +XRZ_0 nb ncz vss ppolyf_u_1k r_width=1u r_length=10u +XM1_0 na vinn tail vss nfet_06v0 w=68.54u l=0.7u +XM2_0 nb vinp tail vss nfet_06v0 w=68.54u l=0.7u +XM3_0 na nd vdd vdd pfet_06v0 w=69.545u l=0.55u +XM4_0 nlev na nd vdd pfet_06v0 w=10u l=0.55u +XM5_0 nb nd vdd vdd pfet_06v0 w=69.545u l=0.55u +XM6_0 vout nb vdd vdd pfet_06v0 w=60u l=1u +XMB0_0 ibias ibias vss vss nfet_06v0 w=34.535u l=2u +XMBC_0 tail ibias vss vss nfet_06v0 w=34.535u l=2u +XMBF_0 nlev ibias vss vss nfet_06v0 w=5u l=2u +XMBO_0 vout ibias vss vss nfet_06v0 w=34.535u l=2u +XMBP_0 ibias ibias vdd vdd pfet_06v0 w=6.31u l=2u +.ends amp_032_ti_ldo_error_selfbias diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..e4f2397c4066ccf38d96e204b2ae6e3377e11940 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/schematic.svg @@ -0,0 +1,2 @@ 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Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":11},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_032_ti_ldo_error_selfbias"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/schematic/amp_032_ti_ldo_error_selfbias.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_032_ti_ldo_error_selfbiasvoutnczvssnandndnlevvddvddndnbnbvddvddvoutnbvssvssibiasibiasvssvsstailibiasvssvssnlevvinnibiasvoutvssvssibiasvddvddibiasibiasvssvoutnczvssnandvddvoutvinpvinnnavsstailvinpvssnbtailvddvddnanczndvddnaamp_032_ti_ldo_error_selfbiasEqual net labels connect. All source devices and exact parameters are retained.RZ_0ppolyf_u_1kw=1u l=10uSubstrate: B=vssMM1_0nfet_06v0w=68.54u l=0.7uMM2_0nfet_06v0w=68.54u l=0.7uMM3_0pfet_06v0w=69.545u l=0.55uMM4_0pfet_06v0w=10u l=0.55uMM5_0pfet_06v0w=69.545u l=0.55uMM6_0pfet_06v0w=60u l=1uMMB0_0nfet_06v0w=34.535u l=2uMMBC_0nfet_06v0w=34.535u l=2uMMBF_0nfet_06v0w=5u l=2uMMBO_0nfet_06v0w=34.535u l=2uMMBP_0pfet_06v0w=6.31u l=2uXXCC_bank1XCC_bank1XXRND_bank2XRND_bank2 +Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..5daa2626af72e46d86082031eef4c8eff7346791 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/testbench.spice @@ -0,0 +1,43 @@ +* Bench nominal AC/DC and unity-buffer transient measurements. +* SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 3.3 +VIN vinp 0 DC 1.6 AC 1 PWL(0 1.6 1u 1.6 1.01u 1.61 3u 1.61 3.01u 1.6 5u 1.6) +LFB vout vinn 1T +CIN vinn 0 1 +CL vout 0 {load_f} +XDUT vdd vout vinp vinn 0 amp_032_ti_ldo_error_selfbias +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let power_w=-v(vdd)*i(vdd) +print output_v power_w +write op.raw +ac dec 100 1 1G +let transfer=v(vout) +let response_db=db(transfer) +meas ac gain_db find response_db at=10 +meas ac unity_hz when response_db=0 fall=1 +let phase_deg=180*cph(transfer)/pi +meas ac phase_unity find phase_deg when response_db=0 fall=1 +let phase_margin=180+phase_unity +print phase_margin +write ac.raw +alter LFB 1p +alter CIN 1a +tran 1n 5u +let tracking_error=abs(v(vout)-v(vinp)) +meas tran tracking_error_v avg tracking_error from=1u to=5u +meas tran step_low_v avg v(vout) from=4u to=5u +meas tran step_high_v avg v(vout) from=2u to=3u +let step_response_v=step_high_v-step_low_v +print step_response_v +write transient.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/problem.md b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..0a672243ffc414d4122beed2135b2b316ef5462f --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/problem.md @@ -0,0 +1,132 @@ +# Self-Biased LDO Error Amplifier Layout Task + +## Objective + +Implement `amp_032_ti_ldo_error_selfbias` as a GF180MCU D layout. Eleven MOS devices form the fixed upstream two-stage amplifier, with a level-shifted PMOS mirror, its 500 kohm gate-rail tie, diode-connected self-bias and series Miller compensation. The direct common-source output stage is the revision present in the pinned netlist; the retired stacked stage is not used. + + +## Inputs and Interface + +`materials/circuit.cdl` is the physical authority. `materials/circuit.spice` +contains the corresponding native simulator wrappers; `materials/testbench.spice` +defines all measurements. Ordered ports: `vdd vout vinp vinn vss`. +`vdd/vss` are supply/return, `vinp/vinn` are differential inputs, and `vout` is the output. +No external bias current is required. Preserve connectivity and total device dimensions; +parallel equivalent fingers are permitted. Do not substitute a different amplifier. + +## Operating Conditions + +Typical native GF180 6 V MOS models, 3.3 V supply, 27 C, statistics disabled. +Input common mode is 1.6 V. Both 1 pF and 10 pF output loads are evaluated. +DC uses unity feedback. AC uses a 1 TH feedback inductor and 1 F input shunt +from 1 Hz to 1 GHz, 100 points/decade. Transient replaces these fixture elements +with 1 pH and 1 aF: the input rises 10 mV at 1 us and falls at 3 us, each in +10 ns. The simulation ends at 5 us, with a 1 ns requested step. +These ideal fixture elements are external test apparatus, outside the DUT. + +## Physical Requirements + +GDS database unit 0.001 um; maximum 10 MiB; top cell `amp_032_ti_ldo_error_selfbias`. +Native standalone DRC includes geometry, connectivity, manufacturing grid, +dummy fill and antenna rules; chip density and seal-ring closure are excluded. +Native LVS must match devices, parameters and every named port. All device, +well, implant, contact, passive-marker and routing layers listed in the runtime +outline form the functional bounding rectangle; text annotations are excluded. +Maximum outline is 5000 by 1000 um. Labels belong on native Metal1 text. + +The 6 V minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS. +Upstream dimensions are rounded to 5 nm, with only subminimum lengths raised. +Physical passives use 1 kohm/square poly and MIM-B, 2 fF/um2, between M4/M5. +Long resistors are series segmented; capacitors are parallel tiled. Nominal +values are implemented by geometry; source and candidate use the same native +process models. MOS diffusion areas/perimeters and interconnect parasitics are +candidate-derived. Magic extracts nominal coupling capacitance and distributed +resistance using zero omission thresholds. Ideal well/substrate connections +exclude distributed substrate noise; no inductance, RF/EM or statistical claim +is made. Finite source and candidate observations must be available. Every declared +operating point must satisfy its functional checks; incomplete evaluation cannot +establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition | Unit | Dimension | Normalization | +| --- | --- | --- | --- | --- | +| `output_v` | DC output voltage | V | bias | target | +| `power_w` | DC supply power: -VDD*I(VDD) | W | supply | ratio | +| `gain_db` | Open-loop magnitude at 10 Hz in dB | dB | response | db20 | +| `unity_hz` | First falling unity-gain crossing | Hz | response | ratio | +| `phase_margin` | 180 degrees plus unwrapped phase at unity crossing | deg | response | target | +| `tracking_error_v` | Mean absolute unity-buffer tracking error over 1–5 us | V | response | ratio | +| `step_response_v` | Mean output at 2–3 us minus mean output at 4–5 us; nonnegative sign-domain check (zero is allowed) | V | functional | unscored | + +DC output must remain between the rails, power and absolute tracking error must +be nonnegative, and the signed output-step observation must be nonnegative (zero is allowed). These +bounds express physical domains and buffer function. Every required measurement +must be finite; failed or missing measurements are evaluation errors, not poor +performance. No upstream data-sheet target is an acceptance gate. Phase margin +is measured and continuously compared, without importing an upstream threshold. + +Each quality observation is paired with an independent source simulation using +the identical deck, load, supply, temperature and models. `target` uses scale +3.3 V for output and 180 degrees for phase; ratio floors are 1 pW for power +and 1 mV for tracking error. These are normalization units, not tolerances. + + +Area target: **19112.51 um2**. Device/contact envelopes sum to 12143.285500 um2, +using `(W+2)*(L+2)` per expanded MOS, resistor segment and capacitor tile +in micrometers. The estimate adds 50% routing plus a 2 um outer margin: +`ceil(100*(1.5*envelope_sum+8*sqrt(envelope_sum)+16))/100`. +This engineering anchor is independent of the witness footprint and is not a +foundry minimum. Coefficient **6** reflects a complete compensated two-stage +loop with self-bias and load-dependent transient response. + + +### Score weights + +Self-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `tracking_error_v` | 0.360000000000 | +| `phase_margin` | 0.225000000000 | +| `gain_db` | 0.090000000000 | +| `unity_hz` | 0.090000000000 | +| `output_v` | 0.045000000000 | +| `power_w` | 0.090000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use `/protocol/task.json`, `/protocol/resources.json` and +`/protocol/harness.json` for the frozen task, reviewed PDK and harness. +KLayout checks physical validity, Magic extracts the submitted layout and +ngspice performs measurements. Use `process-feedback` if exposed. +Write `/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/reference/amp_032_ti_ldo_error_selfbias.gds b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/reference/amp_032_ti_ldo_error_selfbias.gds new file mode 100644 index 0000000000000000000000000000000000000000..74eafbf0e3a26864db368b5b35ed385f8345ef52 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/reference/amp_032_ti_ldo_error_selfbias.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e7771e930cffc0f6c7cac7266e57472524a91a8a92587f42ca47013b75208f2f +size 1255416 diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..d3138e58db59ebde93f2401037baccf8de050a2e --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml @@ -0,0 +1,960 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.amp_033_ti_ldo_ref_selfbias" +title = "Self-Biased LDO Reference Amplifier" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "2d8612b3be9c8b68fbdec4d227211ef68abb60f76a21c90937782b6bf3017d17" + +[[assets]] +path = "reference/amp_033_ti_ldo_ref_selfbias.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "02acc9ce047658f8eb14477dbafdb9f5370cef17f50d30875f6fa6a42c934d71" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_selfbiased_miller_amplifier" +coefficient = 6 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = 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"check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vinp", + "vinn", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 1e-11 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" +tracking_error_v = "V" +step_response_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 1e-12 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" +tracking_error_v = "V" +step_response_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +dimension = "bias" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 3.3 +lower = 0 +upper = 3.3 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", +] + +[[task.evaluation.metrics]] +id = "gain_db" +unit = "dB" +dimension = "response" +direction = "maximize" +normalization = "db20" +aggregation = "max" +category = "performance" +observations = [ + "condition_0:gain_db", + "condition_1:gain_db", +] +baseline = [ + "source_condition_0:gain_db", + "source_condition_1:gain_db", +] + +[[task.evaluation.metrics]] +id = "unity_hz" +unit = "Hz" +dimension = "response" +direction = "maximize" +normalization = "ratio" +aggregation = "max" +lower = 0 +category = "performance" +observations = [ + "condition_0:unity_hz", + "condition_1:unity_hz", +] +baseline = [ + "source_condition_0:unity_hz", + "source_condition_1:unity_hz", +] + +[[task.evaluation.metrics]] +id = "phase_margin" +unit = "deg" +dimension = "response" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 180 +category = "performance" +observations = [ + "condition_0:phase_margin", + "condition_1:phase_margin", +] +baseline = [ + "source_condition_0:phase_margin", + "source_condition_1:phase_margin", +] + +[[task.evaluation.metrics]] +id = "tracking_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:tracking_error_v", + "condition_1:tracking_error_v", +] +baseline = [ + "source_condition_0:tracking_error_v", + "source_condition_1:tracking_error_v", +] + +[[task.evaluation.metrics]] +id = "step_response_v" +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0 +category = "performance" +observations = [ + "condition_0:step_response_v", + "condition_1:step_response_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 6223.21 +rationale = "Self-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +tracking_error_v = 0.36 +phase_margin = 0.225 +gain_db = 0.09 +unity_hz = 0.09 +output_v = 0.045 +power_w = 0.09 + +[task.evaluation.pre_layout] +source_report_sha256 = "6b39697a36cd1f6903fee945161049383fd73ae7ce578231a6be32fbfbb06a18" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" +tracking_error_v = "V" +step_response_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "b6dcd8366c7e6b5a99ec2ffad81f0a9376194f2af47d8b6a9aa7b5df3adf7556" +dut = "e1481981e0bc58b0b42d7555131b589b018621c5d807bd56ca70c866e384419f" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] +value = 74.18441 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.7962011531549 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin] +value = 73.4321 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0003905593035836 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_response_v] +value = 0.0100667 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.tracking_error_v] +value = 0.003798886 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] +value = 7623046.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +load_f = 1e-12 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +gain_db = "dB" +unity_hz = "Hz" +phase_margin = "deg" +tracking_error_v = "V" +step_response_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "b6dcd8366c7e6b5a99ec2ffad81f0a9376194f2af47d8b6a9aa7b5df3adf7556" +dut = "e1481981e0bc58b0b42d7555131b589b018621c5d807bd56ca70c866e384419f" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 74.18444 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 0.7962011531549 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin] +value = 32.4064 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0003905593035836 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_response_v] +value = 0.0100666 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.tracking_error_v] +value = 0.00376649 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] +value = 42373250.0 +unit = "Hz" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_033_ti_ldo_ref_selfbias" + +[qualification] +reference = "reference/amp_033_ti_ldo_ref_selfbias.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Buffers a reference through a self-biased two-stage Miller amplifier under external unity feedback." diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..33b372927a16840589e8eb7d5c5336b7118df8c2 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl @@ -0,0 +1,20 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt amp_033_ti_ldo_ref_selfbias vdd vout vinp vinn vss +CC_0 ncz vout cap_mim_2f0fF w=20u l=18.785u +CC_1 ncz vout cap_mim_2f0fF w=20u l=18.785u +CC_2 ncz vout cap_mim_2f0fF w=20u l=18.785u +CC_3 ncz vout cap_mim_2f0fF w=20u l=18.785u +CC_4 ncz vout cap_mim_2f0fF w=20u l=18.785u +CC_5 ncz vout cap_mim_2f0fF w=20u l=18.785u +RZ_0 nb ncz vss ppolyf_u_1k w=1u l=30.855u +MM1_0 na vinn tail vss nfet_06v0 w=86.42u l=0.7u +MM2_0 nb vinp tail vss nfet_06v0 w=86.42u l=0.7u +MM3_0 na na vdd vdd pfet_06v0 w=20u l=1u +MM4_0 nb na vdd vdd pfet_06v0 w=20u l=1u +MM5_0 vout nb vdd vdd pfet_06v0 w=37.76u l=2.645u +MMB0_0 ibias ibias vss vss nfet_06v0 w=12u l=2u +MMBC_0 tail ibias vss vss nfet_06v0 w=8.315u l=2u +MMBO_0 vout ibias vss vss nfet_06v0 w=4u l=2u +MMBP_0 ibias ibias vdd vdd pfet_06v0 w=10.845u l=2u +.ends amp_033_ti_ldo_ref_selfbias diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..92efe52d0bdc65d37866d5e4488c96d5883473da --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.spice @@ -0,0 +1,20 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt amp_033_ti_ldo_ref_selfbias vdd vout vinp vinn vss +XCC_0 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCC_1 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCC_2 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCC_3 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCC_4 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCC_5 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XRZ_0 nb ncz vss ppolyf_u_1k r_width=1u r_length=30.855u +XM1_0 na vinn tail vss nfet_06v0 w=86.42u l=0.7u +XM2_0 nb vinp tail vss nfet_06v0 w=86.42u l=0.7u +XM3_0 na na vdd vdd pfet_06v0 w=20u l=1u +XM4_0 nb na vdd vdd pfet_06v0 w=20u l=1u +XM5_0 vout nb vdd vdd pfet_06v0 w=37.76u l=2.645u +XMB0_0 ibias ibias vss vss nfet_06v0 w=12u l=2u +XMBC_0 tail ibias vss vss nfet_06v0 w=8.315u l=2u +XMBO_0 vout ibias vss vss nfet_06v0 w=4u l=2u +XMBP_0 ibias ibias vdd vdd pfet_06v0 w=10.845u l=2u +.ends amp_033_ti_ldo_ref_selfbias diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..8e3447c671dcde75995911e8969848eb9aa07241 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/schematic.svg @@ -0,0 +1,2 @@ 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Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":1},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_033_ti_ldo_ref_selfbias"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/schematic/amp_033_ti_ldo_ref_selfbias.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_033_ti_ldo_ref_selfbiasvoutncznbnavddvddvoutnbnbvssvssibiasibiasvssvsstailibiasvoutvssvssibiasvddvddibiasvinnibiasvoutnczvddvoutvinpvinnvssvssnatailvinpvssnbtailvddvddnancznavddvddamp_033_ti_ldo_ref_selfbiasEqual net labels connect. All source devices and exact parameters are retained.RZ_0ppolyf_u_1kw=1u l=30.855uSubstrate: B=vssMM1_0nfet_06v0w=86.42u l=0.7uMM2_0nfet_06v0w=86.42u l=0.7uMM3_0pfet_06v0w=20u l=1uMM4_0pfet_06v0w=20u l=1uMM5_0pfet_06v0w=37.76u l=2.645uMMB0_0nfet_06v0w=12u l=2uMMBC_0nfet_06v0w=8.315u l=2uMMBO_0nfet_06v0w=4u l=2uMMBP_0pfet_06v0w=10.845u l=2uXXCC_bank1XCC_bank1 +Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..60f25cd19e7907614ce4caf7b6c9b0fb45650af2 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/testbench.spice @@ -0,0 +1,43 @@ +* Bench nominal AC/DC and unity-buffer transient measurements. +* SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 3.3 +VIN vinp 0 DC 0.8 AC 1 PWL(0 0.8 1u 0.8 1.01u 0.81 3u 0.81 3.01u 0.8 5u 0.8) +LFB vout vinn 1T +CIN vinn 0 1 +CL vout 0 {load_f} +XDUT vdd vout vinp vinn 0 amp_033_ti_ldo_ref_selfbias +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let power_w=-v(vdd)*i(vdd) +print output_v power_w +write op.raw +ac dec 100 1 1G +let transfer=v(vout) +let response_db=db(transfer) +meas ac gain_db find response_db at=10 +meas ac unity_hz when response_db=0 fall=1 +let phase_deg=180*cph(transfer)/pi +meas ac phase_unity find phase_deg when response_db=0 fall=1 +let phase_margin=180+phase_unity +print phase_margin +write ac.raw +alter LFB 1p +alter CIN 1a +tran 1n 5u +let tracking_error=abs(v(vout)-v(vinp)) +meas tran tracking_error_v avg tracking_error from=1u to=5u +meas tran step_low_v avg v(vout) from=4u to=5u +meas tran step_high_v avg v(vout) from=2u to=3u +let step_response_v=step_high_v-step_low_v +print step_response_v +write transient.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/problem.md b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..dfdd356c3e62abb56c6155fea132766d7a1eb79c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/problem.md @@ -0,0 +1,132 @@ +# Self-Biased LDO Reference Amplifier Layout Task + +## Objective + +Implement `amp_033_ti_ldo_ref_selfbias` as a GF180MCU D layout. Nine MOS devices form the fixed upstream two-stage Miller amplifier, with a matched PMOS mirror and diode-connected self-bias. External unity feedback tests the reference-buffer function; no ideal internal amplifier or bias servo is inserted. + + +## Inputs and Interface + +`materials/circuit.cdl` is the physical authority. `materials/circuit.spice` +contains the corresponding native simulator wrappers; `materials/testbench.spice` +defines all measurements. Ordered ports: `vdd vout vinp vinn vss`. +`vdd/vss` are supply/return, `vinp/vinn` are differential inputs, and `vout` is the output. +No external bias current is required. Preserve connectivity and total device dimensions; +parallel equivalent fingers are permitted. Do not substitute a different amplifier. + +## Operating Conditions + +Typical native GF180 6 V MOS models, 3.3 V supply, 27 C, statistics disabled. +Input common mode is 0.8 V. Both 1 pF and 10 pF output loads are evaluated. +DC uses unity feedback. AC uses a 1 TH feedback inductor and 1 F input shunt +from 1 Hz to 1 GHz, 100 points/decade. Transient replaces these fixture elements +with 1 pH and 1 aF: the input rises 10 mV at 1 us and falls at 3 us, each in +10 ns. The simulation ends at 5 us, with a 1 ns requested step. +These ideal fixture elements are external test apparatus, outside the DUT. + +## Physical Requirements + +GDS database unit 0.001 um; maximum 10 MiB; top cell `amp_033_ti_ldo_ref_selfbias`. +Native standalone DRC includes geometry, connectivity, manufacturing grid, +dummy fill and antenna rules; chip density and seal-ring closure are excluded. +Native LVS must match devices, parameters and every named port. All device, +well, implant, contact, passive-marker and routing layers listed in the runtime +outline form the functional bounding rectangle; text annotations are excluded. +Maximum outline is 5000 by 1000 um. Labels belong on native Metal1 text. + +The 6 V minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS. +Upstream dimensions are rounded to 5 nm, with only subminimum lengths raised. +Physical passives use 1 kohm/square poly and MIM-B, 2 fF/um2, between M4/M5. +Long resistors are series segmented; capacitors are parallel tiled. Nominal +values are implemented by geometry; source and candidate use the same native +process models. MOS diffusion areas/perimeters and interconnect parasitics are +candidate-derived. Magic extracts nominal coupling capacitance and distributed +resistance using zero omission thresholds. Ideal well/substrate connections +exclude distributed substrate noise; no inductance, RF/EM or statistical claim +is made. Finite source and candidate observations must be available. Every declared +operating point must satisfy its functional checks; incomplete evaluation cannot +establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition | Unit | Dimension | Normalization | +| --- | --- | --- | --- | --- | +| `output_v` | DC output voltage | V | bias | target | +| `power_w` | DC supply power: -VDD*I(VDD) | W | supply | ratio | +| `gain_db` | Open-loop magnitude at 10 Hz in dB | dB | response | db20 | +| `unity_hz` | First falling unity-gain crossing | Hz | response | ratio | +| `phase_margin` | 180 degrees plus unwrapped phase at unity crossing | deg | response | target | +| `tracking_error_v` | Mean absolute unity-buffer tracking error over 1–5 us | V | response | ratio | +| `step_response_v` | Mean output at 2–3 us minus mean output at 4–5 us; nonnegative sign-domain check (zero is allowed) | V | functional | unscored | + +DC output must remain between the rails, power and absolute tracking error must +be nonnegative, and the signed output-step observation must be nonnegative (zero is allowed). These +bounds express physical domains and buffer function. Every required measurement +must be finite; failed or missing measurements are evaluation errors, not poor +performance. No upstream data-sheet target is an acceptance gate. Phase margin +is measured and continuously compared, without importing an upstream threshold. + +Each quality observation is paired with an independent source simulation using +the identical deck, load, supply, temperature and models. `target` uses scale +3.3 V for output and 180 degrees for phase; ratio floors are 1 pW for power +and 1 mV for tracking error. These are normalization units, not tolerances. + + +Area target: **6223.21 um2**. Device/contact envelopes sum to 3808.978200 um2, +using `(W+2)*(L+2)` per expanded MOS, resistor segment and capacitor tile +in micrometers. The estimate adds 50% routing plus a 2 um outer margin: +`ceil(100*(1.5*envelope_sum+8*sqrt(envelope_sum)+16))/100`. +This engineering anchor is independent of the witness footprint and is not a +foundry minimum. Coefficient **6** reflects a complete compensated two-stage +loop with self-bias and load-dependent transient response. + + +### Score weights + +Self-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `tracking_error_v` | 0.360000000000 | +| `phase_margin` | 0.225000000000 | +| `gain_db` | 0.090000000000 | +| `unity_hz` | 0.090000000000 | +| `output_v` | 0.045000000000 | +| `power_w` | 0.090000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use `/protocol/task.json`, `/protocol/resources.json` and +`/protocol/harness.json` for the frozen task, reviewed PDK and harness. +KLayout checks physical validity, Magic extracts the submitted layout and +ngspice performs measurements. Use `process-feedback` if exposed. +Write `/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/reference/amp_033_ti_ldo_ref_selfbias.gds b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/reference/amp_033_ti_ldo_ref_selfbias.gds new file mode 100644 index 0000000000000000000000000000000000000000..39f045de34874286221939381985e52ebb198a86 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/reference/amp_033_ti_ldo_ref_selfbias.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:02acc9ce047658f8eb14477dbafdb9f5370cef17f50d30875f6fa6a42c934d71 +size 462360 diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..6ef49eebb872ed1f2b19e0cd800b07591b30a057 --- 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+requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vinp", + "vinn", + "vcmfb", + "vref", + "vdd", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +diff_v = 0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +error_v = "V" +power_w = "W" +recovery_up_v = "V" +recovery_down_v = "V" +recovery_zero_v = "V" +peak_error_v = "V" +mean_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +diff_v = 0.1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +error_v = "V" +power_w = "W" +recovery_up_v = "V" +recovery_down_v = "V" +recovery_zero_v = "V" +peak_error_v = "V" +mean_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +diff_v = 0.2 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +error_v = "V" +power_w = "W" +recovery_up_v = "V" +recovery_down_v = "V" +recovery_zero_v = "V" +peak_error_v = "V" +mean_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "error_v" +category = "performance" +observations = [ + "condition_0:error_v", + "condition_1:error_v", + "condition_2:error_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:error_v", + "source_condition_1:error_v", + "source_condition_2:error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "recovery_up_v" +category = "performance" +observations = [ + "condition_0:recovery_up_v", + "condition_1:recovery_up_v", + "condition_2:recovery_up_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:recovery_up_v", + "source_condition_1:recovery_up_v", + "source_condition_2:recovery_up_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "recovery_down_v" +category = "performance" +observations = [ + "condition_0:recovery_down_v", + "condition_1:recovery_down_v", + "condition_2:recovery_down_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:recovery_down_v", + "source_condition_1:recovery_down_v", + "source_condition_2:recovery_down_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "recovery_zero_v" +category = "performance" +observations = [ + "condition_0:recovery_zero_v", + "condition_1:recovery_zero_v", + "condition_2:recovery_zero_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:recovery_zero_v", + "source_condition_1:recovery_zero_v", + "source_condition_2:recovery_zero_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "peak_error_v" +category = "performance" +observations = [ + "condition_0:peak_error_v", + "condition_1:peak_error_v", + "condition_2:peak_error_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:peak_error_v", + "source_condition_1:peak_error_v", + "source_condition_2:peak_error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "mean_power_w" +category = "performance" +observations = [ + "condition_0:mean_power_w", + "condition_1:mean_power_w", + "condition_2:mean_power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:mean_power_w", + "source_condition_1:mean_power_w", + "source_condition_2:mean_power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 122380.96 +rationale = "Common-mode sensing/controllers: recovery and error 62.3%; output bias 6.92%; power 20.8%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +error_v = 0.124615384617 +peak_error_v = 0.124615384615 +recovery_down_v = 0.124615384615 +recovery_up_v = 0.124615384615 +recovery_zero_v = 0.124615384615 +output_v = 0.069230769231 +mean_power_w = 0.103846153846 +power_w = 0.103846153846 + +[task.evaluation.pre_layout] +source_report_sha256 = "ca92a36735b6c9519507a649e9af3be05f4216c3e85d9fe6d7285957f000ca75" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 3.3 +diff_v = 0 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +error_v = "V" +power_w = "W" +recovery_up_v = "V" +recovery_down_v = "V" +recovery_zero_v = "V" +peak_error_v = "V" +mean_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "b0e54435cc82b9ebbaa50d8ff766335ff3fd909a83374fd4341744f9d538b665" +dut = "ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.error_v] +value = 0.002103636318471 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] +value = 0.0001628409 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.652103636298 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.peak_error_v] +value = 0.2011193 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001628462505231 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_down_v] +value = 0.002431036 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_up_v] +value = 0.001780462 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_zero_v] +value = 0.002103118 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.3 +diff_v = 0.1 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +error_v = "V" +power_w = "W" +recovery_up_v = "V" +recovery_down_v = "V" +recovery_zero_v = "V" +peak_error_v = "V" +mean_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "b0e54435cc82b9ebbaa50d8ff766335ff3fd909a83374fd4341744f9d538b665" +dut = "ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.error_v] +value = 0.002103636318594 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] +value = 0.0001628409 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 1.652103636298 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.peak_error_v] +value = 0.2011193 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0001628462505231 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_down_v] +value = 0.002431036 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_up_v] +value = 0.001780462 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_zero_v] +value = 0.002103118 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 +diff_v = 0.2 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +error_v = "V" +power_w = "W" +recovery_up_v = "V" +recovery_down_v = "V" +recovery_zero_v = "V" +peak_error_v = "V" +mean_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "b0e54435cc82b9ebbaa50d8ff766335ff3fd909a83374fd4341744f9d538b665" +dut = "ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.error_v] +value = 0.002103636318715 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] +value = 0.0001628409 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 1.652103636298 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.peak_error_v] +value = 0.2011193 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.0001628462505231 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_down_v] +value = 0.002431036 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_up_v] +value = 0.001780462 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_zero_v] +value = 0.002103118 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_003_5t_nmos_input" + +[qualification] +reference = "reference/cmfb_003_5t_nmos_input.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Controls common-mode voltage using an NMOS-input core and segmented resistors." diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..8569db9ebc53354a278c5dabb3ee7f05caf40374 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice @@ -0,0 +1,52 @@ +* Derived from analog-db cmfb_003_5t_nmos_input, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: Each sense arm uses twenty series 250-kohm physical poly segments. +.subckt cmfb_003_5t_nmos_input vinp vinn vcmfb vref vdd vss +XRMN_0 vinn RMN_1 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_1 RMN_1 RMN_2 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_2 RMN_2 RMN_3 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_3 RMN_3 RMN_4 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_4 RMN_4 RMN_5 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_5 RMN_5 RMN_6 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_6 RMN_6 RMN_7 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_7 RMN_7 RMN_8 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_8 RMN_8 RMN_9 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_9 RMN_9 RMN_10 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_10 RMN_10 RMN_11 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_11 RMN_11 RMN_12 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_12 RMN_12 RMN_13 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_13 RMN_13 RMN_14 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_14 RMN_14 RMN_15 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_15 RMN_15 RMN_16 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_16 RMN_16 RMN_17 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_17 RMN_17 RMN_18 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_18 RMN_18 RMN_19 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMN_19 RMN_19 cm_sense vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_0 cm_sense RMP_1 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_1 RMP_1 RMP_2 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_2 RMP_2 RMP_3 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_3 RMP_3 RMP_4 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_4 RMP_4 RMP_5 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_5 RMP_5 RMP_6 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_6 RMP_6 RMP_7 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_7 RMP_7 RMP_8 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_8 RMP_8 RMP_9 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_9 RMP_9 RMP_10 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_10 RMP_10 RMP_11 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_11 RMP_11 RMP_12 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_12 RMP_12 RMP_13 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_13 RMP_13 RMP_14 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_14 RMP_14 RMP_15 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_15 RMP_15 RMP_16 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_16 RMP_16 RMP_17 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_17 RMP_17 RMP_18 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_18 RMP_18 RMP_19 vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XRMP_19 RMP_19 vinp vss ppolyf_u_1k r_width=2u r_length=500u m=1 +XM1 mirr cm_sense ntail vss nfet_03v3 w=10u l=1u m=1 +XM2 vcmfb vref ntail vss nfet_03v3 w=10u l=1u m=1 +XM3 mirr mirr vdd vdd pfet_03v3 w=42u l=2u m=1 +XM4 vcmfb mirr vdd vdd pfet_03v3 w=42u l=2u m=1 +XM5 bias bias vss vss nfet_03v3 w=6.5u l=1u m=1 +XM6 bias bias vdd vdd pfet_03v3 w=1u l=2u m=1 +XM8 ntail bias vss vss nfet_03v3 w=13u l=1u m=1 +.ends cmfb_003_5t_nmos_input diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..86027e0f47850547ee93e920e561cf55e76c646d --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/schematic.svg @@ -0,0 +1 @@ +cmfb_003_5t_nmos_input{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.cmfb_003_5t_nmos_input", "netlist_sha256": "ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a", "project_sha256": "4c5e11588439e01fc38d8e48423634afd77fc98f1bd33de80bba7f28c838eee1", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["cmfb_003_5t_nmos_input", "Bank1_20series_ppolyf_u_1k", "Bank2_20series_ppolyf_u_1k"], "banks": [{"name": "Bank1_20series_ppolyf_u_1k", "count": 20, "model": "ppolyf_u_1k", "kind": "series", "members": ["XRMN_0", "XRMN_1", "XRMN_2", "XRMN_3", "XRMN_4", "XRMN_5", "XRMN_6", "XRMN_7", "XRMN_8", "XRMN_9", "XRMN_10", "XRMN_11", "XRMN_12", "XRMN_13", "XRMN_14", "XRMN_15", "XRMN_16", "XRMN_17", "XRMN_18", "XRMN_19"]}, {"name": "Bank2_20series_ppolyf_u_1k", "count": 20, "model": "ppolyf_u_1k", "kind": "series", "members": ["XRMP_0", "XRMP_1", "XRMP_2", "XRMP_3", "XRMP_4", "XRMP_5", "XRMP_6", "XRMP_7", "XRMP_8", "XRMP_9", "XRMP_10", "XRMP_11", "XRMP_12", "XRMP_13", "XRMP_14", "XRMP_15", "XRMP_16", "XRMP_17", "XRMP_18", "XRMP_19"]}], "source_netlist": "tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice", "known_editor_diagnostics": {"ERC_ILLEGAL_PIN_NAME": 40}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}cmfb_003_5t_nmos_inputvinncm_sensevsscm_sensevinpvssvddvssbiasvinncm_sensevsscm_sensevinpvsscm_sensevrefbiasvssvddvcmfbntailmirrvinpvinnvcmfbvrefvddvsscmfb_003_5t_nmos_inputgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Common-mode error amplifierXM342/2XM442/2XM110/1XM210/1XM813/1P bulk → vddN bulk → vss02 Self-biased referenceXM61/2XM56.5/1P bulk → vddN bulk → vss03 Negative-output sensing stringXBANK1Bank1_20series_ppolyf_u_1k04 Positive-output sensing stringXBANK2Bank2_20series_ppolyf_u_1kModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..478bd8bb036cca95fc25933cbf84f704d7fa5278 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/testbench.spice @@ -0,0 +1,40 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 {supply_v} +VREF ref 0 1.65 +* External stable first-order inverting common-mode plant, not a DUT device. +EPL plant 0 ctl 0 -1 +VOFF drive plant 3.3 +RP drive cm 100k +CP cm 0 100n +VD disturb 0 PWL(0 0 10m 0 10.01m 0.1 30m 0.1 30.01m -0.1 50m -0.1 50.01m 0 70m 0) +EP inp cm disturb 0 1 +VOP op inp {diff_v} +VON on inp {-diff_v} +CL ctl 0 10p +XD op on ctl ref vdd 0 cmfb_003_5t_nmos_input +.save v(ctl) v(inp) v(ref) v(vdd) i(vdd) v(cm) v(op) v(on) v(disturb) +.control +set noaskquit +set numdgt=12 +op +let output_v=v(ctl) +let error_v=abs(v(inp)-v(ref)) +let power_w=-v(vdd)*i(vdd) +print output_v error_v power_w +write op.raw all +tran 10u 70m +let err=abs(v(inp)-v(ref)) +let power=-v(vdd)*i(vdd) +meas tran recovery_up_v max err from=25m to=29m +meas tran recovery_down_v max err from=45m to=49m +meas tran recovery_zero_v max err from=65m to=69m +meas tran peak_error_v max err from=10m to=70m +meas tran mean_power_w avg power from=0 to=70m +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/problem.md b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..b1f7ddbcb3ea0852274814816035f1ea8336f7f3 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/problem.md @@ -0,0 +1,94 @@ +# Segmented-Resistor NMOS Common-Mode Controller Layout Task + +## Objective + +Implement `cmfb_003_5t_nmos_input` in gf180mcuD and submit self-contained GDS. Seven MOS devices form an NMOS-input common-mode error amplifier and self-bias network. Each ideal 5 Mohm sense arm is implemented as twenty series GF180 ppolyf_u_1k segments, each 2 um wide and 500 um long: 5,000 squares per arm. The segmentation, substrate terminals and intermediate nodes are part of the maintained circuit. The independent witness uses compact rows connected by metal; it retains both complete resistance chains. + +## Inputs and Interface + +`materials/circuit.spice` is the authoritative physical circuit. The same netlist is used for source calibration. `materials/testbench.spice` defines measurements, and this problem is the description input. +Ordered ports: `vinp vinn vcmfb vref vdd vss`. In order: Positive sensed output, negative sensed output, control output, common-mode reference, supply, and return. + +Preserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT. + +## Operating Conditions + +Temperature is 27 C. Typical GF180 3.3 V MOS and high-resistance poly models, statistical variation disabled. The substrate is not a distributed silicon resistance network. + +VDD = 3.3 V; VSS = 0 V; VREF = 1.65 V. The external first-order inverting plant has drive = 3.3 V - V(vcmfb), followed by 100 kohm and 100 nF to common mode. V(vinp/vinn) = plant output + disturbance +/- d, where d = 0, 0.1 and 0.2 V in separate conditions. Disturbance is 0 through 10 ms, +0.1 V at 10.01 ms through 30 ms, -0.1 V at 30.01 ms through 50 ms, and 0 at 50.01 ms through 70 ms. A 10 pF external capacitor loads vcmfb. Transient output/max step is 10 us. This plant is test apparatus, not an internal ideal servo or a claimed transistor amplifier. Recovery windows are 25–29 ms and 45–49 ms for the positive/negative disturbances; error is measured at the average sensed inputs against VREF. Controller power excludes the external plant. + +## Physical Requirements + +Top cell `cmfb_003_5t_nmos_input`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, GF180 variant-D DRC including antenna, with chip-level density and seal-ring closure outside scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 1100 by 280 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers. + +Every scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. Qualification covers recovery with this specified external plant, not stability with arbitrary amplifiers. The long physical sense chains retain candidate-derived parasitics. Startup, mismatch, noise, PVT and a complete differential amplifier are outside scope. Fabrication signoff is not claimed. + +## Electrical Requirements and Scoring + +All 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output/control voltage | V | target / target | 0 … 3.3 | 3.3 | +| `error_v` | Absolute DC sensed common-mode minus VREF | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `recovery_up_v` | Maximum absolute recovered error over the upward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `recovery_down_v` | Maximum absolute recovered error over the downward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `recovery_zero_v` | Maximum absolute sensed common-mode minus VREF over 65–69 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `peak_error_v` | Maximum absolute sensed common-mode minus VREF over 10–70 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the complete transient | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **122380.96 um2**. 47 expanded device instances; sum of device/contact envelopes 80826.5000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **6**; it is independent of +the reference-relative task score. + + +### Score weights + +Common-mode sensing/controllers: recovery and error 62.3%; output bias 6.92%; power 20.8%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `error_v` | 0.124615384617 | +| `peak_error_v` | 0.124615384615 | +| `recovery_down_v` | 0.124615384615 | +| `recovery_up_v` | 0.124615384615 | +| `recovery_zero_v` | 0.124615384615 | +| `output_v` | 0.069230769231 | +| `mean_power_w` | 0.103846153846 | +| `power_w` | 0.103846153846 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/reference/cmfb_003_5t_nmos_input.gds b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/reference/cmfb_003_5t_nmos_input.gds new file mode 100644 index 0000000000000000000000000000000000000000..a8d1271aa155e664af84b1aaae1e04eb6db903b6 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/reference/cmfb_003_5t_nmos_input.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2231cc449499dd1950deab3347613907727685bcdb2c048cd8b8adde87b7ef90 +size 307578 diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..f1cabb70b8e70fe6a86ee963471389f00be5475a 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+[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vinp", + "vinn", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 1e-12 + +[task.evaluation.jobs.parameters.measurements] +rising_input = "V" +falling_input = "V" +hysteresis_v = "V" +mean_power_w = "W" +low_v = "V" +high_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 5e-12 + +[task.evaluation.jobs.parameters.measurements] +rising_input = "V" +falling_input = "V" +hysteresis_v = "V" +mean_power_w = "W" +low_v = "V" +high_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +load_f = 1e-11 + +[task.evaluation.jobs.parameters.measurements] +rising_input = "V" +falling_input = "V" +hysteresis_v = "V" +mean_power_w = "W" +low_v = "V" +high_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "rising_input" +category = "performance" +observations = [ + "condition_0:rising_input", + "condition_1:rising_input", + "condition_2:rising_input", +] +unit = "V" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:rising_input", + "source_condition_1:rising_input", + "source_condition_2:rising_input", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "falling_input" +category = "performance" +observations = [ + "condition_0:falling_input", + "condition_1:falling_input", + "condition_2:falling_input", +] +unit = "V" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:falling_input", + "source_condition_1:falling_input", + "source_condition_2:falling_input", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "hysteresis_v" +category = "performance" +observations = [ + "condition_0:hysteresis_v", + "condition_1:hysteresis_v", + "condition_2:hysteresis_v", +] +unit = "V" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:hysteresis_v", + "source_condition_1:hysteresis_v", + "source_condition_2:hysteresis_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "mean_power_w" +category = "performance" +observations = [ + "condition_0:mean_power_w", + "condition_1:mean_power_w", + "condition_2:mean_power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:mean_power_w", + "source_condition_1:mean_power_w", + "source_condition_2:mean_power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "low_v" +category = "performance" +observations = [ + "condition_0:low_v", + "condition_1:low_v", + "condition_2:low_v", +] +unit = "V" +direction = "minimize" +aggregation = "max" +lower = 0 +upper = 0.1 + +[[task.evaluation.metrics]] +id = "high_v" +category = "performance" +observations = [ + "condition_0:high_v", + "condition_1:high_v", + "condition_2:high_v", +] +unit = "V" +direction = "target" +aggregation = "max" +lower = 3.2 +upper = 3.31 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 8386.58 +rationale = "Hysteretic comparator: switching thresholds 49.5%; hysteresis 27%; supply power 13.5%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +falling_input = 0.2475 +rising_input = 0.2475 +hysteresis_v = 0.27 +mean_power_w = 0.135 + +[task.evaluation.pre_layout] +source_report_sha256 = "35002328c76574f04d7f3553817fcf70ef27596d3d719f7fa2ae47f1f3a648f1" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +load_f = 1e-12 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +rising_input = "V" +falling_input = "V" +hysteresis_v = "V" +mean_power_w = "W" +low_v = "V" +high_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "8929bab9abc5e6051a5b8075a2ac1d3d60fdadecec8b3cdec6bb4d0bf93f4bdc" +dut = "cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.falling_input] +value = 1.681959 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.hysteresis_v] +value = 0.012438 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] +value = 2.86915e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] +value = 0.0005599238 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.rising_input] +value = 1.694397 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +load_f = 5e-12 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +rising_input = "V" +falling_input = "V" +hysteresis_v = "V" +mean_power_w = "W" +low_v = "V" +high_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "8929bab9abc5e6051a5b8075a2ac1d3d60fdadecec8b3cdec6bb4d0bf93f4bdc" +dut = "cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.falling_input] +value = 1.682001 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.high_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.hysteresis_v] +value = 0.012372 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.low_v] +value = 2.86915e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] +value = 0.0005595666 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.rising_input] +value = 1.694373 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +load_f = 1e-11 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +rising_input = "V" +falling_input = "V" +hysteresis_v = "V" +mean_power_w = "W" +low_v = "V" +high_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "8929bab9abc5e6051a5b8075a2ac1d3d60fdadecec8b3cdec6bb4d0bf93f4bdc" +dut = "cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.falling_input] +value = 1.682 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.high_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.hysteresis_v] +value = 0.012397 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.low_v] +value = 2.869148e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] +value = 0.0005597131 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.rising_input] +value = 1.694397 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_001_hyst_diffpair" + +[qualification] +reference = "reference/cmp_001_hyst_diffpair.gds" + +[presentation] +category = "Mixed-signal" +summary = "Produces distinct rising and falling switching thresholds through resistive hysteresis." diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..f7ec48a383911454f3a3c701d7ac7b0f9e14a135 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice @@ -0,0 +1,20 @@ +* Derived from analog-db cmp_001_hyst_diffpair, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: physical high-resistance poly feedback and tail resistors. +.subckt cmp_001_hyst_diffpair vdd vout vinp vinn vss +XRHN n1 hn vss ppolyf_u_1k r_width=2u r_length=600u m=1 +XRHP n1 hp vss ppolyf_u_1k r_width=2u r_length=600u m=1 +XRT tail vss vss ppolyf_u_1k r_width=2u r_length=12u m=1 +XMB1N b1 n1 vss vss nfet_03v3 w=2u l=0.28u m=1 +XMB1P b1 n1 vdd vdd pfet_03v3 w=5u l=0.28u m=1 +XMB2N b2 b1 vss vss nfet_03v3 w=2u l=0.28u m=2 +XMB2P b2 b1 vdd vdd pfet_03v3 w=5u l=0.28u m=2 +XMB3N vout b2 vss vss nfet_03v3 w=2u l=0.28u m=4 +XMB3P vout b2 vdd vdd pfet_03v3 w=5u l=0.28u m=4 +XMHN hn vout vss vss nfet_03v3 w=1u l=0.3u m=1 +XMHP hp vout vdd vdd pfet_03v3 w=1u l=0.3u m=1 +XMIN n2 vinn tail vss nfet_03v3 w=10u l=0.3u m=2 +XMIP n1 vinp tail vss nfet_03v3 w=10u l=0.3u m=2 +XMPLD n2 n2 vdd vdd pfet_03v3 w=10u l=0.3u m=4 +XMPLM n1 n2 vdd vdd pfet_03v3 w=10u l=0.3u m=4 +.ends cmp_001_hyst_diffpair diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..61a290bf32b699a9094c0a9c215e6a7c16bcfa90 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/schematic.svg @@ -0,0 +1 @@ +cmp_001_hyst_diffpair{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.cmp_001_hyst_diffpair", "netlist_sha256": "cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd", "project_sha256": "25222b67df6220e8063972dac56ff734fe5eac70700bdae82288a66e8c156eb9", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["cmp_001_hyst_diffpair"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice", "known_editor_diagnostics": {"ERC_ILLEGAL_PIN_NAME": 3}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}cmp_001_hyst_diffpairn1voutvddvssb1b2vddvsshpvoutn1hnvinnvinpvssvddn1tailn2vddvoutvinpvinnvsscmp_001_hyst_diffpairgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Differential input stageXMPLD10/0.3 ×4XMPLM10/0.3 ×4XMIN10/0.3 ×2XMIP10/0.3 ×2XRTW/L 2/12P bulk → vddN bulk → vssR substrate → vss02 Three-stage output bufferXMB1P5/0.28XMB2P5/0.28 ×2XMB3P5/0.28 ×4XMB1N2/0.28XMB2N2/0.28 ×2XMB3N2/0.28 ×4P bulk → vddN bulk → vss03 Hysteresis feedbackXMHP1/0.3XRHPW/L 2/600XRHNW/L 2/600XMHN1/0.3P bulk → vddR substrate → vssN bulk → vssModels: ppolyf_u_1k · nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..3a0a6ba4167a03fc07ea4409fc34f13e6c701092 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/testbench.spice @@ -0,0 +1,25 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 3.3 +VP inp 0 PWL(0 1.45 0.1m 1.45 1.1m 1.85 1.2m 1.85 2.2m 1.45 2.3m 1.45) +VN inn 0 1.65 +CL out 0 {load_f} +XD vdd out inp inn 0 cmp_001_hyst_diffpair +.control +set numdgt=12 +tran 0.2u 2.3m +meas tran rising_input find v(inp) when v(out)=1.65 rise=1 +meas tran falling_input find v(inp) when v(out)=1.65 fall=1 +let hysteresis_v=rising_input-falling_input +let power=-v(vdd)*i(vdd) +meas tran mean_power_w avg power from=0 to=2.3m +meas tran low_v max v(out) from=0.02m to=0.08m +meas tran high_v min v(out) from=1.12m to=1.18m +print hysteresis_v +write transient.raw time v(inp) v(out) v(vdd) i(vdd) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/problem.md b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..efafa1ab8f100cb1cafdda8c99ce555a44aba4db --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/problem.md @@ -0,0 +1,118 @@ +# Resistive-Feedback Hysteretic Comparator Layout Task + +## Objective + +Implement the fixed `cmp_001_hyst_diffpair` circuit in GF180MCU D and submit self-contained GDS. +A differential input stage, resistive positive feedback and three output inverters form a hysteretic comparator. Twelve MOS entries expand to 28 physical instances. The physical ppolyf_u_1k resistors are width 2 um: two 600 um feedback devices (300 squares) and one 12 um tail device (6 squares). MOS sizes and multiplicities are retained; ideal resistors become substrate-connected process devices. + +## Inputs and Interface + +`materials/circuit.spice` is authoritative for LVS and source calibration; +`materials/testbench.spice` defines every electrical measurement. This problem +is the description input. Ordered ports: `vdd vout vinp vinn vss`. +In order, these are: Supply, digital output, swept positive input, fixed negative input, and return. + +Preserve the netlist's device connectivity, dimensions, multiplicities and body +connections. Provide physical well/substrate contacts to the declared rails. +Placement, routing, splitting and source/drain interchange are permitted only +where accepted by the declared LVS equivalence rules. No common-centroid or +statistical matching requirement is scored. Ideal external stimulus, bias and +load devices remain testbench apparatus and must not be placed inside the DUT. + +## Operating Conditions + +Use the typical GF180 3.3 V MOS models and physical poly models where present, +with statistical variation disabled. Unless swept explicitly, temperature is 27 C. +VDD = 3.3 V, VSS = 0 V, VINN = 1.65 V. VINP stays at 1.45 V through 0.1 ms, ramps to 1.85 V at 1.1 ms, holds through 1.2 ms, ramps back to 1.45 V at 2.2 ms, then holds through 2.3 ms. Each ramp magnitude is 0.4 V/ms. Evaluate external loads of 1, 5 and 10 pF separately with a 0.2 us transient output step. The transient starts from its DC operating point. + +## Physical Requirements + +Submit top cell `cmp_001_hyst_diffpair` with every named electrical port, resolved hierarchy +and a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna, +strict named-port LVS and geometry must pass, without DRC waivers. Chip-level +density and seal-ring closure are outside this standalone-block scope. + +The functional bounding box must fit within 1300 by 200 um. Area includes all +process device and routing drawing layers listed in runtime constraints: +wells, implants, active, poly, contacts, metals/vias and passive/device markers. +Annotation and pin-purpose shapes are excluded; all functional routing must use +drawing layers. The complete layer list is frozen in `/protocol/task.json`. + +The judge independently extracts distributed wiring resistance and capacitance +from the submitted GDS, retaining candidate-derived MOS/passive geometry and +external body connections. Every scored simulation consumes that extracted DUT. +This model boundary does not include a distributed silicon substrate network. +Thresholds include this finite ramp rate and output load. Offset is intentional and is not zero-centered about VINN. Metastability, fast decision delay, startup, noise, statistical offset, PVT and EM are outside scope. Manufacturing signoff is not claimed. + +## Electrical Requirements and Scoring + +All three operating conditions must complete and every observation must be finite +and meet its inclusive band. Aggregation cannot hide a failing condition; +missing crossings or incomplete extraction/simulation cannot establish success. +Saved waveforms provide the inputs for independently reconstructing observations. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `rising_input` | Interpolated VINP at the first rising VOUT = 1.65 V crossing | V | target / target | 0 … 3.3 | 3.3 | +| `falling_input` | Interpolated VINP at the first falling VOUT = 1.65 V crossing | V | target / target | 0 … 3.3 | 3.3 | +| `hysteresis_v` | Rising-input threshold minus falling-input threshold | V | target / target | 0 … 3.3 | 3.3 | +| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the full 0–2.3 ms transient | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `low_v` | Maximum VOUT over 0.02–0.08 ms | V | functional check | 0 … 0.1 | — | +| `high_v` | Minimum VOUT over 1.12–1.18 ms | V | functional check | 3.2 … 3.31 | — | + +Area reference: **8386.58 um2**. 31 expanded device instances; sum of device/contact envelopes 5392.5600 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **5**; it is independent of +the reference-relative task score. + + +### Score weights + +Hysteretic comparator: switching thresholds 49.5%; hysteresis 27%; supply power 13.5%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `falling_input` | 0.247500000000 | +| `rising_input` | 0.247500000000 | +| `hysteresis_v` | 0.270000000000 | +| `mean_power_w` | 0.135000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 resources listed in `/protocol/resources.json`. +KLayout checks the layout, Magic extracts RC and ngspice simulates the circuit. +`/protocol/task.json` provides frozen constraints and evaluation requirements; +`/protocol/harness.json` describes the harness. If `process-feedback` is +exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/reference/cmp_001_hyst_diffpair.gds b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/reference/cmp_001_hyst_diffpair.gds new file mode 100644 index 0000000000000000000000000000000000000000..08a7f044ab76ef1a5d1d9ed78f231eebc7438515 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/reference/cmp_001_hyst_diffpair.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7afff35caa5ea847d445950d7d0e6336b255a69806944f3c45bf101cb6e29c22 +size 461354 diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..2d37a9a2039e46207f08038f80ad9c058e5304c0 --- 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+stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "voutp", + "voutn", + "vinp", + "vinn", + "clk", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +polarity = 1 +common_v = 1.2 + +[task.evaluation.jobs.parameters.measurements] +delay_s = "s" +slew_s = "s" +power_w = "W" +decision_v = "V" +reset_p_v = "V" +reset_n_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = 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"input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +polarity = -1 +common_v = 1.65 + +[task.evaluation.jobs.parameters.measurements] +delay_s = "s" +slew_s = "s" +power_w = "W" +decision_v = "V" +reset_p_v = "V" +reset_n_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "delay_s" +unit = "s" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +lower = 0 +category = "performance" +observations = [ + "condition_0:delay_s", + "condition_1:delay_s", + "condition_2:delay_s", + "condition_3:delay_s", +] +baseline = [ + "source_condition_0:delay_s", + "source_condition_1:delay_s", + "source_condition_2:delay_s", + "source_condition_3:delay_s", +] + +[[task.evaluation.metrics]] +id = "slew_s" +unit = "s" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +lower = 0 +category = "performance" +observations = [ + "condition_0:slew_s", + "condition_1:slew_s", + "condition_2:slew_s", + "condition_3:slew_s", +] +baseline = [ + "source_condition_0:slew_s", + "source_condition_1:slew_s", + "source_condition_2:slew_s", + "source_condition_3:slew_s", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", + "condition_3:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", + "source_condition_3:power_w", +] + +[[task.evaluation.metrics]] +id = "decision_v" +unit = "V" +dimension = "bias" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 3.3 +lower = 1.65 +upper = 3.3 +category = "performance" +observations = [ + "condition_0:decision_v", + "condition_1:decision_v", + "condition_2:decision_v", + "condition_3:decision_v", +] +baseline = [ + "source_condition_0:decision_v", + "source_condition_1:decision_v", + "source_condition_2:decision_v", + "source_condition_3:decision_v", +] + +[[task.evaluation.metrics]] +id = "reset_p_v" +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0 +upper = 1.65 +category = "performance" +observations = [ + "condition_0:reset_p_v", + "condition_1:reset_p_v", + "condition_2:reset_p_v", + "condition_3:reset_p_v", +] + +[[task.evaluation.metrics]] +id = "reset_n_v" +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0 +upper = 1.65 +category = "performance" +observations = [ + "condition_0:reset_n_v", + "condition_1:reset_n_v", + "condition_2:reset_n_v", + "condition_3:reset_n_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 490.86 +rationale = "Clocked comparators: decision delay 61.4%; output transition 8.18%; decision amplitude 4.09%; supply power 16.4%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +delay_s = 0.613636363637 +slew_s = 0.081818181818 +decision_v = 0.040909090909 +power_w = 0.163636363636 + +[task.evaluation.pre_layout] +source_report_sha256 = "6a19d20fecef014057c36e8103fbdc04d82bce298d769e60479d0368557069c2" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +polarity = 1 +common_v = 1.2 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +delay_s = "s" +slew_s = "s" +power_w = "W" +decision_v = "V" +reset_p_v = "V" +reset_n_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "f23c6b7204b8c87a271e46c6515e8ade911c422c25da0ff6afd3b4680c5c8740" +dut = "36d51c97acf4f0c0c6c65fedab51f34d64af9aaa291f8bb71964cd5163b9739b" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.decision_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.delay_s] +value = 4.099738e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 6.995383e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.reset_n_v] +value = 3.68746e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.reset_p_v] +value = 3.692917e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.slew_s] +value = 2.98826e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +polarity = -1 +common_v = 1.2 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +delay_s = "s" +slew_s = "s" +power_w = "W" +decision_v = "V" +reset_p_v = "V" +reset_n_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "f23c6b7204b8c87a271e46c6515e8ade911c422c25da0ff6afd3b4680c5c8740" +dut = "36d51c97acf4f0c0c6c65fedab51f34d64af9aaa291f8bb71964cd5163b9739b" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.decision_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.delay_s] +value = 4.099738e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 6.995383e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.reset_n_v] +value = 3.692917e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.reset_p_v] +value = 3.68746e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.slew_s] +value = 2.98826e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +polarity = 1 +common_v = 1.65 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +delay_s = "s" +slew_s = "s" +power_w = "W" +decision_v = "V" +reset_p_v = "V" +reset_n_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "f23c6b7204b8c87a271e46c6515e8ade911c422c25da0ff6afd3b4680c5c8740" +dut = "36d51c97acf4f0c0c6c65fedab51f34d64af9aaa291f8bb71964cd5163b9739b" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.decision_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.delay_s] +value = 3.284388e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 7.492169e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.reset_n_v] +value = 3.68784e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.reset_p_v] +value = 3.693198e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.slew_s] +value = 2.837858e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +polarity = -1 +common_v = 1.65 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +delay_s = "s" +slew_s = "s" +power_w = "W" +decision_v = "V" +reset_p_v = "V" +reset_n_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "f23c6b7204b8c87a271e46c6515e8ade911c422c25da0ff6afd3b4680c5c8740" +dut = "36d51c97acf4f0c0c6c65fedab51f34d64af9aaa291f8bb71964cd5163b9739b" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.decision_v] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.delay_s] +value = 3.284388e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 7.492169e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.reset_n_v] +value = 3.693198e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.reset_p_v] +value = 3.68784e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.slew_s] +value = 2.837858e-10 +unit = "s" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_002_strongarm" + +[qualification] +reference = "reference/cmp_002_strongarm.gds" + +[presentation] +category = "Mixed-signal" +summary = "Makes clocked differential decisions with a StrongARM regenerative latch." diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..5f06994b3a35fa0af1a10ca0985f25a5ac0379cb --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl @@ -0,0 +1,21 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt cmp_002_strongarm vdd voutp voutn vinp vinn clk vss +MMINN_0 sp vinn tail vss nfet_03v3 w=8u l=0.28u +MMINN_1 sp vinn tail vss nfet_03v3 w=8u l=0.28u +MMINP_0 sn vinp tail vss nfet_03v3 w=8u l=0.28u +MMINP_1 sn vinp tail vss nfet_03v3 w=8u l=0.28u +MMLEM_0 lm lp sn vss nfet_03v3 w=4u l=0.28u +MMLEP_0 lp lm sp vss nfet_03v3 w=4u l=0.28u +MMLUM_0 lm lp vdd vdd pfet_03v3 w=4u l=0.28u +MMLUP_0 lp lm vdd vdd pfet_03v3 w=4u l=0.28u +MMOBN1_0 voutp lm vss vss nfet_03v3 w=1.5u l=0.28u +MMOBN2_0 voutn lp vss vss nfet_03v3 w=1.5u l=0.28u +MMOBP1_0 voutp lm vdd vdd pfet_03v3 w=3u l=0.28u +MMOBP2_0 voutn lp vdd vdd pfet_03v3 w=3u l=0.28u +MMPC1_0 sp clk vdd vdd pfet_03v3 w=2u l=0.28u +MMPC2_0 sn clk vdd vdd pfet_03v3 w=2u l=0.28u +MMPC3_0 lp clk vdd vdd pfet_03v3 w=2u l=0.28u +MMPC4_0 lm clk vdd vdd pfet_03v3 w=2u l=0.28u +MMTAIL_0 tail clk vss vss nfet_03v3 w=4u l=0.28u +.ends cmp_002_strongarm diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..f23ca0f14f766eef26d09e91797b42378623fae9 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.spice @@ -0,0 +1,21 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt cmp_002_strongarm vdd voutp voutn vinp vinn clk vss +XMINN_0 sp vinn tail vss nfet_03v3 w=8u l=0.28u +XMINN_1 sp vinn tail vss nfet_03v3 w=8u l=0.28u +XMINP_0 sn vinp tail vss nfet_03v3 w=8u l=0.28u +XMINP_1 sn vinp tail vss nfet_03v3 w=8u l=0.28u +XMLEM_0 lm lp sn vss nfet_03v3 w=4u l=0.28u +XMLEP_0 lp lm sp vss nfet_03v3 w=4u l=0.28u +XMLUM_0 lm lp vdd vdd pfet_03v3 w=4u l=0.28u +XMLUP_0 lp lm vdd vdd pfet_03v3 w=4u l=0.28u +XMOBN1_0 voutp lm vss vss nfet_03v3 w=1.5u l=0.28u +XMOBN2_0 voutn lp vss vss nfet_03v3 w=1.5u l=0.28u +XMOBP1_0 voutp lm vdd vdd pfet_03v3 w=3u l=0.28u +XMOBP2_0 voutn lp vdd vdd pfet_03v3 w=3u l=0.28u +XMPC1_0 sp clk vdd vdd pfet_03v3 w=2u l=0.28u +XMPC2_0 sn clk vdd vdd pfet_03v3 w=2u l=0.28u +XMPC3_0 lp clk vdd vdd pfet_03v3 w=2u l=0.28u +XMPC4_0 lm clk vdd vdd pfet_03v3 w=2u l=0.28u +XMTAIL_0 tail clk vss vss nfet_03v3 w=4u l=0.28u +.ends cmp_002_strongarm diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..0aa3901383a82de6e13141078c8880e034d19427 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/schematic.svg @@ -0,0 +1,2 @@ +cmp_002_strongarm{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.cmp_002_strongarm","source_netlist":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl","netlist_sha256":"5b80e3a40ab19415481d51b8e6b4e4bcf45c4517ccc5071aa1b342038c94e14c","project_sha256":"de714f123dfcbc95b393debeb243cb7baaf0c0f38bcf93f937f350484331f413","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"flat-cdl-project: independent source/project flattened device comparison, schema parse, symbol resolution and netlist export.","license":"licenses/gf180mcuD/analog-db/","sheets":["cmp_002_strongarm"],"banks":[],"limitations":["Structured labelled overview, not a manually composed functional schematic. Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cmp_002_strongarm"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/schematic/cmp_002_strongarm.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.cmp_002_strongarmvsssnlmlpvssspvsslmlpvddvddlmlpvddvddlmsplpvoutpvssvsslmvoutnvssvsstaillpvddvddvoutplmvddvddvoutnlpvddvddclkspvddvinnvddclksnvddvddclklpvddvddvssclklmclkvssvsstailvddvoutpvoutnspvinpvinnclkvsstailvinpvsstailsnvinpvinnvsstailsncmp_002_strongarmEqual net labels connect. All source devices and exact parameters are retained.MMINN_0nfet_03v3w=8u l=0.28uMMINN_1nfet_03v3w=8u l=0.28uMMINP_0nfet_03v3w=8u l=0.28uMMINP_1nfet_03v3w=8u l=0.28uMMLEM_0nfet_03v3w=4u l=0.28uMMLEP_0nfet_03v3w=4u l=0.28uMMLUM_0pfet_03v3w=4u l=0.28uMMLUP_0pfet_03v3w=4u l=0.28uMMOBN1_0nfet_03v3w=1.5u l=0.28uMMOBN2_0nfet_03v3w=1.5u l=0.28uMMOBP1_0pfet_03v3w=3u l=0.28uMMOBP2_0pfet_03v3w=3u l=0.28uMMPC1_0pfet_03v3w=2u l=0.28uMMPC2_0pfet_03v3w=2u l=0.28uMMPC3_0pfet_03v3w=2u l=0.28uMMPC4_0pfet_03v3w=2u l=0.28uMMTAIL_0nfet_03v3w=4u l=0.28u +Complete single-sheet circuit. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..21d8b7d2056e99712a8399331c858c86dc578eb5 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/testbench.spice @@ -0,0 +1,30 @@ +* StrongARM: positive and negative decisions, output slew and energy. +* SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VPOL pol 0 {polarity} +VDD vdd 0 3.3 +VCLK clk 0 PULSE(0 3.3 10n .1n .1n 10n 20n) +VP vinp 0 {common_v+polarity*.01} +VN vinn 0 {common_v-polarity*.01} +CP voutp 0 50f +CN voutn 0 50f +XDUT vdd voutp voutn vinp vinn clk 0 cmp_002_strongarm +.control +set noaskquit +set numdgt=12 +tran .01n 100n +let decision=v(pol)*(v(voutp)-v(voutn)) +meas tran decision_v find decision at=99n +let pwr=-3.3*i(vdd) +meas tran power_w avg pwr from=20n to=100n +meas tran delay_s trig v(clk) val=1.65 rise=1 td=80n targ decision val=1.65 rise=1 td=80n +meas tran slew_s trig decision val=.33 rise=1 td=80n targ decision val=2.97 rise=1 td=80n +meas tran reset_p_v find v(voutp) at=89n +meas tran reset_n_v find v(voutn) at=89n +write transient.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..690cde8156a785691d851b60771334cca295f35a --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md @@ -0,0 +1,111 @@ +# StrongARM Dynamic Comparator Layout Task + +## Objective + +Implement `cmp_002_strongarm` as a GF180MCU D layout. Fifteen upstream MOS instances implement the clocked StrongARM latch: differential input pair, clocked tail, cross-coupled regenerative devices, four precharge devices and two output inverters. The input pair multiplicities expand the physical circuit to seventeen devices. The maintained GF180 3.3 V binding uses the fixed sizing defaults and authored ties from the pinned accession. + + +## Inputs and Interface + +`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` +contains matching native simulator wrappers. `materials/testbench.spice` defines +all measurements. Ordered ports: `vdd voutp voutn vinp vinn clk vss`. + +`vdd/vss`: supply and return; `vinp/vinn`: differential inputs; `clk`: evaluate high, precharge low; `voutp/voutn`: buffered differential outputs. Positive input difference produces positive output difference. Supply, clock, input drivers and output loads are external apparatus. No offset-trim variant or proprietary process deck is included. + +## Operating Conditions + +Typical GF180 3.3 V MOS models at 3.3 V supply and 27 C, statistics disabled. Differential input is +20 or -20 mV at common modes 1.2 and 1.65 V, all four combinations. Each output has a 50 fF load. The 50 MHz clock first rises at 10 ns, uses 100 ps edges and 10 ns pulse width. Simulate to 100 ns at 10 ps requested steps; timing uses the fifth evaluation edge near 90 ns. + +## Physical Requirements + +GDS database unit 0.001 um, maximum 10 MiB, top cell `cmp_002_strongarm`. +Native standalone DRC covers geometry, connectivity, manufacturing grid, dummy +fill and antenna; chip-level density and seal-ring closure are excluded. +LVS must match all devices, parameters and named ports. Metal1 labels identify +ports. The functional bounding rectangle includes the device, well, implant, +contact, passive and complete routing layers enumerated in the runtime outline; +text annotations are excluded. Maximum outline is 5000 by 1000 um. + +Keep the 3.3 V models, 0.28 um channel length, fixed widths and multiplicities. Parallel equivalent fingers are permitted. All MOS dimensions lie on the native 5 nm construction grid. Body/well connections are explicit, with native guard-ring/tap geometry. The IHP binding has the same topology but different process sizing; it is not mixed into this GF180 task. + +Candidate-derived native Magic coupling capacitance and distributed wire +resistance feed post-layout simulation, with zero omission thresholds. +Physical MOS diffusion areas/perimeters come from the layout. Substrate/well +connections are ideal: distributed substrate resistance/noise and inductance +are not represented. Four nominal input-polarity/common-mode combinations, reset, decision delay/slew and average supply power. Coefficient 6 reflects regenerative decisions with clocked reset and buffered loads. Offset distribution, metastability statistics, noise, PVT and RF/EM are outside this declared scope. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition | Unit | Dimension | Normalization | +| --- | --- | --- | --- | --- | +| `delay_s` | Clock 1.65 V crossing to signed output difference 1.65 V, fifth rising edge | s | response | ratio | +| `slew_s` | Signed differential output rise from 0.33 to 2.97 V, fifth decision | s | response | ratio | +| `power_w` | Mean supply power over 20–100 ns | W | supply | ratio | +| `decision_v` | Input-polarity-adjusted output difference at 99 ns | V | bias | target | +| `reset_p_v` | Positive output at 89 ns in precharge | V | functional | unscored | +| `reset_n_v` | Negative output at 89 ns in precharge | V | functional | unscored | + +Signed decision must be 1.65–3.3 V; both reset outputs must be 0–1.65 V. Half-supply separates the required resolved/reset logic states, independent of any upstream speed target. Delay, slew and mean supply power must be nonnegative. Timing has no hard upper bound beyond the declared observation window; a missing crossing is an invalid measurement. +Every condition must complete; missing, nonfinite or wrong-unit observations +produce an evaluation error. Upstream advertised performance is not a +qualification requirement. + +Scored observations pair with independent source jobs using the identical +stimuli, parameters, models and backend. Target scales are 3.3 V; ratio floors +use 1 pW for power. These are normalization units, not allowed degradation. +Delay/slew ratios have no floor. + +Area anchor **490.86 um2** uses a 234.840000 um2 sum of expanded +`(W+2)*(L+2)` device/contact envelopes, a 50% routing allowance and 2 um outer +margin: `ceil(100*(1.5*sum+8*sqrt(sum)+16))/100`. It is independent of witness +area and is an engineering estimate, not a foundry minimum. Coefficient **6** +is independent of this score. + + +### Score weights + +Clocked comparators: decision delay 61.4%; output transition 8.18%; decision amplitude 4.09%; supply power 16.4%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `delay_s` | 0.613636363637 | +| `slew_s` | 0.081818181818 | +| `decision_v` | 0.040909090909 | +| `power_w` | 0.163636363636 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Read `/protocol/task.json`, `/protocol/resources.json` and +`/protocol/harness.json`. KLayout performs physical checks, Magic extracts the +candidate, and ngspice measures it. Use `process-feedback` if exposed. +Write `/workspace/output/final.gds`, then explicitly submit using +`python -I /protocol/submit.py`. diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/reference/cmp_002_strongarm.gds b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/reference/cmp_002_strongarm.gds new file mode 100644 index 0000000000000000000000000000000000000000..2c3780b015075fca4219fdd899fa61b181ef0669 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/reference/cmp_002_strongarm.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3a6c839c762a1ef7ac81f55c00f33f87bfbd5e07b906b424e6c40911831f9411 +size 105544 diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..c3b0363483680e327ef9bd81068468630a1ea21b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml @@ -0,0 +1,1118 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.dp_001_resistive_load" +title = "Resistively Loaded Differential Pair" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "0a9b8b8047ca604c4678f5f21881d8cedc806bb47888d1f0f8746e50ea9f0300" + +[[assets]] +path = "reference/dp_001_resistive_load.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "b622f4ddd721ad02fdc226fedd3ec0f979ab450b6a9000d49f81e9b4e1b80447" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_resistive_differential_pair" +coefficient = 4 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "dd31b11683d05938f2a7a36a144ef7220bc5d2c2ca7c406ee1ed0d6a0367e7fd" + +[task.inputs.netlist] +path = "materials/circuit.spice" +format = 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"candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "voutp", + "voutn", + "vinp", + "vinn", + "ibias", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transfer = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +common_v = 1.2 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +imbalance_v = "V" +linearity_v = "V" +slope = "V/V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transfer = "transfer.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transfer = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +common_v = 1.65 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +imbalance_v = "V" +linearity_v = "V" +slope = "V/V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transfer = "transfer.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transfer = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +common_v = 2.1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +imbalance_v = "V" +linearity_v = "V" +slope = "V/V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transfer = "transfer.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "imbalance_v" +category = "performance" +observations = [ + "condition_0:imbalance_v", + "condition_1:imbalance_v", + "condition_2:imbalance_v", +] +unit = "V" +dimension = "bias" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:imbalance_v", + "source_condition_1:imbalance_v", + "source_condition_2:imbalance_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "bias_v" +category = "performance" +observations = [ + "condition_0:bias_v", + "condition_1:bias_v", + "condition_2:bias_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:bias_v", + "source_condition_1:bias_v", + "source_condition_2:bias_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "gain_db" +category = "performance" +observations = [ + "condition_0:gain_db", + "condition_1:gain_db", + "condition_2:gain_db", +] +unit = "dB" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:gain_db", + "source_condition_1:gain_db", + "source_condition_2:gain_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "bandwidth_hz" +category = "performance" +observations = [ + "condition_0:bandwidth_hz", + "condition_1:bandwidth_hz", + "condition_2:bandwidth_hz", +] +unit = "Hz" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:bandwidth_hz", + "source_condition_1:bandwidth_hz", + "source_condition_2:bandwidth_hz", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "linearity_v" +category = "performance" +observations = [ + "condition_0:linearity_v", + "condition_1:linearity_v", + "condition_2:linearity_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:linearity_v", + "source_condition_1:linearity_v", + "source_condition_2:linearity_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "slope" +category = "performance" +observations = [ + "condition_0:slope", + "condition_1:slope", + "condition_2:slope", +] +unit = "V/V" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:slope", + "source_condition_1:slope", + "source_condition_2:slope", +] +normalization = "target" +scale = 5 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 925.98 +rationale = "Local gain stages: signal transfer 38.6%; bandwidth 11.6%; balance and linearity 19.3%; operating points 3.86%; power 11.6%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +gain_db = 0.193181818182 +slope = 0.193181818182 +bandwidth_hz = 0.115909090909 +imbalance_v = 0.096590909091 +linearity_v = 0.096590909091 +bias_v = 0.019318181818 +output_v = 0.019318181818 +power_w = 0.115909090909 + +[task.evaluation.pre_layout] +source_report_sha256 = "ff61107da81a033ee5ef8517acd0ecad0d937b9fb7ecc5e93f10dca981c360dc" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transfer = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 3.3 +common_v = 1.2 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +imbalance_v = "V" +linearity_v = "V" +slope = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transfer = "transfer.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "0844c14284ff4aad3556b61e8ac55981b1315ee1fccd639c56be004b6e23f5ef" +dut = "15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bandwidth_hz] +value = 7805460.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] +value = 0.6333537782254 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] +value = 10.89406 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.imbalance_v] +value = 5.506706202141e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.linearity_v] +value = 2.070048e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 3.088973349248 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001282494313576 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.slope] +value = 3.499673 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transfer = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.3 +common_v = 1.65 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +imbalance_v = "V" +linearity_v = "V" +slope = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transfer = "transfer.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "0844c14284ff4aad3556b61e8ac55981b1315ee1fccd639c56be004b6e23f5ef" +dut = "15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bandwidth_hz] +value = 7998418.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] +value = 0.6333537782254 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 11.98344 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.imbalance_v] +value = 5.684341886081e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.linearity_v] +value = 1.959777e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 3.044919055453 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.000141244731846 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.slope] +value = 3.968331 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transfer = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 +common_v = 2.1 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" +imbalance_v = "V" +linearity_v = "V" +slope = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transfer = "transfer.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "0844c14284ff4aad3556b61e8ac55981b1315ee1fccd639c56be004b6e23f5ef" +dut = "15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bandwidth_hz] +value = 8235992.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] +value = 0.6333537830947 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_db] +value = 12.94184 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.imbalance_v] +value = 6.350475700856e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.linearity_v] +value = 1.820086e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 2.994975342438 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.0001559773152614 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.slope] +value = 4.432213 +unit = "V/V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/dp_001_resistive_load" + +[qualification] +reference = "reference/dp_001_resistive_load.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Produces differential gain with resistive loads and a fixed input pair." diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..9b5c7c77e15ce2bec77ce53c457885c534328d0a --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice @@ -0,0 +1,11 @@ +* Derived from analog-db dp_001_resistive_load, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: physical 22-square high-resistance poly loads. +.subckt dp_001_resistive_load vdd voutp voutn vinp vinn ibias vss +XRN vdd voutn vss ppolyf_u_1k r_width=2u r_length=44u m=1 +XRP vdd voutp vss ppolyf_u_1k r_width=2u r_length=44u m=1 +XMN voutn vinn tail vss nfet_03v3 w=12u l=0.3u m=1 +XMP voutp vinp tail vss nfet_03v3 w=12u l=0.3u m=1 +XMR ibias ibias vss vss nfet_03v3 w=24u l=0.3u m=1 +XMT tail ibias vss vss nfet_03v3 w=24u l=0.3u m=1 +.ends dp_001_resistive_load diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..f5dbba54caf5b30c23f43b3b0a4817318452828e --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/schematic.svg @@ -0,0 +1 @@ +dp_001_resistive_load{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.dp_001_resistive_load", "netlist_sha256": "15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71", "project_sha256": "1ea4b90b6487b38d840868710e0accda3712a527bd934387e6bd12adb17f4036", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["dp_001_resistive_load"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice", "known_editor_diagnostics": {"ERC_ILLEGAL_PIN_NAME": 2}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}dp_001_resistive_loadvinpvinnibiasvssvddvoutpvoutntailvssibiasvoutpvoutnvinpvinnibiasvssvdddp_001_resistive_loadgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Resistively loaded differential pairXRPW/L 2/44XRNW/L 2/44XMP12/0.3XMN12/0.3XMT24/0.3R substrate → vssN bulk → vss02 Bias referenceXMR24/0.3N bulk → vssModels: ppolyf_u_1k · nfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..41d22477961378609458dd63fea0ab3ae0c617a0 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/testbench.spice @@ -0,0 +1,42 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 DC {supply_v} +IB vdd ibias 20u +VCM vcm 0 {common_v} +VD diff 0 DC 0 AC 1 +EP vinp vcm diff 0 0.5 +EN vinn vcm diff 0 -0.5 +CLP voutp 0 1p +CLN voutn 0 1p +XDUT vdd voutp voutn vinp vinn ibias 0 dp_001_resistive_load +.control +set noaskquit +set numdgt=12 +op +let output_v=(v(voutp)+v(voutn))/2 +let imbalance_v=abs(v(voutp)-v(voutn)) +let bias_v=v(ibias) +let power_w=-v(vdd)*i(vdd) +print output_v imbalance_v bias_v power_w +write op.raw v(vdd) v(voutp) v(voutn) v(ibias) i(vdd) +ac dec 100 1 1G +let gain_db=db(v(voutn)-v(voutp)) +meas ac gain_db find gain_db at=10 +let drop_db=db(v(voutn)-v(voutp))-gain_db +meas ac bandwidth_hz when drop_db=-3 fall=1 +write ac.raw frequency v(voutn) v(voutp) v(diff) +dc VD -0.0101 0.0101 0.0001 +let vdout=v(voutn)-v(voutp) +meas dc low_v find vdout at=-0.01 +meas dc high_v find vdout at=0.01 +let slope=(high_v-low_v)/0.02 +let error_v=abs(vdout-(low_v+slope*(v(diff)+0.01))) +meas dc linearity_v max error_v from=-0.01 to=0.01 +print slope +write transfer.raw v(diff) v(voutn) v(voutp) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/problem.md b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..440da056280df5afc4f98b5e3412b7988ad489d1 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/problem.md @@ -0,0 +1,128 @@ +# Resistively Loaded Differential Pair Layout Task + +## Objective + +Implement the fixed `dp_001_resistive_load` circuit in GF180MCU D and submit self-contained GDS. +Four NMOS devices form a differential input pair and tail-current mirror. Two physical GF180 ppolyf_u_1k loads each have width 2 um and length 44 um (22 squares, nominally 22 kohm). MOS dimensions and the resistor ratio follow the fixed binding; the ideal source resistors become process devices with substrate terminals at VSS. + +## Inputs and Interface + +`materials/circuit.spice` is authoritative for LVS and source calibration; +`materials/testbench.spice` defines every electrical measurement. This problem +is the description input. Ordered ports: `vdd voutp voutn vinp vinn ibias vss`. +In order, these are: Supply, output on the vinp branch, output on the vinn branch, positive input, negative input, NMOS reference-current input, and return. + +Preserve the netlist's device connectivity, dimensions, multiplicities and body +connections. Provide physical well/substrate contacts to the declared rails. +Placement, routing, splitting and source/drain interchange are permitted only +where accepted by the declared LVS equivalence rules. No common-centroid or +statistical matching requirement is scored. Ideal external stimulus, bias and +load devices remain testbench apparatus and must not be placed inside the DUT. + +## Operating Conditions + +Use the typical GF180 3.3 V MOS models and physical poly models where present, +with statistical variation disabled. Unless swept explicitly, temperature is 27 C. +VDD = 3.3 V, VSS = 0 V; 20 uA from VDD into ibias; input common mode = 1.2, 1.65 and 2.1 V; external 1 pF on each output. The input differential signal is split +0.5/-0.5 around common mode. AC differential amplitude is 1 V. DC transfer sweeps differential input from -10.1 to +10.1 mV in 0.1 mV increments; requirements use only -10 to +10 mV. Output differential voltage is V(voutn)-V(voutp). + +AC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is +V(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp) +for unit differential excitation; the OTA transfer is defined above. + +## Physical Requirements + +Submit top cell `dp_001_resistive_load` with every named electrical port, resolved hierarchy +and a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna, +strict named-port LVS and geometry must pass, without DRC waivers. Chip-level +density and seal-ring closure are outside this standalone-block scope. + +The functional bounding box must fit within 160 by 160 um. Area includes all +process device and routing drawing layers listed in runtime constraints: +wells, implants, active, poly, contacts, metals/vias and passive/device markers. +Annotation and pin-purpose shapes are excluded; all functional routing must use +drawing layers. The complete layer list is frozen in `/protocol/task.json`. + +The judge independently extracts distributed wiring resistance and capacitance +from the submitted GDS, retaining candidate-derived MOS/passive geometry and +external body connections. Every scored simulation consumes that extracted DUT. +This model boundary does not include a distributed silicon substrate network. +The output has a high common-mode level; it is not a rail-to-rail amplifier. Transient settling, mismatch, noise, PVT and EM are outside scope. Manufacturing signoff is not claimed. + +## Electrical Requirements and Scoring + +All three operating conditions must complete and every observation must be finite +and meet its inclusive band. Aggregation cannot hide a failing condition; +missing crossings or incomplete extraction/simulation cannot establish success. +Saved waveforms provide the inputs for independently reconstructing observations. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output voltage; average of both outputs for the differential pair | V | target / target | 0 … 3.3 | 3.3 | +| `imbalance_v` | Absolute DC difference between the two outputs | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 | +| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — | +| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — | +| `linearity_v` | Maximum absolute differential-output deviation from the line joining the -10/+10 mV samples | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `slope` | Differential-output endpoint difference divided by 20 mV | V/V | target / target | −∞ … +∞ | 5 | + +Area reference: **925.98 um2**. 6 expanded device instances; sum of device/contact envelopes 552.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **4**; it is independent of +the reference-relative task score. + + +### Score weights + +Local gain stages: signal transfer 38.6%; bandwidth 11.6%; balance and linearity 19.3%; operating points 3.86%; power 11.6%; area 15%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.15 | +| `gain_db` | 0.193181818182 | +| `slope` | 0.193181818182 | +| `bandwidth_hz` | 0.115909090909 | +| `imbalance_v` | 0.096590909091 | +| `linearity_v` | 0.096590909091 | +| `bias_v` | 0.019318181818 | +| `output_v` | 0.019318181818 | +| `power_w` | 0.115909090909 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 resources listed in `/protocol/resources.json`. +KLayout checks the layout, Magic extracts RC and ngspice simulates the circuit. +`/protocol/task.json` provides frozen constraints and evaluation requirements; +`/protocol/harness.json` describes the harness. If `process-feedback` is +exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/reference/dp_001_resistive_load.gds b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/reference/dp_001_resistive_load.gds new file mode 100644 index 0000000000000000000000000000000000000000..ef83da752741db5265c89da096970ba9119b8768 Binary files /dev/null and b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/reference/dp_001_resistive_load.gds differ diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..2e850dc5a7585715431137167a0e91db0b68be0b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml @@ -0,0 +1,979 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.gs_001_cascode_cs" +title = "Self-Biased Cascode Common-Source Gain Stage" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "fe2d9389f78b5d491eba5610f0d991bee6c5d8fedc53df054788f8a07bf68682" + +[[assets]] +path = "reference/gs_001_cascode_cs.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "045f0d29479fe5fcaf8955ca6205d10ee8b0f6286b734abe0d38a5891702d0ff" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_cascode_common_source" +coefficient = 4 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "659170c9549c470b2abf932562ad6fafd27cb09b68e6dc0bbcf6ebd8eb1e34da" + +[task.inputs.netlist] +path = "materials/circuit.spice" +format = "spice" +sha256 = "59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299" +subcircuit = "gs_001_cascode_cs" + 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+ ], + [ + 125, + 5, + ], + [ + 127, + 5, + ], + [ + 128, + 17, + ], + [ + 137, + 5, + ], + [ + 151, + 5, + ], + [ + 152, + 5, + ], + [ + 153, + 51, + ], + [ + 166, + 5, + ], + [ + 167, + 5, + ], + [ + 173, + 5, + ], + [ + 178, + 0, + ], + [ + 183, + 0, + ], + [ + 184, + 0, + ], + [ + 185, + 0, + ], + [ + 204, + 0, + ], + [ + 210, + 0, + ], + [ + 220, + 0, + ], + [ + 226, + 0, + ], + [ + 227, + 0, + ], + [ + 241, + 0, + ], +] +max_width_um = 220 +max_height_um = 120 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vin", + "ibias", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "bias_v" +category = "performance" +observations = [ + "condition_0:bias_v", + "condition_1:bias_v", + "condition_2:bias_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:bias_v", + "source_condition_1:bias_v", + "source_condition_2:bias_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "gain_db" +category = "performance" +observations = [ + "condition_0:gain_db", + "condition_1:gain_db", + "condition_2:gain_db", +] +unit = "dB" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:gain_db", + "source_condition_1:gain_db", + "source_condition_2:gain_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "bandwidth_hz" +category = "performance" +observations = [ + "condition_0:bandwidth_hz", + "condition_1:bandwidth_hz", + "condition_2:bandwidth_hz", +] +unit = "Hz" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_condition_0:bandwidth_hz", + "source_condition_1:bandwidth_hz", + "source_condition_2:bandwidth_hz", +] +normalization = "ratio" +lower = 0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 394.4 +rationale = "Local gain stages: signal transfer 50%; bandwidth 15%; operating points 5%; power 15%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +gain_db = 0.5 +bandwidth_hz = 0.15 +bias_v = 0.025 +output_v = 0.025 +power_w = 0.15 + +[task.evaluation.pre_layout] +source_report_sha256 = "0e4a00b1f4762ad83ec5921be08b28e636c1facbd70fb5ade9e669ce89742bec" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 2.7 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "01aa8d8a27335b57290c82c187786883b41ff683eb72db92babb37073605d276" +dut = "59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bandwidth_hz] +value = 521841.2 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] +value = 0.4718821285916 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] +value = 33.66256 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.7191511880448 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001593116578548 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "01aa8d8a27335b57290c82c187786883b41ff683eb72db92babb37073605d276" +dut = "59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bandwidth_hz] +value = 533296.5 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] +value = 0.7718821285968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] +value = 33.47832 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 0.7191068671981 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0001801852073254 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +bias_v = "V" +gain_db = "dB" +bandwidth_hz = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "01aa8d8a27335b57290c82c187786883b41ff683eb72db92babb37073605d276" +dut = "59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bandwidth_hz] +value = 538586.7 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] +value = 1.071882128597 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_db] +value = 33.3961 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 0.7190887958586 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.0001998895409979 +unit = "W" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/gs_001_cascode_cs" + +[qualification] +reference = "reference/gs_001_cascode_cs.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Provides voltage gain through a self-biased cascode common-source stage." diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..8673bf75bd6f91e8342ef21be9ccf91adebc41f6 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice @@ -0,0 +1,14 @@ +* Derived from analog-db gs_001_cascode_cs, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: fixed dimensions and explicit body rails. +.subckt gs_001_cascode_cs vdd vout vin ibias vss +XMNB1 nbias1 nbias1 vss vss nfet_03v3 w=6u l=0.3u m=1 +XMNB2 nbias2 nbias2 nbias1 vss nfet_03v3 w=6u l=0.3u m=1 +XMNCA vout nbias2 nint vss nfet_03v3 w=4u l=0.3u m=1 +XMNIN nint vin vss vss nfet_03v3 w=4u l=0.3u m=1 +XMPB1 pbias1 pbias1 vdd vdd pfet_03v3 w=16u l=0.5u m=1 +XMPB2 ibias ibias pbias1 vdd pfet_03v3 w=16u l=0.5u m=1 +XMPCA vout ibias pint vdd pfet_03v3 w=10u l=0.5u m=1 +XMPLD pint pbias1 vdd vdd pfet_03v3 w=10u l=0.5u m=1 +XMPNR nbias2 ibias vdd vdd pfet_03v3 w=0.5u l=0.5u m=1 +.ends gs_001_cascode_cs diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..f5311387313d7e6fe671cea50d59992bce9c2bad --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/schematic.svg @@ -0,0 +1 @@ +gs_001_cascode_cs{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.gs_001_cascode_cs", "netlist_sha256": "59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299", "project_sha256": "f7f6dca2cd88b9a0f87f19eb045cdebb770aac5c7eef7f185f81a7441a1d2949", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["gs_001_cascode_cs"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}gs_001_cascode_csvssvddpbias1nbias2ibiasnbias1pbias1vddibiasnbias2vinvsspintvoutnintvddvoutvinibiasvssgs_001_cascode_csgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Cascoded gain stageXMPLD10/0.5XMPCA10/0.5XMNCA4/0.3XMNIN4/0.3P bulk → vddN bulk → vss02 Cascode bias generationXMPB116/0.5XMPNR0.5/0.5XMPB216/0.5XMNB26/0.3XMNB16/0.3P bulk → vddN bulk → vssModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..b6546a63132cb4bb95ecb128a4debb2e4749ca01 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/testbench.spice @@ -0,0 +1,31 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 DC {supply_v} +IB ibias 0 20u +* External bias fixture: DC output feedback, AC-isolated input injection. +LFB vout vin 1T +VIN acin 0 DC 0 AC 1 +CIN acin vin 1 +CL vout 0 1p +XDUT vdd vout vin ibias 0 gs_001_cascode_cs +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let bias_v=v(ibias) +let power_w=-v(vdd)*i(vdd) +print output_v bias_v power_w +write op.raw v(vdd) v(vout) v(vin) v(ibias) i(vdd) +ac dec 100 1 1G +let gain_db=db(v(vout)) +meas ac gain_db find gain_db at=10 +let drop_db=db(v(vout))-gain_db +meas ac bandwidth_hz when drop_db=-3 fall=1 +write ac.raw frequency v(vout) v(vin) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/problem.md b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..342593d32dfe99548ef55d0923c9fd6cdd8df06d --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/problem.md @@ -0,0 +1,122 @@ +# Self-Biased Cascode Common-Source Gain Stage Layout Task + +## Objective + +Implement the fixed `gs_001_cascode_cs` circuit in GF180MCU D and submit self-contained GDS. +Nine MOS devices form a cascode common-source stage with PMOS and NMOS bias ladders. An external 20 uA sink biases the PMOS ladder. Total widths, lengths and multiplicities follow the fixed GF180 binding. Physical body contacts and an independently constructed reference complete the circuit. + +## Inputs and Interface + +`materials/circuit.spice` is authoritative for LVS and source calibration; +`materials/testbench.spice` defines every electrical measurement. This problem +is the description input. Ordered ports: `vdd vout vin ibias vss`. +In order, these are: Supply, output, signal input, PMOS reference-current sink, and return. + +Preserve the netlist's device connectivity, dimensions, multiplicities and body +connections. Provide physical well/substrate contacts to the declared rails. +Placement, routing, splitting and source/drain interchange are permitted only +where accepted by the declared LVS equivalence rules. No common-centroid or +statistical matching requirement is scored. Ideal external stimulus, bias and +load devices remain testbench apparatus and must not be placed inside the DUT. + +## Operating Conditions + +Use the typical GF180 3.3 V MOS models and physical poly models where present, +with statistical variation disabled. Unless swept explicitly, temperature is 27 C. +VSS = 0 V; VDD = 2.7, 3.0 and 3.3 V; external 20 uA sink from ibias to VSS; external 1 pF output load. A 1 TH external inductor connects output to input for the DC trip-point solve. A 1 F external coupling capacitor injects a unit AC input through acin while isolating the DC fixture. This measures open-loop small-signal gain at each self-biased trip point; it does not prescribe a fixed DC input voltage. + +AC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is +V(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp) +for unit differential excitation; the OTA transfer is defined above. + +## Physical Requirements + +Submit top cell `gs_001_cascode_cs` with every named electrical port, resolved hierarchy +and a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna, +strict named-port LVS and geometry must pass, without DRC waivers. Chip-level +density and seal-ring closure are outside this standalone-block scope. + +The functional bounding box must fit within 220 by 120 um. Area includes all +process device and routing drawing layers listed in runtime constraints: +wells, implants, active, poly, contacts, metals/vias and passive/device markers. +Annotation and pin-purpose shapes are excluded; all functional routing must use +drawing layers. The complete layer list is frozen in `/protocol/task.json`. + +The judge independently extracts distributed wiring resistance and capacitance +from the submitted GDS, retaining candidate-derived MOS/passive geometry and +external body connections. Every scored simulation consumes that extracted DUT. +This model boundary does not include a distributed silicon substrate network. +Transient settling, fixed-input bias robustness, noise, mismatch, PVT and EM are outside scope. Manufacturing signoff is not claimed. + +## Electrical Requirements and Scoring + +All three operating conditions must complete and every observation must be finite +and meet its inclusive band. Aggregation cannot hide a failing condition; +missing crossings or incomplete extraction/simulation cannot establish success. +Saved waveforms provide the inputs for independently reconstructing observations. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 | +| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 | +| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — | +| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — | + +Area reference: **394.4 um2**. 9 expanded device instances; sum of device/contact envelopes 220.6500 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **4**; it is independent of +the reference-relative task score. + + +### Score weights + +Local gain stages: signal transfer 50%; bandwidth 15%; operating points 5%; power 15%; area 15%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.15 | +| `gain_db` | 0.500000000000 | +| `bandwidth_hz` | 0.150000000000 | +| `bias_v` | 0.025000000000 | +| `output_v` | 0.025000000000 | +| `power_w` | 0.150000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 resources listed in `/protocol/resources.json`. +KLayout checks the layout, Magic extracts RC and ngspice simulates the circuit. +`/protocol/task.json` provides frozen constraints and evaluation requirements; +`/protocol/harness.json` describes the harness. If `process-feedback` is +exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/reference/gs_001_cascode_cs.gds b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/reference/gs_001_cascode_cs.gds new file mode 100644 index 0000000000000000000000000000000000000000..f6949f424652dd432904bf122b15f43d6e565318 Binary files /dev/null and b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/reference/gs_001_cascode_cs.gds differ diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..deddb9710718d9ad1893eaa3c8b475e02852b85c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml @@ -0,0 +1,1750 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.ldo_002_analoggym_folded_cascode" +title = "Folded-Cascode LDO" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "68458169f02a61fd8586477b28c9b643c472331585dc7c5ebc2f9b849535a401" + +[[assets]] +path = "reference/ldo_002_analoggym_folded_cascode.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "96dd0e39ed10b4920541467112818a3e643bbb03dfb55fe5c4eb7c5e122694e3" + +[task] +hours = 8 +kind = "netlist_to_gds" +family = "ldo" +coefficient = 7 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "dc0f8e6469fe2a5c3c3782f343a24ba5ed08e02d9d1818d5593fee7fb97750f3" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +format = "spice" +sha256 = "7463ac0a1cc09ec1f522693a4e4e03b348a693a698cdfb71cade504ca6ff4681" +subcircuit = "ldo_002_analoggym_folded_cascode" + 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"post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", + "vb1", + "vb2", + "vref", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0.001 +do_static = 0 + +[task.evaluation.jobs.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0.1 +load_step_a = 0 +do_static = 0 + +[task.evaluation.jobs.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.1 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_4" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2 +load_a = 0.002 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_5" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:startup" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.measurements] +startup_final_v = "V" +startup_ripple_v = "V" +startup_min_v = "V" +startup_max_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_6" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:regulation" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +line = "ngspice-raw" +load = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 + +[task.evaluation.jobs.parameters.measurements] +line_reg_v_per_v = "V/V" +load_reg_ohm = "ohm" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +line = "line.raw" +load = "load.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +dimension = "bias" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 1.8 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_3:output_v", + "condition_4:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_3:output_v", + "source_condition_4:output_v", +] + +[[task.evaluation.metrics]] +id = "regulation_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:regulation_error_v", + "condition_3:regulation_error_v", + "condition_4:regulation_error_v", +] +baseline = [ + "source_condition_0:regulation_error_v", + "source_condition_3:regulation_error_v", + "source_condition_4:regulation_error_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_3:power_w", + "condition_4:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_3:power_w", + "source_condition_4:power_w", +] + +[[task.evaluation.metrics]] +id = "psrr_db" +unit = "dB" +dimension = "response" +direction = "maximize" +normalization = "db20" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:psrr_db", + "condition_3:psrr_db", + "condition_4:psrr_db", +] +baseline = [ + "source_condition_0:psrr_db", + "source_condition_3:psrr_db", + "source_condition_4:psrr_db", +] + +[[task.evaluation.metrics]] +id = "quiet_ripple_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:quiet_ripple_v", + "condition_1:quiet_ripple_v", + "condition_2:quiet_ripple_v", + "condition_3:quiet_ripple_v", + "condition_4:quiet_ripple_v", +] +baseline = [ + "source_condition_0:quiet_ripple_v", + "source_condition_1:quiet_ripple_v", + "source_condition_2:quiet_ripple_v", + "source_condition_3:quiet_ripple_v", + "source_condition_4:quiet_ripple_v", +] + +[[task.evaluation.metrics]] +id = "recovery_ripple_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:recovery_ripple_v", + "condition_1:recovery_ripple_v", + "condition_2:recovery_ripple_v", + "condition_3:recovery_ripple_v", + "condition_4:recovery_ripple_v", +] +baseline = [ + "source_condition_0:recovery_ripple_v", + "source_condition_1:recovery_ripple_v", + "source_condition_2:recovery_ripple_v", + "source_condition_3:recovery_ripple_v", + "source_condition_4:recovery_ripple_v", +] + +[[task.evaluation.metrics]] +id = "excursion_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:excursion_v", + "condition_1:excursion_v", + "condition_2:excursion_v", + "condition_3:excursion_v", + "condition_4:excursion_v", +] +baseline = [ + "source_condition_0:excursion_v", + "source_condition_1:excursion_v", + "source_condition_2:excursion_v", + "source_condition_3:excursion_v", + "source_condition_4:excursion_v", +] + +[[task.evaluation.metrics]] +id = "late_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:late_error_v", + "condition_1:late_error_v", + "condition_2:late_error_v", + "condition_3:late_error_v", + "condition_4:late_error_v", +] +baseline = [ + "source_condition_0:late_error_v", + "source_condition_1:late_error_v", + "source_condition_2:late_error_v", + "source_condition_3:late_error_v", + "source_condition_4:late_error_v", +] + +[[task.evaluation.metrics]] +id = "mean_power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:mean_power_w", + "condition_1:mean_power_w", + "condition_2:mean_power_w", + "condition_3:mean_power_w", + "condition_4:mean_power_w", +] +baseline = [ + "source_condition_0:mean_power_w", + "source_condition_1:mean_power_w", + "source_condition_2:mean_power_w", + "source_condition_3:mean_power_w", + "source_condition_4:mean_power_w", +] + +[[task.evaluation.metrics]] +id = "quiet_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:quiet_v", + "condition_1:quiet_v", + "condition_2:quiet_v", + "condition_3:quiet_v", + "condition_4:quiet_v", +] + +[[task.evaluation.metrics]] +id = "high_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:high_v", + "condition_1:high_v", + "condition_2:high_v", + "condition_3:high_v", + "condition_4:high_v", +] + +[[task.evaluation.metrics]] +id = "recovery_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:recovery_v", + "condition_1:recovery_v", + "condition_2:recovery_v", + "condition_3:recovery_v", + "condition_4:recovery_v", +] + +[[task.evaluation.metrics]] +id = "startup_final_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_final_v", +] + +[[task.evaluation.metrics]] +id = "startup_ripple_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_ripple_v", +] + +[[task.evaluation.metrics]] +id = "startup_min_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_min_v", +] + +[[task.evaluation.metrics]] +id = "startup_max_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_max_v", +] + +[[task.evaluation.metrics]] +id = "line_reg_v_per_v" +unit = "V/V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_6:line_reg_v_per_v", +] +baseline = [ + "source_condition_6:line_reg_v_per_v", +] + +[[task.evaluation.metrics]] +id = "load_reg_ohm" +unit = "ohm" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1 +lower = 0 +category = "performance" +observations = [ + "condition_6:load_reg_ohm", +] +baseline = [ + "source_condition_6:load_reg_ohm", +] + +[[task.evaluation.metrics]] +id = "kcl_a" +unit = "A" +direction = "minimize" +aggregation = "max" +category = "performance" +observations = [ + "condition_0:kcl_a", + "condition_3:kcl_a", + "condition_4:kcl_a", + "condition_6:kcl_a", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 29211.12 +rationale = "GF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +line_reg_v_per_v = 0.075 +load_reg_ohm = 0.075 +output_v = 0.075 +regulation_error_v = 0.075 +excursion_v = 0.149999999999 +late_error_v = 0.15 +psrr_db = 0.066666666667 +quiet_ripple_v = 0.066666666667 +recovery_ripple_v = 0.066666666667 +mean_power_w = 0.05 +power_w = 0.05 + +[task.evaluation.pre_layout] +source_report_sha256 = "8a07837e2e880d5f2dbefa5f9d956c6a03eb65057dc6c4e025f7501db880c69e" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "11261f220b30f92955ddfdf94826ba7ea8e8156cde660b37afeec1c7f3adc998" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.excursion_v] +value = 1.09468e-13 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] +value = 1.280225925270884e-15 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] +value = 0.001032794 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] +value = 0.002613486 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.801032793744071 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.002613485963459565 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.psrr_db] +value = 95.06447 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.quiet_ripple_v] +value = 9.392487e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.quiet_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_ripple_v] +value = 9.903189e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.regulation_error_v] +value = 0.001032793744070615 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0.001 +do_static = 0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "11261f220b30f92955ddfdf94826ba7ea8e8156cde660b37afeec1c7f3adc998" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.excursion_v] +value = 0.001019546 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.high_v] +value = 1.800818 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.late_error_v] +value = 0.001032794 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] +value = 0.003118443 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.quiet_ripple_v] +value = 9.392487e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.quiet_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_ripple_v] +value = 9.237056e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0.1 +load_step_a = 0 +do_static = 0 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "11261f220b30f92955ddfdf94826ba7ea8e8156cde660b37afeec1c7f3adc998" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.excursion_v] +value = 0.0008052533 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.high_v] +value = 1.80113 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.late_error_v] +value = 0.001032794 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] +value = 0.00264666 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.quiet_ripple_v] +value = 9.392487e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.quiet_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_ripple_v] +value = 1.31406e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +supply_v = 2.1 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "11261f220b30f92955ddfdf94826ba7ea8e8156cde660b37afeec1c7f3adc998" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.excursion_v] +value = 9.525714e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.high_v] +value = 1.80113 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.kcl_a] +value = 6.498707821878114e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.late_error_v] +value = 0.001130236 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.mean_power_w] +value = 0.002744868 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 1.801130235934693 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 0.002744867769010942 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.psrr_db] +value = 53.00476 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.quiet_ripple_v] +value = 5.284662e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.quiet_v] +value = 1.80113 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_ripple_v] +value = 4.32987e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_v] +value = 1.80113 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.regulation_error_v] +value = 0.001130235934692747 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_4.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_4.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.values] +supply_v = 2 +load_a = 0.002 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] +deck = "11261f220b30f92955ddfdf94826ba7ea8e8156cde660b37afeec1c7f3adc998" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.excursion_v] +value = 1.210143e-13 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.high_v] +value = 1.800818 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.kcl_a] +value = 5.611830444784971e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.late_error_v] +value = 0.000818044 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.mean_power_w] +value = 0.004613315 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] +value = 1.800818043967146 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] +value = 0.004613314831447987 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.psrr_db] +value = 73.36913 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.quiet_ripple_v] +value = 9.903189e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.quiet_v] +value = 1.800818 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_ripple_v] +value = 9.703349e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_v] +value = 1.800818 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.regulation_error_v] +value = 0.0008180439671459094 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_5.inputs] +deck = "input:startup" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_5.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.values] + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.measurements] +startup_final_v = "V" +startup_ripple_v = "V" +startup_min_v = "V" +startup_max_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] +deck = "0a7523d165b59949e9cda352809b8803f6c2d70adb879d40654ba67b234a9e73" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_final_v] +value = 1.801033 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_max_v] +value = 1.825731 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_min_v] +value = -2.6463e-40 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_ripple_v] +value = 2.612799e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_6.inputs] +deck = "input:regulation" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_6.outputs] +op = "ngspice-raw" +line = "ngspice-raw" +load = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.values] +supply_v = 2 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.measurements] +line_reg_v_per_v = "V/V" +load_reg_ohm = "ohm" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.exports] +op = "op.raw" +line = "line.raw" +load = "load.raw" + +[task.evaluation.pre_layout.jobs.source_condition_6.input_sha256] +deck = "a9743e1cf295769fc33c0b2111bad663a00f25e782b6e800b7da76fdcea5153d" +dut = "714fb591ed0e943cc084fccffdc210dac36b5396ab8311e5bdbf8b26c41c4c4b" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.kcl_a] +value = 1.280225925270884e-15 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.line_reg_v_per_v] +value = 0.0009744219073581917 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.load_reg_ohm] +value = 0.2147497769264817 +unit = "ohm" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_002_analoggym_folded_cascode" + +[qualification] +reference = "reference/ldo_002_analoggym_folded_cascode.gds" + +[presentation] +category = "Power & references" +summary = "Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power." diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..30b386e1d6ee85b15f0ef02394f38df674b8104a --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl @@ -0,0 +1,269 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt ldo_002_analoggym_folded_cascode vdd vout vss vb1 vb2 vref +CC_0 ncz vout cap_mim_2f0fF w=20u l=16.665u +CC_1 ncz vout cap_mim_2f0fF w=20u l=16.665u +CC_2 ncz vout cap_mim_2f0fF w=20u l=16.665u +RZ_0 ncz ngate vss ppolyf_u_1k w=1u l=2.75u +R_BLEED_0 vout R_BLEED_seg1 vss ppolyf_u_1k w=1u l=48.44u +R_BLEED_1 R_BLEED_seg1 vss vss ppolyf_u_1k w=1u l=48.44u +MM1_0 n2 vout n4 vss nfet_06v0 w=60u l=0.7u +MM2_0 n3 vref n4 vss nfet_06v0 w=60u l=0.7u +MM3_0 n2 nmir vdd vdd pfet_06v0 w=30u l=0.55u +MM4_0 n3 nmir vdd vdd pfet_06v0 w=30u l=0.55u +MM5_0 nmir vb2 n2 vdd pfet_06v0 w=10u l=0.55u +MM6_0 ngate vb2 n3 vdd pfet_06v0 w=10u l=0.55u +MM7_0 nmir vb1 vss vss nfet_06v0 w=20u l=2u +MM8_0 ngate vb1 vss vss nfet_06v0 w=20u l=2u +MM9_0 n4 vb1 vss vss nfet_06v0 w=30u l=0.7u +MMP_0 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_1 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_2 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_3 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_4 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_5 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_6 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_7 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_8 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_9 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_10 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_11 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_12 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_13 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_14 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_15 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_16 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_17 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_18 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_19 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_20 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_21 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_22 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_23 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_24 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_25 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_26 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_27 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_28 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_29 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_30 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_31 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_32 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_33 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_34 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_35 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_36 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_37 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_38 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_39 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_40 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_41 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_42 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_43 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_44 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_45 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_46 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_47 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_48 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_49 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_50 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_51 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_52 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_53 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_54 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_55 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_56 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_57 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_58 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_59 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_60 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_61 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_62 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_63 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_64 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_65 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_66 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_67 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_68 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_69 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_70 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_71 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_72 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_73 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_74 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_75 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_76 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_77 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_78 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_79 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_80 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_81 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_82 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_83 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_84 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_85 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_86 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_87 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_88 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_89 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_90 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_91 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_92 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_93 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_94 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_95 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_96 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_97 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_98 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_99 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_100 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_101 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_102 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_103 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_104 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_105 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_106 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_107 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_108 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_109 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_110 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_111 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_112 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_113 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_114 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_115 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_116 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_117 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_118 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_119 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_120 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_121 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_122 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_123 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_124 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_125 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_126 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_127 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_128 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_129 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_130 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_131 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_132 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_133 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_134 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_135 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_136 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_137 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_138 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_139 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_140 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_141 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_142 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_143 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_144 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_145 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_146 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_147 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_148 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_149 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_150 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_151 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_152 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_153 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_154 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_155 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_156 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_157 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_158 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_159 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_160 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_161 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_162 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_163 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_164 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_165 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_166 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_167 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_168 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_169 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_170 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_171 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_172 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_173 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_174 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_175 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_176 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_177 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_178 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_179 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_180 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_181 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_182 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_183 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_184 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_185 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_186 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_187 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_188 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_189 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_190 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_191 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_192 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_193 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_194 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_195 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_196 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_197 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_198 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_199 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_200 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_201 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_202 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_203 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_204 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_205 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_206 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_207 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_208 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_209 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_210 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_211 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_212 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_213 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_214 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_215 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_216 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_217 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_218 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_219 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_220 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_221 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_222 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_223 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_224 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_225 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_226 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_227 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_228 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_229 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_230 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_231 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_232 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_233 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_234 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_235 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_236 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_237 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_238 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_239 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_240 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_241 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_242 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_243 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_244 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_245 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_246 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_247 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_248 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +MMP_249 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +.ends ldo_002_analoggym_folded_cascode diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..27b7795319815eafcfe3ae955dd7fba15dd2a5d6 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.spice @@ -0,0 +1,269 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt ldo_002_analoggym_folded_cascode vdd vout vss vb1 vb2 vref +XCC_0 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=16.665u +XCC_1 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=16.665u +XCC_2 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=16.665u +XRZ_0 ncz ngate vss ppolyf_u_1k r_width=1u r_length=2.75u +XR_BLEED_0 vout R_BLEED_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XR_BLEED_1 R_BLEED_seg1 vss vss ppolyf_u_1k r_width=1u r_length=48.44u +XM1_0 n2 vout n4 vss nfet_06v0 w=60u l=0.7u +XM2_0 n3 vref n4 vss nfet_06v0 w=60u l=0.7u +XM3_0 n2 nmir vdd vdd pfet_06v0 w=30u l=0.55u +XM4_0 n3 nmir vdd vdd pfet_06v0 w=30u l=0.55u +XM5_0 nmir vb2 n2 vdd pfet_06v0 w=10u l=0.55u +XM6_0 ngate vb2 n3 vdd pfet_06v0 w=10u l=0.55u +XM7_0 nmir vb1 vss vss nfet_06v0 w=20u l=2u +XM8_0 ngate vb1 vss vss nfet_06v0 w=20u l=2u +XM9_0 n4 vb1 vss vss nfet_06v0 w=30u l=0.7u +XMP_0 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_1 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_2 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_3 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_4 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_5 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_6 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_7 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_8 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_9 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_10 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_11 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_12 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_13 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_14 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_15 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_16 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_17 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_18 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_19 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_20 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_21 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_22 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_23 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_24 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_25 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_26 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_27 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_28 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_29 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_30 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_31 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_32 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_33 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_34 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_35 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_36 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_37 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_38 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_39 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_40 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_41 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_42 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_43 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_44 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_45 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_46 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_47 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_48 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_49 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_50 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_51 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_52 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_53 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_54 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_55 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_56 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_57 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_58 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_59 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_60 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_61 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_62 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_63 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_64 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_65 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_66 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_67 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_68 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_69 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_70 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_71 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_72 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_73 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_74 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_75 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_76 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_77 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_78 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_79 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_80 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_81 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_82 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_83 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_84 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_85 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_86 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_87 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_88 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_89 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_90 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_91 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_92 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_93 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_94 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_95 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_96 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_97 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_98 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_99 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_100 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_101 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_102 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_103 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_104 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_105 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_106 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_107 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_108 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_109 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_110 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_111 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_112 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_113 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_114 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_115 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_116 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_117 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_118 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_119 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_120 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_121 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_122 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_123 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_124 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_125 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_126 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_127 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_128 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_129 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_130 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_131 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_132 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_133 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_134 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_135 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_136 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_137 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_138 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_139 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_140 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_141 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_142 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_143 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_144 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_145 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_146 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_147 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_148 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_149 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_150 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_151 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_152 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_153 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_154 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_155 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_156 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_157 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_158 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_159 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_160 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_161 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_162 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_163 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_164 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_165 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_166 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_167 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_168 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_169 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_170 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_171 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_172 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_173 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_174 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_175 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_176 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_177 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_178 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_179 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_180 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_181 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_182 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_183 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_184 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_185 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_186 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_187 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_188 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_189 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_190 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_191 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_192 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_193 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_194 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_195 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_196 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_197 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_198 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_199 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_200 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_201 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_202 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_203 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_204 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_205 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_206 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_207 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_208 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_209 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_210 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_211 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_212 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_213 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_214 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_215 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_216 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_217 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_218 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_219 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_220 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_221 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_222 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_223 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_224 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_225 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_226 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_227 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_228 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_229 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_230 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_231 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_232 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_233 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_234 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_235 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_236 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_237 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_238 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_239 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_240 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_241 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_242 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_243 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_244 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_245 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_246 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_247 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_248 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +XMP_249 vout ngate vdd vdd pfet_06v0 w=10u l=0.55u +.ends ldo_002_analoggym_folded_cascode diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/regulation.spice b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/regulation.spice new file mode 100644 index 0000000000000000000000000000000000000000..464672269a8fa2c7ad0d41b484ce76b4e68376db --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/regulation.spice @@ -0,0 +1,38 @@ +* Regulator nominal and finite-window perturbation observations. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.save v(vdd) v(vss) v(vout) v(cout) v(vref) i(vdd) i(vss) i(vref) v(vb1) v(vb2) i(vb1) i(vb2) @iload[current] +VSS vss 0 0 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 dc {supply_v} ac 1 pulse({supply_v} {supply_v+line_step_v} 100u 1u 1u 100u 500u) +VB1 vb1 0 1 +VB2 vb2 0 .025 +VREF vref 0 1.8 +ILOAD vout 0 dc {load_a} pulse({load_a} {load_a+load_step_a} 100u 1u 1u 100u 500u) +RESR vout cout .1 +COUT cout 0 1n +XDUT vdd vout vss vb1 vb2 vref ldo_002_analoggym_folded_cascode +.control +set numdgt=15 +op +let kcl_a=abs(i(vdd)+i(vss)+i(vref)+@iload[current]+i(vb1)+i(vb2)) +* Current conservation validates the observation, not circuit performance. +if kcl_a > 1e-08 + echo Invalid DC current conservation: kcl_a exceeds 1e-08 A + quit 1 +end +print kcl_a +write op.raw all +dc VDD 2 2.1 .01 +let line_reg_v_per_v=abs((v(vout)[length(v(vout))-1]-v(vout)[0])/.1) +print line_reg_v_per_v +write line.raw all +dc ILOAD .001 .002 .0001 +let load_reg_ohm=abs((v(vout)[length(v(vout))-1]-v(vout)[0])/.001) +print load_reg_ohm +write load.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/schematic.svg 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Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":3},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_002_analoggym_folded_cascode"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/schematic/ldo_002_analoggym_folded_cascode.icproj.json"}}Main-sheet overview; 5 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_002_analoggym_folded_cascodevddvoutngaten4vssvrefn4n3nczvddvddn2nmirvddvddn3nmirvddvb2n2nmirvddvb2voutngaten3vssvssvb1nmirvssvssnczvb1ngatevssvssvb1n4vddvoutngatevddvoutvssvb1vb2vrefvoutncznczngatevoutR_BLEED_seg1vssvoutR_BLEED_seg1voutvssn2ldo_002_analoggym_folded_cascodeEqual net labels connect. All source devices and exact parameters are retained.CC_0cap_mim_2f0fFw=20u l=16.665uCC_1cap_mim_2f0fFw=20u l=16.665uCC_2cap_mim_2f0fFw=20u l=16.665uRZ_0ppolyf_u_1kw=1u l=2.75uSubstrate: B=vssR_BLEED_0ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssR_BLEED_1ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssMM1_0nfet_06v0w=60u l=0.7uMM2_0nfet_06v0w=60u l=0.7uMM3_0pfet_06v0w=30u l=0.55uMM4_0pfet_06v0w=30u l=0.55uMM5_0pfet_06v0w=10u l=0.55uMM6_0pfet_06v0w=10u l=0.55uMM7_0nfet_06v0w=20u l=2uMM8_0nfet_06v0w=20u l=2uMM9_0nfet_06v0w=30u l=0.7uXMMP_bank1MMP_bank1 +Main-sheet overview; 5 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/startup.spice b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/startup.spice new file mode 100644 index 0000000000000000000000000000000000000000..d9ec4e5acf3684dccc6c0ea09e3a78c975e0efc5 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/startup.spice @@ -0,0 +1,30 @@ +* Regulator nominal and finite-window perturbation observations. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.save v(vdd) v(vss) v(vout) v(cout) v(vref) i(vdd) i(vss) i(vref) v(vb1) v(vb2) i(vb1) i(vb2) +VSS vss 0 0 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 PWL(0 0 10u 2 400u 2) +VB1 vb1 0 1 +VB2 vb2 0 .025 +VREF vref 0 1.8 +RLOAD vout 0 1800.0 +RESR vout cout .1 +COUT cout 0 1n +XDUT vdd vout vss vb1 vb2 vref ldo_002_analoggym_folded_cascode +.control +set numdgt=15 +set measdgt=15 +op +write op.raw all +tran 10n 400u 0 10n +meas tran startup_final_v avg v(vout) from=380u to=400u +meas tran startup_ripple_v pp v(vout) from=380u to=400u +meas tran startup_min_v min v(vout) from=0 to=400u +meas tran startup_max_v max v(vout) from=0 to=400u +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..f669bc05ba8d10ef7682cd9ce39054c7463f91e4 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/testbench.spice @@ -0,0 +1,49 @@ +* Regulator nominal and finite-window perturbation observations. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.save v(vdd) v(vss) v(vout) v(cout) v(vref) i(vdd) i(vss) i(vref) v(vb1) v(vb2) i(vb1) i(vb2) @iload[current] +VSS vss 0 0 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 dc {supply_v} ac 1 pulse({supply_v} {supply_v+line_step_v} 100u 1u 1u 100u 500u) +VB1 vb1 0 1 +VB2 vb2 0 .025 +VREF vref 0 1.8 +ILOAD vout 0 dc {load_a} pulse({load_a} {load_a+load_step_a} 100u 1u 1u 100u 500u) +RESR vout cout .1 +COUT cout 0 1n +XDUT vdd vout vss vb1 vb2 vref ldo_002_analoggym_folded_cascode +.csparam do_static={do_static} +.control +set numdgt=15 +set measdgt=15 +if $&do_static +op +let kcl_a=abs(i(vdd)+i(vss)+i(vref)+@iload[current]+i(vb1)+i(vb2)) +print kcl_a +let output_v=v(vout) +let regulation_error_v=abs(v(vout)-1.8) +let power_w=-v(vdd)*i(vdd) +print output_v regulation_error_v power_w +write op.raw all +ac dec 100 1 100Meg +let rejection=-db(v(vout)) +meas ac psrr_db find rejection at=1k +write ac.raw all +end +tran 10n 400u 0 10n +let err=abs(v(vout)-1.8) +let supply_power=-v(vdd)*i(vdd) +meas tran quiet_v avg v(vout) from=80u to=100u +meas tran quiet_ripple_v pp v(vout) from=80u to=100u +meas tran high_v avg v(vout) from=180u to=200u +meas tran recovery_v avg v(vout) from=380u to=400u +meas tran recovery_ripple_v pp v(vout) from=380u to=400u +meas tran excursion_v pp v(vout) from=100u to=400u +meas tran late_error_v avg err from=380u to=400u +meas tran mean_power_w avg supply_power from=0 to=400u +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/problem.md b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..9dae434d8be54689bd8e99e2b470699d5f19db36 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/problem.md @@ -0,0 +1,112 @@ +# Folded-Cascode LDO Layout Task + +## Objective + +Implement `ldo_002_analoggym_folded_cascode` as a GDS layout preserving the complete declared circuit. Nine-MOS folded-cascode error amplifier and a PMOS pass array, with direct output feedback, series RZ/CC and the physical minimum-load bleed. The fixed GF180 6 V binding expands to 259 MOS, three 2 fF/um2 MIM units, one nulling resistor and two series bleed segments. VB1, VB2 and VREF remain external sources; the original 0 V VLP measurement marker becomes a wire. + +## Inputs and Interface + +- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface. +- `materials/circuit.spice`: equivalent source simulation, including physical passives. +- `materials/testbench.spice`: performance observations. +- `materials/startup.spice`: startup observations. +- `materials/regulation.spice`: regulation observations. +- `problem.md`: this contract. + +Ordered ports: `vdd vout vss vb1 vb2 vref`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs. + +## Operating Conditions + +Nominal supply 2.0 V, external reference 1.8 V, VB1=1.0 V and VB2=0.025 V; 27 C, typical GF180 models with statistical variation disabled. Native 6 V DRC requires NMOS L>=0.70 um and PMOS L>=0.55 um; only undersized lengths are increased to those physical minima. All default widths and the 250-fold 10 um pass-device multiplier are retained. R_bleed is 100 kohm inside the physical DUT and consumes Vout^2/R power; external 1/2 mA load currents are additional, not replacements. CC=2 pF and RZ=3 kohm retain their original connections. External output capacitance is 1 nF with 0.1 ohm series ESR. Evaluate no disturbance, 1-to-2 mA load pulse, and +0.1 V input pulse, plus independent DC points at nominal+0.1 V/1 mA and nominal/2 mA. Pulses start at 100 us, have 1 us edges and 100 us high width; restoration finishes at 202 us. Observe 0–400 us with 10 ns maximum step; pre-step/high/recovery windows are 80–100/180–200/380–400 us. Supply rejection is measured at 1 kHz from a 1 V AC supply input (100 samples/decade, 1 Hz–100 MHz). Ascending DC sweeps cover nominal supply to nominal+0.1 V in 10 mV increments at 1 mA and 1–2 mA load in 0.1 mA increments at nominal supply; adjustment metrics are absolute endpoint slopes. These are finite ranges, not dropout measurements. Startup ramps VDD from zero to nominal in 10 us with fixed external references and a resistive 1 mA nominal load (target voltage/1 mA); it uses the ordinary initial DC solution, no UIC or forced initial output, and observes through 400 us. Startup extrema and late-window output/ripple are diagnostics. No dropout, loop gain or phase margin is claimed. Source and candidate use identical decks and parameters; no numerical shunt is used. + +## Physical Requirements + +GF180MCU D native standalone-block FEOL/BEOL, connectivity, grid, dummy and antenna rules; chip density/seal-ring rules are outside this block boundary. Named-port LVS and candidate-derived distributed Magic RC are required. Functional area includes active/poly, passives and all routing metal/vias. Capacitor substrate and resistor terminal models follow the frozen PDK profile. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 20000 by 2000 um; they bound the supported block footprint, not electrical quality. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Unit | Definition | Assignment | +|---|---|---|---| +| output_v | V | DC output | bias; target (scale 1.8) | +| regulation_error_v | V | Absolute DC setpoint error | response; ratio (scale 0.001) | +| power_w | W | Total input rail DC power, including physical bleed/divider and external current bias | supply; ratio (scale 1e-12) | +| psrr_db | dB | Input supply rejection at 1 kHz | response; db20 | +| quiet_ripple_v | V | Peak-to-peak pre-perturbation output 80–100 us | response; ratio (scale 0.001) | +| recovery_ripple_v | V | Peak-to-peak recovered output 380–400 us | response; ratio (scale 0.001) | +| excursion_v | V | Full output range 100–400 us | response; ratio (scale 0.001) | +| late_error_v | V | Mean absolute setpoint error 380–400 us | response; ratio (scale 0.001) | +| mean_power_w | W | Mean input rail power 0–400 us | supply; ratio (scale 1e-12) | +| quiet_v | V | Finite-window quiet_v | diagnostic; unscored | +| high_v | V | Finite-window high_v | diagnostic; unscored | +| recovery_v | V | Finite-window recovery_v | diagnostic; unscored | +| startup_final_v | V | 10 us input ramp with resistive load: startup_final_v | diagnostic; unscored | +| startup_ripple_v | V | 10 us input ramp with resistive load: startup_ripple_v | diagnostic; unscored | +| startup_min_v | V | 10 us input ramp with resistive load: startup_min_v | diagnostic; unscored | +| startup_max_v | V | 10 us input ramp with resistive load: startup_max_v | diagnostic; unscored | +| line_reg_v_per_v | V/V | Absolute ascending supply-sweep endpoint slope, nominal to nominal + 0.1 V, 1 mA load | response; ratio (scale 0.001) | +| load_reg_ohm | ohm | Absolute ascending load-sweep endpoint slope, 1 to 2 mA, nominal supply | response; ratio (scale 1) | +| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored | + +All required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores. + +Each scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude. + +Area anchor: 29211.12 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. For ordinary GF180 resistors this envelope conservatively uses the sheet-only length before contact correction; the explicit parallel 1-ohm bank uses its native dimensions. This is an analytical compact-area anchor, not the witness footprint. + +Coefficient 7 covers regulation, frequency response and recovery across loads. The provenance chain distinguishes the Apache-2.0 sky130_ldo_rl netlist from the BSD-3-Clause AnalogGym sizing/testbench; the actual circuit is the pinned MacAnalog GF180 binding, not another reference implementation. + + +### Score weights + +GF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `line_reg_v_per_v` | 0.075000000000 | +| `load_reg_ohm` | 0.075000000000 | +| `output_v` | 0.075000000000 | +| `regulation_error_v` | 0.075000000000 | +| `excursion_v` | 0.149999999999 | +| `late_error_v` | 0.150000000000 | +| `psrr_db` | 0.066666666667 | +| `quiet_ripple_v` | 0.066666666667 | +| `recovery_ripple_v` | 0.066666666667 | +| `mean_power_w` | 0.050000000000 | +| `power_w` | 0.050000000000 | + +## Tools and Submission + +Solve budget: **8 hours**. + +Use the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `ldo_002_analoggym_folded_cascode`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools. + +The source and extracted-candidate decks require absolute external DC current +conservation residual `kcl_a <= 1e-08 A`. A larger residual aborts +simulation and produces an evaluator error with unknown score, rather than a +functional rejection. The reported residual is an unscored diagnostic. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/reference/ldo_002_analoggym_folded_cascode.gds b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/reference/ldo_002_analoggym_folded_cascode.gds new file mode 100644 index 0000000000000000000000000000000000000000..2a2e71e9a799269e63497c63b65140f27caf483b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/reference/ldo_002_analoggym_folded_cascode.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:96dd0e39ed10b4920541467112818a3e643bbb03dfb55fe5c4eb7c5e122694e3 +size 3714466 diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..5300a910e7960909ca5954aaecf25fcc4f4e3fc9 --- /dev/null +++ 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0, + ], +] +max_width_um = 20000 +max_height_um = 2000 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", + "vb", + "vref", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.0 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +regulation_error_v = "V" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.0 +load_a = 0.001 +line_step_v = 0.1 +load_step_a = 0 +do_static = 0 + +[task.evaluation.jobs.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.0 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0.004 +do_static = 0 + +[task.evaluation.jobs.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.1 +load_a = 0.005 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +regulation_error_v = "V" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_4" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:startup" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.measurements] +startup_error_v = "V" +startup_ripple_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_5" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:sweep" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +line = "ngspice-raw" +load = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.measurements] +line_reg_v_per_v = "V/V" +load_reg_ohm = "ohm" + +[task.evaluation.jobs.parameters.exports] +line = "line.raw" +load = "load.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +aggregation = "max" +direction = "target" +dimension = "bias" +normalization = "target" +scale = 1.8 +lower = 0 +upper = 2.1 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_3:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_3:output_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +aggregation = "max" +direction = "minimize" +dimension = "supply" +normalization = "ratio" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_3:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_3:power_w", +] + +[[task.evaluation.metrics]] +id = "regulation_error_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:regulation_error_v", + "condition_3:regulation_error_v", +] +baseline = [ + "source_condition_0:regulation_error_v", + "source_condition_3:regulation_error_v", +] + +[[task.evaluation.metrics]] +id = "psrr_db" +unit = "dB" +aggregation = "max" +direction = "maximize" +dimension = "response" +normalization = "db20" +category = "performance" +observations = [ + "condition_0:psrr_db", + "condition_3:psrr_db", +] +baseline = [ + "source_condition_0:psrr_db", + "source_condition_3:psrr_db", +] + +[[task.evaluation.metrics]] +id = "quiet_ripple_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:quiet_ripple_v", + "condition_1:quiet_ripple_v", + "condition_2:quiet_ripple_v", + "condition_3:quiet_ripple_v", +] +baseline = [ + "source_condition_0:quiet_ripple_v", + "source_condition_1:quiet_ripple_v", + "source_condition_2:quiet_ripple_v", + "source_condition_3:quiet_ripple_v", +] + +[[task.evaluation.metrics]] +id = "recovery_ripple_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:recovery_ripple_v", + "condition_1:recovery_ripple_v", + "condition_2:recovery_ripple_v", + "condition_3:recovery_ripple_v", +] +baseline = [ + "source_condition_0:recovery_ripple_v", + "source_condition_1:recovery_ripple_v", + "source_condition_2:recovery_ripple_v", + "source_condition_3:recovery_ripple_v", +] + +[[task.evaluation.metrics]] +id = "excursion_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:excursion_v", + "condition_1:excursion_v", + "condition_2:excursion_v", + "condition_3:excursion_v", +] +baseline = [ + "source_condition_0:excursion_v", + "source_condition_1:excursion_v", + "source_condition_2:excursion_v", + "source_condition_3:excursion_v", +] + +[[task.evaluation.metrics]] +id = "late_error_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:late_error_v", + "condition_1:late_error_v", + "condition_2:late_error_v", + "condition_3:late_error_v", +] +baseline = [ + "source_condition_0:late_error_v", + "source_condition_1:late_error_v", + "source_condition_2:late_error_v", + "source_condition_3:late_error_v", +] + +[[task.evaluation.metrics]] +id = "kcl_a" +unit = "A" +aggregation = "max" +direction = "minimize" +category = "performance" +observations = [ + "condition_0:kcl_a", + "condition_3:kcl_a", +] + +[[task.evaluation.metrics]] +id = "startup_error_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_4:startup_error_v", +] +baseline = [ + "source_condition_4:startup_error_v", +] + +[[task.evaluation.metrics]] +id = "startup_ripple_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_4:startup_ripple_v", +] +baseline = [ + "source_condition_4:startup_ripple_v", +] + +[[task.evaluation.metrics]] +id = "line_reg_v_per_v" +unit = "V/V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_5:line_reg_v_per_v", +] +baseline = [ + "source_condition_5:line_reg_v_per_v", +] + +[[task.evaluation.metrics]] +id = "load_reg_ohm" +unit = "ohm" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 0.01 +lower = 0 +category = "performance" +observations = [ + "condition_5:load_reg_ohm", +] +baseline = [ + "source_condition_5:load_reg_ohm", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 169100 +rationale = "GF180 line/load regulators: regulation 25.7%; load and line recovery 25.7%; ripple and rejection 17.1%; startup 12.9%; power 8.57%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +line_reg_v_per_v = 0.064285714286 +load_reg_ohm = 0.064285714286 +output_v = 0.064285714286 +regulation_error_v = 0.064285714286 +excursion_v = 0.12857142857 +late_error_v = 0.128571428571 +psrr_db = 0.057142857143 +quiet_ripple_v = 0.057142857143 +recovery_ripple_v = 0.057142857143 +startup_error_v = 0.064285714286 +startup_ripple_v = 0.064285714286 +power_w = 0.085714285714 + +[task.evaluation.pre_layout] +source_report_sha256 = "32d9f1c91a5661cfbf898915bcb9057dacab191173df319ed4de14dbce413839" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 2.0 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +regulation_error_v = "V" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "49a25613cc329de08e8bb6459abf0623efd4f23af0253d7525b7de8094f891f3" +dut = "a12abf9c431f1396d03564b2cf0d7a5041dc87e93059c53d441693e110314219" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.excursion_v] +value = 1.920464e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] +value = 4.87890977618477e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] +value = 0.01018606 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.810186056713427 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.002221389345144847 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.psrr_db] +value = 46.85305 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.quiet_ripple_v] +value = 1.592282e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_ripple_v] +value = 1.673328e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.regulation_error_v] +value = 0.01018605671342665 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 2.0 +load_a = 0.001 +line_step_v = 0.1 +load_step_a = 0 +do_static = 0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "49a25613cc329de08e8bb6459abf0623efd4f23af0253d7525b7de8094f891f3" +dut = "a12abf9c431f1396d03564b2cf0d7a5041dc87e93059c53d441693e110314219" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.excursion_v] +value = 0.0702689 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.late_error_v] +value = 0.01018606 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.quiet_ripple_v] +value = 1.592282e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_ripple_v] +value = 1.791234e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 2.0 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0.004 +do_static = 0 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "49a25613cc329de08e8bb6459abf0623efd4f23af0253d7525b7de8094f891f3" +dut = "a12abf9c431f1396d03564b2cf0d7a5041dc87e93059c53d441693e110314219" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.excursion_v] +value = 0.2750852 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.late_error_v] +value = 0.01018606 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.quiet_ripple_v] +value = 1.592282e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_ripple_v] +value = 1.841638e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +supply_v = 2.1 +load_a = 0.005 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +power_w = "W" +regulation_error_v = "V" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "49a25613cc329de08e8bb6459abf0623efd4f23af0253d7525b7de8094f891f3" +dut = "a12abf9c431f1396d03564b2cf0d7a5041dc87e93059c53d441693e110314219" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.excursion_v] +value = 1.773914e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.kcl_a] +value = 9.367506770274758e-16 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.late_error_v] +value = 0.00302368 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 1.796976320135997 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 0.01073055462921683 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.psrr_db] +value = 46.16796 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.quiet_ripple_v] +value = 1.247225e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_ripple_v] +value = 1.745715e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.regulation_error_v] +value = 0.003023679864003315 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_4.inputs] +deck = "input:startup" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_4.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.values] + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.measurements] +startup_error_v = "V" +startup_ripple_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] +deck = "351cef196d795d09b7c87fe4e03f77e8cbfb71325624eba3596e069863ae827c" +dut = "a12abf9c431f1396d03564b2cf0d7a5041dc87e93059c53d441693e110314219" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.startup_error_v] +value = 0.01014803 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.startup_ripple_v] +value = 1.47149e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_5.inputs] +deck = "input:sweep" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_5.outputs] +line = "ngspice-raw" +load = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.values] + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.measurements] +line_reg_v_per_v = "V/V" +load_reg_ohm = "ohm" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.exports] +line = "line.raw" +load = "load.raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] +deck = "177111259b17b8a604353a08a3f28ecc03a950f3ecb957449eeafd3d1cfd2c2f" +dut = "a12abf9c431f1396d03564b2cf0d7a5041dc87e93059c53d441693e110314219" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.line_reg_v_per_v] +value = 0.003345370446581405 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.load_reg_ohm] +value = 3.480072701760761 +unit = "ohm" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_003_analoggym_simple" + +[qualification] +reference = "reference/ldo_003_analoggym_simple.gds" + +[presentation] +category = "Power & references" +summary = "Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power." diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..67ba8f5e601d6e1bd9a9c905d79c9d22ba63188b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl @@ -0,0 +1,374 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt ldo_003_analoggym_simple vdd vout vss vb vref +CC_0 ncz vout cap_mim_2f0fF w=20u l=12.5u +CC_1 ncz vout cap_mim_2f0fF w=20u l=12.5u +RZ_0 ncz ngate vss ppolyf_u_1k w=1u l=2.75u +R_BLEED_0 vout R_BLEED_seg1 vss ppolyf_u_1k w=1u l=48.44u +R_BLEED_1 R_BLEED_seg1 vss vss ppolyf_u_1k w=1u l=48.44u +MM1_0 ndiode vout ntail vss nfet_06v0 w=2u l=2u +MM2_0 ngate vref ntail vss nfet_06v0 w=2u l=2u +MM3_0 ngate ndiode vdd vdd pfet_06v0 w=80u l=0.55u +MM4_0 ndiode ndiode vdd vdd pfet_06v0 w=80u l=0.55u +MM5_0 ntail vb vss vss nfet_06v0 w=100u l=0.7u +MMP_0 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_1 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_2 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_3 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_4 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_5 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_6 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_7 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_8 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_9 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_10 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_11 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_12 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_13 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_14 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_15 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_16 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_17 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_18 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_19 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_20 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_21 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_22 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_23 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_24 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_25 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_26 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_27 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_28 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_29 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_30 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_31 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_32 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_33 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_34 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_35 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_36 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_37 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_38 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_39 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_40 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_41 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_42 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_43 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_44 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_45 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_46 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_47 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_48 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_49 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_50 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_51 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_52 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_53 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_54 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_55 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_56 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_57 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_58 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_59 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_60 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_61 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_62 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_63 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_64 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_65 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_66 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_67 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_68 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_69 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_70 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_71 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_72 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_73 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_74 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_75 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_76 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_77 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_78 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_79 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_80 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_81 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_82 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_83 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_84 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_85 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_86 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_87 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_88 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_89 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_90 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_91 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_92 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_93 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_94 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_95 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_96 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_97 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_98 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_99 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_100 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_101 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_102 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_103 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_104 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_105 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_106 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_107 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_108 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_109 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_110 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_111 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_112 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_113 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_114 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_115 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_116 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_117 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_118 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_119 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_120 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_121 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_122 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_123 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_124 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_125 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_126 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_127 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_128 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_129 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_130 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_131 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_132 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_133 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_134 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_135 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_136 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_137 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_138 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_139 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_140 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_141 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_142 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_143 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_144 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_145 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_146 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_147 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_148 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_149 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_150 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_151 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_152 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_153 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_154 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_155 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_156 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_157 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_158 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_159 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_160 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_161 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_162 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_163 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_164 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_165 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_166 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_167 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_168 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_169 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_170 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_171 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_172 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_173 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_174 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_175 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_176 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_177 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_178 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_179 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_180 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_181 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_182 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_183 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_184 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_185 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_186 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_187 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_188 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_189 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_190 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_191 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_192 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_193 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_194 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_195 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_196 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_197 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_198 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_199 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_200 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_201 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_202 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_203 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_204 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_205 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_206 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_207 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_208 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_209 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_210 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_211 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_212 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_213 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_214 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_215 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_216 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_217 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_218 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_219 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_220 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_221 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_222 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_223 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_224 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_225 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_226 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_227 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_228 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_229 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_230 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_231 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_232 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_233 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_234 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_235 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_236 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_237 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_238 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_239 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_240 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_241 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_242 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_243 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_244 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_245 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_246 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_247 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_248 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_249 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_250 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_251 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_252 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_253 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_254 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_255 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_256 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_257 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_258 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_259 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_260 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_261 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_262 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_263 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_264 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_265 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_266 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_267 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_268 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_269 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_270 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_271 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_272 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_273 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_274 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_275 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_276 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_277 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_278 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_279 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_280 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_281 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_282 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_283 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_284 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_285 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_286 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_287 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_288 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_289 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_290 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_291 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_292 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_293 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_294 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_295 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_296 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_297 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_298 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_299 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_300 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_301 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_302 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_303 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_304 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_305 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_306 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_307 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_308 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_309 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_310 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_311 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_312 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_313 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_314 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_315 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_316 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_317 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_318 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_319 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_320 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_321 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_322 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_323 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_324 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_325 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_326 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_327 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_328 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_329 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_330 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_331 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_332 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_333 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_334 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_335 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_336 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_337 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_338 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_339 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_340 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_341 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_342 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_343 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_344 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_345 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_346 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_347 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_348 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_349 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_350 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_351 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_352 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_353 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_354 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_355 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_356 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_357 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_358 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +MMP_359 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +.ends ldo_003_analoggym_simple diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..9725422c3efcc7740fcc2684f8aa7fbfa038ff12 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.spice @@ -0,0 +1,374 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt ldo_003_analoggym_simple vdd vout vss vb vref +XCC_0 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=12.5u +XCC_1 ncz vout cap_mim_2f0_m4m5_noshield c_width=20u c_length=12.5u +XRZ_0 ncz ngate vss ppolyf_u_1k r_width=1u r_length=2.75u +XR_BLEED_0 vout R_BLEED_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XR_BLEED_1 R_BLEED_seg1 vss vss ppolyf_u_1k r_width=1u r_length=48.44u +XM1_0 ndiode vout ntail vss nfet_06v0 w=2u l=2u +XM2_0 ngate vref ntail vss nfet_06v0 w=2u l=2u +XM3_0 ngate ndiode vdd vdd pfet_06v0 w=80u l=0.55u +XM4_0 ndiode ndiode vdd vdd pfet_06v0 w=80u l=0.55u +XM5_0 ntail vb vss vss nfet_06v0 w=100u l=0.7u +XMP_0 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_1 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_2 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_3 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_4 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_5 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_6 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_7 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_8 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_9 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_10 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_11 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_12 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_13 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_14 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_15 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_16 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_17 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_18 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_19 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_20 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_21 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_22 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_23 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_24 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_25 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_26 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_27 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_28 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_29 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_30 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_31 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_32 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_33 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_34 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_35 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_36 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_37 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_38 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_39 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_40 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_41 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_42 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_43 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_44 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_45 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_46 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_47 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_48 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_49 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_50 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_51 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_52 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_53 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_54 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_55 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_56 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_57 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_58 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_59 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_60 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_61 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_62 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_63 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_64 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_65 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_66 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_67 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_68 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_69 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_70 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_71 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_72 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_73 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_74 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_75 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_76 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_77 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_78 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_79 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_80 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_81 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_82 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_83 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_84 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_85 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_86 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_87 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_88 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_89 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_90 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_91 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_92 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_93 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_94 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_95 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_96 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_97 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_98 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_99 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_100 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_101 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_102 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_103 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_104 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_105 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_106 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_107 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_108 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_109 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_110 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_111 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_112 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_113 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_114 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_115 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_116 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_117 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_118 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_119 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_120 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_121 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_122 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_123 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_124 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_125 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_126 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_127 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_128 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_129 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_130 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_131 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_132 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_133 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_134 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_135 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_136 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_137 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_138 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_139 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_140 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_141 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_142 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_143 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_144 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_145 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_146 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_147 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_148 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_149 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_150 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_151 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_152 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_153 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_154 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_155 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_156 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_157 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_158 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_159 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_160 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_161 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_162 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_163 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_164 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_165 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_166 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_167 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_168 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_169 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_170 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_171 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_172 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_173 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_174 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_175 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_176 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_177 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_178 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_179 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_180 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_181 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_182 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_183 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_184 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_185 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_186 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_187 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_188 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_189 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_190 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_191 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_192 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_193 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_194 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_195 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_196 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_197 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_198 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_199 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_200 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_201 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_202 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_203 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_204 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_205 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_206 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_207 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_208 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_209 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_210 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_211 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_212 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_213 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_214 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_215 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_216 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_217 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_218 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_219 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_220 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_221 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_222 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_223 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_224 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_225 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_226 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_227 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_228 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_229 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_230 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_231 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_232 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_233 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_234 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_235 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_236 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_237 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_238 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_239 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_240 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_241 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_242 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_243 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_244 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_245 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_246 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_247 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_248 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_249 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_250 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_251 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_252 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_253 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_254 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_255 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_256 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_257 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_258 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_259 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_260 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_261 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_262 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_263 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_264 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_265 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_266 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_267 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_268 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_269 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_270 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_271 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_272 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_273 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_274 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_275 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_276 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_277 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_278 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_279 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_280 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_281 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_282 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_283 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_284 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_285 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_286 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_287 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_288 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_289 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_290 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_291 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_292 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_293 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_294 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_295 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_296 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_297 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_298 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_299 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_300 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_301 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_302 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_303 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_304 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_305 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_306 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_307 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_308 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_309 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_310 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_311 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_312 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_313 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_314 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_315 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_316 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_317 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_318 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_319 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_320 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_321 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_322 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_323 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_324 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_325 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_326 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_327 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_328 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_329 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_330 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_331 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_332 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_333 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_334 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_335 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_336 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_337 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_338 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_339 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_340 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_341 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_342 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_343 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_344 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_345 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_346 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_347 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_348 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_349 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_350 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_351 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_352 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_353 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_354 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_355 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_356 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_357 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_358 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +XMP_359 vout ngate vdd vdd pfet_06v0 w=20u l=0.55u +.ends ldo_003_analoggym_simple diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..e692f44ad0794434cda5e23f22e77a801669f468 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/schematic.svg @@ -0,0 +1,2 @@ +ldo_003_analoggym_simple{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_003_analoggym_simple","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl","netlist_sha256":"b3ed893165850ba59c078460a0c50ca3d808d92aeef5f73d166600b54f2cc176","project_sha256":"82605fe5c3377606695df9d66fc4c67ff3fd8249171bf1a74ad4e6cd108ee5e5","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"flat-cdl-project: independent source/project flattened device comparison, schema parse, symbol resolution and netlist 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Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":3},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_003_analoggym_simple"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/schematic/ldo_003_analoggym_simple.icproj.json"}}Main-sheet overview; 7 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_003_analoggym_simplevddvoutngatevrefngatentailvddvddnczngatendiodevddvddndiodendiodevssvssvbntailvddvoutngatevddvoutvoutvssvbvrefncznczngatevoutR_BLEED_seg1vssR_BLEED_seg1voutvoutvssndiodentailvssldo_003_analoggym_simpleEqual net labels connect. All source devices and exact parameters are retained.CC_0cap_mim_2f0fFw=20u l=12.5uCC_1cap_mim_2f0fFw=20u l=12.5uRZ_0ppolyf_u_1kw=1u l=2.75uSubstrate: B=vssR_BLEED_0ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssR_BLEED_1ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssMM1_0nfet_06v0w=2u l=2uMM2_0nfet_06v0w=2u l=2uMM3_0pfet_06v0w=80u l=0.55uMM4_0pfet_06v0w=80u l=0.55uMM5_0nfet_06v0w=100u l=0.7uXMMP_bank1MMP_bank1 +Main-sheet overview; 7 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/startup.spice b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/startup.spice new file mode 100644 index 0000000000000000000000000000000000000000..e03114090f4ca453aa9fa086ba173e9c428f0a30 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/startup.spice @@ -0,0 +1,26 @@ +* Independently authored Bench measurements; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VSS vss 0 0 +VDD vdd 0 PWL(0 0 10u 2 100u 2) +VB vb 0 PWL(0 0 10u 1.2 100u 1.2) +VREF vref 0 PWL(0 0 10u 1.8 100u 1.8) +RLOAD vout 0 1800 +RESR vout cout .1 +COUT cout 0 50p +XDUT vdd vout vss vb vref ldo_003_analoggym_simple +.save v(vdd) v(vss) v(vout) v(cout) v(vb) v(vref) i(vdd) i(vss) i(vb) i(vref) +.control +set numdgt=15 +set measdgt=15 +tran 2n 100u 0 2n +let err=abs(v(vout)-1.8) +meas tran startup_error_v avg err from=90u to=100u +meas tran startup_ripple_v pp v(vout) from=90u to=100u +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/sweep.spice b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/sweep.spice new file mode 100644 index 0000000000000000000000000000000000000000..ffbfe8b95c7bcbe329ae5cc74a61ce81fa027a08 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/sweep.spice @@ -0,0 +1,33 @@ +* Independently authored Bench measurements; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 2 +VSS vss 0 0 +VB vb 0 1.2 +VREF vref 0 1.8 +ILOAD vout 0 1m +RESR vout cout .1 +COUT cout 0 50p +XDUT vdd vout vss vb vref ldo_003_analoggym_simple +.save v(vdd) v(vss) v(vout) v(cout) v(vb) v(vref) i(vdd) i(vss) i(vb) i(vref) +.control +set numdgt=15 +set measdgt=15 +dc VDD 1.9 2.2 .005 +meas dc low_v find v(vout) at=2 +meas dc high_v find v(vout) at=2.1 +let line_reg_v_per_v=abs((v(vout)[40]-v(vout)[20])/(v(vdd)[40]-v(vdd)[20])) +print line_reg_v_per_v +write line.raw all +dc ILOAD .001 .005 .0001 +meas dc light_v find v(vout) at=.001 +meas dc heavy_v find v(vout) at=.005 +let load_reg_ohm=abs((v(vout)[length(v(vout))-1]-v(vout)[0])/.004) +print load_reg_ohm +write load.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..10e428ed62304cbcf7393c69020ccc2ca6ab4e74 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/testbench.spice @@ -0,0 +1,45 @@ +* Independently authored Bench measurements; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 dc {supply_v} ac 1 pulse({supply_v} {supply_v+line_step_v} 20u 100n 100n 40u 200u) +VSS vss 0 0 +VB vb 0 1.2 +VREF vref 0 1.8 +ILOAD vout 0 dc {load_a} pulse({load_a} {load_a+load_step_a} 20u 100n 100n 40u 200u) +RESR vout cout .1 +COUT cout 0 50p +XDUT vdd vout vss vb vref ldo_003_analoggym_simple +.save v(vdd) v(vss) v(vout) v(cout) v(vb) v(vref) i(vdd) i(vss) i(vb) i(vref) @iload[current] +.csparam do_static={do_static} +.control +set numdgt=15 +set measdgt=15 +if $&do_static +op +let output_v=v(vout) +let regulation_error_v=abs(v(vout)-1.8) +let power_w=-v(vdd)*i(vdd)-v(vb)*i(vb)-v(vref)*i(vref) +let kcl_a=abs(i(vdd)+i(vss)+i(vb)+i(vref)+@iload[current]) +print output_v regulation_error_v power_w kcl_a +write op.raw all +ac dec 100 1 100Meg +let rejection=-db(v(vout)) +meas ac psrr_db find rejection at=1k +write ac.raw all +end +tran 2n 100u 0 2n +let err=abs(v(vout)-1.8) +meas tran quiet_v avg v(vout) from=10u to=20u +meas tran quiet_ripple_v pp v(vout) from=10u to=20u +meas tran high_v avg v(vout) from=50u to=60u +meas tran recovery_v avg v(vout) from=90u to=100u +meas tran recovery_ripple_v pp v(vout) from=90u to=100u +meas tran excursion_v pp v(vout) from=20u to=100u +meas tran late_error_v avg err from=90u to=100u +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/problem.md b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..f4643b5a5fab845d6240679c1bc4c5ff608fa80c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/problem.md @@ -0,0 +1,104 @@ +# Simple Unity-Feedback LDO Layout Task + +## Objective + +Implement `ldo_003_analoggym_simple` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. A five-transistor NMOS-input error amplifier drives the PMOS pass device, with direct output feedback, the complete 3 kohm/1 pF series compensation and physical 100 kohm bleed. The pass transistor expands to 360 parallel units; the complete core has 365 MOS. GF180 6 V NMOS lengths obey the native 0.70 um minimum and PMOS lengths the 0.55 um minimum. The external bias remains 1.2 V and reference 1.8 V from the fixed binding. + +## Inputs and Interface + +`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/startup.spice`, `materials/sweep.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vdd vout vss vb vref`. VB and VREF are external ideal sources; the upstream zero-volt VLP feedback marker becomes a physical wire. The bleed is inside the DUT and counted in its input power, in addition to the explicitly stated fixture load. At 1.8 V it draws approximately 18 uA. The independent source baseline contains the same physical bleed, compensation and process adaptations. + +## Operating Conditions + +TT, 27 C. Main runs use 2.0 V supply and 1 mA external load, independently applying either no disturbance, a +0.1 V line step, or a +4 mA load step. A separate quiet condition uses 2.1 V/5 mA. Edges are 100 ns, disturbances start at 20 us and last 40 us. Output load is 50 pF behind 0.1 ohm ESR. Transient maximum step 2 ns, duration 100 us, initialized from DC. Upward DC supply sweep: 1.9–2.2 V in 5 mV steps at 1 mA; report the 2.0–2.1 V endpoint slope. Upward load sweep: 1–5 mA in 0.1 mA steps at 2.0 V. PSRR is -20 log10 of output response to a unit AC supply at 1 kHz, reference/bias AC grounded. Startup separately ramps supply/reference/bias together from zero over 10 us into a 1.8 kohm external resistive load; no negative-voltage ideal current load is applied during startup. No solver shunt, isolation L/C or imposed output state. + +All source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold. + +## Physical Requirements + +Submit a valid GDSII containing top cell `ldo_003_analoggym_simple`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 20000/2000 um. The complete functional layer set is `[[5, 0], [11, 17], [11, 39], [12, 0], [13, 17], [21, 0], [22, 0], [22, 4], [24, 0], [24, 5], [30, 0], [30, 4], [31, 0], [32, 0], [33, 0], [34, 0], [34, 3], [34, 4], [34, 5], [35, 0], [36, 0], [36, 3], [36, 4], [36, 5], [37, 0], [38, 0], [40, 0], [41, 0], [42, 0], [42, 3], [42, 4], [42, 5], [46, 0], [46, 3], [46, 4], [46, 5], [49, 0], [53, 0], [53, 3], [53, 4], [53, 5], [55, 0], [62, 0], [75, 0], [80, 5], [81, 0], [81, 3], [81, 4], [81, 5], [82, 0], [86, 17], [88, 17], [96, 1], [100, 5], [100, 7], [100, 8], [108, 5], [110, 5], [110, 11], [110, 12], [110, 13], [110, 14], [110, 15], [110, 16], [111, 5], [112, 1], [115, 5], [116, 5], [117, 5], [117, 10], [118, 5], [119, 5], [122, 5], [123, 5], [124, 5], [125, 5], [127, 5], [128, 17], [137, 5], [151, 5], [152, 5], [153, 51], [166, 5], [167, 5], [173, 5], [178, 0], [183, 0], [184, 0], [185, 0], [204, 0], [210, 0], [220, 0], [226, 0], [227, 0], [241, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor. + +Post-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. The GF180 model boundary retains physical poly substrate and MIM geometry. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +Coefficient 7 reflects compensated regulation, line/load recovery and coordinated startup. No dropout number, loop margin, unlimited load range, PVT or product specification is claimed. Regulation slopes describe the declared finite intervals. Final error/ripple describe 90–100 us, not a proof of asymptotic settling. Input power includes the bleed, delivered load and bias/reference source contributions. + +Every required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores. + +| Metric | Unit | Definition | Dimension / normalization | Functional bounds | +| --- | --- | --- | --- | --- | +| `output_v` | V | DC output | bias / target; scale 1.8 | lower=0; upper=2.1 | +| `power_w` | W | DC rail/reference/bias input power including bleed | supply / ratio; scale 1e-12 | lower=0 | +| `regulation_error_v` | V | Absolute DC output error relative to 1.8 V | response / ratio; scale 0.001 | lower=0 | +| `psrr_db` | dB | Supply rejection at 1 kHz | response / db20 | Finite measurement | +| `quiet_ripple_v` | V | Output variation 10–20 us | response / ratio; scale 0.001 | lower=0 | +| `recovery_ripple_v` | V | Output variation 90–100 us | response / ratio; scale 0.001 | lower=0 | +| `excursion_v` | V | Output excursion 20–100 us | response / ratio; scale 0.001 | lower=0 | +| `late_error_v` | V | Mean absolute output error 90–100 us | response / ratio; scale 0.001 | lower=0 | +| `kcl_a` | A | External DC KCL residual | diagnostic; unscored | Producer validity guard; see below | +| `startup_error_v` | V | Mean final startup error, 90–100 us, 10 us coordinated source ramps | response / ratio; scale 0.001 | lower=0 | +| `startup_ripple_v` | V | Final startup variation, 90–100 us | response / ratio; scale 0.001 | lower=0 | +| `line_reg_v_per_v` | V/V | Absolute endpoint slope, upward 2.0–2.1 V at 1 mA | response / ratio; scale 0.001 | lower=0 | +| `load_reg_ohm` | ohm | Absolute endpoint slope, upward 1–5 mA at 2.0 V | response / ratio; scale 0.01 | lower=0 | + +Target normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff. + +The area anchor is **169100 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (370 units, sum 84512.210000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **7**. + + +### Score weights + +GF180 line/load regulators: regulation 25.7%; load and line recovery 25.7%; ripple and rejection 17.1%; startup 12.9%; power 8.57%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `line_reg_v_per_v` | 0.064285714286 | +| `load_reg_ohm` | 0.064285714286 | +| `output_v` | 0.064285714286 | +| `regulation_error_v` | 0.064285714286 | +| `excursion_v` | 0.128571428570 | +| `late_error_v` | 0.128571428571 | +| `psrr_db` | 0.057142857143 | +| `quiet_ripple_v` | 0.057142857143 | +| `recovery_ripple_v` | 0.057142857143 | +| `startup_error_v` | 0.064285714286 | +| `startup_ripple_v` | 0.064285714286 | +| `power_w` | 0.085714285714 | + +## Tools and Submission + +Solve budget: **8 hours**. + +Use the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs. + +The source and extracted-candidate decks require absolute external DC current +conservation residual `kcl_a <= 1e-08 A`. A larger residual aborts +simulation and produces an evaluator error with unknown score, rather than a +functional rejection. The reported residual is an unscored diagnostic. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/reference/ldo_003_analoggym_simple.gds b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/reference/ldo_003_analoggym_simple.gds new file mode 100644 index 0000000000000000000000000000000000000000..165df7a29ff412f304a1721afa117b02972955d4 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/reference/ldo_003_analoggym_simple.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:38c6dad884a4d19cd85c36af488ca880b2b1a7a2adcd11920842896947b8ee8d +size 6757430 diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..f46f0ee78e8a9e30ee009f823335252ef72255a2 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml @@ -0,0 +1,1993 @@ +in_core = true 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+layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vref", + "ibias", + "vss", +] + +[[task.evaluation.jobs]] +id = "dc_0_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.2 +load_a = 0.0001 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_0_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.2 +load_a = 0.001 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_0_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.2 +load_a = 0.005 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_1_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +load_a = 0.0001 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_1_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +load_a = 0.001 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_1_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +load_a = 0.005 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_2_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_a = 0.0001 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_2_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_a = 0.001 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "dc_2_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_a = 0.005 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.jobs.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[[task.evaluation.jobs]] +id = "step_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:transient" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.2 + +[task.evaluation.jobs.parameters.measurements] +peak_error_v = "V" +high_settled_error_v = "V" +low_settled_error_v = "V" +tail_min_v = "V" + +[task.evaluation.jobs.parameters.exports] +waveform = "ldo-transient.raw" + +[[task.evaluation.jobs]] +id = "step_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:transient" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 + +[task.evaluation.jobs.parameters.measurements] +peak_error_v = "V" +high_settled_error_v = "V" +low_settled_error_v = "V" +tail_min_v = "V" + +[task.evaluation.jobs.parameters.exports] +waveform = "ldo-transient.raw" + +[[task.evaluation.jobs]] +id = "step_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:transient" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 + +[task.evaluation.jobs.parameters.measurements] +peak_error_v = "V" +high_settled_error_v = "V" +low_settled_error_v = "V" +tail_min_v = "V" + +[task.evaluation.jobs.parameters.exports] +waveform = "ldo-transient.raw" + +[[task.evaluation.jobs]] +id = "dropout" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:dropout" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +dropout_v = "V" + +[task.evaluation.jobs.parameters.exports] +waveform = "ldo-dropout.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "dc_0_0:output_v", + "dc_0_1:output_v", + "dc_0_2:output_v", + "dc_1_0:output_v", + "dc_1_1:output_v", + "dc_1_2:output_v", + "dc_2_0:output_v", + "dc_2_1:output_v", + "dc_2_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "min" +baseline = [ + "source_dc_0_0:output_v", + "source_dc_0_1:output_v", + "source_dc_0_2:output_v", + "source_dc_1_0:output_v", + "source_dc_1_1:output_v", + "source_dc_1_2:output_v", + "source_dc_2_0:output_v", + "source_dc_2_1:output_v", + "source_dc_2_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "tail_v" +category = "performance" +observations = [ + "dc_0_0:tail_v", + "dc_0_1:tail_v", + "dc_0_2:tail_v", + "dc_1_0:tail_v", + "dc_1_1:tail_v", + "dc_1_2:tail_v", + "dc_2_0:tail_v", + "dc_2_1:tail_v", + "dc_2_2:tail_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "min" +baseline = [ + "source_dc_0_0:tail_v", + "source_dc_0_1:tail_v", + "source_dc_0_2:tail_v", + "source_dc_1_0:tail_v", + "source_dc_1_1:tail_v", + "source_dc_1_2:tail_v", + "source_dc_2_0:tail_v", + "source_dc_2_1:tail_v", + "source_dc_2_2:tail_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "quiescent_a" +category = "performance" +observations = [ + "dc_0_0:quiescent_a", + "dc_0_1:quiescent_a", + "dc_0_2:quiescent_a", + "dc_1_0:quiescent_a", + "dc_1_1:quiescent_a", + "dc_1_2:quiescent_a", + "dc_2_0:quiescent_a", + "dc_2_1:quiescent_a", + "dc_2_2:quiescent_a", +] +unit = "A" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_dc_0_0:quiescent_a", + "source_dc_0_1:quiescent_a", + "source_dc_0_2:quiescent_a", + "source_dc_1_0:quiescent_a", + "source_dc_1_1:quiescent_a", + "source_dc_1_2:quiescent_a", + "source_dc_2_0:quiescent_a", + "source_dc_2_1:quiescent_a", + "source_dc_2_2:quiescent_a", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "dc_0_0:power_w", + "dc_0_1:power_w", + "dc_0_2:power_w", + "dc_1_0:power_w", + "dc_1_1:power_w", + "dc_1_2:power_w", + "dc_2_0:power_w", + "dc_2_1:power_w", + "dc_2_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_dc_0_0:power_w", + "source_dc_0_1:power_w", + "source_dc_0_2:power_w", + "source_dc_1_0:power_w", + "source_dc_1_1:power_w", + "source_dc_1_2:power_w", + "source_dc_2_0:power_w", + "source_dc_2_1:power_w", + "source_dc_2_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "psrr_db" +category = "performance" +observations = [ + "dc_0_0:psrr_db", + "dc_0_1:psrr_db", + "dc_0_2:psrr_db", + "dc_1_0:psrr_db", + "dc_1_1:psrr_db", + "dc_1_2:psrr_db", + "dc_2_0:psrr_db", + "dc_2_1:psrr_db", + "dc_2_2:psrr_db", +] +unit = "dB" +dimension = "response" +direction = "maximize" +aggregation = "min" +baseline = [ + "source_dc_0_0:psrr_db", + "source_dc_0_1:psrr_db", + "source_dc_0_2:psrr_db", + "source_dc_1_0:psrr_db", + "source_dc_1_1:psrr_db", + "source_dc_1_2:psrr_db", + "source_dc_2_0:psrr_db", + "source_dc_2_1:psrr_db", + "source_dc_2_2:psrr_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "peaking_db" +category = "performance" +observations = [ + "dc_0_0:peaking_db", + "dc_0_1:peaking_db", + "dc_0_2:peaking_db", + "dc_1_0:peaking_db", + "dc_1_1:peaking_db", + "dc_1_2:peaking_db", + "dc_2_0:peaking_db", + "dc_2_1:peaking_db", + "dc_2_2:peaking_db", +] +unit = "dB" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_dc_0_0:peaking_db", + "source_dc_0_1:peaking_db", + "source_dc_0_2:peaking_db", + "source_dc_1_0:peaking_db", + "source_dc_1_1:peaking_db", + "source_dc_1_2:peaking_db", + "source_dc_2_0:peaking_db", + "source_dc_2_1:peaking_db", + "source_dc_2_2:peaking_db", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "peak_error_v" +category = "performance" +observations = [ + "step_0:peak_error_v", + "step_1:peak_error_v", + "step_2:peak_error_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_step_0:peak_error_v", + "source_step_1:peak_error_v", + "source_step_2:peak_error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "high_settled_error_v" +category = "performance" +observations = [ + "step_0:high_settled_error_v", + "step_1:high_settled_error_v", + "step_2:high_settled_error_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_step_0:high_settled_error_v", + "source_step_1:high_settled_error_v", + "source_step_2:high_settled_error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "low_settled_error_v" +category = "performance" +observations = [ + "step_0:low_settled_error_v", + "step_1:low_settled_error_v", + "step_2:low_settled_error_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_step_0:low_settled_error_v", + "source_step_1:low_settled_error_v", + "source_step_2:low_settled_error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "tail_min_v" +category = "performance" +observations = [ + "step_0:tail_min_v", + "step_1:tail_min_v", + "step_2:tail_min_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "min" +baseline = [ + "source_step_0:tail_min_v", + "source_step_1:tail_min_v", + "source_step_2:tail_min_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "dropout_v" +category = "performance" +observations = [ + "dropout:dropout_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_dropout:dropout_v", +] +normalization = "ratio" +scale = 1e-06 +lower = 0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 7597.32 +rationale = "GF180 compact regulator variants: regulation and recovery 36%; rejection and peaking 18%; dropout 18%; quiescent current 9%; internal bias 1.8%; power 7.2%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +high_settled_error_v = 0.09 +low_settled_error_v = 0.09 +output_v = 0.09 +peak_error_v = 0.09 +peaking_db = 0.09 +psrr_db = 0.09 +dropout_v = 0.18 +quiescent_a = 0.09 +tail_min_v = 0.009 +tail_v = 0.009 +power_w = 0.072 + +[task.evaluation.pre_layout] +source_report_sha256 = "e0c0379e448d793b0a33fd356fd4c57768fc8b1bcfff55240bff59111d170086" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_dc_0_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.parameters.values] +supply_v = 2.2 +load_a = 0.0001 + +[task.evaluation.pre_layout.jobs.source_dc_0_0.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.measurements.output_v] +value = 1.805981975438 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.measurements.power_w] +value = 0.0006795919986475 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.measurements.psrr_db] +value = 69.921 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.measurements.quiescent_a] +value = 0.0002089054539307 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_0_0.measurements.tail_v] +value = 0.08818124697064 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_0_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.parameters.values] +supply_v = 2.2 +load_a = 0.001 + +[task.evaluation.pre_layout.jobs.source_dc_0_1.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.measurements.output_v] +value = 1.803251492765 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.measurements.power_w] +value = 0.002659562309811 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.measurements.psrr_db] +value = 97.75298 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.measurements.quiescent_a] +value = 0.0002088919590048 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_0_1.measurements.tail_v] +value = 0.08739288366712 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_0_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.parameters.values] +supply_v = 2.2 +load_a = 0.005 + +[task.evaluation.pre_layout.jobs.source_dc_0_2.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.measurements.output_v] +value = 1.799798190507 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.measurements.power_w] +value = 0.01145952483615 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.measurements.psrr_db] +value = 61.37198 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.measurements.quiescent_a] +value = 0.0002088749255208 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_0_2.measurements.tail_v] +value = 0.08637118659501 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_1_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.parameters.values] +supply_v = 2.7 +load_a = 0.0001 + +[task.evaluation.pre_layout.jobs.source_dc_1_0.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.measurements.output_v] +value = 1.805909084312 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.measurements.power_w] +value = 0.000834059454886 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.measurements.psrr_db] +value = 104.8581 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.measurements.quiescent_a] +value = 0.000208910909217 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_1_0.measurements.tail_v] +value = 0.09031273455719 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_1_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.parameters.values] +supply_v = 2.7 +load_a = 0.001 + +[task.evaluation.pre_layout.jobs.source_dc_1_1.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.measurements.output_v] +value = 1.803284930545 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.measurements.power_w] +value = 0.003264015359829 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.measurements.psrr_db] +value = 78.30936 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.measurements.quiescent_a] +value = 0.0002088945777143 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_1_1.measurements.tail_v] +value = 0.08956385995494 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_1_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.parameters.values] +supply_v = 2.7 +load_a = 0.005 + +[task.evaluation.pre_layout.jobs.source_dc_1_2.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.measurements.output_v] +value = 1.800073800356 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.measurements.power_w] +value = 0.01406396835375 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.measurements.psrr_db] +value = 67.62932 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.measurements.quiescent_a] +value = 0.0002088771680549 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_1_2.measurements.tail_v] +value = 0.08862611274697 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_2_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.parameters.values] +supply_v = 3.3 +load_a = 0.0001 + +[task.evaluation.pre_layout.jobs.source_dc_2_0.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.measurements.output_v] +value = 1.806098813576 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.measurements.power_w] +value = 0.001019988812339 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.measurements.psrr_db] +value = 61.87726 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.measurements.quiescent_a] +value = 0.0002090875188907 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_2_0.measurements.tail_v] +value = 0.09277100487281 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_2_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.parameters.values] +supply_v = 3.3 +load_a = 0.001 + +[task.evaluation.pre_layout.jobs.source_dc_2_1.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.measurements.output_v] +value = 1.803441212054 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.measurements.power_w] +value = 0.003989742841039 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.measurements.psrr_db] +value = 66.05543 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.measurements.quiescent_a] +value = 0.000209012982133 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_2_1.measurements.tail_v] +value = 0.092027134992 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_2_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.outputs] +op = "ngspice-raw" +supply = "ngspice-raw" +impedance = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.parameters.values] +supply_v = 3.3 +load_a = 0.005 + +[task.evaluation.pre_layout.jobs.source_dc_2_2.parameters.measurements] +output_v = "V" +tail_v = "V" +quiescent_a = "A" +power_w = "W" +psrr_db = "dB" +peaking_db = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.parameters.exports] +op = "ldo-op.raw" +supply = "ldo-supply.raw" +impedance = "ldo-impedance.raw" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.input_sha256] +deck = "f477c788073f94ed67cd7fd0b5d6b5f95cf6360fdc7a28a1287701eff130746a" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.measurements.output_v] +value = 1.800292419657 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.measurements.peaking_db] +value = 0.0 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.measurements.power_w] +value = 0.01718953971935 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.measurements.psrr_db] +value = 69.23203 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.measurements.quiescent_a] +value = 0.0002089514301064 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_dc_2_2.measurements.tail_v] +value = 0.09112281361938 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_step_0.inputs] +deck = "input:transient" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_step_0.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_step_0.parameters.values] +supply_v = 2.2 + +[task.evaluation.pre_layout.jobs.source_step_0.parameters.measurements] +peak_error_v = "V" +high_settled_error_v = "V" +low_settled_error_v = "V" +tail_min_v = "V" + +[task.evaluation.pre_layout.jobs.source_step_0.parameters.exports] +waveform = "ldo-transient.raw" + +[task.evaluation.pre_layout.jobs.source_step_0.input_sha256] +deck = "2cf509d414b32f92db3c5247e0e034710320a8f98eb4d7d2d73476bc8fbf4f5c" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_step_0.measurements.high_settled_error_v] +value = 0.0002018095 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_0.measurements.low_settled_error_v] +value = 0.005981975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_0.measurements.peak_error_v] +value = 0.005981975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_0.measurements.tail_min_v] +value = 0.08637119 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_step_1.inputs] +deck = "input:transient" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_step_1.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_step_1.parameters.values] +supply_v = 2.7 + +[task.evaluation.pre_layout.jobs.source_step_1.parameters.measurements] +peak_error_v = "V" +high_settled_error_v = "V" +low_settled_error_v = "V" +tail_min_v = "V" + +[task.evaluation.pre_layout.jobs.source_step_1.parameters.exports] +waveform = "ldo-transient.raw" + +[task.evaluation.pre_layout.jobs.source_step_1.input_sha256] +deck = "2cf509d414b32f92db3c5247e0e034710320a8f98eb4d7d2d73476bc8fbf4f5c" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_step_1.measurements.high_settled_error_v] +value = 7.380036e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_1.measurements.low_settled_error_v] +value = 0.005909084 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_1.measurements.peak_error_v] +value = 0.005909084 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_1.measurements.tail_min_v] +value = 0.08862611 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_step_2.inputs] +deck = "input:transient" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_step_2.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_step_2.parameters.values] +supply_v = 3.3 + +[task.evaluation.pre_layout.jobs.source_step_2.parameters.measurements] +peak_error_v = "V" +high_settled_error_v = "V" +low_settled_error_v = "V" +tail_min_v = "V" + +[task.evaluation.pre_layout.jobs.source_step_2.parameters.exports] +waveform = "ldo-transient.raw" + +[task.evaluation.pre_layout.jobs.source_step_2.input_sha256] +deck = "2cf509d414b32f92db3c5247e0e034710320a8f98eb4d7d2d73476bc8fbf4f5c" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_step_2.measurements.high_settled_error_v] +value = 0.0002924197 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_2.measurements.low_settled_error_v] +value = 0.006098814 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_2.measurements.peak_error_v] +value = 0.006098814 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_step_2.measurements.tail_min_v] +value = 0.09112281 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_dropout] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_dropout.inputs] +deck = "input:dropout" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_dropout.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_dropout.parameters.measurements] +dropout_v = "V" + +[task.evaluation.pre_layout.jobs.source_dropout.parameters.exports] +waveform = "ldo-dropout.raw" + +[task.evaluation.pre_layout.jobs.source_dropout.input_sha256] +deck = "6ed4afa715fc9cadaec7404d1539e998579a4628a2e1538973a34887d17509c6" +dut = "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35" + +[task.evaluation.pre_layout.jobs.source_dropout.measurements.dropout_v] +value = 0.049365 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_004_basic_pmos" + +[qualification] +reference = "reference/ldo_004_basic_pmos.gds" + +[presentation] +category = "Power & references" +summary = "Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power." diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..1919c4f629eb282bd32970c3b5edcc1d7a3f3d38 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice @@ -0,0 +1,13 @@ +* Derived from analog-db ldo_004_basic_pmos, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: external vref/ibias +* interfaces; physical 1k/square poly divider; loop probe replaced by a wire. +.subckt ldo_004_basic_pmos vdd vout vref ibias vss +XM1 noutm fb ibias vss nfet_03v3 w=46u l=0.5u +XM2 egate vref ibias vss nfet_03v3 w=46u l=0.5u +XM3 noutm noutm vdd vdd pfet_03v3 w=50u l=0.5u +XM4 egate noutm vdd vdd pfet_03v3 w=50u l=0.5u +XMP vout egate vdd vdd pfet_03v3 w=10u l=0.3u m=100 +XR1 vout fb vss ppolyf_u_1k r_width=2u r_length=200u +XR2 fb vss vss ppolyf_u_1k r_width=2u r_length=200u +.ends ldo_004_basic_pmos diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/dropout.spice b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/dropout.spice new file mode 100644 index 0000000000000000000000000000000000000000..557c69646812e79708575bde82515bdf35339687 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/dropout.spice @@ -0,0 +1,22 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +* Dropout at 5 mA: upward input sweep and a fixed 1.75 V output threshold. +.include support/models.spice +.include dut.spice +.temp 27 +VDD vdd 0 2.2 +VREF vref 0 0.9 +ITAIL ibias 0 200u +ILOAD vout 0 5m +COUT vout 0 1u +XDUT vdd vout vref ibias 0 ldo_004_basic_pmos +.control +set noaskquit +set numdgt=12 +dc VDD 1.6 2.4 0.005 +meas dc dropout_supply_v when v(vout)=1.75 rise=1 +let dropout_v=dropout_supply_v-1.75 +print dropout_v +write ldo-dropout.raw v(vdd) v(vout) v(ibias) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..8a7806a55cd10942a736607b26e82cd06a79cbb5 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/schematic.svg @@ -0,0 +1 @@ +ldo_004_basic_pmos{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.ldo_004_basic_pmos", "netlist_sha256": "c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35", "project_sha256": "06d111949862fc189a06149c9c4615b5fcd647a75b76ff36a1d914fa90ed421f", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["ldo_004_basic_pmos"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice", "known_editor_diagnostics": {"ERC_ILLEGAL_PIN_NAME": 2}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}ldo_004_basic_pmosegatevddvssvoutfbfbvrefvddegateibiasnoutmvddvoutvrefibiasvssldo_004_basic_pmosgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Error amplifierXM350/0.5XM450/0.5XM146/0.5XM246/0.5P bulk → vddN bulk → vss02 Pass device and feedback dividerXMP10/0.3 ×100XR1W/L 2/200XR2W/L 2/200P bulk → vddR substrate → vssModels: nfet_03v3 · pfet_03v3 · ppolyf_u_1k \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..438ae8aa7f48734dd4ba947f9975c8fdbb14cb9c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/testbench.spice @@ -0,0 +1,39 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +* GF180 externally biased LDO nominal DC and AC measurements. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 DC {supply_v} AC 1 +VREF vref 0 0.9 +ITAIL ibias 0 200u +VLOAD vout load 0 +ILOAD load 0 DC {load_a} AC 0 +COUT vout 0 1u +XDUT vdd vout vref ibias 0 ldo_004_basic_pmos +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let tail_v=v(ibias) +let quiescent_a=-i(VDD)-i(VLOAD) +let power_w=-v(vdd)*i(VDD)-v(vref)*i(VREF) +print output_v tail_v quiescent_a power_w +write ldo-op.raw v(vout) v(ibias) v(vdd) v(vref) i(vdd) i(vref) i(vload) +ac dec 60 1 100meg +let rejection=-db(v(vout)) +meas ac psrr_db find rejection at=1k +write ldo-supply.raw frequency v(vout) v(vdd) +alter @vdd[acmag] = 0 +alter @iload[acmag] = 1 +ac dec 60 1 100meg +let impedance=mag(v(vout)) +meas ac dc_ohm find impedance at=1 +meas ac peak_ohm max impedance from=1 to=100meg +let peaking_db=20*log10(peak_ohm/dc_ohm) +print peaking_db +write ldo-impedance.raw frequency v(vout) i(vload) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/transient.spice b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/transient.spice new file mode 100644 index 0000000000000000000000000000000000000000..b6235cb1b5eeb6fa8f5cb5b745cb7b4b9efb9bc9 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/transient.spice @@ -0,0 +1,25 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +* Externally biased GF180 regulator: settled load-step response, no startup claim. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 {supply_v} +VREF vref 0 0.9 +ITAIL ibias 0 200u +ILOAD vout 0 PWL(0 100u 1m 100u 1.0001m 5m 2m 5m 2.0001m 100u 3m 100u) +COUT vout 0 1u +XDUT vdd vout vref ibias 0 ldo_004_basic_pmos +.control +set noaskquit +set numdgt=12 +tran 200n 3m +let error_v=abs(v(vout)-1.8) +meas tran peak_error_v max error_v from=0.9m to=3m +meas tran high_settled_error_v max error_v from=1.2m to=1.9m +meas tran low_settled_error_v max error_v from=2.2m to=3m +meas tran tail_min_v min v(ibias) from=0.9m to=3m +write ldo-transient.raw time v(vout) v(ibias) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..f3f76c59560438e1fdb67b1067f78631a091db0f --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md @@ -0,0 +1,167 @@ +# Externally Biased 1.8 V PMOS Regulator Core Layout Task + +## Objective + +Implement the fixed `ldo_004_basic_pmos` regulator core in GF180MCU D and submit +self-contained GDS. The circuit contains an error amplifier, a PMOS pass array +and a physical feedback divider. Reference and tail-current generation are +external to this core. + +## Inputs and Interface + +`materials/circuit.spice` is authoritative for LVS and source calibration. +`materials/testbench.spice`, `materials/transient.spice` and +`materials/dropout.spice` define the DC/AC, load-step and dropout measurements. +The ordered ports are `vdd vout vref ibias vss`: input supply, regulated output, +reference-voltage input, error-amplifier tail node, and return. An external +200 uA sink connects `ibias` to VSS; this is not a voltage-bias input. + +Retain the two NMOS input devices at W/L = 46/0.5 um, two PMOS mirror devices +at 50/0.5 um, and the PMOS pass device at 10/0.3 um with multiplicity 100. +Each feedback resistor is `ppolyf_u_1k`, width 2 um and length 200 um, giving +100 squares of nominal 1 kohm/square poly. Preserve connectivity, dimensions +and body connections. Placement, routing and electrically equivalent device +splitting/source-drain interchange are allowed only as accepted by the declared +LVS checks. Provide physical well/substrate contacts to the declared rails. +No statistical matching or common-centroid constraint is scored. + +## Operating Conditions + +Use typical 3.3 V MOS and poly-resistor models at 27 C, with statistical +variation disabled, VSS = 0 V, external VREF = 0.9 V and a 200 uA tail sink. +The external output capacitor is an ideal 1 uF, without added ESR. All nine +combinations of VDD = 2.2, 2.7, 3.3 V and load = 0.1, 1, 5 mA are required. +DC measurements follow the operating-point solve. AC uses 60 points per decade +from 1 Hz to 100 MHz. Supply rejection drives VDD with 1 V AC and zero AC load; +output impedance drives the load sink with 1 A AC and zero AC supply. + +At each of the three supplies, the transient starts from the DC operating point +at 0.1 mA load. Load rises to 5 mA between 1 and 1.0001 ms, then falls to 0.1 mA +between 2 and 2.0001 ms. Run to 3 ms with a 200 ns output step. Evaluate peak +absolute output error relative to 1.8 V over 0.9 to 3 ms, high-load settled error +over 1.2 to 1.9 ms, low-load settled error over 2.2 to 3 ms, and minimum tail +voltage over 0.9 to 3 ms. The recovery windows start 200 us after each load-step onset. Their errors +are continuous quality metrics with no upper acceptance bound; they do not +establish a recovery-time limit. + +The separate dropout sweep uses 5 mA load and sweeps VDD from 1.6 to 2.4 V +in 5 mV steps. Dropout is the supply voltage at the first rising crossing of +VOUT = 1.75 V, minus 1.75 V, using interpolated crossing measurement. +All ideal supplies, sinks and the output capacitor are testbench apparatus. + +## Physical Requirements + +Submit top cell `ldo_004_basic_pmos` with all five named electrical ports, +resolved hierarchy and a maximum file size of 10 MiB. Artifact, GF180 variant-D +DRC including antenna checks, strict named-port LVS and geometry must pass. +There are no DRC waivers. Chip-level density and seal-ring closure are outside +the standalone-block check scope. + +The functional bounding box must fit within 800 by 400 um. Area includes all +process device and routing drawing layers listed in the runtime constraints: +wells, implants, active, poly, contacts, metals/vias and passive/device markers. +Annotation text and pin-purpose shapes are excluded; functional routing must +use drawing layers. + +The judge extracts distributed interconnect RC from the submitted GDS and uses +that extracted DUT in every simulation. MOS and physical resistor geometry are +candidate-derived. The model boundary retains external body connections but +does not include a distributed silicon substrate network. Qualification covers +nominal DC, AC supply rejection/output impedance and these load steps; it does +not establish full loop phase margin, startup, PVT, statistical mismatch, noise, +EM/current-density limits, thermal behavior or fabrication signoff. + +## Electrical Requirements and Scoring + +Every required observation must be finite and satisfy its inclusive band; +aggregation cannot hide a failing operating point. A missing dropout crossing +or incomplete extraction/simulation cannot establish success. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +Measurement definitions below use the supplied SPICE node/source names. +`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered +power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs` +denote magnitude, and `cph` is continuous phase in radians. `find`, `when`, +`from/to`, and `rise/fall` retain the deck's interpolation, window and +crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/ +milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` +mean the stated window average, extrema and sampled derivative. All +declared conditions are measured separately and paired with the same +source condition; a group uses its worst paired quality. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension | +| --- | --- | --- | --- | --- | --- | --- | +| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 3.3 | 3.3 | bias | +| `tail_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 3.3 | 3.3 | bias | +| `quiescent_a` | DC operating point: `-i(VDD)-i(VLOAD)`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply | +| `power_w` | DC operating point: `-v(vdd)*i(VDD)-v(vref)*i(VREF)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply | +| `psrr_db` | AC: Value of `(-db(v(vout))) at=1k`. | dB | maximize / db20 | −∞ … +∞ | — | response | +| `peaking_db` | AC: `20*log10((max (mag(v(vout))) from=1 to=100meg)/(find (mag(v(vout))) at=1))`. | dB | minimize / db20 | −∞ … +∞ | — | response | +| `peak_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=0.9m to=3m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response | +| `high_settled_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=1.2m to=1.9m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response | +| `low_settled_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=2.2m to=3m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response | +| `tail_min_v` | TRAN: Minimum of `v(ibias) from=0.9m to=3m`. | V | target / target | 0 … 3.3 | 3.3 | bias | +| `dropout_v` | DC sweep: `(when v(vout)=1.75 rise=1)-1.75`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response | + +Area reference: **7597.32 um2**. 106 expanded device instances; sum of device/contact envelopes 4876.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **7**; it is independent of +the reference-relative task score. + + +### Score weights + +GF180 compact regulator variants: regulation and recovery 36%; rejection and peaking 18%; dropout 18%; quiescent current 9%; internal bias 1.8%; power 7.2%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `high_settled_error_v` | 0.090000000000 | +| `low_settled_error_v` | 0.090000000000 | +| `output_v` | 0.090000000000 | +| `peak_error_v` | 0.090000000000 | +| `peaking_db` | 0.090000000000 | +| `psrr_db` | 0.090000000000 | +| `dropout_v` | 0.180000000000 | +| `quiescent_a` | 0.090000000000 | +| `tail_min_v` | 0.009000000000 | +| `tail_v` | 0.009000000000 | +| `power_w` | 0.072000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 PDK/EDA resources listed in `/protocol/resources.json`. +KLayout checks the layout, Magic extracts RC and ngspice simulates the circuit. +`/protocol/task.json` provides frozen constraints and evaluation requirements; +`/protocol/harness.json` describes the active harness. If `process-feedback` +is exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then explicitly submit the snapshot with +`python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/reference/ldo_004_basic_pmos.gds b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/reference/ldo_004_basic_pmos.gds new file mode 100644 index 0000000000000000000000000000000000000000..572ce6b072f2bfe27a803d9a02b27e151bbbf9f0 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/reference/ldo_004_basic_pmos.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f157eca4fd675b974c112ce48fea323990fdba3222dff9527059fe8624e7e2b8 +size 760286 diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..f940145e63aca0d0d63ffe1dc4cd624473ae3366 --- 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+[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", + "vref", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.0 +load_a = 5e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.0 +load_a = 0.0002 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_a = 5e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +load_a = 0.0002 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +dimension = "bias" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 3.3 +lower = 0 +upper = 3.3 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", + "condition_3:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", + "source_condition_3:output_v", +] + +[[task.evaluation.metrics]] +id = "regulation_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:regulation_error_v", + "condition_1:regulation_error_v", + "condition_2:regulation_error_v", + "condition_3:regulation_error_v", +] +baseline = [ + "source_condition_0:regulation_error_v", + "source_condition_1:regulation_error_v", + "source_condition_2:regulation_error_v", + "source_condition_3:regulation_error_v", +] + +[[task.evaluation.metrics]] +id = "psrr_db" +unit = "dB" +dimension = "response" +direction = "maximize" +normalization = "db20" +aggregation = "max" +category = "performance" +observations = [ + "condition_0:psrr_db", + "condition_1:psrr_db", + "condition_2:psrr_db", + "condition_3:psrr_db", +] +baseline = [ + "source_condition_0:psrr_db", + "source_condition_1:psrr_db", + "source_condition_2:psrr_db", + "source_condition_3:psrr_db", +] + +[[task.evaluation.metrics]] +id = "excursion_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:excursion_v", + "condition_1:excursion_v", + "condition_2:excursion_v", + "condition_3:excursion_v", +] +baseline = [ + "source_condition_0:excursion_v", + "source_condition_1:excursion_v", + "source_condition_2:excursion_v", + "source_condition_3:excursion_v", +] + +[[task.evaluation.metrics]] +id = "recovery_v" +unit = "V" +dimension = "bias" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 3.3 +lower = 0 +upper = 3.3 +category = "performance" +observations = [ + "condition_0:recovery_v", + "condition_1:recovery_v", + "condition_2:recovery_v", + "condition_3:recovery_v", +] +baseline = [ + "source_condition_0:recovery_v", + "source_condition_1:recovery_v", + "source_condition_2:recovery_v", + "source_condition_3:recovery_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", + "condition_3:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", + "source_condition_3:power_w", +] + +[[task.evaluation.metrics]] +id = "minimum_v" +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 0 +category = "performance" +observations = [ + "condition_0:minimum_v", + "condition_1:minimum_v", + "condition_2:minimum_v", + "condition_3:minimum_v", +] + +[[task.evaluation.metrics]] +id = "maximum_v" +unit = "V" +direction = "maximize" +aggregation = "min" +upper = 3.3 +category = "performance" +observations = [ + "condition_0:maximum_v", + "condition_1:maximum_v", + "condition_2:maximum_v", + "condition_3:maximum_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 29565.16 +rationale = "GF180 compact regulator variants: regulation and recovery 52.9%; rejection and peaking 26.5%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +excursion_v = 0.132352941176 +output_v = 0.132352941176 +recovery_v = 0.132352941176 +regulation_error_v = 0.132352941176 +psrr_db = 0.264705882355 +power_w = 0.105882352941 + +[task.evaluation.pre_layout] +source_report_sha256 = "6afae2300ecd26a9ebc93e965f2e52d395aeb29272090387c67937010a5fae4a" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 3.0 +load_a = 5e-05 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "0c944b34efb418c5260805fb1f92d267dfc8eadb4ed5b19225989ea25aa9ed80" +dut = "6c6e1a98fcbc973243d976044bf8537eca4610acf7525954c480789629ed5b5f" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.excursion_v] +value = 5.458571e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.maximum_v] +value = 1.630708 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_v] +value = 1.630653 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.630702610007 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.001282607287639 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.psrr_db] +value = 36.62515 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_v] +value = 1.630703 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.regulation_error_v] +value = 0.03070261000689 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.0 +load_a = 0.0002 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "0c944b34efb418c5260805fb1f92d267dfc8eadb4ed5b19225989ea25aa9ed80" +dut = "6c6e1a98fcbc973243d976044bf8537eca4610acf7525954c480789629ed5b5f" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.excursion_v] +value = 0.0001859917 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.maximum_v] +value = 1.63062 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_v] +value = 1.630434 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 1.630586619566 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.00173231313653 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.psrr_db] +value = 36.6912 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_v] +value = 1.630587 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.regulation_error_v] +value = 0.03058661956566 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 +load_a = 5e-05 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "0c944b34efb418c5260805fb1f92d267dfc8eadb4ed5b19225989ea25aa9ed80" +dut = "6c6e1a98fcbc973243d976044bf8537eca4610acf7525954c480789629ed5b5f" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.excursion_v] +value = 8.356665e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.maximum_v] +value = 1.635135 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_v] +value = 1.635051 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 1.635134792131 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.001697363141666 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.psrr_db] +value = 36.40827 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_v] +value = 1.635135 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.regulation_error_v] +value = 0.03513479213137 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +supply_v = 3.3 +load_a = 0.0002 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +psrr_db = "dB" +excursion_v = "V" +recovery_v = "V" +power_w = "W" +minimum_v = "V" +maximum_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "0c944b34efb418c5260805fb1f92d267dfc8eadb4ed5b19225989ea25aa9ed80" +dut = "6c6e1a98fcbc973243d976044bf8537eca4610acf7525954c480789629ed5b5f" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.excursion_v] +value = 0.000170333 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.maximum_v] +value = 1.634935 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_v] +value = 1.634765 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 1.634932498211 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 0.002191957091852 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.psrr_db] +value = 36.77022 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_v] +value = 1.634932 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.regulation_error_v] +value = 0.03493249821084 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_005_buffered_ref" + +[qualification] +reference = "reference/ldo_005_buffered_ref.gds" + +[presentation] +category = "Power & references" +summary = "Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power." diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..6042f842ffe65c600c7bf62efbe2f8baaa3602b8 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl @@ -0,0 +1,73 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt ldo_005_buffered_ref vdd vout vss vref +C1_0 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_1 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_2 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_3 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_4 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_5 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_6 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_7 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_8 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_9 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_10 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_11 vout vss cap_mim_2f0fF w=20u l=19.23u +C1_12 vout vss cap_mim_2f0fF w=20u l=19.23u +CEAC_0 ea_ncz ea_out cap_mim_2f0fF w=10u l=10u +CRAC_0 ra_ncz v_ref_out cap_mim_2f0fF w=20u l=18.785u +CRAC_1 ra_ncz v_ref_out cap_mim_2f0fF w=20u l=18.785u +CRAC_2 ra_ncz v_ref_out cap_mim_2f0fF w=20u l=18.785u +CRAC_3 ra_ncz v_ref_out cap_mim_2f0fF w=20u l=18.785u +CRAC_4 ra_ncz v_ref_out cap_mim_2f0fF w=20u l=18.785u +CRAC_5 ra_ncz v_ref_out cap_mim_2f0fF w=20u l=18.785u +C_LPF_0 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_1 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_2 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_3 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_4 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_5 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_6 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_7 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_8 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_9 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_10 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_11 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +C_LPF_12 v_lpf_out vss cap_mim_2f0fF w=20u l=19.23u +R1_0 v_ref_out R1_seg1 vss ppolyf_u_1k w=1u l=50u +R1_1 R1_seg1 v_ref_fb vss ppolyf_u_1k w=1u l=50u +R2_0 v_ref_fb R2_seg1 vss ppolyf_u_1k w=1u l=50u +R2_1 R2_seg1 vss vss ppolyf_u_1k w=1u l=50u +R3_0 vout vss vss ppolyf_u_1k w=1u l=10u +REAND_0 ea_na ea_nd vss ppolyf_u_1k w=1u l=50u +REAZ_0 ea_nb ea_ncz vss ppolyf_u_1k w=1u l=28.43u +RRAZ_0 ra_nb ra_ncz vss ppolyf_u_1k w=1u l=30.855u +R_LPF_0 v_ref_out v_lpf_out vss ppolyf_u_1k w=1u l=10u +MMEA_1_0 ea_na v_lpf_out ea_tail vss nfet_06v0 w=68.54u l=0.7u +MMEA_2_0 ea_nb vout ea_tail vss nfet_06v0 w=68.54u l=0.7u +MMEA_3_0 ea_na ea_nd vdd vdd pfet_06v0 w=100u l=0.55u +MMEA_4_0 ea_nlev ea_na ea_nd vdd pfet_06v0 w=10u l=0.55u +MMEA_5_0 ea_nb ea_nd vdd vdd pfet_06v0 w=100u l=0.55u +MMEA_6_0 ea_out ea_nb vdd vdd pfet_06v0 w=14u l=3.835u +MMEA_B0_0 ea_ibias ea_ibias vss vss nfet_06v0 w=34.535u l=2u +MMEA_BC_0 ea_tail ea_ibias vss vss nfet_06v0 w=34.535u l=2u +MMEA_BF_0 ea_nlev ea_ibias vss vss nfet_06v0 w=5u l=2u +MMEA_BO_0 ea_out ea_ibias vss vss nfet_06v0 w=34.535u l=2u +MMEA_BP_0 ea_ibias ea_ibias vdd vdd pfet_06v0 w=6.31u l=2u +MMP_0 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMP_1 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMP_2 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMP_3 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMP_4 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMP_5 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMP_6 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +MMRA_1_0 ra_na v_ref_fb ra_tail vss nfet_06v0 w=86.42u l=0.7u +MMRA_2_0 ra_nb vref ra_tail vss nfet_06v0 w=86.42u l=0.7u +MMRA_3_0 ra_na ra_na vdd vdd pfet_06v0 w=20u l=1u +MMRA_4_0 ra_nb ra_na vdd vdd pfet_06v0 w=20u l=1u +MMRA_5_0 v_ref_out ra_nb vdd vdd pfet_06v0 w=37.76u l=2.645u +MMRA_B0_0 ra_ibias ra_ibias vss vss nfet_06v0 w=12u l=2u +MMRA_BC_0 ra_tail ra_ibias vss vss nfet_06v0 w=8.315u l=2u +MMRA_BO_0 v_ref_out ra_ibias vss vss nfet_06v0 w=4u l=2u +MMRA_BP_0 ra_ibias ra_ibias vdd vdd pfet_06v0 w=10.845u l=2u +.ends ldo_005_buffered_ref diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..b02ad251062354797dfaafc9b5884acbf524d6f0 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.spice @@ -0,0 +1,73 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt ldo_005_buffered_ref vdd vout vss vref +XC1_0 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_1 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_2 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_3 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_4 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_5 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_6 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_7 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_8 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_9 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_10 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_11 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC1_12 vout vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XCEAC_0 ea_ncz ea_out cap_mim_2f0_m4m5_noshield c_width=10u c_length=10u +XCRAC_0 ra_ncz v_ref_out cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCRAC_1 ra_ncz v_ref_out cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCRAC_2 ra_ncz v_ref_out cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCRAC_3 ra_ncz v_ref_out cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCRAC_4 ra_ncz v_ref_out cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XCRAC_5 ra_ncz v_ref_out cap_mim_2f0_m4m5_noshield c_width=20u c_length=18.785u +XC_LPF_0 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_1 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_2 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_3 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_4 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_5 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_6 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_7 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_8 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_9 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_10 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_11 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XC_LPF_12 v_lpf_out vss cap_mim_2f0_m4m5_noshield c_width=20u c_length=19.23u +XR1_0 v_ref_out R1_seg1 vss ppolyf_u_1k r_width=1u r_length=50u +XR1_1 R1_seg1 v_ref_fb vss ppolyf_u_1k r_width=1u r_length=50u +XR2_0 v_ref_fb R2_seg1 vss ppolyf_u_1k r_width=1u r_length=50u +XR2_1 R2_seg1 vss vss ppolyf_u_1k r_width=1u r_length=50u +XR3_0 vout vss vss ppolyf_u_1k r_width=1u r_length=10u +XREAND_0 ea_na ea_nd vss ppolyf_u_1k r_width=1u r_length=50u +XREAZ_0 ea_nb ea_ncz vss ppolyf_u_1k r_width=1u r_length=28.43u +XRRAZ_0 ra_nb ra_ncz vss ppolyf_u_1k r_width=1u r_length=30.855u +XR_LPF_0 v_ref_out v_lpf_out vss ppolyf_u_1k r_width=1u r_length=10u +XMEA_1_0 ea_na v_lpf_out ea_tail vss nfet_06v0 w=68.54u l=0.7u +XMEA_2_0 ea_nb vout ea_tail vss nfet_06v0 w=68.54u l=0.7u +XMEA_3_0 ea_na ea_nd vdd vdd pfet_06v0 w=100u l=0.55u +XMEA_4_0 ea_nlev ea_na ea_nd vdd pfet_06v0 w=10u l=0.55u +XMEA_5_0 ea_nb ea_nd vdd vdd pfet_06v0 w=100u l=0.55u +XMEA_6_0 ea_out ea_nb vdd vdd pfet_06v0 w=14u l=3.835u +XMEA_B0_0 ea_ibias ea_ibias vss vss nfet_06v0 w=34.535u l=2u +XMEA_BC_0 ea_tail ea_ibias vss vss nfet_06v0 w=34.535u l=2u +XMEA_BF_0 ea_nlev ea_ibias vss vss nfet_06v0 w=5u l=2u +XMEA_BO_0 ea_out ea_ibias vss vss nfet_06v0 w=34.535u l=2u +XMEA_BP_0 ea_ibias ea_ibias vdd vdd pfet_06v0 w=6.31u l=2u +XMP_0 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMP_1 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMP_2 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMP_3 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMP_4 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMP_5 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMP_6 vout ea_out vdd vdd pfet_06v0 w=20u l=0.6u +XMRA_1_0 ra_na v_ref_fb ra_tail vss nfet_06v0 w=86.42u l=0.7u +XMRA_2_0 ra_nb vref ra_tail vss nfet_06v0 w=86.42u l=0.7u +XMRA_3_0 ra_na ra_na vdd vdd pfet_06v0 w=20u l=1u +XMRA_4_0 ra_nb ra_na vdd vdd pfet_06v0 w=20u l=1u +XMRA_5_0 v_ref_out ra_nb vdd vdd pfet_06v0 w=37.76u l=2.645u +XMRA_B0_0 ra_ibias ra_ibias vss vss nfet_06v0 w=12u l=2u +XMRA_BC_0 ra_tail ra_ibias vss vss nfet_06v0 w=8.315u l=2u +XMRA_BO_0 v_ref_out ra_ibias vss vss nfet_06v0 w=4u l=2u +XMRA_BP_0 ra_ibias ra_ibias vdd vdd pfet_06v0 w=10.845u l=2u +.ends ldo_005_buffered_ref diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..f62c35b77aaae0f2da1b42d6a0acd68df03434f8 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/schematic.svg @@ -0,0 +1,2 @@ +ldo_005_buffered_ref{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_005_buffered_ref","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl","netlist_sha256":"1e1c14a91036bf5d0069bcc2a22f99e65c5f6a0a963377cc1e0ff2120293c9ff","project_sha256":"7920413129596dbbbfd9a6c8dc10eab4323675be46b561dd9920eca706f3dd77","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"flat-cdl-project: independent source/project flattened device comparison, schema parse, symbol resolution and netlist export.","license":"licenses/gf180mcuD/analog-db/","sheets":["ldo_005_buffered_ref","MMP_bank1","XC1_bank2","XCRAC_bank3","XC_LPF_bank4"],"banks":[{"name":"MMP_bank1","devices":7,"source_references":["MMP_0","MMP_1","MMP_2","MMP_3","MMP_4","MMP_5","MMP_6"]},{"name":"XC1_bank2","devices":13,"source_references":["C1_0","C1_1","C1_2","C1_3","C1_4","C1_5","C1_6","C1_7","C1_8","C1_9","C1_10","C1_11","C1_12"]},{"name":"XCRAC_bank3","devices":6,"source_references":["CRAC_0","CRAC_1","CRAC_2","CRAC_3","CRAC_4","CRAC_5"]},{"name":"XC_LPF_bank4","devices":13,"source_references":["C_LPF_0","C_LPF_1","C_LPF_2","C_LPF_3","C_LPF_4","C_LPF_5","C_LPF_6","C_LPF_7","C_LPF_8","C_LPF_9","C_LPF_10","C_LPF_11","C_LPF_12"]}],"limitations":["Structured labelled overview, not a manually composed functional schematic. Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":9},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_005_buffered_ref"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/schematic/ldo_005_buffered_ref.icproj.json"}}Main-sheet overview; 4 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_005_buffered_refvoutvssvssv_lpf_outvddvoutea_outra_nczv_ref_outea_nczea_nbra_nczra_nbea_outv_ref_outv_lpf_outvssv_lpf_outea_naea_tailvoutvssea_nbea_tailvddvddea_naea_ndv_ref_outvddea_naea_ndea_nlevvddvddea_ndea_nbR1_seg1vddvddea_outea_nbvssvssea_ibiasea_ibiasvssvssea_tailea_ibiasvssvssea_nlevea_ibiasR1_seg1vssvssea_outea_ibiasvddvddea_ibiasea_ibiasv_ref_fbvssv_ref_fbra_nara_tailvssvrefra_nbra_tailvddvddra_nara_navddvddra_nbra_nav_ref_fbvddvddv_ref_outra_nbvssvssra_ibiasra_ibiasvssR2_seg1vssra_tailra_ibiasvssvssv_ref_outra_ibiasvddvddra_ibiasra_ibiasvddvoutea_outvoutvssvssra_nczv_ref_outvssv_lpf_outvddvoutvssvrefR2_seg1voutea_nczvssea_naea_ndldo_005_buffered_refEqual net labels connect. All source devices and exact parameters are retained.CEAC_0cap_mim_2f0fFw=10u l=10uR1_0ppolyf_u_1kw=1u l=50uSubstrate: B=vssR1_1ppolyf_u_1kw=1u l=50uSubstrate: B=vssR2_0ppolyf_u_1kw=1u l=50uSubstrate: B=vssR2_1ppolyf_u_1kw=1u l=50uSubstrate: B=vssR3_0ppolyf_u_1kw=1u l=10uSubstrate: B=vssREAND_0ppolyf_u_1kw=1u l=50uSubstrate: B=vssREAZ_0ppolyf_u_1kw=1u l=28.43uSubstrate: B=vssRRAZ_0ppolyf_u_1kw=1u l=30.855uSubstrate: B=vssR_LPF_0ppolyf_u_1kw=1u l=10uSubstrate: B=vssMMEA_1_0nfet_06v0w=68.54u l=0.7uMMEA_2_0nfet_06v0w=68.54u l=0.7uMMEA_3_0pfet_06v0w=100u l=0.55uMMEA_4_0pfet_06v0w=10u l=0.55uMMEA_5_0pfet_06v0w=100u l=0.55uMMEA_6_0pfet_06v0w=14u l=3.835uMMEA_B0_0nfet_06v0w=34.535u l=2uMMEA_BC_0nfet_06v0w=34.535u l=2uMMEA_BF_0nfet_06v0w=5u l=2uMMEA_BO_0nfet_06v0w=34.535u l=2uMMEA_BP_0pfet_06v0w=6.31u l=2uMMRA_1_0nfet_06v0w=86.42u l=0.7uMMRA_2_0nfet_06v0w=86.42u l=0.7uMMRA_3_0pfet_06v0w=20u l=1uMMRA_4_0pfet_06v0w=20u l=1uMMRA_5_0pfet_06v0w=37.76u l=2.645uMMRA_B0_0nfet_06v0w=12u l=2uMMRA_BC_0nfet_06v0w=8.315u l=2uMMRA_BO_0nfet_06v0w=4u l=2uMMRA_BP_0pfet_06v0w=10.845u l=2uXMMP_bank1MMP_bank1XXC1_bank2XC1_bank2XXCRAC_bank3XCRAC_bank3XXC_LPF_bank4XC_LPF_bank4 +Main-sheet overview; 4 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..e0bd1cc078de81ced661fb5fb11a32f66cf29670 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/testbench.spice @@ -0,0 +1,33 @@ +* Buffered-reference LDO: nominal regulation and load-step observations. +* SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 DC {supply_v} AC 1 +VREF vref 0 .8 +ILOAD vout 0 DC {load_a} PULSE({load_a} {2*load_a} 100u 1u 1u 100u 500u) +CLOAD vout 0 1u +XDUT vdd vout 0 vref ldo_005_buffered_ref +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let regulation_error_v=abs(output_v-1.6) +let power_w=-v(vdd)*i(vdd) +print output_v regulation_error_v power_w +write op.raw +ac dec 80 1 1Meg +let rejection_db=-db(v(vout)) +meas ac psrr_db find rejection_db at=1k +write ac.raw +tran .1u 500u +meas tran minimum_v min v(vout) from=90u to=500u +meas tran maximum_v max v(vout) from=90u to=500u +meas tran excursion_v pp v(vout) from=90u to=500u +meas tran recovery_v avg v(vout) from=400u to=500u +write transient.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/problem.md b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..d6790c6b3b759c29945f49e28b5faca131ed63ab --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/problem.md @@ -0,0 +1,116 @@ +# Buffered-Reference LDO Layout Task + +## Objective + +Implement `ldo_005_buffered_ref` as a GF180MCU D layout. The fixed upstream GF180 6 V circuit combines its self-biased reference amplifier, gain-two reference divider, RC low-pass filter, self-biased error amplifier, PMOS pass device, bleeder and on-die output capacitor. The two inlined amplifiers retain this LDO accession's own dimensions and compensation values; they are not replaced by the standalone amplifier cases. + + +## Inputs and Interface + +`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` +contains matching native simulator wrappers. `materials/testbench.spice` defines +all measurements. Ordered ports: `vdd vout vss vref`. + +`vdd/vss`: supply and return; `vout`: regulated output; `vref`: external 0.8 V reference. The upstream ideal VREF becomes test apparatus at this explicit port. Its zero-volt VLP loop marker becomes a wire to the output; no physical functional element is removed. The reference divider, RC filter, bleeder and four internal capacitors remain inside the DUT. External load and output capacitor remain test apparatus. + +## Operating Conditions + +Typical native models at 27 C, statistics disabled. All four combinations of 3.0/3.3 V supply and 50/200 uA DC load are evaluated, with a 0.8 V external reference and 1 uF external output load. AC supply injection spans 1 Hz–1 MHz, 80 points/decade. The load doubles at 100 us and returns after 100 us, with 1 us edges; transient evaluation ends at 500 us with 0.1 us requested steps. This is steady-state load-step characterization, not cold-start or dropout qualification. + +## Physical Requirements + +GDS database unit 0.001 um, maximum 10 MiB, top cell `ldo_005_buffered_ref`. +Native standalone DRC covers geometry, connectivity, manufacturing grid, dummy +fill and antenna; chip-level density and seal-ring closure are excluded. +LVS must match all devices, parameters and named ports. Metal1 labels identify +ports. The functional bounding rectangle includes the device, well, implant, +contact, passive and complete routing layers enumerated in the runtime outline; +text annotations are excluded. Maximum outline is 5000 by 1000 um. + +6 V MOS minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS. Only subminimum lengths are raised, and dimensions are quantized to 5 nm. Passives use 1 kohm/square poly, with series segmentation, and 2 fF/um2 MIM-B on M4/M5, with parallel tiling. Source and extracted candidates use the same native layer-specific capacitor models. Geometry, parasitic effects and physical values are authoritative; no ideal R/C replacements are made during post-layout simulation. + +Candidate-derived native Magic coupling capacitance and distributed wire +resistance feed post-layout simulation, with zero omission thresholds. +Physical MOS diffusion areas/perimeters come from the layout. Substrate/well +connections are ideal: distributed substrate resistance/noise and inductance +are not represented. Nominal DC regulation, 1 kHz supply rejection and load-step excursion/recovery across four supply/load points. Coefficient 7 reflects interacting regulation stages and recovery across loads. Noise, loop return-ratio, cold start, dropout, PVT and statistical yield are outside this declared scope. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition | Unit | Dimension | Normalization | +| --- | --- | --- | --- | --- | +| `output_v` | DC regulated output | V | bias | target | +| `regulation_error_v` | Absolute DC error relative to 1.6 V | V | response | ratio | +| `psrr_db` | Negative 20 log10 magnitude of supply-to-output response at 1 kHz | dB | response | db20 | +| `excursion_v` | Output maximum minus minimum over 90–500 us | V | response | ratio | +| `recovery_v` | Mean output over 400–500 us after the load returns | V | bias | target | +| `power_w` | DC supply power -VDD*I(VDD) | W | supply | ratio | +| `minimum_v` | Minimum transient output over 90–500 us | V | functional | unscored | +| `maximum_v` | Maximum transient output over 90–500 us | V | functional | unscored | + +Output and recovered output must be in 0–3.3 V; the transient minimum must be nonnegative and the maximum at most 3.3 V. Supply power and absolute/range errors must be nonnegative. These are supply-domain and physical measurement constraints. Accuracy, rejection and recovery differences enter continuous scoring; no upstream regulation target is a hard gate. +Every condition must complete; missing, nonfinite or wrong-unit observations +produce an evaluation error. Upstream advertised performance is not a +qualification requirement. + +Scored observations pair with independent source jobs using the identical +stimuli, parameters, models and backend. Target scales are 3.3 V; ratio floors +are 1 pW for power and 1 mV for error/excursion. These are normalization units, +not allowed degradation. `db20` compares +amplitude ratios. + +Area anchor **29565.16 um2** uses a 18964.964200 um2 sum of expanded +`(W+2)*(L+2)` device/contact envelopes, a 50% routing allowance and 2 um outer +margin: `ceil(100*(1.5*sum+8*sqrt(sum)+16))/100`. It is independent of witness +area and is an engineering estimate, not a foundry minimum. Coefficient **7** +is independent of this score. + + +### Score weights + +GF180 compact regulator variants: regulation and recovery 52.9%; rejection and peaking 26.5%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `excursion_v` | 0.132352941176 | +| `output_v` | 0.132352941176 | +| `recovery_v` | 0.132352941176 | +| `regulation_error_v` | 0.132352941176 | +| `psrr_db` | 0.264705882355 | +| `power_w` | 0.105882352941 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Read `/protocol/task.json`, `/protocol/resources.json` and +`/protocol/harness.json`. KLayout performs physical checks, Magic extracts the +candidate, and ngspice measures it. Use `process-feedback` if exposed. +Write `/workspace/output/final.gds`, then explicitly submit using +`python -I /protocol/submit.py`. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/reference/ldo_005_buffered_ref.gds b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/reference/ldo_005_buffered_ref.gds new file mode 100644 index 0000000000000000000000000000000000000000..4d1cb3e4e81f46dcee9ec54e37522a97f1d8fc42 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/reference/ldo_005_buffered_ref.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1a4f484845ab2ac229cdaec01be69ad3af07623866f8de8c2981f370ad9f98d8 +size 2144584 diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..360321ea9fa171b2152d19fa810a164367f0f796 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml @@ -0,0 +1,1035 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.ldo_006_stub" +title = "Divider-Biased NMOS Source Follower" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "2ae742ba538a1dd6c31b2d131f78895825123bf949cbdc1783a0f6f3f73aa571" + +[[assets]] +path = "reference/ldo_006_stub.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "7b8cbe36c0f7f829b4b4849ff304dccbb9842e843a35f3e94c27faeef3dba91f" + +[task] +hours = 6 +kind = "netlist_to_gds" +family = "physical_core" +coefficient = 3 +environment = "gf180mcuD-mos-rc-tt" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "a3c9df08c3a9444b5155d88b3b72269f03fb546933e425141ec0b944383c97fc" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +format = "spice" +sha256 = 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"check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply = 1.2 +load = 100000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply = 1.2 +load = 1000000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply = 1.5 +load = 100000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply = 1.5 +load = 1000000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +aggregation = "max" +direction = "target" +dimension = "bias" +normalization = "target" +scale = 0.1 +lower = 0 +upper = 1.5 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", + "condition_3:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", + "source_condition_3:output_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +aggregation = "max" +direction = "minimize" +dimension = "supply" +normalization = "ratio" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", + "condition_3:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", + "source_condition_3:power_w", +] + +[[task.evaluation.metrics]] +id = "step_shift_v" +unit = "V" +aggregation = "max" +direction = "target" +dimension = "response" +normalization = "target" +scale = 0.1 +category = "performance" +observations = [ + "condition_0:step_shift_v", + "condition_1:step_shift_v", + "condition_2:step_shift_v", + "condition_3:step_shift_v", +] +baseline = [ + "source_condition_0:step_shift_v", + "source_condition_1:step_shift_v", + "source_condition_2:step_shift_v", + "source_condition_3:step_shift_v", +] + +[[task.evaluation.metrics]] +id = "ripple_v" +unit = "V" +aggregation = "max" +direction = "minimize" +lower = 0 +category = "performance" +observations = [ + "condition_0:ripple_v", + "condition_1:ripple_v", + "condition_2:ripple_v", + "condition_3:ripple_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 1200 +rationale = "Regulator stub: loaded operating point 34%; load response 34%; power 17%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +output_v = 0.34 +step_shift_v = 0.34 +power_w = 0.17 + +[task.evaluation.pre_layout] +source_report_sha256 = "d94ba804cdff2b078f8cf6de6fc71b07f5781ec0bc41b46a085ba2ad9410e5c5" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply = 1.2 +load = 100000.0 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "c97bbafc088195064829a85602604effaaa2255844497445b39823a5555a810b" +dut = "3c6789457bc622df1c4811b6fa2436d31b314999e060bdfc0443b84766570c0a" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.05755748327764071 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 7.891038427252645e-06 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] +value = 1.558476e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_shift_v] +value = -0.0244887432776407 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply = 1.2 +load = 1000000.0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "c97bbafc088195064829a85602604effaaa2255844497445b39823a5555a810b" +dut = "3c6789457bc622df1c4811b6fa2436d31b314999e060bdfc0443b84766570c0a" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 0.1049486282284016 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 7.326287027635482e-06 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.ripple_v] +value = 7.960358e-11 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_shift_v] +value = -0.0645835182284016 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply = 1.5 +load = 100000.0 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "c97bbafc088195064829a85602604effaaa2255844497445b39823a5555a810b" +dut = "3c6789457bc622df1c4811b6fa2436d31b314999e060bdfc0443b84766570c0a" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 0.143184566600803 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 1.339831443967738e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.ripple_v] +value = 6.911138e-15 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_shift_v] +value = -0.014338166600803 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" +loaded = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +supply = 1.5 +load = 1000000.0 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +power_w = "W" +step_shift_v = "V" +ripple_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +transient = "transient.raw" +loaded = "loaded.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "c97bbafc088195064829a85602604effaaa2255844497445b39823a5555a810b" +dut = "3c6789457bc622df1c4811b6fa2436d31b314999e060bdfc0443b84766570c0a" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 0.1998588147024911 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 1.155033319339639e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.ripple_v] +value = 6.303291e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_shift_v] +value = -0.050102114702491 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_006_stub" + +[qualification] +reference = "reference/ldo_006_stub.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Tracks an input bias with a divider-biased NMOS source follower." diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..1b989e9b684137fd2c117409d627d6a1edcb5055 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl @@ -0,0 +1,9 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt ldo_006_stub vdd vout vss +R1_0 vdd R1_seg1 vss ppolyf_u_1k w=1u l=48.44u +R1_1 R1_seg1 vref vss ppolyf_u_1k w=1u l=48.44u +R2_0 vref R2_seg1 vss ppolyf_u_1k w=1u l=48.44u +R2_1 R2_seg1 vss vss ppolyf_u_1k w=1u l=48.44u +MM1_0 vdd vref vout vss nfet_03v3 w=50u l=0.5u +.ends ldo_006_stub diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..8688f54c2a55e9b608dc8031246a615331267a3c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.spice @@ -0,0 +1,9 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt ldo_006_stub vdd vout vss +XR1_0 vdd R1_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XR1_1 R1_seg1 vref vss ppolyf_u_1k r_width=1u r_length=48.44u +XR2_0 vref R2_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XR2_1 R2_seg1 vss vss ppolyf_u_1k r_width=1u r_length=48.44u +XM1_0 vdd vref vout vss nfet_03v3 w=50u l=0.5u +.ends ldo_006_stub diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..e355b2d4cdbcdb59d0c343bd9464a528f1174aaa --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/schematic.svg @@ -0,0 +1,2 @@ +ldo_006_stub{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_006_stub","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl","netlist_sha256":"b2cbf5b0cf0497af8ad62bded31556d61ed2d15ff665966e7e8e5e7772a58aa3","project_sha256":"bfd60b6f5cabc0002c4d615eb9d4396d917cb10d0f74389af2d04bae37c8ebe0","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"flat-cdl-project: independent source/project flattened device comparison, schema parse, symbol resolution and netlist export.","license":"licenses/gf180mcuD/analog-db/","sheets":["ldo_006_stub"],"banks":[],"limitations":["Structured labelled overview, not a manually composed functional schematic. Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":4},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_006_stub"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/schematic/ldo_006_stub.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.ldo_006_stubR1_seg1R1_seg1vrefvrefR2_seg1vssR2_seg1vddvoutvssvrefvddvddvoutvssldo_006_stubEqual net labels connect. All source devices and exact parameters are retained.R1_0ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssR1_1ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssR2_0ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssR2_1ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssMM1_0nfet_03v3w=50u l=0.5u +Complete single-sheet circuit. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..887e4370c56f1a2b590bd104f1871d52a3bc6992 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/testbench.spice @@ -0,0 +1,40 @@ +* Independently authored measurement fixture; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.options klu reltol=1e-6 abstol=1e-13 vntol=1e-9 +.temp 27 +VDD vdd 0 {supply} +VSS vss 0 0 +RL vout 0 {load} +CL vout 0 10p +ISTEP vout 0 PULSE(0 1u 2u 20n 20n 20u 40u) +XDUT vdd vout vss ldo_006_stub +.control +set numdgt=15 +set measdgt=15 +op +let kcl_residual=abs(i(vdd)+i(vss)+v(vout)/@rl[resistance]) +if kcl_residual > 1e-10 + echo Error: external DC KCL failed + quit 1 +end +let output_v=v(vout) +let power_w=-v(vdd)*i(vdd) +let initial=v(vout) +print output_v power_w +show all +write op.raw all +tran 2n 10u 0 2n +meas tran final_v avg v(vout) from=8u to=10u +meas tran ripple_v pp v(vout) from=8u to=10u +let step_shift_v=final_v-op1.initial +print step_shift_v +write transient.raw all +alter ISTEP 1u +op +show all +write loaded.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/problem.md b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..a221c0e337bf1d519abd92cc7ca9cf8814d8e80b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/problem.md @@ -0,0 +1,77 @@ +# Divider-Biased NMOS Source Follower Layout Task + +## Objective + +A single fixed 50/0.5 um nfet_03v3 (m=1) forms a source follower. Its drain connects to vdd, source to vout, body to vss, and gate to the midpoint of the internal 100 kohm/100 kohm supply divider. Each resistor uses two native ppolyf_u_1k segments, totaling 99995.18 ohm at TT/27 C. There is no control input, external reference, error amplifier or closed-loop regulator. Target top cell: `ldo_006_stub`. + +## Inputs and Interface + +`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (drain and divider supply), vout (source output), vss (body/divider return). + +## Operating Conditions + +GF180 TT, 27 C. Supply is independently 1.2 or 1.5 V; output load is independently 100 kohm or 1 Mohm, in parallel with 10 pF. A 1 uA sink turns on at 2 us with a 20 ns edge and stays on throughout the 10 us run. Maximum step is 2 ns. The initial state has zero additional sink current and is computed by DC OP. A separate loaded DC OP with a 1 uA sink is compared with the 8–10 us transient endpoint. Supply power includes the divider, transistor and resistive load. + +## Physical Requirements + +Use GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Unit | Definition | Bound | Quality | +| --- | --- | --- | --- | --- | +| `output_v` | V | DC loaded source-follower output | 0 to 1.5 | bias: target, target, scale=0.1 | +| `power_w` | W | DC power including internal 100k/100k divider | 0 to unbounded | supply: ratio, minimize, scale=1e-12 | +| `step_shift_v` | V | Mean output at 8–10 us minus initial output | unbounded to unbounded | response: target, target, scale=0.1 | +| `ripple_v` | V | Peak-to-peak output over final 2 us | 0 to unbounded | diagnostic / functional only | + +Only output operating point, finite load-step shift and actual supply loss are scored. Late-window ripple is an unscored diagnostic; sub-nanovolt ripple is below numerical voltage resolution. No regulation accuracy, PSRR, dropout or loop-margin claim is made. The model guide includes 50 um width as a pseudo-device scaling boundary, not a directly measured width sample. + +Static output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances. + +For each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation. + +Compact area anchor: 1200 um2 = 50 × 6 um2 pass-device/contact envelope + 4 × 55 × 2 um2 resistor/contact/isolation envelopes + 460 um2 routing/guard-ring allowance. It is a compact engineering estimate independent of witness sparsity. Coefficient 3: local analog bias/transfer and controlled load response. The circuit and these anchors are fixed before participant evaluation. + + +### Score weights + +Regulator stub: loaded operating point 34%; load response 34%; power 17%; area 15%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.15 | +| `output_v` | 0.340000000000 | +| `step_shift_v` | 0.340000000000 | +| `power_w` | 0.170000000000 | + +## Tools and Submission + +Solve budget: **6 hours**. + +Use the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/reference/ldo_006_stub.gds b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/reference/ldo_006_stub.gds new file mode 100644 index 0000000000000000000000000000000000000000..3aef912ee532c92c489a41ee851944e4ae02d6b6 Binary files /dev/null and b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/reference/ldo_006_stub.gds differ diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..0e2ad039cbbf975ae6685185c65c637220466099 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml @@ -0,0 +1,1749 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.ldo_007_pmos" +title = "PMOS LDO with Feedforward Compensation" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "e3471a69953ad187a43a47fe2955445ba61977e6c9c684182e2d7cbacea5c9dd" + +[[assets]] +path = "reference/ldo_007_pmos.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "3f0f52d09797298309ed93cf98a22fa46923f825e2ee06f9e0f11d376c9f70dd" + +[task] +hours = 8 +kind = "netlist_to_gds" +family = "ldo" +coefficient = 7 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "b8a0d1353178d4f1244262a331bd6441717ea3627b207f36f6b7502a63c3b783" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +format = "spice" +sha256 = "4b3f01ca7600933022e7730cc7cfb614b7abcc2808f7ef777b0019b27514382a" +subcircuit = "ldo_007_pmos" + +[task.inputs.simulation] +path = "materials/circuit.spice" +format = "spice" +sha256 = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.inputs.performance] +path = "materials/testbench.spice" +format = "spice" +sha256 = "2fb6d165d253676d8a3765b4d9fd419edb250fe21010c2c82e802345a4bb1775" + +[task.inputs.startup] +path = "materials/startup.spice" +format = "spice" +sha256 = "5c9f480b2cd83f84efd261cadf6fe56eddfc1da8b15cc092994e33ebb72e6c90" + +[task.inputs.regulation] +path = "materials/regulation.spice" +format = "spice" +sha256 = "5683574723b1f857bddf3b5c6b667dc338edb66a9c2c4df18b0b742bb822f891" + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "ldo_007_pmos" +max_bytes = 10485760 + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 5, + 0, + ], + [ + 11, + 17, + ], + [ + 11, + 39, + ], + [ + 12, + 0, + ], + [ + 13, + 17, + ], + [ + 21, + 0, + ], + [ + 22, + 0, + ], + [ + 22, + 4, + ], + [ + 24, + 0, + ], + [ + 24, + 5, + ], + [ + 30, + 0, + ], + [ + 30, + 4, + ], + [ + 31, + 0, + ], + [ + 32, + 0, + ], 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+ 110, + 16, + ], + [ + 111, + 5, + ], + [ + 112, + 1, + ], + [ + 115, + 5, + ], + [ + 116, + 5, + ], + [ + 117, + 5, + ], + [ + 117, + 10, + ], + [ + 118, + 5, + ], + [ + 119, + 5, + ], + [ + 122, + 5, + ], + [ + 123, + 5, + ], + [ + 124, + 5, + ], + [ + 125, + 5, + ], + [ + 127, + 5, + ], + [ + 128, + 17, + ], + [ + 137, + 5, + ], + [ + 151, + 5, + ], + [ + 152, + 5, + ], + [ + 153, + 51, + ], + [ + 166, + 5, + ], + [ + 167, + 5, + ], + [ + 173, + 5, + ], + [ + 178, + 0, + ], + [ + 183, + 0, + ], + [ + 184, + 0, + ], + [ + 185, + 0, + ], + [ + 204, + 0, + ], + [ + 210, + 0, + ], + [ + 220, + 0, + ], + [ + 226, + 0, + ], + [ + 227, + 0, + ], + [ + 241, + 0, + ], +] +max_width_um = 20000 +max_height_um = 2000 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", + "ebias", + "vref", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0.001 +do_static = 0 + +[task.evaluation.jobs.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0.1 +load_step_a = 0 +do_static = 0 + +[task.evaluation.jobs.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.jobs.parameters.exports] +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 1.9000000000000001 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_4" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 1.8 +load_a = 0.002 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_5" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:startup" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.measurements] +startup_final_v = "V" +startup_ripple_v = "V" +startup_min_v = "V" +startup_max_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_6" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:regulation" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +line = "ngspice-raw" +load = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 + +[task.evaluation.jobs.parameters.measurements] +line_reg_v_per_v = "V/V" +load_reg_ohm = "ohm" +kcl_a = "A" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +line = "line.raw" +load = "load.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +dimension = "bias" +direction = "target" +normalization = "target" +aggregation = "max" +scale = 1.2 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_3:output_v", + "condition_4:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_3:output_v", + "source_condition_4:output_v", +] + +[[task.evaluation.metrics]] +id = "regulation_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:regulation_error_v", + "condition_3:regulation_error_v", + "condition_4:regulation_error_v", +] +baseline = [ + "source_condition_0:regulation_error_v", + "source_condition_3:regulation_error_v", + "source_condition_4:regulation_error_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_3:power_w", + "condition_4:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_3:power_w", + "source_condition_4:power_w", +] + +[[task.evaluation.metrics]] +id = "psrr_db" +unit = "dB" +dimension = "response" +direction = "maximize" +normalization = "db20" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:psrr_db", + "condition_3:psrr_db", + "condition_4:psrr_db", +] +baseline = [ + "source_condition_0:psrr_db", + "source_condition_3:psrr_db", + "source_condition_4:psrr_db", +] + +[[task.evaluation.metrics]] +id = "quiet_ripple_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:quiet_ripple_v", + "condition_1:quiet_ripple_v", + "condition_2:quiet_ripple_v", + "condition_3:quiet_ripple_v", + "condition_4:quiet_ripple_v", +] +baseline = [ + "source_condition_0:quiet_ripple_v", + "source_condition_1:quiet_ripple_v", + "source_condition_2:quiet_ripple_v", + "source_condition_3:quiet_ripple_v", + "source_condition_4:quiet_ripple_v", +] + +[[task.evaluation.metrics]] +id = "recovery_ripple_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:recovery_ripple_v", + "condition_1:recovery_ripple_v", + "condition_2:recovery_ripple_v", + "condition_3:recovery_ripple_v", + "condition_4:recovery_ripple_v", +] +baseline = [ + "source_condition_0:recovery_ripple_v", + "source_condition_1:recovery_ripple_v", + "source_condition_2:recovery_ripple_v", + "source_condition_3:recovery_ripple_v", + "source_condition_4:recovery_ripple_v", +] + +[[task.evaluation.metrics]] +id = "excursion_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:excursion_v", + "condition_1:excursion_v", + "condition_2:excursion_v", + "condition_3:excursion_v", + "condition_4:excursion_v", +] +baseline = [ + "source_condition_0:excursion_v", + "source_condition_1:excursion_v", + "source_condition_2:excursion_v", + "source_condition_3:excursion_v", + "source_condition_4:excursion_v", +] + +[[task.evaluation.metrics]] +id = "late_error_v" +unit = "V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_0:late_error_v", + "condition_1:late_error_v", + "condition_2:late_error_v", + "condition_3:late_error_v", + "condition_4:late_error_v", +] +baseline = [ + "source_condition_0:late_error_v", + "source_condition_1:late_error_v", + "source_condition_2:late_error_v", + "source_condition_3:late_error_v", + "source_condition_4:late_error_v", +] + +[[task.evaluation.metrics]] +id = "mean_power_w" +unit = "W" +dimension = "supply" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:mean_power_w", + "condition_1:mean_power_w", + "condition_2:mean_power_w", + "condition_3:mean_power_w", + "condition_4:mean_power_w", +] +baseline = [ + "source_condition_0:mean_power_w", + "source_condition_1:mean_power_w", + "source_condition_2:mean_power_w", + "source_condition_3:mean_power_w", + "source_condition_4:mean_power_w", +] + +[[task.evaluation.metrics]] +id = "quiet_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:quiet_v", + "condition_1:quiet_v", + "condition_2:quiet_v", + "condition_3:quiet_v", + "condition_4:quiet_v", +] + +[[task.evaluation.metrics]] +id = "high_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:high_v", + "condition_1:high_v", + "condition_2:high_v", + "condition_3:high_v", + "condition_4:high_v", +] + +[[task.evaluation.metrics]] +id = "recovery_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_0:recovery_v", + "condition_1:recovery_v", + "condition_2:recovery_v", + "condition_3:recovery_v", + "condition_4:recovery_v", +] + +[[task.evaluation.metrics]] +id = "startup_final_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_final_v", +] + +[[task.evaluation.metrics]] +id = "startup_ripple_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_ripple_v", +] + +[[task.evaluation.metrics]] +id = "startup_min_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_min_v", +] + +[[task.evaluation.metrics]] +id = "startup_max_v" +unit = "V" +direction = "minimize" +aggregation = "min" +category = "performance" +observations = [ + "condition_5:startup_max_v", +] + +[[task.evaluation.metrics]] +id = "line_reg_v_per_v" +unit = "V/V" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 0.001 +lower = 0 +category = "performance" +observations = [ + "condition_6:line_reg_v_per_v", +] +baseline = [ + "source_condition_6:line_reg_v_per_v", +] + +[[task.evaluation.metrics]] +id = "load_reg_ohm" +unit = "ohm" +dimension = "response" +direction = "minimize" +normalization = "ratio" +aggregation = "max" +scale = 1 +lower = 0 +category = "performance" +observations = [ + "condition_6:load_reg_ohm", +] +baseline = [ + "source_condition_6:load_reg_ohm", +] + +[[task.evaluation.metrics]] +id = "kcl_a" +unit = "A" +direction = "minimize" +aggregation = "max" +category = "performance" +observations = [ + "condition_0:kcl_a", + "condition_3:kcl_a", + "condition_4:kcl_a", + "condition_6:kcl_a", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 98448.9 +rationale = "GF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +line_reg_v_per_v = 0.075 +load_reg_ohm = 0.075 +output_v = 0.075 +regulation_error_v = 0.075 +excursion_v = 0.149999999999 +late_error_v = 0.15 +psrr_db = 0.066666666667 +quiet_ripple_v = 0.066666666667 +recovery_ripple_v = 0.066666666667 +mean_power_w = 0.05 +power_w = 0.05 + +[task.evaluation.pre_layout] +source_report_sha256 = "bde16f6d10904507bd25d6a6ee35eaf18275a988ce7d59c80cd4d1a0241f5d31" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "2fb6d165d253676d8a3765b4d9fd419edb250fe21010c2c82e802345a4bb1775" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.excursion_v] +value = 9.012568e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] +value = 7.979727989493313e-17 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] +value = 0.001163794 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] +value = 0.002062008 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 1.201163794209656 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.002062007670219242 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.psrr_db] +value = 69.12994 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.quiet_ripple_v] +value = 8.641088e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.quiet_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_ripple_v] +value = 5.587975e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.regulation_error_v] +value = 0.001163794209655622 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0.001 +do_static = 0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "2fb6d165d253676d8a3765b4d9fd419edb250fe21010c2c82e802345a4bb1775" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.excursion_v] +value = 0.002793266 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.high_v] +value = 1.200529 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.late_error_v] +value = 0.001163794 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] +value = 0.002516498 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.quiet_ripple_v] +value = 8.641088e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.quiet_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_ripple_v] +value = 8.698153e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0.1 +load_step_a = 0 +do_static = 0 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "2fb6d165d253676d8a3765b4d9fd419edb250fe21010c2c82e802345a4bb1775" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.excursion_v] +value = 0.0006708494 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.high_v] +value = 1.201135 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.late_error_v] +value = 0.001163794 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] +value = 0.002090937 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.quiet_ripple_v] +value = 8.641088e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.quiet_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_ripple_v] +value = 1.048317e-11 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_v] +value = 1.201164 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +supply_v = 1.9000000000000001 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "2fb6d165d253676d8a3765b4d9fd419edb250fe21010c2c82e802345a4bb1775" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.excursion_v] +value = 8.138823e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.high_v] +value = 1.201135 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.kcl_a] +value = 2.775557561562891e-17 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.late_error_v] +value = 0.001134769 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.mean_power_w] +value = 0.002176579 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 1.201134769436585 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 0.002176578905089857 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.psrr_db] +value = 72.36333 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.quiet_ripple_v] +value = 8.623768e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.quiet_v] +value = 1.201135 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_ripple_v] +value = 6.195044e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_v] +value = 1.201135 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.regulation_error_v] +value = 0.001134769436585303 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_4.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_4.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.values] +supply_v = 1.8 +load_a = 0.002 +line_step_v = 0 +load_step_a = 0 +do_static = 1 + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.measurements] +output_v = "V" +regulation_error_v = "V" +power_w = "W" +psrr_db = "dB" +quiet_ripple_v = "V" +recovery_ripple_v = "V" +excursion_v = "V" +late_error_v = "V" +mean_power_w = "W" +quiet_v = "V" +high_v = "V" +recovery_v = "V" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] +deck = "2fb6d165d253676d8a3765b4d9fd419edb250fe21010c2c82e802345a4bb1775" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.excursion_v] +value = 8.252732e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.high_v] +value = 1.200529 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.kcl_a] +value = 2.294605477848322e-15 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.late_error_v] +value = 0.0005290752 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.mean_power_w] +value = 0.003861969 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] +value = 1.200529075214 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] +value = 0.003861968612576786 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.psrr_db] +value = 79.12494 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.quiet_ripple_v] +value = 7.41629e-14 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.quiet_v] +value = 1.200529 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_ripple_v] +value = 7.818191e-12 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_v] +value = 1.200529 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.regulation_error_v] +value = 0.0005290752139999189 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_5.inputs] +deck = "input:startup" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_5.outputs] +op = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.values] + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.measurements] +startup_final_v = "V" +startup_ripple_v = "V" +startup_min_v = "V" +startup_max_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.exports] +op = "op.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] +deck = "5c9f480b2cd83f84efd261cadf6fe56eddfc1da8b15cc092994e33ebb72e6c90" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_final_v] +value = 1.201163 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_max_v] +value = 1.211155 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_min_v] +value = 3.334193e-38 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_ripple_v] +value = 1.089706e-11 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_6.inputs] +deck = "input:regulation" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_6.outputs] +op = "ngspice-raw" +line = "ngspice-raw" +load = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.values] +supply_v = 1.8 +load_a = 0.001 +line_step_v = 0 +load_step_a = 0 + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.measurements] +line_reg_v_per_v = "V/V" +load_reg_ohm = "ohm" +kcl_a = "A" + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.exports] +op = "op.raw" +line = "line.raw" +load = "load.raw" + +[task.evaluation.pre_layout.jobs.source_condition_6.input_sha256] +deck = "5683574723b1f857bddf3b5c6b667dc338edb66a9c2c4df18b0b742bb822f891" +dut = "e5d2e14418cc92ea27f4c6b197e6cae06a5e66cf1e225f60a5bb090c74a42d69" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.kcl_a] +value = 7.979727989493313e-17 +unit = "A" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.line_reg_v_per_v] +value = 0.0002902477307031859 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.load_reg_ohm] +value = 0.6347189956414923 +unit = "ohm" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_007_pmos" + +[qualification] +reference = "reference/ldo_007_pmos.gds" + +[presentation] +category = "Power & references" +summary = "Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power." diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..95cd3d579a1fc2f8ac8961ca74c8b05c40b2d203 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl @@ -0,0 +1,240 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt ldo_007_pmos vdd vout vss ebias vref +CC_0 ncz vout cap_mim_2f0fF w=10u l=2.5u +CFF_0 vout fb cap_mim_2f0fF w=20u l=20u +CFF_1 vout fb cap_mim_2f0fF w=20u l=20u +CFF_2 vout fb cap_mim_2f0fF w=20u l=20u +CFF_3 vout fb cap_mim_2f0fF w=20u l=20u +CFF_4 vout fb cap_mim_2f0fF w=20u l=20u +CFF_5 vout fb cap_mim_2f0fF w=20u l=20u +CFF_6 vout fb cap_mim_2f0fF w=20u l=20u +CFF_7 vout fb cap_mim_2f0fF w=20u l=20u +CFF_8 vout fb cap_mim_2f0fF w=20u l=20u +CFF_9 vout fb cap_mim_2f0fF w=20u l=20u +CFF_10 vout fb cap_mim_2f0fF w=20u l=20u +CFF_11 vout fb cap_mim_2f0fF w=20u l=20u +CFF_12 vout fb cap_mim_2f0fF w=20u l=20u +CFF_13 vout fb cap_mim_2f0fF w=20u l=20u +CFF_14 vout fb cap_mim_2f0fF w=20u l=20u +CFF_15 vout fb cap_mim_2f0fF w=20u l=20u +CFF_16 vout fb cap_mim_2f0fF w=20u l=20u +CFF_17 vout fb cap_mim_2f0fF w=20u l=20u +CFF_18 vout fb cap_mim_2f0fF w=20u l=20u +CFF_19 vout fb cap_mim_2f0fF w=20u l=20u +CFF_20 vout fb cap_mim_2f0fF w=20u l=20u +CFF_21 vout fb cap_mim_2f0fF w=20u l=20u +CFF_22 vout fb cap_mim_2f0fF w=20u l=20u +CFF_23 vout fb cap_mim_2f0fF w=20u l=20u +CFF_24 vout fb cap_mim_2f0fF w=20u l=20u +CFF_25 vout fb cap_mim_2f0fF w=20u l=20u +CFF_26 vout fb cap_mim_2f0fF w=20u l=20u +CFF_27 vout fb cap_mim_2f0fF w=20u l=20u +CFF_28 vout fb cap_mim_2f0fF w=20u l=20u +CFF_29 vout fb cap_mim_2f0fF w=20u l=20u +CFF_30 vout fb cap_mim_2f0fF w=20u l=20u +CFF_31 vout fb cap_mim_2f0fF w=20u l=20u +CFF_32 vout fb cap_mim_2f0fF w=20u l=20u +CFF_33 vout fb cap_mim_2f0fF w=20u l=20u +CFF_34 vout fb cap_mim_2f0fF w=20u l=20u +CFF_35 vout fb cap_mim_2f0fF w=20u l=20u +CFF_36 vout fb cap_mim_2f0fF w=20u l=20u +CFF_37 vout fb cap_mim_2f0fF w=20u l=20u +CFF_38 vout fb cap_mim_2f0fF w=20u l=20u +CFF_39 vout fb cap_mim_2f0fF w=20u l=20u +CFF_40 vout fb cap_mim_2f0fF w=20u l=20u +CFF_41 vout fb cap_mim_2f0fF w=20u l=20u +CFF_42 vout fb cap_mim_2f0fF w=20u l=20u +CFF_43 vout fb cap_mim_2f0fF w=20u l=20u +CFF_44 vout fb cap_mim_2f0fF w=20u l=20u +CFF_45 vout fb cap_mim_2f0fF w=20u l=20u +CFF_46 vout fb cap_mim_2f0fF w=20u l=20u +CFF_47 vout fb cap_mim_2f0fF w=20u l=20u +CFF_48 vout fb cap_mim_2f0fF w=20u l=20u +CFF_49 vout fb cap_mim_2f0fF w=20u l=20u +CFF_50 vout fb cap_mim_2f0fF w=20u l=20u +CFF_51 vout fb cap_mim_2f0fF w=20u l=20u +CFF_52 vout fb cap_mim_2f0fF w=20u l=20u +CFF_53 vout fb cap_mim_2f0fF w=20u l=20u +CFF_54 vout fb cap_mim_2f0fF w=20u l=20u +CFF_55 vout fb cap_mim_2f0fF w=20u l=20u +CFF_56 vout fb cap_mim_2f0fF w=20u l=20u +CFF_57 vout fb cap_mim_2f0fF w=20u l=20u +CFF_58 vout fb cap_mim_2f0fF w=20u l=20u +CFF_59 vout fb cap_mim_2f0fF w=20u l=20u +CFF_60 vout fb cap_mim_2f0fF w=20u l=20u +CFF_61 vout fb cap_mim_2f0fF w=20u l=20u +CFF_62 vout fb cap_mim_2f0fF w=20u l=20u +CFF_63 vout fb cap_mim_2f0fF w=20u l=20u +CFF_64 vout fb cap_mim_2f0fF w=20u l=20u +CFF_65 vout fb cap_mim_2f0fF w=20u l=20u +CFF_66 vout fb cap_mim_2f0fF w=20u l=20u +CFF_67 vout fb cap_mim_2f0fF w=20u l=20u +CFF_68 vout fb cap_mim_2f0fF w=20u l=20u +CFF_69 vout fb cap_mim_2f0fF w=20u l=20u +CFF_70 vout fb cap_mim_2f0fF w=20u l=20u +CFF_71 vout fb cap_mim_2f0fF w=20u l=20u +CFF_72 vout fb cap_mim_2f0fF w=20u l=20u +CFF_73 vout fb cap_mim_2f0fF w=20u l=20u +CFF_74 vout fb cap_mim_2f0fF w=20u l=20u +R1_0 vout fb vss ppolyf_u_1k w=1u l=4.695u +R2_0 fb vss vss ppolyf_u_1k w=1u l=33.86u +MM1_0 noutm fb etail vss nfet_03v3 w=16u l=0.5u +MM2_0 egate vref etail vss nfet_03v3 w=16u l=0.5u +MM3_0 noutm noutm vdd vdd pfet_03v3 w=25u l=0.5u +MM4_0 egate noutm vdd vdd pfet_03v3 w=25u l=0.5u +MM5_0 etail ebias vss vss nfet_03v3 w=48u l=0.5u +MM6_0 ebias ebias vss vss nfet_03v3 w=48u l=0.5u +MMP_0 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_1 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_2 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_3 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_4 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_5 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_6 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_7 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_8 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_9 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_10 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_11 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_12 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_13 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_14 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_15 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_16 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_17 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_18 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_19 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_20 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_21 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_22 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_23 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_24 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_25 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_26 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_27 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_28 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_29 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_30 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_31 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_32 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_33 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_34 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_35 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_36 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_37 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_38 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_39 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_40 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_41 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_42 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_43 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_44 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_45 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_46 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_47 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_48 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_49 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_50 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_51 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_52 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_53 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_54 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_55 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_56 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_57 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_58 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_59 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_60 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_61 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_62 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_63 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_64 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_65 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_66 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_67 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_68 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_69 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_70 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_71 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_72 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_73 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_74 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_75 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_76 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_77 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_78 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_79 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_80 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_81 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_82 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_83 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_84 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_85 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_86 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_87 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_88 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_89 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_90 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_91 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_92 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_93 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_94 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_95 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_96 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_97 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_98 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_99 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_100 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_101 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_102 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_103 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_104 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_105 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_106 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_107 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_108 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_109 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_110 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_111 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_112 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_113 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_114 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_115 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_116 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_117 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_118 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_119 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_120 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_121 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_122 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_123 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_124 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_125 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_126 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_127 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_128 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_129 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_130 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_131 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_132 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_133 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_134 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_135 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_136 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_137 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_138 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +MMP_139 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +RZ_0 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_1 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_2 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_3 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_4 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_5 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_6 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_7 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_8 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_9 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_10 egate ncz vss ppolyf_u_1k w=97.21u l=1u +RZ_11 egate ncz vss ppolyf_u_1k w=97.21u l=1u +.ends ldo_007_pmos diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..66036a2d3dd3fec277925f17a60e8c8b21cf90bf --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.spice @@ -0,0 +1,240 @@ +* Derived from pinned analog-db; Copyright 2026 Danial Noori Zadeh. +* See collection license; 5 nm geometry, physical R/C, explicit interface. +.subckt ldo_007_pmos vdd vout vss ebias vref +XCC_0 ncz vout cap_mim_2f0_m4m5_noshield c_width=10u c_length=2.5u +XCFF_0 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_1 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_2 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_3 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_4 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_5 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_6 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_7 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_8 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_9 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_10 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_11 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_12 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_13 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_14 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_15 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_16 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_17 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_18 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_19 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_20 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_21 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_22 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_23 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_24 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_25 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_26 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_27 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_28 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_29 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_30 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_31 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_32 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_33 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_34 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_35 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_36 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_37 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_38 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_39 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_40 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_41 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_42 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_43 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_44 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_45 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_46 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_47 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_48 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_49 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_50 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_51 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_52 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_53 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_54 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_55 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_56 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_57 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_58 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_59 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_60 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_61 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_62 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_63 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_64 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_65 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_66 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_67 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_68 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_69 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_70 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_71 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_72 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_73 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XCFF_74 vout fb cap_mim_2f0_m4m5_noshield c_width=20u c_length=20u +XR1_0 vout fb vss ppolyf_u_1k r_width=1u r_length=4.695u +XR2_0 fb vss vss ppolyf_u_1k r_width=1u r_length=33.86u +XM1_0 noutm fb etail vss nfet_03v3 w=16u l=0.5u +XM2_0 egate vref etail vss nfet_03v3 w=16u l=0.5u +XM3_0 noutm noutm vdd vdd pfet_03v3 w=25u l=0.5u +XM4_0 egate noutm vdd vdd pfet_03v3 w=25u l=0.5u +XM5_0 etail ebias vss vss nfet_03v3 w=48u l=0.5u +XM6_0 ebias ebias vss vss nfet_03v3 w=48u l=0.5u +XMP_0 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_1 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_2 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_3 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_4 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_5 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_6 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_7 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_8 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_9 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_10 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_11 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_12 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_13 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_14 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_15 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_16 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_17 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_18 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_19 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_20 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_21 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_22 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_23 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_24 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_25 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_26 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_27 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_28 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_29 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_30 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_31 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_32 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_33 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_34 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_35 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_36 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_37 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_38 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_39 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_40 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_41 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_42 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_43 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_44 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_45 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_46 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_47 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_48 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_49 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_50 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_51 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_52 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_53 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_54 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_55 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_56 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_57 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_58 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_59 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_60 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_61 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_62 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_63 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_64 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_65 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_66 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_67 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_68 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_69 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_70 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_71 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_72 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_73 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_74 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_75 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_76 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_77 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_78 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_79 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_80 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_81 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_82 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_83 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_84 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_85 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_86 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_87 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_88 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_89 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_90 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_91 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_92 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_93 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_94 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_95 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_96 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_97 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_98 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_99 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_100 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_101 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_102 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_103 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_104 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_105 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_106 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_107 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_108 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_109 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_110 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_111 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_112 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_113 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_114 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_115 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_116 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_117 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_118 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_119 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_120 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_121 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_122 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_123 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_124 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_125 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_126 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_127 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_128 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_129 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_130 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_131 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_132 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_133 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_134 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_135 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_136 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_137 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_138 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XMP_139 vout egate vdd vdd pfet_03v3 w=20u l=0.5u +XRZ_0 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_1 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_2 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_3 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_4 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_5 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_6 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_7 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_8 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_9 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_10 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +XRZ_11 egate ncz vss ppolyf_u_1k r_width=97.21u r_length=1u +.ends ldo_007_pmos diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/regulation.spice b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/regulation.spice new file mode 100644 index 0000000000000000000000000000000000000000..2636b0df35ff6e1f1733f21e1221b3825db0c69f --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/regulation.spice @@ -0,0 +1,37 @@ +* Regulator nominal and finite-window perturbation observations. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.save v(vdd) v(vss) v(vout) v(cout) v(vref) i(vdd) i(vss) i(vref) v(ebias) @iload[current] +VSS vss 0 0 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 dc {supply_v} ac 1 pulse({supply_v} {supply_v+line_step_v} 100u 1u 1u 100u 500u) +IBIAS vdd ebias 60u +VREF vref 0 1.05 +ILOAD vout 0 dc {load_a} pulse({load_a} {load_a+load_step_a} 100u 1u 1u 100u 500u) +RESR vout cout .1 +COUT cout 0 1n +XDUT vdd vout vss ebias vref ldo_007_pmos +.control +set numdgt=15 +op +let kcl_a=abs(i(vdd)+i(vss)+i(vref)+@iload[current]) +* Current conservation validates the observation, not circuit performance. +if kcl_a > 1e-08 + echo Invalid DC current conservation: kcl_a exceeds 1e-08 A + quit 1 +end +print kcl_a +write op.raw all +dc VDD 1.8 1.9000000000000001 .01 +let line_reg_v_per_v=abs((v(vout)[length(v(vout))-1]-v(vout)[0])/.1) +print line_reg_v_per_v +write line.raw all +dc ILOAD .001 .002 .0001 +let load_reg_ohm=abs((v(vout)[length(v(vout))-1]-v(vout)[0])/.001) +print load_reg_ohm +write load.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..70a77df377a2934e18f2278240ec3548ef7b77ed --- /dev/null +++ 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Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":14},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_007_pmos"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/schematic/ldo_007_pmos.icproj.json"}}Main-sheet overview; 8 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_007_pmosvoutfbvssnczegatevddvoutegatevddnoutmnoutmvddvddnoutmnczegatevssvssebiasetailvssvssebiasebiasvddvoutegatevoutfbvoutvssnczegatevddvoutvssebiasvreffbvssfbvssfbnoutmetailvssvrefvoutetailegatevddldo_007_pmosEqual net labels connect. All source devices and exact parameters are retained.CC_0cap_mim_2f0fFw=10u l=2.5uR1_0ppolyf_u_1kw=1u l=4.695uSubstrate: B=vssR2_0ppolyf_u_1kw=1u l=33.86uSubstrate: B=vssMM1_0nfet_03v3w=16u l=0.5uMM2_0nfet_03v3w=16u l=0.5uMM3_0pfet_03v3w=25u l=0.5uMM4_0pfet_03v3w=25u l=0.5uMM5_0nfet_03v3w=48u l=0.5uMM6_0nfet_03v3w=48u l=0.5uXMMP_bank1MMP_bank1XXCFF_bank2XCFF_bank2XXRZ_bank3XRZ_bank3 +Main-sheet overview; 8 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/startup.spice b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/startup.spice new file mode 100644 index 0000000000000000000000000000000000000000..b7a167757356277b53bef0253cda61a796df5618 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/startup.spice @@ -0,0 +1,29 @@ +* Regulator nominal and finite-window perturbation observations. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.save v(vdd) v(vss) v(vout) v(cout) v(vref) i(vdd) i(vss) i(vref) v(ebias) +VSS vss 0 0 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 PWL(0 0 10u 1.8 400u 1.8) +IBIAS vdd ebias 60u +VREF vref 0 1.05 +RLOAD vout 0 1200.0 +RESR vout cout .1 +COUT cout 0 1n +XDUT vdd vout vss ebias vref ldo_007_pmos +.control +set numdgt=15 +set measdgt=15 +op +write op.raw all +tran 10n 400u 0 10n +meas tran startup_final_v avg v(vout) from=380u to=400u +meas tran startup_ripple_v pp v(vout) from=380u to=400u +meas tran startup_min_v min v(vout) from=0 to=400u +meas tran startup_max_v max v(vout) from=0 to=400u +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..8baa30d6d119fff0e60aab460459b8cad58089e7 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/testbench.spice @@ -0,0 +1,48 @@ +* Regulator nominal and finite-window perturbation observations. +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +.save v(vdd) v(vss) v(vout) v(cout) v(vref) i(vdd) i(vss) i(vref) v(ebias) @iload[current] +VSS vss 0 0 +.options reltol=1e-6 abstol=1e-13 vntol=1e-9 +VDD vdd 0 dc {supply_v} ac 1 pulse({supply_v} {supply_v+line_step_v} 100u 1u 1u 100u 500u) +IBIAS vdd ebias 60u +VREF vref 0 1.05 +ILOAD vout 0 dc {load_a} pulse({load_a} {load_a+load_step_a} 100u 1u 1u 100u 500u) +RESR vout cout .1 +COUT cout 0 1n +XDUT vdd vout vss ebias vref ldo_007_pmos +.csparam do_static={do_static} +.control +set numdgt=15 +set measdgt=15 +if $&do_static +op +let kcl_a=abs(i(vdd)+i(vss)+i(vref)+@iload[current]) +print kcl_a +let output_v=v(vout) +let regulation_error_v=abs(v(vout)-1.2) +let power_w=-v(vdd)*i(vdd) +print output_v regulation_error_v power_w +write op.raw all +ac dec 100 1 100Meg +let rejection=-db(v(vout)) +meas ac psrr_db find rejection at=1k +write ac.raw all +end +tran 10n 400u 0 10n +let err=abs(v(vout)-1.2) +let supply_power=-v(vdd)*i(vdd) +meas tran quiet_v avg v(vout) from=80u to=100u +meas tran quiet_ripple_v pp v(vout) from=80u to=100u +meas tran high_v avg v(vout) from=180u to=200u +meas tran recovery_v avg v(vout) from=380u to=400u +meas tran recovery_ripple_v pp v(vout) from=380u to=400u +meas tran excursion_v pp v(vout) from=100u to=400u +meas tran late_error_v avg err from=380u to=400u +meas tran mean_power_w avg supply_power from=0 to=400u +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..2a48b68da0ea9cedefa8b0595c193c1e3ad7cda8 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md @@ -0,0 +1,112 @@ +# PMOS LDO with Feedforward Compensation Layout Task + +## Objective + +Implement `ldo_007_pmos` as a GDS layout preserving the complete declared circuit. Five-transistor error amplifier, NMOS bias diode and PMOS pass array with complete resistive feedback divider, feedforward CFF across the upper divider, and series RZ/CC across the pass stage. Seven bound MOS expand to 146 units. The 0 V VLP feedback marker becomes a wire; ideal reference and current bias remain external apparatus. + +## Inputs and Interface + +- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface. +- `materials/circuit.spice`: equivalent source simulation, including physical passives. +- `materials/testbench.spice`: performance observations. +- `materials/startup.spice`: startup observations. +- `materials/regulation.spice`: regulation observations. +- `problem.md`: this contract. + +Ordered ports: `vdd vout vss ebias vref`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs. + +## Operating Conditions + +Nominal supply 1.8 V, external reference 1.05 V and 60 uA from VDD into ebias; 27 C, typical GF180 3.3 V models with statistics disabled. Rtop=5 kohm and Rbottom=35 kohm set nominal output 1.2 V. The 140-fold pass array retains 20 um width and 0.5 um length per unit. CFF=60 pF, CC=0.05 pF and RZ=1 ohm are retained. RZ uses twelve parallel native high-poly units (L=1 um, W=97.21 um), nominal 1.000096 ohm at 27 C, to avoid an impossible sub-grid resistor length. No compensation is deleted. External reference-generation and current-source implementation losses are excluded; the 60 uA drawn from VDD and physical divider are included in rail power. External output capacitance is 1 nF with 0.1 ohm series ESR. Evaluate no disturbance, 1-to-2 mA load pulse, and +0.1 V input pulse, plus independent DC points at nominal+0.1 V/1 mA and nominal/2 mA. Pulses start at 100 us, have 1 us edges and 100 us high width; restoration finishes at 202 us. Observe 0–400 us with 10 ns maximum step; pre-step/high/recovery windows are 80–100/180–200/380–400 us. Supply rejection is measured at 1 kHz from a 1 V AC supply input (100 samples/decade, 1 Hz–100 MHz). Ascending DC sweeps cover nominal supply to nominal+0.1 V in 10 mV increments at 1 mA and 1–2 mA load in 0.1 mA increments at nominal supply; adjustment metrics are absolute endpoint slopes. These are finite ranges, not dropout measurements. Startup ramps VDD from zero to nominal in 10 us with fixed external references and a resistive 1 mA nominal load (target voltage/1 mA); it uses the ordinary initial DC solution, no UIC or forced initial output, and observes through 400 us. Startup extrema and late-window output/ripple are diagnostics. No dropout, loop gain or phase margin is claimed. Source and candidate use identical decks and parameters; no numerical shunt is used. + +## Physical Requirements + +GF180MCU D native standalone-block FEOL/BEOL, connectivity, grid, dummy and antenna rules; chip density/seal-ring rules are outside this block boundary. Named-port LVS and candidate-derived distributed Magic RC are required. Functional area includes active/poly, passives and all routing metal/vias. Capacitor substrate and resistor terminal models follow the frozen PDK profile. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 20000 by 2000 um; they bound the supported block footprint, not electrical quality. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Unit | Definition | Assignment | +|---|---|---|---| +| output_v | V | DC output | bias; target (scale 1.2) | +| regulation_error_v | V | Absolute DC setpoint error | response; ratio (scale 0.001) | +| power_w | W | Total input rail DC power, including physical bleed/divider and external current bias | supply; ratio (scale 1e-12) | +| psrr_db | dB | Input supply rejection at 1 kHz | response; db20 | +| quiet_ripple_v | V | Peak-to-peak pre-perturbation output 80–100 us | response; ratio (scale 0.001) | +| recovery_ripple_v | V | Peak-to-peak recovered output 380–400 us | response; ratio (scale 0.001) | +| excursion_v | V | Full output range 100–400 us | response; ratio (scale 0.001) | +| late_error_v | V | Mean absolute setpoint error 380–400 us | response; ratio (scale 0.001) | +| mean_power_w | W | Mean input rail power 0–400 us | supply; ratio (scale 1e-12) | +| quiet_v | V | Finite-window quiet_v | diagnostic; unscored | +| high_v | V | Finite-window high_v | diagnostic; unscored | +| recovery_v | V | Finite-window recovery_v | diagnostic; unscored | +| startup_final_v | V | 10 us input ramp with resistive load: startup_final_v | diagnostic; unscored | +| startup_ripple_v | V | 10 us input ramp with resistive load: startup_ripple_v | diagnostic; unscored | +| startup_min_v | V | 10 us input ramp with resistive load: startup_min_v | diagnostic; unscored | +| startup_max_v | V | 10 us input ramp with resistive load: startup_max_v | diagnostic; unscored | +| line_reg_v_per_v | V/V | Absolute ascending supply-sweep endpoint slope, nominal to nominal + 0.1 V, 1 mA load | response; ratio (scale 0.001) | +| load_reg_ohm | ohm | Absolute ascending load-sweep endpoint slope, 1 to 2 mA, nominal supply | response; ratio (scale 1) | +| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored | + +All required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores. + +Each scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude. + +Area anchor: 98448.9 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. For ordinary GF180 resistors this envelope conservatively uses the sheet-only length before contact correction; the explicit parallel 1-ohm bank uses its native dimensions. This is an analytical compact-area anchor, not the witness footprint. + +Coefficient 7 covers regulation, frequency response and recovery across loads. No on-chip reference/bias generator is claimed. No loop-gain measurement is used, so CFF cannot bypass a purported loop break. The native resistor model includes terminal resistance in both source and candidate. + + +### Score weights + +GF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `line_reg_v_per_v` | 0.075000000000 | +| `load_reg_ohm` | 0.075000000000 | +| `output_v` | 0.075000000000 | +| `regulation_error_v` | 0.075000000000 | +| `excursion_v` | 0.149999999999 | +| `late_error_v` | 0.150000000000 | +| `psrr_db` | 0.066666666667 | +| `quiet_ripple_v` | 0.066666666667 | +| `recovery_ripple_v` | 0.066666666667 | +| `mean_power_w` | 0.050000000000 | +| `power_w` | 0.050000000000 | + +## Tools and Submission + +Solve budget: **8 hours**. + +Use the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `ldo_007_pmos`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools. + +The source and extracted-candidate decks require absolute external DC current +conservation residual `kcl_a <= 1e-08 A`. A larger residual aborts +simulation and produces an evaluator error with unknown score, rather than a +functional rejection. The reported residual is an unscored diagnostic. diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/reference/ldo_007_pmos.gds b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/reference/ldo_007_pmos.gds new file mode 100644 index 0000000000000000000000000000000000000000..efdca39d39664ea79c6db227b3a9a450384fd7ec --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/reference/ldo_007_pmos.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3f0f52d09797298309ed93cf98a22fa46923f825e2ee06f9e0f11d376c9f70dd +size 6886444 diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..45831566c47e49de799e944cafce2f2c0ce7972b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml @@ -0,0 +1,1109 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.sup_001_vcm_detector" +title = "Passive Resistive Common-Mode Averager" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "7b3cd6f9763e777a824813b266141d52ecb5103d9e4fd56a29db1fcfa5c94303" + +[[assets]] +path = "reference/sup_001_vcm_detector.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "63f34ce151c5d05757b6d15f6b316a265cac2bd7a568d889318a6b8584b08067" + +[task] +hours = 6 +kind = "netlist_to_gds" +family = "physical_core" +coefficient = 4 +environment = "gf180mcuD-mos-rc-tt" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "d463ec5e3f76ff76e6bfa8568ab48401b265ca538c12ecc34d1567b31c8e96ce" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +format = "spice" +sha256 = "c0cdf0e12dbdbfc2e7d1fd9fe3c061a29f745efd8656e1a85e100036489db523" +subcircuit = "sup_001_vcm_detector" + +[task.inputs.simulation] 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+layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vcm_out", + "vinp", + "vinn", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +cm = 0.6 +dm = 0.4 +acn = 1 +load = 1000000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +cm = 0.6 +dm = 0.4 +acn = -1 +load = 1000000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +cm = 0.6 +dm = 0.4 +acn = 1 +load = 1000000000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +cm = 0.6 +dm = 0.4 +acn = -1 +load = 1000000000.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +aggregation = "max" +direction = "target" +dimension = "bias" +normalization = "target" +scale = 0.1 +lower = 0 +upper = 0.8 +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", + "condition_3:output_v", +] +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", + "source_condition_3:output_v", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +aggregation = "max" +direction = "minimize" +dimension = "supply" +normalization = "ratio" +scale = 1e-12 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", + "condition_3:power_w", +] +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", + "source_condition_3:power_w", +] + +[[task.evaluation.metrics]] +id = "gain" +unit = "1" +aggregation = "max" +direction = "target" +dimension = "response" +normalization = "target" +scale = 1 +category = "performance" +observations = [ + "condition_0:gain", + "condition_1:gain", + "condition_2:gain", + "condition_3:gain", +] +baseline = [ + "source_condition_0:gain", + "source_condition_1:gain", + "source_condition_2:gain", + "source_condition_3:gain", +] + +[[task.evaluation.metrics]] +id = "gain_10khz" +unit = "1" +aggregation = "max" +direction = "target" +dimension = "response" +normalization = "target" +scale = 1 +category = "performance" +observations = [ + "condition_0:gain_10khz", + "condition_1:gain_10khz", + "condition_2:gain_10khz", + "condition_3:gain_10khz", +] +baseline = [ + "source_condition_0:gain_10khz", + "source_condition_1:gain_10khz", + "source_condition_2:gain_10khz", + "source_condition_3:gain_10khz", +] + +[[task.evaluation.metrics]] +id = "step_error_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 1e-06 +lower = 0 +category = "performance" +observations = [ + "condition_0:step_error_v", + "condition_1:step_error_v", + "condition_2:step_error_v", + "condition_3:step_error_v", +] +baseline = [ + "source_condition_0:step_error_v", + "source_condition_1:step_error_v", + "source_condition_2:step_error_v", + "source_condition_3:step_error_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 6000 +rationale = "Common-mode sensing/controllers: recovery and error 40.5%; signed transfer 31.5%; output bias 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +step_error_v = 0.405 +gain = 0.1575 +gain_10khz = 0.1575 +output_v = 0.045 +power_w = 0.135 + +[task.evaluation.pre_layout] +source_report_sha256 = "d4d00fe90f779513437ee05134dc7f0695b9df5809fede1b2362c1a3452b810f" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +cm = 0.6 +dm = 0.4 +acn = 1 +load = 1000000.0 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "8e7c108e5bd613ec035f19d1774ddbc207f427855379cc1345ce12e920016925" +dut = "944820f6938c6c618a1c6c178d730c23f613e5f83cff5539ace671a1db64356a" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain] +value = 0.6664552 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_10khz] +value = 0.6662918 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.3998731340795595 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 3.198478091135087e-07 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_error_v] +value = 0.0007150141371111816 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +cm = 0.6 +dm = 0.4 +acn = -1 +load = 1000000.0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "8e7c108e5bd613ec035f19d1774ddbc207f427855379cc1345ce12e920016925" +dut = "944820f6938c6c618a1c6c178d730c23f613e5f83cff5539ace671a1db64356a" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain] +value = 2.400499e-13 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz] +value = 1.011667e-12 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 0.3998731340795595 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 3.198478091135087e-07 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_error_v] +value = 0.0007150141371111816 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +cm = 0.6 +dm = 0.4 +acn = 1 +load = 1000000000.0 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "8e7c108e5bd613ec035f19d1774ddbc207f427855379cc1345ce12e920016925" +dut = "944820f6938c6c618a1c6c178d730c23f613e5f83cff5539ace671a1db64356a" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain] +value = 0.9994998 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_10khz] +value = 0.9989494 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 0.5996998646854883 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 8.02837485826182e-08 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_error_v] +value = 0.004027116328761684 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +ac = "ngspice-raw" +transient = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +cm = 0.6 +dm = 0.4 +acn = -1 +load = 1000000000.0 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +power_w = "W" +gain = "1" +gain_10khz = "1" +step_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +ac = "ac.raw" +transient = "transient.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "8e7c108e5bd613ec035f19d1774ddbc207f427855379cc1345ce12e920016925" +dut = "944820f6938c6c618a1c6c178d730c23f613e5f83cff5539ace671a1db64356a" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain] +value = 8.370837e-13 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain_10khz] +value = 4.846298e-13 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 0.5996998646854883 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 8.02837485826182e-08 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_error_v] +value = 0.004027116328761684 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sup_001_vcm_detector" + +[qualification] +reference = "reference/sup_001_vcm_detector.gds" + +[presentation] +category = "Amplifiers & RF" +summary = "Averages two input voltages through a passive resistive common-mode network." diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..4174e9fd92ec94669bbb03b5c61671e996473417 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl @@ -0,0 +1,44 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt sup_001_vcm_detector vcm_out vinp vinn vss +RMN_0 vinn RMN_seg1 vss ppolyf_u_1k w=1u l=48.44u +RMN_1 RMN_seg1 RMN_seg2 vss ppolyf_u_1k w=1u l=48.44u +RMN_2 RMN_seg2 RMN_seg3 vss ppolyf_u_1k w=1u l=48.44u +RMN_3 RMN_seg3 RMN_seg4 vss ppolyf_u_1k w=1u l=48.44u +RMN_4 RMN_seg4 RMN_seg5 vss ppolyf_u_1k w=1u l=48.44u +RMN_5 RMN_seg5 RMN_seg6 vss ppolyf_u_1k w=1u l=48.44u +RMN_6 RMN_seg6 RMN_seg7 vss ppolyf_u_1k w=1u l=48.44u +RMN_7 RMN_seg7 RMN_seg8 vss ppolyf_u_1k w=1u l=48.44u +RMN_8 RMN_seg8 RMN_seg9 vss ppolyf_u_1k w=1u l=48.44u +RMN_9 RMN_seg9 RMN_seg10 vss ppolyf_u_1k w=1u l=48.44u +RMN_10 RMN_seg10 RMN_seg11 vss ppolyf_u_1k w=1u l=48.44u +RMN_11 RMN_seg11 RMN_seg12 vss ppolyf_u_1k w=1u l=48.44u +RMN_12 RMN_seg12 RMN_seg13 vss ppolyf_u_1k w=1u l=48.44u +RMN_13 RMN_seg13 RMN_seg14 vss ppolyf_u_1k w=1u l=48.44u +RMN_14 RMN_seg14 RMN_seg15 vss ppolyf_u_1k w=1u l=48.44u +RMN_15 RMN_seg15 RMN_seg16 vss ppolyf_u_1k w=1u l=48.44u +RMN_16 RMN_seg16 RMN_seg17 vss ppolyf_u_1k w=1u l=48.44u +RMN_17 RMN_seg17 RMN_seg18 vss ppolyf_u_1k w=1u l=48.44u +RMN_18 RMN_seg18 RMN_seg19 vss ppolyf_u_1k w=1u l=48.44u +RMN_19 RMN_seg19 vcm_out vss ppolyf_u_1k w=1u l=48.44u +RMP_0 vcm_out RMP_seg1 vss ppolyf_u_1k w=1u l=48.44u +RMP_1 RMP_seg1 RMP_seg2 vss ppolyf_u_1k w=1u l=48.44u +RMP_2 RMP_seg2 RMP_seg3 vss ppolyf_u_1k w=1u l=48.44u +RMP_3 RMP_seg3 RMP_seg4 vss ppolyf_u_1k w=1u l=48.44u +RMP_4 RMP_seg4 RMP_seg5 vss ppolyf_u_1k w=1u l=48.44u +RMP_5 RMP_seg5 RMP_seg6 vss ppolyf_u_1k w=1u l=48.44u +RMP_6 RMP_seg6 RMP_seg7 vss ppolyf_u_1k w=1u l=48.44u +RMP_7 RMP_seg7 RMP_seg8 vss ppolyf_u_1k w=1u l=48.44u +RMP_8 RMP_seg8 RMP_seg9 vss ppolyf_u_1k w=1u l=48.44u +RMP_9 RMP_seg9 RMP_seg10 vss ppolyf_u_1k w=1u l=48.44u +RMP_10 RMP_seg10 RMP_seg11 vss ppolyf_u_1k w=1u l=48.44u +RMP_11 RMP_seg11 RMP_seg12 vss ppolyf_u_1k w=1u l=48.44u +RMP_12 RMP_seg12 RMP_seg13 vss ppolyf_u_1k w=1u l=48.44u +RMP_13 RMP_seg13 RMP_seg14 vss ppolyf_u_1k w=1u l=48.44u +RMP_14 RMP_seg14 RMP_seg15 vss ppolyf_u_1k w=1u l=48.44u +RMP_15 RMP_seg15 RMP_seg16 vss ppolyf_u_1k w=1u l=48.44u +RMP_16 RMP_seg16 RMP_seg17 vss ppolyf_u_1k w=1u l=48.44u +RMP_17 RMP_seg17 RMP_seg18 vss ppolyf_u_1k w=1u l=48.44u +RMP_18 RMP_seg18 RMP_seg19 vss ppolyf_u_1k w=1u l=48.44u +RMP_19 RMP_seg19 vinp vss ppolyf_u_1k w=1u l=48.44u +.ends sup_001_vcm_detector diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..6f7b779b802e91008165026d4337977ca4181fb1 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.spice @@ -0,0 +1,44 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt sup_001_vcm_detector vcm_out vinp vinn vss +XRMN_0 vinn RMN_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_1 RMN_seg1 RMN_seg2 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_2 RMN_seg2 RMN_seg3 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_3 RMN_seg3 RMN_seg4 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_4 RMN_seg4 RMN_seg5 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_5 RMN_seg5 RMN_seg6 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_6 RMN_seg6 RMN_seg7 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_7 RMN_seg7 RMN_seg8 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_8 RMN_seg8 RMN_seg9 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_9 RMN_seg9 RMN_seg10 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_10 RMN_seg10 RMN_seg11 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_11 RMN_seg11 RMN_seg12 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_12 RMN_seg12 RMN_seg13 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_13 RMN_seg13 RMN_seg14 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_14 RMN_seg14 RMN_seg15 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_15 RMN_seg15 RMN_seg16 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_16 RMN_seg16 RMN_seg17 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_17 RMN_seg17 RMN_seg18 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_18 RMN_seg18 RMN_seg19 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMN_19 RMN_seg19 vcm_out vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_0 vcm_out RMP_seg1 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_1 RMP_seg1 RMP_seg2 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_2 RMP_seg2 RMP_seg3 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_3 RMP_seg3 RMP_seg4 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_4 RMP_seg4 RMP_seg5 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_5 RMP_seg5 RMP_seg6 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_6 RMP_seg6 RMP_seg7 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_7 RMP_seg7 RMP_seg8 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_8 RMP_seg8 RMP_seg9 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_9 RMP_seg9 RMP_seg10 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_10 RMP_seg10 RMP_seg11 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_11 RMP_seg11 RMP_seg12 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_12 RMP_seg12 RMP_seg13 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_13 RMP_seg13 RMP_seg14 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_14 RMP_seg14 RMP_seg15 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_15 RMP_seg15 RMP_seg16 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_16 RMP_seg16 RMP_seg17 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_17 RMP_seg17 RMP_seg18 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_18 RMP_seg18 RMP_seg19 vss ppolyf_u_1k r_width=1u r_length=48.44u +XRMP_19 RMP_seg19 vinp vss ppolyf_u_1k r_width=1u r_length=48.44u +.ends sup_001_vcm_detector diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..4f392765c24df1f52e91857990bf567d1eeec5f1 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/schematic.svg @@ -0,0 +1,2 @@ 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export.","license":"licenses/gf180mcuD/analog-db/","sheets":["sup_001_vcm_detector","XRMN_bank1","XRMP_bank2"],"banks":[{"name":"XRMN_bank1","devices":20,"source_references":["RMN_0","RMN_1","RMN_2","RMN_3","RMN_4","RMN_5","RMN_6","RMN_7","RMN_8","RMN_9","RMN_10","RMN_11","RMN_12","RMN_13","RMN_14","RMN_15","RMN_16","RMN_17","RMN_18","RMN_19"]},{"name":"XRMP_bank2","devices":20,"source_references":["RMP_0","RMP_1","RMP_2","RMP_3","RMP_4","RMP_5","RMP_6","RMP_7","RMP_8","RMP_9","RMP_10","RMP_11","RMP_12","RMP_13","RMP_14","RMP_15","RMP_16","RMP_17","RMP_18","RMP_19"]}],"limitations":["Structured labelled overview, not a manually composed functional schematic. Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":40},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["sup_001_vcm_detector"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/schematic/sup_001_vcm_detector.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.sup_001_vcm_detectorvcm_outvinnvssvcm_outvinpvssvinnvssvcm_outvinpvssvcm_outvinpvinnvssvcm_outsup_001_vcm_detectorEqual net labels connect. All source devices and exact parameters are retained.XXRMN_bank1XRMN_bank1XXRMP_bank2XRMP_bank2 +Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..c479e84a24cdfa9a39ef65d25e130c32d1759346 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/testbench.spice @@ -0,0 +1,50 @@ +* Independently authored measurement fixture; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.options klu reltol=1e-6 abstol=1e-13 vntol=1e-9 +.temp 27 +VP drivep 0 DC {cm+dm/2} AC 1 PULSE({cm+dm/2} {cm+dm/2+0.1} 1u 10n 10n 9u 20u) +VN driven 0 DC {cm-dm/2} AC {acn} PULSE({cm-dm/2} {cm-dm/2+0.1} 1u 10n 10n 9u 20u) +RP drivep vinp 1000 +RN driven vinn 1000 +VSS vss 0 0 +RL vout 0 {load} +CL vout 0 1p +XDUT vout vinp vinn vss sup_001_vcm_detector +.control +set numdgt=15 +set measdgt=15 +op +let kcl_residual=abs(i(vp)+i(vn)+i(vss)+v(vout)/@rl[resistance]) +if kcl_residual > 1e-10 + echo Error: external DC KCL failed + quit 1 +end +let output_v=v(vout) +let power_w=-v(drivep)*i(vp)-v(driven)*i(vn) +print output_v power_w +write op.raw all +ac dec 40 1 10Meg +let mag=mag(v(vout)) +meas ac gain find mag at=1 +meas ac gain_10khz find mag at=10k +write ac.raw all +tran 2n 5u 0 2n +linearize +let expected=(op1.v(drivep)+op1.v(driven)+0.2)/2*@rl[resistance]/(@rl[resistance]+500500) +let error=abs(v(vout)-expected) +let first=floor(2u/(time[1]-time[0])+0.5) +let last=floor(4u/(time[1]-time[0])+0.5) +let idx=first +let integral=0 +while idx < last + let integral=integral+(error[idx]+error[idx+1])/2*(time[idx+1]-time[idx]) + let idx=idx+1 +end +let step_error_v=integral/2u +print step_error_v +write transient.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/problem.md b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..b0e8dad140924317ca855ba14b6748fbc91ee531 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/problem.md @@ -0,0 +1,80 @@ +# Passive Resistive Common-Mode Averager Layout Task + +## Objective + +Two matched 1 Mohm resistors join vinp to vcm_out and vcm_out to vinn. This is a passive average detector, without a buffer, amplifier or CMFB controller. The fixed IHP binding contains ideal R cards, not process-specific resistor models; the maintained physical adaptation uses forty native GF180 ppolyf_u_1k segments (twenty per branch), totaling 999951.8 ohm per branch at TT/27 C. The extra vss port grounds their physical substrate; it is not a functional supply. Target top cell: `sup_001_vcm_detector`. + +## Inputs and Interface + +`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vcm_out (sense output), vinp (positive input), vinn (negative input), vss (physical substrate). + +## Operating Conditions + +27 C, TT. External ideal drivers are 0.8 V and 0.4 V, each followed by 1 kohm source resistance. The output has 1 pF and either 1 Mohm or 1 Gohm to ground. Each load uses common-mode AC (both drivers +1 V) and differential AC (+1/-1 V), 1 Hz–10 MHz at 40 points/decade. Both drivers increase by 0.1 V at 1 us, with 10 ns edges, and stay high through the 5 us observation. Maximum transient step is 2 ns. The initial state is the same biased DC operating point for source and candidate. A 1 Gohm load is a finite high-impedance observation, not an unloaded claim. The analytic DC limit is Vcm*RL/(RL+500.5 kohm), tending to Vcm only as RL tends to infinity. Both input-source powers are included; no zero-power claim follows from the absence of a supply pin. + +## Physical Requirements + +Use GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Unit | Definition | Bound | Quality | +| --- | --- | --- | --- | --- | +| `output_v` | V | Loaded DC sense voltage | 0 to 0.8 | bias: target, target, scale=0.1 | +| `power_w` | W | Net delivered power from both external input sources | 0 to unbounded | supply: ratio, minimize, scale=1e-12 | +| `gain` | 1 | Output magnitude at 1 Hz for declared common/differential input | unbounded to unbounded | response: target, target, scale=1 | +| `gain_10khz` | 1 | Output magnitude at 10 kHz | unbounded to unbounded | response: target, target, scale=1 | +| `step_error_v` | V | Mean absolute error from settled DC target over 2–4 us | 0 to unbounded | response: ratio, minimize, scale=1e-06 | + +The 2–4 us average absolute step error is a finite-window quantity. Common and differential AC magnitudes use a 1 V half-input normalization; the differential residual is not divided by a near-zero source result. Nominal deterministic matching does not establish statistical mismatch or noise. + +Static output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances. + +For each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation. + +Compact area anchor: 6000 um2 = 40 × 55 × 2 um2 resistor/contact/isolation envelopes + 1600 um2 routing allowance. Each envelope accommodates the approximately 48.44 um resistor, end contacts and lateral spacing; the estimate permits folding. It is independent of the long, sparse witness. Coefficient 4: coupled matching, physical passive network, finite loading and parasitic dynamics. The circuit and these anchors are fixed before participant evaluation. + + +### Score weights + +Common-mode sensing/controllers: recovery and error 40.5%; signed transfer 31.5%; output bias 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `step_error_v` | 0.405000000000 | +| `gain` | 0.157500000000 | +| `gain_10khz` | 0.157500000000 | +| `output_v` | 0.045000000000 | +| `power_w` | 0.135000000000 | + +## Tools and Submission + +Solve budget: **6 hours**. + +Use the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs. diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/reference/sup_001_vcm_detector.gds b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/reference/sup_001_vcm_detector.gds new file mode 100644 index 0000000000000000000000000000000000000000..8647b3e35b44f1a3a068cc44fe2d1054a2761a32 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/reference/sup_001_vcm_detector.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:63f34ce151c5d05757b6d15f6b316a265cac2bd7a568d889318a6b8584b08067 +size 679946 diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..e757a7bc3323ffe435a8e4b8dfbd7d502daa33be --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml @@ -0,0 +1,1011 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.tsn_001_ptat_2t" +title = "Two-NMOS Temperature-Response Core" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "e8b422f5c0b6260f5b19aeba4f038bd1a5dfa4f99028778bcd90effd27dd6e48" + +[[assets]] +path = "reference/tsn_001_ptat_2t.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "b653dc94310f2491798fd53264fba4b78ed020fea4b905c7a784b8789bc4ec32" + +[task] +hours = 6 +kind = "netlist_to_gds" +family = "physical_core" +coefficient = 3 +environment = "gf180mcuD-mos-rc-tt" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "9b2ab97119c7c07e140721d1ab21da1af40e521f70bb6b1105e442659124b79e" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +format = "spice" +sha256 = "534d2b4bdfe4354bd80c0db81495c5d60a73fe20912ba79f3ccb749fadaf7efc" +subcircuit = "tsn_001_ptat_2t" + +[task.inputs.simulation] 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"candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" +requires = [] + +[task.evaluation.jobs.inputs] +deck = "input:temperature" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.measurements] +slope_v_c = "V/C" +curvature_v = "V" +output_v_0 = "V" +power_w_0 = "W" +output_v_1 = "V" +power_w_1 = "W" +output_v_2 = "V" +power_w_2 = "W" +output_v_3 = "V" +power_w_3 = "W" +output_v_4 = "V" +power_w_4 = "W" +output_v_5 = "V" +power_w_5 = "W" +output_v_6 = "V" +power_w_6 = "W" +output_v_7 = "V" +power_w_7 = "W" +output_v_8 = "V" +power_w_8 = "W" +output_v_9 = "V" +power_w_9 = "W" +output_v_10 = "V" +power_w_10 = "W" +output_v_11 = "V" +power_w_11 = "W" +output_v_12 = "V" +power_w_12 = "W" +output_v_13 = "V" +power_w_13 = "W" +output_v_14 = "V" +power_w_14 = "W" + +[task.evaluation.jobs.parameters.exports] +temperature = "temperature.raw" +reverse = "reverse.raw" + +[task.evaluation.jobs.outputs] +temperature = "ngspice-raw" +reverse = "ngspice-raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +unit = "V" +aggregation = "max" +direction = "target" +dimension = "bias" +normalization = "target" +scale = 0.1 +lower = 0 +upper = 1.2 +category = "performance" +observations = [ + "condition_0:output_v_0", + "condition_0:output_v_1", + "condition_0:output_v_2", + "condition_0:output_v_3", + "condition_0:output_v_4", + "condition_0:output_v_5", + "condition_0:output_v_6", + "condition_0:output_v_7", + "condition_0:output_v_8", + "condition_0:output_v_9", + "condition_0:output_v_10", + "condition_0:output_v_11", + "condition_0:output_v_12", + "condition_0:output_v_13", + "condition_0:output_v_14", +] +baseline = [ + "source_condition_0:output_v_0", + "source_condition_0:output_v_1", + "source_condition_0:output_v_2", + "source_condition_0:output_v_3", + "source_condition_0:output_v_4", + "source_condition_0:output_v_5", + "source_condition_0:output_v_6", + "source_condition_0:output_v_7", + "source_condition_0:output_v_8", + "source_condition_0:output_v_9", + "source_condition_0:output_v_10", + "source_condition_0:output_v_11", + "source_condition_0:output_v_12", + "source_condition_0:output_v_13", + "source_condition_0:output_v_14", +] + +[[task.evaluation.metrics]] +id = "power_w" +unit = "W" +aggregation = "max" +direction = "minimize" +dimension = "supply" +normalization = "ratio" +scale = 1e-15 +lower = 0 +category = "performance" +observations = [ + "condition_0:power_w_0", + "condition_0:power_w_1", + "condition_0:power_w_2", + "condition_0:power_w_3", + "condition_0:power_w_4", + "condition_0:power_w_5", + "condition_0:power_w_6", + "condition_0:power_w_7", + "condition_0:power_w_8", + "condition_0:power_w_9", + "condition_0:power_w_10", + "condition_0:power_w_11", + "condition_0:power_w_12", + "condition_0:power_w_13", + "condition_0:power_w_14", +] +baseline = [ + "source_condition_0:power_w_0", + "source_condition_0:power_w_1", + "source_condition_0:power_w_2", + "source_condition_0:power_w_3", + "source_condition_0:power_w_4", + "source_condition_0:power_w_5", + "source_condition_0:power_w_6", + "source_condition_0:power_w_7", + "source_condition_0:power_w_8", + "source_condition_0:power_w_9", + "source_condition_0:power_w_10", + "source_condition_0:power_w_11", + "source_condition_0:power_w_12", + "source_condition_0:power_w_13", + "source_condition_0:power_w_14", +] + +[[task.evaluation.metrics]] +id = "slope_v_c" +unit = "V/C" +aggregation = "max" +direction = "target" +dimension = "response" +normalization = "target" +scale = 0.001 +category = "performance" +observations = [ + "condition_0:slope_v_c", +] +baseline = [ + "source_condition_0:slope_v_c", +] + +[[task.evaluation.metrics]] +id = "curvature_v" +unit = "V" +aggregation = "max" +direction = "minimize" +dimension = "response" +normalization = "ratio" +scale = 1e-06 +lower = 0 +category = "performance" +observations = [ + "condition_0:curvature_v", +] +baseline = [ + "source_condition_0:curvature_v", +] + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 1600 +rationale = "Temperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +slope_v_c = 0.423529411764 +curvature_v = 0.317647058824 +output_v = 0.052941176471 +power_w = 0.105882352941 + +[task.evaluation.pre_layout] +source_report_sha256 = "13f84481210e5d20e89fbe1437f0d3ea96a257bc7e991e01d1217d9df07f15f9" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"branch\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:temperature" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +temperature = "ngspice-raw" +reverse = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +slope_v_c = "V/C" +curvature_v = "V" +output_v_0 = "V" +power_w_0 = "W" +output_v_1 = "V" +power_w_1 = "W" +output_v_2 = "V" +power_w_2 = "W" +output_v_3 = "V" +power_w_3 = "W" +output_v_4 = "V" +power_w_4 = "W" +output_v_5 = "V" +power_w_5 = "W" +output_v_6 = "V" +power_w_6 = "W" +output_v_7 = "V" +power_w_7 = "W" +output_v_8 = "V" +power_w_8 = "W" +output_v_9 = "V" +power_w_9 = "W" +output_v_10 = "V" +power_w_10 = "W" +output_v_11 = "V" +power_w_11 = "W" +output_v_12 = "V" +power_w_12 = "W" +output_v_13 = "V" +power_w_13 = "W" +output_v_14 = "V" +power_w_14 = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +temperature = "temperature.raw" +reverse = "reverse.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "4d79f00df8ece04f2b7c2fca93538c4f1e64561915d78be69d4e86cf841d44ed" +dut = "659c035dbae30f070c26ddc944ba6d79737771d6b3f806d36fce8fcf21a88859" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.curvature_v] +value = 0.0636609968167251 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_0] +value = 0.01409487638071293 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_1] +value = 0.04550193785627459 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_10] +value = 0.1283214919502018 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_11] +value = 0.1304940066474028 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_12] +value = 0.1326682671096975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_13] +value = 0.1348524132617638 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_14] +value = 0.1370519952882279 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_2] +value = 0.0856737564035763 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_3] +value = 0.1039092735043374 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_4] +value = 0.111704886595123 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_5] +value = 0.1160246014948687 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_6] +value = 0.1190670659285897 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_7] +value = 0.1215985193036865 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_8] +value = 0.1239142070192962 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v_9] +value = 0.1261369626003105 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_0] +value = 2.046049364723301e-13 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_1] +value = 3.312668677268112e-13 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_10] +value = 1.682457572904658e-10 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_11] +value = 3.008485695681592e-10 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_12] +value = 5.215770410771249e-10 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_13] +value = 8.787232857098892e-10 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_14] +value = 1.441649949211084e-09 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_2] +value = 5.417469370824581e-13 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_3] +value = 1.092152599180897e-12 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_4] +value = 2.411579379714418e-12 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_5] +value = 5.343469805950572e-12 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_6] +value = 1.150548874312516e-11 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_7] +value = 2.384204630414954e-11 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_8] +value = 4.747996477871278e-11 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w_9] +value = 9.099856114274358e-11 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.slope_v_c] +value = 0.0008782651350536781 +unit = "V/C" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 +resistor_formulation = "branch" + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_001_ptat_2t" + +[qualification] +reference = "reference/tsn_001_ptat_2t.gds" + +[presentation] +category = "Power & references" +summary = "Produces a temperature-dependent response whose slope and curvature are measured across the declared range." diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..57ab941ae3b893093916f209c306609980b29824 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl @@ -0,0 +1,20 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt tsn_001_ptat_2t vdd vout vss +MM0_0 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_1 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_2 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_3 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_4 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_5 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_6 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM0_7 vdd vout vout vss nfet_03v3 w=8u l=0.28u +MM1_0 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_1 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_2 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_3 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_4 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_5 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_6 vout vout vss vss nfet_03v3 w=4u l=1u +MM1_7 vout vout vss vss nfet_03v3 w=4u l=1u +.ends tsn_001_ptat_2t diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..2980c59b4c3b6aa0646bf212a5d8252bd453219b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.spice @@ -0,0 +1,20 @@ +* Required Notice: Copyright 2026 Danial Noori Zadeh +* Native physical adaptation; see collection LICENSE and NOTICE. +.subckt tsn_001_ptat_2t vdd vout vss +XM0_0 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_1 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_2 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_3 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_4 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_5 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_6 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM0_7 vdd vout vout vss nfet_03v3 w=8u l=0.28u +XM1_0 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_1 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_2 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_3 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_4 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_5 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_6 vout vout vss vss nfet_03v3 w=4u l=1u +XM1_7 vout vout vss vss nfet_03v3 w=4u l=1u +.ends tsn_001_ptat_2t diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..1f22bc0179fe287a93a27115375010ddf2b845cb --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/schematic.svg @@ -0,0 +1,2 @@ +tsn_001_ptat_2t{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.tsn_001_ptat_2t","source_netlist":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl","netlist_sha256":"534d2b4bdfe4354bd80c0db81495c5d60a73fe20912ba79f3ccb749fadaf7efc","project_sha256":"310f00a88749ce86b20f6477d6ff7898722c464e861e15a8084f60c74d810f2c","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"flat-cdl-project: independent source/project flattened device comparison, schema parse, symbol resolution and netlist export.","license":"licenses/gf180mcuD/analog-db/","sheets":["tsn_001_ptat_2t","MM0_bank1","MM1_bank2"],"banks":[{"name":"MM0_bank1","devices":8,"source_references":["MM0_0","MM0_1","MM0_2","MM0_3","MM0_4","MM0_5","MM0_6","MM0_7"]},{"name":"MM1_bank2","devices":8,"source_references":["MM1_0","MM1_1","MM1_2","MM1_3","MM1_4","MM1_5","MM1_6","MM1_7"]}],"limitations":["Structured labelled overview, not a manually composed functional schematic. Equal net labels connect within a sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Banks and pages preserve individual source devices without equivalent-device substitution. No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{},"presentation":{"layout":"Labelled device and hierarchical bank overview","source_precision":"unchanged"},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["tsn_001_ptat_2t"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/schematic/tsn_001_ptat_2t.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.tsn_001_ptat_2tvoutvssvddvoutvssvoutvssvoutvssvddvoutvssvddtsn_001_ptat_2tEqual net labels connect. All source devices and exact parameters are retained.XMM0_bank1MM0_bank1XMM1_bank2MM1_bank2 +Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect. diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/temperature.spice b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/temperature.spice new file mode 100644 index 0000000000000000000000000000000000000000..5911f5a1531334fed4c491861cdeb7da90ea5068 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/temperature.spice @@ -0,0 +1,98 @@ +* Independently authored measurement fixture; SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.options pivtol=1e-30 pivrel=0.001 gmin=1e-18 reltol=1e-7 abstol=1e-18 vntol=1e-10 +.temp 27 +VDD vdd 0 1.2 +VSS vss 0 0 +RL vout 0 1e12 +CL vout 0 1p +XDUT vdd vout vss tsn_001_ptat_2t +.nodeset v(vout)=0.05 +.control +set numdgt=15 +set measdgt=15 +dc temp -20 120 5 +let kcl_residual=abs(i(vdd)+i(vss)+v(vout)/1e12) +if maximum(kcl_residual) > 1e-14 + echo Error: temperature sweep KCL failed + quit 1 +end +let cold=v(vout)[0] +let hot=v(vout)[length(v(vout))-1] +let slope_v_c=(hot-cold)/140 +let deviation=abs(v(vout)-cold-slope_v_c*("temp-sweep"+20)) +let curvature_v=maximum(deviation) +print slope_v_c curvature_v +let output_v_0=v(vout)[0] +print output_v_0 +let power_w_0=-v(vdd)[0]*i(vdd)[0] +print power_w_0 +let output_v_1=v(vout)[2] +print output_v_1 +let power_w_1=-v(vdd)[2]*i(vdd)[2] +print power_w_1 +let output_v_2=v(vout)[4] +print output_v_2 +let power_w_2=-v(vdd)[4]*i(vdd)[4] +print power_w_2 +let output_v_3=v(vout)[6] +print output_v_3 +let power_w_3=-v(vdd)[6]*i(vdd)[6] +print power_w_3 +let output_v_4=v(vout)[8] +print output_v_4 +let power_w_4=-v(vdd)[8]*i(vdd)[8] +print power_w_4 +let output_v_5=v(vout)[10] +print output_v_5 +let power_w_5=-v(vdd)[10]*i(vdd)[10] +print power_w_5 +let output_v_6=v(vout)[12] +print output_v_6 +let power_w_6=-v(vdd)[12]*i(vdd)[12] +print power_w_6 +let output_v_7=v(vout)[14] +print output_v_7 +let power_w_7=-v(vdd)[14]*i(vdd)[14] +print power_w_7 +let output_v_8=v(vout)[16] +print output_v_8 +let power_w_8=-v(vdd)[16]*i(vdd)[16] +print power_w_8 +let output_v_9=v(vout)[18] +print output_v_9 +let power_w_9=-v(vdd)[18]*i(vdd)[18] +print power_w_9 +let output_v_10=v(vout)[20] +print output_v_10 +let power_w_10=-v(vdd)[20]*i(vdd)[20] +print power_w_10 +let output_v_11=v(vout)[22] +print output_v_11 +let power_w_11=-v(vdd)[22]*i(vdd)[22] +print power_w_11 +let output_v_12=v(vout)[24] +print output_v_12 +let power_w_12=-v(vdd)[24]*i(vdd)[24] +print power_w_12 +let output_v_13=v(vout)[26] +print output_v_13 +let power_w_13=-v(vdd)[26]*i(vdd)[26] +print power_w_13 +let output_v_14=v(vout)[28] +print output_v_14 +let power_w_14=-v(vdd)[28]*i(vdd)[28] +print power_w_14 +write temperature.raw all +dc temp 120 -20 -5 +let kcl_residual=abs(i(vdd)+i(vss)+v(vout)/1e12) +if maximum(kcl_residual) > 1e-14 + echo Error: temperature sweep KCL failed + quit 1 +end +write reverse.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/problem.md b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..489f20b1cbac73ab1740850f1031f04abfe3bf42 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/problem.md @@ -0,0 +1,78 @@ +# Two-NMOS Temperature-Response Core Layout Task + +## Objective + +The fixed GF180 binding contains eight parallel 8/0.28 um upper NMOS with gates tied to their sources, and eight parallel 4/1 um diode-connected lower NMOS. Both groups have grounded bodies. This is a two-group temperature-response core; neither its PTAT name nor a successful simulator exit establishes a useful slope or a converged extracted operating point. Target top cell: `tsn_001_ptat_2t`. + +## Inputs and Interface + +`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/temperature.spice` supplies the shared external fixture and bidirectional temperature sweep. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (supply), vout (sense voltage), vss (both bodies and return). + +## Operating Conditions + +GF180 nfet_03v3 TT, fixed 1.2 V supply, 1 Tohm probe resistance and 1 pF to ground. No external current bias changes with temperature. Ascending and descending temperature sweeps use 5 C steps. Output and power at -20 through 120 C in 10 C steps are sampled from the same ascending sweep used for slope and curvature. The fixed 50 mV nodeset is a Newton initial guess, not a voltage source or a per-temperature bias adjustment. Sparse 1.3, pivtol=1e-30 S, pivrel=0.001, reltol=1e-7, abstol=1e-18 A, vntol=1e-10 V and gmin=1e-18 S are explicit for both circuits; no rshunt is used. + +## Physical Requirements + +Use GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Unit | Definition | Bound | Quality | +| --- | --- | --- | --- | --- | +| `output_v` | V | Independent DC temperature-response output | 0 to 1.2 | bias: target, target, scale=0.1 | +| `power_w` | W | DC supply power at fixed 1.2 V | 0 to unbounded | supply: ratio, minimize, scale=1e-15 | +| `slope_v_c` | V/C | Endpoint temperature slope over -20 to 120 C | unbounded to unbounded | response: target, target, scale=0.001 | +| `curvature_v` | V | Maximum deviation from endpoint secant over -20 to 120 C | 0 to unbounded | response: ratio, minimize, scale=1e-06 | + +The simulator uses an explicit branch-current formulation for constant parasitic resistors: a zero-volt current sensor and a current-controlled voltage source impose V=R*I exactly. Every resistance, terminal and extracted capacitance is retained. This avoids loss of tiny node conductances when added to the much larger metal conductance in conventional nodal stamping. The original extraction and the effective simulation netlist are both retained as evidence. Source and candidate use the same backend setting. This deterministic formulation does not model resistor thermal noise; noise is outside this task's scope. KCL and measurement-validity checks remain mandatory. No self-startup, precision temperature sensing or linear PTAT behavior is assumed. + +Static output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances. + +For each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation. + +Compact area anchor: 1600 um2 = 8 × 10 × 10 um2 upper-device/contact envelopes + 8 × 6 × 8 um2 lower-device/contact envelopes + 416 um2 routing/body-contact allowance, independent of witness area. Coefficient 3: local analog temperature-dependent bias and transfer. The circuit and these anchors are fixed before participant evaluation. + + +### Score weights + +Temperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `slope_v_c` | 0.423529411764 | +| `curvature_v` | 0.317647058824 | +| `output_v` | 0.052941176471 | +| `power_w` | 0.105882352941 | + +## Tools and Submission + +Solve budget: **6 hours**. + +Use the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs. diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/reference/tsn_001_ptat_2t.gds b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/reference/tsn_001_ptat_2t.gds new file mode 100644 index 0000000000000000000000000000000000000000..509201d955135b4ccaa4e5aea587f8f9c66d894e --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/reference/tsn_001_ptat_2t.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b653dc94310f2491798fd53264fba4b78ed020fea4b905c7a784b8789bc4ec32 +size 108080 diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..976287cb920cb4a9ae5b442e3734053fbc483a48 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml @@ -0,0 +1,3537 @@ +in_core = true +kind = "layout_case" +id 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+ +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +temperature_c = -20 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +temperature_c = -20 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +temperature_c = 27 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_3" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +temperature_c = 27 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_4" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +temperature_c = 100 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_5" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 +temperature_c = 100 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_6" +stage = "simulate" +operation = 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"ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3 +temperature_c = -20 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_8" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3 +temperature_c = 27 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v 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"circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3 +temperature_c = 100 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_12" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +temperature_c = -20 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_13" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +temperature_c = -20 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_14" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +temperature_c = 27 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_15" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +temperature_c = 27 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_16" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +temperature_c = 100 +rise_s = 1e-07 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.jobs]] +id = "condition_17" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 +temperature_c = 100 +rise_s = 1e-05 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", + "condition_3:output_v", + "condition_4:output_v", + "condition_5:output_v", + "condition_6:output_v", + "condition_7:output_v", + "condition_8:output_v", + "condition_9:output_v", + "condition_10:output_v", + "condition_11:output_v", + "condition_12:output_v", + "condition_13:output_v", + "condition_14:output_v", + "condition_15:output_v", + "condition_16:output_v", + "condition_17:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", + "source_condition_3:output_v", + "source_condition_4:output_v", + "source_condition_5:output_v", + "source_condition_6:output_v", + "source_condition_7:output_v", + "source_condition_8:output_v", + "source_condition_9:output_v", + "source_condition_10:output_v", + "source_condition_11:output_v", + "source_condition_12:output_v", + "source_condition_13:output_v", + "source_condition_14:output_v", + "source_condition_15:output_v", + "source_condition_16:output_v", + "source_condition_17:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", + "condition_3:power_w", + "condition_4:power_w", + "condition_5:power_w", + "condition_6:power_w", + "condition_7:power_w", + "condition_8:power_w", + "condition_9:power_w", + "condition_10:power_w", + "condition_11:power_w", + "condition_12:power_w", + "condition_13:power_w", + "condition_14:power_w", + "condition_15:power_w", + "condition_16:power_w", + "condition_17:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", + "source_condition_3:power_w", + "source_condition_4:power_w", + "source_condition_5:power_w", + "source_condition_6:power_w", + "source_condition_7:power_w", + "source_condition_8:power_w", + "source_condition_9:power_w", + "source_condition_10:power_w", + "source_condition_11:power_w", + "source_condition_12:power_w", + "source_condition_13:power_w", + "source_condition_14:power_w", + "source_condition_15:power_w", + "source_condition_16:power_w", + "source_condition_17:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "cold_v" +category = "performance" +observations = [ + "condition_0:cold_v", + "condition_1:cold_v", + "condition_2:cold_v", + "condition_3:cold_v", + "condition_4:cold_v", + "condition_5:cold_v", + "condition_6:cold_v", + "condition_7:cold_v", + "condition_8:cold_v", + "condition_9:cold_v", + "condition_10:cold_v", + "condition_11:cold_v", + "condition_12:cold_v", + "condition_13:cold_v", + "condition_14:cold_v", + "condition_15:cold_v", + "condition_16:cold_v", + "condition_17:cold_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:cold_v", + "source_condition_1:cold_v", + "source_condition_2:cold_v", + "source_condition_3:cold_v", + "source_condition_4:cold_v", + "source_condition_5:cold_v", + "source_condition_6:cold_v", + "source_condition_7:cold_v", + "source_condition_8:cold_v", + "source_condition_9:cold_v", + "source_condition_10:cold_v", + "source_condition_11:cold_v", + "source_condition_12:cold_v", + "source_condition_13:cold_v", + "source_condition_14:cold_v", + "source_condition_15:cold_v", + "source_condition_16:cold_v", + "source_condition_17:cold_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "hot_v" +category = "performance" +observations = [ + "condition_0:hot_v", + "condition_1:hot_v", + "condition_2:hot_v", + "condition_3:hot_v", + "condition_4:hot_v", + "condition_5:hot_v", + "condition_6:hot_v", + "condition_7:hot_v", + "condition_8:hot_v", + "condition_9:hot_v", + "condition_10:hot_v", + "condition_11:hot_v", + "condition_12:hot_v", + "condition_13:hot_v", + "condition_14:hot_v", + "condition_15:hot_v", + "condition_16:hot_v", + "condition_17:hot_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:hot_v", + "source_condition_1:hot_v", + "source_condition_2:hot_v", + "source_condition_3:hot_v", + "source_condition_4:hot_v", + "source_condition_5:hot_v", + "source_condition_6:hot_v", + "source_condition_7:hot_v", + "source_condition_8:hot_v", + "source_condition_9:hot_v", + "source_condition_10:hot_v", + "source_condition_11:hot_v", + "source_condition_12:hot_v", + "source_condition_13:hot_v", + "source_condition_14:hot_v", + "source_condition_15:hot_v", + "source_condition_16:hot_v", + "source_condition_17:hot_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "slope_v_per_c" +category = "performance" +observations = [ + "condition_0:slope_v_per_c", + "condition_1:slope_v_per_c", + "condition_2:slope_v_per_c", + "condition_3:slope_v_per_c", + "condition_4:slope_v_per_c", + "condition_5:slope_v_per_c", + "condition_6:slope_v_per_c", + "condition_7:slope_v_per_c", + "condition_8:slope_v_per_c", + "condition_9:slope_v_per_c", + "condition_10:slope_v_per_c", + "condition_11:slope_v_per_c", + "condition_12:slope_v_per_c", + "condition_13:slope_v_per_c", + "condition_14:slope_v_per_c", + "condition_15:slope_v_per_c", + "condition_16:slope_v_per_c", + "condition_17:slope_v_per_c", +] +unit = "V/C" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:slope_v_per_c", + "source_condition_1:slope_v_per_c", + "source_condition_2:slope_v_per_c", + "source_condition_3:slope_v_per_c", + "source_condition_4:slope_v_per_c", + "source_condition_5:slope_v_per_c", + "source_condition_6:slope_v_per_c", + "source_condition_7:slope_v_per_c", + "source_condition_8:slope_v_per_c", + "source_condition_9:slope_v_per_c", + "source_condition_10:slope_v_per_c", + "source_condition_11:slope_v_per_c", + "source_condition_12:slope_v_per_c", + "source_condition_13:slope_v_per_c", + "source_condition_14:slope_v_per_c", + "source_condition_15:slope_v_per_c", + "source_condition_16:slope_v_per_c", + "source_condition_17:slope_v_per_c", +] +normalization = "target" +scale = 0.00047 + +[[task.evaluation.metrics]] +id = "curvature_v" +category = "performance" +observations = [ + "condition_0:curvature_v", + "condition_1:curvature_v", + "condition_2:curvature_v", + "condition_3:curvature_v", + "condition_4:curvature_v", + "condition_5:curvature_v", + "condition_6:curvature_v", + "condition_7:curvature_v", + "condition_8:curvature_v", + "condition_9:curvature_v", + "condition_10:curvature_v", + "condition_11:curvature_v", + "condition_12:curvature_v", + "condition_13:curvature_v", + "condition_14:curvature_v", + "condition_15:curvature_v", + "condition_16:curvature_v", + "condition_17:curvature_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:curvature_v", + "source_condition_1:curvature_v", + "source_condition_2:curvature_v", + "source_condition_3:curvature_v", + "source_condition_4:curvature_v", + "source_condition_5:curvature_v", + "source_condition_6:curvature_v", + "source_condition_7:curvature_v", + "source_condition_8:curvature_v", + "source_condition_9:curvature_v", + "source_condition_10:curvature_v", + "source_condition_11:curvature_v", + "source_condition_12:curvature_v", + "source_condition_13:curvature_v", + "source_condition_14:curvature_v", + "source_condition_15:curvature_v", + "source_condition_16:curvature_v", + "source_condition_17:curvature_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "minimum_slope" +category = "performance" +observations = [ + "condition_0:minimum_slope", + "condition_1:minimum_slope", + "condition_2:minimum_slope", + "condition_3:minimum_slope", + "condition_4:minimum_slope", + "condition_5:minimum_slope", + "condition_6:minimum_slope", + "condition_7:minimum_slope", + "condition_8:minimum_slope", + "condition_9:minimum_slope", + "condition_10:minimum_slope", + "condition_11:minimum_slope", + "condition_12:minimum_slope", + "condition_13:minimum_slope", + "condition_14:minimum_slope", + "condition_15:minimum_slope", + "condition_16:minimum_slope", + "condition_17:minimum_slope", +] +unit = "V/C" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:minimum_slope", + "source_condition_1:minimum_slope", + "source_condition_2:minimum_slope", + "source_condition_3:minimum_slope", + "source_condition_4:minimum_slope", + "source_condition_5:minimum_slope", + "source_condition_6:minimum_slope", + "source_condition_7:minimum_slope", + "source_condition_8:minimum_slope", + "source_condition_9:minimum_slope", + "source_condition_10:minimum_slope", + "source_condition_11:minimum_slope", + "source_condition_12:minimum_slope", + "source_condition_13:minimum_slope", + "source_condition_14:minimum_slope", + "source_condition_15:minimum_slope", + "source_condition_16:minimum_slope", + "source_condition_17:minimum_slope", +] +normalization = "target" +scale = 0.00055 + +[[task.evaluation.metrics]] +id = "maximum_slope" +category = "performance" +observations = [ + "condition_0:maximum_slope", + "condition_1:maximum_slope", + "condition_2:maximum_slope", + "condition_3:maximum_slope", + "condition_4:maximum_slope", + "condition_5:maximum_slope", + "condition_6:maximum_slope", + "condition_7:maximum_slope", + "condition_8:maximum_slope", + "condition_9:maximum_slope", + "condition_10:maximum_slope", + "condition_11:maximum_slope", + "condition_12:maximum_slope", + "condition_13:maximum_slope", + "condition_14:maximum_slope", + "condition_15:maximum_slope", + "condition_16:maximum_slope", + "condition_17:maximum_slope", +] +unit = "V/C" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:maximum_slope", + "source_condition_1:maximum_slope", + "source_condition_2:maximum_slope", + "source_condition_3:maximum_slope", + "source_condition_4:maximum_slope", + "source_condition_5:maximum_slope", + "source_condition_6:maximum_slope", + "source_condition_7:maximum_slope", + "source_condition_8:maximum_slope", + "source_condition_9:maximum_slope", + "source_condition_10:maximum_slope", + "source_condition_11:maximum_slope", + "source_condition_12:maximum_slope", + "source_condition_13:maximum_slope", + "source_condition_14:maximum_slope", + "source_condition_15:maximum_slope", + "source_condition_16:maximum_slope", + "source_condition_17:maximum_slope", +] +normalization = "target" +scale = 0.00055 + +[[task.evaluation.metrics]] +id = "peak_power_w" +category = "performance" +observations = [ + "condition_0:peak_power_w", + "condition_1:peak_power_w", + "condition_2:peak_power_w", + "condition_3:peak_power_w", + "condition_4:peak_power_w", + "condition_5:peak_power_w", + "condition_6:peak_power_w", + "condition_7:peak_power_w", + "condition_8:peak_power_w", + "condition_9:peak_power_w", + "condition_10:peak_power_w", + "condition_11:peak_power_w", + "condition_12:peak_power_w", + "condition_13:peak_power_w", + "condition_14:peak_power_w", + "condition_15:peak_power_w", + "condition_16:peak_power_w", + "condition_17:peak_power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:peak_power_w", + "source_condition_1:peak_power_w", + "source_condition_2:peak_power_w", + "source_condition_3:peak_power_w", + "source_condition_4:peak_power_w", + "source_condition_5:peak_power_w", + "source_condition_6:peak_power_w", + "source_condition_7:peak_power_w", + "source_condition_8:peak_power_w", + "source_condition_9:peak_power_w", + "source_condition_10:peak_power_w", + "source_condition_11:peak_power_w", + "source_condition_12:peak_power_w", + "source_condition_13:peak_power_w", + "source_condition_14:peak_power_w", + "source_condition_15:peak_power_w", + "source_condition_16:peak_power_w", + "source_condition_17:peak_power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "startup_error_v" +category = "performance" +observations = [ + "condition_0:startup_error_v", + "condition_1:startup_error_v", + "condition_2:startup_error_v", + "condition_3:startup_error_v", + "condition_4:startup_error_v", + "condition_5:startup_error_v", + "condition_6:startup_error_v", + "condition_7:startup_error_v", + "condition_8:startup_error_v", + "condition_9:startup_error_v", + "condition_10:startup_error_v", + "condition_11:startup_error_v", + "condition_12:startup_error_v", + "condition_13:startup_error_v", + "condition_14:startup_error_v", + "condition_15:startup_error_v", + "condition_16:startup_error_v", + "condition_17:startup_error_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:startup_error_v", + "source_condition_1:startup_error_v", + "source_condition_2:startup_error_v", + "source_condition_3:startup_error_v", + "source_condition_4:startup_error_v", + "source_condition_5:startup_error_v", + "source_condition_6:startup_error_v", + "source_condition_7:startup_error_v", + "source_condition_8:startup_error_v", + "source_condition_9:startup_error_v", + "source_condition_10:startup_error_v", + "source_condition_11:startup_error_v", + "source_condition_12:startup_error_v", + "source_condition_13:startup_error_v", + "source_condition_14:startup_error_v", + "source_condition_15:startup_error_v", + "source_condition_16:startup_error_v", + "source_condition_17:startup_error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "ripple_v" +category = "performance" +observations = [ + "condition_0:ripple_v", + "condition_1:ripple_v", + "condition_2:ripple_v", + "condition_3:ripple_v", + "condition_4:ripple_v", + "condition_5:ripple_v", + "condition_6:ripple_v", + "condition_7:ripple_v", + "condition_8:ripple_v", + "condition_9:ripple_v", + "condition_10:ripple_v", + "condition_11:ripple_v", + "condition_12:ripple_v", + "condition_13:ripple_v", + "condition_14:ripple_v", + "condition_15:ripple_v", + "condition_16:ripple_v", + "condition_17:ripple_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:ripple_v", + "source_condition_1:ripple_v", + "source_condition_2:ripple_v", + "source_condition_3:ripple_v", + "source_condition_4:ripple_v", + "source_condition_5:ripple_v", + "source_condition_6:ripple_v", + "source_condition_7:ripple_v", + "source_condition_8:ripple_v", + "source_condition_9:ripple_v", + "source_condition_10:ripple_v", + "source_condition_11:ripple_v", + "source_condition_12:ripple_v", + "source_condition_13:ripple_v", + "source_condition_14:ripple_v", + "source_condition_15:ripple_v", + "source_condition_16:ripple_v", + "source_condition_17:ripple_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "final_power_w" +category = "performance" +observations = [ + "condition_0:final_power_w", + "condition_1:final_power_w", + "condition_2:final_power_w", + "condition_3:final_power_w", + "condition_4:final_power_w", + "condition_5:final_power_w", + "condition_6:final_power_w", + "condition_7:final_power_w", + "condition_8:final_power_w", + "condition_9:final_power_w", + "condition_10:final_power_w", + "condition_11:final_power_w", + "condition_12:final_power_w", + "condition_13:final_power_w", + "condition_14:final_power_w", + "condition_15:final_power_w", + "condition_16:final_power_w", + "condition_17:final_power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:final_power_w", + "source_condition_1:final_power_w", + "source_condition_2:final_power_w", + "source_condition_3:final_power_w", + "source_condition_4:final_power_w", + "source_condition_5:final_power_w", + "source_condition_6:final_power_w", + "source_condition_7:final_power_w", + "source_condition_8:final_power_w", + "source_condition_9:final_power_w", + "source_condition_10:final_power_w", + "source_condition_11:final_power_w", + "source_condition_12:final_power_w", + "source_condition_13:final_power_w", + "source_condition_14:final_power_w", + "source_condition_15:final_power_w", + "source_condition_16:final_power_w", + "source_condition_17:final_power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 529.13 +rationale = "Temperature-slope cores: temperature slope 36%; curvature 27%; startup 13.5%; output endpoints 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +maximum_slope = 0.12 +minimum_slope = 0.12 +slope_v_per_c = 0.12 +curvature_v = 0.27 +ripple_v = 0.0675 +startup_error_v = 0.0675 +cold_v = 0.015 +hot_v = 0.015 +output_v = 0.015 +final_power_w = 0.03 +peak_power_w = 0.03 +power_w = 0.03 + +[task.evaluation.pre_layout] +source_report_sha256 = "93936743559eaf0c979f59a61a670b23fec4581b88a52978948926e402002019" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 2.7 +temperature_c = -20 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.cold_v] +value = 0.1166461 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.curvature_v] +value = 0.001773968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_power_w] +value = 3.240497e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.hot_v] +value = 0.1678079 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.maximum_slope] +value = 0.0004842871 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_slope] +value = 0.0003694495 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.1166460983303 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.peak_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 3.240496991286e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.slope_v_per_c] +value = 0.0004263483333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.startup_error_v] +value = 2.170486e-13 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 2.7 +temperature_c = -20 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.cold_v] +value = 0.1166461 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.curvature_v] +value = 0.001773968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_power_w] +value = 3.240497e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.hot_v] +value = 0.1678079 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.maximum_slope] +value = 0.0004842871 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_slope] +value = 0.0003694495 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 0.1166460983303 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.peak_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 3.240496991286e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.slope_v_per_c] +value = 0.0004263483333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.startup_error_v] +value = 2.149947e-13 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 2.7 +temperature_c = 27 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.cold_v] +value = 0.1166461 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.curvature_v] +value = 0.001773968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_power_w] +value = 3.84557e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.hot_v] +value = 0.1678079 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.maximum_slope] +value = 0.0004842871 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_slope] +value = 0.0003694495 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 0.1349992536778 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.peak_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 3.845570407632e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.slope_v_per_c] +value = 0.0004263483333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.startup_error_v] +value = 1.369067e-10 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_3.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_3.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.values] +supply_v = 2.7 +temperature_c = 27 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.cold_v] +value = 0.1166461 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.curvature_v] +value = 0.001773968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_power_w] +value = 3.84557e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.hot_v] +value = 0.1678079 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.maximum_slope] +value = 0.0004842871 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_slope] +value = 0.0003694495 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] +value = 0.1349992536778 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.peak_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] +value = 3.845570407632e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.slope_v_per_c] +value = 0.0004263483333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_3.measurements.startup_error_v] +value = 1.369088e-10 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_4.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_4.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.values] +supply_v = 2.7 +temperature_c = 100 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.cold_v] +value = 0.1166461 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.curvature_v] +value = 0.001773968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.hot_v] +value = 0.1678079 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.maximum_slope] +value = 0.0004842871 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.minimum_slope] +value = 0.0003694495 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] +value = 0.1678078954705 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.peak_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] +value = 4.945078341437e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.slope_v_per_c] +value = 0.0004263483333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_4.measurements.startup_error_v] +value = 1.108785e-11 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_5.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_5.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.values] +supply_v = 2.7 +temperature_c = 100 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_5.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.cold_v] +value = 0.1166461 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.curvature_v] +value = 0.001773968 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.hot_v] +value = 0.1678079 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.maximum_slope] +value = 0.0004842871 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.minimum_slope] +value = 0.0003694495 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_v] +value = 0.1678078954705 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.peak_power_w] +value = 4.945078e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.power_w] +value = 4.945078341437e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.slope_v_per_c] +value = 0.0004263483333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_5.measurements.startup_error_v] +value = 1.10944e-11 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_6.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_6.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.values] +supply_v = 3 +temperature_c = -20 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_6.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_6.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.cold_v] +value = 0.1184336 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.curvature_v] +value = 0.001821132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.final_power_w] +value = 3.757681e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.hot_v] +value = 0.170306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.maximum_slope] +value = 0.0004918432 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.minimum_slope] +value = 0.0003738671 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.output_v] +value = 0.1184336187495 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.peak_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.power_w] +value = 3.757681173638e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.slope_v_per_c] +value = 0.00043227 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_6.measurements.startup_error_v] +value = 1.374298e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_7] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_7.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_7.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_7.parameters.values] +supply_v = 3 +temperature_c = -20 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_7.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_7.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_7.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.cold_v] +value = 0.1184336 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.curvature_v] +value = 0.001821132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.final_power_w] +value = 3.757681e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.hot_v] +value = 0.170306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.maximum_slope] +value = 0.0004918432 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.minimum_slope] +value = 0.0003738671 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.output_v] +value = 0.1184336187495 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.peak_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.power_w] +value = 3.757681173638e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.slope_v_per_c] +value = 0.00043227 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_7.measurements.startup_error_v] +value = 1.374298e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_8] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_8.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_8.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_8.parameters.values] +supply_v = 3 +temperature_c = 27 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_8.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_8.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_8.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.cold_v] +value = 0.1184336 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.curvature_v] +value = 0.001821132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.final_power_w] +value = 4.427596e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.hot_v] +value = 0.170306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.maximum_slope] +value = 0.0004918432 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.minimum_slope] +value = 0.0003738671 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.output_v] +value = 0.1370206057971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.peak_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.power_w] +value = 4.427595435861e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.slope_v_per_c] +value = 0.00043227 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_8.measurements.startup_error_v] +value = 1.783912e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_9] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_9.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_9.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_9.parameters.values] +supply_v = 3 +temperature_c = 27 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_9.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_9.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_9.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.cold_v] +value = 0.1184336 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.curvature_v] +value = 0.001821132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.final_power_w] +value = 4.427596e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.hot_v] +value = 0.170306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.maximum_slope] +value = 0.0004918432 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.minimum_slope] +value = 0.0003738671 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.output_v] +value = 0.1370206057971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.peak_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.power_w] +value = 4.427595435861e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.slope_v_per_c] +value = 0.00043227 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_9.measurements.startup_error_v] +value = 1.783912e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_10] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_10.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_10.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_10.parameters.values] +supply_v = 3 +temperature_c = 100 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_10.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_10.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_10.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.cold_v] +value = 0.1184336 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.curvature_v] +value = 0.001821132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.final_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.hot_v] +value = 0.170306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.maximum_slope] +value = 0.0004918432 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.minimum_slope] +value = 0.0003738671 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.output_v] +value = 0.1703059887 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.peak_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.power_w] +value = 5.655881508494e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.slope_v_per_c] +value = 0.00043227 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_10.measurements.startup_error_v] +value = 3.748606e-10 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_11] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_11.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_11.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_11.parameters.values] +supply_v = 3 +temperature_c = 100 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_11.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_11.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_11.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.cold_v] +value = 0.1184336 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.curvature_v] +value = 0.001821132 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.final_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.hot_v] +value = 0.170306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.maximum_slope] +value = 0.0004918432 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.minimum_slope] +value = 0.0003738671 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.output_v] +value = 0.1703059887 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.peak_power_w] +value = 5.655882e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.power_w] +value = 5.655881508494e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.slope_v_per_c] +value = 0.00043227 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_11.measurements.startup_error_v] +value = 3.748606e-10 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_12] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_12.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_12.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_12.parameters.values] +supply_v = 3.3 +temperature_c = -20 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_12.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_12.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_12.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.cold_v] +value = 0.1201363 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.curvature_v] +value = 0.001860855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.final_power_w] +value = 4.316283e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.hot_v] +value = 0.1726296 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.maximum_slope] +value = 0.0004983875 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.minimum_slope] +value = 0.0003778229 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.output_v] +value = 0.1201363185352 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.peak_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.power_w] +value = 4.316282601372e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.slope_v_per_c] +value = 0.0004374441666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_12.measurements.startup_error_v] +value = 1.282256e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_13] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_13.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_13.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_13.parameters.values] +supply_v = 3.3 +temperature_c = -20 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_13.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_13.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_13.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.cold_v] +value = 0.1201363 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.curvature_v] +value = 0.001860855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.final_power_w] +value = 4.316283e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.hot_v] +value = 0.1726296 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.maximum_slope] +value = 0.0004983875 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.minimum_slope] +value = 0.0003778229 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.output_v] +value = 0.1201363185352 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.peak_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.power_w] +value = 4.316282601372e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.slope_v_per_c] +value = 0.0004374441666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_13.measurements.startup_error_v] +value = 1.282256e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_14] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_14.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_14.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_14.parameters.values] +supply_v = 3.3 +temperature_c = 27 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_14.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_14.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_14.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.cold_v] +value = 0.1201363 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.curvature_v] +value = 0.001860855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.final_power_w] +value = 5.048396e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.hot_v] +value = 0.1726296 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.maximum_slope] +value = 0.0004983875 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.minimum_slope] +value = 0.0003778229 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.output_v] +value = 0.1389290424502 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.peak_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.power_w] +value = 5.048395602318e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.slope_v_per_c] +value = 0.0004374441666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_14.measurements.startup_error_v] +value = 5.107026e-15 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_15] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_15.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_15.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_15.parameters.values] +supply_v = 3.3 +temperature_c = 27 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_15.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_15.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_15.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.cold_v] +value = 0.1201363 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.curvature_v] +value = 0.001860855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.final_power_w] +value = 5.048396e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.hot_v] +value = 0.1726296 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.maximum_slope] +value = 0.0004983875 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.minimum_slope] +value = 0.0003778229 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.output_v] +value = 0.1389290424502 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.peak_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.power_w] +value = 5.048395602318e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.slope_v_per_c] +value = 0.0004374441666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_15.measurements.startup_error_v] +value = 5.107026e-15 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_16] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_16.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_16.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_16.parameters.values] +supply_v = 3.3 +temperature_c = 100 +rise_s = 1e-07 + +[task.evaluation.pre_layout.jobs.source_condition_16.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_16.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_16.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.cold_v] +value = 0.1201363 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.curvature_v] +value = 0.001860855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.final_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.hot_v] +value = 0.1726296 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.maximum_slope] +value = 0.0004983875 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.minimum_slope] +value = 0.0003778229 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.output_v] +value = 0.1726296070769 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.peak_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.power_w] +value = 6.403141689581e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.slope_v_per_c] +value = 0.0004374441666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_16.measurements.startup_error_v] +value = 5.967449e-15 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_17] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_17.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_condition_17.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" +startup = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_17.parameters.values] +supply_v = 3.3 +temperature_c = 100 +rise_s = 1e-05 + +[task.evaluation.pre_layout.jobs.source_condition_17.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" +startup_error_v = "V" +ripple_v = "V" +final_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_17.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" +startup = "startup.raw" + +[task.evaluation.pre_layout.jobs.source_condition_17.input_sha256] +deck = "29661fc18d6c7d50086b0d333cf1c625845fea7a604ac82ff08072a3be2eb2a4" +dut = "bd0c82d0bdfa7c4041d6a043d9482e71472ea1319a71704ac3ffbbcdcb9d6652" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.cold_v] +value = 0.1201363 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.curvature_v] +value = 0.001860855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.final_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.hot_v] +value = 0.1726296 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.maximum_slope] +value = 0.0004983875 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.minimum_slope] +value = 0.0003778229 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.output_v] +value = 0.1726296070769 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.peak_power_w] +value = 6.403142e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.power_w] +value = 6.403141689581e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.ripple_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.slope_v_per_c] +value = 0.0004374441666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_17.measurements.startup_error_v] +value = 5.440093e-15 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_002_ptat_classic" + +[qualification] +reference = "reference/tsn_002_ptat_classic.gds" + +[presentation] +category = "Power & references" +summary = "Produces a temperature-dependent response whose slope and curvature are measured across the declared range." diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..a0f84d6fb03ecc2dcf2ca778c80523493e811869 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl @@ -0,0 +1,16 @@ +* Derived from analog-db tsn_002_ptat_classic, fixed commit +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE, including CODA-Team attribution. +* Original four-MOS W/L/m and output-connected body retained. +* Added three-MOS startup; physical 20 kohm poly resistor and isolated well. +.subckt tsn_002_ptat_classic vdd vout vss +XR0 vout vss vss ppolyf_u_1k r_width=2u r_length=40u m=1 +MM0 vmir net1 vout vout nfet_03v3_dn w=8u l=1u m=1 +XM1 net1 net1 vss vss nfet_03v3 w=2u l=1u m=1 +XM3 vmir vmir vdd vdd pfet_03v3 w=2u l=1u m=1 +XM4 net1 vmir vdd vdd pfet_03v3 w=2u l=1u m=1 +* Added MOS startup with self-disabling injection path; original core W/L and body unchanged. +XSTARTP startup vss vdd vdd pfet_03v3 w=0.42u l=20u m=1 +XSTARTN startup net1 vss vss nfet_03v3 w=2u l=0.28u m=1 +XINJECT net1 startup vdd vss nfet_03v3 w=0.42u l=1u m=1 +.ends tsn_002_ptat_classic diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..86d5fc8439dd60ad7a869eee08181c755f9cfbbd --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.spice @@ -0,0 +1,16 @@ +* Derived from analog-db tsn_002_ptat_classic, fixed commit +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE, including CODA-Team attribution. +* Original four-MOS W/L/m and output-connected body retained. +* Added three-MOS startup; physical 20 kohm poly resistor and isolated well. +.subckt tsn_002_ptat_classic vdd vout vss +XR0 vout vss vss ppolyf_u_1k r_width=2u r_length=40u m=1 +XM0 vmir net1 vout vout nfet_03v3 w=8u l=1u m=1 +XM1 net1 net1 vss vss nfet_03v3 w=2u l=1u m=1 +XM3 vmir vmir vdd vdd pfet_03v3 w=2u l=1u m=1 +XM4 net1 vmir vdd vdd pfet_03v3 w=2u l=1u m=1 +* Added MOS startup with self-disabling injection path; original core W/L and body unchanged. +XSTARTP startup vss vdd vdd pfet_03v3 w=0.42u l=20u m=1 +XSTARTN startup net1 vss vss nfet_03v3 w=2u l=0.28u m=1 +XINJECT net1 startup vdd vss nfet_03v3 w=0.42u l=1u m=1 +.ends tsn_002_ptat_classic diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..e36641c6da8439a715664464e5267d4a5c3923b9 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/schematic.svg @@ -0,0 +1 @@ +tsn_002_ptat_classic{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.tsn_002_ptat_classic", "netlist_sha256": "1efc6b4da14d95c12ff19bd3a1e8a10a8c986a97befff37dadb44ce6f10ef5ea", "project_sha256": "9f72b69ab6d4169d39be09d64af7d0faff51eb7b5596f022071b5d7dace572c8", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["tsn_002_ptat_classic"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl", "known_editor_diagnostics": {"ERC_ILLEGAL_PIN_NAME": 1}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}tsn_002_ptat_classicvssvddnet1startupvddvoutvssvmirnet1vddvoutvsstsn_002_ptat_classicgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 PTAT coreXM32/1XM42/1MM08/1XM12/1XR0W/L 2/40P bulk → vddMM0: B → voutXM1: B → vssR substrate → vss02 Startup injectionXSTARTP0.42/20XINJECT0.42/1XSTARTN2/0.28P bulk → vddN bulk → vssModels: ppolyf_u_1k · nfet_03v3_dn · nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..0c15eae8de85574105fe2b474bc668ebff1daa3f --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/testbench.spice @@ -0,0 +1,47 @@ +* Layout-Bench self-starting PTAT characterization. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp {temperature_c} +.option method=gear maxord=2 +VDD vdd 0 DC {supply_v} PWL(0 0 {rise_s} {supply_v}) +CL vout 0 100f +XDUT vdd vout 0 tsn_002_ptat_classic +.save v(vdd) v(vout) i(vdd) +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let power_w=-v(vdd)*i(vdd) +print output_v power_w +write op.raw all +dc temp -20 100 1 +let vv=v(vout) +let pp=-v(vdd)*i(vdd) +meas dc cold_v find vv at=-20 +meas dc hot_v find vv at=100 +let slope_v_per_c=(hot_v-cold_v)/120 +let error_v=abs(vv-(cold_v+slope_v_per_c*vector(length(vv)))) +meas dc curvature_v max error_v +let local_slope=deriv(vv) +meas dc minimum_slope min local_slope +meas dc maximum_slope max local_slope +meas dc peak_power_w max pp +print slope_v_per_c +write temperature.raw all +reset +tran 1n 100u 0 1n uic +let vv=v(vout) +let error=abs(vv-op1.output_v) +meas tran startup_error_v max error from=90u to=100u +meas tran late_min min vv from=90u to=100u +meas tran late_max max vv from=90u to=100u +let ripple_v=late_max-late_min +let pp=-v(vdd)*i(vdd) +meas tran final_power_w avg pp from=90u to=100u +print ripple_v +write startup.raw all +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..a98af0df8f28721857f395fc116a378dcf4aff60 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md @@ -0,0 +1,156 @@ +# Self-Starting Isolated-Body PTAT Core Layout Task + +## Objective + +Implement `tsn_002_ptat_classic` in GF180MCU D and submit self-contained GDS. +The resistor-degenerated four-MOS source core has a positive temperature slope; +candidate slope is measured and source-paired without a positive-slope acceptance bound. +A maintained three-MOS startup branch establishes its operating state after +power-up. Supply sensitivity remains: this is not a precision temperature +reference or a calibrated thermometer. + +## Inputs and Interface + +`materials/circuit.cdl` is the physical LVS authority; +`materials/circuit.spice` is its simulator representation. +`materials/testbench.spice` defines stimuli and observations. This problem is +the description input. Ordered ports are `vdd vout vss`: supply, +temperature-dependent output and return. + +Retain all device dimensions, multiplicities and four-terminal connections. +The 8/1 um core NMOS has both source and body on `vout`; its body must remain +isolated from VSS. The physical primitive `MM0 ... nfet_03v3_dn` maps to +`XM0 ... nfet_03v3` in the simulator, with the same D/G/S/B and W/L/m. +Use an isolated P-well inside a supply-tied deep N-well, with explicit +N-well enclosure and physical well/substrate contacts. Extraction must retain +the separation between the output body and substrate return. No body-to-VSS +substitution is permitted. The core resistor is physical 1 kohm/square poly, +W=2 um, L=40 um, nominal 20 kohm. + +The added startup devices have W/L of 0.42/20 um (weak PMOS pull-up), +2/0.28 um (NMOS detector) and 0.42/1 um (NMOS injector). The detector reduces +the startup control voltage after bias is established, turning off the +injection path. The weak pull-up/detector branch still draws static current; +all DUT supply power is measured. Preserve this branch as part of the DUT. +Placement, routing, splitting and source/drain interchange are permitted only +where accepted by the declared LVS equivalence rules. No statistical matching +or placement style is scored. External stimulus and the output load belong to +the testbench and must not be placed inside the DUT. + +## Operating Conditions + +Use typical GF180 3.3 V MOS and poly models with statistical variation disabled. +VSS is 0 V. Evaluate all 18 combinations of VDD = 2.7/3.0/3.3 V, +temperature = -20/27/100 C and supply rise time = 0.1/10 us. +Each condition measures its DC operating point and a -20 to 100 C sweep in +1 C steps. The temperature is then restored to the selected value before +startup simulation. The external output capacitance is exactly 100 fF. + +For startup, ramp VDD linearly from 0 to its selected value, then hold it. +Use a zero-initial-state `uic` transient through 100 us with no internal +initial-condition bias or auxiliary startup source. Gear order 2 and a +maximum timestep of 1 ns are declared. Measure final error, ripple and average +power over 90–100 us. These are finite-window error and ripple observations with no settling-error +acceptance threshold; they do not establish settling time or bound overshoot. + +## Physical Requirements + +Submit top cell `tsn_002_ptat_classic`, all named electrical ports, resolved +hierarchy and at most 10 MiB. Artifact, GF180 variant-D DRC including antenna, +strict named-port LVS and geometry must pass with no DRC waivers. Chip-level +density and seal-ring closure are outside this standalone-block scope. + +The functional bounding box must fit within 220 by 65 um. Its area includes +all declared device and routing drawing layers: wells (including deep N-well +and isolated P-well), implants, active, poly, contacts, metals/vias and device +markers. Annotation and pin-purpose shapes are excluded. All functional +routing must use drawing layers. `/protocol/task.json` freezes the layer set. + +Independent candidate extraction retains MOS and resistor geometry and adds +distributed wiring RC. All scored simulation consumes that extracted DUT. +This does not include a distributed silicon substrate model. Larger output +loads are unqualified and can cause oscillation; this is not a pF-load output +buffer. Brownout/restart, arbitrary supply ramps, process/statistical corners, +noise, absolute temperature accuracy, supply rejection, EM and fabrication +signoff are outside scope. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output at the selected supply and temperature | V | target / target | 0 … 3.3 | 3.3 | +| `power_w` | DC delivered supply power, -V(vdd)*I(VDD), including startup bias | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `cold_v` | Output at -20 C | V | target / target | 0 … 3.3 | 3.3 | +| `hot_v` | Output at 100 C | V | target / target | 0 … 3.3 | 3.3 | +| `slope_v_per_c` | (hot_v - cold_v)/120 C | V/C | target / target | −∞ … +∞ | 0.00047 | +| `curvature_v` | Maximum absolute deviation from the endpoint line at all 121 temperatures | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `minimum_slope` | Minimum ngspice deriv(output) over temperature | V/C | target / target | −∞ … +∞ | 0.00055 | +| `maximum_slope` | Maximum ngspice deriv(output) over temperature | V/C | target / target | −∞ … +∞ | 0.00055 | +| `peak_power_w` | Maximum delivered supply power over temperature | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `startup_error_v` | Maximum absolute output error against the selected DC operating point during 90–100 us | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `ripple_v` | Maximum minus minimum output during 90–100 us | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `final_power_w` | Time-average delivered supply power during 90–100 us | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **529.13 um2**. 8 expanded device instances; sum of device/contact envelopes 303.6200 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **6**; it is independent of +the reference-relative task score. + + +### Score weights + +Temperature-slope cores: temperature slope 36%; curvature 27%; startup 13.5%; output endpoints 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `maximum_slope` | 0.120000000000 | +| `minimum_slope` | 0.120000000000 | +| `slope_v_per_c` | 0.120000000000 | +| `curvature_v` | 0.270000000000 | +| `ripple_v` | 0.067500000000 | +| `startup_error_v` | 0.067500000000 | +| `cold_v` | 0.015000000000 | +| `hot_v` | 0.015000000000 | +| `output_v` | 0.015000000000 | +| `final_power_w` | 0.030000000000 | +| `peak_power_w` | 0.030000000000 | +| `power_w` | 0.030000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 resources in `/protocol/resources.json`. KLayout checks +physical validity and geometry, Magic extracts RC and ngspice simulates the +circuit. `/protocol/task.json` provides frozen requirements and +`/protocol/harness.json` describes the harness. When `process-feedback` is +exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then submit with `python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/reference/tsn_002_ptat_classic.gds b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/reference/tsn_002_ptat_classic.gds new file mode 100644 index 0000000000000000000000000000000000000000..4089ae4f93611969739c5f1d729b0a4ae31d05b1 Binary files /dev/null and b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/reference/tsn_002_ptat_classic.gds differ diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..2632fd699af9679115e19193f260df5f5c0b3b62 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml @@ -0,0 +1,1138 @@ +in_core = false +kind = "layout_case" +id = "gf180mcuD.analog-db.tsn_003_ptat_4t_xcoupled" +title = "Four-Transistor Positive-Temperature-Slope Core" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "ad455198447a6dcb5a43193df07242a5d8d5a650465935cda1e42e95f0490a32" + +[[assets]] +path = "reference/tsn_003_ptat_4t_xcoupled.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "5dfcc4df599aa38678db51b8ee22c4bda5e04fdb7e9745fa30605d951be5cca4" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_four_transistor_temperature_core" +coefficient = 3 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = "16fcafe750f6a87bc590c3887b2d8fc05fdbccaf9d46a5d11a7e22d8b00979cb" + +[task.inputs.netlist] +path = "materials/circuit.spice" +format = "spice" +sha256 = "f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09" +subcircuit = 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"layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "vdd", + "vout", + "vss", +] + +[[task.evaluation.jobs]] +id = "condition_0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 2.7 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" + +[[task.evaluation.jobs]] +id = "condition_1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.0 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" + +[[task.evaluation.jobs]] +id = "condition_2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +supply_v = 3.3 + +[task.evaluation.jobs.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" + +[task.evaluation.jobs.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "output_v" +category = "performance" +observations = [ + "condition_0:output_v", + "condition_1:output_v", + "condition_2:output_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:output_v", + "source_condition_1:output_v", + "source_condition_2:output_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "power_w" +category = "performance" +observations = [ + "condition_0:power_w", + "condition_1:power_w", + "condition_2:power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:power_w", + "source_condition_1:power_w", + "source_condition_2:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "cold_v" +category = "performance" +observations = [ + "condition_0:cold_v", + "condition_1:cold_v", + "condition_2:cold_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:cold_v", + "source_condition_1:cold_v", + "source_condition_2:cold_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "hot_v" +category = "performance" +observations = [ + "condition_0:hot_v", + "condition_1:hot_v", + "condition_2:hot_v", +] +unit = "V" +dimension = "bias" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:hot_v", + "source_condition_1:hot_v", + "source_condition_2:hot_v", +] +normalization = "target" +scale = 3.3 +lower = 0 +upper = 3.3 + +[[task.evaluation.metrics]] +id = "slope_v_per_c" +category = "performance" +observations = [ + "condition_0:slope_v_per_c", + "condition_1:slope_v_per_c", + "condition_2:slope_v_per_c", +] +unit = "V/C" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:slope_v_per_c", + "source_condition_1:slope_v_per_c", + "source_condition_2:slope_v_per_c", +] +normalization = "target" +scale = 0.00036 + +[[task.evaluation.metrics]] +id = "curvature_v" +category = "performance" +observations = [ + "condition_0:curvature_v", + "condition_1:curvature_v", + "condition_2:curvature_v", +] +unit = "V" +dimension = "response" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:curvature_v", + "source_condition_1:curvature_v", + "source_condition_2:curvature_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "minimum_slope" +category = "performance" +observations = [ + "condition_0:minimum_slope", + "condition_1:minimum_slope", + "condition_2:minimum_slope", +] +unit = "V/C" +dimension = "response" +direction = "target" +aggregation = "min" +baseline = [ + "source_condition_0:minimum_slope", + "source_condition_1:minimum_slope", + "source_condition_2:minimum_slope", +] +normalization = "target" +scale = 0.00024 + +[[task.evaluation.metrics]] +id = "maximum_slope" +category = "performance" +observations = [ + "condition_0:maximum_slope", + "condition_1:maximum_slope", + "condition_2:maximum_slope", +] +unit = "V/C" +dimension = "response" +direction = "target" +aggregation = "max" +baseline = [ + "source_condition_0:maximum_slope", + "source_condition_1:maximum_slope", + "source_condition_2:maximum_slope", +] +normalization = "target" +scale = 0.00036 + +[[task.evaluation.metrics]] +id = "peak_power_w" +category = "performance" +observations = [ + "condition_0:peak_power_w", + "condition_1:peak_power_w", + "condition_2:peak_power_w", +] +unit = "W" +dimension = "supply" +direction = "minimize" +aggregation = "max" +baseline = [ + "source_condition_0:peak_power_w", + "source_condition_1:peak_power_w", + "source_condition_2:peak_power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 168.38 +rationale = "Temperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +maximum_slope = 0.141176470588 +minimum_slope = 0.141176470588 +slope_v_per_c = 0.141176470588 +curvature_v = 0.317647058822 +cold_v = 0.017647058824 +hot_v = 0.017647058824 +output_v = 0.017647058824 +peak_power_w = 0.052941176471 +power_w = 0.052941176471 + +[task.evaluation.pre_layout] +source_report_sha256 = "dc2d68ef06cf5b2476776301cac23fafcd44a4e107db2b5f8197723fd32caaa4" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_condition_0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_0.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.values] +supply_v = 2.7 + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" + +[task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] +deck = "9381caafa52300ab51973ade851ac0fbe114480213b26c8bc93dc062ec3a78eb" +dut = "f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.cold_v] +value = 0.112257 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.curvature_v] +value = 9.307522e-06 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.hot_v] +value = 0.1437512 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.maximum_slope] +value = 0.0002631716 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_slope] +value = 0.0002622107 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] +value = 0.1245997644977 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.peak_power_w] +value = 0.0001446342 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] +value = 0.0001263739532558 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_0.measurements.slope_v_per_c] +value = 0.0002624516666667 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_1.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.values] +supply_v = 3.0 + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" + +[task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] +deck = "9381caafa52300ab51973ade851ac0fbe114480213b26c8bc93dc062ec3a78eb" +dut = "f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.cold_v] +value = 0.1310849 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.curvature_v] +value = 4.271693e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.hot_v] +value = 0.1670193 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.maximum_slope] +value = 0.000301475 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_slope] +value = 0.0002985129 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] +value = 0.1452018854074 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.peak_power_w] +value = 0.0002091807 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] +value = 0.0001821647842242 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_1.measurements.slope_v_per_c] +value = 0.0002994533333333 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_condition_2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_condition_2.outputs] +op = "ngspice-raw" +temperature = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.values] +supply_v = 3.3 + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.measurements] +output_v = "V" +power_w = "W" +cold_v = "V" +hot_v = "V" +slope_v_per_c = "V/C" +curvature_v = "V" +minimum_slope = "V/C" +maximum_slope = "V/C" +peak_power_w = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.parameters.exports] +op = "op.raw" +temperature = "temperature.raw" + +[task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] +deck = "9381caafa52300ab51973ade851ac0fbe114480213b26c8bc93dc062ec3a78eb" +dut = "f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.cold_v] +value = 0.1503868 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.curvature_v] +value = 7.209692e-05 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.hot_v] +value = 0.1911575 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.maximum_slope] +value = 0.0003428504 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_slope] +value = 0.0003378454 +unit = "V/C" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] +value = 0.1664266865277 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.peak_power_w] +value = 0.0002884296 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] +value = 0.0002508520635496 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_condition_2.measurements.slope_v_per_c] +value = 0.0003397558333333 +unit = "V/C" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_003_ptat_4t_xcoupled" + +[qualification] +reference = "reference/tsn_003_ptat_4t_xcoupled.gds" + +[presentation] +category = "Power & references" +summary = "Produces a temperature-dependent response whose slope and curvature are measured across the declared range." diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..f6cc85dc169807d86ad4d4a5944ce953e7460d1b --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice @@ -0,0 +1,9 @@ +* Derived from analog-db tsn_003_ptat_4t_xcoupled, GF180 binding at +* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. +* See collection LICENSE and NOTICE. Layout-Bench changes: fixed GF180 dimensions and body rails. +.subckt tsn_003_ptat_4t_xcoupled vdd vout vss +XM0 vout na vss vss nfet_03v3 w=4u l=3u m=1 +XM1 na na vss vss nfet_03v3 w=1u l=3u m=1 +XM3 vout vout vdd vdd pfet_03v3 w=2u l=3u m=1 +XM4 na vout vdd vdd pfet_03v3 w=2u l=3u m=1 +.ends tsn_003_ptat_4t_xcoupled diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..b7fefe6a2ff7d553015dd042946ab63ffeb8cc79 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/schematic.svg @@ -0,0 +1 @@ +tsn_003_ptat_4t_xcoupled{"format": "iclayout-schematic", "case_id": "gf180mcuD.analog-db.tsn_003_ptat_4t_xcoupled", "netlist_sha256": "f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09", "project_sha256": "b45a2d40172ab4305d7c0f6db7d2ddb4184a788a54d3c747b6d5806653d2a840", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/analog-db/", "sheets": ["tsn_003_ptat_4t_xcoupled"], "banks": [], "source_netlist": "tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}tsn_003_ptat_4t_xcoupledvddvssvoutnavddvoutvsstsn_003_ptat_4t_xcoupledgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figures01 Cross-coupled PTAT coreXM32/3XM42/3XM04/3XM11/3P bulk → vddN bulk → vssModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..50e4c5c4b4df3f0d50bb30e2b0b0a5110d39630c --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/testbench.spice @@ -0,0 +1,32 @@ +* Maintained Layout-Bench testbench. SPDX-License-Identifier: MIT +.include support/models.spice +.include dut.spice +.include parameters.spice +.temp 27 +VDD vdd 0 DC {supply_v} +XDUT vdd vout 0 tsn_003_ptat_4t_xcoupled +.control +set noaskquit +set numdgt=12 +op +let output_v=v(vout) +let power_w=-v(vdd)*i(vdd) +print output_v power_w +write op.raw v(vdd) v(vout) i(vdd) +dc temp -20 100 1 +let vv=v(vout) +let pp=-v(vdd)*i(vdd) +meas dc cold_v find vv at=-20 +meas dc hot_v find vv at=100 +let slope_v_per_c=(hot_v-cold_v)/120 +let error_v=abs(vv-(cold_v+slope_v_per_c*(vector(length(vv))))) +meas dc curvature_v max error_v +let local_slope=deriv(vv) +meas dc minimum_slope min local_slope +meas dc maximum_slope max local_slope +meas dc peak_power_w max pp +print slope_v_per_c +write temperature.raw v(vout) v(vdd) i(vdd) +quit +.endc +.end diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/problem.md b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..2eadd93fd10c22ed5a6d255015989f4e890b8db3 --- /dev/null +++ b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/problem.md @@ -0,0 +1,126 @@ +# Four-Transistor Positive-Temperature-Slope Core Layout Task + +## Objective + +Implement the fixed `tsn_003_ptat_4t_xcoupled` circuit in GF180MCU D and submit self-contained GDS. +Two NMOS and two PMOS devices form a resistorless temperature-dependent voltage core with cross-coupled bias connections. The fixed GF180 sizes are retained. The output increases with temperature under each declared supply, but both voltage and slope depend strongly on supply. This is a temperature-slope layout task, not a precision reference or calibrated thermometer. + +## Inputs and Interface + +`materials/circuit.spice` is authoritative for LVS and source calibration; +`materials/testbench.spice` defines every electrical measurement. This problem +is the description input. Ordered ports: `vdd vout vss`. +In order, these are: Supply, unloaded temperature-dependent output, and return. + +Preserve the netlist's device connectivity, dimensions, multiplicities and body +connections. Provide physical well/substrate contacts to the declared rails. +Placement, routing, splitting and source/drain interchange are permitted only +where accepted by the declared LVS equivalence rules. No common-centroid or +statistical matching requirement is scored. Ideal external stimulus, bias and +load devices remain testbench apparatus and must not be placed inside the DUT. + +## Operating Conditions + +Use the typical GF180 3.3 V MOS models and physical poly models where present, +with statistical variation disabled. Unless swept explicitly, temperature is 27 C. +VSS = 0 V; VDD = 2.7, 3.0 and 3.3 V. Measure the operating point at 27 C, then sweep temperature from -20 to 100 C inclusive in 1 C steps at each supply. The output is unloaded except for the measurement probe. No ideal internal source or passive is added. + +## Physical Requirements + +Submit top cell `tsn_003_ptat_4t_xcoupled` with every named electrical port, resolved hierarchy +and a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna, +strict named-port LVS and geometry must pass, without DRC waivers. Chip-level +density and seal-ring closure are outside this standalone-block scope. + +The functional bounding box must fit within 120 by 60 um. Area includes all +process device and routing drawing layers listed in runtime constraints: +wells, implants, active, poly, contacts, metals/vias and passive/device markers. +Annotation and pin-purpose shapes are excluded; all functional routing must use +drawing layers. The complete layer list is frozen in `/protocol/task.json`. + +The judge independently extracts distributed wiring resistance and capacitance +from the submitted GDS, retaining candidate-derived MOS/passive geometry and +external body connections. Every scored simulation consumes that extracted DUT. +This model boundary does not include a distributed silicon substrate network. +The temperature sweep is a nominal model sweep, not process-corner or statistical qualification. Startup, output drive, absolute temperature accuracy, supply rejection, mismatch, noise and EM are outside scope. Manufacturing signoff is not claimed. + +## Electrical Requirements and Scoring + +All three operating conditions must complete and every observation must be finite +and meet its inclusive band. Aggregation cannot hide a failing condition; +missing crossings or incomplete extraction/simulation cannot establish success. +Saved waveforms provide the inputs for independently reconstructing observations. + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 | +| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | +| `cold_v` | Output at -20 C | V | target / target | 0 … 3.3 | 3.3 | +| `hot_v` | Output at 100 C | V | target / target | 0 … 3.3 | 3.3 | +| `slope_v_per_c` | (Output at 100 C - output at -20 C)/120 C | V/C | target / target | −∞ … +∞ | 0.00036 | +| `curvature_v` | Maximum deviation from the endpoint line over all 121 temperature samples | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `minimum_slope` | Minimum ngspice deriv(output) over the temperature sweep | V/C | target / target | −∞ … +∞ | 0.00024 | +| `maximum_slope` | Maximum ngspice deriv(output) over the temperature sweep | V/C | target / target | −∞ … +∞ | 0.00036 | +| `peak_power_w` | Maximum -V(vdd)*I(VDD) over the full temperature sweep | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **168.38 um2**. 4 expanded device instances; sum of device/contact envelopes 85.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **3**; it is independent of +the reference-relative task score. + + +### Score weights + +Temperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `maximum_slope` | 0.141176470588 | +| `minimum_slope` | 0.141176470588 | +| `slope_v_per_c` | 0.141176470588 | +| `curvature_v` | 0.317647058822 | +| `cold_v` | 0.017647058824 | +| `hot_v` | 0.017647058824 | +| `output_v` | 0.017647058824 | +| `peak_power_w` | 0.052941176471 | +| `power_w` | 0.052941176471 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use the reviewed GF180 resources listed in `/protocol/resources.json`. +KLayout checks the layout, Magic extracts RC and ngspice simulates the circuit. +`/protocol/task.json` provides frozen constraints and evaluation requirements; +`/protocol/harness.json` describes the harness. If `process-feedback` is +exposed, use its published helper for interim checks. Write +`/workspace/output/final.gds`, then explicitly submit with +`python -I /protocol/submit.py`. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/reference/tsn_003_ptat_4t_xcoupled.gds b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/reference/tsn_003_ptat_4t_xcoupled.gds new file mode 100644 index 0000000000000000000000000000000000000000..d8632f406525d32037280ab15383617f69d37d19 Binary files /dev/null and b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/reference/tsn_003_ptat_4t_xcoupled.gds differ diff --git a/tasks/gf180mcuD/gf-r2r-dac/LICENSE b/tasks/gf180mcuD/gf-r2r-dac/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..261eeb9e9f8b2b4b0d119366dda99c6fd7d35c64 --- /dev/null +++ b/tasks/gf180mcuD/gf-r2r-dac/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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+[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "b7", + "b1", + "b0", + "b2", + "b3", + "b4", + "b5", + "b6", + "out", + "VGND", +] + +[[task.evaluation.jobs]] +id = "code0" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code1" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 1 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code2" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 1 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code4" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 1 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code8" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 1 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code16" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 1 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code32" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 1 +bit6 = 0 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code64" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 1 +bit7 = 0 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code128" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 1 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.jobs]] +id = "code255" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.jobs.parameters.values] +bit0 = 1 +bit1 = 1 +bit2 = 1 +bit3 = 1 +bit4 = 1 +bit5 = 1 +bit6 = 1 +bit7 = 1 + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "accuracy" +category = "performance" +observations = [ + "code0:error_v", + "code1:error_v", + "code2:error_v", + "code4:error_v", + "code8:error_v", + "code16:error_v", + "code32:error_v", + "code64:error_v", + "code128:error_v", + "code255:error_v", +] +unit = "V" +direction = "minimize" +aggregation = "max" +dimension = "response" +baseline = [ + "source_code0:error_v", + "source_code1:error_v", + "source_code2:error_v", + "source_code4:error_v", + "source_code8:error_v", + "source_code16:error_v", + "source_code32:error_v", + "source_code64:error_v", + "source_code128:error_v", + "source_code255:error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[[task.evaluation.metrics]] +id = "settling" +category = "performance" +observations = [ + "code0:settling_error_v", + "code1:settling_error_v", + "code2:settling_error_v", + "code4:settling_error_v", + "code8:settling_error_v", + "code16:settling_error_v", + "code32:settling_error_v", + "code64:settling_error_v", + "code128:settling_error_v", + "code255:settling_error_v", +] +unit = "V" +direction = "minimize" +aggregation = "max" +dimension = "response" +baseline = [ + "source_code0:settling_error_v", + "source_code1:settling_error_v", + "source_code2:settling_error_v", + "source_code4:settling_error_v", + "source_code8:settling_error_v", + "source_code16:settling_error_v", + "source_code32:settling_error_v", + "source_code64:settling_error_v", + "source_code128:settling_error_v", + "source_code255:settling_error_v", +] +normalization = "ratio" +lower = 0 +scale = 1e-06 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 8727.76 +rationale = "Passive R-2R DAC: conversion accuracy 63%; dynamic residual 27%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +accuracy = 0.63 +settling = 0.27 + +[task.evaluation.pre_layout] +source_report_sha256 = "3946170e0f6c6d8774e0e43176c4c4dfd736031a2f9de58139a9db7373dab196" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_code0] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code0.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code0.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code0.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code0.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code0.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code0.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code0.measurements.error_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code0.measurements.settling_error_v] +value = 0.0 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code1] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code1.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code1.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code1.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code1.parameters.values] +bit0 = 1 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code1.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code1.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code1.measurements.error_v] +value = 5e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code1.measurements.settling_error_v] +value = 5e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code2] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code2.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code2.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code2.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code2.parameters.values] +bit0 = 0 +bit1 = 1 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code2.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code2.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code2.measurements.error_v] +value = 3.469447e-18 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code2.measurements.settling_error_v] +value = 3.469447e-18 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code4] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code4.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code4.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code4.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code4.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 1 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code4.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code4.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code4.measurements.error_v] +value = 6.938894e-18 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code4.measurements.settling_error_v] +value = 6.938894e-18 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code8] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code8.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code8.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code8.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code8.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 1 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code8.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code8.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code8.measurements.error_v] +value = 1.387779e-17 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code8.measurements.settling_error_v] +value = 1.387779e-17 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code16] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code16.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code16.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code16.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code16.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 1 +bit5 = 0 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code16.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code16.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code16.measurements.error_v] +value = 2.775558e-17 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code16.measurements.settling_error_v] +value = 2.775558e-17 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code32] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code32.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code32.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code32.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code32.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 1 +bit6 = 0 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code32.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code32.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code32.measurements.error_v] +value = 5.551115e-17 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code32.measurements.settling_error_v] +value = 5.551115e-17 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code64] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code64.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code64.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code64.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code64.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 1 +bit7 = 0 + +[task.evaluation.pre_layout.jobs.source_code64.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code64.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code64.measurements.error_v] +value = 1.110223e-16 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code64.measurements.settling_error_v] +value = 1.110223e-16 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code128] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code128.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code128.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code128.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code128.parameters.values] +bit0 = 0 +bit1 = 0 +bit2 = 0 +bit3 = 0 +bit4 = 0 +bit5 = 0 +bit6 = 0 +bit7 = 1 + +[task.evaluation.pre_layout.jobs.source_code128.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code128.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code128.measurements.error_v] +value = 4.440892e-16 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code128.measurements.settling_error_v] +value = 4.440892e-16 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code255] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_code255.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_code255.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_code255.parameters.measurements] +error_v = "V" +settling_error_v = "V" + +[task.evaluation.pre_layout.jobs.source_code255.parameters.values] +bit0 = 1 +bit1 = 1 +bit2 = 1 +bit3 = 1 +bit4 = 1 +bit5 = 1 +bit6 = 1 +bit7 = 1 + +[task.evaluation.pre_layout.jobs.source_code255.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_code255.input_sha256] +deck = "9392ac55586aabd3303b728f1e3fc712e6214bb5473eb55c906dd64f5d4cf77a" +dut = "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957" + +[task.evaluation.pre_layout.jobs.source_code255.measurements.error_v] +value = 3.75e-07 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_code255.measurements.settling_error_v] +value = 3.75e-07 +unit = "V" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/mattvenn/gf-r2r-dac/tree/1c5c8ddec54fc4e70ce03a19510d4d7461b919e9/xschem/simulation/r2r.spice" + +[qualification] +reference = "reference/r2r.gds" + +[presentation] +category = "Mixed-signal" +summary = "Converts an eight-bit digital code into an analog voltage through an R-2R network." diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..4be58247fa61722840f61ce49611b7ff40a94daa --- /dev/null +++ b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice @@ -0,0 +1,31 @@ +* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed. +.subckt r2r b7 b1 b0 b2 b3 b4 b5 b6 out VGND +*.PININFO VGND:B b0:I b1:I out:O b2:I b3:I b4:I b5:I b6:I b7:I +XR1 net1 b0 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR2 net2 net1 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR3 net3 net2 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR4 VGND net3 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR5 net4 net2 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR6 net5 b1 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR7 net4 net5 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR8 net6 net4 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR9 net7 b2 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR10 net6 net7 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR11 net8 net6 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR12 net9 b3 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR13 net8 net9 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR14 net10 net8 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR15 net11 b4 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR16 net10 net11 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR17 net12 net10 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR18 net13 b5 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR19 net12 net13 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR20 net14 net12 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR21 net15 b6 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR22 net14 net15 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR23 out net14 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR24 net16 b7 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR25 out net16 VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR26 VGND VGND VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +XR27 VGND VGND VGND ppolyf_u_1k r_width=2e-6 r_length=50e-6 +.ends diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/schematic.svg b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..64799dee5795a2c9dc768e9c39ec0d86ef00732b --- /dev/null +++ b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/schematic.svg @@ -0,0 +1 @@ +r2r{"format": "iclayout-schematic", "case_id": "gf180mcuD.gf-r2r-dac.r2r", "netlist_sha256": "64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957", "project_sha256": "bbdf0a75c64d80f164025567088bcca747f5fd2c8a3dfebcd4efc8d8582197bc", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/gf-r2r-dac/", "sheets": ["r2r"], "banks": [], "source_netlist": "tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice", "known_editor_diagnostics": {"ERC_ILLEGAL_PIN_NAME": 27}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}r2rb0b1b2b3b4b5b6b7net2net1outnet5net7net9net11net13net15net16net4net6net8net10net12net14net2VGNDnet3VGNDb7b1b0b2b3b4b5b6outVGNDr2rgf180mcuD · gf-r2r-dac | W/L in µm · display rounded to 3 significant figures01 R–2R ladderXR2W/L 2/50XR5W/L 2/50XR8W/L 2/50XR11W/L 2/50XR14W/L 2/50XR17W/L 2/50XR20W/L 2/50XR23W/L 2/50XR1W/L 2/50XR7W/L 2/50XR10W/L 2/50XR13W/L 2/50XR16W/L 2/50XR19W/L 2/50XR22W/L 2/50XR25W/L 2/50XR6W/L 2/50XR9W/L 2/50XR12W/L 2/50XR15W/L 2/50XR18W/L 2/50XR21W/L 2/50XR24W/L 2/50R substrate → VGND02 TerminationXR3W/L 2/50XR4W/L 2/50R substrate → VGND03 Compensation and signal passivesXR26W/L 2/50XR27W/L 2/50R substrate → VGNDModels: ppolyf_u_1k \ No newline at end of file diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/testbench.spice b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..c2f4c0717c6d5c723b516db53ed527e76ce5ebc6 --- /dev/null +++ b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/testbench.spice @@ -0,0 +1,28 @@ +* GF180MCU nominal characterization: 3.3 V, 27 C, typical models. +.include "support/models.spice" +.include "dut.spice" +.include "parameters.spice" +.temp 27 +VDD unused 0 3.3 +CLOAD out 0 1p +XDUT b7 b1 b0 b2 b3 b4 b5 b6 out 0 r2r +V0 b0 0 PWL(0 0 10n 0 10.1n {3.3*bit0}) +V1 b1 0 PWL(0 0 10n 0 10.1n {3.3*bit1}) +V2 b2 0 PWL(0 0 10n 0 10.1n {3.3*bit2}) +V3 b3 0 PWL(0 0 10n 0 10.1n {3.3*bit3}) +V4 b4 0 PWL(0 0 10n 0 10.1n {3.3*bit4}) +V5 b5 0 PWL(0 0 10n 0 10.1n {3.3*bit5}) +V6 b6 0 PWL(0 0 10n 0 10.1n {3.3*bit6}) +V7 b7 0 PWL(0 0 10n 0 10.1n {3.3*bit7}) +.control +tran 1n 2u +meas tran output_v find v(out) at=1.9u +meas tran early_v find v(out) at=1u +let expected=3.3*(v(b0)/3.3+2*v(b1)/3.3+4*v(b2)/3.3+8*v(b3)/3.3+16*v(b4)/3.3+32*v(b5)/3.3+64*v(b6)/3.3+128*v(b7)/3.3)/256 +let error_v=abs(output_v-expected[length(expected)-1]) +let settling_error_v=abs(early_v-expected[length(expected)-1]) +print error_v settling_error_v +write waveform.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..2fa9c04b3000dad42b2aa48155150b1c0ab7e8be --- /dev/null +++ b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md @@ -0,0 +1,86 @@ +# Eight-Bit R-2R DAC Core Layout Task + +## Objective + +Implement `r2r` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Eight-bit passive voltage conversion with ideal external bit drivers and a 1 pF output load; zero, eight one-hot codes and full scale. + +## Inputs and Interface + +The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration. + +Ordered subcircuit and GDS interface: `b7, b1, b0, b2, b3, b4, b5, b6, out, VGND`. +b0–b7: ideal-driver bit inputs (b0 is LSB); out: analog output; VGND: substrate and ladder return. + +Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together. + +## Operating Conditions + +Use 3.3 V bit-driver levels and 27 C, with 1 pF from out to VGND. Evaluate codes 0, 1, 2, 4, 8, 16, 32, 64, 128 and 255 separately. bit0 is the least significant bit. Each bit starts at 0 V and changes from 10 ns to 10.1 ns to 3.3*bitN V. Simulate through 2 us with a 1 ns requested step. The expected settled voltage is 3.3*code/256 V. The external drivers and load are testbench components, outside the required passive circuit. + +Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope. + +## Physical Requirements + +Submit a nonempty GDS with top cell `r2r` and at most 10485760 bytes. Its functional bounding box must not exceed 200 by 200 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is: + +`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`. + +Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block. + +LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `accuracy` | Absolute difference between output at 1.9 us and 3.3*code/256, checked independently for each declared code. | V | minimize / ratio | 0 … +∞ | 1e-06 | +| `settling` | Absolute difference between output at 1 us and 3.3*code/256 after the 10 ns input transition. | V | minimize / ratio | 0 … +∞ | 1e-06 | + +Area reference: **8727.76 um2**. 27 expanded device instances; sum of device/contact envelopes 5616.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **4**; it is independent of +the reference-relative task score. + + +### Score weights + +Passive R-2R DAC: conversion accuracy 63%; dynamic residual 27%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `accuracy` | 0.630000000000 | +| `settling` | 0.270000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/reference/r2r.gds b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/reference/r2r.gds new file mode 100644 index 0000000000000000000000000000000000000000..63efad9138b3a1bc0907d5c3bc7c2d0afad6fb35 Binary files /dev/null and b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/reference/r2r.gds differ diff --git a/tasks/gf180mcuD/pdk.toml b/tasks/gf180mcuD/pdk.toml new file mode 100644 index 0000000000000000000000000000000000000000..bf2a27112a382ee6e7bd22840c44ce8e65c4227a --- /dev/null +++ b/tasks/gf180mcuD/pdk.toml @@ -0,0 +1,721 @@ +[agent] +id = "gf180mcuD" +support_profiles = [ + "models", + "physical", + "magic", +] +checks = [ + [ + "python", + "-c", + "import os, pya; from pathlib import Path; from cells.draw_fet import draw_nfet; from cells.layers_def import layer; t=pya.Technology(); t.load(str(Path(os.environ['PDK_PATH'], 'libs.tech/klayout/tech/gf180mcu.lyt'))); assert t.name; c=draw_nfet(w_gate=0.42); c.write_gds('/workspace/gf180-smoke.gds'); l=pya.Layout(); l.read('/workspace/gf180-smoke.gds'); assert pya.Region(l.top_cell().begin_shapes_rec(l.layer(*layer['comp']))).area()>0", + ], +] + +[agent.sources.gf180mcuD] +installation = true +path = "gf180mcuD" + +[agent.environment] +USER = "agent" +ICLAYOUT_BENCH_PDK = "gf180mcuD" +PDK_ROOT = "/resources/pdks" +PDK_PATH = "/resources/pdks/gf180mcuD" +KLAYOUT_PATH = "/resources/pdks/gf180mcuD/libs.tech/klayout" +PYTHONPATH = "/resources/pdks/gf180mcuD/libs.tech/klayout/tech/pymacros" + +[source] +kind = "ciel" +family = "gf180mcu" +version = "1689ac3f2dc763876eaf967227c7dfe831b031ae" +libraries = [ + "gf180mcu_fd_pr", +] +license = "Apache-2.0; retained component notices" + +[profiles.models] +check = [ + "python", + "/resources/pdk-check.py", + "models", + "nfet_03v3", + "models.spice", + "--voltage", + "3.3", + "--length", + "0.28u", +] + +[profiles.models.files."design.spice"] +path = "gf180mcuD/libs.tech/ngspice/design.spice" +format = "text" + +[profiles.models.files."sm141064.spice"] +path = "gf180mcuD/libs.tech/ngspice/sm141064.spice" +format = "text" + +[profiles.models.files."sm141064_mim.spice"] +path = "gf180mcuD/libs.tech/ngspice/sm141064_mim.spice" +format = "text" + +[profiles.models.generated."models.spice"] +format = "spice" +content = """ +.include \"design.spice\" +.lib \"sm141064.spice\" typical +.lib \"sm141064.spice\" res_typical +.lib \"sm141064.spice\" bjt_typical +.lib \"sm141064.spice\" mimcap_typical +.param sw_stat_global=0 sw_stat_mismatch=0 +""" + +[profiles.models.generated.".spiceinit"] +format = "text" +content = """ +set ngbehavior=hsa +set num_threads=1 +set sourcepath=( . /workspace/support ) +""" + +[profiles.magic.files."gf180mcuD.tech"] +path = "gf180mcuD/libs.tech/magic/gf180mcuD.tech" +format = "text" + +[profiles.physical.files."drc/connectivity.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/connectivity.rb" +format = "text" + +[profiles.physical.files."drc/generic_layers.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/generic_layers.rb" +format = "text" + +[profiles.physical.files."drc/gf180mcu.drc"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/gf180mcu.drc" +format = "text" + +[profiles.physical.files."drc/helper.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/helper.rb" +format = "text" + +[profiles.physical.files."drc/options.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/options.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/antenna.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/antenna.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/comp.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/comp.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/contact.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/contact.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/cup.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/cup.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/density.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/density.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/dnwell.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/dnwell.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/drc_bjt.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/drc_bjt.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/dualgate.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/dualgate.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/dummy_comp.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/dummy_comp.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/dummy_exclude.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/dummy_exclude.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/dummy_metal.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/dummy_metal.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/dummy_poly2.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/dummy_poly2.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/efuse.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/efuse.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/esd.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/esd.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/geom.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/geom.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/guard_ring.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/guard_ring.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/hres.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/hres.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/ldnmos.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/ldnmos.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/ldpmos.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/ldpmos.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/lres.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/lres.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/lvpwell.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/lvpwell.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/lvs_bjt.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/lvs_bjt.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/mcell.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/mcell.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/metal.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/metal.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/metaltop.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/metaltop.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/metaltop_30k.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/metaltop_30k.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/mim_a.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/mim_a.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/mim_b.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/mim_b.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/mslot.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/mslot.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/nat.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/nat.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/nplus.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/nplus.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/nwell.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/nwell.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/otp_mk.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/otp_mk.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/poly2.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/poly2.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/pplus.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/pplus.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/pres.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/pres.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/sab.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/sab.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/sram_3p3.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/sram_3p3.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/sram_5p0.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/sram_5p0.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/via.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/via.rb" +format = "text" + +[profiles.physical.files."drc/rule_decks/ymtp_mk.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_decks/ymtp_mk.rb" +format = "text" + +[profiles.physical.files."drc/rule_framework.rb"] +path = "gf180mcuD/libs.tech/klayout/tech/drc/rule_framework.rb" +format = "text" + +[profiles.physical.files."lvs/gf180mcu.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/gf180mcu.lvs" +format = "text" + +[[profiles.physical.files."lvs/gf180mcu.lvs".replace]] +old = "reader = RBA::NetlistSpiceReader.new(SubcircuitModelsReader.new)" +new = """ +# ICLayout-Bench adapter: official ngspice primitive X wrappers use total W, SI L/W. +class GF180SpiceReader < SubcircuitModelsReader + def wants_subcircuit(name) + %w[NFET_03V3 PFET_03V3 PPOLYF_U_1K].include?(name.upcase) + end + def element(circuit, ele, name, model, value, nets, params) + if ele == 'X' && %w[NFET_03V3 PFET_03V3].include?(model.upcase) + error('GF180 MOS requires four terminals') unless nets.size == 4 + return super(circuit, 'M', name, model, value, nets, params) + elsif ele == 'X' && model.upcase == 'PPOLYF_U_1K' + error('GF180 resistor requires three terminals') unless nets.size == 3 + mapped = {'W' => params.fetch('R_WIDTH'), 'L' => params.fetch('R_LENGTH')} + return super(circuit, 'R', name, model, 0, nets, mapped) + end + super + end +end + +reader = RBA::NetlistSpiceReader.new(GF180SpiceReader.new)""" + +[profiles.physical.files."lvs/rule_decks/bjt_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/bjt_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/bjt_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/bjt_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/bjt_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/bjt_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/custom_classes.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/custom_classes.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/devices_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/diode_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/diode_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/efuse_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/efuse_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/efuse_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/efuse_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/efuse_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/efuse_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/general_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/general_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/layers_definitions.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/layers_definitions.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mimcap_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mimcap_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mimcap_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mimcap_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mimcap_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mimcap_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mos_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mos_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mos_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mos_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mos_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mos_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mos_sab_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mos_sab_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/mos_sab_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/mos_sab_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/moscap_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/moscap_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/moscap_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/moscap_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/res_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/res_connections.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/res_derivations.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/res_derivations.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/res_extraction.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/res_extraction.lvs" +format = "text" + +[profiles.physical.files."lvs/rule_decks/substrate_connections.lvs"] +path = "gf180mcuD/libs.tech/klayout/tech/lvs/rule_decks/substrate_connections.lvs" +format = "text" + +[profiles.physical.generated."drc.json"] +format = "text" +content = """ +{ + \"deck\": \"drc/gf180mcu.drc\", + \"variables\": { + \"variant\": \"D\", + \"run_mode\": \"flat\", + \"workers\": \"2\", + \"threads\": \"2\", + \"decks\": \"all,-density\" + }, + \"scope\": \"GF180MCU D standalone block FEOL, BEOL, connectivity, manufacturing grid and antenna rules. Chip-level density and seal-ring rules are outside the block boundary. No marker waivers.\", + \"required_categories\": [ + \"'DF.1a_LV'\", + \"'CO.1'\", + \"'PL.1_LV'\", + \"'M1.1'\", + \"'ANT.1'\", + \"comp_OFFGRID\", + \"comp_ACUTE\", + \"'DCF.1a'\" + ] +} +""" + +[profiles.physical.generated."lvs.json"] +format = "text" +content = """ +{ + \"deck\": \"lvs/gf180mcu.lvs\", + \"layer_names\": { + \"metal1\": \"metal1_con\" + }, + \"variables\": { + \"metal_top\": \"11K\", + \"metal_level\": \"5LM\", + \"mim_option\": \"B\", + \"mim_cap\": \"2\", + \"poly_res\": \"1k\", + \"run_mode\": \"flat\", + \"combine\": \"true\", + \"spice_net_names\": \"true\", + \"consider_dn_dw_features\": \"true\", + \"check_ports\": \"true\" + }, + \"scope\": \"GF180MCU D nominal device connectivity and dimensions with named top-level ports; nfet_03v3/pfet_03v3 total-width X wrappers and ppolyf_u_1k SI dimensions. Standard isolated substrate domain, explicit substrate and well contacts required.\" +} +""" + +[notices.LICENSE] +format = "text" +content = """ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + \"License\" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + \"Licensor\" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + \"Legal Entity\" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an \"AS IS\" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets \"[]\" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same \"printed page\" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the \"License\"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an \"AS IS\" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +""" + +[notices.AUTHORS] +format = "text" +content = """ +# This is the list of GlobalFoundries PDK's significant contributors. +# +# This does not necessarily list everyone who has contributed code, +# especially since many employees of one corporation may be contributing. +# To see the full list of contributors, see the revision history in +# source control. + +# Companies +Google LLC +GlobalFoundries +Efabless Corporation +Mabrains LLC + +# Individuals +tansell@google.com, me@mith.ro (Tim 'mithro' Ansell) +proppy@google.com (Johan 'proppy' Euphrosine) +tim@efabless.com (Tim Edwards) +mkk@efabless.com (Mohamed Kassem) +stefan.schippers@gmail.com (Stefan Schippers) +amro_tork@mabrains.com (Amro Tork) +farag_agoor@mabrains.com (Farag Agoor) +mohanad_mohamed@mabrains.com (Mohanad Mohammed) +leomoser99@gmail.com (Leo Moser) +clyde.laforge@cern.ch (Clyde Laforge) + +# This is the list of GlobalFoundries PDK's significant contributors. +# +# This does not necessarily list everyone who has contributed code, +# especially since many employees of one corporation may be contributing. +# To see the full list of contributors, see the revision history in +# source control. + +# Companies +Google LLC +GlobalFoundries +Efabless Corporation +Mabrains LLC + +# Individuals +tansell@google.com, me@mith.ro (Tim 'mithro' Ansell) +proppy@google.com (Johan 'proppy' Euphrosine) +tim@efabless.com (Tim Edwards) +mkk@efabless.com (Mohamed Kassem) +stefan.schippers@gmail.com (Stefan Schippers) +amro_tork@mabrains.com (Amro Tork) +farag_agoor@mabrains.com (Farag Agoor) +mohanad_mohamed@mabrains.com (Mohanad Mohammed) +rehab_hassan@mabrains.com (Rehab Hassan) +""" + +[notices.NOTICE] +format = "text" +content = """ +GF180MCU primitive models and KLayout rules: GlobalFoundries PDK Authors. +Magic technology and installation: open-pdks contributors. +Prebuilt distribution: https://github.com/fossi-foundation/ciel-releases +The reviewed LVS reader adapter maps ngspice X wrappers to native devices. +""" diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/LICENSE b/tasks/gf180mcuD/tt_tnt_gf_vco/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..1d36b303b17a1fb426660c058a4c2bd4040b02f1 --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/LICENSE @@ -0,0 +1,231 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. 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If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + +GF180 primitive symbol export expressions in materials/circuit.spice +================================================================== +Copyright 2022 GlobalFoundries PDK Authors. Licensed under Apache-2.0. +Source: gf180mcu_fd_pr/cells/xschem/symbols; exported MOS geometry expressions. +# This is the list of GlobalFoundries PDK's significant contributors. +# +# This does not necessarily list everyone who has contributed code, +# especially since many employees of one corporation may be contributing. +# To see the full list of contributors, see the revision history in +# source control. + +# Companies +Google LLC +GlobalFoundries +Efabless Corporation +Mabrains LLC + +# Individuals +tansell@google.com, me@mith.ro (Tim 'mithro' Ansell) +proppy@google.com (Johan 'proppy' Euphrosine) +tim@efabless.com (Tim Edwards) +mkk@efabless.com (Mohamed Kassem) +stefan.schippers@gmail.com (Stefan Schippers) +amro_tork@mabrains.com (Amro Tork) +farag_agoor@mabrains.com (Farag Agoor) +mohanad_mohamed@mabrains.com (Mohanad Mohammed) + +The Apache-2.0 license text above also applies to these expressions. diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..468132d2d126ee9c0727c35790c212a4199433d8 --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml @@ -0,0 +1,1012 @@ +in_core = true +kind = "layout_case" +id = "gf180mcuD.tt_tnt_gf_vco.vco" +title = "Quadrature Voltage-Controlled Oscillator" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "e1113550941284d9688713e8cf2193bdd555f5b92db6e57fc4dccfd93edce5f1" + +[[assets]] +path = "reference/vco.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "bb9965bde8204258d632097e28f91ebaf0e8bbfeb663cd0d89f619b9faf3f2b5" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_vco" +coefficient = 8 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = 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+[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "GND", + "VDD", + "ctrl", + "out_0", + "out_90", + "out_180", + "out_270", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +frequency_lo = "Hz" +frequency_hi = "Hz" +tuning_ratio = "1" +phase90_lo = "1" +phase90_hi = "1" +phase180_lo = "1" +phase180_hi = "1" +phase270_lo = "1" +phase270_hi = "1" +min0_lo = "V" +min0_hi = "V" +min90_lo = "V" +min90_hi = "V" +min180_lo = "V" +min180_hi = "V" +min270_lo = "V" +min270_hi = "V" +max0_lo = "V" +max0_hi = "V" +max90_lo = "V" +max90_hi = "V" +max180_lo = "V" +max180_hi = "V" +max270_lo = "V" +max270_hi = "V" +power_lo = "W" +power_hi = "W" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "low_control_frequency" +category = "performance" +observations = [ + "nominal:frequency_lo", +] +unit = "Hz" +direction = "target" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:frequency_lo", +] +normalization = "target" +scale = 150000000.0 +lower = 0 + +[[task.evaluation.metrics]] +id = "high_control_frequency" +category = "performance" +observations = [ + "nominal:frequency_hi", +] +unit = "Hz" +direction = "target" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:frequency_hi", +] +normalization = "target" +scale = 300000000.0 +lower = 0 + +[[task.evaluation.metrics]] +id = "tuning" +category = "performance" +observations = [ + "nominal:tuning_ratio", +] +unit = "1" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:tuning_ratio", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "quadrature90" +category = "performance" +observations = [ + "nominal:phase90_lo", + "nominal:phase90_hi", +] +unit = "1" +direction = "target" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:phase90_lo", + "source_nominal:phase90_hi", +] +normalization = "target" +scale = 1.0 + +[[task.evaluation.metrics]] +id = "quadrature180" +category = "performance" +observations = [ + "nominal:phase180_lo", + "nominal:phase180_hi", +] +unit = "1" +direction = "target" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:phase180_lo", + "source_nominal:phase180_hi", +] +normalization = "target" +scale = 1.0 + +[[task.evaluation.metrics]] +id = "quadrature270" +category = "performance" +observations = [ + "nominal:phase270_lo", + "nominal:phase270_hi", +] +unit = "1" +direction = "target" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:phase270_lo", + "source_nominal:phase270_hi", +] +normalization = "target" +scale = 1.0 + +[[task.evaluation.metrics]] +id = "low" +category = "performance" +observations = [ + "nominal:min0_lo", + "nominal:min0_hi", + "nominal:min90_lo", + "nominal:min90_hi", + "nominal:min180_lo", + "nominal:min180_hi", + "nominal:min270_lo", + "nominal:min270_hi", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.33 + +[[task.evaluation.metrics]] +id = "high" +category = "performance" +observations = [ + "nominal:max0_lo", + "nominal:max0_hi", + "nominal:max90_lo", + "nominal:max90_hi", + "nominal:max180_lo", + "nominal:max180_hi", + "nominal:max270_lo", + "nominal:max270_hi", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 2.97 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:power_lo", + "nominal:power_hi", +] +unit = "W" +direction = "minimize" +aggregation = "min" +dimension = "supply" +baseline = [ + "source_nominal:power_lo", + "source_nominal:power_hi", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 907.08 +rationale = "Quadrature VCO: frequency targets 31.5%; tuning 18%; quadrature 27%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +high_control_frequency = 0.1575 +low_control_frequency = 0.1575 +tuning = 0.18 +quadrature180 = 0.09 +quadrature270 = 0.09 +quadrature90 = 0.09 +supply = 0.135 + +[task.evaluation.pre_layout] +source_report_sha256 = "a5b35f2742ccca984ae926050bd4a5c0a2e8e9107803304c36b811323eebbd81" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +frequency_lo = "Hz" +frequency_hi = "Hz" +tuning_ratio = "1" +phase90_lo = "1" +phase90_hi = "1" +phase180_lo = "1" +phase180_hi = "1" +phase270_lo = "1" +phase270_hi = "1" +min0_lo = "V" +min0_hi = "V" +min90_lo = "V" +min90_hi = "V" +min180_lo = "V" +min180_hi = "V" +min270_lo = "V" +min270_hi = "V" +max0_lo = "V" +max0_hi = "V" +max90_lo = "V" +max90_hi = "V" +max180_lo = "V" +max180_hi = "V" +max270_lo = "V" +max270_hi = "V" +power_lo = "W" +power_hi = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.values] + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "10807fd6a4d31baac59badfa27b3e7ff84ccde6ee929b29b745f7b3ec7f11f50" +dut = "021943933973e205dfb533131232917d18d1ffe8b24bedc5e45534992e2a1615" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.frequency_hi] +value = 245975700.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.frequency_lo] +value = 97631840.0 +unit = "Hz" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max0_hi] +value = 3.317763 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max0_lo] +value = 3.309453 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max180_hi] +value = 3.317763 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max180_lo] +value = 3.309453 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max270_hi] +value = 3.317763 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max270_lo] +value = 3.309453 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max90_hi] +value = 3.317764 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.max90_lo] +value = 3.309453 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min0_hi] +value = -0.0107174 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min0_lo] +value = -0.004189301 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min180_hi] +value = -0.01070071 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min180_lo] +value = -0.004189262 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min270_hi] +value = -0.01069855 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min270_lo] +value = -0.004189316 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min90_hi] +value = -0.01069834 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.min90_lo] +value = -0.004189306 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase180_hi] +value = 0.5000085 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase180_lo] +value = 0.4999975 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase270_hi] +value = 0.7500184 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase270_lo] +value = 0.7500025 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase90_hi] +value = 0.2500067 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase90_lo] +value = 0.2499969 +unit = "1" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.power_hi] +value = 0.002622109 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.power_lo] +value = 0.001899201 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.tuning_ratio] +value = 2.51942 +unit = "1" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/smunaut/tt_tnt_gf_vco/tree/897b3ec12ed693161fb56f4205d1b19dc5e56c1a/xschem/vco.sch" + +[qualification] +reference = "reference/vco.gds" + +[presentation] +category = "Mixed-signal" +summary = "Generates quadrature oscillation with a voltage-controlled tuning response." diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..d33aa44e20e6e5770e8bfea851b613d34dad5e15 --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice @@ -0,0 +1,74 @@ +* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed. +.subckt vco GND VDD ctrl out_0 out_90 out_180 out_270 +*.ipin VDD +*.ipin GND +*.ipin ctrl +*.opin out_0 +*.opin out_180 +*.opin out_90 +*.opin out_270 +x1 GND VDD s0_p s0_n s1_p s1_n bias vco_dly +x2 GND VDD s1_p s1_n s2_p s2_n bias vco_dly +x3 GND VDD s2_p s2_n s3_p s3_n bias vco_dly +x4 GND VDD s3_p s3_n s0_n s0_p bias vco_dly +XM1 bias bias VDD VDD pfet_03v3 L=0.5u W=6.0u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 net1 net1 GND GND nfet_03v3 L=0.5u W=2u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 bias ctrl net1 GND nfet_03v3 L=0.28u W=2u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +x5 GND VDD s2_p s2_n out_90 out_270 vco_out_p +x6 GND VDD s0_p s0_n out_0 out_180 vco_out_p +.ends + +* expanding symbol: vco_dly.sym # of pins=7 +.subckt vco_dly GND VDD in_p in_n out_p out_n bias +*.opin out_p +*.ipin VDD +*.ipin GND +*.opin out_n +*.ipin in_p +*.ipin in_n +*.ipin bias +XM1 out_n in_p GND GND nfet_03v3 L=0.4u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 out_p in_p VDD GND nfet_03v3 L=0.4u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 out_p in_n GND GND nfet_03v3 L=0.4u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 out_n in_n VDD GND nfet_03v3 L=0.4u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 out_p out_n net1 VDD pfet_03v3 L=0.4u W=3.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 out_n out_p net1 VDD pfet_03v3 L=0.4u W=3.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 net1 bias VDD VDD pfet_03v3 L=0.5u W=6.0u nf=2 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: vco_out_p.sym # of pins=6 +.subckt vco_out_p GND VDD in_p in_n out_p out_n +*.ipin in_p +*.ipin VDD +*.ipin GND +*.ipin in_n +*.opin out_p +*.opin out_n +XM4 int_p int_n GND GND nfet_03v3 L=0.28u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 int_n int_p GND GND nfet_03v3 L=0.28u W=1u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 int_p in_n VDD VDD pfet_03v3 L=0.28u W=2.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM1 int_n in_p VDD VDD pfet_03v3 L=0.28u W=2.0u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 out_p int_n VDD VDD pfet_03v3 L=0.28u W=8.0u nf=4 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 out_p int_n GND GND nfet_03v3 L=0.28u W=4.0u nf=4 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 out_n int_p GND GND nfet_03v3 L=0.28u W=4.0u nf=4 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 out_n int_p VDD VDD pfet_03v3 L=0.28u W=8.0u nf=4 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/schematic.svg b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..d667c1b41197ab2a546b847fd702959ef63d4922 --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/schematic.svg @@ -0,0 +1 @@ +vco{"format": "iclayout-schematic", "case_id": "gf180mcuD.tt_tnt_gf_vco.vco", "netlist_sha256": "021943933973e205dfb533131232917d18d1ffe8b24bedc5e45534992e2a1615", "project_sha256": "ff1838feccbde14ef1088185d1c0bf49730c2498a128a37e0b66860b4d349c57", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/tt_tnt_gf_vco/", "sheets": ["vco", "vco_dly", "vco_out_p"], "banks": [], "source_netlist": "tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}vcoGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nGNDVDDin_pin_nout_pout_ns0_ps0_ps0_ns0_ns1_ps1_ps1_ns2_ps2_ns3_ps3_ps3_nGNDGNDGNDGNDVDDbiasbiasbiasbiasVDDctrlGNDbiasnet1s2_ps2_nout_90out_270s0_ps0_nout_0out_180GNDGNDVDDGNDVDDctrlout_0out_90out_180out_270vcogf180mcuD · tt_tnt_gf_vco | W/L in µm · display rounded to 3 significant figures01 Quadrature ringx1vco_dlyx2vco_dlyx4vco_dlyx3vco_dly02 Control-to-biasXM16/0.5 NF=2XM22/0.28 NF=2XM32/0.5 NF=2P bulk → VDDN bulk → GND03 Phase output buffersx5vco_out_px6vco_out_pModels: vco_dly · pfet_03v3 · nfet_03v3 · vco_out_pvco_dlybiasin_pGNDin_nnet1VDDout_nout_pGNDVDDin_pin_nout_pout_nbiasvco_dlygf180mcuD · tt_tnt_gf_vco | W/L in µm · display rounded to 3 significant figures01 Cross-coupled delay cellXM76/0.5 NF=2XM53/0.4XM63/0.4XM11/0.4XM31/0.4XM41/0.4XM21/0.4P bulk → VDDN bulk → GNDModels: nfet_03v3 · pfet_03v3vco_out_pout_pint_nVDDout_nint_pGNDin_pin_nVDDGNDint_nint_pGNDVDDin_pin_nout_pout_nvco_out_pgf180mcuD · tt_tnt_gf_vco | W/L in µm · display rounded to 3 significant figures01 Differential receiverXM12/0.28XM22/0.28XM31/0.28XM41/0.28P bulk → VDDN bulk → GND02 Phase output invertersXM58/0.28 NF=4XM78/0.28 NF=4XM64/0.28 NF=4XM84/0.28 NF=4P bulk → VDDN bulk → GNDModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/testbench.spice b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..20a3702b7baf92c4bfec997cbca4ed226711c78a --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/testbench.spice @@ -0,0 +1,77 @@ +* GF180MCU nominal characterization: 3.3 V, 27 C, typical models. +.include "support/models.spice" +.include "dut.spice" +.include "parameters.spice" +.temp 27 +VDD_LO vdd_lo 0 PWL(0 0 1n 3.3) +VDD_HI vdd_hi 0 PWL(0 0 1n 3.3) +Vlo ctrl_lo 0 1.65 +XDUT_lo 0 vdd_lo ctrl_lo o0_lo o90_lo o180_lo o270_lo vco +C0_lo o0_lo 0 50f +C90_lo o90_lo 0 50f +C180_lo o180_lo 0 50f +C270_lo o270_lo 0 50f +Vhi ctrl_hi 0 2.1 +XDUT_hi 0 vdd_hi ctrl_hi o0_hi o90_hi o180_hi o270_hi vco +C0_hi o0_hi 0 50f +C90_hi o90_hi 0 50f +C180_hi o180_hi 0 50f +C270_hi o270_hi 0 50f +.control +tran .02n 600n +meas tran period_lo trig v(o0_lo) val=1.65 rise=1 td=400n targ v(o0_lo) val=1.65 rise=2 td=400n +let frequency_lo=1/period_lo +print frequency_lo +meas tran delta90_lo trig v(o0_lo) val=1.65 rise=1 td=400n targ v(o90_lo) val=1.65 rise=1 td=400n +let phase90_lo=delta90_lo/period_lo +let phase90_lo=phase90_lo-floor(phase90_lo) +print phase90_lo +meas tran delta180_lo trig v(o0_lo) val=1.65 rise=1 td=400n targ v(o180_lo) val=1.65 rise=1 td=400n +let phase180_lo=delta180_lo/period_lo +let phase180_lo=phase180_lo-floor(phase180_lo) +print phase180_lo +meas tran delta270_lo trig v(o0_lo) val=1.65 rise=1 td=400n targ v(o270_lo) val=1.65 rise=1 td=400n +let phase270_lo=delta270_lo/period_lo +let phase270_lo=phase270_lo-floor(phase270_lo) +print phase270_lo +meas tran min0_lo min v(o0_lo) from=400n to=600n +meas tran max0_lo max v(o0_lo) from=400n to=600n +meas tran min90_lo min v(o90_lo) from=400n to=600n +meas tran max90_lo max v(o90_lo) from=400n to=600n +meas tran min180_lo min v(o180_lo) from=400n to=600n +meas tran max180_lo max v(o180_lo) from=400n to=600n +meas tran min270_lo min v(o270_lo) from=400n to=600n +meas tran max270_lo max v(o270_lo) from=400n to=600n +meas tran period_hi trig v(o0_hi) val=1.65 rise=1 td=400n targ v(o0_hi) val=1.65 rise=2 td=400n +let frequency_hi=1/period_hi +print frequency_hi +meas tran delta90_hi trig v(o0_hi) val=1.65 rise=1 td=400n targ v(o90_hi) val=1.65 rise=1 td=400n +let phase90_hi=delta90_hi/period_hi +let phase90_hi=phase90_hi-floor(phase90_hi) +print phase90_hi +meas tran delta180_hi trig v(o0_hi) val=1.65 rise=1 td=400n targ v(o180_hi) val=1.65 rise=1 td=400n +let phase180_hi=delta180_hi/period_hi +let phase180_hi=phase180_hi-floor(phase180_hi) +print phase180_hi +meas tran delta270_hi trig v(o0_hi) val=1.65 rise=1 td=400n targ v(o270_hi) val=1.65 rise=1 td=400n +let phase270_hi=delta270_hi/period_hi +let phase270_hi=phase270_hi-floor(phase270_hi) +print phase270_hi +meas tran min0_hi min v(o0_hi) from=400n to=600n +meas tran max0_hi max v(o0_hi) from=400n to=600n +meas tran min90_hi min v(o90_hi) from=400n to=600n +meas tran max90_hi max v(o90_hi) from=400n to=600n +meas tran min180_hi min v(o180_hi) from=400n to=600n +meas tran max180_hi max v(o180_hi) from=400n to=600n +meas tran min270_hi min v(o270_hi) from=400n to=600n +meas tran max270_hi max v(o270_hi) from=400n to=600n +let tuning_ratio=frequency_hi/frequency_lo +print tuning_ratio +let pwr_lo=-3.3*i(vdd_lo) +let pwr_hi=-3.3*i(vdd_hi) +meas tran power_lo avg pwr_lo from=400n to=600n +meas tran power_hi avg pwr_hi from=400n to=600n +write waveform.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..8b381579b2ce96030bc0fe3f860f60236e20ca09 --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md @@ -0,0 +1,98 @@ +# Quadrature Voltage-Controlled Oscillator Layout Task + +## Objective + +Implement `vco` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Four-phase oscillation, quadrature and frequency tuning at control voltages 1.65 V and 2.10 V, with 50 fF on each output. + +## Inputs and Interface + +The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration. + +Ordered subcircuit and GDS interface: `GND, VDD, ctrl, out_0, out_90, out_180, out_270`. +GND/VDD: return/supply; ctrl: tuning voltage; out_0/out_90/out_180/out_270: quadrature outputs. + +Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together. + +## Operating Conditions + +Use 27 C and two independent copies of the submitted circuit at ctrl = 1.65 V and 2.10 V. Each copy has its own ideal supply ramping from 0 V at 0 ns to 3.3 V at 1 ns and 50 fF from each output to ground. Simulate through 600 ns with a 0.02 ns requested step. Characterize steady oscillation over 400–600 ns. Each operating point must meet every applicable requirement; their supply powers are checked individually. + +Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope. + +## Physical Requirements + +Submit a nonempty GDS with top cell `vco` and at most 10485760 bytes. Its functional bounding box must not exceed 700 by 240 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is: + +`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`. + +Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block. + +LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `low_control_frequency` | Inverse period between the first two out_0 rising 1.65 V crossings after 400 ns at ctrl=1.65 V. | Hz | target / target | 0 … +∞ | 150000000.0 | +| `high_control_frequency` | The same frequency measurement at ctrl=2.10 V. | Hz | target / target | 0 … +∞ | 300000000.0 | +| `tuning` | Frequency at 2.10 V divided by frequency at 1.65 V. | 1 | maximize / ratio | 0 … +∞ | — | +| `quadrature90` | First out_90 versus out_0 rising-crossing displacement after 400 ns, divided by period and reduced modulo one cycle. | 1 | target / target | −∞ … +∞ | 1.0 | +| `quadrature180` | The same phase measurement for out_180. | 1 | target / target | −∞ … +∞ | 1.0 | +| `quadrature270` | The same phase measurement for out_270. | 1 | target / target | −∞ … +∞ | 1.0 | +| `low` | Minimum voltage on each output over 400–600 ns at each control voltage. | V | functional check | −∞ … 0.33 | — | +| `high` | Maximum voltage on each output over 400–600 ns at each control voltage. | V | functional check | 2.97 … +∞ | — | +| `supply` | Average delivered supply power over 400–600 ns, separately for each control voltage. | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **907.08 um2**. 47 expanded device instances; sum of device/contact envelopes 540.0800 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **8**; it is independent of +the reference-relative task score. + + +### Score weights + +Quadrature VCO: frequency targets 31.5%; tuning 18%; quadrature 27%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `high_control_frequency` | 0.157500000000 | +| `low_control_frequency` | 0.157500000000 | +| `tuning` | 0.180000000000 | +| `quadrature180` | 0.090000000000 | +| `quadrature270` | 0.090000000000 | +| `quadrature90` | 0.090000000000 | +| `supply` | 0.135000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/reference/vco.gds b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/reference/vco.gds new file mode 100644 index 0000000000000000000000000000000000000000..3318323ea51c29370b9c5f5270d934ec71188604 --- /dev/null +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/reference/vco.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bb9965bde8204258d632097e28f91ebaf0e8bbfeb663cd0d89f619b9faf3f2b5 +size 201870 diff --git a/tasks/gf180mcuD/voidwalkers-scandff/LICENSE b/tasks/gf180mcuD/voidwalkers-scandff/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..9a73a0626c8232d265f07d041ec0d5da0c02c149 --- /dev/null +++ b/tasks/gf180mcuD/voidwalkers-scandff/LICENSE @@ -0,0 +1,253 @@ +MIT License + +Copyright (c) 2025 Jianxun Zhu + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + +GF180 primitive symbol export expressions in materials/circuit.spice +================================================================== +Copyright 2022 GlobalFoundries PDK Authors. Licensed under Apache-2.0. +Source: gf180mcu_fd_pr/cells/xschem/symbols; exported MOS geometry expressions. +# This is the list of GlobalFoundries PDK's significant contributors. +# +# This does not necessarily list everyone who has contributed code, +# especially since many employees of one corporation may be contributing. +# To see the full list of contributors, see the revision history in +# source control. + +# Companies +Google LLC +GlobalFoundries +Efabless Corporation +Mabrains LLC + +# Individuals +tansell@google.com, me@mith.ro (Tim 'mithro' Ansell) +proppy@google.com (Johan 'proppy' Euphrosine) +tim@efabless.com (Tim Edwards) +mkk@efabless.com (Mohamed Kassem) +stefan.schippers@gmail.com (Stefan Schippers) +amro_tork@mabrains.com (Amro Tork) +farag_agoor@mabrains.com (Farag Agoor) +mohanad_mohamed@mabrains.com (Mohanad Mohammed) + +The MIT terms above apply to the source circuit; the following Apache-2.0 terms apply to these expressions. + + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..036c1b0fd24a638d9f35957ff08658842cdc9529 --- /dev/null +++ b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml @@ -0,0 +1,1307 @@ +in_core = true +kind = "layout_case" +id = "gf180mcuD.voidwalkers-scandff.scan_dff" +title = "Scan D Flip-Flop with Active-Low Reset" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "99ace8db2b9b5611c896d24f0fb95767f76f6568867a21be756c596f11345166" + +[[assets]] +path = "reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds" +role = "reference" +visibility = "maintainer" +format = "gds" +sha256 = "ffd6654d5505bf6340acbb3061ad81fab36951badda45b3bd3a8448be0fa00ab" + +[task] +hours = 3 +kind = "netlist_to_gds" +family = "gf180_scan_dff" +coefficient = 5 +environment = "gf180mcuD-typical-rc" + +[task.inputs.description] +path = "problem.md" +format = "text" +sha256 = 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0.23 +left_um = 0.0 +right_um = 0.0 + +[[task.constraints.hard.rails]] +name = "VSS" +layer = [ + 34, + 0, +] +connectivity_layer = "metal1" +y_um = 0.35000000000000003 +thickness_um = 0.23 +left_um = 0.0 +right_um = 0.0 + +[task.evaluation] +mode = "post_layout" + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" +requires = [ + "artifact", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +ports = [ + "S", + "VDD", + "Q", + "B", + "CLK", + "A", + "RN", + "VSS", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.measurements] +low19 = "V" +low59 = "V" +reset89 = "V" +reset99 = "V" +low139 = "V" +high39 = "V" +high79 = "V" +high119 = "V" +power_w = "W" +delay_data_rise = "s" +slew_data_rise = "s" +delay_data_fall = "s" +slew_data_fall = "s" +delay_scan_rise = "s" +slew_scan_rise = "s" +delay_scan_fall = "s" +slew_scan_fall = "s" +delay_reset_fall = "s" +slew_reset_fall = "s" + +[task.evaluation.jobs.parameters.values] + +[task.evaluation.jobs.parameters.exports] +waveform = "waveform.raw" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "low" +category = "performance" +observations = [ + "nominal:low19", + "nominal:low59", + "nominal:reset89", + "nominal:reset99", + "nominal:low139", +] +unit = "V" +direction = "minimize" +aggregation = "max" +upper = 0.33 + +[[task.evaluation.metrics]] +id = "high" +category = "performance" +observations = [ + "nominal:high39", + "nominal:high79", + "nominal:high119", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 2.97 + +[[task.evaluation.metrics]] +id = "supply" +category = "performance" +observations = [ + "nominal:power_w", +] +unit = "W" +direction = "minimize" +aggregation = "min" +dimension = "supply" +baseline = [ + "source_nominal:power_w", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "propagation_delay" +category = "performance" +observations = [ + "nominal:delay_data_rise", + "nominal:delay_data_fall", + "nominal:delay_scan_rise", + "nominal:delay_scan_fall", + "nominal:delay_reset_fall", +] +baseline = [ + "source_nominal:delay_data_rise", + "source_nominal:delay_data_fall", + "source_nominal:delay_scan_rise", + "source_nominal:delay_scan_fall", + "source_nominal:delay_reset_fall", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +normalization = "ratio" +lower = 0.0 + +[[task.evaluation.metrics]] +id = "output_transition" +category = "performance" +observations = [ + "nominal:slew_data_rise", + "nominal:slew_data_fall", + "nominal:slew_scan_rise", + "nominal:slew_scan_fall", + "nominal:slew_reset_fall", +] +baseline = [ + "source_nominal:slew_data_rise", + "source_nominal:slew_data_fall", + "source_nominal:slew_scan_rise", + "source_nominal:slew_scan_fall", + "source_nominal:slew_reset_fall", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +normalization = "ratio" +lower = 0.0 + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 175.5775 +rationale = "Scan flip-flop: clock-to-output delay 51%; output transition 17%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +propagation_delay = 0.51 +output_transition = 0.17 +supply = 0.17 + +[task.evaluation.pre_layout] +source_report_sha256 = "7c186efc01707e6576d7e22647bdb61c6ed569f153d08f49cbfed8c6f659cdfb" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:netlist" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +low19 = "V" +low59 = "V" +reset89 = "V" +reset99 = "V" +low139 = "V" +high39 = "V" +high79 = "V" +high119 = "V" +power_w = "W" +delay_data_rise = "s" +slew_data_rise = "s" +delay_data_fall = "s" +slew_data_fall = "s" +delay_scan_rise = "s" +slew_scan_rise = "s" +delay_scan_fall = "s" +slew_scan_fall = "s" +delay_reset_fall = "s" +slew_reset_fall = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.values] + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +waveform = "waveform.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "43d1b9312f6024b9fe2f2c55e841d741e915254ffa5d9a1e476ab406323c46dc" +dut = "659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_data_fall] +value = 5.492321e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_data_rise] +value = 5.498161e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_reset_fall] +value = 4.179378e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_scan_fall] +value = 5.492321e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_scan_rise] +value = 5.49924e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.high119] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.high39] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.high79] +value = 3.3 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.low139] +value = 3.669273e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.low19] +value = 6.604153e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.low59] +value = 3.66929e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.power_w] +value = 4.187209e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.reset89] +value = 5.576545e-08 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.reset99] +value = 7.300858e-09 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_data_fall] +value = 2.787912e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_data_rise] +value = 3.358882e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_reset_fall] +value = 2.787695e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_scan_fall] +value = 2.787912e-10 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_scan_rise] +value = 3.358867e-10 +unit = "s" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 180 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "drc.json" + +[toolchain.backends.drc.support_profiles] +support = "physical" + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +timeout_seconds = 180 +support = "build/support/gf180-physical" +profile = "lvs.json" + +[toolchain.backends.lvs.support_profiles] +support = "physical" + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 180 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-magic" +technology = "gf180mcuD.tech" +tech_name = "gf180mcuD" +style = "ngspice()" +gds_readonly = false +grid_subdivision = 10 +case_insensitive_ports = true +timeout_seconds = 240 + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.ngspice] +type = "ngspice-docker" + +[toolchain.backends.ngspice.settings] +image = "iclayout-bench-tools:local" +support = "build/support/gf180-models" +timeout_seconds = 240 + +[toolchain.backends.ngspice.support_profiles] +support = "models" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "ngspice" + +[origin] +url = "https://github.com/radityankn/voidwalkers-scandff-gf180mcu/tree/b136150cdcfd55a9568fe14a825c214c3af5dde4/designs/cells/gf180mcu_voidwalkers_sc_sdffrnq_4/sch/gf180mcu_voidwalkers_sc_sdffrnq_4.sch" + +[qualification] +reference = "reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds" + +[presentation] +category = "Logic & memory" +summary = "Stores a clocked bit with scan selection and asynchronous active-low reset." diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..eb4a37d93f39573dbbe31163e45f0ae564c04ecd --- /dev/null +++ b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice @@ -0,0 +1,139 @@ +* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed. +.subckt gf180mcu_voidwalkers_sc_sdffrnq_4 S VDD Q B CLK A RN VSS +*.ipin A +*.ipin B +*.ipin S +*.iopin VDD +*.iopin VSS +*.opin Q +*.ipin RN +*.ipin CLK +x2 VDD VSS Q net1 CLK RN d_flip_flop_r +x1 VDD B VSS net1 A S mux_toplevel_nobuffer +.ends + +* expanding symbol: voidwalkers-scandff-gf180mcu/designs/libs/core_digital/d_flip_flop/d_flip_flop_r.sym # of pins=6 +.subckt d_flip_flop_r VDD VSS Q DATA CLK RN +*.ipin DATA +*.ipin VDD +*.ipin VSS +*.opin Q +*.ipin CLK +*.ipin RN +XM1 net1 DATA VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 PROBE[0] CLK_INV net2 VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM3 PROBE[0] CLK net1 VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM4 net2 DATA VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM5 CLK_INV_2 CLK VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM8 CLK_INV_2 CLK VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM13 net3 PROBE[1] VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM14 PROBE[0] CLK net4 VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM15 PROBE[0] CLK_INV net3 VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM16 net4 PROBE[1] VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM9 net5 PROBE[1] VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM10 PROBE[2] CLK net6 VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM11 PROBE[2] CLK_INV_2 net5 VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM12 net6 PROBE[1] VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM19 net7 PROBE[3] VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM20 PROBE[2] CLK_INV_2 net8 VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' ++ pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM21 PROBE[2] CLK net7 VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM22 net8 PROBE[3] VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM23 QN PROBE[3] VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM24 QN PROBE[3] VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM25 Q QN VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM26 Q QN VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM6 net9 PROBE[0] VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM27 PROBE[1] R net9 VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM28 PROBE[1] PROBE[0] VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM17 net10 PROBE[2] VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM29 PROBE[3] R net10 VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM30 PROBE[3] PROBE[2] VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM7 PROBE[1] R VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM18 PROBE[3] R VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM31 R RN VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM32 R RN VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM33 CLK_INV CLK VDD VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM34 CLK_INV CLK VSS VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: voidwalkers-scandff-gf180mcu/designs/libs/core_digital/mux2x1_transmission_gate/mux_toplevel_nobuffer.sym # ++ of pins=10 +.subckt mux_toplevel_nobuffer vdd INPUT_1 vss out INPUT_2 SELECTOR +*.iopin vdd +*.opin out +*.ipin INPUT_1 +*.ipin INPUT_2 +*.ipin SELECTOR +*.iopin vdd +*.iopin vss +*.iopin vss +*.iopin vdd +*.iopin vss +x2 vdd net1 INPUT_1 out SELECTOR vss mux_tg +x3 vdd SELECTOR INPUT_2 out net1 vss mux_tg +x1 vdd SELECTOR net1 vss mux_inverter +.ends + + +* expanding symbol: voidwalkers-scandff-gf180mcu/designs/libs/core_digital/mux2x1_transmission_gate/mux_tg.sym # of pins=6 +.subckt mux_tg VDD P_GATE IN OUT N_GATE VSS +*.iopin VDD +*.iopin VSS +*.opin OUT +*.ipin IN +*.ipin P_GATE +*.ipin N_GATE +XM1 IN N_GATE OUT VSS nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 IN P_GATE OUT VDD pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends + + +* expanding symbol: voidwalkers-scandff-gf180mcu/designs/libs/core_digital/mux2x1_transmission_gate/mux_inverter.sym # of ++ pins=4 +.subckt mux_inverter vdd in out_inv gnd +*.iopin vdd +*.iopin gnd +*.opin out_inv +*.ipin in +XM1 out_inv in gnd gnd nfet_03v3 L=0.3u W=0.85u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +XM2 out_inv in vdd vdd pfet_03v3 L=0.3u W=1.7u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1 +.ends diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/schematic.svg b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..b2f8bb8ec8c0e18516c7a74e0860b2c42d4d60c8 --- /dev/null +++ b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/schematic.svg @@ -0,0 +1 @@ +scan_dff{"format": "iclayout-schematic", "case_id": "gf180mcuD.voidwalkers-scandff.scan_dff", "netlist_sha256": "659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58", "project_sha256": "026355359b88d5571512ab36e7c5a600600cfa1daa05e82656b2365713aedd61", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/gf180mcuD/voidwalkers-scandff/", "sheets": ["gf180mcu_voidwalkers_sc_sdffrnq_4", "d_flip_flop_r", "mux_toplevel_nobuffer", "mux_tg", "mux_inverter"], "banks": [], "source_netlist": "tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.", "PROBE[n] node names are retained; export verification uses the editor Spectre syntax encoder because its ngspice encoder rejects brackets. No Spectre simulator is required or used."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}gf180mcu_voidwalkers_sc_sdffrnq_4VDDVSSQDATACLKRNvddINPUT_1vssoutINPUT_2SELECTORBASQCLKRNVDDVDDVSSVSSnet1SVDDQBCLKARNVSSscan_dffgf180mcuD · voidwalkers-scandff | W/L in µm · display rounded to 3 significant figures01 Scan select → resettable flip-flopx1mux_toplevel_nobufferx2d_flip_flop_rModels: d_flip_flop_r · mux_toplevel_nobufferd_flip_flop_rnet1DATAVDDnet3PROBE[1]CLKCLK_INVnet2net4VSSPROBE[0]VDDnet9PROBE[0]RVSSPROBE[1]net5PROBE[1]VDDnet7PROBE[3]CLK_INV_2CLKnet6net8VSSPROBE[2]VDDnet10PROBE[2]RVSSPROBE[3]PROBE[3]VDDQVSSQNCLK_INV_2CLK_INVRRNVDDVSSCLKVDDVSSQDATACLKRNd_flip_flop_rgf180mcuD · voidwalkers-scandff | W/L in µm · display rounded to 3 significant figures01 Master sampling / feedbackXM11.7/0.3XM131.7/0.3XM31.7/0.3XM151.7/0.3XM20.85/0.3XM140.85/0.3XM40.85/0.3XM160.85/0.3P bulk → VDDN bulk → VSS02 Master reset latchXM61.7/0.3XM271.7/0.3XM280.85/0.3XM70.85/0.3P bulk → VDDN bulk → VSS03 Slave sampling / feedbackXM91.7/0.3XM191.7/0.3XM111.7/0.3XM211.7/0.3XM100.85/0.3XM200.85/0.3XM120.85/0.3XM220.85/0.3P bulk → VDDN bulk → VSS04 Slave reset latchXM171.7/0.3XM291.7/0.3XM300.85/0.3XM180.85/0.3P bulk → VDDN bulk → VSS05 Output buffersXM231.7/0.3XM251.7/0.3XM240.85/0.3XM260.85/0.3P bulk → VDDN bulk → VSS06 Clock and reset polarityXM51.7/0.3XM331.7/0.3XM311.7/0.3XM80.85/0.3XM340.85/0.3XM320.85/0.3P bulk → VDDN bulk → VSSModels: pfet_03v3 · nfet_03v3mux_toplevel_nobufferVDDP_GATEINOUTN_GATEVSSVDDP_GATEINOUTN_GATEVSSvddinout_invgndnet1vssINPUT_1INPUT_2outvddvddvddSELECTORnet1net1vddINPUT_1vssoutINPUT_2SELECTORmux_toplevel_nobuffergf180mcuD · voidwalkers-scandff | W/L in µm · display rounded to 3 significant figures01 Scan-data selectionx1mux_inverterx2mux_tgx3mux_tgModels: mux_tg · mux_invertermux_tgP_GATEN_GATEINOUTVDDP_GATEINOUTN_GATEVSSmux_tggf180mcuD · voidwalkers-scandff | W/L in µm · display rounded to 3 significant figures01 Transmission gateXM21.7/0.3XM10.85/0.3P bulk → VDDN bulk → VSSModels: nfet_03v3 · pfet_03v3mux_invertervddgndout_invinvddinout_invgndmux_invertergf180mcuD · voidwalkers-scandff | W/L in µm · display rounded to 3 significant figures01 Select inverterXM21.7/0.3XM10.85/0.3P bulk → vddN bulk → gndModels: nfet_03v3 · pfet_03v3 \ No newline at end of file diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/testbench.spice b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..98c658244bdcf24bca299d2a40e1ed27c4b58a7f --- /dev/null +++ b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/testbench.spice @@ -0,0 +1,40 @@ +* GF180MCU nominal characterization: 3.3 V, 27 C, typical models. +.include "support/models.spice" +.include "dut.spice" +.include "parameters.spice" +.temp 27 +VDD vdd 0 3.3 +VCLK clk 0 PULSE(0 3.3 10n .1n .1n 10n 20n) +VRN rn 0 PWL(0 0 5n 0 5.1n 3.3 85n 3.3 85.1n 0 95n 0 95.1n 3.3) +VS s 0 PWL(0 0 40n 0 40.1n 3.3 80n 3.3 80.1n 0) +VA a 0 PWL(0 0 20n 0 20.1n 3.3 60n 3.3 60.1n 0 100n 0 100.1n 3.3 120n 3.3 120.1n 0) +VB b 0 PWL(0 0 60n 0 60.1n 3.3) +CLOAD q 0 50f +XDUT s vdd q b clk a rn 0 gf180mcu_voidwalkers_sc_sdffrnq_4 +.control +tran .01n 140n +meas tran low19 find v(q) at=19n +meas tran high39 find v(q) at=39n +meas tran low59 find v(q) at=59n +meas tran high79 find v(q) at=79n +meas tran reset89 find v(q) at=89n +meas tran reset99 find v(q) at=99n +meas tran high119 find v(q) at=119n +meas tran low139 find v(q) at=139n +* Measure effective CLK->Q arcs for functional and scan data, plus asynchronous reset. +meas tran delay_data_rise trig v(clk) val=1.65 rise=1 td=100n targ v(q) val=1.65 rise=1 td=100n +meas tran slew_data_rise trig v(q) val=0.66 rise=1 td=100n targ v(q) val=2.64 rise=1 td=100n +meas tran delay_data_fall trig v(clk) val=1.65 rise=1 td=120n targ v(q) val=1.65 fall=1 td=120n +meas tran slew_data_fall trig v(q) val=2.64 fall=1 td=120n targ v(q) val=0.66 fall=1 td=120n +meas tran delay_scan_rise trig v(clk) val=1.65 rise=1 td=60n targ v(q) val=1.65 rise=1 td=60n +meas tran slew_scan_rise trig v(q) val=0.66 rise=1 td=60n targ v(q) val=2.64 rise=1 td=60n +meas tran delay_scan_fall trig v(clk) val=1.65 rise=1 td=40n targ v(q) val=1.65 fall=1 td=40n +meas tran slew_scan_fall trig v(q) val=2.64 fall=1 td=40n targ v(q) val=0.66 fall=1 td=40n +meas tran delay_reset_fall trig v(rn) val=1.65 fall=1 td=80n targ v(q) val=1.65 fall=1 td=80n +meas tran slew_reset_fall trig v(q) val=2.64 fall=1 td=80n targ v(q) val=0.66 fall=1 td=80n +let pwr=-3.3*i(vdd) +meas tran power_w avg pwr from=20n to=140n +write waveform.raw +quit +.endc +.end diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..d90ac144c3f8c2775f805e86cd75b08f2c21b110 --- /dev/null +++ b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md @@ -0,0 +1,116 @@ +# Scan D Flip-Flop with Active-Low Reset Layout Task + +## Objective + +Implement `gf180mcu_voidwalkers_sc_sdffrnq_4` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Functional data and scan selection, rising-edge storage, asynchronous active-low reset, and 50 MHz operation with 50 fF load. + +## Inputs and Interface + +The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration. + +Ordered subcircuit and GDS interface: `S, VDD, Q, B, CLK, A, RN, VSS`. +VDD/VSS: supply/return; A: functional data; B: scan data; S: select (0=A, 1=B); CLK: rising-edge clock; RN: active-low asynchronous reset; Q: stored output. + +Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together. + +## Operating Conditions + +Use 3.3 V and 27 C, a 50 fF Q load and the same 50 MHz clock throughout (first rise 10 ns, rise/fall 0.1 ns, high time 10 ns). Select A initially; select B at 40.1 ns; return to A at 80.1 ns. A rises at 20.1 ns, falls at 60.1 ns, rises at 100.1 ns and falls at 120.1 ns. B rises at 60.1 ns. RN starts low, releases at 5.1 ns, asserts at 85.1 ns and releases at 95.1 ns. All data/reset transitions take 0.1 ns, as specified in the testbench. Simulate through 140 ns. + +Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope. + +## Physical Requirements + +Submit a nonempty GDS with top cell `gf180mcu_voidwalkers_sc_sdffrnq_4` and at most 10485760 bytes. Its functional bounding box must not exceed 80 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is: + +`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`. + +Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block. + +LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success. + + +The standard-cell functional frame has fixed height 6.35 um and width on a 0.005 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply. + +- `VDD`: centre y = 6 um, thickness at least 0.23 um, from left + 0 um to right − 0 um. +- `VSS`: centre y = 0.35 um, thickness at least 0.23 um, from left + 0 um to right − 0 um. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | +| --- | --- | --- | --- | --- | --- | +| `low` | Q at 19, 59, 89, 99 and 139 ns; the 89 ns sample checks asynchronous reset before the next rising clock. | V | functional check | −∞ … 0.33 | — | +| `high` | Q at 39, 79 and 119 ns, exercising functional and scan data. | V | functional check | 2.97 … +∞ | — | +| `propagation_delay` | Worst paired quality over: delay_data_rise, delay_data_fall, delay_scan_rise, delay_scan_fall, delay_reset_fall. | s | minimize / ratio | 0 … +∞ | — | +| `output_transition` | Worst paired quality over: slew_data_rise, slew_data_fall, slew_scan_rise, slew_scan_fall, slew_reset_fall. | s | minimize / ratio | 0 … +∞ | — | +| `supply` | Average VDD power over 20–140 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 | + +Area reference: **175.5775 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 27.65 by 6.35 um = 175.577 um2. Reference SHA-256: ffd6654d5505bf6340acbb3061ad81fab36951badda45b3bd3a8448be0fa00ab. This footprint includes the maintained explicit taps and routing. + +The capability coefficient remains **5**; it is independent of +the reference-relative task score. + +### Standard-cell design guidance + +Plan the device rows, power rails and signal access before routing. Represent +pull-up and pull-down connectivity as transistor-edge graphs; explore compatible +Euler trails and alternative orderings to share diffusion and reduce breaks. +Choose among legal orderings using routing length, parasitic loading and signal +access, rather than diffusion sharing alone. Preserve the fixed netlist sizes, +models and connectivity; size optimization is outside this task. + +Use the task's declared row height, grid and rail geometry. Keep local routes +compact, leave signal pins accessible, and avoid consuming extra routing layers +without benefit. Check DRC and named-port LVS, then extract the candidate and +compare both transition directions and power with the source simulation. Iterate +on measured parasitic effects rather than visual compactness alone. These are +optional techniques, not a mandated algorithm or reference placement. + +Adapted from Xu et al., *Standard Cell Library Design and Optimization Methodology +for ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing, +track counts and process-specific dimensions do not apply to this task. + + +### Score weights + +Scan flip-flop: clock-to-output delay 51%; output transition 17%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.15 | +| `propagation_delay` | 0.510000000000 | +| `output_transition` | 0.170000000000 | +| `supply` | 0.170000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task. + +Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck. diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds new file mode 100644 index 0000000000000000000000000000000000000000..e3ce7fc8196df6636f74a45079fc51a6831dece7 Binary files /dev/null and b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds differ diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE b/tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..261eeb9e9f8b2b4b0d119366dda99c6fd7d35c64 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..85a0a3f544ab3072d55f316162fd8c809e3aa571 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml @@ -0,0 +1,1166 @@ +in_core = false +kind = "layout_case" +id = "module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator" +title = "IHP AnalogAcademy comparator" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "6555f7c6a8b7a3330ccb93621458f99753c3ceadd7acab40fb9610bd64edf3c1" + +[[assets]] +path = "reference/DIFF_COMPARATOR.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "9f2548f157ccfc4448820dbd71f26c60d9a0525043e86d8928ea448cf56d7279" + +[task] +hours = 3 +coefficient = 6 +kind = "netlist_to_gds" +family = "ihp_sg13g2_analog_comparator" +environment = "ihp-sg13g2-comparator-rc-tt" + +[task.inputs.description] +path = "problem.md" +sha256 = "c15d95f6e71753ce74b456e4f0b8ff70ab3ebd15fb6b15f7bfe261f8358f653a" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +sha256 = "0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c" +format = "spice" +subcircuit = "DIFF_COMPARATOR" + +[task.inputs.simulation] +path = "materials/circuit.spice" +sha256 = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221" +format = "spice" + +[task.inputs.performance] +path = "materials/testbench.spice" +sha256 = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e" +format = "spice" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 3, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 19, + 0, + ], + [ + 24, + 0, + ], + [ + 26, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], + [ + 30, + 0, + ], + [ + 31, + 0, + ], + [ + 32, + 0, + ], + [ + 33, + 0, + ], + [ + 35, + 0, + ], + [ + 36, + 0, + ], + [ + 40, + 0, + ], + [ + 44, + 0, + ], + [ + 46, + 0, + ], + [ + 49, + 0, + ], + [ + 50, + 0, + ], + [ + 51, + 0, + ], + [ + 52, + 0, + ], + [ + 53, + 0, + ], + [ + 55, + 0, + ], + [ + 58, + 0, + ], + [ + 66, + 0, + ], + [ + 67, + 0, + ], + [ + 90, + 0, + ], + [ + 101, + 0, + ], + [ + 111, + 0, + ], + [ + 125, + 0, + ], + [ + 126, + 0, + ], + [ + 128, + 0, + ], + [ + 129, + 0, + ], + [ + 133, + 0, + ], + [ + 134, + 0, + ], + [ + 139, + 0, + ], + [ + 152, + 0, + ], +] +max_width_um = 45 +max_height_um = 45 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "DIFF_COMPARATOR" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 502.96 +rationale = "Clocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +worst_delay = 0.710526315789 +supply_power = 0.189473684211 + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +top_cell = "DIFF_COMPARATOR" +ports = [ + "vdd", + "gnd", + "V+", + "V-", + "clk", + "out-", + "out+", + "vbias", +] + +[[task.evaluation.jobs]] +id = "negative_5mv" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +input_difference = -0.005 +polarity = -1 + +[task.evaluation.jobs.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.jobs.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[[task.evaluation.jobs]] +id = "negative_3mv" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +input_difference = -0.003 +polarity = -1 + +[task.evaluation.jobs.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.jobs.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[[task.evaluation.jobs]] +id = "positive_3mv" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +input_difference = 0.003 +polarity = 1 + +[task.evaluation.jobs.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.jobs.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[[task.evaluation.jobs]] +id = "positive_5mv" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +waveform = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +input_difference = 0.005 +polarity = 1 + +[task.evaluation.jobs.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.jobs.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "worst_delay" +category = "performance" +observations = [ + "negative_5mv:delay_c02", + "negative_5mv:delay_c03", + "negative_5mv:delay_c04", + "negative_5mv:delay_c05", + "negative_5mv:delay_c06", + "negative_5mv:delay_c07", + "negative_5mv:delay_c08", + "negative_5mv:delay_c09", + "negative_3mv:delay_c02", + "negative_3mv:delay_c03", + "negative_3mv:delay_c04", + "negative_3mv:delay_c05", + "negative_3mv:delay_c06", + "negative_3mv:delay_c07", + "negative_3mv:delay_c08", + "negative_3mv:delay_c09", + "positive_3mv:delay_c02", + "positive_3mv:delay_c03", + "positive_3mv:delay_c04", + "positive_3mv:delay_c05", + "positive_3mv:delay_c06", + "positive_3mv:delay_c07", + "positive_3mv:delay_c08", + "positive_3mv:delay_c09", + "positive_5mv:delay_c02", + "positive_5mv:delay_c03", + "positive_5mv:delay_c04", + "positive_5mv:delay_c05", + "positive_5mv:delay_c06", + "positive_5mv:delay_c07", + "positive_5mv:delay_c08", + "positive_5mv:delay_c09", +] +unit = "s" +direction = "minimize" +aggregation = "max" +dimension = "response" +baseline = [ + "source_negative_5mv:delay_c02", + "source_negative_5mv:delay_c03", + "source_negative_5mv:delay_c04", + "source_negative_5mv:delay_c05", + "source_negative_5mv:delay_c06", + "source_negative_5mv:delay_c07", + "source_negative_5mv:delay_c08", + "source_negative_5mv:delay_c09", + "source_negative_3mv:delay_c02", + "source_negative_3mv:delay_c03", + "source_negative_3mv:delay_c04", + "source_negative_3mv:delay_c05", + "source_negative_3mv:delay_c06", + "source_negative_3mv:delay_c07", + "source_negative_3mv:delay_c08", + "source_negative_3mv:delay_c09", + "source_positive_3mv:delay_c02", + "source_positive_3mv:delay_c03", + "source_positive_3mv:delay_c04", + "source_positive_3mv:delay_c05", + "source_positive_3mv:delay_c06", + "source_positive_3mv:delay_c07", + "source_positive_3mv:delay_c08", + "source_positive_3mv:delay_c09", + "source_positive_5mv:delay_c02", + "source_positive_5mv:delay_c03", + "source_positive_5mv:delay_c04", + "source_positive_5mv:delay_c05", + "source_positive_5mv:delay_c06", + "source_positive_5mv:delay_c07", + "source_positive_5mv:delay_c08", + "source_positive_5mv:delay_c09", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "decision_margin" +category = "performance" +observations = [ + "negative_5mv:margin_c02", + "negative_5mv:margin_c03", + "negative_5mv:margin_c04", + "negative_5mv:margin_c05", + "negative_5mv:margin_c06", + "negative_5mv:margin_c07", + "negative_5mv:margin_c08", + "negative_5mv:margin_c09", + "negative_3mv:margin_c02", + "negative_3mv:margin_c03", + "negative_3mv:margin_c04", + "negative_3mv:margin_c05", + "negative_3mv:margin_c06", + "negative_3mv:margin_c07", + "negative_3mv:margin_c08", + "negative_3mv:margin_c09", + "positive_3mv:margin_c02", + "positive_3mv:margin_c03", + "positive_3mv:margin_c04", + "positive_3mv:margin_c05", + "positive_3mv:margin_c06", + "positive_3mv:margin_c07", + "positive_3mv:margin_c08", + "positive_3mv:margin_c09", + "positive_5mv:margin_c02", + "positive_5mv:margin_c03", + "positive_5mv:margin_c04", + "positive_5mv:margin_c05", + "positive_5mv:margin_c06", + "positive_5mv:margin_c07", + "positive_5mv:margin_c08", + "positive_5mv:margin_c09", +] +unit = "V" +direction = "maximize" +aggregation = "min" +lower = 1.0 + +[[task.evaluation.metrics]] +id = "supply_power" +category = "performance" +observations = [ + "negative_5mv:supply_power", + "negative_3mv:supply_power", + "positive_3mv:supply_power", + "positive_5mv:supply_power", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_negative_5mv:supply_power", + "source_negative_3mv:supply_power", + "source_positive_3mv:supply_power", + "source_positive_5mv:supply_power", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.pre_layout] +source_report_sha256 = "3a8ba863ecaddad4b7a01a0ac94e32a8770b03b0d7aeda98f3fcf1f88c2e56f5" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"30c5b5b710850a636e75d962f27982d72b8b68307dd77a34df044e2a3b07d34b\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_negative_5mv] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.parameters.values] +input_difference = -0.005 +polarity = -1 + +[task.evaluation.pre_layout.jobs.source_negative_5mv.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.input_sha256] +deck = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e" +dut = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c02] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c03] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c04] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c05] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c06] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c07] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c08] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.delay_c09] +value = 1.779459e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c02] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c03] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c04] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c05] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c06] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c07] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c08] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.margin_c09] +value = 1.199985 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_5mv.measurements.supply_power] +value = 5.722953e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_negative_3mv] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.parameters.values] +input_difference = -0.003 +polarity = -1 + +[task.evaluation.pre_layout.jobs.source_negative_3mv.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.input_sha256] +deck = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e" +dut = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c02] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c03] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c04] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c05] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c06] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c07] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c08] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.delay_c09] +value = 1.860315e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c02] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c03] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c04] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c05] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c06] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c07] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c08] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.margin_c09] +value = 1.199975 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_negative_3mv.measurements.supply_power] +value = 5.815247e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_positive_3mv] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.parameters.values] +input_difference = 0.003 +polarity = 1 + +[task.evaluation.pre_layout.jobs.source_positive_3mv.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.input_sha256] +deck = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e" +dut = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c02] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c03] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c04] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c05] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c06] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c07] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c08] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.delay_c09] +value = 1.871706e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c02] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c03] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c04] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c05] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c06] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c07] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c08] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.margin_c09] +value = 1.199971 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_3mv.measurements.supply_power] +value = 5.782437e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_positive_5mv] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.outputs] +waveform = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.parameters.values] +input_difference = 0.005 +polarity = 1 + +[task.evaluation.pre_layout.jobs.source_positive_5mv.parameters.exports] +waveform = "comparator.raw" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.parameters.measurements] +supply_power = "W" +delay_c02 = "s" +margin_c02 = "V" +delay_c03 = "s" +margin_c03 = "V" +delay_c04 = "s" +margin_c04 = "V" +delay_c05 = "s" +margin_c05 = "V" +delay_c06 = "s" +margin_c06 = "V" +delay_c07 = "s" +margin_c07 = "V" +delay_c08 = "s" +margin_c08 = "V" +delay_c09 = "s" +margin_c09 = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.input_sha256] +deck = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e" +dut = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c02] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c03] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c04] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c05] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c06] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c07] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c08] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.delay_c09] +value = 1.797676e-09 +unit = "s" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c02] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c03] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c04] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c05] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c06] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c07] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c08] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.margin_c09] +value = 1.199982 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_positive_5mv.measurements.supply_power] +value = 5.667991e-05 +unit = "W" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +support = "build/support/comparator-klayout" +profile = "drc-upstream.json" +timeout_seconds = 600 + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +support = "build/support/comparator-klayout" +profile = "lvs-upstream.json" +timeout_seconds = 600 + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 120 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/comparator-magic" +technology = "magic/ihp-sg13g2.tech" +tech_name = "ihp-sg13g2" +style = "ngspice()" +capacitance_threshold_ff = 0 +timeout_seconds = 600 + +[toolchain.backends.simulation] +type = "ngspice-docker" + +[toolchain.backends.simulation.support_profiles] +support = "analog-models" + +[toolchain.backends.simulation.settings] +image = "iclayout-bench-tools:local" +support = "build/support/comparator-analog-models" +timeout_seconds = 600 + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "simulation" + +[qualification] +reference = "reference/DIFF_COMPARATOR.gds" + +[origin] +url = "https://github.com/IHP-GmbH/IHP-AnalogAcademy/tree/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator" + +[presentation] +category = "Mixed-signal" +summary = "Compares two input voltages using a clocked regenerative decision." diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..e47b5bd11f5a434b502680b655c6c667b04ccdc1 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl @@ -0,0 +1,19 @@ +** sch_path: /source/DIFF_COMPARATOR.sch +.subckt DIFF_COMPARATOR vdd gnd v+ v- clk out- out+ vbias +*.PININFO vdd:B gnd:B v+:I v-:I clk:I out-:O out+:O vbias:I +MM2 net3 v+ net1 well sg13_lv_pmos w=8u l=200n ng=2 m=4 +MM1 net2 v- net1 well sg13_lv_pmos w=8u l=200n ng=2 m=4 +MM4 out- net2 vdd well sg13_lv_pmos w=8u l=0.200u ng=2 m=1 +MM5 out+ net3 vdd well sg13_lv_pmos w=8u l=0.200u ng=2 m=1 +MM11 gnd net3 out+ sub sg13_lv_nmos w=4.0u l=0.200u ng=2 m=1 +MM12 gnd net2 out- sub sg13_lv_nmos w=4.0u l=0.200u ng=2 m=1 +MM6 gnd net2 net3 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 +MM10 gnd clk net3 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 +MM7 gnd clk net2 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 +MM8 gnd net3 net2 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 +MM3 gnd gnd gnd sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=4 +MM13 net1 clk net4 well sg13_lv_pmos w=18u l=0.3u ng=4 m=1 +MM9 net4 vbias vdd well sg13_lv_pmos w=18u l=0.3u ng=4 m=1 +RR1 vdd well ntap1 A=15.376e-12 P=99.2e-6 +RR2 gnd sub ptap1 A=11.376e-12 P=75.84e-6 +.ends diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.spice b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..fd91617f08e6f6f2b51a0acb5f158547bb2f6c07 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.spice @@ -0,0 +1,19 @@ +** sch_path: /workspace/source/DIFF_COMPARATOR.sch +.subckt DIFF_COMPARATOR vdd gnd v+ v- clk out- out+ vbias +*.PININFO vdd:B gnd:B v+:I v-:I clk:I out-:O out+:O vbias:I +XM2 net3 v+ net1 well sg13_lv_pmos w=8u l=200n ng=2 m=4 mm_ok=1 +XM1 net2 v- net1 well sg13_lv_pmos w=8u l=200n ng=2 m=4 mm_ok=1 +XM4 out- net2 vdd well sg13_lv_pmos w=8u l=0.200u ng=2 m=1 mm_ok=1 +XM5 out+ net3 vdd well sg13_lv_pmos w=8u l=0.200u ng=2 m=1 mm_ok=1 +XM11 gnd net3 out+ sub sg13_lv_nmos w=4.0u l=0.200u ng=2 m=1 mm_ok=1 +XM12 gnd net2 out- sub sg13_lv_nmos w=4.0u l=0.200u ng=2 m=1 mm_ok=1 +XM6 gnd net2 net3 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 mm_ok=1 +XM10 gnd clk net3 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 mm_ok=1 +XM7 gnd clk net2 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 mm_ok=1 +XM8 gnd net3 net2 sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=1 mm_ok=1 +XM3 gnd gnd gnd sub sg13_lv_nmos w=4.0u l=0.200u ng=1 m=4 mm_ok=1 +XM13 net1 clk net4 well sg13_lv_pmos w=18u l=0.3u ng=4 m=1 mm_ok=1 +XM9 net4 vbias vdd well sg13_lv_pmos w=18u l=0.3u ng=4 m=1 mm_ok=1 +XR1 vdd well ntap1 a=15.376e-12 p=99.2e-6 r=8.553275 +XR2 gnd sub ptap1 a=11.376e-12 p=75.84e-6 r=11.23647 +.ends diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/schematic.svg b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..64a01b3bd7a13f946e4def79f38f6fbbc57ef241 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/schematic.svg @@ -0,0 +1 @@ +comparator{"format": "iclayout-schematic", "case_id": "module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator", "netlist_sha256": "0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c", "project_sha256": "21dc89819dfc2d5117385f13f03f48c9854bdb20e78655b5d6ca04019c8a6784", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/ihp-sg13g2/IHP-AnalogAcademy/", "sheets": ["DIFF_COMPARATOR"], "banks": [], "source_netlist": "tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}DIFF_COMPARATORvbiasvddv-v+net4net1clknet2net3gndout-net2vddout+net3gndgndvddwellgndsubvddgndv+v-clkout-out+vbiascomparatorihp-sg13g2 · IHP-AnalogAcademy | W/L in µm · display rounded to 3 significant figures01 Clocked differential inputMM918/0.3MM1318/0.3MM18/0.2 ×4MM28/0.2 ×4MM84/0.2MM64/0.2MM74/0.2MM104/0.2P bulk → wellN bulk → sub02 Output invertersMM48/0.2MM58/0.2MM124/0.2MM114/0.2P bulk → wellN bulk → sub03 DummyMM34/0.2 ×4N bulk → sub04 Substrate contacts / repeated banksRR1A=15.4 µm²RR2A=11.4 µm²Models: sg13_lv_pmos · sg13_lv_nmos · ntap1 · ptap1 \ No newline at end of file diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/testbench.spice b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..0aba6412ed6c3be1b8a8f8f6bbae4efdb508612e --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/testbench.spice @@ -0,0 +1,39 @@ +* Comparator accepted nominal performance test; see problem.md for scoring rules. +.include dut.spice +.include parameters.spice +.lib /workspace/support/models/cornerMOSlv.lib mos_tt +.lib /workspace/support/models/cornerRES.lib res_typ +.temp 27 +VDD VDD 0 DC 1.2 +VBIAS VBIAS 0 DC 0.6 +VCLK CLK 0 PULSE(0 1.2 0 500p 500p 5n 10n) +VINP VINP 0 DC {0.6+input_difference} +CINP VINP 0 6.4p +CBIAS VBIAS 0 6.4p +COUTP OUTP 0 50f +COUTM OUTM 0 50f +XDUT VDD 0 VINP VBIAS CLK OUTM OUTP VBIAS DIFF_COMPARATOR +.tran 500p 100n 0 10p +.measure tran supply_power AVG par('-v(VDD)*i(VDD)') FROM=20n TO=100n +.measure tran delay_c02 TRIG v(CLK) VAL=0.6 FALL=1 TD=20n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=25.75n +.measure tran margin_c02 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=28.75n TO=29.75n +.measure tran delay_c03 TRIG v(CLK) VAL=0.6 FALL=1 TD=30n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=35.75n +.measure tran margin_c03 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=38.75n TO=39.75n +.measure tran delay_c04 TRIG v(CLK) VAL=0.6 FALL=1 TD=40n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=45.75n +.measure tran margin_c04 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=48.75n TO=49.75n +.measure tran delay_c05 TRIG v(CLK) VAL=0.6 FALL=1 TD=50n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=55.75n +.measure tran margin_c05 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=58.75n TO=59.75n +.measure tran delay_c06 TRIG v(CLK) VAL=0.6 FALL=1 TD=60n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=65.75n +.measure tran margin_c06 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=68.75n TO=69.75n +.measure tran delay_c07 TRIG v(CLK) VAL=0.6 FALL=1 TD=70n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=75.75n +.measure tran margin_c07 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=78.75n TO=79.75n +.measure tran delay_c08 TRIG v(CLK) VAL=0.6 FALL=1 TD=80n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=85.75n +.measure tran margin_c08 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=88.75n TO=89.75n +.measure tran delay_c09 TRIG v(CLK) VAL=0.6 FALL=1 TD=90n TARG par('{polarity}*(v(OUTP)-v(OUTM))') VAL=1 RISE=1 TD=95.75n +.measure tran margin_c09 MIN par('{polarity}*(v(OUTP)-v(OUTM))') FROM=98.75n TO=99.75n +.control +run +write comparator.raw time v(VINP) v(VBIAS) v(CLK) v(OUTP) v(OUTM) i(VDD) +quit +.endc +.end diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..9bb35f518dd65b3c783c9461450e15b29db62586 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md @@ -0,0 +1,170 @@ +# Dynamic Comparator Layout Task + +## Objective + +Create an IHP SG13G2 layout for the `DIFF_COMPARATOR` dynamic differential +comparator. Preserve the topology, device parameters, explicit well and +substrate connections, and eight-port interface in the authoritative materials. +The submitted GDS must pass the physical checks, fit the functional outline, and +meet the clocked decision requirements after candidate-derived RC extraction. + +## Inputs and Interface + +In addition to this problem, the solver receives the following declared +materials. The structured constraints +and evaluation plan are also available at runtime through `/protocol/task.json`. + +| Input | Purpose | +|---|---| +| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `DIFF_COMPARATOR` | +| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist | +| [materials/testbench.spice](materials/testbench.spice) | Clock stimulus and public measurement expressions | + +Use one distinct external conductor for each ordered port. Internal nodes must +not be exposed as ports. + +| Port | Function | +|---|---| +| `vdd` | Positive supply | +| `gnd` | Ground and substrate reference | +| `V+`, `V-` | Differential input pair | +| `clk` | Dynamic latch clock | +| `out-`, `out+` | Complementary decision outputs | +| `vbias` | Bias input | + +The extraction port order is `vdd gnd V+ V- clk out- out+ vbias`. + +## Operating Conditions + +The supplied deck evaluates the pre-layout and candidate-derived netlists with +the same model and stimulus definitions. + +| Parameter | Setting | +|---|---| +| Process corner | `mos_tt`, `res_typ` | +| Temperature | 27 °C | +| Supply | `VDD = 1.2 V` | +| Input reference and bias | `V- = vbias = 0.6 V` | +| Differential input | `V+ − V- = −5, −3, +3, +5 mV`, tested separately | +| Clock | 100 MHz, 1.2 V swing, 500 ps rise and fall, 5 ns high time | +| Output load | 50 fF on each output | +| Transient analysis | 100 ns duration, 10 ps maximum time step | +| Measurements | Skip the first two cycles and evaluate the next eight cycles | + +The testbench excludes power consumed by the external clock, input, and bias +drivers from the reported supply-power measurement. + +## Physical Requirements + +Submit a readable GDSII file with a nonempty `DIFF_COMPARATOR` top cell. The file +must be at most 10 MiB (10,485,760 bytes) and must contain the complete hierarchy +needed by the target cell. + +The evaluator runs the pinned SG13G2 main and additional maximal DRC rules in +deep mode, with density and antenna checks disabled and no waivers. LVS uses the +current `lvs-upstream.json` profile and strict named-port matching against +`materials/circuit.cdl`; port names are matched case-insensitively, while every +declared port must remain on its own conductor with the declared connectivity. + +The functional outline is the recursive bounding box of polygons on these +SG13G2 datatype-0 layers, including child cells and the complete routing stack: + +`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`. + +The maximum width is 45 µm and the maximum height is +45 µm, measured along the submitted X and Y axes. +Functional area is width multiplied by height. Text, annotation and filler +layers are excluded. The area score below uses this same functional footprint. + +After the physical and geometry gates pass, Magic extracts distributed wire +resistance and layout capacitance from the submitted GDS. Device merging and +resistor-network simplification are disabled. The compact-device extraction +boundary represents MOS bodies at ideal model rails; explicit taps remain part +of physical LVS but are not emitted as extracted tap elements. Substrate sheet +and tap resistance as extracted quantities, body coupling, and noise are outside +the declared scope. The source and post-layout runs use the same nominal +stimuli and models; a finite-source-tap versus ideal-body calibration bounds this +extraction choice. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +Measurement definitions below use the supplied SPICE node/source names. +`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered +power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs` +denote magnitude, and `cph` is continuous phase in radians. `find`, `when`, +`from/to`, and `rise/fall` retain the deck's interpolation, window and +crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/ +milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` +mean the stated window average, extrema and sampled derivative. All +declared conditions are measured separately and paired with the same +source condition; a group uses its worst paired quality. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension | +| --- | --- | --- | --- | --- | --- | --- | +| `worst_delay` | Clock falling through 0.6 V to polarity-correct output difference reaching 1 V in cycles 2–9 (trigger delays 20–90 ns; target search starts 5.75 ns later). Every cycle and input condition is paired; the worst quality is scored. | s | minimize / ratio | 0 … +∞ | — | response | +| `decision_margin` | Minimum polarity*(V(OUTP)-V(OUTM)) in each 1 ns decision window, 28.75–29.75 ns through 98.75–99.75 ns; all eight cycles and four signed input conditions must pass. | V | functional check | 1.0 … +∞ | — | functional check | +| `supply_power` | Mean delivered VDD power, -V(VDD)*I(VDD), over 20–100 ns, independently for each signed input condition. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply | + +Area reference: **502.96 um2**. 24 expanded device instances; sum of device/contact envelopes 306.3377 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **6**; it is independent of +the reference-relative task score. + + +### Score weights + +Clocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `worst_delay` | 0.710526315789 | +| `supply_power` | 0.189473684211 | + +## Tools and Submission + +Solve budget: **3 hours**. + +The runtime environment and support resources are declared in +`/protocol/resources.json` and `/protocol/harness.json`; the working directory is +`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic +performs RC extraction; ngspice runs the supplied deck with the reviewed SG13G2 +models. The evaluator provides the tool and PDK resources named by the case +toolchain. + +For pre-layout simulation, use `materials/circuit.spice` as `dut.spice` +beside the supplied testbench and use the per-job values exposed in +`/protocol/task.json`. For the submitted layout, the evaluator supplies the +netlist produced by candidate-derived RC extraction. If the harness declares +`process-feedback`, the optional command is +`python -I /protocol/process_check.py`; the final evaluation remains independent. + +Write the result to `/workspace/output/final.gds`, then run +`python -I /protocol/submit.py` and wait for the submission receipt. Solver +netlists, waveforms, and measurements are not accepted as substitutes for the +independent evaluator inputs. diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/reference/DIFF_COMPARATOR.gds b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/reference/DIFF_COMPARATOR.gds new file mode 100644 index 0000000000000000000000000000000000000000..9d9ba28a290b4c4af740b87cd8972b8d6e1f7092 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/reference/DIFF_COMPARATOR.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9f2548f157ccfc4448820dbd71f26c60d9a0525043e86d8928ea448cf56d7279 +size 199746 diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..ca8bce6d7dac9f88ac04281e23e3f5c6ef187239 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml @@ -0,0 +1,594 @@ +in_core = false +kind = "layout_case" +id = "module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA" +title = "IHP AnalogAcademy full_OTA" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "d02c9549e1d7ef313f774236268cc2f80b6efb6d7c764002fe118bd0a651f70f" + +[[assets]] +path = "reference/two_stage_OTA_layout.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "50fa39a6984b6f9d1bc0dda38b379861b981c10b85842cc64d9c0e020f7f15bc" + +[task] +hours = 3 +coefficient = 6 +kind = "netlist_to_gds" +family = "ihp_sg13g2_two_stage_ota" +environment = "ihp-sg13g2-full-ota-rc-tt" + +[task.inputs.description] +path = "problem.md" +sha256 = "ab78fb43d86ffe211d3ae76848a0459a591d1631e1c8d287659b8518a530f1a8" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +sha256 = "b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409" +format = "spice" +subcircuit = "two_stage_OTA_layout" + +[task.inputs.simulation] +path = "materials/circuit.spice" +sha256 = "2c82bb396be0377ae24ee933e5402f87edf9e5da5f2c509774e6ff5c50705a20" +format = "spice" + +[task.inputs.performance] +path = "materials/testbench.spice" +sha256 = "62851f9d9bf6754a4d9b70ca2d9d63a0fd6241ae5e65b289fc5e2e8882469bea" +format = "spice" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 3, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 19, + 0, + ], + [ + 24, + 0, + ], + [ + 26, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], + [ + 30, + 0, + ], + [ + 31, + 0, + ], + [ + 32, + 0, + ], + [ + 33, + 0, + ], + [ + 35, + 0, + ], + [ + 36, + 0, + ], + [ + 40, + 0, + ], + [ + 44, + 0, + ], + [ + 46, + 0, + ], + [ + 49, + 0, + ], + [ + 50, + 0, + ], + [ + 51, + 0, + ], + [ + 52, + 0, + ], + [ + 53, + 0, + ], + [ + 55, + 0, + ], + [ + 58, + 0, + ], + [ + 66, + 0, + ], + [ + 67, + 0, + ], + [ + 90, + 0, + ], + [ + 101, + 0, + ], + [ + 111, + 0, + ], + [ + 125, + 0, + ], + [ + 126, + 0, + ], + [ + 128, + 0, + ], + [ + 129, + 0, + ], + [ + 133, + 0, + ], + [ + 134, + 0, + ], + [ + 139, + 0, + ], + [ + 152, + 0, + ], +] +max_width_um = 80 +max_height_um = 50 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "two_stage_OTA_layout" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 2936.48 +rationale = "Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.1 +low_frequency_gain = 0.27 +unity_gain_bandwidth = 0.225 +phase_margin = 0.225 +output_bias = 0.045 +supply_power = 0.135 + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +top_cell = "two_stage_OTA_layout" +ports = [ + "v-", + "v+", + "vss", + "vdd", + "iout", + "vout", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +ac = "ngspice-raw" +op = "ngspice-raw" + +[task.evaluation.jobs.parameters.exports] +ac = "ota-ac.raw" +op = "ota-op.raw" + +[task.evaluation.jobs.parameters.measurements] +low_frequency_gain = "dB" +unity_gain_bandwidth = "Hz" +phase_margin = "deg" +supply_power = "W" +output_bias = "V" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "low_frequency_gain" +category = "performance" +observations = [ + "nominal:low_frequency_gain", +] +unit = "dB" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:low_frequency_gain", +] +normalization = "db20" + +[[task.evaluation.metrics]] +id = "unity_gain_bandwidth" +category = "performance" +observations = [ + "nominal:unity_gain_bandwidth", +] +unit = "Hz" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:unity_gain_bandwidth", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "phase_margin" +category = "performance" +observations = [ + "nominal:phase_margin", +] +unit = "deg" +direction = "target" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:phase_margin", +] +normalization = "target" +scale = 180 +lower = 0 +upper = 180 + +[[task.evaluation.metrics]] +id = "supply_power" +category = "performance" +observations = [ + "nominal:supply_power", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_nominal:supply_power", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[[task.evaluation.metrics]] +id = "output_bias" +category = "performance" +observations = [ + "nominal:output_bias", +] +unit = "V" +direction = "target" +aggregation = "min" +dimension = "bias" +baseline = [ + "source_nominal:output_bias", +] +normalization = "target" +scale = 1.2 +lower = 0 +upper = 1.2 + +[task.evaluation.pre_layout] +source_report_sha256 = "3f51127da701e18e468482e3f12272f1923ec7764474fe59fa890f3ef0ed8e69" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"46a60326db6f55e6517e1b351825550ad9e1a19b30e7ba8579189923428f2c9c\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +ac = "ngspice-raw" +op = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +ac = "ota-ac.raw" +op = "ota-op.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +low_frequency_gain = "dB" +unity_gain_bandwidth = "Hz" +phase_margin = "deg" +supply_power = "W" +output_bias = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "62851f9d9bf6754a4d9b70ca2d9d63a0fd6241ae5e65b289fc5e2e8882469bea" +dut = "2c82bb396be0377ae24ee933e5402f87edf9e5da5f2c509774e6ff5c50705a20" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.low_frequency_gain] +value = 70.11943 +unit = "dB" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.output_bias] +value = 0.5996295207507 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.phase_margin] +value = 61.2768 +unit = "deg" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply_power] +value = 0.000197040688801 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.unity_gain_bandwidth] +value = 4148602.0 +unit = "Hz" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +support = "build/support/full-ota-klayout-spice" +profile = "drc-upstream.json" +timeout_seconds = 600 + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +support = "build/support/full-ota-klayout-spice" +profile = "lvs-upstream.json" +timeout_seconds = 600 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/full-ota-magic" +technology = "magic/ihp-sg13g2.tech" +tech_name = "ihp-sg13g2" +style = "ngspice()" +capacitance_threshold_ff = 0 +timeout_seconds = 600 + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 120 + +[toolchain.backends.simulation] +type = "ngspice-docker" + +[toolchain.backends.simulation.support_profiles] +support = "analog-models" + +[toolchain.backends.simulation.settings] +image = "iclayout-bench-tools:local" +support = "build/support/full-ota-models" +timeout_seconds = 600 + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "simulation" + +[qualification] +reference = "reference/two_stage_OTA_layout.gds" + +[origin] +url = "https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch" + +[presentation] +category = "Amplifiers & RF" +summary = "Amplifies differential signals with a two-stage CMOS OTA." diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..58c5234c10f9d1aaec309700865386c763fdfa3d --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl @@ -0,0 +1,22 @@ +** sch_path: /source/two_stage_OTA_layout.sch +.subckt two_stage_OTA_layout v- v+ vss vdd iout vout +*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B +MM4 dn4 dn3 vss bulk2 sg13_lv_nmos w=720n l=9.75u ng=1 m=1 +MM3 dn3 dn3 vss bulk2 sg13_lv_nmos w=720n l=9.75u ng=1 m=1 +MM1 dn3 v- dn2 bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM2 dn4 v+ dn2 bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM7 dn2 iout vdd bulk1 sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1 +MM5 vout iout vdd bulk4 sg13_lv_pmos w=75u l=2.08u ng=8 m=1 +MM6 vout dn4 vss bulk2 sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1 +MM9 iout iout vdd bulk4 sg13_lv_pmos w=75u l=2.08u ng=8 m=1 +CC2 dn4 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1 +MM8 dn4 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM10 dn3 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM15 dn2 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM16 dn2 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +RR1 vdd bulk ntap1 A=28.1356e-12 P=181.52e-6 +RR3 vdd bulk1 ntap1 A=6.9626e-12 P=44.92e-6 +RR5 vdd bulk4 ntap1 A=26.815e-12 P=173e-6 +RR2 vss bulk2 ptap1 A=8.559e-12 P=57.06e-6 +RR4 vss bulk2 ptap1 A=30.288e-12 P=201.92e-6 +.ends diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.spice b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.spice new file mode 100644 index 0000000000000000000000000000000000000000..dc04e4053c3506785b42f669a950e1a449b29f28 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.spice @@ -0,0 +1,22 @@ +** sch_path: /workspace/source/two_stage_OTA_layout.sch +.subckt two_stage_OTA_layout v- v+ vss vdd iout vout +*.PININFO v-:B v+:B vss:B vdd:B iout:B vout:B +XM4 dn4 dn3 vss bulk2 sg13_lv_nmos w=720n l=9.75u ng=1 m=1 mm_ok=1 +XM3 dn3 dn3 vss bulk2 sg13_lv_nmos w=720n l=9.75u ng=1 m=1 mm_ok=1 +XM1 dn3 v- dn2 bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 mm_ok=1 +XM2 dn4 v+ dn2 bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 mm_ok=1 +XM7 dn2 iout vdd bulk1 sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1 mm_ok=1 +XM5 vout iout vdd bulk4 sg13_lv_pmos w=75u l=2.08u ng=8 m=1 mm_ok=1 +XM6 vout dn4 vss bulk2 sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1 mm_ok=1 +XM9 iout iout vdd bulk4 sg13_lv_pmos w=75u l=2.08u ng=8 m=1 mm_ok=1 +XC2 dn4 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1 mm_ok=1 +XM8 dn4 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 mm_ok=1 +XM10 dn3 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 mm_ok=1 +XM15 dn2 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 mm_ok=1 +XM16 dn2 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 mm_ok=1 +XR1 vdd bulk ntap1 a=28.1356e-12 p=181.52e-6 r=4.674333 +XR3 vdd bulk1 ntap1 a=6.9626e-12 p=44.92e-6 r=18.8888 +XR5 vdd bulk4 ntap1 a=26.815e-12 p=173e-6 r=4.904537 +XR2 vss bulk2 ptap1 a=8.559e-12 p=57.06e-6 r=14.9347 +XR4 vss bulk2 ptap1 a=30.288e-12 p=201.92e-6 r=4.220354 +.ends diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/schematic.svg b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/schematic.svg new file mode 100644 index 0000000000000000000000000000000000000000..4f76e429e6d0b452299c0110d55f9bdc977bca4a --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/schematic.svg @@ -0,0 +1 @@ +full_OTA{"format": "iclayout-schematic", "case_id": "module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA", "netlist_sha256": "b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409", "project_sha256": "26f35c235ecc11623eb2e424d9cce66540de58982ab21bf4979d485005a4a65a", "authoring_tool": "Analog Canvas", "tool_commit": "cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f", "verification": "Source-to-project terminal, model and parameter comparison; schema parse and netlist export. Physical R/C/Q use explicit external model bindings; original references are shown on the drawing.", "license": "licenses/ihp-sg13g2/IHP-AnalogAcademy/", "sheets": ["two_stage_OTA_layout"], "banks": [], "source_netlist": "tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl", "known_editor_diagnostics": {}, "limitations": ["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."], "presentation": {"revision": 2, "significant_figures": 3, "source_precision": "unchanged", "layout": "Case-specific functional groups and direct local wiring"}}two_stage_OTA_layoutvssvdddn4ioutvoutdn4dn3dn2vddbulkbulk1bulk4vssbulk2vddioutvddv-v+dn4vssdn2dn3v-v+vssvddioutvoutfull_OTAihp-sg13g2 · IHP-AnalogAcademy | W/L in µm · display rounded to 3 significant figures01 Input transconductance stageMM75.3/1.95MM13.64/3.7 ×2MM23.64/3.7 ×2MM30.72/9.75MM40.72/9.75MM7: B → bulk1MM1, MM2: B → bulkN bulk → bulk202 Output stage and Miller compensationMM975/2.08MM575/2.08CC222.3/22.3MM628.8/9.75P bulk → bulk4N bulk → bulk203 Input-pair dummiesMM83.64/3.7 ×2MM103.64/3.7 ×2MM153.64/3.7 ×2MM163.64/3.7 ×2P bulk → bulk04 Substrate contacts / repeated banksRR1A=28.1 µm²RR3A=6.96 µm²RR5A=26.8 µm²RR2A=8.56 µm²RR4A=30.3 µm²Models: sg13_lv_nmos · sg13_lv_pmos · cap_cmim · ntap1 · ptap1 \ No newline at end of file diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/testbench.spice b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/testbench.spice new file mode 100644 index 0000000000000000000000000000000000000000..ed64451d938f472be3830e7688aafac01dd56625 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/testbench.spice @@ -0,0 +1,39 @@ +* Full OTA nominal AC/DC measurements. SPDX-License-Identifier: Apache-2.0 +* Adapted from the IHP AnalogAcademy OTA testbench; explicit measurements added. +* DUT port order: v- v+ vss vdd iout vout. +.lib /workspace/support/models/cornerMOSlv.lib mos_tt +.lib /workspace/support/models/cornerCAP.lib cap_typ +.lib /workspace/support/models/cornerRES.lib res_typ +.include dut.spice +.temp 27 +* Approved numerical conditioning for floating capacitive extraction nodes. +.option rshunt=1e12 +VDD vdd 0 DC 1.2 +VIN vp 0 DC 0.6 AC 1 +IBIAS iout 0 DC 80u +LFEEDBACK vout vm 4G +CFEEDBACK vm 0 4G +CLOAD vout 0 500f +XDUT vm vp 0 vdd iout vout two_stage_OTA_layout +.control +set noaskquit +set numdgt=12 +op +let supply_power = -v(vdd)*i(VDD) +let output_bias = v(vout) +print supply_power output_bias +write ota-op.raw all +ac dec 100 1 10meg +let differential = v(vp)-v(vm) +let transfer = v(vout)/differential +let gain_db = db(transfer) +let phase_deg = 180*cph(transfer)/pi +meas ac low_frequency_gain find gain_db at=1 +meas ac unity_gain_bandwidth when gain_db=0 fall=1 +meas ac phase_at_unity find phase_deg when gain_db=0 fall=1 +let phase_margin = 180+phase_at_unity +print phase_margin +write ota-ac.raw frequency v(vp) v(vm) v(vout) differential transfer gain_db phase_deg +quit +.endc +.end diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md new file mode 100644 index 0000000000000000000000000000000000000000..d721a4dc42a82a5955890b54b2b911241643eb33 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md @@ -0,0 +1,177 @@ +# Two-Stage CMOS OTA Layout Task + +## Objective + +Create an IHP SG13G2 layout for the `two_stage_OTA_layout` two-stage CMOS +operational transconductance amplifier. Preserve the MOS and MIM devices, +dimensions, connectivity, well and substrate connections, and six-port +interface in the authoritative materials. The submitted GDS must pass the +physical checks, fit the functional outline, and meet the nominal DC-bias and +AC-response limits after candidate-derived RC extraction. + +## Inputs and Interface + +In addition to this problem, the solver receives the following declared +materials. The structured constraints +and evaluation plan are also available at runtime through `/protocol/task.json`. + +| Input | Purpose | +|---|---| +| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `two_stage_OTA_layout` | +| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist | +| [materials/testbench.spice](materials/testbench.spice) | Nominal bias, feedback fixture, AC sweep, and measurements | + +Use one external label on each distinct conductor. Internal nodes must not be +declared as external ports. + +| Port | Function | Nominal connection | +|---|---|---| +| `v-` | Inverting input | DC feedback from `vout`; AC feedback fixture return | +| `v+` | Non-inverting input | 0.6 V DC and unit AC excitation | +| `vss` | Ground and substrate supply | 0 V | +| `vdd` | Positive supply | 1.2 V | +| `iout` | Bias-current node | Ideal 80 µA sink to ground | +| `vout` | Single-ended output | 500 fF load to ground | + +The extraction port order is `v- v+ vss vdd iout vout`. + +## Operating Conditions + +The pre-layout and candidate-derived simulations use the supplied deck and the +same nominal model and fixture. + +| Parameter | Setting | +|---|---| +| Process corner | `mos_tt`, `cap_typ`, `res_typ` | +| Temperature | 27 °C | +| Supply | `VDD = 1.2 V`, `VSS = 0 V` | +| Input DC level | `V+ = 0.6 V` | +| Bias and load | 80 µA sink at `iout`; 500 fF from `vout` to ground | +| Feedback fixture | 4 GH inductor from `vout` to `v-`; 4 GF capacitor from `v-` to ground | +| AC sweep | 100 points/decade from 1 Hz through 10 MHz | +| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout | + +The feedback fixture closes the DC loop while opening the AC loop for transfer +measurement. Supply power is `-V(vdd) × I(VDD)` at the operating point and +excludes external input and bias-source power. + +## Physical Requirements + +Submit a readable GDSII file with a nonempty `two_stage_OTA_layout` top cell. The +file must be at most 10 MiB (10,485,760 bytes) and must contain the complete +hierarchy needed by the target cell. + +The evaluator runs the pinned SG13G2 main and additional maximal DRC rules in +deep mode, with density and antenna checks disabled and no waivers. LVS uses the +current `lvs-upstream.json` profile and strict named-port matching against +`materials/circuit.cdl`; every declared port must stay on its own conductor with +the declared connectivity and device parameters. Port names are matched +case-insensitively. + +The functional outline is the recursive bounding box of polygons on these +SG13G2 datatype-0 layers, including child cells and the complete routing stack: + +`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`. + +The maximum width is 80 µm and the maximum height is +50 µm, measured along the submitted X and Y axes. +Functional area is width multiplied by height. Text, annotation and filler +layers are excluded. The area score below uses this same functional footprint. + +After the physical and geometry gates pass, Magic extracts distributed wire +resistance and layout capacitance from the submitted GDS. Device merging and +resistor-network simplification are disabled. The compact-device extraction +boundary represents MOS bodies at ideal model rails; explicit taps remain in the +physical LVS netlist but are not emitted as extracted tap elements. Substrate +sheet and tap resistance as extracted quantities, body coupling, and noise are +outside the declared scope. The finite source tap elements are covered by the +same-condition source calibration and are not treated as additional post-layout +requirements. + +## Electrical Requirements and Scoring + +Physical checks and declared functional bounds remain mandatory. Quality has no +fixed allowed-degradation threshold. Each `source_*` job simulates the declared +source circuit with exactly the same testbench, model resources, parameters, +load and measurement window as its paired extracted-candidate job. A source +observation is the 100-point electrical baseline; it is independent of the +submitted GDS. All individual pairs are retained in the evaluation report. + +For a post-layout observation x and its source observation b: + +- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared, + use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements; + s is a normalization floor, not an allowed degradation or pass threshold. +- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize. +- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and + zero-valued operating points are never divided directly. + +Scoring uses `layout`. A metric uses its worst paired quality q. The score is +S = 100 * product(q_i ** w_i), including area quality +q_area = area_reference / candidate_functional_area. The weights below sum to +one. Dimensions describe measurements but do not determine their weights. +Physical or functional rejection scores zero; missing or invalid measurements +produce an unknown score, including measurements with zero weight. +Source-equivalent performance at the area reference scores 100; improvements +can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit. + +Measurement definitions below use the supplied SPICE node/source names. +`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered +power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs` +denote magnitude, and `cph` is continuous phase in radians. `find`, `when`, +`from/to`, and `rise/fall` retain the deck's interpolation, window and +crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/ +milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` +mean the stated window average, extrema and sampled derivative. All +declared conditions are measured separately and paired with the same +source condition; a group uses its worst paired quality. + +| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension | +| --- | --- | --- | --- | --- | --- | --- | +| `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vp)-v(vm))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response | +| `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vp)-v(vm)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response | +| `phase_margin` | AC: `180+(find (180*cph((v(vout)/(v(vp)-v(vm))))/pi) when (db((v(vout)/(v(vp)-v(vm)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response | +| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply | +| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias | + +Area reference: **2936.48 um2**. 24 expanded device instances; sum of device/contact envelopes 1887.1830 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim. + +The capability coefficient remains **6**; it is independent of +the reference-relative task score. + + +### Score weights + +Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics. + +| Metric | Weight | +| --- | ---: | +| `functional_area` | 0.1 | +| `low_frequency_gain` | 0.270000000000 | +| `unity_gain_bandwidth` | 0.225000000000 | +| `phase_margin` | 0.225000000000 | +| `output_bias` | 0.045000000000 | +| `supply_power` | 0.135000000000 | + +## Tools and Submission + +Solve budget: **3 hours**. + +Runtime environment and support resources are declared in +`/protocol/resources.json` and `/protocol/harness.json`; the working directory is +`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic +performs RC extraction; ngspice runs the supplied deck with the reviewed SG13G2 +models. The evaluator provides the tool and PDK resources named by the case +toolchain. + +For pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside +the supplied testbench, with the model paths and settings exposed by the runtime +resource bundle. For the submitted layout, the evaluator supplies the +candidate-derived extracted netlist. If the harness declares +`process-feedback`, the optional command is +`python -I /protocol/process_check.py`; the final evaluation remains independent. + +Write the result to `/workspace/output/final.gds`, then run +`python -I /protocol/submit.py` and wait for the submission receipt. Solver +netlists, waveforms, and measurements are not accepted as substitutes for the +independent evaluator inputs. diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/reference/two_stage_OTA_layout.gds b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/reference/two_stage_OTA_layout.gds new file mode 100644 index 0000000000000000000000000000000000000000..70b15163f8f55779272eeb9ac249e7b304f0eae2 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/reference/two_stage_OTA_layout.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:50fa39a6984b6f9d1bc0dda38b379861b981c10b85842cc64d9c0e020f7f15bc +size 353592 diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml new file mode 100644 index 0000000000000000000000000000000000000000..fb71f7bf750aa9f554d879678528444072c00dd4 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml @@ -0,0 +1,630 @@ +in_core = false +kind = "layout_case" +id = "module_1_bandgap_reference.part_3_layout.OTA_layout.input_pair" +title = "IHP AnalogAcademy input_pair" +status = "qualified" + +[[assets]] +path = "materials/schematic.svg" +role = "schematic" +visibility = "maintainer" +format = "svg" +sha256 = "be0b3098da9309ede946b43b9bda1188c5f8a717d0d558693d32b98ae726e0f2" + +[[assets]] +path = "reference/input_common_centroid.gds" +role = "physical-witness" +visibility = "maintainer" +format = "gds" +sha256 = "b28969621e1ec84dfe1ae5336ae5e85af0e1aa9b16068c430748ef105f122be2" + +[task] +hours = 3 +coefficient = 3 +kind = "netlist_to_gds" +family = "ihp_sg13g2_pmos_input_pair" +environment = "ihp-sg13g2-input-pair-rc-tt" + +[task.inputs.description] +path = "problem.md" +sha256 = "b91a95f0f2879d8d309b2b9a6a9b918bf174b21a49a70f096d8843ffb8351d77" +format = "text" + +[task.inputs.netlist] +path = "materials/circuit.cdl" +sha256 = "25456f0316c22ee5586ad3e306f0d513fd35e48f32ee67ce9cb0dc373d306f3d" +format = "spice" +subcircuit = "input_common_centroid" + +[task.inputs.simulation] +path = "materials/circuit.spice" +sha256 = "cde9a2075fbac6afcf32fd02baf847398de1e9d179b3d3a87762534adfd8bd2b" +format = "spice" + +[task.inputs.performance] +path = "materials/testbench.spice" +sha256 = "0ce316136b95395971965c7760a711d8431e8c1d4294a074b658520442e11dde" +format = "spice" + +[task.constraints] +quality = [ + { id = "area", type = "functional_bbox_area", layers_from = "outline" }, +] + +[[task.constraints.hard]] +id = "outline" +type = "bbox_max" +functional_layers = [ + [ + 1, + 0, + ], + [ + 3, + 0, + ], + [ + 5, + 0, + ], + [ + 6, + 0, + ], + [ + 7, + 0, + ], + [ + 8, + 0, + ], + [ + 10, + 0, + ], + [ + 11, + 0, + ], + [ + 13, + 0, + ], + [ + 14, + 0, + ], + [ + 19, + 0, + ], + [ + 24, + 0, + ], + [ + 26, + 0, + ], + [ + 28, + 0, + ], + [ + 29, + 0, + ], + [ + 30, + 0, + ], + [ + 31, + 0, + ], + [ + 32, + 0, + ], + [ + 33, + 0, + ], + [ + 35, + 0, + ], + [ + 36, + 0, + ], + [ + 40, + 0, + ], + [ + 44, + 0, + ], + [ + 46, + 0, + ], + [ + 49, + 0, + ], + [ + 50, + 0, + ], + [ + 51, + 0, + ], + [ + 52, + 0, + ], + [ + 53, + 0, + ], + [ + 55, + 0, + ], + [ + 58, + 0, + ], + [ + 66, + 0, + ], + [ + 67, + 0, + ], + [ + 90, + 0, + ], + [ + 101, + 0, + ], + [ + 111, + 0, + ], + [ + 125, + 0, + ], + [ + 126, + 0, + ], + [ + 128, + 0, + ], + [ + 129, + 0, + ], + [ + 133, + 0, + ], + [ + 134, + 0, + ], + [ + 139, + 0, + ], + [ + 152, + 0, + ], +] +max_width_um = 45 +max_height_um = 40 + +[task.output] +path = "output/final.gds" +format = "gds" +top_cell = "input_common_centroid" +max_bytes = 10485760 + +[task.evaluation] +mode = "post_layout" + +[task.evaluation.scoring] +method = "layout" +area_metric = "functional_area" +area_target = 1236.14 +rationale = "Local gain stages: signal transfer 44.7%; balance and linearity 22.4%; operating points 4.47%; power 13.4%; area 15%. Each objective's weight is divided equally among its metrics." + +[task.evaluation.scoring.weights] +functional_area = 0.15 +differential_gain = 0.223684210526 +differential_gain_high = 0.223684210526 +drain_balance = 0.223684210526 +common_drain = 0.022368421053 +tail_voltage = 0.022368421053 +supply_power = 0.134210526316 + +[[task.evaluation.jobs]] +id = "artifact" +stage = "check" +operation = "layout.artifact" +gate = "artifact" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "drc" +stage = "check" +operation = "layout.drc" +gate = "drc" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" + +[[task.evaluation.jobs]] +id = "lvs" +stage = "check" +operation = "layout.lvs" +gate = "lvs" + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +netlist = "input:netlist" + +[task.evaluation.jobs.outputs] +database = "klayout-lvs" +binding = "json" + +[[task.evaluation.jobs]] +id = "geometry" +stage = "check" +operation = "layout.geometry" +gate = "constraint" +requires = [ + "artifact", + "drc", + "lvs", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" +task = "task" +constraints = "input:constraints" +database = "job:lvs:database" +binding = "job:lvs:binding" + +[[task.evaluation.jobs]] +id = "parasitics" +stage = "extract" +operation = "layout.extract_rc" +requires = [ + "artifact", + "drc", + "lvs", + "geometry", +] + +[task.evaluation.jobs.inputs] +layout = "candidate" + +[task.evaluation.jobs.outputs] +netlist = "spice" + +[task.evaluation.jobs.parameters] +top_cell = "input_common_centroid" +ports = [ + "v-", + "v+", + "vdd", + "dn3", + "dn4", + "tail", +] + +[[task.evaluation.jobs]] +id = "nominal" +stage = "simulate" +operation = "circuit.simulate" +requires = [ + "parasitics", +] + +[task.evaluation.jobs.inputs] +deck = "input:performance" +dut = "job:parasitics:netlist" + +[task.evaluation.jobs.outputs] +ac = "ngspice-raw" +op = "ngspice-raw" + +[task.evaluation.jobs.parameters.values] +tail_current = 2e-05 +common_mode = 0.5 +drain_load = 50000 + +[task.evaluation.jobs.parameters.exports] +ac = "input-ac.raw" +op = "input-op.raw" + +[task.evaluation.jobs.parameters.measurements] +tail_voltage = "V" +drain_balance = "V" +common_drain = "V" +supply_power = "W" +differential_gain = "V/V" +differential_gain_high = "V/V" + +[[task.evaluation.metrics]] +id = "functional_area" +category = "physical" +observations = [ + "geometry:area", +] +unit = "um2" +direction = "minimize" +aggregation = "max" + +[[task.evaluation.metrics]] +id = "differential_gain" +category = "performance" +observations = [ + "nominal:differential_gain", +] +unit = "V/V" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:differential_gain", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "differential_gain_high" +category = "performance" +observations = [ + "nominal:differential_gain_high", +] +unit = "V/V" +direction = "maximize" +aggregation = "min" +dimension = "response" +baseline = [ + "source_nominal:differential_gain_high", +] +normalization = "ratio" +lower = 0 + +[[task.evaluation.metrics]] +id = "tail_voltage" +category = "performance" +observations = [ + "nominal:tail_voltage", +] +unit = "V" +direction = "target" +aggregation = "min" +dimension = "bias" +baseline = [ + "source_nominal:tail_voltage", +] +normalization = "target" +scale = 1.2 + +[[task.evaluation.metrics]] +id = "common_drain" +category = "performance" +observations = [ + "nominal:common_drain", +] +unit = "V" +direction = "target" +aggregation = "min" +dimension = "bias" +baseline = [ + "source_nominal:common_drain", +] +normalization = "target" +scale = 1.2 +lower = 0 +upper = 1.2 + +[[task.evaluation.metrics]] +id = "drain_balance" +category = "performance" +observations = [ + "nominal:drain_balance", +] +unit = "V" +direction = "target" +aggregation = "min" +dimension = "bias" +baseline = [ + "source_nominal:drain_balance", +] +normalization = "target" +scale = 1.2 + +[[task.evaluation.metrics]] +id = "supply_power" +category = "performance" +observations = [ + "nominal:supply_power", +] +unit = "W" +direction = "minimize" +aggregation = "max" +dimension = "supply" +baseline = [ + "source_nominal:supply_power", +] +normalization = "ratio" +lower = 0 +scale = 1e-12 + +[task.evaluation.pre_layout] +source_report_sha256 = "f82335367c588d196a9e3634129a29b2b3e98a9f67b5fa984c53f940f2253886" + +[task.evaluation.pre_layout.backends] +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"868b87913ea2ceaa4e2650d73a934158d54aae1ad194f3713dc37b8c89b75884\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" + +[task.evaluation.pre_layout.jobs.source_nominal] +operation = "circuit.simulate" + +[task.evaluation.pre_layout.jobs.source_nominal.inputs] +deck = "input:performance" +dut = "input:simulation" + +[task.evaluation.pre_layout.jobs.source_nominal.outputs] +ac = "ngspice-raw" +op = "ngspice-raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.values] +tail_current = 2e-05 +common_mode = 0.5 +drain_load = 50000 + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports] +ac = "input-ac.raw" +op = "input-op.raw" + +[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements] +tail_voltage = "V" +drain_balance = "V" +common_drain = "V" +supply_power = "W" +differential_gain = "V/V" +differential_gain_high = "V/V" + +[task.evaluation.pre_layout.jobs.source_nominal.input_sha256] +deck = "0ce316136b95395971965c7760a711d8431e8c1d4294a074b658520442e11dde" +dut = "cde9a2075fbac6afcf32fd02baf847398de1e9d179b3d3a87762534adfd8bd2b" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.common_drain] +value = 0.4999951466028 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.differential_gain] +value = 2.72776 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.differential_gain_high] +value = 3.584662 +unit = "V/V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.drain_balance] +value = -1.11022302463e-16 +unit = "V" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply_power] +value = 2.400003087359e-05 +unit = "W" + +[task.evaluation.pre_layout.jobs.source_nominal.measurements.tail_voltage] +value = 1.192980871489 +unit = "V" + +[toolchain.bindings] +"layout.artifact" = "artifact" +"layout.drc" = "drc" +"layout.lvs" = "lvs" +"layout.geometry" = "geometry" +"layout.extract_rc" = "rc" +"circuit.simulate" = "simulation" + +[toolchain.backends.artifact] +type = "klayout-docker" + +[toolchain.backends.artifact.settings] +image = "iclayout-bench-tools:local" +check = "artifact" +timeout_seconds = 600 + +[toolchain.backends.drc] +type = "klayout-docker" + +[toolchain.backends.drc.support_profiles] +support = "klayout" + +[toolchain.backends.drc.settings] +image = "iclayout-bench-tools:local" +check = "drc" +support = "build/support/input-pair-klayout" +profile = "drc-upstream.json" +timeout_seconds = 600 + +[toolchain.backends.lvs] +type = "klayout-docker" + +[toolchain.backends.lvs.support_profiles] +support = "klayout" + +[toolchain.backends.lvs.settings] +image = "iclayout-bench-tools:local" +check = "lvs" +support = "build/support/input-pair-klayout" +profile = "lvs-upstream.json" +timeout_seconds = 600 + +[toolchain.backends.rc] +type = "magic-rc-docker" + +[toolchain.backends.rc.support_profiles] +support = "magic" + +[toolchain.backends.rc.settings] +image = "iclayout-bench-tools:local" +support = "build/support/input-pair-magic" +technology = "magic/ihp-sg13g2.tech" +tech_name = "ihp-sg13g2" +style = "ngspice()" +capacitance_threshold_ff = 0 +timeout_seconds = 600 + +[toolchain.backends.geometry] +type = "klayout-geometry-docker" + +[toolchain.backends.geometry.settings] +image = "iclayout-bench-tools:local" +timeout_seconds = 120 + +[toolchain.backends.simulation] +type = "ngspice-docker" + +[toolchain.backends.simulation.support_profiles] +support = "analog-models" + +[toolchain.backends.simulation.settings] +image = "iclayout-bench-tools:local" +support = "build/support/input-pair-models" +timeout_seconds = 600 + +[qualification] +reference = "reference/input_common_centroid.gds" + +[origin] +url = "https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch" + +[presentation] +category = "Amplifiers & RF" +summary = "Converts a differential input into a balanced response using a matched PMOS pair." diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl new file mode 100644 index 0000000000000000000000000000000000000000..466c2e2c4738296ac9a5ad68dd3f9b241d975ca4 --- /dev/null +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl @@ -0,0 +1,13 @@ +* Maintained IHP AnalogAcademy derivative for the Layout-Bench input-pair case. +* The shared source node is promoted to an explicit tail port so the pair can +* be biased and its differential transconductance can be checked standalone. +.subckt input_common_centroid v- v+ vdd dn3 dn4 tail +*.PININFO v-:B v+:B vdd:B dn3:B dn4:B tail:B +MM1 dn3 v- tail bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM2 dn4 v+ tail bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM8 dn4 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM10 dn3 vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM15 tail vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +MM16 tail vdd vdd bulk sg13_lv_pmos w=3.64u l=3.7u ng=1 m=2 +RR1 vdd bulk ntap1 A=4.42e-10 P=9.4e-05 +.ends input_common_centroid