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+{"id":"TO_Apr2025.160GHz_LNA","in_core":false,"title":"TO_Apr2025 160-derived four-stage LNA at 100 MHz","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies voltage through four direct-coupled SiGe HBT stages with emitter degeneration and interstage bias clamps.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/160GHz_LNA/design_data/qucs-s/160GHz_LNA(MAIN).sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Four-Stage SiGe HBT Voltage Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained four-stage direct-coupled\ncommon-emitter voltage amplifier in `LNA160_FOUR_STAGE`. Preserve the circuit\nconnectivity, HBT multiplicities, passive dimensions and five external ports.\nThe submitted top cell must be `LNA160_FOUR_STAGE` and must pass the physical\nchecks and nominal post-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and drawn device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal operating-point and AC testbench |\n\nThe circuit is a four-stage direct-coupled common-emitter amplifier. Four\n`npn13G2` devices (`Nx=1`) form the gain chain. Each collector has an `rppd`\nload to `VDD`, each emitter has an `rsil` resistor to `VSS`, and the three\ninterstage collector nodes have `rppd` clamps to `VBIAS`. The emitter\nresistors are 4 µm wide with lengths 20.00, 20.01, 20.02 and 20.03 µm in\nstage order. An explicit `ptap1` connects the substrate body to `VSS`.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `IN` | Voltage input to the first HBT base |\n| `OUT` | Voltage output from the fourth collector and 50 fF load node |\n| `VDD` | Common collector-load supply, 1.2 V |\n| `VSS` | Common return and substrate-tap reference |\n| `VBIAS` | Interstage clamp-bias supply, 0.76 V |\n\nLVS and simulation use this order exactly. The netlists specify\nfour 0.07 × 0.9 µm drawn `npn13G2` devices, four 2 × 20 µm `rppd` collector\nloads, four stage-specific `rsil` emitter resistors, three 1 × 4 µm `rppd`\ninterstage clamps, and a substrate tap with `A=4 µm²`, `P=8 µm` and finite\nsimulator equivalent `R=81.6666667 Ω`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`; 27 °C |\n| Supplies and DC bias | `VDD=1.2 V`, `VSS=0 V`, `VIN=0.8 V`, `VBIAS=0.76 V` |\n| AC stimulus | 1 V at `VIN` for small-signal gain normalization |\n| Output load | 50 fF from `OUT` to `VSS` |\n| AC sweep | 1 MHz–1 GHz, 40 points per decade; gain measured at 100 MHz |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal input.\nThe deck reports the input bias, output bias, `VDD` current, `VBIAS` current\nand voltage gain; only the metrics in the table below are acceptance\ncriteria.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 10 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe five ports, HBT multiplicities, passive geometry and explicit substrate\ntap. Artifact, DRC, LVS and geometry gates all precede candidate extraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 160 µm and the maximum height is\n90 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Strict LVS\nretains the finite `ptap1` card and the drawn HBT geometry. In the simulator\nexport, the ordinary `npn13G2` model supplies its effective device dimensions\nwhile `Nx=1` and all terminal connections are preserved; the drawn LVS\ndimensions are not silently used as behavioral dimensions. The candidate path\nreconciles the approved SG13G2 substrate body boundary to `VSS` with tap\nextraction disabled. The finite source tap remains in calibration. Only the internal HBT body domain, identified through its physical tap\nreturn, may be reconciled to VSS. Collector, base, emitter, resistor terminals\nand geometry, and top-level ports remain candidate-derived. No other\ninternal-node aliases or simulator global-ground substitutions are permitted.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `gain_db` | AC: Value of `(db(v(out)/v(in))) at=100meg`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `output_bias` | DC operating point: `v(out)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `supply_current` | DC operating point: `-i(vdd)`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **1326.32 um2**. 16 expanded device instances; sum of device/contact envelopes 836.9640 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_db` | 0.688235294117 |\n| `output_bias` | 0.052941176471 |\n| `supply_current` | 0.158823529412 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`LNA160_FOUR_STAGE` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe evaluator uses the submitted snapshot for all physical checks, extraction\nand simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml","case_sha256":"a4f6da41ad22694e6f4a6a3d59aa2a1c186e5c52448168ba8a4800c20c981d65","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/circuit.cdl","netlist_sha256":"26b815aa103d0d81b54e21c661b28860304a5d23be900d17192cbb92100be3c6","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"}
+{"id":"TO_Apr2025.40_GHZ_LOW_NOISE_TIA","in_core":false,"title":"TO_Apr2025 40 GHz low-noise single-ended TIA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts input current to voltage through three SiGe HBT stages with resistive feedback and emitter degeneration.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/40_GHZ_LOW_NOISE_TIA/design_data/qucs-s/40_GHz_Low_Noise_TIA.sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Three-Stage SiGe HBT Transimpedance Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained three-stage, single-ended\ntransimpedance amplifier in `FDM_QNC_00_LN_TIA`. Preserve the circuit\nconnectivity, device multiplicities, passive dimensions and six external\nports. The submitted top cell must be `FDM_QNC_00_LN_TIA` and must pass the\nphysical checks and nominal post-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal pre-layout and post-layout operating-point and AC testbench |\n\nThe circuit is a three-stage SiGe HBT transimpedance core. Q1 is the input\ncommon-emitter device (`Nx=5`), Q2 is the intermediate common-collector\ndevice (`Nx=10`), and Q3 is the output common-emitter device (`Nx=10`). The\nresistor network provides collector loads, emitter degeneration and feedback;\nthree `cap_cmim` capacitors decouple the independent supply rails. The\nexplicit `ptap1` connects the substrate body to `VSS`.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `RFin` | Current input and transimpedance sensing node |\n| `RFout` | Voltage output and 50 fF load node |\n| `VSS` | Common return and substrate-tap reference |\n| `vcc1` | Q1 collector-load supply, 1.7 V |\n| `vcc2` | Q2 collector supply, 2.1 V |\n| `vcc3` | Q3 collector-load supply, 2.1 V |\n\nLVS and simulation use this order exactly. The netlists specify\nthree `npn13G2` devices, `rppd` and `rsil` resistors, 30 × 60 µm `cap_cmim`\ndevices with `m=2`, and a substrate tap with `A=25 µm²`, `P=20 µm` and\nfinite simulator equivalent `R=21.7391304348 Ω`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`, `cap_typ`; 26.85 °C |\n| Supplies | `vcc1=1.7 V`, `vcc2=2.1 V`, `vcc3=2.1 V` |\n| Input DC current | −100 µA, 0 A and +100 µA from `VSS` into `RFin` |\n| AC stimulus | 1 A at the zero-volt `VSENSE` source for normalization |\n| Output load | 50 fF from `RFout` to `VSS` |\n| AC sweep | 1 MHz–100 MHz, 40 points per decade |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal 1 A\ninput. Transfer uses the current measured at `VSENSE`, and supply power is\ncalculated from the three independent supply sources.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 32 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe six ports, device multiplicities, passive geometry and explicit substrate\ntap. Artifact, DRC, strict LVS and geometry gates all precede candidate\nextraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 660 µm and the maximum height is\n620 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Drawn emitter\ngeometry is checked against the candidate; effective ordinary `npn13G2`\ndimensions use the simulator model defaults, with the extracted `Nx` retained. The standard\npath disables tap extraction at the approved SG13G2 substrate boundary so\nthe compact-device body can be reconciled to `VSS`; strict LVS still checks\nthe finite `ptap1` card. Device terminals, multiplicities, resistor geometry,\nMIM geometry and top-level connectivity remain candidate-derived. The\nfinite source tap is retained in pre-layout calibration, and the accepted\nmodel boundary is limited to the nominal low-frequency transfer and bias\nmeasurements in this task. No other internal-node aliases are permitted; a simulator global ground\nalias must not replace the explicit source substrate connection.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `transimpedance_low` | AC: Value of `(real(v(RFout)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `transimpedance_high` | AC: Value of `(mag(v(RFout)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `input_bias` | DC operating point: `v(RFin)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `output_bias` | DC operating point: `v(RFout)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `supply_power` | DC operating point: `-v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)-v(vcc3)*i(VCC3)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **18573.26 um2**. 15 expanded device instances; sum of device/contact envelopes 12204.4550 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `transimpedance_high` | 0.344117647059 |\n| `transimpedance_low` | 0.344117647059 |\n| `input_bias` | 0.026470588235 |\n| `output_bias` | 0.026470588235 |\n| `supply_power` | 0.158823529412 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`FDM_QNC_00_LN_TIA` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe explicit submission command is required after the file has been\nvalidated. The evaluator uses the submitted snapshot for all physical checks,\nextraction and simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml","case_sha256":"dc96d8b5faa197829ac8b5f9258b11e647e8c3d406fce9b51a3c2d2238411d7d","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/circuit.cdl","netlist_sha256":"17a094c09698acfbe6a25a50d3a0292ebb82fd82b7e21269442bcdd4fa3c0d45","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"}
+{"id":"TO_Apr2025.97_GHZ_LINEAR_TIA","in_core":false,"title":"TO_Apr2025 97-derived multi-stage linear TIA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts input current to voltage using three SiGe HBT stages and active emitter-follower feedback.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/97_GHZ_LINEAR_TIA/design_data/qucs-s/97_GHZ_LINEAR_TIA.sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Linear SiGe HBT Transimpedance Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained multi-stage linear\ntransimpedance amplifier in `FMD_QNC_01_LIN_TIA`. Preserve the circuit\nconnectivity, HBT multiplicities, passive dimensions and six external ports.\nThe submitted top cell must be `FMD_QNC_01_LIN_TIA` and must pass the physical\nchecks and nominal post-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal operating-point, AC and DC-linearity testbench |\n\nThe circuit is a three-stage SiGe HBT transimpedance core with active\nfeedback. Q1 is the input common-emitter device (`Nx=5`), Q2 is the\nintermediate emitter follower (`Nx=10`), Q3 is the output common-emitter\ndevice (`Nx=10`), and Q4 is an active emitter-follower feedback device\n(`Nx=5`) sensing `RFOUT`. `RFB` returns the Q4 feedback signal to the\nQ2/Q3 interstage node. The remaining resistors provide collector loading,\nemitter degeneration and input feedback; three `cap_cmim` devices decouple\nthe independent supply rails. An explicit `ptap1` connects the substrate\nbody to `VSS`.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `RFIN` | Current input and transimpedance sensing node |\n| `RFOUT` | Voltage output and 50 fF load node |\n| `VCC1` | First collector-load supply, 1.7 V |\n| `VCC2` | Q2/Q4 collector supply, 2.1 V |\n| `VCC3` | Q3 collector-load supply, 2.1 V |\n| `VSS` | Common return and substrate-tap reference |\n\nLVS and simulation use this order exactly. The netlists specify\nthe HBT multiplicities, resistor dimensions, 30 × 60 µm `cap_cmim` devices\nwith `m=2`, and a substrate tap with `A=4 µm²`, `P=8 µm` and finite\nsimulator equivalent `R=81.6666667 Ω`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`, `cap_typ`; 26.85 °C |\n| Supplies | `VCC1=1.7 V`, `VCC2=2.1 V`, `VCC3=2.1 V` |\n| Input DC current | −5 µA, 0 A and +5 µA from `VSS` into `RFIN` |\n| AC stimulus | 1 A at the zero-volt `VSENSE` source for normalization |\n| Output load | 50 fF from `RFOUT` to `VSS` |\n| AC sweep | 1 MHz–100 MHz, 40 points per decade |\n| Linearity sweep | 21 DC points from −5 µA to +5 µA in 0.5 µA steps |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal 1 A\ninput. Transfer is normalized by the current measured at `VSENSE`, and\nsupply power is calculated from the three independent supply sources.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 32 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe six ports, device multiplicities, passive geometry and explicit substrate\ntap. Artifact, DRC, strict LVS and geometry gates all precede candidate\nextraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 720 µm and the maximum height is\n620 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Drawn emitter\ngeometry is checked against the candidate; effective ordinary `npn13G2`\ndimensions use the simulator model defaults, with the extracted `Nx` retained. The standard\npath disables tap extraction at the approved SG13G2 substrate boundary so\nthe compact-device body can be reconciled to `VSS`; strict LVS still checks\nthe finite `ptap1` card. Device terminals, multiplicities, resistor geometry,\nMIM geometry and top-level connectivity remain candidate-derived. The\nfinite source tap is retained in pre-layout calibration, and the accepted\nmodel boundary is limited to the nominal transfer, bias, power and linearity\nmeasurements in this task. No other internal-node aliases are permitted; a simulator global ground\nalias must not replace the explicit source substrate connection.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `transimpedance_low` | AC: Value of `(real(v(RFOUT)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `transimpedance_high` | AC: Value of `(mag(v(RFOUT)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `linearity_error_pct` | Maximum absolute deviation of DC RFOUT from the line through the endpoint samples, divided by absolute output span, times 100; IIN sweeps -5 to +5 uA in 0.5 uA steps. | percent | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `input_bias` | DC operating point: `v(RFIN)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `output_bias` | DC operating point: `v(RFOUT)`. | V | target / target | 0 … 2.1 | 2.1 | bias |\n| `supply_power` | DC operating point: `-v(VCC1)*i(VCC1)-v(VCC2)*i(VCC2)-v(VCC3)*i(VCC3)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **18718.54 um2**. 17 expanded device instances; sum of device/contact envelopes 12300.6100 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 53.2%; linearity 20.5%; bias 4.09%; supply cost 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `transimpedance_high` | 0.265909090909 |\n| `transimpedance_low` | 0.265909090909 |\n| `linearity_error_pct` | 0.204545454545 |\n| `input_bias` | 0.020454545455 |\n| `output_bias` | 0.020454545455 |\n| `supply_power` | 0.122727272727 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`FMD_QNC_01_LIN_TIA` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe evaluator uses the submitted snapshot for all physical checks, extraction\nand simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml","case_sha256":"7f46e608f85c1375b19a29ba2ed65c64623fe1338f7a36885ebd559581d49ce4","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/circuit.cdl","netlist_sha256":"150ab19522eecccf2889ed62c07b14e15e29e97a75ce12563fcd95d846be9112","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"}
+{"id":"TO_Apr2025.DC_to_130_GHz_TIA.design_1","in_core":false,"title":"Two-stage SiGe HBT TIA with nominal AC/DC requirements","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts input current to voltage through two direct-coupled SiGe HBT stages with first-stage resistive feedback.","source_url":"https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/DC_to_130_GHz_TIA/design_1/design_data/qucs-s/DC_to_130_GHz_TIA.sch","status":"qualified","collection":"TO_Apr2025","task_kind":"netlist_to_gds","problem":"# Two-Stage SiGe HBT Transimpedance Amplifier Layout Task\n\n## Objective\n\nCreate a clean SG13G2 layout for the maintained two-stage transimpedance\namplifier in `FMD_QNC_03a_TIA_1`. Preserve the circuit connectivity, HBT\nmultiplicities, passive dimensions and five external ports. The submitted top\ncell must be `FMD_QNC_03a_TIA_1` and must pass the physical checks and nominal\npost-layout measurements below.\n\n## Inputs and Interface\n\nIn addition to this problem, the runtime task supplies the following declared\ninputs:\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist and device geometry |\n| [materials/circuit.spice](materials/circuit.spice) | Authoritative simulator export |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal operating-point and AC testbench |\n\nThe circuit is a two-stage SiGe HBT transimpedance core. Q1 is the first\ncommon-emitter stage (`Nx=5`) and drives Q2, the second common-emitter stage\n(`Nx=4`). `RC1` and `RC2` are independent collector loads, `RRF` provides\nfirst-stage resistive feedback from `DN1` to `INPUT`, and `C1` and `C2`\ndecouple the two supply rails. The explicit `ptap1` has both terminals on\n`VEE`, so it is a same-net substrate tie.\n\nThe ordered top-level interface is:\n\n| Port | Function |\n|---|---|\n| `INPUT` | Current input and transimpedance sensing node |\n| `OUTPUT` | Voltage output and 50 fF load node |\n| `VCC2V` | Q1 collector-load supply, 2 V |\n| `VCC2V1` | Q2 collector-load supply, 2 V |\n| `VEE` | Common return and substrate reference |\n\nLVS and simulation use this order exactly. The netlists specify\n`npn13G2` devices with `Nx=5` and `Nx=4`, `rppd` resistors with dimensions\n15 × 4 µm, 11.5 × 2 µm and 29 × 6.3 µm, two 30 × 30 µm `cap_cmim`\ndevices with `m=1`, and the tap geometry `A=3.6504 µm²`, `P=18.72 µm`.\n\n## Operating Conditions\n\n| Parameter | Setting |\n|---|---|\n| Models and temperature | `hbt_typ`, `res_typ`, `cap_typ`; 26.85 °C |\n| Supplies | `VCC2V=2 V`, `VCC2V1=2 V`, `VEE=0 V` |\n| Input DC current | −100 µA, 0 A and +100 µA from the return into `INPUT` |\n| AC stimulus | 1 A at the zero-volt `VSENSE` source for normalization |\n| Output load | 50 fF from `OUTPUT` to the simulator return |\n| External loads | No external resistive input or output load |\n| AC sweep | 1 MHz–100 MHz, 40 points per decade |\n| Solver options | `rshunt=1e12` Ω, `reltol=1e-6`, `vntol=1e-8` V, `abstol=1e-12` A |\n\nThe AC stimulus is a small-signal normalization, not a large-signal 1 A\ninput. The shunt anchors DC-floating capacitive islands while retaining their\nAC coupling. Transfer is normalized by the current measured at `VSENSE`, and\nsupply power is calculated from the two independent supply sources.\n\n## Physical Requirements\n\nThe candidate GDS must be readable, non-empty and no larger than 32 MiB. It\nmust pass the pinned SG13G2 main and additional maximal DRC scopes in deep\nmode without waivers; density and antenna checks are outside this declared scope. It must\nalso pass strict named-port LVS against `materials/circuit.cdl`, including\nthe five ports, device multiplicities, passive geometry and the same-net\nsubstrate tap. Artifact, DRC, LVS and geometry gates all precede candidate\nextraction.\n\nThe GDS must include the complete target hierarchy. Port names are matched\ncase-insensitively; each declared port must remain on its own conductor with\nthe declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 720 µm and the maximum height is\n860 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nCandidate post-layout extraction combines candidate-derived HBT geometry and\n`Nx` with distributed interconnect resistance and capacitance. Drawn emitter\ngeometry is checked against the candidate; effective ordinary `npn13G2`\ndimensions use the simulator model defaults, with the extracted `Nx` retained. It preserves\ndevice terminals, resistor and MIM geometry, top-level connectivity and the\nsame-net substrate boundary. The simulator export represents the tap with\nits finite PDK equivalent `R=43.80789 Ω`; because both tap terminals are\n`VEE`, this element has no DC voltage drop. The `rshunt` conditioning and\nsubstrate boundary are numerical model choices and do not add an external\nport or change the maintained circuit.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `transimpedance_low` | AC: Value of `(real(v(output)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `transimpedance_high` | AC: Value of `(mag(v(output)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |\n| `input_bias` | DC operating point: `v(input)`. | V | target / target | 0 … 2.0 | 2.0 | bias |\n| `output_bias` | DC operating point: `v(output)`. | V | target / target | 0 … 2.0 | 2.0 | bias |\n| `supply_power` | DC operating point: `-v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **3852.28 um2**. 8 expanded device instances; sum of device/contact envelopes 2487.4228 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `transimpedance_high` | 0.344117647059 |\n| `transimpedance_low` | 0.344117647059 |\n| `input_bias` | 0.026470588235 |\n| `output_bias` | 0.026470588235 |\n| `supply_power` | 0.158823529412 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover the supplied task, resources, harness and constraints from\n`/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the tool and PDK resources selected by the\nruntime environment. If the harness declares `process-feedback`, request\nan optional frozen process check with `python -I /protocol/process_check.py`;\nthe final evaluation remains independent.\n\nWrite the answer to `/workspace/output/final.gds` as a GDS file with top cell\n`FMD_QNC_03a_TIA_1` and wait for the submission receipt:\n\n```bash\npython -I /protocol/submit.py\n```\n\nThe evaluator uses the submitted snapshot for all physical checks, extraction\nand simulations.\n","case_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml","case_sha256":"14aae4dca4c95dbe6ec8c9e6afa48112cba35b8993ad40207511749810fffd14","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/problem.md","netlist_path":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/circuit.cdl","netlist_sha256":"41054606cd4c4845149df6c9a38a7d38d45ae4ba22afb5ff588d33051aaf06f3","license_path":"tasks/ihp-sg13g2/TO_Apr2025/LICENSE"}
+{"id":"freepdk45.OpenRAM.cell_6t","in_core":true,"title":"Six-Transistor SRAM Bitcell","pdk":"freepdk45","category":"Logic & memory","summary":"Stores one bit using cross-coupled inverters and wordline-controlled access transistors.","source_url":"https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/cell_6t.sp","status":"qualified","collection":"OpenRAM","task_kind":"netlist_to_gds","problem":"# Six-Transistor SRAM Bitcell Layout Task\n\n## Objective\n\nImplement the supplied six-transistor SRAM bitcell, including cross-coupled storage, complementary bitlines and a common wordline. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `cell_6t`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `bl br wl vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nEach bitline has 10 fF. Ideal external switches (10 ohm on, 1e12 ohm off) implement write and precharge. Write BL=0/BR=1 during 0–500 ps, then precharge and read at 1 ns and 2 ns; write the opposite value at 4–4.5 ns, then read at 5 ns and 6 ns. Sample differential bitline voltage 110 ps after each read starts. Wordline transitions take 10 ps; read pulses last 300 ps. The second read checks retention after a nondestructive read and idle interval. The supplied deck gives every switch edge. Power includes DUT supply current and the precharge supply over 0–7 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `read0` | `find par('v(br)-v(bl)') at=1110p` | V | functional check | 0.3 … +∞ | — |\n| `repeat0` | `find par('v(br)-v(bl)') at=2110p` | V | functional check | 0.3 … +∞ | — |\n| `read1` | `find par('v(bl)-v(br)') at=5110p` | V | functional check | 0.3 … +∞ | — |\n| `repeat1` | `find par('v(bl)-v(br)') at=6110p` | V | functional check | 0.3 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=7n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `read_delay` | WL rising through 0.5 V to signed bitline difference reaching 0.1 V, for read edges at 1, 2, 5 and 6 ns (distinct from the 0.3 V sampled-level requirement). | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **1.46 um2**. 6 expanded device instances; sum of device/contact envelopes 0.6670 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSRAM cell: read delay 64%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.2 |\n| `read_delay` | 0.640000000000 |\n| `supply` | 0.160000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml","case_sha256":"6c2679fb5cb32d7cd00408e7808ee42dbc1da3e896cea43ed2737f606383d15f","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md","netlist_path":"tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice","netlist_sha256":"18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488","license_path":"tasks/freepdk45/OpenRAM/LICENSE"}
+{"id":"freepdk45.OpenRAM.sense_amp","in_core":false,"title":"Clocked SRAM Sense Amplifier","pdk":"freepdk45","category":"Logic & memory","summary":"Resolves a small bitline voltage difference into a clocked digital decision.","source_url":"https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/sense_amp.sp","status":"qualified","collection":"OpenRAM","task_kind":"netlist_to_gds","problem":"# Clocked SRAM Sense Amplifier Layout Task\n\n## Objective\n\nImplement the supplied clocked regenerative sense amplifier. A lower sampled BL than BR must produce a low Dout; the opposite differential must produce a high Dout. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `sense_amp`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `bl br dout sclk vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nBL/BR are 0.8/1.0 V for the first decision and 1.0/0.8 V for the second. SCLK is low while sampling and rises at 500 ps and 1500 ps with 10 ps edges; it stays high for 480 ps. Dout drives 0.5 fF. Sample Dout at 610 ps and 1610 ps. Average supply power over 0–2 ns. This is a 200 mV differential, loaded decision task; 50 mV sensitivity is not specified.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `low` | `find v(dout) at=610p` | V | functional check | −∞ … 0.1 | — |\n| `high` | `find v(dout) at=1610p` | V | functional check | 0.9 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `decision_delay_fall` | SCLK 50% to Dout 50% decision delay; see testbench window. | s | minimize / ratio | 0.0 … +∞ | — |\n\nArea reference: **2.82 um2**. 7 expanded device instances; sum of device/contact envelopes 1.4529 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `decision_delay_fall` | 0.680000000000 |\n| `supply` | 0.170000000000 |\n\nOnly the falling output decision delay contributes to timing quality. Both\ndecision polarities must satisfy their sampled final-level checks; rising\ndecision timing is outside this task's measured objective.\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml","case_sha256":"8328dbb68781a7494f950d373dc294d519ddfe7115bc9f11ad7b4d0d02c7fb8a","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md","netlist_path":"tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice","netlist_sha256":"f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f","license_path":"tasks/freepdk45/OpenRAM/LICENSE"}
+{"id":"freepdk45.OpenRAM.write_driver","in_core":true,"title":"Complementary SRAM Write Driver","pdk":"freepdk45","category":"Logic & memory","summary":"Drives complementary bitlines during a write and releases them when disabled.","source_url":"https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/write_driver.sp","status":"qualified","collection":"OpenRAM","task_kind":"netlist_to_gds","problem":"# Complementary SRAM Write Driver Layout Task\n\n## Objective\n\nImplement the supplied complementary tri-state write driver: WEN=1 drives BL=DIN and BR=NOT DIN; WEN=0 disables both outputs. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `write_driver`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `din bl br wen vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nBL and BR each drive 10 fF and a 100 kohm resistor to 0.5 V. DIN starts low, rises at 500 ps and falls at 1 ns, with 10 ps edges and a 1 ns period. WEN is high until 2 ns and falls over 10 ps. Sample the enabled complementary outputs at 300 ps and 710 ps, and both disabled outputs at 11.9 ns. The passive midpoint loads test high impedance without accessing internal nodes. Average DUT supply power over 0–2 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `bl_low` | `find v(bl) at=300p` | V | functional check | −∞ … 0.1 | — |\n| `br_high` | `find v(br) at=300p` | V | functional check | 0.9 … +∞ | — |\n| `bl_high` | `find v(bl) at=710p` | V | functional check | 0.9 … +∞ | — |\n| `br_low` | `find v(br) at=710p` | V | functional check | −∞ … 0.1 | — |\n| `z_bl` | `find v(bl) at=11.9n` | V | functional check | 0.45 … 0.55 | — |\n| `z_br` | `find v(br) at=11.9n` | V | functional check | 0.45 … 0.55 | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `data_delay` | DIN rising through 0.5 V after 0.5 ns to BL rising or BR falling through 0.5 V; both arcs are source-paired. | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **3.36 um2**. 12 expanded device instances; sum of device/contact envelopes 1.7748 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **3**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `data_delay` | 0.680000000000 |\n| `supply` | 0.170000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/OpenRAM/cases/write_driver/case.toml","case_sha256":"344c861ca5e70437c468459eb92ecca2682a2025c4ff1fa304260a1ae34ebdd4","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/OpenRAM/cases/write_driver/problem.md","netlist_path":"tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice","netlist_sha256":"40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4","license_path":"tasks/freepdk45/OpenRAM/LICENSE"}
+{"id":"freepdk45.nangate45-pdk.AOI21_X1","in_core":false,"title":"AND-OR-Invert Gate","pdk":"freepdk45","category":"Logic & memory","summary":"Implements AND-OR-invert logic in a fixed-height standard cell.","source_url":"https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/AOI21_X1.spi","status":"qualified","collection":"nangate45-pdk","task_kind":"netlist_to_gds","problem":"# AND-OR-Invert Gate Layout Task\n\n## Objective\n\nImplement ZN = NOT (A OR (B1 AND B2)) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `AOI21_X1`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `A B1 B2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nZN drives 5 fF. Apply the three-bit Gray cycle 000, 001, 011, 010, 110, 111, 101, 100, 000 and then its reverse to A/B1/B2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This covers the truth table and both directions of every transition in that cycle. Average DUT supply power over 0–8.4 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n\nThe standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.\n\n- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_4` | `find v(ZN) at=2.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_5` | `find v(ZN) at=2.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_7` | `find v(ZN) at=3.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_9` | `find v(ZN) at=4.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_10` | `find v(ZN) at=5.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_11` | `find v(ZN) at=5.610n` | V | functional check | −∞ … 0.1 | — |\n| `state_12` | `find v(ZN) at=6.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_13` | `find v(ZN) at=6.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_14` | `find v(ZN) at=7.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_15` | `find v(ZN) at=7.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_16` | `find v(ZN) at=8.110n` | V | functional check | 0.9 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=8.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `propagation_delay` | Worst paired quality over: delay_b1_fall_2, delay_b2_rise_3, delay_a_fall_4, delay_a_rise_8, delay_a_fall_9, delay_a_rise_13, delay_b2_fall_14, delay_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — |\n| `output_transition` | Worst paired quality over: transition_b1_fall_2, transition_b2_rise_3, transition_a_fall_4, transition_a_rise_8, transition_a_fall_9, transition_a_rise_13, transition_b2_fall_14, transition_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **2.0049 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.23 by 1.63 um = 2.0049 um2. Reference SHA-256: 1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94. This footprint includes the maintained explicit taps and routing.\n\nThe capability coefficient remains **2**; it is independent of\nthe reference-relative task score.\n\n### Standard-cell design guidance\n\nPlan the device rows, power rails and signal access before routing. Represent\npull-up and pull-down connectivity as transistor-edge graphs; explore compatible\nEuler trails and alternative orderings to share diffusion and reduce breaks.\nChoose among legal orderings using routing length, parasitic loading and signal\naccess, rather than diffusion sharing alone. Preserve the fixed netlist sizes,\nmodels and connectivity; size optimization is outside this task.\n\nUse the task's declared row height, grid and rail geometry. Keep local routes\ncompact, leave signal pins accessible, and avoid consuming extra routing layers\nwithout benefit. Check DRC and named-port LVS, then extract the candidate and\ncompare both transition directions and power with the source simulation. Iterate\non measured parasitic effects rather than visual compactness alone. These are\noptional techniques, not a mandated algorithm or reference placement.\n\nAdapted from Xu et al., *Standard Cell Library Design and Optimization Methodology\nfor ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,\ntrack counts and process-specific dimensions do not apply to this task.\n\n\n### Score weights\n\nStandard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.2 |\n| `propagation_delay` | 0.480000000000 |\n| `output_transition` | 0.160000000000 |\n| `supply` | 0.160000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml","case_sha256":"d9ce43cffb98fa1756ef7ba34c343716a1f413f55bef095b6f6dce04a4344ce5","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md","netlist_path":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice","netlist_sha256":"07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e","license_path":"tasks/freepdk45/nangate45-pdk/LICENSE"}
+{"id":"freepdk45.nangate45-pdk.NAND2_X1","in_core":true,"title":"Two-Input NAND","pdk":"freepdk45","category":"Logic & memory","summary":"Implements two-input NAND logic in a fixed-height standard cell.","source_url":"https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/NAND2_X1.spi","status":"qualified","collection":"nangate45-pdk","task_kind":"netlist_to_gds","problem":"# Two-Input NAND Layout Task\n\n## Objective\n\nImplement ZN = NOT (A1 AND A2) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `NAND2_X1`.\n\n## Inputs and Interface\n\nOrdered SPICE ports: `A1 A2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.\n\n## Operating Conditions\n\nUse the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.\n\nZN drives 5 fF. Apply 00, 01, 11, 10, 00, 10, 11, 01, 00 to A1/A2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This visits the full truth table and both directions of each single-input transition. Average DUT supply power over 0–4.4 ns.\n\nThe deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.\n\nThe hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.\n\nTranslation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.\n\n\nThe standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.\n\n- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.\n\n## Electrical Requirements and Scoring\n\nArtifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_4` | `find v(ZN) at=2.110n` | V | functional check | 0.9 … +∞ | — |\n| `state_5` | `find v(ZN) at=2.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — |\n| `state_7` | `find v(ZN) at=3.610n` | V | functional check | 0.9 … +∞ | — |\n| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — |\n| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=4.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `propagation_delay` | Worst paired quality over: delay_a1_fall_2, delay_a2_rise_3, delay_a2_fall_6, delay_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — |\n| `output_transition` | Worst paired quality over: transition_a1_fall_2, transition_a2_rise_3, transition_a2_fall_6, transition_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — |\n\nArea reference: **1.6789 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.03 by 1.63 um = 1.6789 um2. Reference SHA-256: d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f. This footprint includes the maintained explicit taps and routing.\n\nThe capability coefficient remains **1**; it is independent of\nthe reference-relative task score.\n\n### Standard-cell design guidance\n\nPlan the device rows, power rails and signal access before routing. Represent\npull-up and pull-down connectivity as transistor-edge graphs; explore compatible\nEuler trails and alternative orderings to share diffusion and reduce breaks.\nChoose among legal orderings using routing length, parasitic loading and signal\naccess, rather than diffusion sharing alone. Preserve the fixed netlist sizes,\nmodels and connectivity; size optimization is outside this task.\n\nUse the task's declared row height, grid and rail geometry. Keep local routes\ncompact, leave signal pins accessible, and avoid consuming extra routing layers\nwithout benefit. Check DRC and named-port LVS, then extract the candidate and\ncompare both transition directions and power with the source simulation. Iterate\non measured parasitic effects rather than visual compactness alone. These are\noptional techniques, not a mandated algorithm or reference placement.\n\nAdapted from Xu et al., *Standard Cell Library Design and Optimization Methodology\nfor ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,\ntrack counts and process-specific dimensions do not apply to this task.\n\n\n### Score weights\n\nStandard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.2 |\n| `propagation_delay` | 0.480000000000 |\n| `output_transition` | 0.160000000000 |\n| `supply` | 0.160000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.\n","case_path":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml","case_sha256":"c3ac5b9c510046ebbca1312d025e605fd5e29b72f4208e34da04cac1078f5aeb","pdk_path":"tasks/freepdk45/pdk.toml","pdk_sha256":"18da21ad21262147a6b83e4c7c45805f0237134a6194718c0f385bcf5c45cb3e","description_path":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md","netlist_path":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice","netlist_sha256":"1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0","license_path":"tasks/freepdk45/nangate45-pdk/LICENSE"}
+{"id":"gf180mcuD.2AMLogic-sar-adc.track_switch","in_core":false,"title":"Dummy-Compensated Track Switch","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Tracks an analog input through a transmission gate with dummy compensation.","source_url":"https://github.com/2AMLogic/gf180-sar-adc/tree/c32c8da53e52fbb7d75f6f628b8cc9f6f45a13fc/design/adc-top/adc_top.spice","status":"qualified","collection":"2AMLogic-sar-adc","task_kind":"netlist_to_gds","problem":"# Dummy-Compensated Track Switch Layout Task\n\n## Objective\n\nImplement `adc_tgate_dum` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Complementary-clock tracking, settling and hold feedthrough for 0.5 V / 2.5 V steps and a 1 pF output capacitor.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `vin, vout, clk, clkb, vdd, vss`.\nvin: signal input; vout: sampled output; clk/clkb: complementary track control; vdd/vss: supply and device body connections.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C with a 1 pF capacitor from vout to vss. Vin begins at 0.5 V, rises to 2.5 V at 5.1 ns, falls to 0.5 V at 30.1 ns and rises to 2.5 V at 55.1 ns. Track initially (clk=3.3 V, clkb=0 V), hold from 20.1 to 45 ns and resume tracking at 45.1 ns. All transitions take 0.1 ns. Simulate to 70 ns with a 0.01 ns requested step. The four MOS widths are fixed to the upstream default values: 40, 80, 17.5 and 35 um; every channel length is 0.28 um. vss is the explicit form of the original global ground connection.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `adc_tgate_dum` and at most 10485760 bytes. Its functional bounding box must not exceed 160 by 160 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `high` | vout at 19 and 69 ns. | V | functional check | 2.48 … 2.52 | — |\n| `low` | vout at 54 ns, after tracking resumes with vin=0.5 V. | V | functional check | 0.48 … 0.52 | — |\n| `hold` | Maximum absolute vout-2.5 V over 21–44 ns, including the vin transition while the switch is open. | V | minimize / ratio | 0 … 3.3 | 0.02 |\n| `settling` | First vin rising 1.5 V crossing to vout reaching 2.48 V. | s | minimize / ratio | 0 … +∞ | 1e-15 |\n\nThe tracking checks define a 1% settling-accuracy task: 20 mV is 1% of\nthe declared 2 V input step. Both sampled tracking levels must meet that\naccuracy; the settling measurement uses the same high-level boundary.\nThis is an explicit sampled acquisition requirement, not a tolerance fitted\nto the reference layout. Hold error remains continuous quality, with q=(source_error+0.02 V)/\n(candidate_error+0.02 V), so reducing absolute error always improves quality.\nThe 20 mV floor uses the declared acquisition-accuracy scale and keeps\nnear-zero source error well-conditioned; it is not a hold-error pass threshold.\n\nArea reference: **702.46 um2**. 4 expanded device instances; sum of device/contact envelopes 411.5400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTrack/hold switches: acquisition 39.4%; hold fidelity 50.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `settling` | 0.393750000000 |\n| `hold` | 0.506250000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml","case_sha256":"f286c12fd475fce7956745d2e16ead5fac4babe3bcf335db0029bd3cbe4ba314","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md","netlist_path":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice","netlist_sha256":"24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd","license_path":"tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE"}
+{"id":"gf180mcuD.Chipathon2023_ADC.comparator","in_core":false,"title":"Dynamic Comparator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Compares two input voltages using a clocked regenerative decision.","source_url":"https://github.com/ishi-kai/Chipathon2023_ADC/tree/3dce439b2125a9d628e43be40c65cf8fce5d795c/gitefu/comp_20240331/comp_20240331.sch","status":"qualified","collection":"Chipathon2023_ADC","task_kind":"netlist_to_gds","problem":"# Dynamic Comparator Layout Task\n\n## Objective\n\nImplement `comp_20240331` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Clocked differential decisions for both signs of a 20 mV input difference at 1.65 V common mode, 50 MHz and 50 fF per output.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `VDD, CLK, VOUTP, VOUTN, VINP, VINN, VSS`.\nVDD/VSS: supply/return; CLK: clock; VINP/VINN: differential inputs; VOUTP/VOUTN: directional differential outputs.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C. The clock begins rising at 10 ns and repeats every 20 ns, with 0.1 ns rise/fall and 10 ns high time. Each output has 50 fF to ground. Evaluate polarity = -1 and +1 separately: VINP = 1.65 + polarity*0.01 V and VINN = 1.65 - polarity*0.01 V. Simulate to 100 ns with a 0.01 ns requested step.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `comp_20240331` and at most 10485760 bytes. Its functional bounding box must not exceed 200 by 100 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `decision` | polarity*(VOUTP-VOUTN) at 99 ns. | V | functional check | 2.97 … +∞ | — |\n| `delay` | Final clock rising 1.65 V crossing after 80 ns to the corresponding directional output crossing 2.97 V. | s | minimize / ratio | 0 … +∞ | — |\n| `supply` | Average power delivered by VDD over 20–100 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **301.49 um2**. 15 expanded device instances; sum of device/contact envelopes 164.1600 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nClocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `delay` | 0.710526315789 |\n| `supply` | 0.189473684211 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml","case_sha256":"38d81022f3034a87f5450f6d6c148a6aeb851c21ac5d4ab3f6ef3f6e3eeb5826","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/problem.md","netlist_path":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice","netlist_sha256":"0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d","license_path":"tasks/gf180mcuD/Chipathon2023_ADC/LICENSE"}
+{"id":"gf180mcuD.Jianxun-OTA.ota_5t","in_core":true,"title":"Five-Transistor OTA with Bias and Dummies","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies a differential input with a compact five-transistor OTA core and bias network.","source_url":"https://github.com/Jianxun/iic-osic-tools-project-template/tree/178a401d847ce7a602d0ce70a1ba90a15b5f9536/designs/libs/core_analog/ota_5t/ota_5t.spice","status":"qualified","collection":"Jianxun-OTA","task_kind":"netlist_to_gds","problem":"# Five-Transistor OTA with Bias and Dummies Layout Task\n\n## Objective\n\nImplement `ota_5t` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Small-signal differential gain and unity frequency at 1.65 V common mode, 10 uA bias and 1 pF load.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `vdd, out, in_p, in_n, i_bias, vss`.\nvdd/vss: supply/return; out: single-ended output; in_p/in_n: differential inputs; i_bias: current-bias input.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C, a 10 uA current from vdd into i_bias, input common mode 1.65 V and 1 pF from out to ground. The differential AC excitation is 1 V (in_p: +0.5 V; in_n: -0.5 V). Measure the DC output and supply power, then sweep 10 Hz to 1 GHz at 40 points/decade.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `ota_5t` and at most 10485760 bytes. Its functional bounding box must not exceed 320 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `gain` | 20 log10 of the single-ended differential voltage gain at 10 Hz. | dB | maximize / db20 | −∞ … +∞ | — |\n| `unity` | First falling 0 dB gain crossing in the declared AC sweep. | Hz | maximize / ratio | 0 … +∞ | — |\n| `output_bias` | DC operating-point voltage at out. | V | target / target | 0 … 3.3 | 3.3 |\n| `supply` | DC power delivered by the 3.3 V source, including the bias-current branch. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **510.1 um2**. 16 expanded device instances; sum of device/contact envelopes 291.8400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 36%; bandwidth 30%; operating points 6%; power 18%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain` | 0.360000000000 |\n| `unity` | 0.300000000000 |\n| `output_bias` | 0.060000000000 |\n| `supply` | 0.180000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml","case_sha256":"a1a3a8a82fbbaabf2bb6863d59a97ac3b653abe614f6bf611d3afaed9f8f3781","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md","netlist_path":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice","netlist_sha256":"fe6966f64eb3bc72880adca79dac070e0c0e2ea05cdc46c83f49616611d36fac","license_path":"tasks/gf180mcuD/Jianxun-OTA/LICENSE"}
+{"id":"gf180mcuD.analog-db.amp_004_folded_cascode","in_core":false,"title":"Externally Biased PMOS-Input Folded-Cascode OTA","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies differential inputs with an externally biased PMOS folded-cascode stage across three supply voltages.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_004_folded_cascode","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Externally Biased PMOS-Input Folded-Cascode OTA Layout Task\n\n## Objective\n\nImplement the fixed `amp_004_folded_cascode` circuit in GF180MCU D and submit self-contained GDS.\nFourteen MOS entries (17 instances after multiplicity expansion) form a PMOS-input folded-cascode OTA with a bias mirror and cascode branches. The two ideal internal voltage sources become explicit vb1/vb2 ports. Total MOS widths, lengths and multiplicities are retained; the maintained devices use single-finger geometry instead of the upstream nf settings. Source and extracted simulation both represent this maintained implementation.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vinn vinp vout vdd ibias vss vb1 vb2`.\nIn order, these are: Negative input, positive input, output, supply, PMOS reference-current sink, return, NMOS cascode bias, and PMOS cascode bias.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVSS = 0 V; VDD = 2.7, 3.0 and 3.3 V; a 20 uA sink from ibias to VSS; VB1 = 1.2 V and VB2 = 1.95 V; external 1 pF output load. VINP has DC 1.65 V and AC +0.5 V. A 1 TH output-to-VINN inductor closes DC feedback; a 1 F coupling capacitor injects AC -0.5 V at VINN. The open-loop transfer is V(vout)/(V(vinp)-V(vinn)). These large L/C elements are external measurement apparatus. At 2.7 V the reduced headroom lowers gain and shifts the DC operating point.\n\nAC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is\nV(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp)\nfor unit differential excitation; the OTA transfer is defined above.\n\n## Physical Requirements\n\nSubmit top cell `amp_004_folded_cascode` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 400 by 340 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThe case measures small-signal unity-crossing phase margin with the declared load. Startup, large-signal settling, other loads, mismatch, noise, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — |\n| `unity_hz` | First falling 0 dB crossing of open-loop transfer | Hz | maximize / ratio | 0 … +∞ | — |\n| `phase_margin` | 180 degrees plus unwrapped transfer phase at the unity crossing | deg | target / target | 0 … 180 | 180 |\n\nArea reference: **5150.02 um2**. 17 expanded device instances; sum of device/contact envelopes 3278.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_db` | 0.270000000000 |\n| `bandwidth_hz` | 0.112500000000 |\n| `unity_hz` | 0.112500000000 |\n| `phase_margin` | 0.225000000000 |\n| `bias_v` | 0.022500000000 |\n| `output_v` | 0.022500000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml","case_sha256":"93601b6cde701068f87a90c9a7042ecbb858146278ff4b26ee44c142f94e0f68","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice","netlist_sha256":"0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.amp_017_tan_clia","in_core":false,"title":"Tan CLIA Three-Stage Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with current inversion and physical R/C compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_017_tan_clia","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Tan CLIA Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_017_tan_clia` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded NMOS branches drive voutn/net050. XM70 and XM71/XM72 form the current-inversion path through net3/net5; XM61 and the DM_1-controlled XM73 bias this path. XM68/XM69 drive the output. The 889198 ohm resistor from net5 to net2, 0.61268 pF net2-to-vss capacitor and 1.07905 pF net8-to-vout capacitor all remain.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 512 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout net1`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net1`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nGF180MCU D, nominal TT/typical, 27 C, supply 1.8 V, input reference 0.3 V,\nexternal current sink 2.32803e-06 A to vss, and 10 pF output load. Use the fixed GF180 3.3 V device binding at its authored 1.8 V operating rail; round W/L to the 5 nm manufacturing grid.\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 20 us (100 ns rise/fall, 80 us high duration), and runs to 200 us with\n10 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 80–100 and 180–200 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_017_tan_clia`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nGF180 native standalone-block DRC includes FEOL, BEOL, connectivity, manufacturing grid, antenna and dummy fill, with chip-level density and seal-ring closure outside scope. Native MIM-B uses M4/M5 and 2 fF/um2; resistors use 1 kohm/square unsilicided poly. The model boundary excludes distributed substrate resistance. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.8 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 20–200 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.8 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=88555.19 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 2 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1000 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 7: Multistage compensation includes a resistively isolated capacitor and a current-inversion output-drive path.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed GF180MCU D resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml","case_sha256":"b61b6d19f1ef1fd31d784c357c32d4e4ea511820d47c06927ea369a1df462362","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl","netlist_sha256":"59a4d962ade70da8bbdc21dffc81adf077c84baa2057b100deaed0c5f34e7dc2","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.amp_018_telescopic_cascode","in_core":false,"title":"Tail-Referenced Telescopic Cascode Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies differential inputs with an NMOS telescopic cascode and tail-referenced bias across three capacitive loads.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_018_telescopic_cascode","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Tail-Referenced Telescopic Cascode Amplifier Layout Task\n\n## Objective\n\nImplement `amp_018_telescopic_cascode` in gf180mcuD and submit self-contained GDS. Ten MOS devices form an NMOS-input telescopic cascode amplifier. Fixed upstream W/L/m are retained, including the single finger of XM5. The two ideal internal sources become external bias connections: VDD minus gate_pc is 1.143 V, and casc_n minus tail is 0.917 V. Exposing tail preserves the second source's relative bias instead of replacing it with an absolute ground-referenced voltage.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is the authoritative physical circuit. The same netlist is used for source calibration. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `vdd vout vinp vinn ibias vss gate_pc casc_n tail`. In order: Supply, output, positive input, negative input, reference-current input, return, PMOS cascode bias, NMOS cascode bias, and accessible tail node.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical GF180 3.3 V MOS and high-resistance poly models, statistical variation disabled. The substrate is not a distributed silicon resistance network.\n\nVDD = 3.3 V; VSS = 0 V; a 20 uA current source from VDD into ibias. VINP is 1.65 V DC with AC amplitude +0.5 V; VINN has DC output feedback through a 1 TH inductor and AC -0.5 V through a 1 F coupling capacitor. These ideal measurement elements are external apparatus. Output loads are 1, 3 and 5 pF. AC uses 100 points/decade from 1 Hz to 1 GHz and transfer V(vout)/(V(vinp)-V(vinn)).\n\n## Physical Requirements\n\nTop cell `amp_018_telescopic_cascode`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, GF180 variant-D DRC including antenna, with chip-level density and seal-ring closure outside scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 140 by 100 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. The declared bias gives about 15 dB gain; this is not a high-gain OTA qualification. Large-signal settling, noise, mismatch, other biases and PVT are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output/control voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `tail_v` | DC V(tail) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD; telescopic also includes both external voltage-bias sources | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(differential transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `unity_hz` | First falling 0 dB crossing | Hz | maximize / ratio | 0 … +∞ | — |\n| `phase_margin` | 180 degrees plus unwrapped transfer phase at unity crossing | deg | target / target | 0 … 180 | 180 |\n\nArea reference: **544.15 um2**. 10 expanded device instances; sum of device/contact envelopes 312.9250 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_db` | 0.270000000000 |\n| `unity_hz` | 0.225000000000 |\n| `phase_margin` | 0.225000000000 |\n| `bias_v` | 0.015000000000 |\n| `output_v` | 0.015000000000 |\n| `tail_v` | 0.015000000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml","case_sha256":"c5b3dac4ccb6d500333d24ac98fc8304ea009082629b2e93fb0fa11e31fdceaf","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice","netlist_sha256":"6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.amp_019_ti_ldo_error","in_core":false,"title":"Externally Biased TI-Architecture Error Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies a differential error signal using external bias, level shifting and series Miller compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_019_ti_ldo_error","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Externally Biased TI-Architecture Error Amplifier Layout Task\n\n## Objective\n\nImplement `amp_019_ti_ldo_error` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. All twelve MOS remain, including the externally driven NMOS reference diode, four sinks, NMOS differential pair, level-shift branch and PMOS output stage. RND connects na to nd; all 500 kohm remains. Rz/Cc remain in series between nb and vout. No servo is inside the DUT. Four parallel native resistors implement 470 ohm; 32 parallel MIM units implement 25 pF. Native 6 V PMOS lengths become 0.55 um; other dimensions and multiplicities retain the fixed GF180 binding.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vdd vout vinp vinn ibias vss`. `vinp` is the non-inverting input and `vinn` the inverting input, verified by follower response. The ideal 1 mA source from vdd to ibias is external and included in supply power. The feedback wire connects vout to vinn externally.\n\n## Operating Conditions\n\n3.3 V supply, 1 mA external bias; common-mode inputs 1.4, 1.6 and 1.8 V with 10 pF output load, plus 1.6 V with 1 pF. Direct follower in DC, AC and transient. AC input is 1 V and the reported gain is **closed-loop follower transfer**, never open-loop gain or loop margin. The input rises 10 mV at 20 us with 10 ns edges and returns after 40 us; simulate through 100 us with maximum 10 ns steps. Start at the DC operating point. No extra output resistance, solver shunt, feedback isolation L/C, forced initial conditions or stability claim. Windows are 10–20, 50–60 and 90–100 us.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `amp_019_ti_ldo_error`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[5, 0], [11, 17], [11, 39], [12, 0], [13, 17], [21, 0], [22, 0], [22, 4], [24, 0], [24, 5], [30, 0], [30, 4], [31, 0], [32, 0], [33, 0], [34, 0], [34, 3], [34, 4], [34, 5], [35, 0], [36, 0], [36, 3], [36, 4], [36, 5], [37, 0], [38, 0], [40, 0], [41, 0], [42, 0], [42, 3], [42, 4], [42, 5], [46, 0], [46, 3], [46, 4], [46, 5], [49, 0], [53, 0], [53, 3], [53, 4], [53, 5], [55, 0], [62, 0], [75, 0], [80, 5], [81, 0], [81, 3], [81, 4], [81, 5], [82, 0], [86, 17], [88, 17], [96, 1], [100, 5], [100, 7], [100, 8], [108, 5], [110, 5], [110, 11], [110, 12], [110, 13], [110, 14], [110, 15], [110, 16], [111, 5], [112, 1], [115, 5], [116, 5], [117, 5], [117, 10], [118, 5], [119, 5], [122, 5], [123, 5], [124, 5], [125, 5], [127, 5], [128, 17], [137, 5], [151, 5], [152, 5], [153, 51], [166, 5], [167, 5], [173, 5], [178, 0], [183, 0], [184, 0], [185, 0], [204, 0], [210, 0], [220, 0], [226, 0], [227, 0], [241, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. The GF180 model boundary retains physical poly substrate and MIM geometry.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 6 reflects the complete two-stage compensated feedback circuit. It does not claim verified open-loop gain, phase margin, noise, PVT or settling time. Late variation is a finite-window observation. The bias sink ratios are geometric ratios, not promises of saturated current mirrors.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | DC direct-follower output | bias / target; scale 3.3 | lower=0; upper=3.3 |\n| `power_w` | W | Total 3.3 V supply power including external 1 mA bias | supply / ratio; scale 1e-12 | lower=0 |\n| `gain_1hz` | 1 | Closed-loop follower magnitude at 1 Hz | response / target; scale 1 | Finite measurement |\n| `gain_1mhz` | 1 | Closed-loop follower magnitude at 1 MHz | response / target; scale 1 | Finite measurement |\n| `tracking_error_v` | V | Mean absolute tracking error, 20–100 us | response / ratio; scale 0.001 | lower=0 |\n| `ripple_v` | V | Finite-window peak-to-peak output, 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `step_response_v` | V | Mean output 50–60 us minus 10–20 us | unscored / functional | lower=0 |\n| `kcl_a` | A | External DC KCL residual | diagnostic; unscored | Producer validity guard; see below |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **63700 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (58 units, sum 31829.640000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **6**.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `tracking_error_v` | 0.360000000000 |\n| `ripple_v` | 0.225000000000 |\n| `gain_1hz` | 0.090000000000 |\n| `gain_1mhz` | 0.090000000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml","case_sha256":"c661845add976c09b3d919b6bbf1ef9fa5cf495d38e52b5c83235f092d83c4ca","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl","netlist_sha256":"3af8b547c72e7e34d0f919ace84d1eafff32f9c4b7f1b6a0e60ca6d45bab8fcc","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.amp_032_ti_ldo_error_selfbias","in_core":false,"title":"Self-Biased LDO Error Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Amplifies an error signal with a self-biased two-stage core, level-shifted mirror and Miller compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_032_ti_ldo_error_selfbias","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Biased LDO Error Amplifier Layout Task\n\n## Objective\n\nImplement `amp_032_ti_ldo_error_selfbias` as a GF180MCU D layout. Eleven MOS devices form the fixed upstream two-stage amplifier, with a level-shifted PMOS mirror, its 500 kohm gate-rail tie, diode-connected self-bias and series Miller compensation. The direct common-source output stage is the revision present in the pinned netlist; the retired stacked stage is not used.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority. `materials/circuit.spice`\ncontains the corresponding native simulator wrappers; `materials/testbench.spice`\ndefines all measurements. Ordered ports: `vdd vout vinp vinn vss`.\n`vdd/vss` are supply/return, `vinp/vinn` are differential inputs, and `vout` is the output.\nNo external bias current is required. Preserve connectivity and total device dimensions;\nparallel equivalent fingers are permitted. Do not substitute a different amplifier.\n\n## Operating Conditions\n\nTypical native GF180 6 V MOS models, 3.3 V supply, 27 C, statistics disabled.\nInput common mode is 1.6 V. Both 1 pF and 10 pF output loads are evaluated.\nDC uses unity feedback. AC uses a 1 TH feedback inductor and 1 F input shunt\nfrom 1 Hz to 1 GHz, 100 points/decade. Transient replaces these fixture elements\nwith 1 pH and 1 aF: the input rises 10 mV at 1 us and falls at 3 us, each in\n10 ns. The simulation ends at 5 us, with a 1 ns requested step.\nThese ideal fixture elements are external test apparatus, outside the DUT.\n\n## Physical Requirements\n\nGDS database unit 0.001 um; maximum 10 MiB; top cell `amp_032_ti_ldo_error_selfbias`.\nNative standalone DRC includes geometry, connectivity, manufacturing grid,\ndummy fill and antenna rules; chip density and seal-ring closure are excluded.\nNative LVS must match devices, parameters and every named port. All device,\nwell, implant, contact, passive-marker and routing layers listed in the runtime\noutline form the functional bounding rectangle; text annotations are excluded.\nMaximum outline is 5000 by 1000 um. Labels belong on native Metal1 text.\n\nThe 6 V minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS.\nUpstream dimensions are rounded to 5 nm, with only subminimum lengths raised.\nPhysical passives use 1 kohm/square poly and MIM-B, 2 fF/um2, between M4/M5.\nLong resistors are series segmented; capacitors are parallel tiled. Nominal\nvalues are implemented by geometry; source and candidate use the same native\nprocess models. MOS diffusion areas/perimeters and interconnect parasitics are\ncandidate-derived. Magic extracts nominal coupling capacitance and distributed\nresistance using zero omission thresholds. Ideal well/substrate connections\nexclude distributed substrate noise; no inductance, RF/EM or statistical claim\nis made. Finite source and candidate observations must be available. Every declared\noperating point must satisfy its functional checks; incomplete evaluation cannot\nestablish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | bias | target |\n| `power_w` | DC supply power: -VDD*I(VDD) | W | supply | ratio |\n| `gain_db` | Open-loop magnitude at 10 Hz in dB | dB | response | db20 |\n| `unity_hz` | First falling unity-gain crossing | Hz | response | ratio |\n| `phase_margin` | 180 degrees plus unwrapped phase at unity crossing | deg | response | target |\n| `tracking_error_v` | Mean absolute unity-buffer tracking error over 1–5 us | V | response | ratio |\n| `step_response_v` | Mean output at 2–3 us minus mean output at 4–5 us; nonnegative sign-domain check (zero is allowed) | V | functional | unscored |\n\nDC output must remain between the rails, power and absolute tracking error must\nbe nonnegative, and the signed output-step observation must be nonnegative (zero is allowed). These\nbounds express physical domains and buffer function. Every required measurement\nmust be finite; failed or missing measurements are evaluation errors, not poor\nperformance. No upstream data-sheet target is an acceptance gate. Phase margin\nis measured and continuously compared, without importing an upstream threshold.\n\nEach quality observation is paired with an independent source simulation using\nthe identical deck, load, supply, temperature and models. `target` uses scale\n3.3 V for output and 180 degrees for phase; ratio floors are 1 pW for power\nand 1 mV for tracking error. These are normalization units, not tolerances.\n\n\nArea target: **19112.51 um2**. Device/contact envelopes sum to 12143.285500 um2,\nusing `(W+2)*(L+2)` per expanded MOS, resistor segment and capacitor tile\nin micrometers. The estimate adds 50% routing plus a 2 um outer margin:\n`ceil(100*(1.5*envelope_sum+8*sqrt(envelope_sum)+16))/100`.\nThis engineering anchor is independent of the witness footprint and is not a\nfoundry minimum. Coefficient **6** reflects a complete compensated two-stage\nloop with self-bias and load-dependent transient response.\n\n\n### Score weights\n\nSelf-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `tracking_error_v` | 0.360000000000 |\n| `phase_margin` | 0.225000000000 |\n| `gain_db` | 0.090000000000 |\n| `unity_hz` | 0.090000000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json` for the frozen task, reviewed PDK and harness.\nKLayout checks physical validity, Magic extracts the submitted layout and\nngspice performs measurements. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml","case_sha256":"8f8de97eaf47a1393e176354f75fd7929374b58a93bbee14337d8870179d55e7","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl","netlist_sha256":"9e9cb685378e09c43bf827a69c0189e83fb9ef47b6d96655c466e1bfa411b7d1","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.amp_033_ti_ldo_ref_selfbias","in_core":false,"title":"Self-Biased LDO Reference Amplifier","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Buffers a reference through a self-biased two-stage Miller amplifier under external unity feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_033_ti_ldo_ref_selfbias","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Biased LDO Reference Amplifier Layout Task\n\n## Objective\n\nImplement `amp_033_ti_ldo_ref_selfbias` as a GF180MCU D layout. Nine MOS devices form the fixed upstream two-stage Miller amplifier, with a matched PMOS mirror and diode-connected self-bias. External unity feedback tests the reference-buffer function; no ideal internal amplifier or bias servo is inserted.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority. `materials/circuit.spice`\ncontains the corresponding native simulator wrappers; `materials/testbench.spice`\ndefines all measurements. Ordered ports: `vdd vout vinp vinn vss`.\n`vdd/vss` are supply/return, `vinp/vinn` are differential inputs, and `vout` is the output.\nNo external bias current is required. Preserve connectivity and total device dimensions;\nparallel equivalent fingers are permitted. Do not substitute a different amplifier.\n\n## Operating Conditions\n\nTypical native GF180 6 V MOS models, 3.3 V supply, 27 C, statistics disabled.\nInput common mode is 0.8 V. Both 1 pF and 10 pF output loads are evaluated.\nDC uses unity feedback. AC uses a 1 TH feedback inductor and 1 F input shunt\nfrom 1 Hz to 1 GHz, 100 points/decade. Transient replaces these fixture elements\nwith 1 pH and 1 aF: the input rises 10 mV at 1 us and falls at 3 us, each in\n10 ns. The simulation ends at 5 us, with a 1 ns requested step.\nThese ideal fixture elements are external test apparatus, outside the DUT.\n\n## Physical Requirements\n\nGDS database unit 0.001 um; maximum 10 MiB; top cell `amp_033_ti_ldo_ref_selfbias`.\nNative standalone DRC includes geometry, connectivity, manufacturing grid,\ndummy fill and antenna rules; chip density and seal-ring closure are excluded.\nNative LVS must match devices, parameters and every named port. All device,\nwell, implant, contact, passive-marker and routing layers listed in the runtime\noutline form the functional bounding rectangle; text annotations are excluded.\nMaximum outline is 5000 by 1000 um. Labels belong on native Metal1 text.\n\nThe 6 V minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS.\nUpstream dimensions are rounded to 5 nm, with only subminimum lengths raised.\nPhysical passives use 1 kohm/square poly and MIM-B, 2 fF/um2, between M4/M5.\nLong resistors are series segmented; capacitors are parallel tiled. Nominal\nvalues are implemented by geometry; source and candidate use the same native\nprocess models. MOS diffusion areas/perimeters and interconnect parasitics are\ncandidate-derived. Magic extracts nominal coupling capacitance and distributed\nresistance using zero omission thresholds. Ideal well/substrate connections\nexclude distributed substrate noise; no inductance, RF/EM or statistical claim\nis made. Finite source and candidate observations must be available. Every declared\noperating point must satisfy its functional checks; incomplete evaluation cannot\nestablish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | bias | target |\n| `power_w` | DC supply power: -VDD*I(VDD) | W | supply | ratio |\n| `gain_db` | Open-loop magnitude at 10 Hz in dB | dB | response | db20 |\n| `unity_hz` | First falling unity-gain crossing | Hz | response | ratio |\n| `phase_margin` | 180 degrees plus unwrapped phase at unity crossing | deg | response | target |\n| `tracking_error_v` | Mean absolute unity-buffer tracking error over 1–5 us | V | response | ratio |\n| `step_response_v` | Mean output at 2–3 us minus mean output at 4–5 us; nonnegative sign-domain check (zero is allowed) | V | functional | unscored |\n\nDC output must remain between the rails, power and absolute tracking error must\nbe nonnegative, and the signed output-step observation must be nonnegative (zero is allowed). These\nbounds express physical domains and buffer function. Every required measurement\nmust be finite; failed or missing measurements are evaluation errors, not poor\nperformance. No upstream data-sheet target is an acceptance gate. Phase margin\nis measured and continuously compared, without importing an upstream threshold.\n\nEach quality observation is paired with an independent source simulation using\nthe identical deck, load, supply, temperature and models. `target` uses scale\n3.3 V for output and 180 degrees for phase; ratio floors are 1 pW for power\nand 1 mV for tracking error. These are normalization units, not tolerances.\n\n\nArea target: **6223.21 um2**. Device/contact envelopes sum to 3808.978200 um2,\nusing `(W+2)*(L+2)` per expanded MOS, resistor segment and capacitor tile\nin micrometers. The estimate adds 50% routing plus a 2 um outer margin:\n`ceil(100*(1.5*envelope_sum+8*sqrt(envelope_sum)+16))/100`.\nThis engineering anchor is independent of the witness footprint and is not a\nfoundry minimum. Coefficient **6** reflects a complete compensated two-stage\nloop with self-bias and load-dependent transient response.\n\n\n### Score weights\n\nSelf-biased Miller buffers: tracking 36%; phase margin 22.5%; gain and bandwidth 18%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `tracking_error_v` | 0.360000000000 |\n| `phase_margin` | 0.225000000000 |\n| `gain_db` | 0.090000000000 |\n| `unity_hz` | 0.090000000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json` for the frozen task, reviewed PDK and harness.\nKLayout checks physical validity, Magic extracts the submitted layout and\nngspice performs measurements. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml","case_sha256":"b94fe14867a4a6bf3d550499f65139d32a5ef878d957ed09c0b6f2a7cef169cf","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl","netlist_sha256":"9b965341e7687a517833fa3ffa030c708a3bcb2622a922f5edb74e959bbff646","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.cmfb_003_5t_nmos_input","in_core":false,"title":"Segmented-Resistor NMOS Common-Mode Controller","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Controls common-mode voltage using an NMOS-input core and segmented resistors.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_003_5t_nmos_input","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Segmented-Resistor NMOS Common-Mode Controller Layout Task\n\n## Objective\n\nImplement `cmfb_003_5t_nmos_input` in gf180mcuD and submit self-contained GDS. Seven MOS devices form an NMOS-input common-mode error amplifier and self-bias network. Each ideal 5 Mohm sense arm is implemented as twenty series GF180 ppolyf_u_1k segments, each 2 um wide and 500 um long: 5,000 squares per arm. The segmentation, substrate terminals and intermediate nodes are part of the maintained circuit. The independent witness uses compact rows connected by metal; it retains both complete resistance chains.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is the authoritative physical circuit. The same netlist is used for source calibration. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `vinp vinn vcmfb vref vdd vss`. In order: Positive sensed output, negative sensed output, control output, common-mode reference, supply, and return.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical GF180 3.3 V MOS and high-resistance poly models, statistical variation disabled. The substrate is not a distributed silicon resistance network.\n\nVDD = 3.3 V; VSS = 0 V; VREF = 1.65 V. The external first-order inverting plant has drive = 3.3 V - V(vcmfb), followed by 100 kohm and 100 nF to common mode. V(vinp/vinn) = plant output + disturbance +/- d, where d = 0, 0.1 and 0.2 V in separate conditions. Disturbance is 0 through 10 ms, +0.1 V at 10.01 ms through 30 ms, -0.1 V at 30.01 ms through 50 ms, and 0 at 50.01 ms through 70 ms. A 10 pF external capacitor loads vcmfb. Transient output/max step is 10 us. This plant is test apparatus, not an internal ideal servo or a claimed transistor amplifier. Recovery windows are 25–29 ms and 45–49 ms for the positive/negative disturbances; error is measured at the average sensed inputs against VREF. Controller power excludes the external plant.\n\n## Physical Requirements\n\nTop cell `cmfb_003_5t_nmos_input`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, GF180 variant-D DRC including antenna, with chip-level density and seal-ring closure outside scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 1100 by 280 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. Qualification covers recovery with this specified external plant, not stability with arbitrary amplifiers. The long physical sense chains retain candidate-derived parasitics. Startup, mismatch, noise, PVT and a complete differential amplifier are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output/control voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `error_v` | Absolute DC sensed common-mode minus VREF | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `recovery_up_v` | Maximum absolute recovered error over the upward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `recovery_down_v` | Maximum absolute recovered error over the downward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `recovery_zero_v` | Maximum absolute sensed common-mode minus VREF over 65–69 ms | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `peak_error_v` | Maximum absolute sensed common-mode minus VREF over 10–70 ms | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the complete transient | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **122380.96 um2**. 47 expanded device instances; sum of device/contact envelopes 80826.5000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCommon-mode sensing/controllers: recovery and error 62.3%; output bias 6.92%; power 20.8%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `error_v` | 0.124615384617 |\n| `peak_error_v` | 0.124615384615 |\n| `recovery_down_v` | 0.124615384615 |\n| `recovery_up_v` | 0.124615384615 |\n| `recovery_zero_v` | 0.124615384615 |\n| `output_v` | 0.069230769231 |\n| `mean_power_w` | 0.103846153846 |\n| `power_w` | 0.103846153846 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml","case_sha256":"ac03814e40b31b14631ab6f61e76846a0280f9943c6a377718379926b3d500b8","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice","netlist_sha256":"ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.cmp_001_hyst_diffpair","in_core":false,"title":"Resistive-Feedback Hysteretic Comparator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Produces distinct rising and falling switching thresholds through resistive hysteresis.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_001_hyst_diffpair","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Resistive-Feedback Hysteretic Comparator Layout Task\n\n## Objective\n\nImplement the fixed `cmp_001_hyst_diffpair` circuit in GF180MCU D and submit self-contained GDS.\nA differential input stage, resistive positive feedback and three output inverters form a hysteretic comparator. Twelve MOS entries expand to 28 physical instances. The physical ppolyf_u_1k resistors are width 2 um: two 600 um feedback devices (300 squares) and one 12 um tail device (6 squares). MOS sizes and multiplicities are retained; ideal resistors become substrate-connected process devices.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd vout vinp vinn vss`.\nIn order, these are: Supply, digital output, swept positive input, fixed negative input, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVDD = 3.3 V, VSS = 0 V, VINN = 1.65 V. VINP stays at 1.45 V through 0.1 ms, ramps to 1.85 V at 1.1 ms, holds through 1.2 ms, ramps back to 1.45 V at 2.2 ms, then holds through 2.3 ms. Each ramp magnitude is 0.4 V/ms. Evaluate external loads of 1, 5 and 10 pF separately with a 0.2 us transient output step. The transient starts from its DC operating point.\n\n## Physical Requirements\n\nSubmit top cell `cmp_001_hyst_diffpair` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 1300 by 200 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThresholds include this finite ramp rate and output load. Offset is intentional and is not zero-centered about VINN. Metastability, fast decision delay, startup, noise, statistical offset, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `rising_input` | Interpolated VINP at the first rising VOUT = 1.65 V crossing | V | target / target | 0 … 3.3 | 3.3 |\n| `falling_input` | Interpolated VINP at the first falling VOUT = 1.65 V crossing | V | target / target | 0 … 3.3 | 3.3 |\n| `hysteresis_v` | Rising-input threshold minus falling-input threshold | V | target / target | 0 … 3.3 | 3.3 |\n| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the full 0–2.3 ms transient | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `low_v` | Maximum VOUT over 0.02–0.08 ms | V | functional check | 0 … 0.1 | — |\n| `high_v` | Minimum VOUT over 1.12–1.18 ms | V | functional check | 3.2 … 3.31 | — |\n\nArea reference: **8386.58 um2**. 31 expanded device instances; sum of device/contact envelopes 5392.5600 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nHysteretic comparator: switching thresholds 49.5%; hysteresis 27%; supply power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `falling_input` | 0.247500000000 |\n| `rising_input` | 0.247500000000 |\n| `hysteresis_v` | 0.270000000000 |\n| `mean_power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml","case_sha256":"bc8505f1bb608ddd79d74f941a65dc7fbf782cfd0ae168173a1b6a8f89d65a84","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice","netlist_sha256":"cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.cmp_002_strongarm","in_core":true,"title":"StrongARM Dynamic Comparator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Makes clocked differential decisions with a StrongARM regenerative latch.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_002_strongarm","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# StrongARM Dynamic Comparator Layout Task\n\n## Objective\n\nImplement `cmp_002_strongarm` as a GF180MCU D layout. Fifteen upstream MOS instances implement the clocked StrongARM latch: differential input pair, clocked tail, cross-coupled regenerative devices, four precharge devices and two output inverters. The input pair multiplicities expand the physical circuit to seventeen devices. The maintained GF180 3.3 V binding uses the fixed sizing defaults and authored ties from the pinned accession.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice`\ncontains matching native simulator wrappers. `materials/testbench.spice` defines\nall measurements. Ordered ports: `vdd voutp voutn vinp vinn clk vss`.\n\n`vdd/vss`: supply and return; `vinp/vinn`: differential inputs; `clk`: evaluate high, precharge low; `voutp/voutn`: buffered differential outputs. Positive input difference produces positive output difference. Supply, clock, input drivers and output loads are external apparatus. No offset-trim variant or proprietary process deck is included.\n\n## Operating Conditions\n\nTypical GF180 3.3 V MOS models at 3.3 V supply and 27 C, statistics disabled. Differential input is +20 or -20 mV at common modes 1.2 and 1.65 V, all four combinations. Each output has a 50 fF load. The 50 MHz clock first rises at 10 ns, uses 100 ps edges and 10 ns pulse width. Simulate to 100 ns at 10 ps requested steps; timing uses the fifth evaluation edge near 90 ns.\n\n## Physical Requirements\n\nGDS database unit 0.001 um, maximum 10 MiB, top cell `cmp_002_strongarm`.\nNative standalone DRC covers geometry, connectivity, manufacturing grid, dummy\nfill and antenna; chip-level density and seal-ring closure are excluded.\nLVS must match all devices, parameters and named ports. Metal1 labels identify\nports. The functional bounding rectangle includes the device, well, implant,\ncontact, passive and complete routing layers enumerated in the runtime outline;\ntext annotations are excluded. Maximum outline is 5000 by 1000 um.\n\nKeep the 3.3 V models, 0.28 um channel length, fixed widths and multiplicities. Parallel equivalent fingers are permitted. All MOS dimensions lie on the native 5 nm construction grid. Body/well connections are explicit, with native guard-ring/tap geometry. The IHP binding has the same topology but different process sizing; it is not mixed into this GF180 task.\n\nCandidate-derived native Magic coupling capacitance and distributed wire\nresistance feed post-layout simulation, with zero omission thresholds.\nPhysical MOS diffusion areas/perimeters come from the layout. Substrate/well\nconnections are ideal: distributed substrate resistance/noise and inductance\nare not represented. Four nominal input-polarity/common-mode combinations, reset, decision delay/slew and average supply power. Coefficient 6 reflects regenerative decisions with clocked reset and buffered loads. Offset distribution, metastability statistics, noise, PVT and RF/EM are outside this declared scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `delay_s` | Clock 1.65 V crossing to signed output difference 1.65 V, fifth rising edge | s | response | ratio |\n| `slew_s` | Signed differential output rise from 0.33 to 2.97 V, fifth decision | s | response | ratio |\n| `power_w` | Mean supply power over 20–100 ns | W | supply | ratio |\n| `decision_v` | Input-polarity-adjusted output difference at 99 ns | V | bias | target |\n| `reset_p_v` | Positive output at 89 ns in precharge | V | functional | unscored |\n| `reset_n_v` | Negative output at 89 ns in precharge | V | functional | unscored |\n\nSigned decision must be 1.65–3.3 V; both reset outputs must be 0–1.65 V. Half-supply separates the required resolved/reset logic states, independent of any upstream speed target. Delay, slew and mean supply power must be nonnegative. Timing has no hard upper bound beyond the declared observation window; a missing crossing is an invalid measurement.\nEvery condition must complete; missing, nonfinite or wrong-unit observations\nproduce an evaluation error. Upstream advertised performance is not a\nqualification requirement.\n\nScored observations pair with independent source jobs using the identical\nstimuli, parameters, models and backend. Target scales are 3.3 V; ratio floors\nuse 1 pW for power. These are normalization units, not allowed degradation.\nDelay/slew ratios have no floor.\n\nArea anchor **490.86 um2** uses a 234.840000 um2 sum of expanded\n`(W+2)*(L+2)` device/contact envelopes, a 50% routing allowance and 2 um outer\nmargin: `ceil(100*(1.5*sum+8*sqrt(sum)+16))/100`. It is independent of witness\narea and is an engineering estimate, not a foundry minimum. Coefficient **6**\nis independent of this score.\n\n\n### Score weights\n\nClocked comparators: decision delay 61.4%; output transition 8.18%; decision amplitude 4.09%; supply power 16.4%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `delay_s` | 0.613636363637 |\n| `slew_s` | 0.081818181818 |\n| `decision_v` | 0.040909090909 |\n| `power_w` | 0.163636363636 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRead `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. KLayout performs physical checks, Magic extracts the\ncandidate, and ngspice measures it. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit using\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml","case_sha256":"2a2e079b46db026858622975af955aefaf7f3e134282079fc257261a30befb62","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl","netlist_sha256":"5b80e3a40ab19415481d51b8e6b4e4bcf45c4517ccc5071aa1b342038c94e14c","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.dp_001_resistive_load","in_core":false,"title":"Resistively Loaded Differential Pair","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Produces differential gain with resistive loads and a fixed input pair.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/dp_001_resistive_load","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Resistively Loaded Differential Pair Layout Task\n\n## Objective\n\nImplement the fixed `dp_001_resistive_load` circuit in GF180MCU D and submit self-contained GDS.\nFour NMOS devices form a differential input pair and tail-current mirror. Two physical GF180 ppolyf_u_1k loads each have width 2 um and length 44 um (22 squares, nominally 22 kohm). MOS dimensions and the resistor ratio follow the fixed binding; the ideal source resistors become process devices with substrate terminals at VSS.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd voutp voutn vinp vinn ibias vss`.\nIn order, these are: Supply, output on the vinp branch, output on the vinn branch, positive input, negative input, NMOS reference-current input, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVDD = 3.3 V, VSS = 0 V; 20 uA from VDD into ibias; input common mode = 1.2, 1.65 and 2.1 V; external 1 pF on each output. The input differential signal is split +0.5/-0.5 around common mode. AC differential amplitude is 1 V. DC transfer sweeps differential input from -10.1 to +10.1 mV in 0.1 mV increments; requirements use only -10 to +10 mV. Output differential voltage is V(voutn)-V(voutp).\n\nAC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is\nV(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp)\nfor unit differential excitation; the OTA transfer is defined above.\n\n## Physical Requirements\n\nSubmit top cell `dp_001_resistive_load` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 160 by 160 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThe output has a high common-mode level; it is not a rail-to-rail amplifier. Transient settling, mismatch, noise, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage; average of both outputs for the differential pair | V | target / target | 0 … 3.3 | 3.3 |\n| `imbalance_v` | Absolute DC difference between the two outputs | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — |\n| `linearity_v` | Maximum absolute differential-output deviation from the line joining the -10/+10 mV samples | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `slope` | Differential-output endpoint difference divided by 20 mV | V/V | target / target | −∞ … +∞ | 5 |\n\nArea reference: **925.98 um2**. 6 expanded device instances; sum of device/contact envelopes 552.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 38.6%; bandwidth 11.6%; balance and linearity 19.3%; operating points 3.86%; power 11.6%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `gain_db` | 0.193181818182 |\n| `slope` | 0.193181818182 |\n| `bandwidth_hz` | 0.115909090909 |\n| `imbalance_v` | 0.096590909091 |\n| `linearity_v` | 0.096590909091 |\n| `bias_v` | 0.019318181818 |\n| `output_v` | 0.019318181818 |\n| `power_w` | 0.115909090909 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml","case_sha256":"3731b97781f49826538972a11873f565a6888789bb4c0710206cd90234436ec7","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice","netlist_sha256":"15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.gs_001_cascode_cs","in_core":false,"title":"Self-Biased Cascode Common-Source Gain Stage","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Provides voltage gain through a self-biased cascode common-source stage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/gs_001_cascode_cs","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Biased Cascode Common-Source Gain Stage Layout Task\n\n## Objective\n\nImplement the fixed `gs_001_cascode_cs` circuit in GF180MCU D and submit self-contained GDS.\nNine MOS devices form a cascode common-source stage with PMOS and NMOS bias ladders. An external 20 uA sink biases the PMOS ladder. Total widths, lengths and multiplicities follow the fixed GF180 binding. Physical body contacts and an independently constructed reference complete the circuit.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd vout vin ibias vss`.\nIn order, these are: Supply, output, signal input, PMOS reference-current sink, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVSS = 0 V; VDD = 2.7, 3.0 and 3.3 V; external 20 uA sink from ibias to VSS; external 1 pF output load. A 1 TH external inductor connects output to input for the DC trip-point solve. A 1 F external coupling capacitor injects a unit AC input through acin while isolating the DC fixture. This measures open-loop small-signal gain at each self-biased trip point; it does not prescribe a fixed DC input voltage.\n\nAC uses 100 points per decade from 1 Hz to 1 GHz. Gain-stage transfer is\nV(vout) for unit AC injection; differential-pair transfer is V(voutn)-V(voutp)\nfor unit differential excitation; the OTA transfer is defined above.\n\n## Physical Requirements\n\nSubmit top cell `gs_001_cascode_cs` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 220 by 120 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nTransient settling, fixed-input bias robustness, noise, mismatch, PVT and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_db` | 20 log10(abs(transfer)) at 10 Hz | dB | maximize / db20 | −∞ … +∞ | — |\n| `bandwidth_hz` | First frequency where transfer gain falls 3 dB below its 10 Hz value | Hz | maximize / ratio | 0 … +∞ | — |\n\nArea reference: **394.4 um2**. 9 expanded device instances; sum of device/contact envelopes 220.6500 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 50%; bandwidth 15%; operating points 5%; power 15%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `gain_db` | 0.500000000000 |\n| `bandwidth_hz` | 0.150000000000 |\n| `bias_v` | 0.025000000000 |\n| `output_v` | 0.025000000000 |\n| `power_w` | 0.150000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml","case_sha256":"bab2233575478f0fcbebc4d4993224829c772207aa1cbba15eb1dcdb6d6d31d6","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice","netlist_sha256":"59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.ldo_002_analoggym_folded_cascode","in_core":false,"title":"Folded-Cascode LDO","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_002_analoggym_folded_cascode","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Folded-Cascode LDO Layout Task\n\n## Objective\n\nImplement `ldo_002_analoggym_folded_cascode` as a GDS layout preserving the complete declared circuit. Nine-MOS folded-cascode error amplifier and a PMOS pass array, with direct output feedback, series RZ/CC and the physical minimum-load bleed. The fixed GF180 6 V binding expands to 259 MOS, three 2 fF/um2 MIM units, one nulling resistor and two series bleed segments. VB1, VB2 and VREF remain external sources; the original 0 V VLP measurement marker becomes a wire.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/startup.spice`: startup observations.\n- `materials/regulation.spice`: regulation observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vdd vout vss vb1 vb2 vref`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\nNominal supply 2.0 V, external reference 1.8 V, VB1=1.0 V and VB2=0.025 V; 27 C, typical GF180 models with statistical variation disabled. Native 6 V DRC requires NMOS L>=0.70 um and PMOS L>=0.55 um; only undersized lengths are increased to those physical minima. All default widths and the 250-fold 10 um pass-device multiplier are retained. R_bleed is 100 kohm inside the physical DUT and consumes Vout^2/R power; external 1/2 mA load currents are additional, not replacements. CC=2 pF and RZ=3 kohm retain their original connections. External output capacitance is 1 nF with 0.1 ohm series ESR. Evaluate no disturbance, 1-to-2 mA load pulse, and +0.1 V input pulse, plus independent DC points at nominal+0.1 V/1 mA and nominal/2 mA. Pulses start at 100 us, have 1 us edges and 100 us high width; restoration finishes at 202 us. Observe 0–400 us with 10 ns maximum step; pre-step/high/recovery windows are 80–100/180–200/380–400 us. Supply rejection is measured at 1 kHz from a 1 V AC supply input (100 samples/decade, 1 Hz–100 MHz). Ascending DC sweeps cover nominal supply to nominal+0.1 V in 10 mV increments at 1 mA and 1–2 mA load in 0.1 mA increments at nominal supply; adjustment metrics are absolute endpoint slopes. These are finite ranges, not dropout measurements. Startup ramps VDD from zero to nominal in 10 us with fixed external references and a resistive 1 mA nominal load (target voltage/1 mA); it uses the ordinary initial DC solution, no UIC or forced initial output, and observes through 400 us. Startup extrema and late-window output/ripple are diagnostics. No dropout, loop gain or phase margin is claimed. Source and candidate use identical decks and parameters; no numerical shunt is used.\n\n## Physical Requirements\n\nGF180MCU D native standalone-block FEOL/BEOL, connectivity, grid, dummy and antenna rules; chip density/seal-ring rules are outside this block boundary. Named-port LVS and candidate-derived distributed Magic RC are required. Functional area includes active/poly, passives and all routing metal/vias. Capacitor substrate and resistor terminal models follow the frozen PDK profile. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 20000 by 2000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_v | V | DC output | bias; target (scale 1.8) |\n| regulation_error_v | V | Absolute DC setpoint error | response; ratio (scale 0.001) |\n| power_w | W | Total input rail DC power, including physical bleed/divider and external current bias | supply; ratio (scale 1e-12) |\n| psrr_db | dB | Input supply rejection at 1 kHz | response; db20 |\n| quiet_ripple_v | V | Peak-to-peak pre-perturbation output 80–100 us | response; ratio (scale 0.001) |\n| recovery_ripple_v | V | Peak-to-peak recovered output 380–400 us | response; ratio (scale 0.001) |\n| excursion_v | V | Full output range 100–400 us | response; ratio (scale 0.001) |\n| late_error_v | V | Mean absolute setpoint error 380–400 us | response; ratio (scale 0.001) |\n| mean_power_w | W | Mean input rail power 0–400 us | supply; ratio (scale 1e-12) |\n| quiet_v | V | Finite-window quiet_v | diagnostic; unscored |\n| high_v | V | Finite-window high_v | diagnostic; unscored |\n| recovery_v | V | Finite-window recovery_v | diagnostic; unscored |\n| startup_final_v | V | 10 us input ramp with resistive load: startup_final_v | diagnostic; unscored |\n| startup_ripple_v | V | 10 us input ramp with resistive load: startup_ripple_v | diagnostic; unscored |\n| startup_min_v | V | 10 us input ramp with resistive load: startup_min_v | diagnostic; unscored |\n| startup_max_v | V | 10 us input ramp with resistive load: startup_max_v | diagnostic; unscored |\n| line_reg_v_per_v | V/V | Absolute ascending supply-sweep endpoint slope, nominal to nominal + 0.1 V, 1 mA load | response; ratio (scale 0.001) |\n| load_reg_ohm | ohm | Absolute ascending load-sweep endpoint slope, 1 to 2 mA, nominal supply | response; ratio (scale 1) |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 29211.12 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. For ordinary GF180 resistors this envelope conservatively uses the sheet-only length before contact correction; the explicit parallel 1-ohm bank uses its native dimensions. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 7 covers regulation, frequency response and recovery across loads. The provenance chain distinguishes the Apache-2.0 sky130_ldo_rl netlist from the BSD-3-Clause AnalogGym sizing/testbench; the actual circuit is the pinned MacAnalog GF180 binding, not another reference implementation.\n\n\n### Score weights\n\nGF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_reg_v_per_v` | 0.075000000000 |\n| `load_reg_ohm` | 0.075000000000 |\n| `output_v` | 0.075000000000 |\n| `regulation_error_v` | 0.075000000000 |\n| `excursion_v` | 0.149999999999 |\n| `late_error_v` | 0.150000000000 |\n| `psrr_db` | 0.066666666667 |\n| `quiet_ripple_v` | 0.066666666667 |\n| `recovery_ripple_v` | 0.066666666667 |\n| `mean_power_w` | 0.050000000000 |\n| `power_w` | 0.050000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `ldo_002_analoggym_folded_cascode`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml","case_sha256":"119e94e34c41cc595db48ab20b807dec4a9cbc7d055d5c285617970609dd0bd4","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl","netlist_sha256":"7463ac0a1cc09ec1f522693a4e4e03b348a693a698cdfb71cade504ca6ff4681","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.ldo_003_analoggym_simple","in_core":false,"title":"Simple Unity-Feedback LDO","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_003_analoggym_simple","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Simple Unity-Feedback LDO Layout Task\n\n## Objective\n\nImplement `ldo_003_analoggym_simple` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. A five-transistor NMOS-input error amplifier drives the PMOS pass device, with direct output feedback, the complete 3 kohm/1 pF series compensation and physical 100 kohm bleed. The pass transistor expands to 360 parallel units; the complete core has 365 MOS. GF180 6 V NMOS lengths obey the native 0.70 um minimum and PMOS lengths the 0.55 um minimum. The external bias remains 1.2 V and reference 1.8 V from the fixed binding.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/startup.spice`, `materials/sweep.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vdd vout vss vb vref`. VB and VREF are external ideal sources; the upstream zero-volt VLP feedback marker becomes a physical wire. The bleed is inside the DUT and counted in its input power, in addition to the explicitly stated fixture load. At 1.8 V it draws approximately 18 uA. The independent source baseline contains the same physical bleed, compensation and process adaptations.\n\n## Operating Conditions\n\nTT, 27 C. Main runs use 2.0 V supply and 1 mA external load, independently applying either no disturbance, a +0.1 V line step, or a +4 mA load step. A separate quiet condition uses 2.1 V/5 mA. Edges are 100 ns, disturbances start at 20 us and last 40 us. Output load is 50 pF behind 0.1 ohm ESR. Transient maximum step 2 ns, duration 100 us, initialized from DC. Upward DC supply sweep: 1.9–2.2 V in 5 mV steps at 1 mA; report the 2.0–2.1 V endpoint slope. Upward load sweep: 1–5 mA in 0.1 mA steps at 2.0 V. PSRR is -20 log10 of output response to a unit AC supply at 1 kHz, reference/bias AC grounded. Startup separately ramps supply/reference/bias together from zero over 10 us into a 1.8 kohm external resistive load; no negative-voltage ideal current load is applied during startup. No solver shunt, isolation L/C or imposed output state.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `ldo_003_analoggym_simple`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 20000/2000 um. The complete functional layer set is `[[5, 0], [11, 17], [11, 39], [12, 0], [13, 17], [21, 0], [22, 0], [22, 4], [24, 0], [24, 5], [30, 0], [30, 4], [31, 0], [32, 0], [33, 0], [34, 0], [34, 3], [34, 4], [34, 5], [35, 0], [36, 0], [36, 3], [36, 4], [36, 5], [37, 0], [38, 0], [40, 0], [41, 0], [42, 0], [42, 3], [42, 4], [42, 5], [46, 0], [46, 3], [46, 4], [46, 5], [49, 0], [53, 0], [53, 3], [53, 4], [53, 5], [55, 0], [62, 0], [75, 0], [80, 5], [81, 0], [81, 3], [81, 4], [81, 5], [82, 0], [86, 17], [88, 17], [96, 1], [100, 5], [100, 7], [100, 8], [108, 5], [110, 5], [110, 11], [110, 12], [110, 13], [110, 14], [110, 15], [110, 16], [111, 5], [112, 1], [115, 5], [116, 5], [117, 5], [117, 10], [118, 5], [119, 5], [122, 5], [123, 5], [124, 5], [125, 5], [127, 5], [128, 17], [137, 5], [151, 5], [152, 5], [153, 51], [166, 5], [167, 5], [173, 5], [178, 0], [183, 0], [184, 0], [185, 0], [204, 0], [210, 0], [220, 0], [226, 0], [227, 0], [241, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. The GF180 model boundary retains physical poly substrate and MIM geometry.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 7 reflects compensated regulation, line/load recovery and coordinated startup. No dropout number, loop margin, unlimited load range, PVT or product specification is claimed. Regulation slopes describe the declared finite intervals. Final error/ripple describe 90–100 us, not a proof of asymptotic settling. Input power includes the bleed, delivered load and bias/reference source contributions.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | DC output | bias / target; scale 1.8 | lower=0; upper=2.1 |\n| `power_w` | W | DC rail/reference/bias input power including bleed | supply / ratio; scale 1e-12 | lower=0 |\n| `regulation_error_v` | V | Absolute DC output error relative to 1.8 V | response / ratio; scale 0.001 | lower=0 |\n| `psrr_db` | dB | Supply rejection at 1 kHz | response / db20 | Finite measurement |\n| `quiet_ripple_v` | V | Output variation 10–20 us | response / ratio; scale 0.001 | lower=0 |\n| `recovery_ripple_v` | V | Output variation 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `excursion_v` | V | Output excursion 20–100 us | response / ratio; scale 0.001 | lower=0 |\n| `late_error_v` | V | Mean absolute output error 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `kcl_a` | A | External DC KCL residual | diagnostic; unscored | Producer validity guard; see below |\n| `startup_error_v` | V | Mean final startup error, 90–100 us, 10 us coordinated source ramps | response / ratio; scale 0.001 | lower=0 |\n| `startup_ripple_v` | V | Final startup variation, 90–100 us | response / ratio; scale 0.001 | lower=0 |\n| `line_reg_v_per_v` | V/V | Absolute endpoint slope, upward 2.0–2.1 V at 1 mA | response / ratio; scale 0.001 | lower=0 |\n| `load_reg_ohm` | ohm | Absolute endpoint slope, upward 1–5 mA at 2.0 V | response / ratio; scale 0.01 | lower=0 |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **169100 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (370 units, sum 84512.210000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **7**.\n\n\n### Score weights\n\nGF180 line/load regulators: regulation 25.7%; load and line recovery 25.7%; ripple and rejection 17.1%; startup 12.9%; power 8.57%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_reg_v_per_v` | 0.064285714286 |\n| `load_reg_ohm` | 0.064285714286 |\n| `output_v` | 0.064285714286 |\n| `regulation_error_v` | 0.064285714286 |\n| `excursion_v` | 0.128571428570 |\n| `late_error_v` | 0.128571428571 |\n| `psrr_db` | 0.057142857143 |\n| `quiet_ripple_v` | 0.057142857143 |\n| `recovery_ripple_v` | 0.057142857143 |\n| `startup_error_v` | 0.064285714286 |\n| `startup_ripple_v` | 0.064285714286 |\n| `power_w` | 0.085714285714 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml","case_sha256":"74cdf0ae82fb0e29a765b85696f96cd241b2ef1764589d0c10c2bfae03bb5690","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl","netlist_sha256":"b3ed893165850ba59c078460a0c50ca3d808d92aeef5f73d166600b54f2cc176","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.ldo_004_basic_pmos","in_core":true,"title":"Externally Biased 1.8 V PMOS Regulator Core","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_004_basic_pmos","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Externally Biased 1.8 V PMOS Regulator Core Layout Task\n\n## Objective\n\nImplement the fixed `ldo_004_basic_pmos` regulator core in GF180MCU D and submit\nself-contained GDS. The circuit contains an error amplifier, a PMOS pass array\nand a physical feedback divider. Reference and tail-current generation are\nexternal to this core.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration.\n`materials/testbench.spice`, `materials/transient.spice` and\n`materials/dropout.spice` define the DC/AC, load-step and dropout measurements.\nThe ordered ports are `vdd vout vref ibias vss`: input supply, regulated output,\nreference-voltage input, error-amplifier tail node, and return. An external\n200 uA sink connects `ibias` to VSS; this is not a voltage-bias input.\n\nRetain the two NMOS input devices at W/L = 46/0.5 um, two PMOS mirror devices\nat 50/0.5 um, and the PMOS pass device at 10/0.3 um with multiplicity 100.\nEach feedback resistor is `ppolyf_u_1k`, width 2 um and length 200 um, giving\n100 squares of nominal 1 kohm/square poly. Preserve connectivity, dimensions\nand body connections. Placement, routing and electrically equivalent device\nsplitting/source-drain interchange are allowed only as accepted by the declared\nLVS checks. Provide physical well/substrate contacts to the declared rails.\nNo statistical matching or common-centroid constraint is scored.\n\n## Operating Conditions\n\nUse typical 3.3 V MOS and poly-resistor models at 27 C, with statistical\nvariation disabled, VSS = 0 V, external VREF = 0.9 V and a 200 uA tail sink.\nThe external output capacitor is an ideal 1 uF, without added ESR. All nine\ncombinations of VDD = 2.2, 2.7, 3.3 V and load = 0.1, 1, 5 mA are required.\nDC measurements follow the operating-point solve. AC uses 60 points per decade\nfrom 1 Hz to 100 MHz. Supply rejection drives VDD with 1 V AC and zero AC load;\noutput impedance drives the load sink with 1 A AC and zero AC supply.\n\nAt each of the three supplies, the transient starts from the DC operating point\nat 0.1 mA load. Load rises to 5 mA between 1 and 1.0001 ms, then falls to 0.1 mA\nbetween 2 and 2.0001 ms. Run to 3 ms with a 200 ns output step. Evaluate peak\nabsolute output error relative to 1.8 V over 0.9 to 3 ms, high-load settled error\nover 1.2 to 1.9 ms, low-load settled error over 2.2 to 3 ms, and minimum tail\nvoltage over 0.9 to 3 ms. The recovery windows start 200 us after each load-step onset. Their errors\nare continuous quality metrics with no upper acceptance bound; they do not\nestablish a recovery-time limit.\n\nThe separate dropout sweep uses 5 mA load and sweeps VDD from 1.6 to 2.4 V\nin 5 mV steps. Dropout is the supply voltage at the first rising crossing of\nVOUT = 1.75 V, minus 1.75 V, using interpolated crossing measurement.\nAll ideal supplies, sinks and the output capacitor are testbench apparatus.\n\n## Physical Requirements\n\nSubmit top cell `ldo_004_basic_pmos` with all five named electrical ports,\nresolved hierarchy and a maximum file size of 10 MiB. Artifact, GF180 variant-D\nDRC including antenna checks, strict named-port LVS and geometry must pass.\nThere are no DRC waivers. Chip-level density and seal-ring closure are outside\nthe standalone-block check scope.\n\nThe functional bounding box must fit within 800 by 400 um. Area includes all\nprocess device and routing drawing layers listed in the runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation text and pin-purpose shapes are excluded; functional routing must\nuse drawing layers.\n\nThe judge extracts distributed interconnect RC from the submitted GDS and uses\nthat extracted DUT in every simulation. MOS and physical resistor geometry are\ncandidate-derived. The model boundary retains external body connections but\ndoes not include a distributed silicon substrate network. Qualification covers\nnominal DC, AC supply rejection/output impedance and these load steps; it does\nnot establish full loop phase margin, startup, PVT, statistical mismatch, noise,\nEM/current-density limits, thermal behavior or fabrication signoff.\n\n## Electrical Requirements and Scoring\n\nEvery required observation must be finite and satisfy its inclusive band;\naggregation cannot hide a failing operating point. A missing dropout crossing\nor incomplete extraction/simulation cannot establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 3.3 | 3.3 | bias |\n| `tail_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 3.3 | 3.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-i(VLOAD)`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)-v(vref)*i(VREF)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `psrr_db` | AC: Value of `(-db(v(vout))) at=1k`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `peaking_db` | AC: `20*log10((max (mag(v(vout))) from=1 to=100meg)/(find (mag(v(vout))) at=1))`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `peak_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=0.9m to=3m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `high_settled_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=1.2m to=1.9m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `low_settled_error_v` | TRAN: Maximum of `(abs(v(vout)-1.8)) from=2.2m to=3m`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `tail_min_v` | TRAN: Minimum of `v(ibias) from=0.9m to=3m`. | V | target / target | 0 … 3.3 | 3.3 | bias |\n| `dropout_v` | DC sweep: `(when v(vout)=1.75 rise=1)-1.75`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n\nArea reference: **7597.32 um2**. 106 expanded device instances; sum of device/contact envelopes 4876.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nGF180 compact regulator variants: regulation and recovery 36%; rejection and peaking 18%; dropout 18%; quiescent current 9%; internal bias 1.8%; power 7.2%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `high_settled_error_v` | 0.090000000000 |\n| `low_settled_error_v` | 0.090000000000 |\n| `output_v` | 0.090000000000 |\n| `peak_error_v` | 0.090000000000 |\n| `peaking_db` | 0.090000000000 |\n| `psrr_db` | 0.090000000000 |\n| `dropout_v` | 0.180000000000 |\n| `quiescent_a` | 0.090000000000 |\n| `tail_min_v` | 0.009000000000 |\n| `tail_v` | 0.009000000000 |\n| `power_w` | 0.072000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 PDK/EDA resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the active harness. If `process-feedback`\nis exposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit the snapshot with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml","case_sha256":"ce81b0be63953d3451a1ca61a2079a2ac2c7b9f5c88b9ab2d7d8246562237dcd","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice","netlist_sha256":"c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.ldo_005_buffered_ref","in_core":false,"title":"Buffered-Reference LDO","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_005_buffered_ref","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Buffered-Reference LDO Layout Task\n\n## Objective\n\nImplement `ldo_005_buffered_ref` as a GF180MCU D layout. The fixed upstream GF180 6 V circuit combines its self-biased reference amplifier, gain-two reference divider, RC low-pass filter, self-biased error amplifier, PMOS pass device, bleeder and on-die output capacitor. The two inlined amplifiers retain this LDO accession's own dimensions and compensation values; they are not replaced by the standalone amplifier cases.\n\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice`\ncontains matching native simulator wrappers. `materials/testbench.spice` defines\nall measurements. Ordered ports: `vdd vout vss vref`.\n\n`vdd/vss`: supply and return; `vout`: regulated output; `vref`: external 0.8 V reference. The upstream ideal VREF becomes test apparatus at this explicit port. Its zero-volt VLP loop marker becomes a wire to the output; no physical functional element is removed. The reference divider, RC filter, bleeder and four internal capacitors remain inside the DUT. External load and output capacitor remain test apparatus.\n\n## Operating Conditions\n\nTypical native models at 27 C, statistics disabled. All four combinations of 3.0/3.3 V supply and 50/200 uA DC load are evaluated, with a 0.8 V external reference and 1 uF external output load. AC supply injection spans 1 Hz–1 MHz, 80 points/decade. The load doubles at 100 us and returns after 100 us, with 1 us edges; transient evaluation ends at 500 us with 0.1 us requested steps. This is steady-state load-step characterization, not cold-start or dropout qualification.\n\n## Physical Requirements\n\nGDS database unit 0.001 um, maximum 10 MiB, top cell `ldo_005_buffered_ref`.\nNative standalone DRC covers geometry, connectivity, manufacturing grid, dummy\nfill and antenna; chip-level density and seal-ring closure are excluded.\nLVS must match all devices, parameters and named ports. Metal1 labels identify\nports. The functional bounding rectangle includes the device, well, implant,\ncontact, passive and complete routing layers enumerated in the runtime outline;\ntext annotations are excluded. Maximum outline is 5000 by 1000 um.\n\n6 V MOS minimum channel lengths are 0.70 um NMOS and 0.55 um PMOS. Only subminimum lengths are raised, and dimensions are quantized to 5 nm. Passives use 1 kohm/square poly, with series segmentation, and 2 fF/um2 MIM-B on M4/M5, with parallel tiling. Source and extracted candidates use the same native layer-specific capacitor models. Geometry, parasitic effects and physical values are authoritative; no ideal R/C replacements are made during post-layout simulation.\n\nCandidate-derived native Magic coupling capacitance and distributed wire\nresistance feed post-layout simulation, with zero omission thresholds.\nPhysical MOS diffusion areas/perimeters come from the layout. Substrate/well\nconnections are ideal: distributed substrate resistance/noise and inductance\nare not represented. Nominal DC regulation, 1 kHz supply rejection and load-step excursion/recovery across four supply/load points. Coefficient 7 reflects interacting regulation stages and recovery across loads. Noise, loop return-ratio, cold start, dropout, PVT and statistical yield are outside this declared scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Dimension | Normalization |\n| --- | --- | --- | --- | --- |\n| `output_v` | DC regulated output | V | bias | target |\n| `regulation_error_v` | Absolute DC error relative to 1.6 V | V | response | ratio |\n| `psrr_db` | Negative 20 log10 magnitude of supply-to-output response at 1 kHz | dB | response | db20 |\n| `excursion_v` | Output maximum minus minimum over 90–500 us | V | response | ratio |\n| `recovery_v` | Mean output over 400–500 us after the load returns | V | bias | target |\n| `power_w` | DC supply power -VDD*I(VDD) | W | supply | ratio |\n| `minimum_v` | Minimum transient output over 90–500 us | V | functional | unscored |\n| `maximum_v` | Maximum transient output over 90–500 us | V | functional | unscored |\n\nOutput and recovered output must be in 0–3.3 V; the transient minimum must be nonnegative and the maximum at most 3.3 V. Supply power and absolute/range errors must be nonnegative. These are supply-domain and physical measurement constraints. Accuracy, rejection and recovery differences enter continuous scoring; no upstream regulation target is a hard gate.\nEvery condition must complete; missing, nonfinite or wrong-unit observations\nproduce an evaluation error. Upstream advertised performance is not a\nqualification requirement.\n\nScored observations pair with independent source jobs using the identical\nstimuli, parameters, models and backend. Target scales are 3.3 V; ratio floors\nare 1 pW for power and 1 mV for error/excursion. These are normalization units,\nnot allowed degradation. `db20` compares\namplitude ratios.\n\nArea anchor **29565.16 um2** uses a 18964.964200 um2 sum of expanded\n`(W+2)*(L+2)` device/contact envelopes, a 50% routing allowance and 2 um outer\nmargin: `ceil(100*(1.5*sum+8*sqrt(sum)+16))/100`. It is independent of witness\narea and is an engineering estimate, not a foundry minimum. Coefficient **7**\nis independent of this score.\n\n\n### Score weights\n\nGF180 compact regulator variants: regulation and recovery 52.9%; rejection and peaking 26.5%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `excursion_v` | 0.132352941176 |\n| `output_v` | 0.132352941176 |\n| `recovery_v` | 0.132352941176 |\n| `regulation_error_v` | 0.132352941176 |\n| `psrr_db` | 0.264705882355 |\n| `power_w` | 0.105882352941 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRead `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. KLayout performs physical checks, Magic extracts the\ncandidate, and ngspice measures it. Use `process-feedback` if exposed.\nWrite `/workspace/output/final.gds`, then explicitly submit using\n`python -I /protocol/submit.py`.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml","case_sha256":"72472f50517883b49724573e7b61dd3b7f3272f0b9a9e2d0b24b46bccc29f8f4","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl","netlist_sha256":"1e1c14a91036bf5d0069bcc2a22f99e65c5f6a0a963377cc1e0ff2120293c9ff","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.ldo_006_stub","in_core":false,"title":"Divider-Biased NMOS Source Follower","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Tracks an input bias with a divider-biased NMOS source follower.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_006_stub","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Divider-Biased NMOS Source Follower Layout Task\n\n## Objective\n\nA single fixed 50/0.5 um nfet_03v3 (m=1) forms a source follower. Its drain connects to vdd, source to vout, body to vss, and gate to the midpoint of the internal 100 kohm/100 kohm supply divider. Each resistor uses two native ppolyf_u_1k segments, totaling 99995.18 ohm at TT/27 C. There is no control input, external reference, error amplifier or closed-loop regulator. Target top cell: `ldo_006_stub`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (drain and divider supply), vout (source output), vss (body/divider return).\n\n## Operating Conditions\n\nGF180 TT, 27 C. Supply is independently 1.2 or 1.5 V; output load is independently 100 kohm or 1 Mohm, in parallel with 10 pF. A 1 uA sink turns on at 2 us with a 20 ns edge and stays on throughout the 10 us run. Maximum step is 2 ns. The initial state has zero additional sink current and is computed by DC OP. A separate loaded DC OP with a 1 uA sink is compared with the 8–10 us transient endpoint. Supply power includes the divider, transistor and resistive load.\n\n## Physical Requirements\n\nUse GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | DC loaded source-follower output | 0 to 1.5 | bias: target, target, scale=0.1 |\n| `power_w` | W | DC power including internal 100k/100k divider | 0 to unbounded | supply: ratio, minimize, scale=1e-12 |\n| `step_shift_v` | V | Mean output at 8–10 us minus initial output | unbounded to unbounded | response: target, target, scale=0.1 |\n| `ripple_v` | V | Peak-to-peak output over final 2 us | 0 to unbounded | diagnostic / functional only |\n\nOnly output operating point, finite load-step shift and actual supply loss are scored. Late-window ripple is an unscored diagnostic; sub-nanovolt ripple is below numerical voltage resolution. No regulation accuracy, PSRR, dropout or loop-margin claim is made. The model guide includes 50 um width as a pseudo-device scaling boundary, not a directly measured width sample.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`.  Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 1200 um2 = 50 × 6 um2 pass-device/contact envelope + 4 × 55 × 2 um2 resistor/contact/isolation envelopes + 460 um2 routing/guard-ring allowance. It is a compact engineering estimate independent of witness sparsity. Coefficient 3: local analog bias/transfer and controlled load response. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nRegulator stub: loaded operating point 34%; load response 34%; power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `output_v` | 0.340000000000 |\n| `step_shift_v` | 0.340000000000 |\n| `power_w` | 0.170000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml","case_sha256":"3a47bf05ab107c1f351121652575a3e1687eb0ea83580f2ac8a13a35f0548534","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl","netlist_sha256":"b2cbf5b0cf0497af8ad62bded31556d61ed2d15ff665966e7e8e5e7772a58aa3","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.ldo_007_pmos","in_core":false,"title":"PMOS LDO with Feedforward Compensation","pdk":"gf180mcuD","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_007_pmos","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# PMOS LDO with Feedforward Compensation Layout Task\n\n## Objective\n\nImplement `ldo_007_pmos` as a GDS layout preserving the complete declared circuit. Five-transistor error amplifier, NMOS bias diode and PMOS pass array with complete resistive feedback divider, feedforward CFF across the upper divider, and series RZ/CC across the pass stage. Seven bound MOS expand to 146 units. The 0 V VLP feedback marker becomes a wire; ideal reference and current bias remain external apparatus.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/startup.spice`: startup observations.\n- `materials/regulation.spice`: regulation observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vdd vout vss ebias vref`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\nNominal supply 1.8 V, external reference 1.05 V and 60 uA from VDD into ebias; 27 C, typical GF180 3.3 V models with statistics disabled. Rtop=5 kohm and Rbottom=35 kohm set nominal output 1.2 V. The 140-fold pass array retains 20 um width and 0.5 um length per unit. CFF=60 pF, CC=0.05 pF and RZ=1 ohm are retained. RZ uses twelve parallel native high-poly units (L=1 um, W=97.21 um), nominal 1.000096 ohm at 27 C, to avoid an impossible sub-grid resistor length. No compensation is deleted. External reference-generation and current-source implementation losses are excluded; the 60 uA drawn from VDD and physical divider are included in rail power. External output capacitance is 1 nF with 0.1 ohm series ESR. Evaluate no disturbance, 1-to-2 mA load pulse, and +0.1 V input pulse, plus independent DC points at nominal+0.1 V/1 mA and nominal/2 mA. Pulses start at 100 us, have 1 us edges and 100 us high width; restoration finishes at 202 us. Observe 0–400 us with 10 ns maximum step; pre-step/high/recovery windows are 80–100/180–200/380–400 us. Supply rejection is measured at 1 kHz from a 1 V AC supply input (100 samples/decade, 1 Hz–100 MHz). Ascending DC sweeps cover nominal supply to nominal+0.1 V in 10 mV increments at 1 mA and 1–2 mA load in 0.1 mA increments at nominal supply; adjustment metrics are absolute endpoint slopes. These are finite ranges, not dropout measurements. Startup ramps VDD from zero to nominal in 10 us with fixed external references and a resistive 1 mA nominal load (target voltage/1 mA); it uses the ordinary initial DC solution, no UIC or forced initial output, and observes through 400 us. Startup extrema and late-window output/ripple are diagnostics. No dropout, loop gain or phase margin is claimed. Source and candidate use identical decks and parameters; no numerical shunt is used.\n\n## Physical Requirements\n\nGF180MCU D native standalone-block FEOL/BEOL, connectivity, grid, dummy and antenna rules; chip density/seal-ring rules are outside this block boundary. Named-port LVS and candidate-derived distributed Magic RC are required. Functional area includes active/poly, passives and all routing metal/vias. Capacitor substrate and resistor terminal models follow the frozen PDK profile. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 20000 by 2000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_v | V | DC output | bias; target (scale 1.2) |\n| regulation_error_v | V | Absolute DC setpoint error | response; ratio (scale 0.001) |\n| power_w | W | Total input rail DC power, including physical bleed/divider and external current bias | supply; ratio (scale 1e-12) |\n| psrr_db | dB | Input supply rejection at 1 kHz | response; db20 |\n| quiet_ripple_v | V | Peak-to-peak pre-perturbation output 80–100 us | response; ratio (scale 0.001) |\n| recovery_ripple_v | V | Peak-to-peak recovered output 380–400 us | response; ratio (scale 0.001) |\n| excursion_v | V | Full output range 100–400 us | response; ratio (scale 0.001) |\n| late_error_v | V | Mean absolute setpoint error 380–400 us | response; ratio (scale 0.001) |\n| mean_power_w | W | Mean input rail power 0–400 us | supply; ratio (scale 1e-12) |\n| quiet_v | V | Finite-window quiet_v | diagnostic; unscored |\n| high_v | V | Finite-window high_v | diagnostic; unscored |\n| recovery_v | V | Finite-window recovery_v | diagnostic; unscored |\n| startup_final_v | V | 10 us input ramp with resistive load: startup_final_v | diagnostic; unscored |\n| startup_ripple_v | V | 10 us input ramp with resistive load: startup_ripple_v | diagnostic; unscored |\n| startup_min_v | V | 10 us input ramp with resistive load: startup_min_v | diagnostic; unscored |\n| startup_max_v | V | 10 us input ramp with resistive load: startup_max_v | diagnostic; unscored |\n| line_reg_v_per_v | V/V | Absolute ascending supply-sweep endpoint slope, nominal to nominal + 0.1 V, 1 mA load | response; ratio (scale 0.001) |\n| load_reg_ohm | ohm | Absolute ascending load-sweep endpoint slope, 1 to 2 mA, nominal supply | response; ratio (scale 1) |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 98448.9 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. For ordinary GF180 resistors this envelope conservatively uses the sheet-only length before contact correction; the explicit parallel 1-ohm bank uses its native dimensions. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 7 covers regulation, frequency response and recovery across loads. No on-chip reference/bias generator is claimed. No loop-gain measurement is used, so CFF cannot bypass a purported loop break. The native resistor model includes terminal resistance in both source and candidate.\n\n\n### Score weights\n\nGF180 line/load regulators: regulation 30%; load and line recovery 30%; ripple and rejection 20%; power 10%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_reg_v_per_v` | 0.075000000000 |\n| `load_reg_ohm` | 0.075000000000 |\n| `output_v` | 0.075000000000 |\n| `regulation_error_v` | 0.075000000000 |\n| `excursion_v` | 0.149999999999 |\n| `late_error_v` | 0.150000000000 |\n| `psrr_db` | 0.066666666667 |\n| `quiet_ripple_v` | 0.066666666667 |\n| `recovery_ripple_v` | 0.066666666667 |\n| `mean_power_w` | 0.050000000000 |\n| `power_w` | 0.050000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `ldo_007_pmos`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml","case_sha256":"2c6a1875c4327f5b25fa89eadd2bc7eab6c5a7e0a0c1eeaed625b9e5a09185f7","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl","netlist_sha256":"4b3f01ca7600933022e7730cc7cfb614b7abcc2808f7ef777b0019b27514382a","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.sup_001_vcm_detector","in_core":false,"title":"Passive Resistive Common-Mode Averager","pdk":"gf180mcuD","category":"Amplifiers & RF","summary":"Averages two input voltages through a passive resistive common-mode network.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sup_001_vcm_detector","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Passive Resistive Common-Mode Averager Layout Task\n\n## Objective\n\nTwo matched 1 Mohm resistors join vinp to vcm_out and vcm_out to vinn. This is a passive average detector, without a buffer, amplifier or CMFB controller. The fixed IHP binding contains ideal R cards, not process-specific resistor models; the maintained physical adaptation uses forty native GF180 ppolyf_u_1k segments (twenty per branch), totaling 999951.8 ohm per branch at TT/27 C. The extra vss port grounds their physical substrate; it is not a functional supply. Target top cell: `sup_001_vcm_detector`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vcm_out (sense output), vinp (positive input), vinn (negative input), vss (physical substrate).\n\n## Operating Conditions\n\n27 C, TT. External ideal drivers are 0.8 V and 0.4 V, each followed by 1 kohm source resistance. The output has 1 pF and either 1 Mohm or 1 Gohm to ground. Each load uses common-mode AC (both drivers +1 V) and differential AC (+1/-1 V), 1 Hz–10 MHz at 40 points/decade. Both drivers increase by 0.1 V at 1 us, with 10 ns edges, and stay high through the 5 us observation. Maximum transient step is 2 ns. The initial state is the same biased DC operating point for source and candidate. A 1 Gohm load is a finite high-impedance observation, not an unloaded claim. The analytic DC limit is Vcm*RL/(RL+500.5 kohm), tending to Vcm only as RL tends to infinity. Both input-source powers are included; no zero-power claim follows from the absence of a supply pin.\n\n## Physical Requirements\n\nUse GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | Loaded DC sense voltage | 0 to 0.8 | bias: target, target, scale=0.1 |\n| `power_w` | W | Net delivered power from both external input sources | 0 to unbounded | supply: ratio, minimize, scale=1e-12 |\n| `gain` | 1 | Output magnitude at 1 Hz for declared common/differential input | unbounded to unbounded | response: target, target, scale=1 |\n| `gain_10khz` | 1 | Output magnitude at 10 kHz | unbounded to unbounded | response: target, target, scale=1 |\n| `step_error_v` | V | Mean absolute error from settled DC target over 2–4 us | 0 to unbounded | response: ratio, minimize, scale=1e-06 |\n\nThe 2–4 us average absolute step error is a finite-window quantity. Common and differential AC magnitudes use a 1 V half-input normalization; the differential residual is not divided by a near-zero source result. Nominal deterministic matching does not establish statistical mismatch or noise.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`.  Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 6000 um2 = 40 × 55 × 2 um2 resistor/contact/isolation envelopes + 1600 um2 routing allowance. Each envelope accommodates the approximately 48.44 um resistor, end contacts and lateral spacing; the estimate permits folding. It is independent of the long, sparse witness. Coefficient 4: coupled matching, physical passive network, finite loading and parasitic dynamics. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nCommon-mode sensing/controllers: recovery and error 40.5%; signed transfer 31.5%; output bias 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `step_error_v` | 0.405000000000 |\n| `gain` | 0.157500000000 |\n| `gain_10khz` | 0.157500000000 |\n| `output_v` | 0.045000000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml","case_sha256":"d55e2d90c82eb4a446b13abeca2375c30aa7bea68a78fd683cce8f4af4104670","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl","netlist_sha256":"c0cdf0e12dbdbfc2e7d1fd9fe3c061a29f745efd8656e1a85e100036489db523","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.tsn_001_ptat_2t","in_core":false,"title":"Two-NMOS Temperature-Response Core","pdk":"gf180mcuD","category":"Power & references","summary":"Produces a temperature-dependent response whose slope and curvature are measured across the declared range.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_001_ptat_2t","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Two-NMOS Temperature-Response Core Layout Task\n\n## Objective\n\nThe fixed GF180 binding contains eight parallel 8/0.28 um upper NMOS with gates tied to their sources, and eight parallel 4/1 um diode-connected lower NMOS. Both groups have grounded bodies. This is a two-group temperature-response core; neither its PTAT name nor a successful simulator exit establishes a useful slope or a converged extracted operating point. Target top cell: `tsn_001_ptat_2t`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/temperature.spice` supplies the shared external fixture and bidirectional temperature sweep. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (supply), vout (sense voltage), vss (both bodies and return).\n\n## Operating Conditions\n\nGF180 nfet_03v3 TT, fixed 1.2 V supply, 1 Tohm probe resistance and 1 pF to ground. No external current bias changes with temperature. Ascending and descending temperature sweeps use 5 C steps. Output and power at -20 through 120 C in 10 C steps are sampled from the same ascending sweep used for slope and curvature. The fixed 50 mV nodeset is a Newton initial guess, not a voltage source or a per-temperature bias adjustment. Sparse 1.3, pivtol=1e-30 S, pivrel=0.001, reltol=1e-7, abstol=1e-18 A, vntol=1e-10 V and gmin=1e-18 S are explicit for both circuits; no rshunt is used.\n\n## Physical Requirements\n\nUse GF180 native KLayout main rule deck and named-interface LVS; Magic RC extraction with its reviewed 10-way grid subdivision. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | Independent DC temperature-response output | 0 to 1.2 | bias: target, target, scale=0.1 |\n| `power_w` | W | DC supply power at fixed 1.2 V | 0 to unbounded | supply: ratio, minimize, scale=1e-15 |\n| `slope_v_c` | V/C | Endpoint temperature slope over -20 to 120 C | unbounded to unbounded | response: target, target, scale=0.001 |\n| `curvature_v` | V | Maximum deviation from endpoint secant over -20 to 120 C | 0 to unbounded | response: ratio, minimize, scale=1e-06 |\n\nThe simulator uses an explicit branch-current formulation for constant parasitic resistors: a zero-volt current sensor and a current-controlled voltage source impose V=R*I exactly. Every resistance, terminal and extracted capacitance is retained. This avoids loss of tiny node conductances when added to the much larger metal conductance in conventional nodal stamping. The original extraction and the effective simulation netlist are both retained as evidence. Source and candidate use the same backend setting. This deterministic formulation does not model resistor thermal noise; noise is outside this task's scope. KCL and measurement-validity checks remain mandatory. No self-startup, precision temperature sensing or linear PTAT behavior is assumed.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`.  Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 1600 um2 = 8 × 10 × 10 um2 upper-device/contact envelopes + 8 × 6 × 8 um2 lower-device/contact envelopes + 416 um2 routing/body-contact allowance, independent of witness area. Coefficient 3: local analog temperature-dependent bias and transfer. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nTemperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `slope_v_c` | 0.423529411764 |\n| `curvature_v` | 0.317647058824 |\n| `output_v` | 0.052941176471 |\n| `power_w` | 0.105882352941 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml","case_sha256":"ae46695ccced40bea2ff56991b625536b0e5f297958c5f450d761d54b11135c6","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl","netlist_sha256":"534d2b4bdfe4354bd80c0db81495c5d60a73fe20912ba79f3ccb749fadaf7efc","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.tsn_002_ptat_classic","in_core":true,"title":"Self-Starting Isolated-Body PTAT Core","pdk":"gf180mcuD","category":"Power & references","summary":"Produces a temperature-dependent response whose slope and curvature are measured across the declared range.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_002_ptat_classic","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Self-Starting Isolated-Body PTAT Core Layout Task\n\n## Objective\n\nImplement `tsn_002_ptat_classic` in GF180MCU D and submit self-contained GDS.\nThe resistor-degenerated four-MOS source core has a positive temperature slope;\ncandidate slope is measured and source-paired without a positive-slope acceptance bound.\nA maintained three-MOS startup branch establishes its operating state after\npower-up. Supply sensitivity remains: this is not a precision temperature\nreference or a calibrated thermometer.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical LVS authority;\n`materials/circuit.spice` is its simulator representation.\n`materials/testbench.spice` defines stimuli and observations. This problem is\nthe description input. Ordered ports are `vdd vout vss`: supply,\ntemperature-dependent output and return.\n\nRetain all device dimensions, multiplicities and four-terminal connections.\nThe 8/1 um core NMOS has both source and body on `vout`; its body must remain\nisolated from VSS. The physical primitive `MM0 ... nfet_03v3_dn` maps to\n`XM0 ... nfet_03v3` in the simulator, with the same D/G/S/B and W/L/m.\nUse an isolated P-well inside a supply-tied deep N-well, with explicit\nN-well enclosure and physical well/substrate contacts. Extraction must retain\nthe separation between the output body and substrate return. No body-to-VSS\nsubstitution is permitted. The core resistor is physical 1 kohm/square poly,\nW=2 um, L=40 um, nominal 20 kohm.\n\nThe added startup devices have W/L of 0.42/20 um (weak PMOS pull-up),\n2/0.28 um (NMOS detector) and 0.42/1 um (NMOS injector). The detector reduces\nthe startup control voltage after bias is established, turning off the\ninjection path. The weak pull-up/detector branch still draws static current;\nall DUT supply power is measured. Preserve this branch as part of the DUT.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No statistical matching\nor placement style is scored. External stimulus and the output load belong to\nthe testbench and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse typical GF180 3.3 V MOS and poly models with statistical variation disabled.\nVSS is 0 V. Evaluate all 18 combinations of VDD = 2.7/3.0/3.3 V,\ntemperature = -20/27/100 C and supply rise time = 0.1/10 us.\nEach condition measures its DC operating point and a -20 to 100 C sweep in\n1 C steps. The temperature is then restored to the selected value before\nstartup simulation. The external output capacitance is exactly 100 fF.\n\nFor startup, ramp VDD linearly from 0 to its selected value, then hold it.\nUse a zero-initial-state `uic` transient through 100 us with no internal\ninitial-condition bias or auxiliary startup source. Gear order 2 and a\nmaximum timestep of 1 ns are declared. Measure final error, ripple and average\npower over 90–100 us. These are finite-window error and ripple observations with no settling-error\nacceptance threshold; they do not establish settling time or bound overshoot.\n\n## Physical Requirements\n\nSubmit top cell `tsn_002_ptat_classic`, all named electrical ports, resolved\nhierarchy and at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass with no DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 220 by 65 um. Its area includes\nall declared device and routing drawing layers: wells (including deep N-well\nand isolated P-well), implants, active, poly, contacts, metals/vias and device\nmarkers. Annotation and pin-purpose shapes are excluded. All functional\nrouting must use drawing layers. `/protocol/task.json` freezes the layer set.\n\nIndependent candidate extraction retains MOS and resistor geometry and adds\ndistributed wiring RC. All scored simulation consumes that extracted DUT.\nThis does not include a distributed silicon substrate model. Larger output\nloads are unqualified and can cause oscillation; this is not a pF-load output\nbuffer. Brownout/restart, arbitrary supply ramps, process/statistical corners,\nnoise, absolute temperature accuracy, supply rejection, EM and fabrication\nsignoff are outside scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output at the selected supply and temperature | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC delivered supply power, -V(vdd)*I(VDD), including startup bias | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `cold_v` | Output at -20 C | V | target / target | 0 … 3.3 | 3.3 |\n| `hot_v` | Output at 100 C | V | target / target | 0 … 3.3 | 3.3 |\n| `slope_v_per_c` | (hot_v - cold_v)/120 C | V/C | target / target | −∞ … +∞ | 0.00047 |\n| `curvature_v` | Maximum absolute deviation from the endpoint line at all 121 temperatures | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `minimum_slope` | Minimum ngspice deriv(output) over temperature | V/C | target / target | −∞ … +∞ | 0.00055 |\n| `maximum_slope` | Maximum ngspice deriv(output) over temperature | V/C | target / target | −∞ … +∞ | 0.00055 |\n| `peak_power_w` | Maximum delivered supply power over temperature | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `startup_error_v` | Maximum absolute output error against the selected DC operating point during 90–100 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `ripple_v` | Maximum minus minimum output during 90–100 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `final_power_w` | Time-average delivered supply power during 90–100 us | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **529.13 um2**. 8 expanded device instances; sum of device/contact envelopes 303.6200 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTemperature-slope cores: temperature slope 36%; curvature 27%; startup 13.5%; output endpoints 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `maximum_slope` | 0.120000000000 |\n| `minimum_slope` | 0.120000000000 |\n| `slope_v_per_c` | 0.120000000000 |\n| `curvature_v` | 0.270000000000 |\n| `ripple_v` | 0.067500000000 |\n| `startup_error_v` | 0.067500000000 |\n| `cold_v` | 0.015000000000 |\n| `hot_v` | 0.015000000000 |\n| `output_v` | 0.015000000000 |\n| `final_power_w` | 0.030000000000 |\n| `peak_power_w` | 0.030000000000 |\n| `power_w` | 0.030000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources in `/protocol/resources.json`. KLayout checks\nphysical validity and geometry, Magic extracts RC and ngspice simulates the\ncircuit. `/protocol/task.json` provides frozen requirements and\n`/protocol/harness.json` describes the harness. When `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then submit with `python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml","case_sha256":"7e55370aaf8b7af565f5184681e6716ec83d8a276446c05c92522b4eb3b10114","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl","netlist_sha256":"1efc6b4da14d95c12ff19bd3a1e8a10a8c986a97befff37dadb44ce6f10ef5ea","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.analog-db.tsn_003_ptat_4t_xcoupled","in_core":false,"title":"Four-Transistor Positive-Temperature-Slope Core","pdk":"gf180mcuD","category":"Power & references","summary":"Produces a temperature-dependent response whose slope and curvature are measured across the declared range.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_003_ptat_4t_xcoupled","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Four-Transistor Positive-Temperature-Slope Core Layout Task\n\n## Objective\n\nImplement the fixed `tsn_003_ptat_4t_xcoupled` circuit in GF180MCU D and submit self-contained GDS.\nTwo NMOS and two PMOS devices form a resistorless temperature-dependent voltage core with cross-coupled bias connections. The fixed GF180 sizes are retained. The output increases with temperature under each declared supply, but both voltage and slope depend strongly on supply. This is a temperature-slope layout task, not a precision reference or calibrated thermometer.\n\n## Inputs and Interface\n\n`materials/circuit.spice` is authoritative for LVS and source calibration;\n`materials/testbench.spice` defines every electrical measurement. This problem\nis the description input. Ordered ports: `vdd vout vss`.\nIn order, these are: Supply, unloaded temperature-dependent output, and return.\n\nPreserve the netlist's device connectivity, dimensions, multiplicities and body\nconnections. Provide physical well/substrate contacts to the declared rails.\nPlacement, routing, splitting and source/drain interchange are permitted only\nwhere accepted by the declared LVS equivalence rules. No common-centroid or\nstatistical matching requirement is scored. Ideal external stimulus, bias and\nload devices remain testbench apparatus and must not be placed inside the DUT.\n\n## Operating Conditions\n\nUse the typical GF180 3.3 V MOS models and physical poly models where present,\nwith statistical variation disabled. Unless swept explicitly, temperature is 27 C.\nVSS = 0 V; VDD = 2.7, 3.0 and 3.3 V. Measure the operating point at 27 C, then sweep temperature from -20 to 100 C inclusive in 1 C steps at each supply. The output is unloaded except for the measurement probe. No ideal internal source or passive is added.\n\n## Physical Requirements\n\nSubmit top cell `tsn_003_ptat_4t_xcoupled` with every named electrical port, resolved hierarchy\nand a file size at most 10 MiB. Artifact, GF180 variant-D DRC including antenna,\nstrict named-port LVS and geometry must pass, without DRC waivers. Chip-level\ndensity and seal-ring closure are outside this standalone-block scope.\n\nThe functional bounding box must fit within 120 by 60 um. Area includes all\nprocess device and routing drawing layers listed in runtime constraints:\nwells, implants, active, poly, contacts, metals/vias and passive/device markers.\nAnnotation and pin-purpose shapes are excluded; all functional routing must use\ndrawing layers. The complete layer list is frozen in `/protocol/task.json`.\n\nThe judge independently extracts distributed wiring resistance and capacitance\nfrom the submitted GDS, retaining candidate-derived MOS/passive geometry and\nexternal body connections. Every scored simulation consumes that extracted DUT.\nThis model boundary does not include a distributed silicon substrate network.\nThe temperature sweep is a nominal model sweep, not process-corner or statistical qualification. Startup, output drive, absolute temperature accuracy, supply rejection, mismatch, noise and EM are outside scope. Manufacturing signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll three operating conditions must complete and every observation must be finite\nand meet its inclusive band. Aggregation cannot hide a failing condition;\nmissing crossings or incomplete extraction/simulation cannot establish success.\nSaved waveforms provide the inputs for independently reconstructing observations.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output voltage | V | target / target | 0 … 3.3 | 3.3 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `cold_v` | Output at -20 C | V | target / target | 0 … 3.3 | 3.3 |\n| `hot_v` | Output at 100 C | V | target / target | 0 … 3.3 | 3.3 |\n| `slope_v_per_c` | (Output at 100 C - output at -20 C)/120 C | V/C | target / target | −∞ … +∞ | 0.00036 |\n| `curvature_v` | Maximum deviation from the endpoint line over all 121 temperature samples | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `minimum_slope` | Minimum ngspice deriv(output) over the temperature sweep | V/C | target / target | −∞ … +∞ | 0.00024 |\n| `maximum_slope` | Maximum ngspice deriv(output) over the temperature sweep | V/C | target / target | −∞ … +∞ | 0.00036 |\n| `peak_power_w` | Maximum -V(vdd)*I(VDD) over the full temperature sweep | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **168.38 um2**. 4 expanded device instances; sum of device/contact envelopes 85.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **3**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTemperature-slope cores: temperature slope 42.4%; curvature 31.8%; output endpoints 5.29%; power 10.6%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `maximum_slope` | 0.141176470588 |\n| `minimum_slope` | 0.141176470588 |\n| `slope_v_per_c` | 0.141176470588 |\n| `curvature_v` | 0.317647058822 |\n| `cold_v` | 0.017647058824 |\n| `hot_v` | 0.017647058824 |\n| `output_v` | 0.017647058824 |\n| `peak_power_w` | 0.052941176471 |\n| `power_w` | 0.052941176471 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed GF180 resources listed in `/protocol/resources.json`.\nKLayout checks the layout, Magic extracts RC and ngspice simulates the circuit.\n`/protocol/task.json` provides frozen constraints and evaluation requirements;\n`/protocol/harness.json` describes the harness. If `process-feedback` is\nexposed, use its published helper for interim checks. Write\n`/workspace/output/final.gds`, then explicitly submit with\n`python -I /protocol/submit.py`.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml","case_sha256":"8576bf939c13cb0a1cedb4855f4e09a92ba6a5811af0ab7552b30e35461dcb8e","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/problem.md","netlist_path":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice","netlist_sha256":"f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09","license_path":"tasks/gf180mcuD/analog-db/LICENSE"}
+{"id":"gf180mcuD.gf-r2r-dac.r2r","in_core":true,"title":"Eight-Bit R-2R DAC Core","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Converts an eight-bit digital code into an analog voltage through an R-2R network.","source_url":"https://github.com/mattvenn/gf-r2r-dac/tree/1c5c8ddec54fc4e70ce03a19510d4d7461b919e9/xschem/simulation/r2r.spice","status":"qualified","collection":"gf-r2r-dac","task_kind":"netlist_to_gds","problem":"# Eight-Bit R-2R DAC Core Layout Task\n\n## Objective\n\nImplement `r2r` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Eight-bit passive voltage conversion with ideal external bit drivers and a 1 pF output load; zero, eight one-hot codes and full scale.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `b7, b1, b0, b2, b3, b4, b5, b6, out, VGND`.\nb0–b7: ideal-driver bit inputs (b0 is LSB); out: analog output; VGND: substrate and ladder return.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V bit-driver levels and 27 C, with 1 pF from out to VGND. Evaluate codes 0, 1, 2, 4, 8, 16, 32, 64, 128 and 255 separately. bit0 is the least significant bit. Each bit starts at 0 V and changes from 10 ns to 10.1 ns to 3.3*bitN V. Simulate through 2 us with a 1 ns requested step. The expected settled voltage is 3.3*code/256 V. The external drivers and load are testbench components, outside the required passive circuit.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `r2r` and at most 10485760 bytes. Its functional bounding box must not exceed 200 by 200 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `accuracy` | Absolute difference between output at 1.9 us and 3.3*code/256, checked independently for each declared code. | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `settling` | Absolute difference between output at 1 us and 3.3*code/256 after the 10 ns input transition. | V | minimize / ratio | 0 … +∞ | 1e-06 |\n\nArea reference: **8727.76 um2**. 27 expanded device instances; sum of device/contact envelopes 5616.0000 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nPassive R-2R DAC: conversion accuracy 63%; dynamic residual 27%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `accuracy` | 0.630000000000 |\n| `settling` | 0.270000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml","case_sha256":"4b8fa1f0e83dc6d5b3a65e1c8a04e59f6a00e66df24f61477013ab7a3335bed2","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md","netlist_path":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice","netlist_sha256":"64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957","license_path":"tasks/gf180mcuD/gf-r2r-dac/LICENSE"}
+{"id":"gf180mcuD.tt_tnt_gf_vco.vco","in_core":true,"title":"Quadrature Voltage-Controlled Oscillator","pdk":"gf180mcuD","category":"Mixed-signal","summary":"Generates quadrature oscillation with a voltage-controlled tuning response.","source_url":"https://github.com/smunaut/tt_tnt_gf_vco/tree/897b3ec12ed693161fb56f4205d1b19dc5e56c1a/xschem/vco.sch","status":"qualified","collection":"tt_tnt_gf_vco","task_kind":"netlist_to_gds","problem":"# Quadrature Voltage-Controlled Oscillator Layout Task\n\n## Objective\n\nImplement `vco` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Four-phase oscillation, quadrature and frequency tuning at control voltages 1.65 V and 2.10 V, with 50 fF on each output.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `GND, VDD, ctrl, out_0, out_90, out_180, out_270`.\nGND/VDD: return/supply; ctrl: tuning voltage; out_0/out_90/out_180/out_270: quadrature outputs.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 27 C and two independent copies of the submitted circuit at ctrl = 1.65 V and 2.10 V. Each copy has its own ideal supply ramping from 0 V at 0 ns to 3.3 V at 1 ns and 50 fF from each output to ground. Simulate through 600 ns with a 0.02 ns requested step. Characterize steady oscillation over 400–600 ns. Each operating point must meet every applicable requirement; their supply powers are checked individually.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `vco` and at most 10485760 bytes. Its functional bounding box must not exceed 700 by 240 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `low_control_frequency` | Inverse period between the first two out_0 rising 1.65 V crossings after 400 ns at ctrl=1.65 V. | Hz | target / target | 0 … +∞ | 150000000.0 |\n| `high_control_frequency` | The same frequency measurement at ctrl=2.10 V. | Hz | target / target | 0 … +∞ | 300000000.0 |\n| `tuning` | Frequency at 2.10 V divided by frequency at 1.65 V. | 1 | maximize / ratio | 0 … +∞ | — |\n| `quadrature90` | First out_90 versus out_0 rising-crossing displacement after 400 ns, divided by period and reduced modulo one cycle. | 1 | target / target | −∞ … +∞ | 1.0 |\n| `quadrature180` | The same phase measurement for out_180. | 1 | target / target | −∞ … +∞ | 1.0 |\n| `quadrature270` | The same phase measurement for out_270. | 1 | target / target | −∞ … +∞ | 1.0 |\n| `low` | Minimum voltage on each output over 400–600 ns at each control voltage. | V | functional check | −∞ … 0.33 | — |\n| `high` | Maximum voltage on each output over 400–600 ns at each control voltage. | V | functional check | 2.97 … +∞ | — |\n| `supply` | Average delivered supply power over 400–600 ns, separately for each control voltage. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **907.08 um2**. 47 expanded device instances; sum of device/contact envelopes 540.0800 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nQuadrature VCO: frequency targets 31.5%; tuning 18%; quadrature 27%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `high_control_frequency` | 0.157500000000 |\n| `low_control_frequency` | 0.157500000000 |\n| `tuning` | 0.180000000000 |\n| `quadrature180` | 0.090000000000 |\n| `quadrature270` | 0.090000000000 |\n| `quadrature90` | 0.090000000000 |\n| `supply` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml","case_sha256":"0216ce13ab17e57ba9f49bea65d267a15b41c8dedf27f6769ba9fad6c1d851b0","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md","netlist_path":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice","netlist_sha256":"021943933973e205dfb533131232917d18d1ffe8b24bedc5e45534992e2a1615","license_path":"tasks/gf180mcuD/tt_tnt_gf_vco/LICENSE"}
+{"id":"gf180mcuD.voidwalkers-scandff.scan_dff","in_core":true,"title":"Scan D Flip-Flop with Active-Low Reset","pdk":"gf180mcuD","category":"Logic & memory","summary":"Stores a clocked bit with scan selection and asynchronous active-low reset.","source_url":"https://github.com/radityankn/voidwalkers-scandff-gf180mcu/tree/b136150cdcfd55a9568fe14a825c214c3af5dde4/designs/cells/gf180mcu_voidwalkers_sc_sdffrnq_4/sch/gf180mcu_voidwalkers_sc_sdffrnq_4.sch","status":"qualified","collection":"voidwalkers-scandff","task_kind":"netlist_to_gds","problem":"# Scan D Flip-Flop with Active-Low Reset Layout Task\n\n## Objective\n\nImplement `gf180mcu_voidwalkers_sc_sdffrnq_4` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Functional data and scan selection, rising-edge storage, asynchronous active-low reset, and 50 MHz operation with 50 fF load.\n\n## Inputs and Interface\n\nThe delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.\n\nOrdered subcircuit and GDS interface: `S, VDD, Q, B, CLK, A, RN, VSS`.\nVDD/VSS: supply/return; A: functional data; B: scan data; S: select (0=A, 1=B); CLK: rising-edge clock; RN: active-low asynchronous reset; Q: stored output.\n\nPreserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.\n\n## Operating Conditions\n\nUse 3.3 V and 27 C, a 50 fF Q load and the same 50 MHz clock throughout (first rise 10 ns, rise/fall 0.1 ns, high time 10 ns). Select A initially; select B at 40.1 ns; return to A at 80.1 ns. A rises at 20.1 ns, falls at 60.1 ns, rises at 100.1 ns and falls at 120.1 ns. B rises at 60.1 ns. RN starts low, releases at 5.1 ns, asserts at 85.1 ns and releases at 95.1 ns. All data/reset transitions take 0.1 ns, as specified in the testbench. Simulate through 140 ns.\n\nUse the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.\n\n## Physical Requirements\n\nSubmit a nonempty GDS with top cell `gf180mcu_voidwalkers_sc_sdffrnq_4` and at most 10485760 bytes. Its functional bounding box must not exceed 80 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:\n\n`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.\n\nText and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.\n\nLVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.\n\n\nThe standard-cell functional frame has fixed height 6.35 um and width on a 0.005 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.\n\n- `VDD`: centre y = 6 um, thickness at least 0.23 um, from left + 0 um to right − 0 um.\n- `VSS`: centre y = 0.35 um, thickness at least 0.23 um, from left + 0 um to right − 0 um.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `low` | Q at 19, 59, 89, 99 and 139 ns; the 89 ns sample checks asynchronous reset before the next rising clock. | V | functional check | −∞ … 0.33 | — |\n| `high` | Q at 39, 79 and 119 ns, exercising functional and scan data. | V | functional check | 2.97 … +∞ | — |\n| `propagation_delay` | Worst paired quality over: delay_data_rise, delay_data_fall, delay_scan_rise, delay_scan_fall, delay_reset_fall. | s | minimize / ratio | 0 … +∞ | — |\n| `output_transition` | Worst paired quality over: slew_data_rise, slew_data_fall, slew_scan_rise, slew_scan_fall, slew_reset_fall. | s | minimize / ratio | 0 … +∞ | — |\n| `supply` | Average VDD power over 20–140 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **175.5775 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 27.65 by 6.35 um = 175.577 um2. Reference SHA-256: ffd6654d5505bf6340acbb3061ad81fab36951badda45b3bd3a8448be0fa00ab. This footprint includes the maintained explicit taps and routing.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n### Standard-cell design guidance\n\nPlan the device rows, power rails and signal access before routing. Represent\npull-up and pull-down connectivity as transistor-edge graphs; explore compatible\nEuler trails and alternative orderings to share diffusion and reduce breaks.\nChoose among legal orderings using routing length, parasitic loading and signal\naccess, rather than diffusion sharing alone. Preserve the fixed netlist sizes,\nmodels and connectivity; size optimization is outside this task.\n\nUse the task's declared row height, grid and rail geometry. Keep local routes\ncompact, leave signal pins accessible, and avoid consuming extra routing layers\nwithout benefit. Check DRC and named-port LVS, then extract the candidate and\ncompare both transition directions and power with the source simulation. Iterate\non measured parasitic effects rather than visual compactness alone. These are\noptional techniques, not a mandated algorithm or reference placement.\n\nAdapted from Xu et al., *Standard Cell Library Design and Optimization Methodology\nfor ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,\ntrack counts and process-specific dimensions do not apply to this task.\n\n\n### Score weights\n\nScan flip-flop: clock-to-output delay 51%; output transition 17%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `propagation_delay` | 0.510000000000 |\n| `output_transition` | 0.170000000000 |\n| `supply` | 0.170000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.\n\nUse a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.\n","case_path":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml","case_sha256":"fe6e95a3b09be67897fb5e30546a601dfdbf4498ebcd13ffa82f4ec00259f4ad","pdk_path":"tasks/gf180mcuD/pdk.toml","pdk_sha256":"ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde","description_path":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md","netlist_path":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice","netlist_sha256":"659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58","license_path":"tasks/gf180mcuD/voidwalkers-scandff/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.adc_001_inv1b","in_core":false,"title":"CMOS Inverter Threshold Core","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Characterizes an inverter switching threshold, output swing and timing.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/adc_001_inv1b","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# CMOS Inverter Threshold Core Layout Task\n\n## Objective\n\nThe fixed binding is a CMOS inverter: one 1/0.13 um NMOS and one 2.5/0.13 um PMOS, each m=1. Bodies connect to their respective rails through native physical contacts. It provides a threshold decision core; there is no sampling, independent reference, encoding or complete ADC. Target top cell: `adc_001_inv1b`.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (1.2 V rail), vin (gate input), vout (drain output), vss (return).\n\n## Operating Conditions\n\nIHP LV MOS TT, 27 C, VDD=1.2 V. Input driver impedance is 50 ohm; output capacitance is 20 fF. DC input sweeps 0–1.2 V in 1 mV steps. The transient driver starts at 0 V, rises at 10 ns, falls at 20.1 ns, has 100 ps edges and a 20 ns period. The initial DC output is high. The 31 ns run uses a maximum 1 ps step. Power is the net energy from supply and input driver divided by the 10–30 ns window.\n\n## Physical Requirements\n\nUse IHP native KLayout main and maximum rule decks and named-interface LVS; Magic full RC extraction. No case-specific waivers. Candidate extraction must preserve every model, multiplicity, size, resistor value, connection and ordered port. The functional outline includes devices, wells, contacts and all routing layers declared in the public task; annotation and pin labels do not add area. Maximum outline: 5000 by 1000 um. Maximum GDS size: 10485760 bytes. Every device and resistor must be physical; no ideal internal macro or auxiliary servo may be added. External sources, probe loads and storage capacitors belong to the testbench.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Bound | Quality |\n| --- | --- | --- | --- | --- |\n| `threshold_v` | V | Unique DC output=0.6 V crossing | unbounded to unbounded | response: target, target, scale=0.6 |\n| `delay_s` | s | Worst 50% input to opposite 50% output delay | 0 to unbounded | response: ratio, minimize, scale=1e-12 |\n| `transition_s` | s | Worst output 10–90% or 90–10% transition | 0 to unbounded | response: ratio, minimize, scale=1e-12 |\n| `power_w` | W | Mean net supply and input-driver power from 10–30 ns | 0 to unbounded | supply: ratio, minimize, scale=1e-12 |\n| `swing_v` | V | DC high minus low output; meaningful logic transition | 0.6 to unbounded | diagnostic / functional only |\n\nThe DC threshold is the unique output=0.6 V crossing, not a scan endpoint. Delay is the worse input 50% to opposite output 50% delay. Transition is the worse output 10–90% rise or 90–10% fall. Guards reject missing or multiple DC/transition crossings; independent audits require the intended 10–15 ns and 20–25 ns windows and correct ordering. DC high/low output uses actual endpoint samples, with a minimum 0.6 V swing establishing a meaningful logic transition. This is nominal loaded characterization, not Liberty/PVT or ADC accuracy.\n\nStatic output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.\n\nFor each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`.  Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.\n\nCompact area anchor: 120 um2 = 20 um2 NMOS contact envelope + 30 um2 PMOS/well envelope + 20 um2 body-contact/isolation allowance + 50 um2 routing. These envelopes follow the fixed widths and contact/isolation needs, not the witness bounding box. Coefficient 1: a single logic stage with loaded transitions and connectivity. The circuit and these anchors are fixed before participant evaluation.\n\n\n### Score weights\n\nInverter threshold element: switching threshold 25.5%; delay 34%; transition 12.8%; power 12.8%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `threshold_v` | 0.255000000000 |\n| `delay_s` | 0.340000000000 |\n| `transition_s` | 0.127500000000 |\n| `power_w` | 0.127500000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml","case_sha256":"15a45dfb0015daf6001fe5b5ef6f14c368245cfcfca8bed74fbf773f49575cb4","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl","netlist_sha256":"ac17dacdee7c373b47d4038a7318a7b0fedc024031b06f93011f8eaab684caf4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_001_5t","in_core":false,"title":"Five-Transistor OTA Core with Bias Mirror","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies a differential input using an NMOS pair, PMOS mirror load and a separate bias reference.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_001_5t","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Five-Transistor OTA Core with Bias Mirror Layout Task\n\n## Objective\n\nImplement the fixed six-MOS `amp_001_5t` circuit in IHP SG13G2 and submit a\nself-contained GDS. The circuit consists of a five-transistor OTA core and a\nsixth, diode-connected bias-reference MOS. Device dimensions are fixed.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is authoritative for physical LVS;\n`materials/circuit.spice` is its simulator representation.\n`materials/testbench.spice` defines the AC/DC measurements. Port order is\n`vdd vout vinp vinn ibias vss`: supply, single-ended output, non-inverting input,\ninverting input, reference-current input, and return. Supply 20 uA from `vdd`\ninto `ibias`; it is not an ideal voltage-bias input.\n\nThe NMOS input pair has W/L = 10/10 um; the PMOS mirror pair 10/7 um;\nthe NMOS tail and reference devices 3.8/1 um, all with multiplicity 1.\nThe CDL also declares substrate and well taps. Retain all electrical connections,\nbody connections, sizes and tap devices. Placement and routing are free; normal\nsource/drain equivalence and electrically equivalent device splitting are allowed\nonly when the declared LVS checks accept them. No additional common-centroid or\nstatistical matching requirement is scored.\n\n## Operating Conditions\n\nThe pinned `mos_tt`/`res_typ` models run at 27 C, with VDD = 1.5 V, VSS = 0 V,\n20 uA reference current, 0.8 V non-inverting input bias, and an external 10 pF\noutput load. The 4 GH/4 GF feedback network closes the DC loop and opens the AC\nloop. It is testbench apparatus, not part of the submitted layout. AC sweeps\n1 Hz to 100 MHz at 100 points per decade. The power measurement includes the\nreference-current branch supplied from VDD. The 1e12 ohm numerical shunt is\npart of the declared simulation setup.\n\n## Physical Requirements\n\nSubmit top cell `amp_001_5t`, with all six named electrical ports, no unresolved\nhierarchy, and at most 10 MiB. Artifact, DRC, strict named-port LVS and geometry\nchecks must pass. DRC uses the pinned main and extra/maximal rules without\nwaivers; density and antenna are outside this standalone-block scope.\n\nThe functional bounding box must fit within 120 by 70 um. Its area includes all\nprocess device and routing drawing layers enumerated in the published runtime\nconstraints, including wells, taps, implants, active, poly, contacts, all routing\nmetals/vias and passive/device markers. Annotation text and pin-purpose shapes\nare excluded from area; functional routing must use drawing layers.\n\nThe judge extracts distributed RC from the submitted GDS and simulates that\nextracted DUT. Physical LVS retains explicit taps. Magic models the body\nconnection through its extracted network without the separate compact `ptap1`\nand `ntap1` devices; source calibration records the effect of this boundary.\nThis task covers nominal deterministic AC/DC behavior, not statistical mismatch,\nPVT, noise, distortion, transient settling, EM or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vinp)-v(vinn))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vinp)-v(vinn)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin` | AC: `180+(find (180*cph((v(vout)/(v(vinp)-v(vinn))))/pi) when (db((v(vout)/(v(vinp)-v(vinn)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `bias_voltage` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **1198.35 um2**. 8 expanded device instances; sum of device/contact envelopes 754.0020 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `low_frequency_gain` | 0.270000000000 |\n| `unity_gain_bandwidth` | 0.225000000000 |\n| `phase_margin` | 0.225000000000 |\n| `bias_voltage` | 0.022500000000 |\n| `output_bias` | 0.022500000000 |\n| `supply_power` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed IHP PDK/EDA resources exposed through `/protocol/resources.json`;\nKLayout and Magic support layout checking and extraction, and ngspice supports\nsimulation. `/protocol/task.json` provides the frozen constraints and evaluation\nrequirements; `/protocol/harness.json` describes the active harness.\nIf `process-feedback` is exposed, use its published helper for interim checks.\nWrite `/workspace/output/final.gds`, then explicitly submit it with\n`python -I /protocol/submit.py`. The final judge evaluates the submitted snapshot.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml","case_sha256":"dde3348d36bcf3ff96a8c0ae663883f63be4bf2ddf5cefed06e059520f2ca531","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/circuit.cdl","netlist_sha256":"55016e668fdcbc3087c98af6d92f196225fd586da3a9a8e049200fd0419c119f","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_002_alfio_raffc","in_core":false,"title":"Current-Buffer and Active-Feedforward OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with current-buffered compensation and an active feedforward path to the output.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_002_alfio_raffc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Current-Buffer and Active-Feedforward OTA Layout Task\n\n## Objective\n\nLay out `amp_002_alfio_raffc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS common-source stage\ndrives `net013`, then a PMOS stage and NMOS mirror at `net043` drive the\noutput NMOS. An active feedforward path drives the output PMOS directly\nfrom `net050`. One capacitor connects output to `net063`, the source side\nof the first-stage NMOS cascode; the second connects `net050` to `net013`.\nThe current-buffer compensation terminal and the additional active path\nare real connection differences from the dual-capacitor and shared-resistor\nrepresentatives. This case is not counted from a changed circuit name or size.\n\nThe maintained circuit retains all 24 source MOS groups as 89 physical\nfingers, 4 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. The original W=18/20/30 um devices use 2×9/2×10/3×10 um parallel fingers; the resulting short-width model behavior is calibrated independently.\nThe source's 14.3293 uA sink is external through `net1`. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net1`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net1`\nconnects the external 14.3293 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net063` → `vout`, 3 parallel `cap_cmim` unit(s), each 43.46 × 43.46 um; nominal total 8.520333 pF.\n- `c1`: `net050` → `net013`, 1 parallel `cap_cmim` unit(s), each 36.515 × 36.515 um; nominal total 2.0058602 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_002_alfio_raffc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 1500 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **20690.01 um2**. 96 expanded device instances; sum of device/contact envelopes 13605.7469 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml","case_sha256":"7677b61845c2e61f53047c9ea7b71153fd50135ccc327cf8e9fb62c41d98dbce","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/circuit.cdl","netlist_sha256":"da8813082f4c6fb73b07d677efa730e1f1c250c9ebd438233f3f725346ac88f9","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_003_fan_smc","in_core":false,"title":"Single-Capacitor Three-Stage Feedforward OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with a single compensation capacitor and active feedforward.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_003_fan_smc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Single-Capacitor Three-Stage Feedforward OTA Layout Task\n\n## Objective\n\nLay out `amp_003_fan_smc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; the PMOS stage at `net043`\nand its NMOS mirror drive `net049`, which controls the NMOS output device.\nAn active feedforward path drives the output PMOS directly from `net050`.\nA single physical capacitor branch connects `net050` to output. This is the\nsingle-capacitor representative: there is no second `net049` capacitor or\nseries nulling resistor. The large retained mirror multiplicities and coupled\nthree-stage/feedforward paths require their own loaded recovery calibration.\n\nThe maintained circuit retains all 24 source MOS groups as 412 physical\nfingers, 2 MIM units and 0 high-poly segments. All MOS dimensions/multiplicities are retained exactly.\nThe maintained 3 uA sink is external through `net013`.\nThe source value was 60 uA; the maintained 3 uA bias is a deliberate headroom calibration, not an unchanged upstream operating point. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 3 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `vout`, 2 parallel `cap_cmim` unit(s), each 40.825 × 40.825 um; nominal total 5.0131059 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_003_fan_smc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 2800 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **20940.39 um2**. 417 expanded device instances; sum of device/contact envelopes 13771.5365 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml","case_sha256":"0b4b04cb2457d60b37725c6f3a041541f36de8c315917b83f22d3ae3cddf0460","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/circuit.cdl","netlist_sha256":"5c0aa44f171b64424a7dc717a4d76f332bc9da6b39923f4ae527433622c43601","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_005_hoilee_affc","in_core":false,"title":"Current-Buffered Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a folded input stage and two current-buffered compensation paths.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_005_hoilee_affc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Current-Buffered Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_005_hoilee_affc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS/diode/mirror stage\ndrives `net049`, followed by the NMOS output stage. A parallel path drives\nthe output PMOS directly from `net050`. One capacitor connects `net049` to\noutput. The other connects output to `net1`, the source terminal of an\nadditional common-gate NMOS returning current to `net050`. Six additional\nMOS (XM59–XM64) form this biased current-buffer branch; these devices and\nthe low-impedance compensation terminal distinguish it from direct Miller\nand shared-resistor compensation.\n\nThe maintained circuit retains all 30 source MOS groups as 276 physical\nfingers, 7 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. All source multiplicities are retained.\nThe maintained 3.15498 uA sink is external through `net013`.\nThe external bias is deliberately calibrated to 0.3 times the source current; this is not an unchanged upstream operating point. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 3.15498 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net049` → `vout`, 4 parallel `cap_cmim` unit(s), each 44.775 × 44.775 um; nominal total 12.05746 pF.\n- `c1`: `vout` → `net1`, 3 parallel `cap_cmim` unit(s), each 49.965 × 49.965 um; nominal total 11.258239 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_005_hoilee_affc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 3300 × 140 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **42066.41 um2**. 286 expanded device instances; sum of device/contact envelopes 27776.6506 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml","case_sha256":"bb422bdb3dbdea32fa479906b6aa1c05a91d351148a8dd5dbd10ab10b5d606f6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/materials/circuit.cdl","netlist_sha256":"d16b4edb2bff902499a0519b595961ad69cf940221b11f12a423ef2863685757","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_006_leung_dfcfc1","in_core":false,"title":"Output-Controlled Auxiliary Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with dual compensation paths and an output-controlled auxiliary stage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_006_leung_dfcfc1","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Output-Controlled Auxiliary Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_006_leung_dfcfc1`, retaining the complete folded PMOS-input stage,\nthree-stage signal path, direct output feedforward, and auxiliary compensation.\nThe folded stage drives `net050`, which drives the output PMOS and the\nPMOS/diode/mirror path to `net049`. That node drives both the output NMOS\nand an auxiliary common-source NMOS whose drain is `net1`; a biased PMOS\nloads this auxiliary drain. C0 connects `net050` to output, while C1 connects\n`net049` to `net1`. The auxiliary branch therefore acts on the NMOS output\ncontrol node. In contrast, the separate AMP007 case's auxiliary PMOS senses\n`net050` and its compensation terminates at `net2`.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical device graph.\n- `materials/circuit.spice`: matching simulator representation with finite taps.\n- `materials/testbench.spice`: public bias, bilateral AC and step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD supply,\nVINN/VINP the inverting/noninverting inputs, VOUT output, and `net013` the\nexternal bias-sink connection. Input PMOS bodies connect to the separate\n`net31` source-tied well; other PMOS use the VDD well and NMOS use the VSS\nsubstrate contact. Preserve all 26 MOS groups, 675 physical fingers, W/L/m,\nbody connections, and both internal capacitive branches. Native equivalent\nparallel fingering is allowed only when all physical and electrical checks pass.\n\nThe maintained MOS dimensions are rounded to the actual 10 nm PyCell grid;\nthe 1,413 rounded source fingers are regrouped within their original MOS\ngroups using integer factors, with <=10 um single width. Each group retains\nexactly its rounded total W and L; individual W/m and diffusion perimeter\nchange. Every body connection remains intact. Distributed 2 x 2 um body\ncontacts at <=20 um pitch replace continuous tap strips. All capacitors are physical `cap_cmim`:\n\n- `c0`: `net050` (top plate) to `vout` (bottom plate), 8 parallel 48.935 × 48.935 um MIM units.\n- `c1`: `net049` (top plate) to `net1` (bottom plate), 3 parallel 50.94 × 50.94 um MIM units.\n\nThese are internal compensation devices, distinct from the external load.\nThe normalized source's 27.4754 uA bias is deliberately calibrated to\n6.86885 uA, improving headroom and finite tracking at the declared signal\nlevels. No ideal output servo or internal numerical damping element is added.\n\n## Operating Conditions\n\nUse typical IHP LV MOS/MIM/poly models at 27 C and VDD=1.2 V, with an external\n6.86885 uA sink from `net013` to VSS. Every combination of 5/10/20 pF output\nload and 0.5/0.7 V DC input must pass. A zero-volt source from VINN (`vm`) to\nVOUT closes unity feedback. VINP is AC ground. The two DC input levels\nindependently check operating-point error and the complete sampled return ratio.\n\nAt the closed input/output boundary, inject a series AC voltage with zero\nparallel AC current, then zero series voltage and unit current into `vm`.\nBoth injections retain the original circuit and loading. With first-run\n`b=-I(VPROBE)`, `d=V(vm)` and second-run `a=-I(VPROBE)`, `c=V(vm)`, define\n`delta=a*d-b*c` and the bilateral return ratio\n`T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian et al., Eq. 30).\nThe deck exports both injections' voltages/currents for independent two-port\nadmittance reconstruction. This is a finite external-loop measurement,\nnot a certificate for every internal pole or a complete Nyquist proof.\n\nSweep 0.01 Hz–10 GHz at 300 points/decade. Use continuous phase starting\non its natural low-frequency branch, without a phase-offset correction.\nCheck both first and final descending unity crossings, minimum sampled\n`abs(1+T)`, maximum absolute continuous phase of `1+T` across the entire sweep,\nand maximum gain over 2–10 GHz. Missing crossings or invalid measurements\nare evaluator errors; both first and final phase margins must lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nobservations affect continuous quality and do not establish a stability certificate.\n\nFor each condition, VINP's pulse starts at 0.5 V, rises to 0.7 V at\n2–2.02 us and falls at 10.02–10.04 us, with a 16 us period. Transient uses\nits own pulse-start operating point, independently of the AC DC-input setting.\nSimulate 0–18 us with the KLU linear solver and Gear order 2, 2 ns maximum step, `itl4=1000`,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-12`, and `vntol=1e-8`.\nThe numerical shunt is not a physical device. The maintained 1 pA absolute\ncurrent tolerance is checked at 0.1 pA with tenfold tighter relative/voltage\ntolerances and a 1e13 ohm shunt. Initial experimental 10 fA/1 fA current\ntolerances produced excessive iteration cost in the extracted low-resistance\nnetwork. This numerical-floor calibration preserves every electrical bound\nand all physical/parasitic elements; half-step and trapezoidal controls\nindependently check the observable dynamics. PVT, mismatch, noise,\ndistortion, supply startup, rail-to-rail operation and arbitrary-load stability\nare outside this contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_006_leung_dfcfc1`, at most 32 MiB. Pass native\nIHP main/maximal DRC without waivers (standalone scope, density/antenna off),\nstrict named-interface LVS with explicit taps, and a 6400 × 130 um functional\nenvelope. Every device/contact/interconnect drawing layer listed in the\nruntime `outline` constraint contributes to area; annotation/pin-purpose\nlayers do not. Labels alone do not establish electrical connectivity.\n\nPost-layout simulation uses the submitted GDS's complete Magic RC, with\nphysical MIM devices and interconnect resistances/capacitances. Half-grid\nimport is explicit. Magic retains only Metal3 interface labels in its isolated\nextraction copy to avoid repeated internal well-name aliases, while native LVS\nchecks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics.\nMagic idealizes well/substrate taps, whereas source simulation uses finite\nphysical tap models. Distributed substrate resistance/noise and fabrication\nsignoff remain unqualified. The long independent witness is a feasibility\nlayout, not an area optimum.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_error_v` | DC operating point: `abs(v(vout)-v(vp))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 10g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 10g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=2g to=10g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **82915.92 um2**. 1164 expanded device instances; sum of device/contact envelopes 54901.4182 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nMultiple-crossing feedback amplifiers: loaded recovery 28.6%; loop stability 24.5%; gain and bandwidth 12.3%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `output_error_v` | 0.095454545449 |\n| `recovery_down_v` | 0.095454545455 |\n| `recovery_up_v` | 0.095454545455 |\n| `final_phase_margin_deg` | 0.061363636364 |\n| `minimum_return_distance` | 0.061363636364 |\n| `phase_margin_deg` | 0.061363636364 |\n| `return_phase_excursion_deg` | 0.061363636364 |\n| `dc_gain_db` | 0.030681818182 |\n| `final_unity_hz` | 0.030681818182 |\n| `hf_gain_db` | 0.030681818182 |\n| `unity_hz` | 0.030681818182 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied\nIHP primitives with KLayout, Magic and ngspice. Write\n`/workspace/output/final.gds` and explicitly submit via the harness protocol.\nHost configuration, source records and reference answers are outside solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml","case_sha256":"f1fc328337ea9dc61bf86ec17f7c68052f869111bd9fbd3f03aeaac87f89969b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl","netlist_sha256":"0bfae437fa4eb43463b0ddab03b7d1c9edbe3d7f08fde84a418d30cb3cc137b2","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_007_leung_dfcfc2","in_core":false,"title":"Auxiliary-Stage Miller Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with active feedforward and a separate auxiliary Miller-compensation stage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_007_leung_dfcfc2","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Auxiliary-Stage Miller Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_007_leung_dfcfc2` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; the PMOS/diode/mirror path\ndrives `net049` and then the NMOS output stage. Direct feedforward drives\nthe output PMOS from `net050`. A separate PMOS common-source branch has\ngate `net050`, drain `net2` and an NMOS bias sink. C1 connects `net050` to\noutput; C2 connects `net050` to `net2`, across the auxiliary stage. This\ncompensation branch is distinct from output-to-current-buffer injection and\nfrom the `net049`-controlled auxiliary termination in the other cases.\n\nThe maintained circuit retains all 26 source MOS groups as 440 physical\nfingers, 10 MIM units and 0 high-poly segments. All MOS dimensions/multiplicities are retained exactly.\nThe maintained 20 uA sink is external through `net1`.\nThe source bias-current value is retained. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net1`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net1`\nconnects the external 20 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c1`: `net050` → `vout`, 5 parallel `cap_cmim` unit(s), each 47.61 × 47.61 um; nominal total 17.038429 pF.\n- `c2`: `net050` → `net2`, 5 parallel `cap_cmim` unit(s), each 47.61 × 47.61 um; nominal total 17.038429 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\nThe transient nonlinear iteration ceiling is explicitly `itl4=1000`, with\nunchanged accuracy tolerances. This allows the retained high-multiplicity\nmirror/auxiliary network to converge; it is not a relaxed acceptance limit.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_007_leung_dfcfc2`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 3500 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **52764.97 um2**. 453 expanded device instances; sum of device/contact envelopes 34876.8788 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml","case_sha256":"d13548cc4035967c3e16d35c71b714287fecd68580111da54af663c47ef9733b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/materials/circuit.cdl","netlist_sha256":"3e1d203a196d5cf5f13d15a6c347fcf8c2a907ccddd8b352a845f0fbeff664c0","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_008_leung_nmcf","in_core":false,"title":"Dual-Capacitor Three-Stage OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with two compensation capacitors and output feedforward.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_008_leung_nmcf","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Dual-Capacitor Three-Stage OTA Layout Task\n\n## Objective\n\nLay out `amp_008_leung_nmcf` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS stage at `net043`\nand its NMOS mirror drive `net049`, which controls the NMOS output device.\nA parallel feedforward path drives the output PMOS directly from `net050`.\nTwo capacitive paths connect `net050` to output and `net049` to output.\nThese couple two internal gain nodes to the load, unlike the maintained\ntwo-stage OTA's single Miller path.\n\nThe maintained circuit retains all 24 source MOS groups as 236 physical\nfingers, 3 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. All source multiplicities are retained.\nThe source's 7.52942 uA sink is external through `net013`. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 7.52942 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `vout`, 2 parallel `cap_cmim` unit(s), each 46.95 × 46.95 um; nominal total 6.6279315 pF.\n- `c1`: `net049` → `vout`, 1 parallel `cap_cmim` unit(s), each 30.75 × 30.75 um; nominal total 1.4232638 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_008_leung_nmcf`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 1700 × 130 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **17797.36 um2**. 242 expanded device instances; sum of device/contact envelopes 11690.9447 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml","case_sha256":"9a48c600d5c6530833f21513f58bb8c80c1d5562cc3024fbc0a367545c56cc61","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/materials/circuit.cdl","netlist_sha256":"8e12afdcc86858f64dc3dab7effa448ef1cb877a1c235001b3db1406d36d132a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_009_leung_nmcnr","in_core":false,"title":"Shared-Nulling-Resistor Three-Stage OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages whose compensation capacitors share a nulling resistor.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_009_leung_nmcnr","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Shared-Nulling-Resistor Three-Stage OTA Layout Task\n\n## Objective\n\nLay out `amp_009_leung_nmcnr` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; the PMOS stage at `net043`\nand its NMOS mirror drive `net049`, which controls the NMOS output device.\nThe output PMOS gate connects to the bias mirror, not to `net050`.\nTwo capacitors connect `net050` and `net049` to a common `net044` node;\na physical high-poly resistor connects that junction to output. The shared\nresistance and bias-controlled output PMOS distinguish this circuit from\nboth the dual-capacitor feedforward OTA and the two-stage series-R/C OTA.\n\nThe maintained circuit retains all 24 source MOS groups as 272 physical\nfingers, 3 MIM units and 1 high-poly segments. All MOS dimensions/multiplicities are retained exactly.\nThe source's 3 uA sink is external through `net013`. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 3 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `net044`, 2 parallel `cap_cmim` unit(s), each 40.825 × 40.825 um; nominal total 5.0131059 pF.\n- `c1`: `net044` → `net049`, 1 parallel `cap_cmim` unit(s), each 44.72 × 44.72 um; nominal total 3.0069728 pF.\n- `r0`: `net044` → `vout`, 1 series `rhigh` segment(s), each W=1 um / L=6.94 um, m=1 and b=0; body through the VSS substrate tap.\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating\nevery 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_009_leung_nmcnr`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 2050 × 330 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **18158.97 um2**. 279 expanded device instances; sum of device/contact envelopes 11930.2526 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml","case_sha256":"6e86a09e63e8fc29cefd2776238309c67d68befb9547f4bb8fb7c0b1f9cccd67","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/materials/circuit.cdl","netlist_sha256":"68c55b7866f4dd6640069867385394c0ed2c9b8c026a215df0b2dd381faab6ef","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_010_peng_acbc","in_core":false,"title":"Auxiliary-Branch Compensation OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with feedforward and a compensated auxiliary branch.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_010_peng_acbc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Auxiliary-Branch Compensation OTA Layout Task\n\n## Objective\n\nLay out `amp_010_peng_acbc` with its physical compensation and fixed transistor network,\nfor the declared loop response and sustained unity-feedback step recovery.\n\nThe folded PMOS-input stage drives `net050`; a PMOS/diode/mirror stage\ndrives `net049`, followed by the NMOS output stage. The output PMOS also\nreceives feedforward drive from `net050`. C0 connects `net050` to output,\nwhile C1 connects `net049` to `net1`. The auxiliary node has a bias-fed PMOS,\na diode-connected PMOS and an NMOS controlled by `net043`; this three-device\nbranch creates a distinct active compensation termination. It is neither a\nsecond output-connected Miller capacitor nor the six-MOS current-buffer\nbranch of the other representative.\n\nThe maintained circuit retains all 27 source MOS groups as 237 physical\nfingers, 6 MIM units and 0 high-poly segments. MOS W/L are rounded to the nearest 0.01 um process grid. All source multiplicities are retained.\nThe maintained 1.80825 uA sink is external through `net013`.\nThe external bias is deliberately calibrated to 0.1 times the source current; this is not an unchanged upstream operating point. Physical\nsubstrate and separate N-well contacts retain the input PMOS bodies at their\ncommon source `net31`, electrically separate from the VDD well. No internal\nideal bias source or output servo is introduced. Capacitor values are rounded\nto physical geometry; every branch remains internal to the DUT.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model circuit.\n- `materials/testbench.spice`: public bias, AC injection and transient deck.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is output, and `net013`\nconnects the external 1.80825 uA sink to VSS. Input PMOS bodies retain\nthe separate source-tied well; other PMOS bodies use the VDD well and NMOS\nbodies use the VSS substrate contact. Preserve device W/L/m, body connectivity,\nall internal branches and total multiplicities in the authoritative netlist.\nNative equivalent parallel fingers are allowed only when LVS and electrical\nrequirements pass. Do not short distinct ports or create extra driven monitors.\n\nInternal passives, distinct from the external load:\n\n- `c0`: `net050` → `vout`, 4 parallel `cap_cmim` unit(s), each 50.405 × 50.405 um; nominal total 15.276243 pF.\n- `c1`: `net049` → `net1`, 2 parallel `cap_cmim` unit(s), each 38.31 × 38.31 um; nominal total 4.4152275 pF.\n\n\n## Operating Conditions\n\nUse typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.\nAll output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN\nthrough a zero-volt measurement source. AC injects 1 V in series with this\nfeedback connection, with VINP AC=0. The return ratio is\n`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz\nto 100 MHz at 150 points/decade. Use continuous phase without an arbitrary\nlow-frequency phase-offset correction; the first descending 0 dB crossing\ndefines unity frequency and `180+phase(T)` there defines phase margin.\nA missing crossing is an evaluator error.\n\nVINP rises 0.5→0.7 V at 20–20.1 us and falls at 100.1–100.2 us, repeating\nevery 160 us. Simulate 0–180 us with Gear order 2, 10 ns maximum step,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThe numerical shunt is not a manufactured bias or startup device.\nPVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and\narbitrary-load stability remain outside the contract.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_010_peng_acbc`, at most 10 MiB. Pass native IHP main/maximal\nDRC without waivers (standalone scope; density/antenna disabled), strict\nnamed-interface LVS with explicit taps and a 2100 × 140 um\nfunctional envelope. All functional device, contact and routing drawing layers\nlisted in the runtime `outline` constraint contribute to bounding-box area;\nannotation and pin-purpose layers do not.\n\nPost-layout simulation consumes candidate-derived Magic RC with the physical\nMIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.\nMagic idealizes substrate/well taps; source simulation retains finite tap models.\nDistributed substrate resistance/noise and fabrication signoff are unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=50u to=95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=130u to=175u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=90u to=95u)-(avg v(vout) from=170u to=175u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=20u to=180u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=20u to=100u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=100.2u to=180u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **32926.15 um2**. 246 expanded device instances; sum of device/contact envelopes 21714.0299 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml","case_sha256":"7f37a4c2c0a3922d3b837b9535a5a4e4ff68c0fb822cb09216d32f609b622343","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/materials/circuit.cdl","netlist_sha256":"e8fcd5473160b4dd336813dfb86122e023e06285c6878100e717abe9a4f6aa6f","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_011_peng_iac","in_core":false,"title":"Peng IAC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through three stages with cascoded bias and auxiliary current paths.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_011_peng_iac","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Peng IAC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_011_peng_iac` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded branches feed voutn/voutp. The PMOS bias mirror is cascoded with vb2, generated by XM65/XM63/XM64. XM10 drives net043; XM67/XM68 and XM70 retain the auxiliary current path, with XM69 driving net10 against XM66. XM11/XM23 drive vout. Compensation retains 1.95593 pF between voutp and vout, and 4.33595 pF between net10 and net4 with 1.46466 Mohm from net4 to vss.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 505 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout vb1`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `vb1`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nIHP SG13G2, nominal TT/typical, 27 C, supply 1.5 V, input reference 0.24 V,\nexternal current sink 7.11568e-07 A to vss, and 10 pF output load. Use the fixed IHP LV binding at 1.5 V, adapting the authored 1.8 V stimulus to the LV process rail; retain its bias current and input reference. Round W/L to 10 nm so half-gate contacts remain on grid.\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 2 us (100 ns rise/fall, 18 us high duration), and runs to 40 us with\n2 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nA disconnected timing marker forces exact integration-window endpoints.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 15–20 and 35–40 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 GH inductor and AC-isolates its bias node with 1 kF to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. Both decks use rshunt=1e12 ohm to regularize\notherwise floating extracted nodes; this numerical conductance is applied equally\nto source and candidate and is not a DUT compensation branch. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_011_peng_iac`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nIHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.5 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 2–40 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.5 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=30926.75 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 1.5 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1360 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 8: Active auxiliary current feedback, cascoded bias, and two interacting compensation paths affect finite-window recovery and frequency response.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed IHP SG13G2 resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml","case_sha256":"6a3084040055da18f94c36d2e394ba1614007d8a14df2d9367223caa7eda2e70","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl","netlist_sha256":"3d202284343734913c74c1436446a7dab16631757da8c617aaae8e6f67a2db15","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_012_peng_tcfc","in_core":false,"title":"Auxiliary Source-Driven Output-Control OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a folded input stage and an auxiliary source-driven output-control path.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_012_peng_tcfc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Auxiliary Source-Driven Output-Control OTA Layout Task\n\n## Objective\n\nLay out `amp_012_peng_tcfc` with its complete transistor signal and bias paths.\nThe PMOS-input folded stage produces `voutp`, driving the output PMOS and\n`net043` branch. The large PMOS path through `net049` feeds `net10`, while\n`net043` controls its NMOS pulldown. `net10` drives the output NMOS. Preserve\nboth original compensation branches and the added local output-control MIM.\nUnlike a direct `net050/net049` output stage, this circuit includes the\nsource-driven auxiliary PMOS and a separate `net10` control node.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical graph.\n- `materials/circuit.spice`: equivalent simulator graph with finite body taps.\n- `materials/testbench.spice`: DC, bilateral-loop and sustained-step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout vb1`. VSS/VDD are return/supply;\nVINN/VINP are inverting/noninverting inputs; VOUT is output; `vb1`\nconnects to the external bias sink. Input PMOS bodies use the separate\n`net31` source-tied well; other PMOS use VDD and NMOS use the VSS substrate.\nPreserve all 32 MOS groups, 108 physical fingers,\nW/L/m, every body connection and all physical passive devices.\n\nMOS dimensions are rounded to the 10 nm physical grid. Parallel regrouping\nwithin each original group preserves its rounded total W and L, with at most\n10 um single-finger width; individual width/multiplicity and diffusion perimeter\nchange. Distributed 2 × 2 um body contacts have at most 20 um pitch.\nAll internal capacitors use `cap_cmim`:\n\n- `c0`: `voutp` (top) to `vout` (bottom), 1 parallel 35.325 × 35.325 um MIM units.\n- `c1`: `net049` (top) to `vout` (bottom), 1 parallel 41.2 × 41.2 um MIM units.\n- `clocal`: `net10` (top) to `vout` (bottom), 1 parallel 51.64 × 51.64 um MIM units.\n\nThe raw 1.29849 uA sink is calibrated to 0.16231125 uA. A real approximately\n4 pF `net10–vout` MIM is added to suppress the internal output-control\noscillation. Both original 1.87196 pF `voutp–vout` and 2.54606 pF\n`net049–vout` branches remain. There is no added output-to-ground capacitor.\nNo ideal servo, diagnostic clamp or hidden damping element is part of this DUT.\n\n## Operating Conditions\n\nUse typical IHP LV MOS/MIM/poly models at 27 C and VDD=1.2 V, with a\n0.162311 uA sink from `vb1` to VSS. All combinations of external\n5/10/15 pF load and 0.5/0.7 V DC input must pass. These external loads are\nadditional to every internal capacitor above.\n\nA zero-volt source connects VINN (`vm`) to VOUT. VINP is AC ground.\nUse series voltage and parallel current injection at that boundary, retaining\nthe complete DUT and loading. With voltage-injection `b=-I(VPROBE)`,\n`d=V(vm)` and current-injection `a=-I(VPROBE)`, `c=V(vm)`, set\n`delta=a*d-b*c` and `T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian Eq. 30).\nBoth raw injections are exported for independent Y-matrix reconstruction.\nSweep 0.01 Hz–10 GHz at 300 points/decade. Continuous phase uses its natural\nlow-frequency branch without an offset correction. Check first and final\ndescending unity crossings, minimum sampled `abs(1+T)`, maximum absolute\ncontinuous phase of `1+T` across the entire sweep, and gain over 2–10 GHz.\nA good first crossover alone cannot establish acceptance.\n\nVINP pulses 0.5→0.7→0.5 V with 20 ns edges, rising at 2 us and falling\nat 20.02 us, period 100 us. Transient starts at its own pulse-start operating\npoint, independently of the AC DC-input setting. Simulate 0–40 us with Gear2,\n2 ns maximum step, KLU, `itl4=1000`, `rshunt=1e12`, `reltol=1e-5`,\n`abstol=1e-12`, `vntol=1e-8`. The numerical shunt is not a physical device.\nQualification also checks half step, tighter tolerances/dense AC, trapezoidal\nintegration, long tails and finite stimulus/load boundaries.\nThese are finite external-loop and observable-recovery requirements, not an\ninternal pole inventory, arbitrary-load stability, PVT, noise, mismatch,\ndistortion, rail-to-rail behavior or supply-startup qualification.\n\nFirst and final crossing phase margins must both lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nmetrics affect continuous quality without adding a stability acceptance screen.\nMissing crossings or invalid observations are evaluator errors.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_012_peng_tcfc`, at most 32 MiB. Native IHP main/maximal DRC\nmust pass without waivers (standalone scope, density/antenna off), together\nwith strict named-interface LVS and a 1400 × 160 um functional envelope.\nAll device/contact/interconnect drawing layers in the runtime `outline`\nconstraint contribute to area; annotation/pin-purpose layers do not.\nPost-layout simulation uses the submitted GDS's complete Magic RC, with\nphysical MIM devices and interconnect resistances/capacitances. Half-grid\nimport is explicit. Magic retains only Metal3 interface labels in its isolated\nextraction copy to avoid repeated internal well-name aliases, while native LVS\nchecks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics.\nMagic idealizes well/substrate taps, whereas source simulation uses finite\nphysical tap models. Distributed substrate resistance/noise and fabrication\nsignoff remain unqualified. The long independent witness is a feasibility\nlayout, not an area optimum.\n\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_error_v` | DC operating point: `abs(v(vout)-v(vp))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | bias |\n| `bias_v` | DC operating point: `v(vb1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 10g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 10g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=2g to=10g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=15u to=19u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=30u to=39u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=18u to=19u)-(avg v(vout) from=38u to=39u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=40u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=20u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=20.04u to=40u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **14710.04 um2**. 180 expanded device instances; sum of device/contact envelopes 9648.5648 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nMultiple-crossing feedback amplifiers: loaded recovery 28.6%; loop stability 24.5%; gain and bandwidth 12.3%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `output_error_v` | 0.095454545449 |\n| `recovery_down_v` | 0.095454545455 |\n| `recovery_up_v` | 0.095454545455 |\n| `final_phase_margin_deg` | 0.061363636364 |\n| `minimum_return_distance` | 0.061363636364 |\n| `phase_margin_deg` | 0.061363636364 |\n| `return_phase_excursion_deg` | 0.061363636364 |\n| `dc_gain_db` | 0.030681818182 |\n| `final_unity_hz` | 0.030681818182 |\n| `hf_gain_db` | 0.030681818182 |\n| `unity_hz` | 0.030681818182 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Host configuration, source records\nand reference answers remain outside solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml","case_sha256":"207646009d3117d253c8f92935ff90e4e7fe6c555f6729a251f59252b9cf5237","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl","netlist_sha256":"5d1695a711afd0ce2ecc5a85c10c5c4cb632b5771cc6b7963d4993e28a1edba9","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_013_qu2017_azc","in_core":false,"title":"Qu AZC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through a three-stage network with auxiliary output-control branches.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_013_qu2017_azc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Qu AZC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_013_qu2017_azc` without changing the declared circuit. XM9/XM10 form the PMOS input pair with their bodies tied to the common source net019. XM14–XM17 form the active NMOS load around DM_2/net063; XM4/XM5 convert this to net050. XM11 drives net094 and XM12 with the XM6/XM7 mirror drives net057. XM23/XM24 drive net049; XM13/XM18 drive VOUT. The active compensation retains C0 (net063–VOUT), C1 (net051–vss), C2 (net043–vss), both resistors from net078 to net077/net082, and both resistors from net057 to net051/net043. The entire bias tree and all body relationships remain.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vss vdd vinn vinp vout vb1`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nThe integer-micrometre MOS dimensions are unchanged. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.5 V supply, 0.3 V input reference, 10 pF output load. The external current sink is i0 vb1 vss 1e-06. A direct unity follower receives a 100 mV step at 2 us with 100 ns edges and 8 us high width; falling starts at 10.1 us and completes at 10.2 us. Observe 0–20 us with 0.5 ns maximum step. Report high-window statistics at 8–10 us and return-window statistics at 18–20 us, not a settling time. The rail is adapted from the authored 1.8 V analysis to the actual IHP LV binding; no transistor sizing campaign is performed.\n\nThe transient deck directly connects vinn to vout. The frequency deck closes DC feedback through 1 TH, shunts its remote end by 1 F and injects +0.5/−0.5 V AC at the inputs. This isolates the DC feedback at every measured AC frequency. Residual AC common mode and DC feedback mismatch must each be at most 1 uV; open gain is never inferred from a nearly zero closed-loop input error.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e12 (1 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 10 TOhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_013_qu2017_azc`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `output_v` | V | DC follower output | bias; target |\n| `power_w` | W | DC rail power, -VDD*I(VDD); external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `late_error_v` | V | Mean absolute follower tracking error, 8–10 us | response; ratio; 0 ≤ value |\n| `return_error_v` | V | Mean absolute follower tracking error, 18–20 us | response; ratio; 0 ≤ value |\n| `ripple_v` | V | Full output peak-to-peak range, 8–10 us | response; ratio; 0 ≤ value |\n| `return_ripple_v` | V | Full output peak-to-peak range, 18–20 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted rail power over 2–20 us; external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `bias_v` | V | External current-bias port DC voltage | diagnostic; unscored |\n| `high_v` | V | Mean follower output, 8–10 us | diagnostic; unscored |\n| `low_v` | V | Mean follower output, 18–20 us | diagnostic; unscored |\n| `output_min_v` | V | Minimum output over 0–20 us | diagnostic; unscored |\n| `output_max_v` | V | Maximum output over 0–20 us | diagnostic; unscored |\n| `fixture_cm_max` | V | Residual common-mode excitation in the differential AC fixture | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | DC voltage mismatch across the external feedback inductor | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\nDC bias, 1 Hz/10 kHz differential gain, 10 kHz closed response, tracking error, output range and rail power are distinct observations.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 8079.11 um2 / functional area. The bias scale is 1.5 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 1 mV (1% of the 100 mV step); power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 8 reflects multistage analog routing, active compensation/body connectivity and physical passive matching.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml","case_sha256":"b94ea2bb1b84e7949c8d3f8259e9c11efef6cf4cceacf67eec120736b7961491","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl","netlist_sha256":"482f6b9455334bd331c08b6de22220b5256182a28ee463283da40ab2867df6a6","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_014_ramos_pfc","in_core":false,"title":"Ramos PFC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through a cascoded input and mirror stages into a single-ended output.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_014_ramos_pfc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Ramos PFC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_014_ramos_pfc` with the supplied fixed topology and dimensions. The PMOS input pair drives the cascoded NMOS branches at dm_2/net063; the voutn mirror produces net050. XM10 and the XM21/XM22 mirror drive net049, while XM11/XM23 drive the single-ended output. Both compensation paths remain: 63 pF from net050 to vout and 25 pF from net050 to net049. The vb3/vb4 bias network is retained.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 2583 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout net1`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net1`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nIHP SG13G2, nominal TT/typical, 27 C, supply 1.5 V, input reference 0.4 V,\nexternal current sink 2.4e-05 A to vss, and 10 pF output load. Use the fixed IHP LV binding at 1.5 V, adapting the authored 1.8 V stimulus to the LV process rail; retain its bias current and input reference. Round W/L to 5 nm (the supplied integer-micrometre sizes are unchanged).\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 20 us (100 ns rise/fall, 80 us high duration), and runs to 200 us with\n10 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 80–100 and 180–200 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_014_ramos_pfc`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nIHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.5 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 20–200 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.5 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=190064.1 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 1.5 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1360 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 7: Multistage compensation couples the first-stage node, current-inversion path and output response.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed IHP SG13G2 resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml","case_sha256":"00752bcb24eae77fe9856f4c5f9fbebff3f02938dcb5a2c4f35567c917e1c378","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl","netlist_sha256":"397c4c086e2c70372a03c3e1e0be1323519379a0f9ea38be34814434aff0122c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_015_sau_cfcc","in_core":false,"title":"Input-Driven Active-Feedforward OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a folded input stage and direct input-driven active feedforward.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_015_sau_cfcc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Input-Driven Active-Feedforward OTA Layout Task\n\n## Objective\n\nLay out `amp_015_sau_cfcc` with its complete transistor signal and bias paths.\nThe PMOS-input folded stage produces `voutn`, controlling the mirror at\n`net050` and the auxiliary PMOS at `net049`. The `net050 → net043 → net049`\npath and direct input-driven PMOS feedforward jointly drive the output\nPMOS/NMOS at `net050/net049`. Preserve the original `net063–vout` compensation\nand both explicitly added physical capacitor arrays.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical graph.\n- `materials/circuit.spice`: equivalent simulator graph with finite body taps.\n- `materials/testbench.spice`: DC, bilateral-loop and sustained-step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout net013`. VSS/VDD are return/supply;\nVINN/VINP are inverting/noninverting inputs; VOUT is output; `net013`\nconnects to the external bias sink. Input PMOS bodies use the separate\n`net31` source-tied well; other PMOS use VDD and NMOS use the VSS substrate.\nPreserve all 24 MOS groups, 225 physical fingers,\nW/L/m, every body connection and all physical passive devices.\n\nMOS dimensions are rounded to the 10 nm physical grid. Parallel regrouping\nwithin each original group preserves its rounded total W and L, with at most\n10 um single-finger width; individual width/multiplicity and diffusion perimeter\nchange. Distributed 2 × 2 um body contacts have at most 20 um pitch.\nAll internal capacitors use `cap_cmim`:\n\n- `c0`: `net063` (top) to `vout` (bottom), 1 parallel 51.3 × 51.3 um MIM units.\n- `clocal`: `net050` (top) to `vout` (bottom), 4 parallel 51.64 × 51.64 um MIM units.\n- `cout`: `vout` (top) to `vss` (bottom), 12 parallel 51.64 × 51.64 um MIM units.\n\nThe raw 10.0474 uA sink is calibrated to 1.255925 uA. The original\n3.94789 pF `net063–vout` compensation remains. Approximately 16 pF is added\nat `net050–vout` and another 48 pF at `vout–vss`. These are physical\ncompensation/output-storage devices, included in the netlist, area and\nextracted simulation. This maintained circuit is explicitly not capless.\nNo ideal servo, diagnostic clamp or hidden damping element is part of this DUT.\n\n## Operating Conditions\n\nUse typical IHP LV MOS/MIM/poly models at 27 C and VDD=1.2 V, with a\n1.25592 uA sink from `net013` to VSS. All combinations of external\n5/10/15 pF load and 0.5/0.7 V DC input must pass. These external loads are\nadditional to every internal capacitor above.\n\nA zero-volt source connects VINN (`vm`) to VOUT. VINP is AC ground.\nUse series voltage and parallel current injection at that boundary, retaining\nthe complete DUT and loading. With voltage-injection `b=-I(VPROBE)`,\n`d=V(vm)` and current-injection `a=-I(VPROBE)`, `c=V(vm)`, set\n`delta=a*d-b*c` and `T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian Eq. 30).\nBoth raw injections are exported for independent Y-matrix reconstruction.\nSweep 0.01 Hz–10 GHz at 300 points/decade. Continuous phase uses its natural\nlow-frequency branch without an offset correction. Check first and final\ndescending unity crossings, minimum sampled `abs(1+T)`, maximum absolute\ncontinuous phase of `1+T` across the entire sweep, and gain over 2–10 GHz.\nA good first crossover alone cannot establish acceptance.\n\nVINP pulses 0.5→0.7→0.5 V with 20 ns edges, rising at 2 us and falling\nat 20.02 us, period 100 us. Transient starts at its own pulse-start operating\npoint, independently of the AC DC-input setting. Simulate 0–40 us with Gear2,\n2 ns maximum step, KLU, `itl4=1000`, `rshunt=1e12`, `reltol=1e-5`,\n`abstol=1e-12`, `vntol=1e-8`. The numerical shunt is not a physical device.\nQualification also checks half step, tighter tolerances/dense AC, trapezoidal\nintegration, long tails and finite stimulus/load boundaries.\nThese are finite external-loop and observable-recovery requirements, not an\ninternal pole inventory, arbitrary-load stability, PVT, noise, mismatch,\ndistortion, rail-to-rail behavior or supply-startup qualification.\n\nFirst and final crossing phase margins must both lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nmetrics affect continuous quality without adding a stability acceptance screen.\nMissing crossings or invalid observations are evaluator errors.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_015_sau_cfcc`, at most 32 MiB. Native IHP main/maximal DRC\nmust pass without waivers (standalone scope, density/antenna off), together\nwith strict named-interface LVS and a 3600 × 150 um functional envelope.\nAll device/contact/interconnect drawing layers in the runtime `outline`\nconstraint contribute to area; annotation/pin-purpose layers do not.\nPost-layout simulation uses the submitted GDS's complete Magic RC, with\nphysical MIM devices and interconnect resistances/capacitances. Half-grid\nimport is explicit. Magic retains only Metal3 interface labels in its isolated\nextraction copy to avoid repeated internal well-name aliases, while native LVS\nchecks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics.\nMagic idealizes well/substrate taps, whereas source simulation uses finite\nphysical tap models. Distributed substrate resistance/noise and fabrication\nsignoff remain unqualified. The long independent witness is a feasibility\nlayout, not an area optimum.\n\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_error_v` | DC operating point: `abs(v(vout)-v(vp))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | bias |\n| `bias_v` | DC operating point: `v(net013)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 10g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 10g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=2g to=10g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=15u to=19u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=30u to=39u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=18u to=19u)-(avg v(vout) from=38u to=39u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=40u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=2u to=20u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=20.04u to=40u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **84393.45 um2**. 364 expanded device instances; sum of device/contact envelopes 55883.1016 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nMultiple-crossing feedback amplifiers: loaded recovery 28.6%; loop stability 24.5%; gain and bandwidth 12.3%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `output_error_v` | 0.095454545449 |\n| `recovery_down_v` | 0.095454545455 |\n| `recovery_up_v` | 0.095454545455 |\n| `final_phase_margin_deg` | 0.061363636364 |\n| `minimum_return_distance` | 0.061363636364 |\n| `phase_margin_deg` | 0.061363636364 |\n| `return_phase_excursion_deg` | 0.061363636364 |\n| `dc_gain_db` | 0.030681818182 |\n| `final_unity_hz` | 0.030681818182 |\n| `hf_gain_db` | 0.030681818182 |\n| `unity_hz` | 0.030681818182 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Host configuration, source records\nand reference answers remain outside solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml","case_sha256":"9417f8541247b88cd15964c6ae5121bc7191045b9865491c9012d7387ebd2315","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl","netlist_sha256":"9934cbb25b0b85a604e0e3a453094d54a55c9ea1edfc8d66e6eb3b4fce0a0190","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_016_song_dacfc","in_core":false,"title":"Song DACFC Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a primary signal path and a separately biased auxiliary input pair.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_016_song_dacfc","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Song DACFC Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_016_song_dacfc` with the supplied fixed topology and dimensions. The primary PMOS input pair feeds the cascoded voutn/net4 path. The separate XM57/XM58 input pair, biased by XM59, feeds net043/net049 directly; XM7 also feeds net049 from voutn. XM60/XM61 retain the main cascodes, while XM62/XM63, XM68/XM69 and XM64/XM65/XM70/XM71 retain the auxiliary net70 feedback network. XM11/XM23 drive vout. Both compensation capacitors remain: 1.5 pF from vout to net70 and 0.7 pF from net4 to vss.\nDo not replace the circuit, delete compensation, or add a servo. The physical core\ncontains 472 MOS after expanding explicit upstream multiplicities. Each PMOS\ninput body remains tied to its own tail node through its physical well contact.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its\nmatching simulator representation. `materials/testbench.spice` defines closed-loop\nobservations and `materials/ac.spice` defines balanced differential AC excitation.\nOrdered ports: `vss vdd vinn vinp vout net013`. `vss` is ground, `vdd` supply,\n`vinn/vinp` negative/positive input, `vout` the single-ended output, and `net013`\nthe external bias-current sink. Bias, input drivers, feedback wiring and load are\nexternal test apparatus; taps and all internal R/C are physical DUT elements.\n\n## Operating Conditions\n\nIHP SG13G2, nominal TT/typical, 27 C, supply 1.5 V, input reference 0.3 V,\nexternal current sink 5e-06 A to vss, and 10 pF output load. Use the fixed IHP LV binding at 1.5 V, adapting the authored 1.8 V stimulus to the LV process rail; retain its bias current and input reference. Round W/L to 5 nm (the supplied integer-micrometre sizes are unchanged).\nThe closed-loop deck ties vinn directly to vout, drives vinp with a +100 mV pulse\nstarting at 2 us (100 ns rise/fall, 18 us high duration), and runs to 40 us with\n2 ns maximum steps, Gear order 2, reltol=1e-5, abstol=1 pA, vntol=10 nV.\nA disconnected timing marker forces exact integration-window endpoints.\nTransient starts from the solved DC point; this is not a zero-state supply-ramp\nstartup test. High and return windows are 15–20 and 35–40 us.\n\nAC spans 1 Hz–1 GHz at 200 points/decade. The differential deck retains DC output\nfeedback through a 1 TH inductor and AC-isolates its bias node with 1 F to ground;\nvinp/vinn receive balanced +0.5/-0.5 V small-signal excitation. It verifies residual\ninput common-mode amplitude <=1 uV and DC feedback mismatch <=1 uV. These are external small-signal bias fixtures,\nnot physical compensation. The separate closed-loop deck measures actual follower\nresponse. No voltage-transfer estimate is labeled a loop return ratio.\n\n## Physical Requirements\n\nSupply a GDS <=64 MiB with top cell `amp_016_song_dacfc`, within 20000 by 2000 um\n(the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS\nand functional-area measurement must pass; no marker waivers apply. Preserve\nMOS dimensions, multiplicities, body connections, all physical R/C and tap geometry.\nFunctional layers in the published task include active, implant, wells, gates,\ncontacts, passive plates, vias and routing; annotation/text-only layers are excluded.\nIHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition | Unit | Treatment |\n| --- | --- | --- | --- |\n| gain_db, gain_10khz_db | Balanced differential Vout/(Vinp−Vinn) magnitude at 1 Hz and 10 kHz | dB | Response, source-paired db20 maximize |\n| closed_gain_10khz_db | Actual unity-follower transfer at 10 kHz | dB | Response target, 6 dB scale |\n| output_v | DC follower output | V | Bias target, 1.5 V scale |\n| power_w | DC power drawn from VDD | W | Supply, inverse ratio, 1 pW floor |\n| mean_power_w | Mean supply power over 2–40 us | W | Supply, inverse ratio, 1 pW floor |\n| late_error_v, return_error_v | Mean absolute tracking error in high/return window | V | Response, inverse ratio, 1 mV floor |\n| ripple_v, return_ripple_v | Full output peak-to-peak range in high/return window | V | Response, inverse ratio, 1 mV floor |\n| high_v, low_v | Window means | V | Diagnostic |\n| bias_v | External bias port DC voltage | V | Diagnostic |\n| output_min_v, output_max_v | Full-transient extrema | V | Diagnostic |\n| dc_feedback_error_v | Absolute DC voltage across the external feedback inductor | V | Measurement-validity check, 0–1 uV |\n| fixture_cm_max | Maximum residual common-mode AC drive | V | Measurement-validity check, 0–1 uV |\n\nAll measurements must be finite and complete. Nonnegative supply power and\nabsolute-error/range values follow their physical domains. The common-mode fixture\nbound verifies the differential excitation, not DUT common-mode regulation. The\nDC feedback bound rejects a failed bias-isolation solve. Both checks fail the\nsource or candidate simulation before scoring. These\nare the only electrical hard bounds; upstream paper targets are not gates.\nWindow errors and ripple do not assert settled operation or periodic steady state.\nNo phase margin, unity crossing, settling time, CMRR, noise, PVT or mismatch is claimed.\n\nQuality uses independently simulated same-condition source observations. For gain,\nq=10^((candidate−source)/20); target q=1/(1+abs(candidate−source)/scale);\ninverse-ratio q=(source+floor)/(candidate+floor). The 6 dB target scale corresponds\nto a factor-of-two amplitude change; 1.5 V is the bias normalization and 1 mV is\n1% of the 100 mV test step, preventing numerical zero error from dominating quality.\nArea quality is Q=18074.4 um2/functional_area.\n\nThe compact-area anchor is independent of any reference layout: sum\nm*((W+2.4)*(L+2.4)+3.2^2) um2 over upstream-bound MOS, add 1.2*C/density\nfor capacitors (density 1.5 fF/um2) and 2*R/sheet_resistance um2\nfor resistor contact/routing envelopes (sheet resistance 1360 ohm),\nthen apply a 50% global routing allowance. This is an engineering estimate, not a\nfoundry minimum. Coefficient 8: An auxiliary differential feed-forward path and active net70 compensation interact with the main amplifier and output dynamics.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed IHP SG13G2 resources and the ngspice 45 tools environment.\nThe runtime `/protocol/task.json` supplies frozen requirements and resource bindings.\nSubmit `/workspace/output/final.gds` through the session's explicit submission tool;\nwriting a file alone does not submit it. Evaluation performs artifact, native\nDRC/LVS, geometry, candidate RC, independent source and post-layout simulation.\nThe source baseline, witness and authoring repository are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml","case_sha256":"3ed55b713b9b4dca398869cc7de076adb42fa553862db5d6b2af0066ab05a11c","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl","netlist_sha256":"cc7cee55037a3aa08fbbc4323632ff893f435beea53209e451e1e948293363a4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_021_yan_az","in_core":false,"title":"Yan AZ Three-Stage Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through a cascoded input stage and separate mirror-driven internal branches.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_021_yan_az","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Yan AZ Three-Stage Amplifier Layout Task\n\n## Objective\n\nImplement `amp_021_yan_az` without changing the declared circuit. XM9/XM10 form the PMOS input pair with bodies tied to net019. XM14/XM15 are the cascoded load branches controlled by XM16/XM17 and the net078 resistive network; XM4/XM5 produce net050. XM11/XM22 drive net094, while XM23 and the distinct XM67 mirror branch drive net057. XM13/XM18 drive VOUT. C0 connects net063 to VOUT, C1 shunts net051, and R2 connects net094 to net051; both net078 load resistors remain. AZ denotes the authored active compensation network, not auto-zero clocks.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vss vdd vinn vinp vout vb1`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nW/L are rounded to 10 nm for centred contacts on the 5 nm grid. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.5 V supply, 0.3 V input reference, 10 pF output load. The external current sink is i0 vb1 vss 1.0981e-05. A direct unity follower receives a 100 mV step at 2 us with 100 ns edges and 8 us high width; falling starts at 10.1 us and completes at 10.2 us. Observe 0–20 us with 0.5 ns maximum step. Report high-window statistics at 8–10 us and return-window statistics at 18–20 us, not a settling time. The rail is adapted from the authored 1.8 V analysis to the actual IHP LV binding; no transistor sizing campaign is performed.\n\nThe transient deck directly connects vinn to vout. The frequency deck closes DC feedback through 1 TH, shunts its remote end by 1 F and injects +0.5/−0.5 V AC at the inputs. This isolates the DC feedback at every measured AC frequency. Residual AC common mode and DC feedback mismatch must each be at most 1 uV; open gain is never inferred from a nearly zero closed-loop input error.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e12 (1 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 10 TOhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_021_yan_az`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `output_v` | V | DC follower output | bias; target |\n| `power_w` | W | DC rail power, -VDD*I(VDD); external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `late_error_v` | V | Mean absolute follower tracking error, 8–10 us | response; ratio; 0 ≤ value |\n| `return_error_v` | V | Mean absolute follower tracking error, 18–20 us | response; ratio; 0 ≤ value |\n| `ripple_v` | V | Full output peak-to-peak range, 8–10 us | response; ratio; 0 ≤ value |\n| `return_ripple_v` | V | Full output peak-to-peak range, 18–20 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted rail power over 2–20 us; external current-sink implementation excluded | supply; ratio; 0 ≤ value |\n| `bias_v` | V | External current-bias port DC voltage | diagnostic; unscored |\n| `high_v` | V | Mean follower output, 8–10 us | diagnostic; unscored |\n| `low_v` | V | Mean follower output, 18–20 us | diagnostic; unscored |\n| `output_min_v` | V | Minimum output over 0–20 us | diagnostic; unscored |\n| `output_max_v` | V | Maximum output over 0–20 us | diagnostic; unscored |\n| `fixture_cm_max` | V | Residual common-mode excitation in the differential AC fixture | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | DC voltage mismatch across the external feedback inductor | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\nDC bias, 1 Hz/10 kHz differential gain, 10 kHz closed response, tracking error, output range and rail power are distinct observations.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 24054.76 um2 / functional area. The bias scale is 1.5 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 1 mV (1% of the 100 mV step); power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 8 reflects multistage analog routing, active compensation/body connectivity and physical passive matching.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml","case_sha256":"fff4c6f88be23227dd9a60fb1afd4fa0e2afee8f581454c1a37b053c47893f16","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl","netlist_sha256":"490cbd376da9905b4a78527ec19101306e5a21c01822906a68d15a5cc974394c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_022_fer_two_stage","in_core":false,"title":"Fer Two-Stage Miller Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a PMOS input pair, common-source second stage and Miller capacitor.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_022_fer_two_stage","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fer Two-Stage Miller Amplifier Layout Task\n\n## Objective\n\nImplement `amp_022_fer_two_stage` as a GDS layout preserving the complete declared circuit. PMOS differential input pair, NMOS mirror load, NMOS common-source second stage and PMOS current-source load, retaining Miller CC and the complete NMOS-to-PMOS bias mirror. The 10 bound MOS expand to 63 physical units; CC is a 36.46 um square native MIM (1.999831 pF).\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/ac.spice`: frequency observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vdd vout vinp vinn ibias vss`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\n1.5 V, 27 C, TT LV MOS and typical passives; external 20 uA flows from VDD into ibias. The NMOS diode/mirror drives the PMOS diode: bias/tail/output-load multiplicities are 3:3:17; input-pair multiplicities are 5 each, NMOS load 2 each, and second-stage NMOS 24. The PMOS input bodies remain VDD. vinp is noninverting. The unity follower ties vinn directly to vout. Input is 0.6 V with a +0.2 V pulse at 2 us, 100 ns edges, 8 us high width; falling completes at 10.2 us. The load is 10 pF, maximum transient step 0.5 ns, total window 20 us. High/return statistics use 8–10/18–20 us. Balanced AC uses +0.5/-0.5 V excitation and a 1 TH/1 F DC-feedback isolation network over 1 Hz–1 GHz (200 points/decade). Residual AC common mode and DC feedback mismatch must be at most 1 uV.\n\n## Physical Requirements\n\nIHP native standalone-block DRC, named-port LVS and distributed Magic RC extraction. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. The functional footprint includes active/poly, passives, all routed metals and vias, excluding text and nonfunctional boundary markers. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 2000 by 1000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_v | V | DC follower output | bias; target (scale 1.5) |\n| power_w | W | DC rail power, -VDD*I(VDD); includes external reference current drawn from VDD | supply; ratio (scale 1e-12) |\n| gain_db | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| gain_10khz_db | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| closed_gain_10khz_db | dB | Direct follower output/signal AC gain at 10 kHz | response; target (scale 6) |\n| late_error_v | V | Mean absolute follower tracking error, 8–10 us | response; ratio (scale 0.001) |\n| return_error_v | V | Mean absolute follower tracking error, 18–20 us | response; ratio (scale 0.001) |\n| ripple_v | V | Full output peak-to-peak range, 8–10 us | response; ratio (scale 0.001) |\n| return_ripple_v | V | Full output peak-to-peak range, 18–20 us | response; ratio (scale 0.001) |\n| mean_power_w | W | Time-weighted rail power over 2–20 us; includes external reference current drawn from VDD | supply; ratio (scale 1e-12) |\n| bias_v | V | External current-bias port DC voltage | diagnostic; unscored |\n| high_v | V | Mean follower output, 8–10 us | diagnostic; unscored |\n| low_v | V | Mean follower output, 18–20 us | diagnostic; unscored |\n| output_min_v | V | Minimum output over 0–20 us | diagnostic; unscored |\n| output_max_v | V | Maximum output over 0–20 us | diagnostic; unscored |\n| fixture_cm_max | V | Residual common-mode excitation in the differential AC fixture | diagnostic; unscored |\n| dc_feedback_error_v | V | DC voltage mismatch across the external feedback inductor | diagnostic; unscored |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 7022.72 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 6 covers a complete compensated feedback loop with direct-follower recovery. No numerical node shunt is used. No phase margin, unity-gain crossing, noise or settling-time claim is made.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `return_ripple_v` | 0.112500000000 |\n| `ripple_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.060000000000 |\n| `gain_10khz_db` | 0.060000000000 |\n| `gain_db` | 0.060000000000 |\n| `output_v` | 0.045000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `amp_022_fer_two_stage`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml","case_sha256":"01e6ec6e7364722ccaf64fa089fdcfea8ba0a6c31fdf47b13b7c14aa9491a2b3","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl","netlist_sha256":"2376cfd1faf596940cbb75f9c842a71c603ab59107c0e88575b03a351e5550dc","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_023_fer_fd2s","in_core":true,"title":"Two-Stage Fully Differential OTA with RC Common-Mode Feedback","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies fully differential signals with two output stages, physical R/C compensation and transistor common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_023_fer_fd2s","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Two-Stage Fully Differential OTA with RC Common-Mode Feedback Layout Task\n\n## Objective\n\nImplement `amp_023_fer_fd2s`: an NMOS-input folded first stage, two NMOS\ncommon-source output stages, dual series R/C compensation and transistor\ncommon-mode feedback sensing both outputs through physical R/C arms. Preserve\nall device groups and validate both differential and common-mode behavior in\nthe specified unity differential feedback connection.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit for native LVS.\n- `materials/circuit.spice`: equivalent process-model simulator representation.\n- `materials/testbench.spice`: declared stimuli, differential feedback and measurements.\n\nOrdered ports are `vinp vinn voutp voutn vdd vss ibias vcmr`.\nVINP/VINN are differential inputs; VOUTP/VOUTN are differential outputs;\nVDD/VSS are supply/return; IBIAS receives 20 uA from VDD; VCMR receives the\ncommon-mode reference relative to VSS. The bias mirrors and common-mode\ncontroller stay in the DUT. Do not replace the internal controller with an\nideal servo or omit physical passive devices.\n\nRetain all 28 MOS groups' fixed W/L/m (50 individual transistors), models and\nconnectivity. Equivalent parallel fingering/native merging is allowed if all\nchecks pass. NMOS and resistor bodies connect through the explicit substrate\ntap to VSS; PMOS bodies connect through the well tap to VDD. Keep supplies,\nbody connections and ordered ports faithful to the circuit.\n\nEach output compensation path has a W=1 um, L=0.96 um `rhigh` (nominally\n1.52 kohm at 27 C) between `o1a`/`o1b` and `za`/`zb`, followed by two parallel\n25.85 × 25.85 um `cap_cmim` units to the corresponding output (2.01294 pF).\nEach output-to-`vsen` sensing arm contains eight series W=1 um, L=18 um\n`rhigh` segments (nominally 205.28 kohm total), in parallel with a\n9.95 × 9.95 um MIM (150.096 fF). Resistors use m=1, b=0. These internal\ndevices are separate from external output loads; they must be physically\nimplemented with the same terminal mapping. Internal nodes are not bias ports.\n\n## Operating Conditions\n\nUse typical MOS, capacitor and resistor models, 27 C, 1.2 V supply, 20 uA\nfrom VDD to IBIAS, and input common mode 0.5 V. Each output has an external\n1, 5 or 10 pF load. For each load, evaluate paired positive and negative\nstimuli: `step_v` is +0.1 or −0.1 V and `kick_a` is respectively +100 or\n−100 uA. All six conditions must pass.\n\nDefine `d=VOUTP−VOUTN` and `c=(VOUTP+VOUTN)/2`. The external differential\nfeedback apparatus drives `VINP=0.5+(VSIG−d)/2` and\n`VINN=0.5−(VSIG−d)/2`, through zero-volt series probes. It holds input\ncommon mode and closes differential unity feedback. It does not force output\ncommon mode: the actual DUT controller, its two R/C sense arms and actual\noutput stages close that loop.\n\nAt DC, VSIG=0 and VCMR=0.75 V. Differential AC uses opposite +0.5/−0.5 V\nseries probe excitations and sweeps 1 Hz–1 GHz at 150 points/decade. Measure\n`A=d/(VINP−VINN)`; its sign is retained. Low-frequency gain is dB magnitude\nat 1 Hz; unity frequency is the first falling 0 dB crossing; phase margin is\n180 degrees plus continuous phase there, without subtracting an arbitrary\nphase offset. A missing crossing is an error. This voltage-injection return\nratio is scoped to the high-impedance input and declared unity feedback.\n\nCommon-mode AC sets both series probe AC magnitudes to zero and VCMR AC=1 V,\nkeeping differential feedback closed. Sweep 1 Hz–1 GHz at 100 points/decade.\nMeasure `abs(c/VCMR)` at 1 Hz and its maximum over the complete sweep.\nThis is closed-loop common-mode tracking/peaking, not an internal common-mode\nloop phase-margin measurement.\n\nThe transient sequence runs 0–8 us using Gear order 2 with maximum step 1 ns.\nUse `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-13`, `vntol=1e-8`.\nVSIG rises from zero to `step_v` during 1–1.005 us, holds for 4 us, and\nreturns during 5.005–5.010 us. VCMR rises 0.75→0.8 V during 3–3.005 us,\nholds for 1 us, and returns during 4.005–4.010 us. Thus reference tracking\nis tested while a nonzero differential output is present. Equal current\nsources inject `kick_a` into both outputs during a 6–6.060 us pulse:\n5 ns rise, 50 ns hold and 5 ns fall. Negative `kick_a` withdraws current.\nThe pulse periods are 20 us; only this finite 8 us sequence is measured.\nNo startup initialization is imposed; transient starts from the solved DC point.\n\n## Physical Requirements\n\nSubmit GDSII top cell `amp_023_fer_fd2s`, at most 10 MiB. Pass native IHP\nmain/maximal DRC without waivers (standalone scope, density/antenna disabled),\nstrict named-port LVS with physical taps, and a 1200 × 400 um functional\noutline. Include all device, contact and routing drawing layers enumerated by\nthe runtime outline constraint. Pin-purpose and annotation layers do not\ncontribute to bounding-box area and cannot conceal functional geometry.\n\nPost-layout measurements must consume the candidate-derived Magic RC netlist,\nincluding physical passives, transistor junction geometry and interconnect.\nThe extraction configuration subdivides Magic's initial grid by two before\nGDS import and imports its isolated copy with `gds_readonly=false`; the submitted\nGDS remains immutable. No extraction error is waived. Device parameters,\ngeometry and port connectivity must survive extraction. Magic idealizes\nwell/substrate taps; source simulation retains their finite process models.\nDistributed substrate resistance/noise and fabrication signoff are outside scope.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_cm_v` | DC operating point: `(v(outp)+v(outn))/2`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `output_dm_v` | DC operating point: `v(outp)-v(outn)`. | V | target / target | −∞ … +∞ | 1.2 | bias |\n| `bias_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dm_gain_db` | AC: Value of `(db(((v(outp)-v(outn))/(v(inp)-v(inn))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db(((v(outp)-v(outn))/(v(inp)-v(inn)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph(((v(outp)-v(outn))/(v(inp)-v(inn))))/pi) when (db(((v(outp)-v(outn))/(v(inp)-v(inn)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `cm_gain_vv` | AC: Value of `(mag(((v(outp)+v(outn))/2))) at=1`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `cm_peak_vv` | AC: Maximum of `(mag(((v(outp)+v(outn))/2)))`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `dm_up_error_v` | TRAN: Maximum of `(abs((v(outp)-v(outn))-v(sig))) from=1.5u to=1.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `dm_down_error_v` | TRAN: Maximum of `(abs((v(outp)-v(outn))-v(sig))) from=5.5u to=5.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_up_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=3.5u to=3.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_down_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=4.5u to=5.9u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_kick_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=6.5u to=7.9u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_kick_peak_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=6u to=6.5u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `dm_peak_v` | TRAN: Maximum of `(abs((v(outp)-v(outn)))) from=1u to=5u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=0 to=8u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dm_cm_error_v` | TRAN: Maximum of `(abs((v(outp)-v(outn))-v(sig))) from=3.5u to=3.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_dm_error_v` | TRAN: Maximum of `(abs(((v(outp)+v(outn))/2)-v(ref))) from=1.5u to=1.95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `dm_high_v` | TRAN: Mean of `(v(outp)-v(outn)) from=1.8u to=1.95u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `cm_high_v` | TRAN: Mean of `((v(outp)+v(outn))/2) from=3.8u to=3.95u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n\nArea reference: **8435.0 um2**. 76 expanded device instances; sum of device/contact envelopes 5503.6687 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **9**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nDifferential amplifier with CMFB: differential recovery 22.5%; common-mode recovery 22.5%; cross-coupling 9%; loop margin 13.5%; AC transfer 9%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `dm_down_error_v` | 0.075000000000 |\n| `dm_peak_v` | 0.075000000000 |\n| `dm_up_error_v` | 0.075000000000 |\n| `cm_down_error_v` | 0.056250000000 |\n| `cm_kick_error_v` | 0.056250000000 |\n| `cm_kick_peak_v` | 0.056250000000 |\n| `cm_up_error_v` | 0.056250000000 |\n| `cm_dm_error_v` | 0.045000000000 |\n| `dm_cm_error_v` | 0.045000000000 |\n| `phase_margin_deg` | 0.135000000000 |\n| `cm_gain_vv` | 0.022500000000 |\n| `cm_peak_vv` | 0.022500000000 |\n| `dm_gain_db` | 0.022500000000 |\n| `unity_hz` | 0.022500000000 |\n| `bias_v` | 0.015000000000 |\n| `output_cm_v` | 0.015000000000 |\n| `output_dm_v` | 0.015000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover task inputs, frozen requirements, reviewed resources and harness\nfeedback through `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the supplied IHP primitives and KLayout, Magic\nand ngspice. Write `/workspace/output/final.gds` and explicitly submit using\nthe harness protocol. Reference GDS, source records and host configuration\nremain outside standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml","case_sha256":"9d100090b3a7df8bad339688f9f705251ab92674b7f974b87053bdd944576885","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/circuit.cdl","netlist_sha256":"4c52bdbbe491a400eff644efb33e0e97af38d50073ccb1a5a5a76964931f569c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_024_smcnr","in_core":false,"title":"Series-Nulling-Resistor Two-Stage OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals through two stages with a physical series nulling resistor in the Miller path.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_024_smcnr","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Series-Nulling-Resistor Two-Stage OTA Layout Task\n\n## Objective\n\nLay out `amp_024_smcnr`, a PMOS-input two-stage OTA with series R/C Miller\ncompensation, for stable loaded unity-feedback response. Preserve the eight\nMOS groups' fixed W/L/m, physical compensation network and explicit bias interface.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model simulation representation.\n- `materials/testbench.spice`: nominal bias, loop-gain and finite-step measurements.\n\nOrdered ports: `vss vdd vinn vinp vout ibias`. VSS is return, VDD is supply,\nVINN/VINP are inverting/noninverting inputs, VOUT is the output, and IBIAS\nconnects an external 100 nA current sink to VSS. The bias mirror remains inside\nthe DUT. No ideal source is a layout device. NMOS and resistor bodies connect\nthrough the explicit substrate tap to VSS; PMOS bodies connect through the\nwell tap to VDD. Preserve device models and total W/L/m; equivalent parallel\nMOS fingers and native resistor merging are allowed when LVS and all other\nrequirements pass. Supply and return must remain distinct.\n\nThe internal compensation path is `outn` → two parallel MIM units → `nzo` →\nfour series high-poly segments → `vout`. Each `cap_cmim` is 25.85 × 25.85 um,\nnominally 1.00647 pF; each `rhigh` is W=1 um, L=18 um, m=1, b=0, giving\napproximately 100 kohm for the chain with the process model. These are DUT\ndevices, separately from the external load. Do not delete or replace them with\nideal parasitic annotations. Internal nodes are not extra bias ports.\n\n## Operating Conditions\n\nUse typical MOS, capacitor and resistor models at 27 C, 1.2 V supply and a\n100 nA external bias sink. External output loads are 5, 10 and 20 pF. All\nthree conditions must pass. Qualification is nominal and does not cover PVT,\nmismatch, rail-to-rail operation or arbitrary output loads.\n\nAt DC, VINP=0.5 V and VOUT feeds VINN through the zero-volt probe. AC uses a\n1 V series injection at this feedback connection, VINP AC=0, and\n`T=-V(vout)/V(vm)`. Sweep 0.01 Hz–100 MHz at 150 points/decade. Gain is\n`20 log10(abs(T))`; phase is its continuous phase without subtracting a fitted\nlow-frequency offset. Unity frequency is the first descending 0 dB crossing;\nphase margin is 180 degrees plus phase there. Missing crossings are errors.\nThis voltage-injection measurement uses the high-impedance MOS input boundary.\n\nTransient keeps the zero-volt feedback connection. VINP rises 0.5→0.7 V from\n20 to 20.1 us, falls from 100.1 to 100.2 us, and repeats every 160 us. Simulate\n0–180 us using Gear order 2 with 50 ns maximum step. Use `rshunt=1e12`,\n`reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`. This weak numerical shunt is\npart of the declared simulator boundary, not a physical bias or startup source.\n\n## Physical Requirements\n\nSubmit GDSII with top cell `amp_024_smcnr`, at most 10 MiB. Pass native IHP\nmain plus maximal DRC (standalone scope, density/antenna disabled), strict\nnamed-port LVS with physical taps, and a 650 × 80 um functional envelope.\nThere are no case DRC waivers. All functional devices, contacts and routing\nmust lie on the drawing layers listed in the runtime `outline` constraint;\nannotation/pin-purpose layers do not contribute to its bounding-box area.\n\nPost-layout simulation must consume the candidate's Magic RC extraction,\nincluding physical R/C devices and extracted interconnect. Well/substrate taps\nare ideal connections in this extractor, rather than the finite source tap\nmodels; this is not a distributed substrate or substrate-noise model. The\nOSDI resistor model and MOS/MIM model resources must be available.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `bias_v` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=50u to=95u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=130u to=175u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `step_gain` | Transient: `((avg v(vout) from=90u to=95u)-(avg v(vout) from=170u to=175u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=20u to=180u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `peak_v` | TRAN: Maximum of `v(vout) from=20u to=100u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n| `trough_v` | TRAN: Minimum of `v(vout) from=100.2u to=180u`. | V | target / target | 0 … 1.2 | 1.2 | response |\n\nArea reference: **5869.81 um2**. 35 expanded device instances; sum of device/contact envelopes 3813.4378 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **7**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCompensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.143181818182 |\n| `recovery_up_v` | 0.143181818182 |\n| `phase_margin_deg` | 0.204545454543 |\n| `dc_gain_db` | 0.081818181818 |\n| `unity_hz` | 0.081818181818 |\n| `peak_v` | 0.027272727273 |\n| `step_gain` | 0.027272727273 |\n| `trough_v` | 0.027272727273 |\n| `bias_v` | 0.020454545455 |\n| `output_v` | 0.020454545455 |\n| `mean_power_w` | 0.061363636364 |\n| `power_w` | 0.061363636364 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover task, inputs, resources and harness feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives and KLayout, Magic and ngspice tools. Write `/workspace/output/final.gds`\nand explicitly submit through the harness protocol. Host configuration, source\nrecords and reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml","case_sha256":"b88a4f25693448653662ea6fe34a6a5d65c57a1f1e81e11e63be837ff2633ab8","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/materials/circuit.cdl","netlist_sha256":"0b9a0afed61b6479a3c7cb1b8c6581ab8ad8623db88c3d5515137be83de4399c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_026_fan_chopper_ota","in_core":false,"title":"Fan Two-Stage OTA with Static Output Chopper","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a two-stage core and an output chopper held in its straight-through state.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_026_fan_chopper_ota","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Two-Stage OTA Layout Task\n\n## Objective\n\nImplement the supplied 23-MOS, two-capacitor two-stage OTA with its statically straight-through output chopper. Preserve all devices, connections and dimensions. The cross branches remain present and off; no CMFB exists or may be added. Four MIM units realize the two 6 pF compensation capacitors (44.67 um square each).\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4`. Preserve these named connections.\n\nThe native CDL and simulator SPICE describe the same circuit. VINP/VINN are\nthe differential inputs; VOUTP/VOUTN are outputs; VDD/VSS are supply/return;\nVB1 through VB4 are bias ports. Independent bias sources are outside the physical core. Physical well/substrate taps are included.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode 0.6 V; vb1/vb2/vb3/vb4=0.3983759766/0.65/0.45/0.55 V. Loads are 1 and 10 pF per output. Differential steps are ±50 mV at 10 us, returning at 40.02 us; 5 uA per output common-mode injection runs from 60 to 61.02 us. Maximum transient step is 2 ns, duration 100 us. An external ideal differential unity-feedback fixture drives the signal test; it does not sense or regulate output common mode. AC transfer divides the output difference by the actual input difference.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and strict named-interface LVS must pass. Keep the supplied tap geometry and compact-device parameters consistent. Functional device, well, contact and routing layers define area; annotation layers do not. The bounding rectangle must fit 5000 by 1000 um. No DRC waivers apply.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nAll declared measurements must be finite and use the extracted candidate. Gain and phase at 10 Hz/100 kHz, output bias, supply power, small differential step response, common-mode kick and recovery are observed by the supplied deck. Step response subtracts 8–9 us baseline from 38–39 us response. The common-mode baseline is 58–59 us; kick peak is 60–62 us and residual is 98–99 us. Continuous quality uses independently simulated same-condition source observations. The physical-domain checks are nonnegative supplied power and nonnegative absolute errors; they are not upstream specifications.\n\nQ is 14924.75 um2 divided by functional area. The anchor sums (W+2.4)(L+2.4) for each MOS and 3.2² um2 for each local tap and one global tap, adds four (44.67+2.4)² um2 MIM envelopes, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (50 mV scale), with common-mode kick/recovery retained as unscored diagnostics because this core has no common-mode regulator; bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 7 reflects multistage compensation and loaded differential response; common-mode drift and kick response remain observations, not proof of regulation. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `cm_bias_v` | `(v(outp)+v(outn))/2` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `dm_bias_v` | `v(outp)-v(outn)` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `power_w` | `-v(vdd)*i(VDD)-v(vb1)*i(VB1)-v(vb2)*i(VB2)-v(vb3)*i(VB3)-v(vb4)*i(VB4)` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `gain_db` | `find gain at=10` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `gain_100khz_db` | `find gain at=100k` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `phase_100khz_deg` | `find phase_deg at=100k` | deg | target / target / response | −∞ … +∞ | 180 |\n| `step_response_v` | `dm_high_v-dm_before_v` | V | target / target / response | −∞ … +∞ | 0.05 |\n| `cm_before_v` | `avg cm from=58u to=59u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_kick_v` | `max cm_delta from=60u to=62u` | V | functional check | 0 … +∞ | — |\n| `cm_recovery_v` | `max cm_delta from=98u to=99u` | V | functional check | 0 … +∞ | — |\n| `cm_min_v` | `min cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\n\n\n### Score weights\n\nDifferential OTA cores: differential response 66%; bias 6%; power 18%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_100khz_db` | 0.165000000000 |\n| `gain_db` | 0.165000000000 |\n| `phase_100khz_deg` | 0.165000000000 |\n| `step_response_v` | 0.165000000000 |\n| `cm_bias_v` | 0.030000000000 |\n| `dm_bias_v` | 0.030000000000 |\n| `power_w` | 0.180000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the reviewed IHP resources. Submit only the GDS with top cell amp_026_fan_chopper_ota. Evaluation runs native DRC/LVS, area, candidate-derived Magic RC extraction and ngspice post-layout observations. The source circuit is independently simulated for scoring.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml","case_sha256":"6b14c7474639d3bf338882eb43da15b4fb4e756e135b88c6ef88d53de44b29fe","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl","netlist_sha256":"232e765fe36c1fdd781bd26c556b0418f9bd53f3e39011fd244d67fd463e52c4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_027_fan_rrl_ota","in_core":false,"title":"Fan Telescopic OTA with Transistor DDA-CMFB","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals using a telescopic core with transistor common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_027_fan_rrl_ota","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Telescopic OTA Layout Task\n\n## Objective\n\nImplement the supplied 16-MOS telescopic OTA with its transistor DDA-CMFB. Preserve all devices, connections and dimensions. This task contains only the OTA core.\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4`. Preserve these named connections.\n\nThe native CDL and simulator SPICE describe the same circuit. VINP/VINN are\nthe differential inputs; VOUTP/VOUTN are outputs; VDD/VSS are supply/return;\nVB1 through VB4 are bias ports. Independent bias sources are outside the physical core. Physical well/substrate taps are included.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode 0.6 V; vb1/vb2/vb3/vb4=0.45/0.75/0.55/0.6 V. Loads are 1 and 10 pF per output. Differential steps are ±20 uV at 10 us, returning at 40.02 us; 5 uA per output common-mode injection runs from 60 to 61.02 us. Maximum transient step is 2 ns, duration 100 us. This is an open-loop signal test with the internal CMFB operating.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and strict named-interface LVS must pass. Keep the supplied tap geometry and compact-device parameters consistent. Functional device, well, contact and routing layers define area; annotation layers do not. The bounding rectangle must fit 5000 by 1000 um. No DRC waivers apply.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nAll declared measurements must be finite and use the extracted candidate. Gain and phase at 10 Hz/100 kHz, output bias, supply power, small differential step response, common-mode kick and recovery are observed by the supplied deck. Step response subtracts 8–9 us baseline from 38–39 us response. The common-mode baseline is 58–59 us; kick peak is 60–62 us and residual is 98–99 us. Continuous quality uses independently simulated same-condition source observations. The physical-domain checks are nonnegative supplied power and nonnegative absolute errors; they are not upstream specifications.\n\nQ is 1035.78 um2 divided by functional area. The anchor sums (W+2.4)(L+2.4) for each MOS and 3.2² um2 for each local tap and one global tap, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (1 mV scale), and inverse absolute common-mode error (1 uV floor); bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 6 reflects the complete signal amplifier coupled to a transistor common-mode recovery loop. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `cm_bias_v` | `(v(outp)+v(outn))/2` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `dm_bias_v` | `v(outp)-v(outn)` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `power_w` | `-v(vdd)*i(VDD)-v(vb1)*i(VB1)-v(vb2)*i(VB2)-v(vb3)*i(VB3)-v(vb4)*i(VB4)` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `gain_db` | `find gain at=10` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `gain_100khz_db` | `find gain at=100k` | dB | maximize / db20 / response | −∞ … +∞ | — |\n| `phase_100khz_deg` | `find phase_deg at=100k` | deg | target / target / response | −∞ … +∞ | 180 |\n| `step_response_v` | `dm_high_v-dm_before_v` | V | target / target / response | −∞ … +∞ | 0.001 |\n| `cm_before_v` | `avg cm from=58u to=59u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_kick_v` | `max cm_delta from=60u to=62u` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `cm_recovery_v` | `max cm_delta from=98u to=99u` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `cm_min_v` | `min cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=0 to=100u` | V | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\n\n\n### Score weights\n\nDifferential OTA cores: differential response 49.5%; common-mode recovery 22.5%; bias 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_100khz_db` | 0.123750000000 |\n| `gain_db` | 0.123750000000 |\n| `phase_100khz_deg` | 0.123750000000 |\n| `step_response_v` | 0.123750000000 |\n| `cm_kick_v` | 0.112500000000 |\n| `cm_recovery_v` | 0.112500000000 |\n| `cm_bias_v` | 0.022500000000 |\n| `dm_bias_v` | 0.022500000000 |\n| `power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **6 hours**.\n\nUse the reviewed IHP resources. Submit only the GDS with top cell amp_027_fan_rrl_ota. Evaluation runs native DRC/LVS, area, candidate-derived Magic RC extraction and ngspice post-layout observations. The source circuit is independently simulated for scoring.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml","case_sha256":"d7a5554c046d4b527e851cabc1929099f376234d0cc452cdea4c3cca4f94bbdc","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl","netlist_sha256":"afb6faf1d0f260f490f7bd748612c8d10ebbef233154362b853c867b9012b33e","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_029_two_stage_miller_comp","in_core":false,"title":"Differential Two-Stage Miller Amplifier Without CMFB","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies fully differential signals through two Miller-compensated stages without common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_029_two_stage_miller_comp","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Differential Two-Stage Miller Amplifier Without CMFB Layout Task\n\n## Objective\n\nImplement `amp_029_two_stage_miller_comp` as a GDS layout preserving the complete declared circuit. Fully differential NMOS-input two-stage Miller amplifier without CMFB. Ten physical MOS retain both PMOS first-stage current sources, both PMOS common-source output drivers, NMOS reference/tail/output sinks, and both series R/C Miller branches. VBL and the 20 uA reference source are external apparatus.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit and ordered named interface.\n- `materials/circuit.spice`: equivalent source simulation, including physical passives.\n- `materials/testbench.spice`: performance observations.\n- `materials/ac.spice`: frequency observations.\n- `problem.md`: this contract.\n\nOrdered ports: `vinp vinn voutp voutn vdd vss ref vbl`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs.\n\n## Operating Conditions\n\n1.2 V, 27 C, TT LV MOS and typical passives; inputs have 0.6 V common mode, VBL=0.7087 V and 20 uA flows from VDD into ref. Each output has 10 pF to ground. The fixed binding uses 30 kohm and 0.4 pF per Miller branch, represented by native rhigh/MIM. Open AC drives +0.5/-0.5 V at 1 Hz–1 GHz, 200 points/decade, with no DC or AC common-mode feedback. The separate closed test uses external differential feedback vp=0.6+(signal-voutp+voutn)/2 and vm=0.6-(signal-voutp+voutn)/2. It fixes input common mode only; it neither senses nor servos output common mode. A 10 mV signal pulse starts at 2 us with 100 ns edges and 8 us high width. Maximum transient step is 1 ns through 20 us. Report 8–10 and 18–20 us windows. Closed and open DC differential offsets may differ because one fixture closes differential feedback; their input common mode and external bias are identical.\n\n## Physical Requirements\n\nIHP native standalone-block DRC, named-port LVS and distributed Magic RC extraction. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. The functional footprint includes active/poly, passives, all routed metals and vias, excluding text and nonfunctional boundary markers. No DRC waivers are declared. The core topology, body connections and physical compensation are fixed. Geometrically equivalent implementations must retain the named ports and device parameters. Functional bounds are 2000 by 1000 um; they bound the supported block footprint, not electrical quality.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Unit | Definition | Assignment |\n|---|---|---|---|\n| output_cm_v | V | DC output common mode | bias; target (scale 1.2) |\n| offset_v | V | DC differential output offset | bias; target (scale 0.01) |\n| power_w | W | DC rail power including external current bias | supply; ratio (scale 1e-12) |\n| gain_db | dB | Balanced open differential AC gain at 1 Hz | response; db20 |\n| gain_10khz_db | dB | Balanced open differential AC gain at 10 kHz | response; db20 |\n| late_error_v | V | Mean absolute differential tracking error 8–10 us | response; ratio (scale 0.001) |\n| return_error_v | V | Mean absolute differential tracking error 18–20 us | response; ratio (scale 0.001) |\n| ripple_v | V | Differential peak-to-peak output 8–10 us | response; ratio (scale 0.001) |\n| fixture_cm_max | V | fixture_cm_max | diagnostic; unscored |\n| high_v | V | high_v | diagnostic; unscored |\n| low_v | V | low_v | diagnostic; unscored |\n| cm_min_v | V | cm_min_v | diagnostic; unscored |\n| cm_max_v | V | cm_max_v | diagnostic; unscored |\n| kcl_a | A | Absolute external DC current-balance residual; producer validity guard at 10 nA | diagnostic; unscored |\n\nAll required jobs must finish with finite valid measurements. The 10 nA DC KCL residual bounds numerical validity; nonnegative power/error/range bounds follow their physical definitions. Additional fixture validity bounds are stated above and in runtime task metadata. There are no data-sheet gain, regulation-accuracy or speed gates. Failed extraction, invalid measurements and missing jobs cannot be replaced by low scores.\n\nEach scored candidate observation is paired with the independent source observation in the identical condition. Ratio-minimize uses (source+scale)/(candidate+scale); target uses scale/(scale+abs(candidate-source)); db20-maximize uses 10^((candidate-source)/20). Scores are continuous and not capped at 100. Each metric uses its worst same-condition paired quality. Diagnostics are unscored. Source results, not the reference GDS, define performance normalization. The 1 mV error/ripple floors and 1 pW power floors regularize zero values; they are not acceptance tolerances. Target scales use the stated rail/output voltage or differential step amplitude.\n\nArea anchor: 2278.38 um2. 1.5 times the sum over expanded physical MOS, resistor and capacitor units of (W + 4 um)*(L + 4 um). The 4 um allowances cover local contacts/isolation; 50% covers compact routing. Body taps are covered by the allowance, not counted twice. This is an analytical compact-area anchor, not the witness footprint.\n\nCoefficient 6 covers the compensated differential feedback experiment. No CMFB is added. Miller capacitors are open at DC and provide no DC common-mode feedback. A large parasitic-induced common-mode shift and reduced differential response are continuous quality losses. These finite-window measurements do not certify robust biasing, settling, phase margin or useful product gain. No numerical node shunt is used.\n\n\n### Score weights\n\nFinite-window amplifier response: tracking error 36%; ripple 22.5%; AC transfer 18%; bias and offset 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `late_error_v` | 0.180000000000 |\n| `return_error_v` | 0.180000000000 |\n| `ripple_v` | 0.225000000000 |\n| `gain_10khz_db` | 0.090000000000 |\n| `gain_db` | 0.090000000000 |\n| `offset_v` | 0.022500000000 |\n| `output_cm_v` | 0.022500000000 |\n| `power_w` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `amp_029_two_stage_miller_comp`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-08 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml","case_sha256":"bfd0997869c87d352f280ef91aa2dfead89c6876e5ae19bf4d362a19a4620ca6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl","netlist_sha256":"7f89e7956013c5963092250563b16713f48f9a31dd350503d0e5fb7d7d408923","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_034_fan_chopper_cmfb","in_core":false,"title":"Fan Output CMFB OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a folded first stage, static output chopper and output common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_034_fan_chopper_cmfb","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Output CMFB OTA Layout Task\n\n## Objective\n\nImplement `amp_034_fan_chopper_cmfb` without changing the declared circuit. The fixed upstream flattened composite contains a PMOS input pair, folded-cascode first stage, statically straight-through transmission-gate output chopper and common-source second stage. Its own seven-transistor PMOS-input CMFB detects the output mean through two 1 MOhm resistors and drives vb4o, exclusively controlling XM8O/XM9O. The tail and folded PMOS sources retain the separate external core__vb4 bias. Both 6 pF Miller branches and the 1 fF vb4o compensation branch remain. This is the upstream composite itself, not a servo added during Bench integration.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm core__out1_p core__out1_n vb4o`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nW/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. The subminimum 1 fF CCM is realized by seven series 7.016 fF MIM units (2.11 um sides), approximately 1.002 fF equivalent. Intermediate nodes and their physical parasitics are retained in both source and candidate models. The branch is never omitted. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.2 V supply, 0.6 V input common mode, 10 pF on each output. The external voltage sources are vb1_core core__vb1 vss dc 0.3983759766; vb2_core core__vb2 vss dc 0.65; vb3_core core__vb3 vss dc 0.45; vb4_core core__vb4 vss dc 0.55; vrefcm vref_cm vss dc 0.5. Both the no-disturbance condition and the following combined sequence run for 150 us with a 2 ns maximum step. The differential command rises from 0 to 10 mV at 10 us and returns after 10 us; equal +20 uA currents enter both outputs at 30 us for 2 us. The output reference rises by 25 mV at 50 us for 15 us; input common mode rises by 25 mV at 75 us for 15 us. The stage-1 reference is not an interface of this circuit. All edges are 20 ns. Pulse widths are measured after the rising edge, so falling edges start one edge duration after nominal delay plus width. The unperturbed condition sets every step and kick amplitude to zero. The two CMFB loops, where present, remain connected throughout. Monitor ports are unloaded; their extraction and routing parasitics remain. No external clock is applied: straight-through chopper gates stay tied to their actual rails, and crossed paths stay off.\n\nThe external fixture enforces inp = icm + (signal − (outp−outn))/2 and inn = icm − (signal − (outp−outn))/2. It closes only the differential measurement loop; the DUT transistors close common-mode feedback. The frequency deck retains this DC feedback, isolates each feedback branch with 1 TH/1 F low-pass elements and injects +0.5/−0.5 V AC. The actual differential excitation remains 1 V and residual common-mode must be at most 1 uV.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e12 (1 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 10 TOhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_034_fan_chopper_cmfb`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `cm_quiet_v` | V | avg cm, 5–9 us | bias; target |\n| `cm_pre_kick_v` | V | avg cm, 28–29 us | bias; target |\n| `cm_recovery_v` | V | avg cm, 45–49 us | bias; target |\n| `cm_ref_v` | V | avg cm, 60–64 us | bias; target |\n| `cm_input_cm_v` | V | avg cm, 85–89 us | bias; target |\n| `cm_stage_ref_v` | V | avg cm, 120–124 us | bias; target |\n| `cm_late_v` | V | avg cm, 145–149 us | bias; target |\n| `cm_quiet_pp_v` | V | pp cm, 5–9 us | response; ratio; 0 ≤ value |\n| `cm_late_pp_v` | V | pp cm, 145–149 us | response; ratio; 0 ≤ value |\n| `cm_kick_v` | V | max cm_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `cm_recovery_error_v` | V | avg cm_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `s1_quiet_v` | V | avg s1, 5–9 us | bias; target |\n| `s1_pre_kick_v` | V | avg s1, 28–29 us | bias; target |\n| `s1_recovery_v` | V | avg s1, 45–49 us | bias; target |\n| `s1_ref_v` | V | avg s1, 60–64 us | bias; target |\n| `s1_input_cm_v` | V | avg s1, 85–89 us | bias; target |\n| `s1_stage_ref_v` | V | avg s1, 120–124 us | bias; target |\n| `s1_late_v` | V | avg s1, 145–149 us | bias; target |\n| `s1_quiet_pp_v` | V | pp s1, 5–9 us | response; ratio; 0 ≤ value |\n| `s1_late_pp_v` | V | pp s1, 145–149 us | response; ratio; 0 ≤ value |\n| `s1_kick_v` | V | max s1_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `s1_recovery_error_v` | V | avg s1_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `dm_high_error_v` | V | avg dmerror, 18–19 us | response; ratio; 0 ≤ value |\n| `dm_return_error_v` | V | avg dmerror, 25–29 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted delivered power over the declared transient window | supply; ratio; 0 ≤ value |\n| `cm_bias_v` | V | DC cm_bias_v | bias; target |\n| `s1_bias_v` | V | DC s1_bias_v | bias; target |\n| `dm_bias_v` | V | DC dm_bias_v | bias; target |\n| `power_w` | W | DC delivered power from DUT supply and declared external bias/reference sources | supply; ratio; 0 ≤ value |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `fixture_cm_max` | V | Fixture validity fixture_cm_max | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | Fixture validity dc_feedback_error_v | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\n`cm` is the output mean and `s1` is the first-stage mean. Quiet/pre-kick/recovery/reference/input-CM/stage-reference/late windows are 5–9, 28–29, 45–49, 60–64, 85–89, 120–124 and 145–149 us. Recovery is relative to each run’s pre-kick mean; it is not a claim of asymptotic settling. All window values are evaluated for both zero-stimulus and disturbed conditions.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 20711.65 um2 / functional area. The bias scale is 1.2 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 0.1 mV for differential error (1% of the 10 mV step) and 1 mV for common-mode excursions; power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 8 reflects the folded multistage differential core, transistor common-mode control and physical compensation.\n\n\n### Score weights\n\nOne/two-loop CMFB amplifier assemblies: output common-mode dynamics 33.8%; stage-1 common-mode dynamics 5.62%; differential tracking 22.5%; AC transfer 11.2%; common-mode operating points 5.62%; power 11.2%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `cm_kick_v` | 0.084375000000 |\n| `cm_late_pp_v` | 0.084375000000 |\n| `cm_quiet_pp_v` | 0.084375000000 |\n| `cm_recovery_error_v` | 0.084375000000 |\n| `s1_kick_v` | 0.014062500000 |\n| `s1_late_pp_v` | 0.014062500000 |\n| `s1_quiet_pp_v` | 0.014062500000 |\n| `s1_recovery_error_v` | 0.014062500000 |\n| `dm_high_error_v` | 0.112500000007 |\n| `dm_return_error_v` | 0.112500000000 |\n| `closed_gain_10khz_db` | 0.037500000000 |\n| `gain_10khz_db` | 0.037500000000 |\n| `gain_db` | 0.037500000000 |\n| `cm_bias_v` | 0.003308823529 |\n| `cm_input_cm_v` | 0.003308823529 |\n| `cm_late_v` | 0.003308823529 |\n| `cm_pre_kick_v` | 0.003308823529 |\n| `cm_quiet_v` | 0.003308823529 |\n| `cm_recovery_v` | 0.003308823529 |\n| `cm_ref_v` | 0.003308823529 |\n| `cm_stage_ref_v` | 0.003308823529 |\n| `dm_bias_v` | 0.003308823529 |\n| `s1_bias_v` | 0.003308823529 |\n| `s1_input_cm_v` | 0.003308823529 |\n| `s1_late_v` | 0.003308823529 |\n| `s1_pre_kick_v` | 0.003308823529 |\n| `s1_quiet_v` | 0.003308823529 |\n| `s1_recovery_v` | 0.003308823529 |\n| `s1_ref_v` | 0.003308823529 |\n| `s1_stage_ref_v` | 0.003308823529 |\n| `mean_power_w` | 0.056250000000 |\n| `power_w` | 0.056250000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml","case_sha256":"0987c00cb47a0baa86dcee578ed4c9ad0252ab81190f5ad0dd65ff9f419ae416","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl","netlist_sha256":"1898e7ade5f22a3a7785fcc52bb04bce6a9405a9b63a01f0b01da6ad316e00a3","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.amp_035_fan_chopper_cmfb_dual","in_core":false,"title":"Fan Dual CMFB OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a static output chopper and separate stage/output common-mode feedback loops.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_035_fan_chopper_cmfb_dual","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Dual CMFB OTA Layout Task\n\n## Objective\n\nImplement `amp_035_fan_chopper_cmfb_dual` without changing the declared circuit. The independently frozen flattened composite contains the PMOS input/folded-cascode first stage, static straight-through output chopper and common-source second stage. One seven-transistor CMFB detects the output mean through two 1 MOhm resistors and drives XM8O/XM9O on vb4o. A second seven-transistor CMFB detects stg1_p/stg1_n through two 50 MOhm resistors and drives vb4_ctl, controlling the first-stage tail and folded PMOS sources. The 50 MOhm override, distinct 0.3265 V stage reference, 100 pF inner-loop compensation and both 6 pF Miller capacitors remain. Neither loop is replaced or independently opened to infer joint stability.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 vref_out vref_s1 stg1_p stg1_n vb4o vb4_ctl`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core.\n\nW/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary.\n\n## Operating Conditions\n\nTT MOS, typical MIM/high-poly, 27 C, 1.2 V supply, 0.6 V input common mode, 10 pF on each output. The external voltage sources are vb1_core core__vb1 vss dc 0.3983759766; vb2_core core__vb2 vss dc 0.65; vb3_core core__vb3 vss dc 0.45; vrefout vref_out vss dc 0.5; vrefs1 vref_s1 vss dc 0.3265. Both the no-disturbance condition and the following combined sequence run for 150 us with a 2 ns maximum step. The differential command rises from 0 to 10 mV at 10 us and returns after 10 us; equal +20 uA currents enter both outputs at 30 us for 2 us. The output reference rises by 25 mV at 50 us for 15 us; input common mode rises by 25 mV at 75 us for 15 us. The stage-1 reference rises by 10 mV at 110 us for 15 us. All edges are 20 ns. Pulse widths are measured after the rising edge, so falling edges start one edge duration after nominal delay plus width. The unperturbed condition sets every step and kick amplitude to zero. The two CMFB loops, where present, remain connected throughout. Monitor ports are unloaded; their extraction and routing parasitics remain. No external clock is applied: straight-through chopper gates stay tied to their actual rails, and crossed paths stay off.\n\nThe external fixture enforces inp = icm + (signal − (outp−outn))/2 and inn = icm − (signal − (outp−outn))/2. It closes only the differential measurement loop; the DUT transistors close common-mode feedback. The frequency deck retains this DC feedback, isolates each feedback branch with 1 TH/1 F low-pass elements and injects +0.5/−0.5 V AC. The actual differential excitation remains 1 V and residual common-mode must be at most 1 uV.\n\nBoth decks sweep 1 Hz–1 GHz at 200 points/decade. AC describes the linearization of the verified DC point, not proof of a dynamically stable equilibrium. An explicit rshunt=1e14 (100 TOhm) numerical shunt to ground at each node regularizes otherwise floating extraction/series-capacitor nodes; source and candidate use the identical setting. Sensitivity is checked with 1 POhm. Supply startup is not simulated: transient starts from the DC operating point, and the no-disturbance interval tests whether that point persists. Use the default sparse solver with pivtol=1e-18, below the numerical shunt conductance, and the tolerances declared in the decks.\n\n## Physical Requirements\n\nSubmit a native SG13G2 GDS with top cell `amp_035_fan_chopper_cmfb_dual`, at most 67108864 bytes, within 20000 × 2000 um. Native main and maximal DRC, named-interface LVS and geometry must pass without marker waivers. Keep every MOS, body connection and passive path. Unit multiplicities and the declared passive series/parallel realization are fixed in the materials.\n\nThe functional footprint includes active, gate, contact, metal, via, MIM and complete routing shapes; well, text, annotations and nonfunctional markers alone do not define it. The runtime task supplies the exact layer set. Candidate GDS drives native connectivity extraction and distributed wire resistance/ground capacitance extraction, then the same native MOS/MIM/high-poly simulation models used by the source. This nominal MOS/R/C boundary does not assert RF/coupling extraction, PVT, mismatch, noise or manufacturing signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nEvery declared simulation must complete with finite measurements and complete raw records. Transient means use full-precision cumulative integration with interpolated endpoint corrections; incomplete windows are errors. PP denotes the full finite-window range, including any oscillation or slow drift. No phase margin, loop gain, settling time or periodic steady state is claimed.\n\n| Metric | Unit | Definition | Quality role / functional domain |\n| --- | --- | --- | --- |\n| `cm_quiet_v` | V | avg cm, 5–9 us | bias; target |\n| `cm_pre_kick_v` | V | avg cm, 28–29 us | bias; target |\n| `cm_recovery_v` | V | avg cm, 45–49 us | bias; target |\n| `cm_ref_v` | V | avg cm, 60–64 us | bias; target |\n| `cm_input_cm_v` | V | avg cm, 85–89 us | bias; target |\n| `cm_stage_ref_v` | V | avg cm, 120–124 us | bias; target |\n| `cm_late_v` | V | avg cm, 145–149 us | bias; target |\n| `cm_quiet_pp_v` | V | pp cm, 5–9 us | response; ratio; 0 ≤ value |\n| `cm_late_pp_v` | V | pp cm, 145–149 us | response; ratio; 0 ≤ value |\n| `cm_kick_v` | V | max cm_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `cm_recovery_error_v` | V | avg cm_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `s1_quiet_v` | V | avg s1, 5–9 us | bias; target |\n| `s1_pre_kick_v` | V | avg s1, 28–29 us | bias; target |\n| `s1_recovery_v` | V | avg s1, 45–49 us | bias; target |\n| `s1_ref_v` | V | avg s1, 60–64 us | bias; target |\n| `s1_input_cm_v` | V | avg s1, 85–89 us | bias; target |\n| `s1_stage_ref_v` | V | avg s1, 120–124 us | bias; target |\n| `s1_late_v` | V | avg s1, 145–149 us | bias; target |\n| `s1_quiet_pp_v` | V | pp s1, 5–9 us | response; ratio; 0 ≤ value |\n| `s1_late_pp_v` | V | pp s1, 145–149 us | response; ratio; 0 ≤ value |\n| `s1_kick_v` | V | max s1_delta, 30–33 us | response; ratio; 0 ≤ value |\n| `s1_recovery_error_v` | V | avg s1_delta, 45–49 us | response; ratio; 0 ≤ value |\n| `dm_high_error_v` | V | avg dmerror, 18–19 us | response; ratio; 0 ≤ value |\n| `dm_return_error_v` | V | avg dmerror, 25–29 us | response; ratio; 0 ≤ value |\n| `mean_power_w` | W | Time-weighted delivered power over the declared transient window | supply; ratio; 0 ≤ value |\n| `cm_bias_v` | V | DC cm_bias_v | bias; target |\n| `s1_bias_v` | V | DC s1_bias_v | bias; target |\n| `dm_bias_v` | V | DC dm_bias_v | bias; target |\n| `power_w` | W | DC delivered power from DUT supply and declared external bias/reference sources | supply; ratio; 0 ≤ value |\n| `closed_gain_10khz_db` | dB | Direct follower output/signal AC gain at 10 kHz | response; target |\n| `gain_db` | dB | Balanced differential open AC gain at 1 Hz | response; db20 |\n| `gain_10khz_db` | dB | Balanced differential open AC gain at 10 kHz | response; db20 |\n| `fixture_cm_max` | V | Fixture validity fixture_cm_max | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n| `dc_feedback_error_v` | V | Fixture validity dc_feedback_error_v | diagnostic; unscored; 0 ≤ value ≤ 1e-06 |\n\n`cm` is the output mean and `s1` is the first-stage mean. Quiet/pre-kick/recovery/reference/input-CM/stage-reference/late windows are 5–9, 28–29, 45–49, 60–64, 85–89, 120–124 and 145–149 us. Recovery is relative to each run’s pre-kick mean; it is not a claim of asymptotic settling. All window values are evaluated for both zero-stimulus and disturbed conditions.\n\nPerformance is continuously paired with the independently simulated source under exactly the same conditions. Gain quality is 10^((candidate−source)/20); target quality is 1/(1+abs(candidate−source)/scale); inverse-ratio quality is (source+floor)/(candidate+floor). Area quality is Q = 361466.3 um2 / functional area. The bias scale is 1.2 V; closed-response scale is 6 dB (factor two in amplitude). Error/range floors are 0.1 mV for differential error (1% of the 10 mV step) and 1 mV for common-mode excursions; power floor is 1 pW. Physical/domain and fixture-validity gates are not upstream product targets.\n\nThe compact-area anchor sums m*((W+2.4)*(L+2.4)+3.2^2) um2 for MOS, 1.2*C/(1.5 fF/um2) for physical capacitor envelopes, and 2*R/(1360 Ohm) um2 for resistor envelopes, then adds 50% global routing allowance. It is an engineering estimate independent of the reference GDS. Coefficient 9 reflects two interacting transistor CM loops, high-impedance sensing and large physical passive networks.\n\n\n### Score weights\n\nOne/two-loop CMFB amplifier assemblies: output common-mode dynamics 27%; stage-1 common-mode dynamics 22.5%; differential tracking 18%; AC transfer 9%; common-mode operating points 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `cm_kick_v` | 0.067500000000 |\n| `cm_late_pp_v` | 0.067500000000 |\n| `cm_quiet_pp_v` | 0.067500000000 |\n| `cm_recovery_error_v` | 0.067500000000 |\n| `s1_kick_v` | 0.056250000000 |\n| `s1_late_pp_v` | 0.056250000000 |\n| `s1_quiet_pp_v` | 0.056250000000 |\n| `s1_recovery_error_v` | 0.056250000000 |\n| `dm_high_error_v` | 0.089999999992 |\n| `dm_return_error_v` | 0.090000000000 |\n| `closed_gain_10khz_db` | 0.030000000000 |\n| `gain_10khz_db` | 0.030000000000 |\n| `gain_db` | 0.030000000000 |\n| `cm_bias_v` | 0.002647058824 |\n| `cm_input_cm_v` | 0.002647058824 |\n| `cm_late_v` | 0.002647058824 |\n| `cm_pre_kick_v` | 0.002647058824 |\n| `cm_quiet_v` | 0.002647058824 |\n| `cm_recovery_v` | 0.002647058824 |\n| `cm_ref_v` | 0.002647058824 |\n| `cm_stage_ref_v` | 0.002647058824 |\n| `dm_bias_v` | 0.002647058824 |\n| `s1_bias_v` | 0.002647058824 |\n| `s1_input_cm_v` | 0.002647058824 |\n| `s1_late_v` | 0.002647058824 |\n| `s1_pre_kick_v` | 0.002647058824 |\n| `s1_quiet_v` | 0.002647058824 |\n| `s1_recovery_v` | 0.002647058824 |\n| `s1_ref_v` | 0.002647058824 |\n| `s1_stage_ref_v` | 0.002647058824 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the reviewed SG13G2 resources and ngspice 45 tool environment. The runtime `/protocol/task.json` publishes frozen inputs, requirements and tool bindings. Submit `/workspace/output/final.gds` explicitly through the session submission tool; writing the file alone does not submit it. The evaluation executes native checks, candidate-derived RC and independent paired source/post-layout simulations. The reference GDS, maintainer README and development checkout are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml","case_sha256":"d6ca987ce5e07f0cbae536f0db86b9f6a21d5a85966fdf885a02101fdf3fe3ef","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl","netlist_sha256":"70db9a09e47cfaf6dc9aecb394d7300c2d6125f26d16252ff1ba67688085165c","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.buf_001_super_follower","in_core":false,"title":"MIM-Compensated Local-Feedback Source Follower","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Buffers a signal with local feedback and physical MIM compensation.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/buf_001_super_follower","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# MIM-Compensated Local-Feedback Source Follower Layout Task\n\n## Objective\n\nImplement `buf_001_super_follower` in ihp-sg13g2 and submit self-contained GDS. Six MOS entries expand to 17 physical MOS instances in a local-feedback source follower. Fixed IHP W/L/m are retained. The internal na-to-VSS 250 fF compensation is implemented as a 12.85 by 12.85 um cap_cmim (nominally 249.74 fF at 27 C, including model perimeter capacitance); it is not removed or moved to the output. Explicit physical taps and the MIM dimensions are common to LVS, source simulation and extracted simulation.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit. `materials/circuit.spice` is its equivalent simulator model-call representation. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `vdd vout vin ibias vss`. In order: Supply, output, signal input, reference-current input, and return.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical IHP low-voltage MOS and resistor models and typical capacitor models; explicit finite physical tap models and a 1e12 ohm ngspice numerical shunt at each node. Candidate Magic RC is extracted with zero coupling-capacitance threshold.\n\nVDD = 1.5 V; VSS = 0 V; a 20 uA current source from VDD into ibias. VIN = 0.55 V DC, AC amplitude 1 V. External output loads are 5, 10 and 20 pF. AC uses 100 points/decade from 1 Hz to 1 GHz. VIN stays at 0.55 V through 1 us, ramps to 0.65 V at 1.001 us, holds through 3 us, ramps back at 3.001 us and holds through 5 us. Transient output/max step is 0.2 ns. Recovered errors compare output to its 2.5 us and 0.5 us samples, over 1.5–2.9 us and 3.5–4.9 us respectively.\n\n## Physical Requirements\n\nTop cell `buf_001_super_follower`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, IHP main and maximal DRC, with density and antenna outside this standalone scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 160 by 45 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. This is a level-shifting source follower with about 0.84 small-signal gain, not a unity-gain rail-to-rail buffer. Qualification is restricted to the stated low-input range; higher input bias compresses the gain. Noise, mismatch, other input levels, PVT and RF/EM are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 3 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | DC output/control voltage | V | target / target | 0 … 1.5 | 1.5 |\n| `bias_v` | DC V(ibias) | V | target / target | 0 … 1.5 | 1.5 |\n| `power_w` | DC power delivered by VDD, -V(vdd)*I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 |\n| `gain_vv` | Magnitude V(vout) at 10 Hz with unit AC input | V/V | target / target | −∞ … +∞ | 1.0 |\n| `bandwidth_hz` | First falling 3 dB crossing relative to the 10 Hz gain | Hz | maximize / ratio | 0 … +∞ | — |\n| `step_gain` | (Vout at 2.5 us - Vout at 0.5 us) / 0.1 V | V/V | target / target | −∞ … +∞ | 1.0 |\n| `recovery_up_v` | Maximum absolute recovered error over the upward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `recovery_down_v` | Maximum absolute recovered error over the downward-step window | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `mean_power_w` | Time-average -V(vdd)*I(VDD) over the complete transient | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **1242.88 um2**. 20 expanded device instances; sum of device/contact envelopes 782.8540 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSuper source follower: loaded recovery 36%; source-follower transfer 27%; bandwidth 13.5%; bias 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `recovery_down_v` | 0.180000000000 |\n| `recovery_up_v` | 0.180000000000 |\n| `gain_vv` | 0.135000000000 |\n| `step_gain` | 0.135000000000 |\n| `bandwidth_hz` | 0.135000000000 |\n| `bias_v` | 0.022500000000 |\n| `output_v` | 0.022500000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml","case_sha256":"9791170a62118768f8f4cc2a9def54e1334a2aea69723fbd1e886cf372c326a7","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/circuit.cdl","netlist_sha256":"2f617c485f1bd1d94d47a1fc21c6c1e815fb9f4a4278ee93c2a1eb80b80a4404","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.cmfb_002_5t_pmos_input","in_core":false,"title":"PMOS-Input Common-Mode Detector and Controller","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Detects and controls common-mode voltage with a PMOS-input feedback core.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_002_5t_pmos_input","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# PMOS-Input Common-Mode Detector and Controller Layout Task\n\n## Objective\n\nImplement `cmfb_002_5t_pmos_input` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. Seven MOS implement a PMOS-input five-transistor OTA plus the PMOS/NMOS diode bias branch. Two 1 Mohm sensing arms each use four series physical high-poly units. The pinned IHP widths/lengths are quantized to the 10 nm drawing grid, including the 0.29 um bias NMOS. Bodies and all sensing/bias devices are retained.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vinp vinn vcmfb vref vdd vss`. The resistor midpoint senses input common mode. Reference and input sources are external. This is a standalone detector/controller; it contains neither a controlled amplifier nor a complete common-mode feedback loop. Fixture dependent voltage sources only establish specified input voltages and are outside the DUT.\n\n## Operating Conditions\n\n1.5 V supply; 0.5 and 0.7 V input common mode and equal reference. Output has 1 pF to ground and 10 Mohm to the common-mode source. At each bias, separate unit AC common-mode, reference and balanced differential excitations cover 1 Hz–100 MHz. Verify zero differential component in common-mode excitation and zero common-mode component in differential excitation. Centered 2 mV DC sweeps separately vary the common-mode or reference source. Separate 1 mV common-mode/reference or 100 mV differential steps start at 20 us, have 100 ns edges and last 40 us. The 100 us transient starts at DC, maximum step 20 ns. Rail power includes both diode bias devices, but excludes fixture driver losses. No external plant/servo, solver shunt or forced state.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `cmfb_002_5t_pmos_input`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. Magic uses ideal well/substrate tap connections; source simulation retains native finite tap models. This boundary does not establish distributed substrate resistance or substrate-noise accuracy.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 4 covers a compact gain/bias/passive network. Nonnegative common-mode and nonpositive reference DC slopes are functional sign-domain constraints. Both include zero and do not establish a minimum response magnitude. Reported response/ripple windows do not certify a closed-loop CM regulator or upstream optimization claims.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `output_v` | V | Natural loaded output with zero CM error | bias / target; scale 1.5 | lower=0; upper=1.5 |\n| `power_w` | W | Rail power including dual-diode bias | supply / ratio; scale 1e-12 | lower=0 |\n| `signed_gain` | 1 | Real transfer at 1 Hz, selected CM/reference/differential input | response / target; scale 1 | Finite measurement |\n| `gain_1khz` | 1 | Magnitude at 1 kHz, selected excitation | response / target; scale 1 | Finite measurement |\n| `gain_100khz` | 1 | Magnitude at 100 kHz, selected excitation | response / target; scale 1 | Finite measurement |\n| `step_response_v` | V | Mean response 50–60 us minus 10–20 us | response / target; scale 0.01 | Finite measurement |\n| `ripple_v` | V | Recovery window output variation | response / ratio; scale 0.0001 | lower=0 |\n| `dc_cm_slope` | 1 | Centered 2 mV DC output slope for dc_cm_slope | response / target; scale 1 | lower=0 |\n| `dc_ref_slope` | 1 | Centered 2 mV DC output slope for dc_ref_slope | response / target; scale 1 | upper=0 |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; current-validity and KCL bounds distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **10500 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (15 units, sum 5245.926900 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **4**.\n\n\n### Score weights\n\nCommon-mode sensing/controllers: signed transfer 45%; ripple 19.3%; output bias 6.43%; power 19.3%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `dc_cm_slope` | 0.075000000000 |\n| `dc_ref_slope` | 0.075000000000 |\n| `gain_100khz` | 0.075000000000 |\n| `gain_1khz` | 0.075000000000 |\n| `signed_gain` | 0.075000000000 |\n| `step_response_v` | 0.075000000000 |\n| `ripple_v` | 0.192857142857 |\n| `output_v` | 0.064285714286 |\n| `power_w` | 0.192857142857 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml","case_sha256":"e7c7ec054ba2113ab41ab9c43a845ac046c5c90136a5c3a3cb533254145e0435","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl","netlist_sha256":"9d0cf10dd16c7a3e2e929dc7fe72dbfb0dd5f4d53f52574e92414e293c903d45","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.cmfb_004_output_switched_cap","in_core":false,"title":"MIM Switched-Capacitor Common-Mode Sampler","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Samples common-mode voltage using clocked switches and physical MIM capacitors.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_004_output_switched_cap","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# MIM Switched-Capacitor Common-Mode Sampler Layout Task\n\n## Objective\n\nImplement `cmfb_004_output_switched_cap` in IHP SG13G2 and submit a self-contained GDS. Sixteen minimum-size MOS (W/L = 0.15/0.13 um) implement eight transmission paths. Four internal MIM capacitors retain the original connections: two separate vbias-to-vcm capacitors and two floating control-to-sense capacitors. Each is a 25.85 by 25.85 um cap_cmim, nominally about 1.00647 pF. Explicit physical substrate and well taps are included. The output samples common-mode displacement; this is a switched-capacitor sensing network with driven inputs, not a complete closed-loop amplifier or a loop-stability qualification.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` supplies measurement apparatus. This problem is the description input. The ordered ports are `vinp vinn vcmfb vcm vbias clk_phi clk_phi_not vdd vss`: sensed positive/negative inputs, sampled control output, common-mode reference, control reference, two independent clock nets, supply and return.\n\nPreserve connectivity, MOS W/L/m, capacitor dimensions and unit multiplicities, and body/tap connections. Placement and routing are free. Device splitting/combination and source/drain interchange are allowed only when accepted by the declared native LVS equivalences. No common-centroid or statistical matching requirement is scored. All specified ideal external sources, loads and measurement apparatus belong outside the DUT.\n\n## Operating Conditions\n\nTypical IHP low-voltage MOS, typical resistor and capacitor models at 27 C; VDD = 1.5 V and VSS = 0 V. Each node has the declared 1e12 ohm numerical shunt. Transient integration uses Gear order 2 with a 1 ns output and maximum step. Physical taps have finite source-model resistance; Magic treats well/substrate ties ideally. Distributed silicon substrate resistance, statistical mismatch, PVT, noise and RF/EM are outside scope.\n\nVcm = 0.75 V; Vbias = 0.6 V. Each condition starts with input common mode 0.75 V. It changes linearly over 40–40.1 us to common_v, then holds through 100 us. Inputs are common mode +/- diff_v. The five (common_v, diff_v) pairs in volts are (0.65,0), (0.65,0.1), (0.75,0.1), (0.85,0), (0.85,0.1). Phi starts high, falls after 1 us, and alternates with its complementary independent clock; rise/fall times are 2 ns, low width 5 us and period 10 us. Phi high precharges the floating capacitors; phi low couples them to the sensed inputs and output. Finite complementary slopes permit overlap. An external 1 pF loads vcmfb; stop time is 100 us. The target after repeated transfers is 0.6 V + common_v - 0.75 V.\n\n## Physical Requirements\n\nThe GDS top cell is `cmfb_004_output_switched_cap`, with a 10 MiB maximum file size. Provide physical, correctly connected and accessible labeled interface metal; retain every named port. Pass IHP main and maximal DRC (density and antenna excluded for this standalone block), strict named-interface LVS and a functional bounding box no larger than 320 by 70 um. No DRC waivers are used. The functional footprint includes device, passive, implant, well and complete routing layers; excludes annotations/pin text and nonfunctional markers. Its explicit GDS layer/datatype set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. The area is the bounding-box area of those layers, not summed metal area.\n\nThe candidate GDS must pass artifact, DRC, LVS and hard geometry before extraction. Magic candidate-derived distributed interconnect resistance and capacitance, with zero coupling-capacitance threshold, feed the supplied testbench. Internal MIM devices remain in candidate extraction. Source simulation alone cannot establish acceptance. This is nominal block qualification, not fabrication signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `output_v` | V(out) at 95 us | V | target / target | 0 … 1.5 | 1.5 |\n| `sample_error_v` | Maximum absolute V(out) minus [0.6 V + (V(vinp)+V(vinn))/2 - 0.75 V], over 92–95 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `hold_drift_v` | Maximum absolute V(out) minus its 95 us sample, over 96.1–99 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `clock_power_w` | Mean of max(0,-V(phi) I(VPH)) + max(0,-V(phin) I(VPL)), over 80–100 us; returned energy is not credited | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **5263.8 um2**. 22 expanded device instances; sum of device/contact envelopes 3414.7414 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nCommon-mode sampler: sample accuracy 45%; hold drift 27%; output bias 4.5%; clock power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `sample_error_v` | 0.450000000000 |\n| `hold_drift_v` | 0.270000000000 |\n| `output_v` | 0.045000000000 |\n| `clock_power_w` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed SG13G2 device/rule/model resources supplied through `/protocol/resources.json` and the task definitions in `/protocol/task.json`. KLayout supplies layout and physical checks; Magic supplies candidate RC; ngspice consumes the declared deck. Discover available feedback through the runtime harness protocol. Write `output/final.gds` in the workspace and explicitly submit that GDS through the submission protocol. Reference layouts, source checkouts and authoring scripts are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml","case_sha256":"285e435bc587d2d15059a5ca420ffba031121c3bccde510802bb3088f55f1725","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/circuit.cdl","netlist_sha256":"3a3ca59eef1a93dd54f0e78087fccb7e250f354833ec52950e1b0f425daef481","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.drv_001_pam4_sige_dac","in_core":true,"title":"Upstream broadband SiGe PAM4 current-steering driver","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Combines weighted current-steering cells into a SiGe PAM4 driver.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/drv_001_pam4_sige_dac","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Broadband SiGe PAM4 Driver Layout Task\n\n## Objective\n\nLay out the upstream inductorless, three-cell current-steering PAM4 driver as\n`pam4drv_pam4_lay`. One LSB cell and two parallel MSB cells contain twelve\nthree-finger `npn13G2` HBTs, twelve physical `rsil` resistors and three physical\nMIM degeneration capacitors. Preserve the supplied topology and dimensions.\nThe task coefficient is 4.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the native LVS authority;\n`materials/circuit.spice` is its simulator representation;\n`materials/testbench.spice` defines the electrical measurements.\n\nOrdered ports: `lsbp lsbn msbp msbn outp outn vcc vcasc vcmb tmsb0 tlsb0 tmsb1 sub`.\nThe first four ports are differential LSB/MSB inputs, `outp/outn` are differential\noutputs, `vcc` is the supply, `vcasc` biases the cascode bases, `vcmb` is the input\ntermination reference, the three tail ports connect to external current sinks,\nand `sub` is the ideal substrate reference. The three testbench VCCS tails are\nexternal bias apparatus, not missing physical transistors.\n\n## Operating Conditions\n\nUse the upstream **layout signoff point**, not its separate static sizing point:\n4 V supply, 3.35 V cascode bias, 1.9 V input common mode and 15 mA per cell.\nThe nominal corners are `hbt_typ`, `res_typ` and `cap_typ` at 27 °C. HBTs have\n`Nx=3`. Physical dimensions are fixed by the netlists; the nominal targets are\n50 Ω collector loads, 48 Ω input terminations, 3.2 Ω degeneration and 16 fF\nbridging capacitance. PDK geometry models determine their actual values.\n\nBoth RF ports use 50 Ω per side (100 Ω differential). AC gain is differential\npower-wave S21 = `2*Vout/Vsrc`, measured at 1 GHz; bandwidth is checked by the\n50 GHz gain relative to 1 GHz. S11 is evaluated at **32 GHz**, and S22 at\n**50 GHz**, using the testbench's 20 points/decade sweep and interpolation.\nDo not substitute the preceding sweep samples for these endpoints.\n\nThe large-signal test drives LSB and MSB in phase at 1 GHz through the same\nsource impedances, with ±0.8 V per source around 1.9 V. Supplies and bias ramp\nfrom zero over 8 ns; sine excitation starts at 9 ns. The 16–21 ns measurement\nwindow contains five periods. Swing is twice the fundamental phasor amplitude\nusing the exported transient samples, rather than raw peak-to-peak excursion.\n\n## Physical Requirements\n\nSubmit GDS with the exact top-cell name, all thirteen labeled ports, and at most\n10 MiB. Native SG13G2 DRC checks main and extra maximal rules without density or\nantenna; no marker waivers apply. Native LVS compares devices, dimensions,\nconnectivity and named ports. Functional width/height must not exceed 160/120 µm.\nThe published `outline` layer list covers HBT, resistor, MIM, substrate-contact,\nseven-metal and via geometry; pin/text and presentation layers are excluded.\n\nPost-layout simulation uses KPEX 0.3.12 nominal 2.5D **coupling capacitance** from\nthe submitted GDS. Native extracted devices are checked against the candidate's\nindependent LVS database. MIM devices retain extracted endpoints and `w/l/m`;\nno MIM layers are stripped and no source devices are reinserted. The process\nreference plane is tied to `sub`. Distributed wire resistance, inductance,\npads/package, statistical yield and process-corner robustness are not claimed\nby this upstream CC characterization contract. Finite substrate/tail-generator\ncircuits are outside the physical core. A PAM4 eye/RLM result is not established\nby these tone and small-signal checks.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nAll measurements and their paired source observations must be finite and usable.\nPerformance is scored continuously against the same-condition source circuit;\nupstream data-sheet targets are not acceptance thresholds. Supply consumption\nand output swing must be nonnegative; zero or otherwise unusable ratio baselines\ncannot establish a score. Physical checks remain mandatory.\n\n| Metric | Definition | Unit | Quality rule | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `lsb_gain_db` | LSB S21 at 1 GHz | dB | maximize / db20 | none |\n| `msb_gain_db` | MSB S21 at 1 GHz | dB | maximize / db20 | none |\n| `dac_weight_db` | MSB minus LSB gain | dB | source target | none |\n| `lsb_rel50_db` | LSB S21(50 GHz) minus S21(1 GHz) | dB | maximize / db20 | none |\n| `msb_rel50_db` | MSB S21(50 GHz) minus S21(1 GHz) | dB | maximize / db20 | none |\n| `s11_32g_db` | MSB input reflection coefficient, 20 log10(abs(S11)), at 32 GHz | dB | minimize / db20 | none |\n| `s22_50g_db` | Output reflection coefficient, 20 log10(abs(S22)), at 50 GHz | dB | minimize / db20 | none |\n| `power_mw` | Power drawn from the 4 V rail at OP | mW | minimize / ratio | ≥ 0 |\n| `swing_vpp` | Differential output fundamental swing | V | maximize / ratio | ≥ 0 |\n\nIndependent source simulation uses the same deck, conditions and models.\nResponse quality uses `db20` for gain,\nrelative bandwidth and reflection-coefficient dB, and a maximizing ratio for swing. Binary\nweight uses target normalization to its source value with a `20*log10(2)` dB scale, the ideal binary amplitude-weight interval. Supply quality uses a minimizing\npower ratio. Area quality is `Q = 10000 µm² / functional_area`. The frozen compact\nallowance is 4500 µm² for device rows + 2000 µm² for terminations/loads +\n3500 µm² for routing, vias and substrate contacts. Reflection-coefficient dB\nis the negative of positive return loss, so smaller values improve quality. Physical or electrical rejection scores zero; incomplete evaluation\ncannot establish success. The area target is a compact sizing allowance,\nnot the area of a qualified reference.\n\n\n### Score weights\n\nPAM4 SiGe driver: binary weighting 22.5%; high-frequency transfer 22.5%; port matching 18%; gain and swing 18%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `dac_weight_db` | 0.225000000000 |\n| `lsb_rel50_db` | 0.112500000000 |\n| `msb_rel50_db` | 0.112500000000 |\n| `s11_32g_db` | 0.090000000000 |\n| `s22_50g_db` | 0.090000000000 |\n| `lsb_gain_db` | 0.060000000000 |\n| `msb_gain_db` | 0.060000000000 |\n| `swing_vpp` | 0.060000000000 |\n| `power_mw` | 0.090000000000 |\n\n## Tools and Submission\n\nSolve budget: **4 hours**.\n\nUse the reviewed SG13G2 resources and the runtime task/protocol metadata.\nNgspice must be ≥45 with `ngbehavior=hsa`, compiled R3_CMC support and the\nspecified HBT/capacitor models. The toolchain provides native KLayout checks,\ncandidate-derived KPEX capacitance and ngspice feedback. Write\n`/workspace/output/final.gds` and explicitly submit it through the runtime\nsubmission interface. Reference and maintainer material is not a solver input.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml","case_sha256":"f09f7966d5b3a9e727670b252db9e476e15ad0b10cf64b326897054b23acfdbe","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/circuit.cdl","netlist_sha256":"310d1f67d5d237cfc88525f26568c5bcf45680bb2e8141982600669ee81a2ead","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.ia_002_fan_chopper_simple","in_core":false,"title":"Fan Clocked Capacitive Instrumentation Amplifier","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Processes differential signals with a clocked, capacitively coupled instrumentation amplifier.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_002_fan_chopper_simple","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Clocked Capacitive Instrumentation Amplifier Layout Task\n\n## Objective\n\nImplement the supplied 39 MOS, 2 R, 6 C circuit. Preserve the running input, feedback and output choppers. There is no CMFB. Do not add a servo, remove or disable signal/feedback branches, or change the fixed transistor sizing and bias contract.\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n`. Preserve these named connections.\n\nThe CDL and simulator netlist are equivalent physical representations. Use their exact ordered interface. Bias sources and clocks are external. Additional inch, fbch, g2 and summing-node ports are high-impedance monitors, with no external drives or loads. Every ideal upstream passive is implemented with physical MIM or high-poly primitives; no case requires another case's circuit or development source.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode and vref=0.6 V; vb1/vb2/vb3/vb4=0.5/0.75/0.45/0.55 V. Each complementary clock pair runs synchronously at 5 kHz with 50 ns rise/fall, 99.95 us pulse width and 200 us period. All positive phases align. Differential sinusoidal input is 10 mV peak at 100 and 200 Hz; load is 50 fF per output. Maximum timestep is 200 ns with adaptive edge resolution. The test runs 40 ms; 0–20 ms is discarded. The 20–40 ms observation spans 100 chop cycles and two/four signal cycles. Adjacent 20–30/30–40 ms windows report transfer variation. This is a finite-window observation of the full clocked circuit, not a claim of asymptotic periodic stability.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and named-interface LVS must pass without waivers. The functional bounding rectangle includes device, well, contact and complete routing layers, excluding annotations, and must fit 5000 by 1000 um. Native physical taps and all passive units are part of the contract.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nUse the supplied transient testbench on the extracted candidate. Time-weighted sine/cosine integrals give complex differential transfer and input admittance. Full-precision cumulative integrals at the 20/30/40 ms clock breakpoints avoid cancellation of rounded measurement averages. The summed endpoint error must not exceed 1 ps; this is measurement validity, not a circuit performance gate. Input impedance is the magnitude of differential voltage divided by differential source current, where input current is -(i(VP)-i(VN))/2. Residual RMS removes the measured DC and fundamental; full output peak-to-peak also includes signal and all ripple. It must not be represented as switching ripple alone. Input and feedback modulation errors compare clock-demodulated branch voltages to the associated external signals. Raw monitor waveforms support independent checking of the switching paths. Ordinary DC/AC does not replace these measurements.\n\nEvery measurement must be finite. Magnitudes, RMS values and total consumed supply/clock power have nonnegative physical domains. No paper gain, input-impedance boost or ripple specification is a hard gate. Slow common-mode excursions and finite-window variation are reported and scored, not suppressed with a CMFB. The source uses the identical physical devices, clocks, loads and observation windows in an independent simulation. No PAC/PNoise, PSS, noise, mismatch, PVT or supply-startup capability is claimed.\n\nArea quality is Q=71369.42 um2/functional area. The compact estimate sums MOS (W+2.4)(L+2.4), a 3.2² local tap envelope per MOS and one global tap, each MIM (side+2.4)², and forty (.5+2.4)(84.45+2.4) resistor envelopes per bias arm, then adds 50% routing allowance. It is independent of the witness. Gain and input-impedance magnitudes use source ratios; phase is diagnostic to avoid angular-wrap scoring; residual and window variation use inverse ratios with 1 uV floor; output bias uses 1.2 V target scale; power uses inverse ratios with 1 pW floor. Other observations are diagnostics. Coefficient 8 reflects clock modulation coupled to a compensated capacitive signal-feedback loop; no common-mode regulation is assumed.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `gain_vv` | `2*sqrt(dsmean^2+dcmean^2)/amplitude` | V/V | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `phase_deg` | `180*ph(dsmean+j(dcmean))/pi` | deg | diagnostic | −∞ … +∞ | — |\n| `zin_ohm` | `amplitude/(2*sqrt(ismean^2+icmean^2))` | ohm | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `admittance_real_s` | `-2*ismean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `admittance_imag_s` | `-2*icmean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `dm_mean_v` | `avg dm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `residual_rms_v` | `rms residual from=20m to=40m` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `ripple_pp_v` | `pp dm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_mean_v` | `avg cm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `cm_min_v` | `min cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `window_change_v` | `2*sqrt((dsfirst-dslast)^2+(dcfirst-dclast)^2)` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `modulation_error_rms_v` | `rms modulation_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `feedback_error_rms_v` | `rms feedback_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `power_w` | `avg supplied from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `clock_power_w` | `avg clocks from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `boundary_error_s` | `abs(time[i20]-20m)+abs(time[i30]-30m)+abs(time[i40]-40m)` | s | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\nThe 1 ps endpoint alignment check aborts simulation with a nonzero exit\nbefore invalid integrals are reported. Its residual is diagnostic; a failed\nvalidity check produces an evaluator error and unknown score, not electrical failure.\n\n\n### Score weights\n\nClocked instrumentation amplifiers: signal fidelity 31.3%; drift and ripple 19.6%; input impedance 15.7%; common-mode behavior 15.7%; supply and clock power 7.83%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_vv` | 0.156521739130 |\n| `residual_rms_v` | 0.156521739130 |\n| `window_change_v` | 0.195652173914 |\n| `zin_ohm` | 0.156521739130 |\n| `cm_mean_v` | 0.078260869565 |\n| `dm_mean_v` | 0.078260869565 |\n| `clock_power_w` | 0.039130434783 |\n| `power_w` | 0.039130434783 |\n\n## Tools and Submission\n\nSolve budget: **10 hours**.\n\nSubmit GDS top cell ia_002_fan_chopper_simple. Evaluation runs native DRC/LVS, geometry, Magic candidate-derived RC extraction and ngspice transient measurement using reviewed resources. Reference materials and source checkouts are not solver inputs.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml","case_sha256":"345627f61d37dc99db2d9b5010c2f0e22aa14f64075a0f9ccf78c9e870b5e688","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl","netlist_sha256":"97f83b5e7f5fb018b9212759ab77f039f748e14d2ef15280b1e4fc7730ba8afb","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.ia_003_fan_chopper_pf","in_core":false,"title":"Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Combines clocked capacitive instrumentation amplification with positive feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_003_fan_chopper_pf","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback Layout Task\n\n## Objective\n\nImplement the supplied 47 MOS, 2 R, 8 C circuit. Preserve the running input, feedback and output choppers, including the positive-feedback chopper and capacitors. There is no CMFB. Do not add a servo, remove or disable signal/feedback branches, or change the fixed transistor sizing and bias contract.\n\n## Inputs and Interface\n\n- `problem.md`: description input.\n- `materials/circuit.cdl`: netlist input.\n- `materials/circuit.spice`: simulation input.\n- `materials/testbench.spice`: performance input.\n\nOrdered ports: `vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not clk_chpf clk_chpf_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n pfch_p pfch_n`. Preserve these named connections.\n\nThe CDL and simulator netlist are equivalent physical representations. Use their exact ordered interface. Bias sources and clocks are external. Additional inch, fbch, g2 and summing-node and pfch ports are high-impedance monitors, with no external drives or loads. Every ideal upstream passive is implemented with physical MIM or high-poly primitives; no case requires another case's circuit or development source.\n\n## Operating Conditions\n\nTT, 27 C, VDD=1.2 V, input common mode and vref=0.6 V; vb1/vb2/vb3/vb4=0.5/0.75/0.45/0.55 V. Each complementary clock pair runs synchronously at 5 kHz with 50 ns rise/fall, 99.95 us pulse width and 200 us period. All positive phases align. Differential sinusoidal input is 10 mV peak at 100 and 200 Hz; load is 50 fF per output. Maximum timestep is 200 ns with adaptive edge resolution. The test runs 40 ms; 0–20 ms is discarded. The 20–40 ms observation spans 100 chop cycles and two/four signal cycles. Adjacent 20–30/30–40 ms windows report transfer variation. This is a finite-window observation of the full clocked circuit, not a claim of asymptotic periodic stability.\n\n## Physical Requirements\n\nSubmit a nonempty GDSII of at most 10485760 bytes.\nNative IHP DRC and named-interface LVS must pass without waivers. The functional bounding rectangle includes device, well, contact and complete routing layers, excluding annotations, and must fit 5000 by 1000 um. Native physical taps and all passive units are part of the contract.\n\nMagic extracts candidate interconnect resistance/capacitance and device\njunction geometry. Wells/substrate are connected to physical tap rails; source\nsimulation retains finite tap models. Distributed substrate, statistical\nmismatch and manufacturing signoff are outside this nominal contract.\n\nThe scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`.\n\n## Electrical Requirements and Scoring\n\nUse the supplied transient testbench on the extracted candidate. Time-weighted sine/cosine integrals give complex differential transfer and input admittance. Full-precision cumulative integrals at the 20/30/40 ms clock breakpoints avoid cancellation of rounded measurement averages. The summed endpoint error must not exceed 1 ps; this is measurement validity, not a circuit performance gate. Input impedance is the magnitude of differential voltage divided by differential source current, where input current is -(i(VP)-i(VN))/2. Residual RMS removes the measured DC and fundamental; full output peak-to-peak also includes signal and all ripple. It must not be represented as switching ripple alone. Input and feedback and positive-feedback modulation errors compare clock-demodulated branch voltages to the associated external signals. Raw monitor waveforms support independent checking of the switching paths. Ordinary DC/AC does not replace these measurements.\n\nEvery measurement must be finite. Magnitudes, RMS values and total consumed supply/clock power have nonnegative physical domains. No paper gain, input-impedance boost or ripple specification is a hard gate. Slow common-mode excursions and finite-window variation are reported and scored, not suppressed with a CMFB. The source uses the identical physical devices, clocks, loads and observation windows in an independent simulation. No PAC/PNoise, PSS, noise, mismatch, PVT or supply-startup capability is claimed.\n\nArea quality is Q=73567.47 um2/functional area. The compact estimate sums MOS (W+2.4)(L+2.4), a 3.2² local tap envelope per MOS and one global tap, each MIM (side+2.4)², and forty (.5+2.4)(84.45+2.4) resistor envelopes per bias arm, then adds 50% routing allowance. It is independent of the witness. Gain and input-impedance magnitudes use source ratios; phase is diagnostic to avoid angular-wrap scoring; residual and window variation use inverse ratios with 1 uV floor; output bias uses 1.2 V target scale; power uses inverse ratios with 1 pW floor. Other observations are diagnostics. Coefficient 9 reflects interacting positive/negative signal feedback and impedance control under clock modulation; no common-mode regulation is assumed.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observation | Unit | Quality / dimension | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `functional_area` | Functional bounding-rectangle area | um2 | area quality Q | positive area | — |\n| `gain_vv` | `2*sqrt(dsmean^2+dcmean^2)/amplitude` | V/V | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `phase_deg` | `180*ph(dsmean+j(dcmean))/pi` | deg | diagnostic | −∞ … +∞ | — |\n| `zin_ohm` | `amplitude/(2*sqrt(ismean^2+icmean^2))` | ohm | maximize / ratio / response | 0 … +∞ | 1e-12 |\n| `admittance_real_s` | `-2*ismean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `admittance_imag_s` | `-2*icmean/amplitude` | S | diagnostic | −∞ … +∞ | — |\n| `dm_mean_v` | `avg dm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `residual_rms_v` | `rms residual from=20m to=40m` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `ripple_pp_v` | `pp dm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_mean_v` | `avg cm from=20m to=40m` | V | target / target / bias | −∞ … +∞ | 1.2 |\n| `cm_min_v` | `min cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `cm_max_v` | `max cm from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `window_change_v` | `2*sqrt((dsfirst-dslast)^2+(dcfirst-dclast)^2)` | V | minimize / ratio / response | 0 … +∞ | 1e-06 |\n| `modulation_error_rms_v` | `rms modulation_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `feedback_error_rms_v` | `rms feedback_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `power_w` | `avg supplied from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `clock_power_w` | `avg clocks from=20m to=40m` | W | minimize / ratio / supply | 0 … +∞ | 1e-12 |\n| `pf_error_rms_v` | `rms pf_error from=20m to=40m` | V | diagnostic | −∞ … +∞ | — |\n| `boundary_error_s` | `abs(time[i20]-20m)+abs(time[i30]-30m)+abs(time[i40]-40m)` | s | diagnostic | −∞ … +∞ | — |\n\nApply each row to every declared load/tone condition. Pair each candidate\nobservation with its `source_` job under the identical condition. The supplied\ndeck defines intermediate vectors used in the expressions above.\nThe 1 ps endpoint alignment check aborts simulation with a nonzero exit\nbefore invalid integrals are reported. Its residual is diagnostic; a failed\nvalidity check produces an evaluator error and unknown score, not electrical failure.\n\n\n### Score weights\n\nClocked instrumentation amplifiers: signal fidelity 31.3%; drift and ripple 19.6%; input impedance 15.7%; common-mode behavior 15.7%; supply and clock power 7.83%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_vv` | 0.156521739130 |\n| `residual_rms_v` | 0.156521739130 |\n| `window_change_v` | 0.195652173914 |\n| `zin_ohm` | 0.156521739130 |\n| `cm_mean_v` | 0.078260869565 |\n| `dm_mean_v` | 0.078260869565 |\n| `clock_power_w` | 0.039130434783 |\n| `power_w` | 0.039130434783 |\n\n## Tools and Submission\n\nSolve budget: **10 hours**.\n\nSubmit GDS top cell ia_003_fan_chopper_pf. Evaluation runs native DRC/LVS, geometry, Magic candidate-derived RC extraction and ngspice transient measurement using reviewed resources. Reference materials and source checkouts are not solver inputs.\n\nDiscover the frozen task, resources and submission interface through\n`/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`.\nDeclared inputs are under `/task`. Write `/workspace/output/final.gds`\nand explicitly submit with `python -I /protocol/submit.py`. Creating the file\nalone does not submit it. Only feedback supported by the active harness is available.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml","case_sha256":"0a8fe01b64575b18ec2f8ff36e376afd21c9db605c347689aaf31998b81c4cb6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl","netlist_sha256":"870cd5a0b88e0e29454c43f5d4c2e7c555b0ec9dd9f609f9c1e19f6b9258d71a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.ia_006_fan_chopper_cmfb","in_core":true,"title":"Clocked Capacitive Instrumentation Amplifier with Transistor CMFB","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Combines clocked capacitive instrumentation amplification with transistor common-mode feedback.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_006_fan_chopper_cmfb","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Clocked Capacitive Instrumentation Amplifier with CMFB Layout Task\n\n## Objective\n\nImplement `ia_006_fan_chopper_cmfb`: a complete capacitively coupled differential\ninstrumentation amplifier with input, feedback and interstage/output chopping,\na two-stage amplifier and transistor common-mode feedback (CMFB). Preserve the\nphysical signal/feedback capacitors, both bias-return paths, compensation and\nthe actual common-mode controller. Validate operation with all clocks running.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative physical circuit for native LVS.\n- `materials/circuit.spice`: equivalent process-model simulator representation.\n- `materials/testbench.spice`: independent bias, clocks, loads and measurements.\n\nThe ordered interface is:\n\n```text\nvinp vinn voutp voutn vref\nclk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not\nvdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm\ncore__vsum_p core__vsum_n\n```\n\nVINP/VINN and VOUTP/VOUTN are the differential input and output. VREF biases\nthe summing nodes through physical high-poly return arms; VREF_CM is the\nreference for the actual transistor common-mode controller. The four CORE__VB\nports supply the declared core bias voltages. The final two ports are\nhigh-impedance summing-node monitors: the testbench observes them without\napplying voltage/current drive, a servo or an external load. Keep these named\nconnections; they also distinguish the symmetric native LVS branches.\n\nUse the fixed models, dimensions, multiplicities and connections in the\nnetlist. The 46 source MOS groups have a maintained 61-finger implementation;\nparallel fingering/merging is allowed when all checks pass. Core matching pairs\nhave fixed total W*m/L and on-grid finger dimensions; do not replace them with\nunqualified model widths. NMOS and resistor bodies connect to SUB through the\nexplicit VSS substrate tap, and PMOS bodies to WELL through the VDD well tap.\nDo not drive the internal CMFB actuator VB4O externally.\n\nPhysical passive requirements are:\n\n| Branch | Physical implementation | Nominal value at TT, 27 C |\n| --- | --- | --- |\n| Each input arm | Four parallel 51.6 × 51.6 um `cap_cmim` units | 16.008384 pF |\n| Each capacitive feedback arm | One 23.11 × 23.11 um `cap_cmim` | 0.80480575 pF |\n| Each differential Miller path | One 51.6 × 51.6 um `cap_cmim` | 4.002096 pF |\n| CMFB actuator to VSS | One 25.85 × 25.85 um `cap_cmim` | 1.00646975 pF |\n| Each summing-node return to VREF | 41 series `rhigh` segments, W=1 um, L=180 um, m=1, b=0 | 10.46156 Mohm |\n| Each output-to-common-mode-sense arm | Four of the same high-poly segments | 1.02064 Mohm |\n\nThe input/feedback capacitor ratio is approximately 19.891. All internal\npassives are physical DUT devices, distinct from external output loads. Preserve\nMIM plate orientation. The maintained compensation is deliberately retuned for\nthe physical combined loop; the source's ideal 1 pF Miller / 1 fF controller\nvalues do not define this task.\n\n## Operating Conditions\n\nUse TT MOS/capacitor/resistor models at 27 C and VDD/VSS=1.2/0 V. VREF and\nVREF_CM are both 0.6 V. Relative to VSS, CORE__VB1/2/3/4 are respectively\n0.5/0.75/0.45/0.589 V. There is no ideal external output-common-mode or\ndifferential-feedback servo. Each output has a 1 pF or 5 pF external load.\nAt each load, run both signs of a 10 mV differential input step: four conditions.\n\nThe input common mode stays at 0.6 V. Both inputs initially equal 0.6 V.\nDuring 500–501 us they move to `0.6+step_v/2` and `0.6-step_v/2`, hold\nfor 500 us, then return during 1001–1002 us. `step_v` is +0.01 or −0.01 V.\nThe pulse period is 10 ms; only the finite 0–1.5 ms sequence is measured.\n\nAll three true/complement clock pairs run synchronously at 20 kHz between\n0 and 1.2 V. True clocks begin high, fall during 25–25.05 us, hold low for\n24.95 us, then rise during 50–50.05 us; the 50 us pattern repeats. Complement\nclocks have exactly opposite levels with the same 50 ns edges. Finite\ncomplementary slopes may produce overlap or dead intervals according to device\nthresholds; no ideal break-before-make behavior is assumed. Input, feedback and\noutput/interstage clocks all switch; frozen-clock gain is not an acceptance test.\n\nTransient starts from the solved DC operating point. Use Gear order 2, the\nKLU solver, maximum time step 500 ns, `rshunt=1e13`, `reltol=1e-5`,\n`abstol=1e-13` and `vntol=1e-8`. Save the declared port voltages and source\ncurrents. The settled observation windows contain integer clock periods;\nstartup from a zero-supply state is not covered.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ia_006_fan_chopper_cmfb`, no larger than 10 MiB.\nPass native IHP main/maximal DRC without waivers (standalone scope with\ndensity/antenna disabled), strict named-interface LVS including taps, and a\n3000 × 700 um functional outline. Device, contact and complete routing layers\nare enumerated by the runtime outline constraint. Pin/annotation layers are\nexcluded from area and cannot conceal functional geometry.\n\nThe submitted layout must provide the actual capacitors, resistor segments and\nmatching-aware core. Post-layout simulation consumes candidate-derived Magic\nRC with device junction geometry and interconnect. Extraction subdivides the\ninitial Magic grid by two and uses `gds_readonly=false` on an isolated import;\nthe submitted GDS remains immutable. No extraction diagnostic is waived.\nMagic idealizes the explicit tap devices while retaining its extracted RC\nnetwork; the source simulator includes finite tap models. Distributed substrate\nnoise and manufacturing signoff are not qualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `gain_vv` | Transient: `((avg (v(voutp)-v(voutn)) from=900u to=1m)-(avg (v(voutp)-v(voutn)) from=400u to=500u))/(2*((avg v(vinp) from=900u to=1m)-.6))`. | V/V | target / target | −∞ … +∞ | 1.0 | response |\n| `baseline_error_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=400u to=500u))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `return_error_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=1.4m to=1.5m)-(avg (v(voutp)-v(voutn)) from=400u to=500u))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `high_drift_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=950u to=1m)-(avg (v(voutp)-v(voutn)) from=900u to=950u))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `return_drift_v` | Transient: `abs((avg (v(voutp)-v(voutn)) from=1.45m to=1.5m)-(avg (v(voutp)-v(voutn)) from=1.4m to=1.45m))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `ripple_rms_v` | Transient: `sqrt((avg (((v(voutp)-v(voutn))-(avg (v(voutp)-v(voutn)) from=900u to=1m))^2) from=900u to=1m))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `ripple_pp_v` | Transient: `(max (v(voutp)-v(voutn)) from=900u to=1m)-(min (v(voutp)-v(voutn)) from=900u to=1m)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `cm_mean_v` | TRAN: Mean of `((v(voutp)+v(voutn))/2) from=900u to=1m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `cm_min_v` | TRAN: Minimum of `((v(voutp)+v(voutn))/2) from=400u to=1.5m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `cm_max_v` | TRAN: Maximum of `((v(voutp)+v(voutn))/2) from=400u to=1.5m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `sum_cm_v` | TRAN: Mean of `((v(monp)+v(monn))/2) from=900u to=1m`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `sum_error_v` | Transient: `abs((avg ((v(monp)-v(monn))*(v(clk_chin)/.6-1)) from=900u to=1m))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-1.2*i(VDD)) from=400u to=1.5m`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `clock_power_w` | Mean sum of positive delivered power from all six chopper clock sources over 900 us–1 ms; negative (returned) power from each source is clipped to zero before summation. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_cm_v` | DC operating point: `(v(voutp)+v(voutn))/2`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `dc_dm_v` | DC operating point: `v(voutp)-v(voutn)`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `baseline_v` | TRAN: Mean of `(v(voutp)-v(voutn)) from=400u to=500u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `plateau_v` | TRAN: Mean of `(v(voutp)-v(voutn)) from=900u to=1m`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `return_v` | TRAN: Mean of `(v(voutp)-v(voutn)) from=1.4m to=1.5m`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `dc_power_w` | DC operating point: `-1.2*i(VDD)`. | W | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n\nArea reference: **102216.79 um2**. 166 expanded device instances; sum of device/contact envelopes 67727.1707 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **10**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nClocked instrumentation amplifiers: signal fidelity 37.9%; drift and ripple 23.7%; common-mode behavior 18.9%; supply and clock power 9.47%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `baseline_error_v` | 0.126315789472 |\n| `gain_vv` | 0.126315789474 |\n| `return_error_v` | 0.126315789474 |\n| `high_drift_v` | 0.059210526316 |\n| `return_drift_v` | 0.059210526316 |\n| `ripple_pp_v` | 0.059210526316 |\n| `ripple_rms_v` | 0.059210526316 |\n| `cm_max_v` | 0.037894736842 |\n| `cm_mean_v` | 0.037894736842 |\n| `cm_min_v` | 0.037894736842 |\n| `sum_cm_v` | 0.037894736842 |\n| `sum_error_v` | 0.037894736842 |\n| `clock_power_w` | 0.047368421053 |\n| `mean_power_w` | 0.047368421053 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover frozen task inputs, requirements, reviewed resources and harness\nfeedback in `/protocol/task.json`, `/protocol/resources.json` and\n`/protocol/harness.json`. Use the supplied IHP primitives and KLayout, Magic\nand ngspice. Write `/workspace/output/final.gds` and explicitly submit through\nthe harness protocol. Source records, reference GDS and host configuration\nremain outside standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml","case_sha256":"7ca1dc67f774b163a585dd222d9cc95f30cd5f15085f5bb2d30ab8a403ce83f2","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/circuit.cdl","netlist_sha256":"e5049836e133e951c36c34dd5eed0fe1c2492f1671930153c97cf4ccae786f1d","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.ldo_001_analoggym_basic","in_core":false,"title":"Multistage Error-Amplifier PMOS Regulator","pdk":"ihp-sg13g2","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_001_analoggym_basic","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Multistage Error-Amplifier PMOS Regulator Layout Task\n\n## Objective\n\nLay out `ldo_001_analoggym_basic`: a PMOS pass regulator with a folded\nPMOS-input error amplifier, cascoded bias branches, mirrored loads and an\nadditional PMOS/NMOS intermediate branch driving the pass-gate node `net1`.\nThe auxiliary PMOS source and body connect to `net1`; the input pair has a\nseparate source-tied `net20` well. Internal compensation connects `net106`\nto output and the 3:1 physical divider returns one quarter of output voltage.\nThis complete multistage error amplifier and its internal pass-gate drive\nare distinct from the simpler 5T and mirror-OTA regulator cases.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical circuit.\n- `materials/circuit.spice`: matching simulator circuit with finite taps.\n- `materials/testbench.spice`: bilateral loop and current-load recovery.\n- `materials/startup.spice`: synchronized zero-state resistive startup.\n- `materials/sweeps.spice`: line/load and downward headroom sweeps.\n\nOrdered ports: `vdd vout vss ib vref vfb sense`. VDD/VSS are supply/return,\nVOUT output, IB connects an external current sink to VSS, and VREF is the\nexternal reference. VFB is the physical divider midpoint and SENSE is the\ninverting error-amplifier input. Connect them only through the testbench's\nzero-volt injection link; no additional servo or feedback element is permitted.\nThe source's zero-volt output measurement link is collapsed into VOUT and\nrelocated to this explicitly declared divider/input boundary.\n\nRetain all 24 source MOS groups. Integer regrouping converts 1,168 source\nfingers into 831 physical fingers with <=10 um individual width, preserving\neach original group's total W, L and body connection exactly. Individual W/m\nand diffusion perimeter change, so the maintained simulator and extracted\ncandidate are qualified independently. Other PMOS bodies use the VDD well;\nNMOS bodies and physical high-poly backplates use the VSS substrate contact.\nExplicit 2 x 2 um substrate/well taps use <=20 um pitch. Preserve the current\nnative circuit's dimensions and total multiplicities; equivalent parallel\nfingering requires all physical and electrical checks to pass.\n\nAll internal passives are physical DUT elements:\n\n- Three parallel 42.685 × 42.685 um `cap_cmim` units: top `net106`, bottom VOUT;\n  approximately 8.22 pF total, retaining the source's approximately 8.2 pF branch.\n- One 51.64 × 51.64 um `cap_cmim`: top `net10`, bottom VOUT, approximately\n  4 pF. This added physical local compensation closes the internal dynamic mode.\n- Twelve series `rhigh` segments from VOUT to VFB and four from VFB to VSS,\n  each W=1 um, L=17.465 um, b=0: approximately 300/100 kohm total.\n\nThere is no additional external output capacitor, but the compensation is\nreal output-connected storage. Do not delete or idealize any internal passive.\n\n## Operating Conditions\n\nThe loop/load testbench allows 1000 DC operating-point iterations (`itl1=1000`)\nfor both source and extracted simulations. Error tolerances and physical stimuli\nare unchanged; this is a convergence setting, not added circuit damping.\n\nUse typical IHP LV MOS/MIM/poly models at 27 C. VDD is 1.2 or 1.3 V,\nVREF=0.225 V, and the external IB-to-VSS sink is 8 uA. The reference is\nexplicitly changed from the normalized source's 0.4 V: the 3:1 divider then\nhas a 0.9 V ideal output target, within the LV supply. The 8 uA bias and\nall original total MOS widths/lengths are retained. This is a bounded\nregulator core, not a precision reference, PVT or manufacturing-signoff task.\n\nMain measurements cover both supplies and initial current loads 0.2/0.5 mA.\nAfter an operating point, the load doubles at 2–2.2 us, remains high for\n8 us, and returns at 10.2–10.4 us; the period is 16 us. Simulate 0–18 us\nwith KLU, Gear order 2, maximum step 1 ns, `rshunt=1e12`, `reltol=1e-5`,\n`abstol=1e-12` and `vntol=1e-8`. The numerical shunt is not a physical\nbias or startup device. Explicit `.save` lists retain all measured vectors;\nevery extracted circuit element still participates in the solve.\n\nMeasure the bilateral return ratio at the actual divider/input boundary:\nfirst inject unit series AC voltage from SENSE to VFB, with zero parallel\ncurrent; then use zero series voltage and unit current into SENSE. With\nfirst-run `b=-I(VPROBE)`, `d=V(SENSE)` and second-run `a=-I(VPROBE)`,\n`c=V(SENSE)`, define `delta=a*d-b*c` and\n`T=(2*delta-a+d)/(1-2*delta+a-d)` (Tian et al., Eq. 30).\nBoth injections retain divider, input and reverse-path loading. Exported\nvoltages/currents permit an independent two-port admittance calculation.\nSweep 0.01 Hz–1 GHz at 300 points/decade, using continuous natural phase\nwithout an arbitrary low-frequency offset. Check first/final descending\nunity crossings, minimum sampled `abs(1+T)`, full sampled return-difference\nphase and maximum 200 MHz–1 GHz gain. This finite external-loop contract\nis not an exhaustive proof of all internal poles.\n\nSweep load 0.2–1 mA in 10 uA steps at each supply. Downward VDD sweeps\n1.3–0.8 V in 1 mV steps at 0.2/1 mA measure the first 30 mV output-error\ncrossing. The line span uses both endpoints of 1.2–1.3 V. The regulation\nfloor includes amplifier headroom and is not a pass-resistance-only dropout\nrating. These DC sweeps do not extend dynamic stability to every intermediate\nsupply/load combination.\n\nStartup uses `uic` with supply, reference and bias ramping together from zero\nin 10 or 20 us. For both supplies, use 900/4500 ohm resistive loads (nominally\n1/0.2 mA at 0.9 V), maximum step 2 ns, and simulate to 50 us. This does not\nqualify arbitrary sequencing or a constant-current load imposed at zero supply.\nFaster 1 us startup and 20 ns current-load edges are outside qualification: they\nproduce excessive peaks in the same extracted circuit. The README provides\nrunnable failure probes. The maintained contract explicitly narrows the\ninitial development stimuli without relaxing the voltage-excursion bounds.\nLoads below 0.2 mA are outside the qualified dynamic range.\n\nFirst and final crossing phase margins must both lie in [0, 180] degrees.\nMinimum return distance and return-phase excursion have only nonnegative\ndomain bounds; high-frequency gain has no acceptance bound. These full-sweep\nmetrics affect continuous quality without adding a stability acceptance screen.\nMissing crossings or invalid observations are evaluator errors.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ldo_001_analoggym_basic`, at most 32 MiB. Pass native\nIHP main/maximal DRC without waivers (standalone density/antenna disabled),\nstrict named-interface LVS with explicit taps, and a 5500 × 360 um functional\nenvelope. All device/contact/interconnect drawing layers in the runtime\n`outline` contribute to area; annotation and pin-purpose layers do not.\n\nCandidate-derived Magic RC includes both capacitor plates, every poly segment,\nMOS and interconnect parasitic. Half-grid import and zero parasitic thresholds\nare explicit. Native LVS checks the original GDS's tap labels; the Magic\nextraction copy retains only Metal3 interface text, avoiding internal well-name\naliases without altering geometry. Magic idealizes well/substrate taps while\nsource simulation includes their finite models. Distributed substrate\nresistance/noise and fabrication signoff remain unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `bias_v` | DC operating point: `v(ib)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-@iload[current]`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 1g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 1g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=200meg to=1g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `minimum_v` | TRAN: Minimum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_v` | TRAN: Maximum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `recovery_load_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_release_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `loaded_ripple_v` | Transient: `(max v(vout) from=9u to=9.5u)-(min v(vout) from=9u to=9.5u)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `released_ripple_v` | Transient: `(max v(vout) from=17u to=17.5u)-(min v(vout) from=17u to=17.5u)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_error_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=40u to=49u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_peak_v` | TRAN: Maximum of `v(vout) from=0 to=50u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `startup_minimum_v` | TRAN: Minimum of `v(vout) from=0 to=50u`. | V | target / target | −∞ … +∞ | 1.3 | response |\n| `regulation_floor_v` | DC: Crossing coordinate where `(abs(v(vout)-0.9))=0.03 rise=1`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `headroom_v` | DC sweep: `(when (abs(v(vout)-0.9))=0.03 rise=1)-(find v(vout) when (abs(v(vout)-0.9))=0.03 rise=1)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n\nArea reference: **42364.42 um2**. 1240 expanded device instances; sum of device/contact envelopes 27974.3733 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **9**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nIHP regulators: regulation and headroom 22.5%; load recovery 22.5%; startup 13.5%; loop stability 13.5%; AC transfer and extrema 4.5%; internal bias 1.8%; quiescent current 7.2%; power 4.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `headroom_v` | 0.045000000000 |\n| `line_span_v` | 0.045000000000 |\n| `load_span_v` | 0.045000000000 |\n| `output_v` | 0.045000000000 |\n| `regulation_floor_v` | 0.045000000000 |\n| `loaded_ripple_v` | 0.056250000000 |\n| `recovery_load_v` | 0.056250000000 |\n| `recovery_release_v` | 0.056250000000 |\n| `released_ripple_v` | 0.056250000000 |\n| `startup_error_v` | 0.045000000000 |\n| `startup_minimum_v` | 0.045000000000 |\n| `startup_peak_v` | 0.045000000000 |\n| `final_phase_margin_deg` | 0.033750000000 |\n| `minimum_return_distance` | 0.033750000000 |\n| `phase_margin_deg` | 0.033750000000 |\n| `return_phase_excursion_deg` | 0.033750000000 |\n| `dc_gain_db` | 0.007500000000 |\n| `final_unity_hz` | 0.007500000000 |\n| `hf_gain_db` | 0.007500000000 |\n| `maximum_v` | 0.007500000000 |\n| `minimum_v` | 0.007500000000 |\n| `unity_hz` | 0.007500000000 |\n| `bias_v` | 0.018000000000 |\n| `quiescent_a` | 0.072000000000 |\n| `mean_power_w` | 0.022500000000 |\n| `power_w` | 0.022500000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover task/resources/feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied\nIHP primitives and KLayout/Magic/ngspice. Write `/workspace/output/final.gds`\nand explicitly submit via the harness protocol. Host configuration, source\nrecords and reference answers are excluded from standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml","case_sha256":"53db61a2e3fbe8b58aaf94ca5228beb06b42fe8688ff538676485d51ede6fca6","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl","netlist_sha256":"eebb188d9aa510eb1d03395ad2a4fe8b12ca6e4e16d4172dbd4d72bad3d0d79b","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.ldo_008_fer_mirror_ota","in_core":true,"title":"Mirror-OTA Regulator with Bilateral Return-Ratio Measurements","pdk":"ihp-sg13g2","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_008_fer_mirror_ota","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Mirror-OTA Regulator with Bilateral Return-Ratio Measurements Layout Task\n\n## Objective\n\nImplement `ldo_008_fer_mirror_ota`: a mirror-loaded NMOS-input error amplifier,\ndiode/tail bias network, PMOS pass device, feedback divider and series R/C\ncompensation. Preserve all seven source MOS groups as 81 physical fingers,\n40 MIM units and three high-poly resistors, with explicit substrate/well taps.\nThe internal compensation and divider remain part of the DUT.\n\nMOS dimensions and multiplicities are unchanged from the fixed IHP binding.\nThe source 160 pF capacitor becomes forty 51.64 um square MIM units, nominally\n160.331872 pF total. The source 2 kohm compensation resistor becomes one\nW=1 um / L=1.325 um `rhigh`; each source 9 kohm divider resistor becomes one\nW=1 um / L=6.235 um `rhigh`, with m=1 and b=0. Source capacitor PLUS is\n`czero`, MINUS is `vout`; the series resistor connects `egate` to `czero`.\nDivider upper/lower connect `vout–fb` and `fb–vss`. Every passive stays physical.\n\nThe external source bias is unchanged at 20 uA from VDD to NBIAS. The external\nreference is deliberately changed from the source 0.6 V to **0.5 V**, giving\na nominal 1.0 V output and defined headroom at 1.2/1.3 V supply. There is no\nseparate internal or external COUT; compensation still provides physical\noutput-connected capacitance. This is not a claim of zero internal storage.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: equivalent simulator representation.\n- `materials/testbench.spice`: DC bias, bilateral loop measurements and load steps.\n- `materials/startup.spice`: zero-state resistive-load startup.\n- `materials/sweeps.spice`: DC line/load and regulation-headroom sweeps.\n- `materials/fast.spice`: short, finely resolved load-impulse response.\n\nOrdered ports: `vdd vout vss nbias vref fb sense`. VDD/VSS are supply/return;\nVOUT is output; NBIAS receives the supply-fed current; VREF receives the 0.5 V\nreference. FB is the physical divider junction and SENSE is the amplifier's\nfeedback-input gate. Connect SENSE externally to FB through the zero-volt\nmeasurement source. This external link replaces the raw VLP's measurement role;\nit is not a manufactured voltage source. The relocated break exposes the\nactual input/divider boundary; the upper divider still connects to output.\nPMOS bodies connect through the VDD well tap; NMOS/poly bodies through the VSS\ntap. Preserve every W/L/m, body connection and physical passive. Equivalent\nparallel finger arrangements require native LVS and every other check to pass.\n\n## Operating Conditions\n\nUse typical IHP LV MOS, MIM and resistor models at 27 C. Main conditions are\nall combinations of VDD=1.2/1.3 V and initial load 0.1/0.5 mA. The current\nload doubles at 2–2.02 us and returns at 10.02–10.04 us. Run to 18 us with\n1 ns maximum step, Gear order 2, `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`\nand `vntol=1e-8`. Startup and fast tests use the same accuracy tolerances.\n\nFor AC, independent supply/reference/load sources have no AC excitation.\nPerform two sweeps, 0.01 Hz–1 GHz at 300 points/decade, at the same operating\npoint. VPROBE is oriented SENSE→FB and IINJ from ground→SENSE. Both have\nzero DC value and are ordinary external test sources. First set VPROBE AC=1 V,\nIINJ AC=0; second set VPROBE AC=0, IINJ AC=1 A. The 1 A is only a normalized\nlinear AC excitation, not a physical large-signal load.\n\nLet B=−I(VPROBE)/1 V and D=V(SENSE)/1 V from the first sweep; A=−I(VPROBE)/1 A\nand C=V(SENSE)/1 A from the second. With delta=AD−BC, define\n`T=(2*delta−A+D)/(1−2*delta+A−D)`. This bilateral two-port return ratio includes\nboth directional transmissions and port loading. The old voltage-only\n`−V(FB)/V(SENSE)` is not the accepted loop metric. Reset the circuit before\ntransient analysis; neither AC experiment changes its DC or transient topology.\n\nThis measures the declared external feedback loop with the internal circuit\nretained. It is not an exhaustive pole proof for all internal device loops or\nan RF/model-validity claim beyond the declared tests. Both first and final crossing phase margins must lie in [0, 180] degrees.\nThe full-sweep return-distance and return-phase metrics have only nonnegative\ndomain bounds; high-frequency gain is unbounded. They affect continuous\nquality without adding a stability acceptance screen.\n\nStartup uses 1/10 kohm loads and simultaneous linear supply/reference/bias\nramps from zero over 1/10 us: eight combinations including both supplies.\nRun with `uic`, no internal-node initial conditions, to 30 us with 2 ns\nmaximum step. Startup qualification is resistive-load and synchronized-ramp\nonly, not arbitrary reference sequencing or constant-current startup.\n\nDC sweeps: supply decreases from 1.3 to 0.8 V by 1 mV at 0.1/1 mA; line\nspan is measured over 1.2–1.3 V. Regulation floor is the first increasing\ncrossing of `abs(VOUT−1.0)=0.03 V`. Headroom is supply **minus actual output at\nthat crossing**, not supply minus the nominal target. The lower supply sweep\nis a boundary probe, not an extended qualified operating range. Separately\nsweep load 0.1–1 mA by 10 uA at each qualified supply, retaining both endpoints.\n\nFast conditions use the four main DC biases and a +1 uA load pulse beginning\nat 1 ns, 5 ps rise/fall and 1 ns high time. Run 100 ns with 5 ps maximum step.\nIt probes fast recovery around the solved operating point without modifying\ncompensation, adding an output capacitor or clamping an internal node.\n\nTransient extrema and AC sweep screens use the saved in-window samples;\nDC crossing locations and mean power use interpolation/integration. Numerical\nqualification also checks interpolated recovery-window endpoints.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ldo_008_fer_mirror_ota`, at most 10 MiB. Native main/maximal\nDRC has no waivers (standalone scope, density/antenna disabled). Strict named-port\nLVS includes physical taps. Functional outline is at most 3350 × 310 um and\nincludes all device, passive, contact and routing drawing layers; annotation\nand pin-purpose layers do not contribute. Magic candidate RC must preserve\nall physical MOS/MIM/poly and interconnect parasitics. Half-grid import is\nexplicit; extraction idealizes taps whereas source simulation uses their finite\nmodels. Distributed substrate resistance, PVT, mismatch, noise, fabrication\nsignoff and arbitrary-load stability are outside qualification.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `bias_v` | DC operating point: `v(nbias)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-@iload[current]`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((T))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `final_unity_hz` | AC: Crossing coordinate where `(db((T)))=0 fall=last`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `final_phase_margin_deg` | AC: `180+(find (180*cph((T))/pi) when (db((T)))=0 fall=last)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_return_distance` | AC: `vecmin((mag(1+(T))))`; sweep `dec 300 0.01 1g`. | 1 | target / target | 0 … +∞ | 1.0 | response |\n| `return_phase_excursion_deg` | AC: `vecmax(abs(180*cph(1+(T))/pi))`; sweep `dec 300 0.01 1g`. | deg | minimize / ratio | 0 … +∞ | 1e-12 | response |\n| `hf_gain_db` | AC: Maximum of `(db((T))) from=200meg to=1g`. | dB | minimize / db20 | −∞ … +∞ | — | response |\n| `minimum_v` | TRAN: Minimum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_v` | TRAN: Maximum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `recovery_load_v` | TRAN: Maximum of `(abs(v(vout)-1.0)) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_release_v` | TRAN: Maximum of `(abs(v(vout)-1.0)) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `startup_error_v` | TRAN: Maximum of `(abs(v(vout)-1.0)) from=25u to=30u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_peak_v` | TRAN: Maximum of `v(vout) from=0 to=30u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `startup_minimum_v` | TRAN: Minimum of `v(vout) from=0 to=30u`. | V | target / target | −∞ … +∞ | 1.3 | response |\n| `regulation_floor_v` | DC: Crossing coordinate where `(abs(v(vout)-1.0))=0.03 rise=1`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `headroom_v` | DC sweep: `(when (abs(v(vout)-1.0))=0.03 rise=1)-(find v(vout) when (abs(v(vout)-1.0))=0.03 rise=1)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `fast_peak_v` | Maximum absolute deviation of transient VOUT from its initial DC operating-point value over 0–100 ns in the fast load-pulse deck. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `fast_tail_v` | The same absolute deviation from initial DC VOUT over 80–100 ns. | V | target / target | 0 … 1.3 | 1.3 | response |\n\nArea reference: **172708.78 um2**. 126 expanded device instances; sum of device/contact envelopes 114596.5905 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **9**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nIHP regulators: regulation and headroom 22.5%; load recovery 22.5%; startup 13.5%; loop stability 13.5%; AC transfer and extrema 4.5%; internal bias 1.8%; quiescent current 7.2%; power 4.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `headroom_v` | 0.045000000000 |\n| `line_span_v` | 0.045000000000 |\n| `load_span_v` | 0.045000000000 |\n| `output_v` | 0.045000000000 |\n| `regulation_floor_v` | 0.045000000000 |\n| `recovery_load_v` | 0.112500000000 |\n| `recovery_release_v` | 0.112500000000 |\n| `startup_error_v` | 0.045000000000 |\n| `startup_minimum_v` | 0.045000000000 |\n| `startup_peak_v` | 0.045000000000 |\n| `final_phase_margin_deg` | 0.033750000000 |\n| `minimum_return_distance` | 0.033750000000 |\n| `phase_margin_deg` | 0.033750000000 |\n| `return_phase_excursion_deg` | 0.033750000000 |\n| `dc_gain_db` | 0.005625000000 |\n| `fast_peak_v` | 0.005625000000 |\n| `fast_tail_v` | 0.005625000000 |\n| `final_unity_hz` | 0.005625000000 |\n| `hf_gain_db` | 0.005625000000 |\n| `maximum_v` | 0.005625000000 |\n| `minimum_v` | 0.005625000000 |\n| `unity_hz` | 0.005625000000 |\n| `bias_v` | 0.018000000000 |\n| `quiescent_a` | 0.072000000000 |\n| `mean_power_w` | 0.022500000000 |\n| `power_w` | 0.022500000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use supplied IHP\nprimitives, KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Source records, host configuration\nand reference layouts stay outside standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml","case_sha256":"0112b24633297076d0939a9aa711cb2221e1205f570acd15f48196bc31f04326","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/circuit.cdl","netlist_sha256":"810d7fc0b63340bbd097f338e2a5c7fed29aaa5a51370abe30fc28b80297e1db","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.ldo_009_fer_5t_pass","in_core":false,"title":"Unity-Feedback Regulator with Internal Output Storage","pdk":"ihp-sg13g2","category":"Power & references","summary":"Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_009_fer_5t_pass","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Unity-Feedback Regulator with Internal Output Storage Layout Task\n\n## Objective\n\nLay out `ldo_009_fer_5t_pass` with the complete physical error amplifier, pass array,\ncompensation, output storage, bleeder and reference path.\n\nA five-transistor NMOS-input error amplifier drives a PMOS pass array;\nan on-chip diode-connected NMOS biases the tail mirror. The maintained circuit\nretains all seven source MOS groups (29 physical fingers), the output bleeder,\nreference-series resistor, Miller path and internal output capacitor. Unity\nfeedback senses output directly; there is no feedback divider. This adds\nphysical output storage, a reference impedance, explicit return ratio and\nzero-state startup to the existing externally loaded regulator coverage.\n\nThe original 2 pF Miller compensation is deliberately retuned to five physical\n36.515 um square units, nominally 10.0293 pF. Thirteen 50.635 um square MIM\nunits retain the approximately 50 pF internal COUT. Four physical high-poly\nsegments implement the approximately 100 kohm bleeder and one implements\napproximately 10 kohm reference resistance. MOS dimensions and multiplicities\nare unchanged; explicit substrate/well taps are added. The 20 uA bias source\nand 0.9 V reference are external. The raw zero-volt loop measurement source\nbecomes an external zero-volt link between distinct output and sense ports;\nit is not a manufactured voltage-source device or an ideal common-mode servo.\n\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model representation.\n- `materials/testbench.spice`: operating point, return ratio and load steps.\n- `materials/startup.spice`: distinct zero-state resistive-load startup deck.\n- `materials/sweeps.spice`: distinct DC line/load and headroom sweeps.\n\nOrdered ports: `vdd vout vss nbias ref0 sense`. VDD/VSS are supply/return;\nVOUT is regulated output; NBIAS receives an external 20 uA source **from VDD**;\nREF0 receives an external 0.9 V reference; SENSE connects externally to VOUT\nthrough the zero-volt probe. Preserve this explicit high-impedance feedback\ninterface. No other drive is permitted on SENSE, and no extra internal servo\nor reference generator is part of the DUT. PMOS bodies connect to the VDD\nwell through its tap; NMOS/poly bodies connect through the VSS substrate tap.\nPreserve all W/L/m and internal connectivity; equivalent parallel fingers\nare permitted only when native LVS and all measurements pass.\n\nAll following passives remain physical DUT devices, not external loads or\nparasitic annotations:\n\n- `cmil`: `vout` to `otao`, 5 parallel 36.515 × 36.515 um MIM units, nominal total 10.029301 pF.\n- `cout`: `vout` to `vss`, 13 parallel 50.635 × 50.635 um MIM units, nominal total 50.101434 pF.\n- `rbld`: `vout` to `vss`, 4 series high-poly segments, each W=1 um / L=17.465 um, m=1 and b=0.\n- `rref`: `ref0` to `vref`, 1 series high-poly segments, each W=1 um / L=6.94 um, m=1 and b=0.\n\n## Operating Conditions\n\nUse typical LV MOS, MIM and resistor models at 27 C. Qualification uses\nVDD=1.2/1.3 V and REF0=0.9 V. The main deck starts from a solved operating\npoint with 0.1/0.5 mA constant-current loads; each doubles at 2–2.02 us and\nreturns at 10.02–10.04 us. Run to 18 us with 1 ns maximum step, Gear order 2,\n`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nThere is no external output capacitor: internal COUT remains in candidate RC.\n\nAC injects 1 V in series with the zero-volt output-to-SENSE link. Reference,\nsupply and current sources have zero AC drive. At the high-impedance MOS input\nboundary, `T=-V(vout)/V(sense)` defines return ratio. Sweep 0.01 Hz–1 GHz\nat 150 points/decade. Gain uses `20 log10(abs(T))`; continuous phase has no\nfitted offset. Unity frequency is the first descending 0 dB crossing and phase\nmargin is 180 degrees plus phase there. Missing crossings are errors.\n\nStartup separately uses 900/9000 ohm output loads, with supply, reference and\nbias ramped linearly together from zero over 1/10 us. Use `uic`, no internal\nnode initial conditions and 2 ns maximum step to 30 us. The load is resistive\nthroughout startup; this is not constant-current startup qualification. All\neight supply/load/ramp combinations must pass. After startup, the main deck's\nconstant-current load contract and its finite recovery windows apply separately.\n\nDC sweeps use the same numerical tolerances. Sweep supply downward from 1.3\nto 0.8 V in 1 mV steps at 0.1/1 mA; measure line span only over 1.2–1.3 V.\nThe **regulation floor** is the first rising crossing of\n`abs(VOUT−0.9)=0.03 V` on that downward sweep. `headroom_v` is this supply\nminus 0.9 V. This includes error-amplifier headroom or pass-device limitation;\nit is not a pass-resistance-only dropout rating. The sweep below the floor is\na boundary probe and is not a qualified low-supply operating range. Separately,\nsweep load 0.1–1 mA in 10 uA steps at each qualified supply for load span.\n\n## Physical Requirements\n\nSubmit GDSII top cell `ldo_009_fer_5t_pass`, at most 10 MiB. Pass native main/maximal\nDRC with no waivers (standalone scope, density/antenna disabled), strict\nnamed-interface LVS including taps, and a 1600 × 330 um functional envelope.\nThe runtime outline includes complete device/contact/routing drawing layers;\nannotation and pin-purpose layers do not contribute to bounding-box area.\nCandidate Magic RC must retain all physical MOS/MIM/poly and interconnect\nparasitics. Half-grid GDS import is explicit. Magic idealizes tap connections;\nsource simulation uses finite contact models. Distributed substrate resistance,\nnoise, PVT, mismatch, arbitrary startup/reference sequencing, brownout and\nfabrication signoff remain unqualified.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `bias_v` | DC operating point: `v(nbias)`. | V | target / target | 0 … 1.3 | 1.3 | bias |\n| `quiescent_a` | DC operating point: `-i(VDD)-@iload[current]`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `dc_gain_db` | AC: Value of `(db((-v(vout)/v(sense)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(sense))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(sense)))/pi) when (db((-v(vout)/v(sense))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `minimum_v` | TRAN: Minimum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_v` | TRAN: Maximum of `v(vout) from=2u to=18u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `recovery_load_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_release_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `startup_error_v` | TRAN: Maximum of `(abs(v(vout)-0.9)) from=25u to=30u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `startup_peak_v` | TRAN: Maximum of `v(vout) from=0 to=30u`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `startup_minimum_v` | TRAN: Minimum of `v(vout) from=0 to=30u`. | V | target / target | −∞ … +∞ | 1.3 | response |\n| `regulation_floor_v` | DC: Crossing coordinate where `(abs(v(vout)-0.9))=0.03 rise=1`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `headroom_v` | DC sweep: `(when (abs(v(vout)-0.9))=0.03 rise=1)-0.9`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n\nArea reference: **65470.09 um2**. 54 expanded device instances; sum of device/contact envelopes 43312.7759 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **8**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nIHP regulators: regulation and headroom 22.5%; load recovery 22.5%; startup 13.5%; loop stability 13.5%; AC transfer and extrema 4.5%; internal bias 1.8%; quiescent current 7.2%; power 4.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `headroom_v` | 0.045000000000 |\n| `line_span_v` | 0.045000000000 |\n| `load_span_v` | 0.045000000000 |\n| `output_v` | 0.045000000000 |\n| `regulation_floor_v` | 0.045000000000 |\n| `recovery_load_v` | 0.112500000000 |\n| `recovery_release_v` | 0.112500000000 |\n| `startup_error_v` | 0.045000000000 |\n| `startup_minimum_v` | 0.045000000000 |\n| `startup_peak_v` | 0.045000000000 |\n| `phase_margin_deg` | 0.135000000000 |\n| `dc_gain_db` | 0.011250000000 |\n| `maximum_v` | 0.011250000000 |\n| `minimum_v` | 0.011250000000 |\n| `unity_hz` | 0.011250000000 |\n| `bias_v` | 0.018000000000 |\n| `quiescent_a` | 0.072000000000 |\n| `mean_power_w` | 0.022500000000 |\n| `power_w` | 0.022500000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives, KLayout, Magic and ngspice. Write `/workspace/output/final.gds` and\nexplicitly submit it through the harness. Host configuration, source records\nand reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml","case_sha256":"774402d4f540f236c7e54b4eb60eba62f666693a84801777e06517d2eaeefcee","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/circuit.cdl","netlist_sha256":"1788fa17f1811dd7e6596e6edc5c2edde837c878b590084fd239855c89ba50a4","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.smp_001_nmos_th","in_core":true,"title":"Physical NMOS Sample-and-Hold: Headroom and Retention","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Samples and holds a voltage with an NMOS switch and an internal storage capacitor.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/smp_001_nmos_th","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Physical NMOS Sample-and-Hold Layout Task\n\n## Objective\n\nImplement `smp_001_nmos_th`: a single-NMOS sampling switch with an internal\nphysical storage capacitor. Preserve the switch and stored-charge node, and\nmeet acquisition, turn-off pedestal, isolated-input feedthrough, hold drift\nand reacquisition requirements at the specified input and temperature points.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native physical circuit.\n- `materials/circuit.spice`: equivalent simulator representation.\n- `materials/testbench.spice`: independent stimuli and measurements.\n\nThe ordered interface is `vin clk vout vss`. VIN is driven through an external\n1 kohm source resistance; CLK receives the external clock; VOUT is the storage\nnode. The source's unused VDD port is removed. There is no DUT supply-current\nmetric or added artificial supply connection. Tie VSS to ground.\n\nRetain the `sg13_lv_nmos` with W=2 um, L=0.13 um, m=1 and drain/gate/source\nconnected to VIN/CLK/VOUT. Its body connects through the explicit VSS substrate\ntap. One `cap_cmim` with W=L=18.2 um connects its top plate to VOUT and bottom\nplate to VSS, nominally 499.772 fF at TT, 27 C. Preserve plate orientation.\nThe capacitor is internal physical storage, not a testbench load or an ideal\nreplacement. The native and simulator circuits include the same explicit tap.\n\nPreserve models, sizes and connectivity. Equivalent parallel fingering is\npermitted only when all physical and electrical checks pass. Do not add a\nbuffer, complementary switch, dummy cancellation device, hold-node servo,\nexternal storage capacitor or other topology change.\n\n## Operating Conditions\n\nUse typical MOS and capacitor models at 27 and 85 C. CLK is externally driven\nbetween 0 and 1.2 V, with 2 ns linear transitions. The ideal signal source SRC\ndrives VIN through 1 kohm. Qualify four sampled levels, `sample_v` = 0.1, 0.4,\n0.6 and 0.7 V, at both temperatures. At each point the off-state input is\nseparately driven to `hold_v` = 0 or 1.2 V: sixteen conditions. These are\nspecified sample points, not rail-to-rail or continuous-range qualification.\n\nThe finite sequence starts from a solved DC operating point with SRC=0 and\nCLK=1.2 V. SRC moves to `sample_v` during 20–22 ns. CLK falls during\n200–202 ns, isolating the storage node. SRC moves to `hold_v` during\n400–402 ns while CLK remains zero. SRC returns to `sample_v` during\n11.2–11.202 us; CLK rises during 11.4–11.402 us. Stop at 11.7 us.\nNo output load, DC bias source or discharge resistor is attached to VOUT.\n\nUse Gear order 2, KLU, maximum time step 2 ns, `gmin=1e-15`,\n`rshunt=1e15`, `reltol=1e-6`, `abstol=1e-15` and `vntol=1e-9`.\nThe numerical shunt is not a specified physical retention load. Save SRC,\nVIN, CLK, VOUT and both ideal voltage-source currents.\n\n## Physical Requirements\n\nSubmit GDSII top cell `smp_001_nmos_th`, at most 10 MiB, within an 80 × 80 um\nfunctional outline. Pass native IHP main/maximal DRC without waivers\n(standalone scope with density/antenna disabled), strict named-port LVS,\nfunctional geometry and candidate-derived Magic RC extraction. Functional\narea includes the complete device/contact/routing layers enumerated by the\nruntime outline; annotation and pin layers do not count.\n\nPost-layout simulation must consume the submitted layout's extracted NMOS,\nphysical MIM, junction geometry and interconnect RC. The isolated Magic import\nuses half-grid subdivision and `gds_readonly=false`; the submitted GDS remains\nimmutable. No diagnostic is waived. Source simulation retains the finite tap\nmodel; Magic idealizes the tap connection. Distributed substrate noise and\nfabrication signoff are outside this contract.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `track_error_v` | Maximum absolute VOUT minus target over 80–190 ns; target is VSRC sampled at 180 ns. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `pedestal_abs_v` | Absolute difference between VOUT at 220 ns and 180 ns (held minus tracked sample). | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `feedthrough_peak_v` | Maximum absolute VOUT minus its 390 ns sample over 400–450 ns, during the input transition in hold. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `hold_drift_v` | Absolute difference between VOUT at 11 us and 1 us. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `hold_error_v` | Maximum absolute VOUT minus target over 220 ns–11 us; target is VSRC at 180 ns. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `reacquire_error_v` | Maximum absolute VOUT minus target over 11.48–11.69 us; target is VSRC at 180 ns. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `clock_energy_j` | Integral of max(-V(CLK)*I(VCLK), 0) over 0–11.7 us; returned clock energy is excluded. | J | minimize / ratio | 0 … +∞ | 1e-21 | supply |\n| `target` | TRAN: Value of `v(src) at=180n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `track_v` | TRAN: Value of `v(vout) at=180n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `held_v` | TRAN: Value of `v(vout) at=220n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `before_input_v` | TRAN: Value of `v(vout) at=390n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `after_input_v` | TRAN: Value of `v(vout) at=450n`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `hold_start_v` | TRAN: Value of `v(vout) at=1u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `hold_end_v` | TRAN: Value of `v(vout) at=11u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `reacquired_v` | TRAN: Value of `v(vout) at=11.65u`. | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `pedestal_v` | Signed VOUT(220 ns) − VOUT(180 ns). | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `feedthrough_v` | Signed VOUT(450 ns) − VOUT(390 ns). | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n| `drift_v` | Signed VOUT(11 us) − VOUT(1 us). | V | diagnostic | −∞ … +∞ | — | unscored diagnostic |\n\nArea reference: **661.39 um2**. 3 expanded device instances; sum of device/contact envelopes 407.6560 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTrack/hold switches: acquisition 35%; hold fidelity 45%; clock energy 10%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `reacquire_error_v` | 0.175000000000 |\n| `track_error_v` | 0.175000000000 |\n| `feedthrough_peak_v` | 0.112500000000 |\n| `hold_drift_v` | 0.112500000000 |\n| `hold_error_v` | 0.112500000000 |\n| `pedestal_abs_v` | 0.112500000000 |\n| `clock_energy_j` | 0.100000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`\nfor the frozen inputs, requirements, reviewed IHP primitives and harness\nfeedback. Work with the supplied KLayout, Magic and ngspice resources.\nWrite `/workspace/output/final.gds` and explicitly submit through the harness.\nReference GDS, source records and host configuration are not standard inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml","case_sha256":"1be1c1ee7e3f211added229b308a5fcb1b07d2610bf187ef2d0c2606b7285fae","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/circuit.cdl","netlist_sha256":"846cb6797fae4bca4b793d23239e778299f46ec0b3342e44d2a014ca5d6b3802","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.sw_001_transmission_gate_pair","in_core":false,"title":"Bidirectional CMOS Transmission Gate","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Transfers analog signals bidirectionally through a CMOS transmission gate.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_001_transmission_gate_pair","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Bidirectional CMOS Transmission Gate Layout Task\n\n## Objective\n\nImplement `sw_001_transmission_gate_pair` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. The fixed IHP binding has one NMOS and one PMOS, each W=2 um, L=0.13 um, m=1. Both connect the bidirectional signal terminals, with the NMOS body at vss and PMOS body at vdd. No internal clock generator is added.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/forward.spice`, `materials/reverse.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `port_a port_b vctl vctl_not vdd vss`. The fixture supplies complementary controls externally. Both signal/control ports stay within 0–1.5 V. Native body taps remain physically checked; finite well/substrate resistances are outside the Magic RC compact-model boundary.\n\n## Operating Conditions\n\n1.5 V supply. DC on/off conditions use signal common modes 0.15, 0.75 and 1.35 V and both signs of a 10 mV port difference. On controls are 1.5/0 V; off controls are 0/1.5 V. Ron is the absolute port drop divided by actual port-source current, accepted only above 1 nA and independently checked for the correct current direction. Off leakage uses held voltages at both terminals. Dynamic tests drive each direction separately through 100 ohm, with a 1 pF receiving load and 1 Mohm resistor to the selected common mode. Signal steps are common-mode ±50 mV with 1 ns edges starting at 20 ns; separate static-input runs isolate control feedthrough. Complementary controls turn off at 70 ns for 60 ns, with matched 1 ns edges, no extra overlap/dead interval. Runs start from DC and end at 180 ns with maximum 50 ps steps. The finite receiving resistance defines the off-node behavior physically. The isolated window-marker source only schedules exact time breakpoints; it connects to no DUT terminal.\n\nAll source/candidate jobs share exactly the same fixtures, parameters, nominal TT models and 27 C temperature. Testbench control blocks and frozen runtime parameters define all stimulus and measurement details. Source simulation is independent of the reference GDS. No paper or data-sheet performance number is an acceptance threshold.\n\n## Physical Requirements\n\nSubmit a valid GDSII containing top cell `sw_001_transmission_gate_pair`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor.\n\nPost-layout simulation must consume native candidate-GDS-derived distributed wire RC, retaining every physical MOS, resistor and capacitor. Native LVS alone does not substitute for PEX. Magic uses ideal well/substrate tap connections; source simulation retains native finite tap models. This boundary does not establish distributed substrate resistance or substrate-noise accuracy.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nCoefficient 3 covers local bidirectional analog conduction and loaded control transitions. Tracking error is integrated over exactly 20–60 ns; control-edge excursion uses the inclusive 69–75 ns sample window; held mean shift compares 90–100 ns with 65–69 ns. These are loaded feedthrough/hold observations, not an intrinsic charge-injection constant or perfect floating-node retention. No energy score is claimed: body-rail current alone cannot measure control and signal-driver energy.\n\nEvery required condition must yield finite, valid measurements and pass the functional bounds below. Missing or invalid extraction/measurements are evaluation errors, not low performance scores.\n\n| Metric | Unit | Definition | Dimension / normalization | Functional bounds |\n| --- | --- | --- | --- | --- |\n| `ron_ohm` | ohm | 10 mV DC port drop divided by measured port current | response / ratio; scale 1 | lower=0 |\n| `on_current_a` | A | Absolute DC on current; excludes numerical-noise division | unscored / functional | lower=1e-09 |\n| `leakage_a` | A | Off-state current with both ports held at defined voltages | bias / ratio; scale 1e-12 | lower=0 |\n| `kcl_a` | A | External KCL including control and body sources | diagnostic; unscored | Producer validity guard; see below |\n| `tracking_error_v` | V | Mean loaded dynamic tracking error, 20–60 ns | response / ratio; scale 0.0001 | lower=0 |\n| `feedthrough_v` | V | Output excursion during turn-off, 69–75 ns | response / ratio; scale 0.0001 | lower=0 |\n| `hold_shift_v` | V | Finite loaded hold mean 90–100 ns minus 65–69 ns | response / target; scale 0.1 | Finite measurement |\n\nTarget normalization preserves the source operating point/transfer using its declared voltage or gain scale. Ratio floors prevent zero-error/noise-floor division; they are numerical normalization units, not acceptance tolerances. Voltage bounds are the declared physical rails; producer validity guards distinguish measurements from numerical noise. There is no source-relative performance hard cutoff.\n\nThe area anchor is **300 um²**: twice the sum of `(W + 6 um) × (L + 8 um)` over every expanded MOS and physical passive unit (2 units, sum 130.080000 um²), rounded upward to 100 um². Contact/well/tap/isolation envelopes are included in the 6/8 um allowances; the factor two allows routing. This is an engineering compact-footprint estimate, independent of measured witness area, not a foundry minimum or demonstrated optimum. Task coefficient: **3**.\n\n\n### Score weights\n\nTransmission/chopper switches: on-state conduction 21.4%; off-state leakage 17.1%; transfer fidelity 25.7%; switching disturbance 25.7%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `ron_ohm` | 0.214285714286 |\n| `leakage_a` | 0.171428571429 |\n| `tracking_error_v` | 0.257142857143 |\n| `feedthrough_v` | 0.128571428571 |\n| `hold_shift_v` | 0.128571428571 |\n\n## Tools and Submission\n\nSolve budget: **8 hours**.\n\nUse the runtime task and reviewed PDK resource bundle for the declared native checks, extraction and ngspice measurements. Write `output/final.gds` with the required top cell, then explicitly submit its path through the session submission interface; creating a file alone is not submission. Reference GDS, qualification results and development sources are excluded from standard solver inputs.\n\nThe source and extracted-candidate decks require absolute external DC current\nconservation residual `kcl_a <= 1e-09 A`. A larger residual aborts\nsimulation and produces an evaluator error with unknown score, rather than a\nfunctional rejection. The reported residual is an unscored diagnostic.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml","case_sha256":"1b1360f0bb6680a736fdc9041626be634b9b576aa5cfc8c85e6c0b41321ec7a7","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl","netlist_sha256":"541f878fd2a9d6f0eab4f125d64563a2a2e56b0deb4fa7adef4d2db88adc11cf","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.sw_002_chopper_diff","in_core":false,"title":"Differential Polarity-Commutating Switch","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Commutates differential signal polarity with a clock-controlled switch network.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_002_chopper_diff","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Differential Polarity-Commutating Switch Layout Task\n\n## Objective\n\nImplement `sw_002_chopper_diff` in ihp-sg13g2 and submit self-contained GDS. Eight MOS devices form four transmission paths that connect a differential input directly or with reversed polarity. The two complementary clock nets are independent layout ports. Fixed IHP W/L/m are retained; explicit substrate/well taps are included in both maintained circuit representations.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit. `materials/circuit.spice` is its equivalent simulator model-call representation. `materials/testbench.spice` defines measurements, and this problem is the description input.\nOrdered ports: `va_p va_n vb_p vb_n vctl vctl_not vdd vss`. In order: Positive input, negative input, positive output, negative output, direct-path clock, complementary clock, supply, and return.\n\nPreserve connectivity, W/L/m, passive geometry and body connections. Provide physical contacts. Placement and routing are free; splitting and source/drain interchange are allowed only under the declared LVS equivalences. No statistical matching or common-centroid constraint is scored. Ideal external sources, loads and fixtures belong to the testbench, not the DUT.\n\n## Operating Conditions\n\nTemperature is 27 C. Typical IHP low-voltage MOS and resistor models; explicit finite physical tap models and a 1e12 ohm ngspice numerical shunt at each node. Candidate Magic RC is extracted with zero coupling-capacitance threshold.\n\nVDD = 1.5 V; VSS = 0 V; input common mode = 0.75 V; differential input = -0.2 or +0.2 V. Each output has an external 10 kohm resistor to common mode and 1 pF to ground. DC checks both clock states (vctl = 0 or 1.5 V), giving four conditions. Transient clocks are complementary 0/1.5 V pulses, delay 1 us, rise/fall 2 ns, high width 5 us and period 10 us; output/max step is 0.1 ns with Gear order 2, stop time 12 us. A second transient sets both inputs to 0.75 V to separate clock feedthrough/injection from signal reversal. The finite clock slopes deliberately permit overlap; non-overlap operation is not claimed.\n\n## Physical Requirements\n\nTop cell `sw_002_chopper_diff`, named ports, resolved hierarchy, at most 10 MiB. Pass artifact, IHP main and maximal DRC, with density and antenna outside this standalone scope; strict named-port LVS; geometry, without DRC waivers. Functional bounding box must fit within 90 by 40 um. The footprint includes every process device and routing drawing layer in the frozen runtime outline list: active, wells, implants, poly, contacts, metals/vias and device/passive markers. Annotation and pin-purpose shapes are excluded. All functional routing must use drawing layers.\n\nEvery scored simulation consumes the submitted GDS-derived distributed wiring RC and extracted device geometry. Ron includes the declared terminal loading and common mode. Injection is net terminal charge integrated under driven equal inputs, not stored charge on a disconnected sampler. Noise, chopping an amplifier, RF/EM, mismatch and other clock rates are outside scope. Fabrication signoff is not claimed.\n\n## Electrical Requirements and Scoring\n\nAll 4 operating conditions must complete. Every finite observation must meet its inclusive band; aggregation cannot hide a failing condition. Missing measurements/crossings or incomplete extraction do not establish success.\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `ron_p` | Absolute (selected positive-output input minus V(vb_p)) / current through its 10 kohm load | ohm | minimize / ratio | 0 … +∞ | 1e-06 |\n| `ron_n` | Absolute (selected negative-output input minus V(vb_n)) / current through its 10 kohm load | ohm | minimize / ratio | 0 … +∞ | 1e-06 |\n| `transfer` | DC output differential divided by the selected signed input differential | V/V | target / target | −∞ … +∞ | 1.0 |\n| `common_error_v` | Absolute DC output common-mode minus 0.75 V | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `straight_gain` | Output differential / input differential at 4 us | V/V | target / target | −∞ … +∞ | 1.0 |\n| `crossed_gain` | Output differential / input differential at 9 us | V/V | target / target | −∞ … +∞ | 1.0 |\n| `common_glitch_v` | Maximum absolute output common-mode minus 0.75 V over 1–1.1 us with equal inputs | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `differential_glitch_v` | Maximum absolute output differential over 1–1.1 us with equal inputs | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `input_charge_c` | Absolute integral of I(VAP)+I(VAN) over 1–1.1 us with equal inputs | C | minimize / ratio | 0 … +∞ | 1e-21 |\n| `clock_power_w` | Average positive supplied power from both clock sources over 2–12 us with equal inputs; returned energy is not credited | W | minimize / ratio | 0 … +∞ | 1e-12 |\n\nArea reference: **459.68 um2**. 10 expanded device instances; sum of device/contact envelopes 278.7760 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nTransmission/chopper switches: on-state conduction 23.7%; transfer fidelity 28.4%; switching disturbance 28.4%; clock power 9.47%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `ron_n` | 0.118421052632 |\n| `ron_p` | 0.118421052632 |\n| `common_error_v` | 0.071052631579 |\n| `crossed_gain` | 0.071052631579 |\n| `straight_gain` | 0.071052631579 |\n| `transfer` | 0.071052631579 |\n| `common_glitch_v` | 0.094736842105 |\n| `differential_glitch_v` | 0.094736842105 |\n| `input_charge_c` | 0.094736842105 |\n| `clock_power_w` | 0.094736842105 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse reviewed resources from `/protocol/resources.json`. KLayout checks, Magic extracts RC, and ngspice simulates. Frozen constraints and requirements are in `/protocol/task.json`; `/protocol/harness.json` describes the harness. If available, use the published `process-feedback` helper for interim checks. Write `/workspace/output/final.gds` and explicitly submit using `python -I /protocol/submit.py`.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml","case_sha256":"684990b80dc0182f03f2ab08b93f9e005165274c0db7e444ab00845b3b618a4b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/circuit.cdl","netlist_sha256":"e0b1c58cdd6e35af46612beae826db9d950ca0e83ddb0297ee224699fd9c3c7a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.sw_003_binary_capbank","in_core":true,"title":"Three-Bit MIM Capacitive Transfer Bank","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Selects capacitive transfer using a three-bit bank of physical MIM capacitors.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_003_binary_capbank","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Three-Bit MIM Capacitive Transfer Bank Layout Task\n\n## Objective\n\nImplement `sw_003_binary_capbank` in IHP SG13G2 and submit a self-contained GDS. Twelve minimum-size MOS (W/L = 0.15/0.13 um) select the bottom plates of a 1:1:2:4 MIM capacitor bank between vinp and VCM. Eight identical 25.85 by 25.85 um cap_cmim units implement those weights, each nominally about 1.00647 pF. Explicit physical substrate and well taps are included. For code k, the ideal capacitive transfer is (1+k)/8. Qualification covers all eight static codes and bipolar input steps at each fixed code; live code transitions, ADC conversion, charge redistribution after a code change and mismatch linearity are outside scope.\n\n## Inputs and Interface\n\n`materials/circuit.cdl` is the authoritative physical circuit; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` supplies measurement apparatus. This problem is the description input. The ordered ports are `vinp vout VCM VDD VSS V_D0 V_D0_NOT V_D1 V_D1_NOT V_D2 V_D2_NOT`: signal input, floating output, common-mode reference, supply/return and three independent pairs of complementary code controls. SPICE names are case-insensitive; preserve these physical labels.\n\nPreserve connectivity, MOS W/L/m, capacitor dimensions and unit multiplicities, and body/tap connections. Placement and routing are free. Device splitting/combination and source/drain interchange are allowed only when accepted by the declared native LVS equivalences. No common-centroid or statistical matching requirement is scored. All specified ideal external sources, loads and measurement apparatus belong outside the DUT.\n\n## Operating Conditions\n\nTypical IHP low-voltage MOS, typical resistor and capacitor models at 27 C; VDD = 1.5 V and VSS = 0 V. Each node has the declared 1e12 ohm numerical shunt. Transient integration uses Gear order 2 with a 1 ns output and maximum step. Physical taps have finite source-model resistance; Magic treats well/substrate ties ideally. Distributed silicon substrate resistance, statistical mismatch, PVT, noise and RF/EM are outside scope.\n\nAll eight binary codes are separate required conditions. Bit k is driven by 1.5*bk V and its complement by 1.5*(1-bk) V; controls remain static. VCM = 0.75 V. VINP has DC 0.65 V and unit AC amplitude. AC uses 50 points/decade from 1 kHz to 100 MHz; acceptance measurements are at 10 kHz. VINP stays at 0.65 V through 10 us, rises to 0.85 V at 10.002 us, holds through 30 us, returns to 0.65 V at 30.002 us and holds through 50 us. Vout has an external 1e12 ohm return to ground, in addition to the numerical shunt; no ideal external holding capacitor is added. Absolute output DC is not a retained sample requirement: measurements compare increments. The testbench expected-value voltage source is measurement apparatus only.\n\n## Physical Requirements\n\nThe GDS top cell is `sw_003_binary_capbank`, with a 10 MiB maximum file size. Provide physical, correctly connected and accessible labeled interface metal; retain every named port. Pass IHP main and maximal DRC (density and antenna excluded for this standalone block), strict named-interface LVS and a functional bounding box no larger than 460 by 75 um. No DRC waivers are used. The functional footprint includes device, passive, implant, well and complete routing layers; excludes annotations/pin text and nonfunctional markers. Its explicit GDS layer/datatype set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. The area is the bounding-box area of those layers, not summed metal area.\n\nThe candidate GDS must pass artifact, DRC, LVS and hard geometry before extraction. Magic candidate-derived distributed interconnect resistance and capacitance, with zero coupling-capacitance threshold, feed the supplied testbench. Internal MIM devices remain in candidate extraction. Source simulation alone cannot establish acceptance. This is nominal block qualification, not fabrication signoff.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |\n| --- | --- | --- | --- | --- | --- |\n| `gain_vv` | Magnitude V(out)/V(vinp) at 10 kHz, unit AC input | V/V | target / target | −∞ … +∞ | 1.0 |\n| `phase_deg` | Phase of V(out)/V(vinp) at 10 kHz, in degrees | deg | target / target | −∞ … +∞ | 180 |\n| `input_cap_f` | Imaginary part of -I(VI), divided by 2 pi f at 10 kHz, unit AC input | F | minimize / ratio | 0 … +∞ | 1e-21 |\n| `gain_error` | Absolute gain_vv minus (1+code)/8 | V/V | minimize / ratio | 0 … +∞ | 1e-09 |\n| `step_gain` | [V(out) at 29 us minus V(out) at 9 us] / 0.2 V | V/V | target / target | −∞ … +∞ | 1.0 |\n| `step_error` | Absolute step_gain minus (1+code)/8 | V/V | minimize / ratio | 0 … +∞ | 1e-09 |\n| `return_error_v` | Absolute V(out) at 49 us minus V(out) at 9 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n| `settling_error_v` | Maximum absolute V(out) minus its 29 us value, over 20–29 us | V | minimize / ratio | 0 … +∞ | 1e-06 |\n\nArea reference: **9532.78 um2**. 22 expanded device instances; sum of device/contact envelopes 6227.9559 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nBinary capacitor bank: code transfer accuracy 54%; recovery 27%; phase 9%; area 10%. Each objective's weight is divided equally among its metrics. Redundant transfer and loading observations are retained with zero weight; their measurement validity and bounds still apply.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `gain_error` | 0.270000000000 |\n| `step_error` | 0.270000000000 |\n| `return_error_v` | 0.135000000000 |\n| `settling_error_v` | 0.135000000000 |\n| `phase_deg` | 0.090000000000 |\n| `gain_vv` | 0 |\n| `input_cap_f` | 0 |\n| `step_gain` | 0 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the reviewed SG13G2 device/rule/model resources supplied through `/protocol/resources.json` and the task definitions in `/protocol/task.json`. KLayout supplies layout and physical checks; Magic supplies candidate RC; ngspice consumes the declared deck. Discover available feedback through the runtime harness protocol. Write `output/final.gds` in the workspace and explicitly submit that GDS through the submission protocol. Reference layouts, source checkouts and authoring scripts are not solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml","case_sha256":"0a972bb98c65bf095dda4123587fecb7a0e3ff15be1e8692216a0a64ae098123","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/circuit.cdl","netlist_sha256":"dec8a6b73b1345482fdf6cf69f3065c000b7cf50ddebe04ee1738603f0b24c77","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.trm_001_vcr","in_core":false,"title":"Resistor-Pullup NMOS Shunt Trim","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Controls a resistor-pulled output using an NMOS shunt driven by an analog voltage.","source_url":"https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/trm_001_vcr","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Resistor-Pullup NMOS Shunt Trim Layout Task\n\n## Objective\n\nImplement `trm_001_vcr`, a voltage-controlled NMOS shunt with a physical\napproximately 200 kohm supply pullup. Preserve the source W=2 um / L=0.5 um\nNMOS, eight series high-poly segments and explicit substrate tap. Qualification\nmeasures loaded trim range, monotonic control, operating-point conductance,\ntemperature/load sensitivity and finite control-step recovery. This is an\nunbuffered nonlinear control node, not an ideal programmable resistor or DAC.\n\n## Inputs and Interface\n\n- `materials/circuit.cdl`: authoritative native LVS circuit.\n- `materials/circuit.spice`: matching process-model representation.\n- `materials/testbench.spice`: control sweeps, conductance and loaded recovery.\n\nOrdered ports: `vdd vcode vout vss`. VDD is supply, VCODE controls the shunt\nMOS gate, VOUT is the pullup/shunt junction and VSS is return. The NMOS source\nand substrate connect through the explicit VSS tap; the physical poly body\nuses the same substrate. Eight series `rhigh` segments connect VDD to VOUT,\neach W=1 um / L=17.465 um, m=1 and b=0. They replace the source ideal 200 kohm\nresistor and remain inside the DUT. Preserve device models, dimensions and\nconnectivity; native equivalent resistor merging is allowed only when LVS and\nall other checks pass. There are no internal ideal sources or extra bias ports.\n\n## Operating Conditions\n\nTypical IHP LV MOS/poly models, all eight combinations of supplies 1.1/1.3 V,\ntemperatures 27/85 C and external output loads 500 kohm/1 Mohm. A 1 pF output\nload is external test apparatus. DC operating point uses VCODE=0.4 V.\nSweep VCODE from 0.2 to 0.8 V in 2 mV increments; every sampled slope must\nsatisfy maximum_slope <= 0 V/V: increasing NMOS gate control must not\nincrease the pullup/shunt output voltage. This is the declared sampled sweep,\nnot a proof of global monotonicity beyond the control interval.\n\nFor transient, VCODE rises 0.3→0.5 V at 2–2.02 us and falls at\n10.02–10.04 us, repeating every 16 us. Run to 18 us with 2 ns maximum step,\nGear order 2, `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.\nNo output clamp, feedback servo or ideal storage is internal to the DUT.\n\n## Physical Requirements\n\nSubmit GDSII top cell `trm_001_vcr`, at most 10 MiB. Pass native main/maximal DRC\nwithout waivers (standalone scope, density/antenna disabled), strict named-port\nLVS with explicit tap and a 110 × 80 um functional outline. The runtime\noutline includes complete device, resistor, contact and routing drawing layers;\nannotation/pin-purpose layers do not contribute to its area.\nCandidate Magic RC must preserve physical MOS/poly and interconnect parasitics.\nThe extractor idealizes the substrate contact; source simulation includes the\nfinite tap model. Distributed substrate effects, PVT, mismatch, noise,\nprecision trimming and fabrication signoff remain outside qualification.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `power_w` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `high_v` | DC VOUT at VCODE=0.2 V. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `low_v` | DC VOUT at VCODE=0.8 V. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `knee_code_v` | First VCODE value where VOUT falls through 0.2 V during the 0.2–0.8 V code sweep (2 mV steps). | V | target / target | 0 … 1.3 | 1.3 | response |\n| `maximum_slope` | Maximum sampled derivative dVOUT/dVCODE over 0.2–0.8 V; nonpositive is the declared sign-domain bound. | V/V | target / target | −∞ … 0 | 0.1 | response |\n| `span_v` | VOUT at VCODE=0.2 V minus VOUT at VCODE=0.8 V. | V | target / target | 0 … 1.3 | 1.3 | response |\n| `conductance_04_s` | Shunt conductance [-I(VDD) − VOUT/RLOAD]/VOUT at VCODE=0.4 V; subtract external load current. | S | target / target | −∞ … +∞ | 0.00015 | response |\n| `conductance_06_s` | The same shunt-conductance definition at VCODE=0.6 V. | S | target / target | −∞ … +∞ | 0.0005 | response |\n| `conductance_ratio` | conductance_06_s / conductance_04_s, using the same load and temperature. | 1 | target / target | −∞ … +∞ | 5 | response |\n| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-(avg v(vout) from=9u to=9.5u))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-(avg v(vout) from=17u to=17.5u))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `step_span_v` | Transient: `(avg v(vout) from=17u to=17.5u)-(avg v(vout) from=9u to=9.5u)`. | V | target / target | 0 … 1.3 | 1.3 | response |\n\nHigh/low endpoints are continuous source-paired quality observations. Their\n0–1.3 V bounds express the nonnegative, supply-limited output domain; shunt-control function does not require a narrower absolute endpoint range.\n\nArea reference: **636.57 um2**. 10 expanded device instances; sum of device/contact envelopes 391.7515 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nVoltage-controlled trim element: control characteristic 36%; conductance 22.5%; loaded recovery 18%; operating range 4.5%; power 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `knee_code_v` | 0.090000000000 |\n| `maximum_slope` | 0.090000000000 |\n| `span_v` | 0.090000000000 |\n| `step_span_v` | 0.090000000000 |\n| `conductance_04_s` | 0.075000000000 |\n| `conductance_06_s` | 0.075000000000 |\n| `conductance_ratio` | 0.075000000000 |\n| `recovery_down_v` | 0.090000000000 |\n| `recovery_up_v` | 0.090000000000 |\n| `high_v` | 0.015000000000 |\n| `low_v` | 0.015000000000 |\n| `output_v` | 0.015000000000 |\n| `mean_power_w` | 0.045000000000 |\n| `power_w` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nDiscover inputs, resources and feedback through `/protocol/task.json`,\n`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP\nprimitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`\nand explicitly submit through the harness. Host configuration, source records\nand reference layouts are outside the standard solver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml","case_sha256":"9a9d46760b695a72297235a62f694c4bf1ff8cb8f2f63cd37846f37aa659c587","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/circuit.cdl","netlist_sha256":"ed94062ae8c8856ffe51593d5134a9926c266e6620767f13d491a21ad288136a","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"ihp-sg13g2.analog-db.vref_001_vgs","in_core":false,"title":"Mixed LV/HV VGS Reference with Picoampere Load and Zero-State Recovery","pdk":"ihp-sg13g2","category":"Power & references","summary":"Establishes a voltage reference using a mixed low/high-voltage two-transistor core.","source_url":"https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/raw/vref_001_vgs/ihp-sg13g2/_dut.spice","status":"qualified","collection":"analog-db","task_kind":"netlist_to_gds","problem":"# Mixed LV/HV VGS Reference Layout Task\n\n## Objective\n\nImplement the two-transistor `vref_001_vgs` reference with its original device\nsizes and connections. An upper LV NMOS has gate and source at VREF; a lower\nHV NMOS is diode-connected. The maintained function is a high-impedance,\napproximately 0.36 V reference for picoampere loads. It is not a bandgap,\nprecision reference, buffered supply or temperature sensor.\n\n## Inputs and Interface\n\nThe declared inputs are this description, `materials/circuit.cdl` for native\nLVS, the equivalent `materials/circuit.spice`, and `materials/testbench.spice`.\nOrdered ports are `vdd vref vss`: positive supply, reference output, and return.\nThe LV NMOS has W/L=2.5/2 um, D=VDD, G=S=VREF, B=VSS. The HV NMOS has\nW/L=1/2 um, D=G=VREF, S=B=VSS. Both multiplicities are one.\n\nRetain the explicit 40 × 2 um marked substrate tap (A=80 um², P=84 um),\nwith both terminals on VSS. An unmarked substrate contact establishes that\nsame-net body boundary. Additional legal same-net contacts are permitted\nonly when native LVS and the declared checks pass. Do not replace the HV\ndevice with an LV device or change either gate/source connection. The source\nsimulator represents the marked tap with its finite 5.9756097561 ohm PDK\nequivalent; its two terminals are the same net. Parallel fingering is allowed\nonly if total dimensions, multiplicity, body mapping and all checks agree.\n\n## Operating Conditions\n\nUse the pinned IHP typical LV/HV PSP models. Nine jobs combine VDD=1.0,\n1.2 and 1.5 V with temperatures −20, 27 and 85 °C. The only external\ncapacitance is 100 fF from VREF to VSS. No numerical `rshunt` is added.\nUse `gmin=1e-16 S`, `reltol=1e-6`, `abstol=1e-18 A`, `vntol=1e-10 V`,\nGear order two and maximum transient step 1 us. These small currents require\nthe specified numerical conditioning; default simulator tolerances do not\nestablish this contract.\n\nFor each job, the DC operating point has the declared supply and zero load.\nThe separate transient starts with VREF=0 and otherwise zero stored charge\n(`uic`). VDD rises linearly from zero to its declared value over 100 us.\nThe run ends at 50 ms. ILOAD is positive when withdrawing current from VREF:\n0→+1 pA during 10–10.01 ms, +1→0 pA during 20–20.01 ms,\n0→−1 pA during 30–30.01 ms, and −1→0 pA during 40–40.01 ms.\nIt holds each value between edges. Negative load is an external current\ninjection, not on-chip power generation.\n\nEach job also sweeps supply 1.0–1.5 V in 10 mV increments at its declared\ntemperature, load −1–+1 pA in 0.1 pA increments at its declared supply and\ntemperature, and temperature −20–85 °C in 5 °C increments at its declared\nsupply. DC sweeps have no time-varying stimulus; line and temperature sweeps\nuse zero load. All endpoints participate. These are finite sampled conditions,\nnot process-corner, mismatch or arbitrary temperature/load guarantees.\nThe DC load sweep uses a −1–+1 V external control in 0.1 V increments and\na 1 pA/V transconductance stimulus; it avoids a tiny-current sweep endpoint\ntolerance without changing the DUT or its actual −1–+1 pA load range.\n\n## Physical Requirements\n\nSubmit a GDSII with top cell `vref_001_vgs`, at most 1 MiB. It must pass\nnative main/maximal SG13G2 DRC without waivers, strict named-port LVS, and a\n100 × 100 um functional outline. Density and antenna checks are outside\nthe declared standalone DRC scope. The footprint includes every device,\ncontact and routing drawing layer enumerated in the runtime constraints;\nannotation and pin-purpose layers cannot conceal functional geometry.\n\nCandidate-derived Magic distributed RC must retain both LV/HV model calls,\ntheir dimensions and their actual junction/interconnect loading. Extraction\nidealizes well/substrate contacts and does not establish distributed substrate\nresistance or noise. Only Metal3 text layer 30/25 supplies extraction labels;\nnative DRC/LVS still inspect the complete original GDS and physical taps.\nThe external 100 fF load is additional to candidate capacitance.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `reference_v` | Unloaded DC VREF | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `supply_a` | Unloaded DC −I(VDD) | A | minimize / ratio | 0 … +∞ | 1e-12 | bias |\n| `power_w` | Unloaded DC −VDD·I(VDD) | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `startup_error_v` | Maximum absolute reference error, 8–9 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `load_error_v` | Same, 18–19 ms under +1 pA | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `release_error_v` | Same, 28–29 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `injection_error_v` | Same, 38–39 ms under −1 pA | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `return_error_v` | Same, 48–49 ms | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `minimum_v` | Minimum VREF over the full 0–50 ms startup/load transient. | V | target / target | −∞ … +∞ | 1.5 | bias |\n| `maximum_v` | Maximum VREF over the full 0–50 ms startup/load transient. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `line_min_v` | DC sweep: `vecmin(v(vref))`; sweep `VDD 1.0 1.5 .01`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `line_max_v` | DC sweep: `vecmax(v(vref))`; sweep `VDD 1.0 1.5 .01`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `line_span_v` | Supply-sweep maximum minus minimum | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `temperature_min_v` | DC sweep: `vecmin(v(vref))`; sweep `temp -20 85 5`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `temperature_max_v` | DC sweep: `vecmax(v(vref))`; sweep `temp -20 85 5`. | V | target / target | 0 … 1.5 | 1.5 | bias |\n| `temperature_span_v` | Temperature-sweep maximum minus minimum | V | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `output_resistance_ohm` | (Unloaded DC VREF − DC VREF at +1 pA)/1 pA | ohm | minimize / ratio | 0 … +∞ | 1e-06 | response |\n| `loaded_reference_v` | DC VREF at +1 pA | V | target / target | 0 … 1.5 | 1.5 | bias |\n\nArea reference: **210.61 um2**. 3 expanded device instances; sum of device/contact envelopes 121.7863 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **5**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nVGS reference: line and temperature drift 31.5%; load regulation 22.5%; startup and disturbance recovery 18%; reference and extrema 9%; supply cost 9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `line_span_v` | 0.157500000001 |\n| `temperature_span_v` | 0.157500000000 |\n| `load_error_v` | 0.056250000000 |\n| `loaded_reference_v` | 0.056250000000 |\n| `output_resistance_ohm` | 0.056250000000 |\n| `release_error_v` | 0.056250000000 |\n| `injection_error_v` | 0.060000000000 |\n| `return_error_v` | 0.060000000000 |\n| `startup_error_v` | 0.060000000000 |\n| `line_max_v` | 0.012857142857 |\n| `line_min_v` | 0.012857142857 |\n| `maximum_v` | 0.012857142857 |\n| `minimum_v` | 0.012857142857 |\n| `reference_v` | 0.012857142857 |\n| `temperature_max_v` | 0.012857142857 |\n| `temperature_min_v` | 0.012857142857 |\n| `power_w` | 0.045000000000 |\n| `supply_a` | 0.045000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nUse the supplied task, process resources and runtime protocol. Write\n`/workspace/output/final.gds` and submit it through `python -I /protocol/submit.py`.\nThe evaluator independently checks the frozen submitted GDS. Collection\nlicenses, reference layouts, research files and host configuration are not\nsolver inputs.\n","case_path":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml","case_sha256":"a50bb930f1a93a259d15f9c8896d7324d8ffb61787533e72b6868a1ce65f47af","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/problem.md","netlist_path":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/circuit.cdl","netlist_sha256":"4352aeb85c2a7bfb00181738a742d0ccbd5033b422393bafa6a82bd84c1e84b9","license_path":"tasks/ihp-sg13g2/analog-db/LICENSE"}
+{"id":"module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA","in_core":false,"title":"IHP AnalogAcademy full_OTA","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Amplifies differential signals with a two-stage CMOS OTA.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# Two-Stage CMOS OTA Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `two_stage_OTA_layout` two-stage CMOS\noperational transconductance amplifier. Preserve the MOS and MIM devices,\ndimensions, connectivity, well and substrate connections, and six-port\ninterface in the authoritative materials. The submitted GDS must pass the\nphysical checks, fit the functional outline, and meet the nominal DC-bias and\nAC-response limits after candidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `two_stage_OTA_layout` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Nominal bias, feedback fixture, AC sweep, and measurements |\n\nUse one external label on each distinct conductor. Internal nodes must not be\ndeclared as external ports.\n\n| Port | Function | Nominal connection |\n|---|---|---|\n| `v-` | Inverting input | DC feedback from `vout`; AC feedback fixture return |\n| `v+` | Non-inverting input | 0.6 V DC and unit AC excitation |\n| `vss` | Ground and substrate supply | 0 V |\n| `vdd` | Positive supply | 1.2 V |\n| `iout` | Bias-current node | Ideal 80 µA sink to ground |\n| `vout` | Single-ended output | 500 fF load to ground |\n\nThe extraction port order is `v- v+ vss vdd iout vout`.\n\n## Operating Conditions\n\nThe pre-layout and candidate-derived simulations use the supplied deck and the\nsame nominal model and fixture.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `cap_typ`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V`, `VSS = 0 V` |\n| Input DC level | `V+ = 0.6 V` |\n| Bias and load | 80 µA sink at `iout`; 500 fF from `vout` to ground |\n| Feedback fixture | 4 GH inductor from `vout` to `v-`; 4 GF capacitor from `v-` to ground |\n| AC sweep | 100 points/decade from 1 Hz through 10 MHz |\n| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout |\n\nThe feedback fixture closes the DC loop while opening the AC loop for transfer\nmeasurement. Supply power is `-V(vdd) × I(VDD)` at the operating point and\nexcludes external input and bias-source power.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `two_stage_OTA_layout` top cell. The\nfile must be at most 10 MiB (10,485,760 bytes) and must contain the complete\nhierarchy needed by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; every declared port must stay on its own conductor with\nthe declared connectivity and device parameters. Port names are matched\ncase-insensitively.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 80 µm and the maximum height is\n50 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; explicit taps remain in the\nphysical LVS netlist but are not emitted as extracted tap elements. Substrate\nsheet and tap resistance as extracted quantities, body coupling, and noise are\noutside the declared scope. The finite source tap elements are covered by the\nsame-condition source calibration and are not treated as additional post-layout\nrequirements.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vp)-v(vm))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |\n| `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vp)-v(vm)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |\n| `phase_margin` | AC: `180+(find (180*cph((v(vout)/(v(vp)-v(vm))))/pi) when (db((v(vout)/(v(vp)-v(vm)))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n\nArea reference: **2936.48 um2**. 24 expanded device instances; sum of device/contact envelopes 1887.1830 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nSmall-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `low_frequency_gain` | 0.270000000000 |\n| `unity_gain_bandwidth` | 0.225000000000 |\n| `phase_margin` | 0.225000000000 |\n| `output_bias` | 0.045000000000 |\n| `supply_power` | 0.135000000000 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRuntime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside\nthe supplied testbench, with the model paths and settings exposed by the runtime\nresource bundle. For the submitted layout, the evaluator supplies the\ncandidate-derived extracted netlist. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml","case_sha256":"e8c96270684e41df167d5a346b0c0834c0a8a9d1804848c2d75fb571debcb348","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl","netlist_sha256":"b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"}
+{"id":"module_1_bandgap_reference.part_3_layout.OTA_layout.input_pair","in_core":false,"title":"IHP AnalogAcademy input_pair","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Converts a differential input into a balanced response using a matched PMOS pair.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# PMOS Differential Input Pair Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `input_common_centroid` matched PMOS\ndifferential input pair. Preserve the device topology, dimensions, dummy\ndevices, explicit well and substrate connections, and six-port interface in the\nauthoritative materials. The submitted GDS must pass the physical checks, fit\nthe functional outline, and meet the nominal differential-response limits after\ncandidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `input_common_centroid` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Bias, load, AC sweep, and public measurement expressions |\n\nUse one external label on each distinct conductor. Internal nodes must not be\ndeclared as external ports.\n\n| Port | Function | Nominal connection |\n|---|---|---|\n| `v-` | Inverting PMOS gate | Differential input |\n| `v+` | Non-inverting PMOS gate | Differential input |\n| `vdd` | PMOS well and dummy-device supply | 1.2 V supply |\n| `dn3`, `dn4` | Differential drain outputs | 50 kΩ loads to ground |\n| `tail` | Shared source and dummy-drain node | 20 µA source current from `vdd` |\n\nThe extraction port order is `v- v+ vdd dn3 dn4 tail`.\n\n## Operating Conditions\n\nThe pre-layout and candidate-derived simulations use the supplied deck and the\nsame nominal model and parameter values.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V` |\n| Bias | 20 µA current source from `vdd` to `tail` |\n| Input DC level | `v- = v+ = 0.5 V` common mode |\n| Input AC stimulus | Equal and opposite small-signal inputs, −0.5 V and +0.5 V |\n| Drain loads | 50 kΩ from each of `dn3` and `dn4` to ground |\n| AC sweep | 40 points/decade from 1 Hz through 1 GHz |\n| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout |\n\nSupply power is `-V(vdd) × I(VDD)` at the DC operating point. The evaluator\nchecks the 1 MHz and 100 MHz differential gain observations from the sweep.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `input_common_centroid` top cell.\nThe file must be at most 10 MiB (10,485,760 bytes) and must contain the complete\nhierarchy needed by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; every declared port must stay on its own conductor\nwith the declared connectivity and device parameters. Port names are matched\ncase-insensitively.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 45 µm and the maximum height is\n40 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; the explicit tap is checked\nby physical LVS but is not emitted as an extracted tap element. Well/substrate\nsheet resistance, tap resistance as an extracted quantity, body coupling, and\nnoise are outside the declared scope. The finite source tap is used only in source calibration.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `differential_gain` | AC: Value of `(abs(((v(dn3)-v(dn4))/(v(vp)-v(vm))))) at=1meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `differential_gain_high` | AC: Value of `(abs(((v(dn3)-v(dn4))/(v(vp)-v(vm))))) at=100meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `tail_voltage` | DC operating point: `v(tail)`. | V | target / target | −∞ … +∞ | 1.2 | bias |\n| `common_drain` | DC operating point: `(v(dn3)+v(dn4))/2`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `drain_balance` | DC operating point: `v(dn3)-v(dn4)`. | V | target / target | −∞ … +∞ | 1.2 | bias |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **1236.14 um2**. 13 expanded device instances; sum of device/contact envelopes 778.4891 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **3**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 44.7%; balance and linearity 22.4%; operating points 4.47%; power 13.4%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `differential_gain` | 0.223684210526 |\n| `differential_gain_high` | 0.223684210526 |\n| `drain_balance` | 0.223684210526 |\n| `common_drain` | 0.022368421053 |\n| `tail_voltage` | 0.022368421053 |\n| `supply_power` | 0.134210526316 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRuntime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside\nthe supplied testbench. The evaluator generates `parameters.spice` from the\nper-job values in `/protocol/task.json` and supplies the model paths and settings\nthrough the runtime resource bundle. For the submitted layout, the evaluator\nsupplies the candidate-derived extracted netlist. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml","case_sha256":"3599b501cc1fbc77ef71218e592580de85311c0af6f96fa7c8e2b3703b87d253","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl","netlist_sha256":"25456f0316c22ee5586ad3e306f0d513fd35e48f32ee67ce9cb0dc373d306f3d","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"}
+{"id":"module_1_bandgap_reference.part_3_layout.OTA_layout.output_stage","in_core":false,"title":"IHP AnalogAcademy output_stage","pdk":"ihp-sg13g2","category":"Amplifiers & RF","summary":"Provides the loaded output response of a two-stage CMOS OTA.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# CMOS OTA Output Stage Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `output_stage` output stage of a two-stage\nCMOS operational transconductance amplifier. Preserve the device topology,\ndimensions, compensation capacitor, explicit well and substrate connections,\nand five-port interface in the authoritative materials. The submitted GDS must\npass the physical checks, fit the functional outline, and meet the nominal\noutput-response limits after candidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `output_stage` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Bias, load, AC sweep, and public measurement expressions |\n\nUse one external label on each distinct conductor. Internal nodes must not be\ndeclared as external ports.\n\n| Port | Function | Nominal connection |\n|---|---|---|\n| `vdd` | PMOS supply and n-well reference | 1.2 V supply |\n| `iout` | Bias replica/control node | 20 µA current sink to ground |\n| `vout` | Single-ended output | 100 kΩ and 500 fF loads to ground |\n| `vss` | NMOS supply and substrate reference | Ground |\n| `dn4` | NMOS gate and compensation-capacitor node | 0.33 V DC with 1 V AC |\n\nThe extraction port order is `vdd iout vout vss dn4`.\n\nThe circuit contains the PMOS output current source `MM5`, diode-connected bias\nreplica `MM9`, long-channel NMOS pull-down `MM6`, MIM compensation capacitor\n`CC2`, and explicit tap devices `RR4` and `RR5`.\n\n## Operating Conditions\n\nThe pre-layout and candidate-derived simulations use the supplied deck and the\nsame nominal model and parameter values.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `cap_typ`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V`, `VSS = 0 V` |\n| Bias | 20 µA current sink at `iout` |\n| Input stimulus | `dn4 = 0.33 V` DC with 1 V AC small signal |\n| Output load | 100 kΩ resistor and 500 fF capacitor to ground |\n| AC sweep | 40 points/decade from 1 Hz through 1 GHz |\n| Numerical conditioning | `rshunt = 1e12`: 1 TΩ from every analog node to ground, identical pre-layout and post-layout |\n\nSupply power is `-V(vdd) × I(VDD)` at the DC operating point.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `output_stage` top cell. The file\nmust be at most 10 MiB (10,485,760 bytes) and must contain the complete\nhierarchy needed by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; every declared port must stay on its own conductor\nwith the declared connectivity and device parameters. Port names are matched\ncase-insensitively.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 55 µm and the maximum height is\n45 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; explicit taps remain in the\nphysical LVS netlist but are not emitted as extracted tap elements. Substrate\nsheet and tap resistance as extracted quantities, body coupling, and noise are\noutside the declared scope. The finite source taps are used only in source calibration.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `output_gain` | AC: Value of `(abs((-v(vout)/v(dn4)))) at=1meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `output_gain_high` | AC: Value of `(abs((-v(vout)/v(dn4)))) at=100meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |\n| `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |\n| `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **2292.35 um2**. 6 expanded device instances; sum of device/contact envelopes 1466.0063 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **4**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nLocal gain stages: signal transfer 60.7%; operating points 6.07%; power 18.2%; area 15%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.15 |\n| `output_gain` | 0.303571428572 |\n| `output_gain_high` | 0.303571428571 |\n| `output_bias` | 0.060714285714 |\n| `supply_power` | 0.182142857143 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nRuntime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside\nthe supplied testbench. The evaluator generates `parameters.spice` from the\nper-job values in `/protocol/task.json` and supplies the model paths and settings\nthrough the runtime resource bundle. For the submitted layout, the evaluator\nsupplies the candidate-derived extracted netlist. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml","case_sha256":"24e04f3a64bd2477b89dbbef2c7789208eaa798e4e8e7b8efd60d080a80fa6fb","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/circuit.cdl","netlist_sha256":"81620ebba529edccd1beddbcb1349c0e3e7ee58b9e3749d8235433610bd98ad5","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"}
+{"id":"module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator","in_core":false,"title":"IHP AnalogAcademy comparator","pdk":"ihp-sg13g2","category":"Mixed-signal","summary":"Compares two input voltages using a clocked regenerative decision.","source_url":"https://github.com/IHP-GmbH/IHP-AnalogAcademy/tree/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator","status":"qualified","collection":"IHP-AnalogAcademy","task_kind":"netlist_to_gds","problem":"# Dynamic Comparator Layout Task\n\n## Objective\n\nCreate an IHP SG13G2 layout for the `DIFF_COMPARATOR` dynamic differential\ncomparator. Preserve the topology, device parameters, explicit well and\nsubstrate connections, and eight-port interface in the authoritative materials.\nThe submitted GDS must pass the physical checks, fit the functional outline, and\nmeet the clocked decision requirements after candidate-derived RC extraction.\n\n## Inputs and Interface\n\nIn addition to this problem, the solver receives the following declared\nmaterials. The structured constraints\nand evaluation plan are also available at runtime through `/protocol/task.json`.\n\n| Input | Purpose |\n|---|---|\n| [materials/circuit.cdl](materials/circuit.cdl) | Authoritative LVS netlist for `DIFF_COMPARATOR` |\n| [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |\n| [materials/testbench.spice](materials/testbench.spice) | Clock stimulus and public measurement expressions |\n\nUse one distinct external conductor for each ordered port. Internal nodes must\nnot be exposed as ports.\n\n| Port | Function |\n|---|---|\n| `vdd` | Positive supply |\n| `gnd` | Ground and substrate reference |\n| `V+`, `V-` | Differential input pair |\n| `clk` | Dynamic latch clock |\n| `out-`, `out+` | Complementary decision outputs |\n| `vbias` | Bias input |\n\nThe extraction port order is `vdd gnd V+ V- clk out- out+ vbias`.\n\n## Operating Conditions\n\nThe supplied deck evaluates the pre-layout and candidate-derived netlists with\nthe same model and stimulus definitions.\n\n| Parameter | Setting |\n|---|---|\n| Process corner | `mos_tt`, `res_typ` |\n| Temperature | 27 °C |\n| Supply | `VDD = 1.2 V` |\n| Input reference and bias | `V- = vbias = 0.6 V` |\n| Differential input | `V+ − V- = −5, −3, +3, +5 mV`, tested separately |\n| Clock | 100 MHz, 1.2 V swing, 500 ps rise and fall, 5 ns high time |\n| Output load | 50 fF on each output |\n| Transient analysis | 100 ns duration, 10 ps maximum time step |\n| Measurements | Skip the first two cycles and evaluate the next eight cycles |\n\nThe testbench excludes power consumed by the external clock, input, and bias\ndrivers from the reported supply-power measurement.\n\n## Physical Requirements\n\nSubmit a readable GDSII file with a nonempty `DIFF_COMPARATOR` top cell. The file\nmust be at most 10 MiB (10,485,760 bytes) and must contain the complete hierarchy\nneeded by the target cell.\n\nThe evaluator runs the pinned SG13G2 main and additional maximal DRC rules in\ndeep mode, with density and antenna checks disabled and no waivers. LVS uses the\ncurrent `lvs-upstream.json` profile and strict named-port matching against\n`materials/circuit.cdl`; port names are matched case-insensitively, while every\ndeclared port must remain on its own conductor with the declared connectivity.\n\nThe functional outline is the recursive bounding box of polygons on these\nSG13G2 datatype-0 layers, including child cells and the complete routing stack:\n\n`1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.\n\nThe maximum width is 45 µm and the maximum height is\n45 µm, measured along the submitted X and Y axes.\nFunctional area is width multiplied by height. Text, annotation and filler\nlayers are excluded. The area score below uses this same functional footprint.\n\nAfter the physical and geometry gates pass, Magic extracts distributed wire\nresistance and layout capacitance from the submitted GDS. Device merging and\nresistor-network simplification are disabled. The compact-device extraction\nboundary represents MOS bodies at ideal model rails; explicit taps remain part\nof physical LVS but are not emitted as extracted tap elements. Substrate sheet\nand tap resistance as extracted quantities, body coupling, and noise are outside\nthe declared scope. The source and post-layout runs use the same nominal\nstimuli and models; a finite-source-tap versus ideal-body calibration bounds this\nextraction choice.\n\n## Electrical Requirements and Scoring\n\nPhysical checks and declared functional bounds remain mandatory. Quality has no\nfixed allowed-degradation threshold. Each `source_*` job simulates the declared\nsource circuit with exactly the same testbench, model resources, parameters,\nload and measurement window as its paired extracted-candidate job. A source\nobservation is the 100-point electrical baseline; it is independent of the\nsubmitted GDS. All individual pairs are retained in the evaluation report.\n\nFor a post-layout observation x and its source observation b:\n\n- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,\n  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;\n  s is a normalization floor, not an allowed degradation or pass threshold.\n- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.\n- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and\n  zero-valued operating points are never divided directly.\n\nScoring uses `layout`. A metric uses its worst paired quality q. The score is\nS = 100 * product(q_i ** w_i), including area quality\nq_area = area_reference / candidate_functional_area. The weights below sum to\none. Dimensions describe measurements but do not determine their weights.\nPhysical or functional rejection scores zero; missing or invalid measurements\nproduce an unknown score, including measurements with zero weight.\nSource-equivalent performance at the area reference scores 100; improvements\ncan exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.\n\nMeasurement definitions below use the supplied SPICE node/source names.\n`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered\npower therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`\ndenote magnitude, and `cph` is continuous phase in radians. `find`, `when`,\n`from/to`, and `rise/fall` retain the deck's interpolation, window and\ncrossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/\nmilli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`\nmean the stated window average, extrema and sampled derivative. All\ndeclared conditions are measured separately and paired with the same\nsource condition; a group uses its worst paired quality.\n\n| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |\n| --- | --- | --- | --- | --- | --- | --- |\n| `worst_delay` | Clock falling through 0.6 V to polarity-correct output difference reaching 1 V in cycles 2–9 (trigger delays 20–90 ns; target search starts 5.75 ns later). Every cycle and input condition is paired; the worst quality is scored. | s | minimize / ratio | 0 … +∞ | — | response |\n| `decision_margin` | Minimum polarity*(V(OUTP)-V(OUTM)) in each 1 ns decision window, 28.75–29.75 ns through 98.75–99.75 ns; all eight cycles and four signed input conditions must pass. | V | functional check | 1.0 … +∞ | — | functional check |\n| `supply_power` | Mean delivered VDD power, -V(VDD)*I(VDD), over 20–100 ns, independently for each signed input condition. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |\n\nArea reference: **502.96 um2**. 24 expanded device instances; sum of device/contact envelopes 306.3377 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.\n\nThe capability coefficient remains **6**; it is independent of\nthe reference-relative task score.\n\n\n### Score weights\n\nClocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics.\n\n| Metric | Weight |\n| --- | ---: |\n| `functional_area` | 0.1 |\n| `worst_delay` | 0.710526315789 |\n| `supply_power` | 0.189473684211 |\n\n## Tools and Submission\n\nSolve budget: **3 hours**.\n\nThe runtime environment and support resources are declared in\n`/protocol/resources.json` and `/protocol/harness.json`; the working directory is\n`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic\nperforms RC extraction; ngspice runs the supplied deck with the reviewed SG13G2\nmodels. The evaluator provides the tool and PDK resources named by the case\ntoolchain.\n\nFor pre-layout simulation, use `materials/circuit.spice` as `dut.spice`\nbeside the supplied testbench and use the per-job values exposed in\n`/protocol/task.json`. For the submitted layout, the evaluator supplies the\nnetlist produced by candidate-derived RC extraction. If the harness declares\n`process-feedback`, the optional command is\n`python -I /protocol/process_check.py`; the final evaluation remains independent.\n\nWrite the result to `/workspace/output/final.gds`, then run\n`python -I /protocol/submit.py` and wait for the submission receipt. Solver\nnetlists, waveforms, and measurements are not accepted as substitutes for the\nindependent evaluator inputs.\n","case_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml","case_sha256":"d553f9e09dd960a229e184f1feff7247c57d2d7cc8ae117ad712cecabf6aae9b","pdk_path":"tasks/ihp-sg13g2/pdk.toml","pdk_sha256":"0a320f50264256229e68c27884a7dfab185774d53be6ee86aac24f8806e8ddc4","description_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md","netlist_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl","netlist_sha256":"0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c","license_path":"tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE"}