diff --git a/README.md b/README.md index bbd60308b02e43fcf32f2646b1321ba9dab0eea7..a2301f8588bf7a6ad2777faa7c8e884a9bbb71ec 100644 --- a/README.md +++ b/README.md @@ -17,325 +17,208 @@ configs: # ICLayout-Bench Dataset -92 qualified public circuit-layout tasks: nine FreePDK45, 27 GF180MCU, -49 IHP SG13G2 and seven SKY130A, for the -[ICLayout-Bench evaluator](https://github.com/lizhangmai/ICLayout-Bench). -Each task supplies a netlist, layout requirements, test stimuli, scoring contract -and a reference layout. Available on [Hugging Face](https://huggingface.co/datasets/MAI716/ICLayout-Bench). - -## Load and select +ICLayout-Bench provides **92 public circuit-layout tasks**, including a +**21-task core benchmark**, for studying and evaluating automated IC layout. +Given a transistor-level SPICE netlist and English requirements, a participant +produces a GDS layout. The +[ICLayout-Bench evaluator](https://github.com/lizhangmai/ICLayout-Bench) checks +physical correctness and measures post-layout electrical behavior and area under +each task's declared conditions. + +Each task includes requirements, a netlist, test stimuli, an evaluation contract +and a qualified reference layout. Browsing these materials requires no EDA tools; +running physical and electrical checks requires the evaluator and its declared +external tools and process resources. Collection licenses differ, and the +analog-db materials include noncommercial terms; see [licensing](#licensing). + +## Tasks and subsets + +| Process | All tasks | Core tasks | Circuit coverage | Resource declaration | +| --- | ---: | ---: | --- | --- | +| FreePDK45 | 9 | 3 | Logic cells, SRAM and peripheral circuits, differential amplifier | [pdk.toml](tasks/freepdk45/pdk.toml) | +| GF180MCU | 27 | 7 | Amplifiers, comparators, regulators, temperature references, DAC, oscillator and scan logic | [pdk.toml](tasks/gf180mcuD/pdk.toml) | +| IHP SG13G2 | 49 | 7 | Amplifiers, feedback and sampled circuits, regulators, references and SiGe circuits | [pdk.toml](tasks/ihp-sg13g2/pdk.toml) | +| SKY130A | 7 | 4 | Amplifiers, comparator, current mirror, power-on reset, sample-and-hold and DAC | [pdk.toml](tasks/sky130A/pdk.toml) | +| **Total** | **92** | **21** | | | + +The only Hugging Face configuration is `default`; its `test` split contains +**all 92 tasks**. There are no separate training or validation splits. The core +benchmark is a subset selected by `in_core`, not a separate split. Tasks outside +core remain available for broader evaluation or focused exercises. + +The core covers logic, storage, passive networks, sampling, oscillation, +high-frequency behavior and feedback control while reducing repeated circuit +families. It is a selection for capability coverage, not a measured difficulty +ranking. `core_order` gives the evaluator's dispatch order, not difficulty. +The full corpus is weighted toward amplifiers and RF: its presentation categories +contain 52 Amplifiers & RF, 17 Mixed-signal, 14 Power & references and 9 Logic & +memory tasks. Report the selected subset and per-task results when comparing +participants. + +## Browse and download + +To browse the task table with the Hugging Face `datasets` library: ```python from datasets import load_dataset -repo_id = "MAI716/ICLayout-Bench" -tasks = load_dataset(repo_id, split="test") # Complete corpus. -core = tasks.filter(lambda task: task["in_core"]).sort("core_order") # Current 21-task benchmark. +tasks = load_dataset("MAI716/ICLayout-Bench", split="test") +core = tasks.filter(lambda task: task["in_core"]).sort("core_order") print(tasks[0]["problem"]) ``` -`data.parquet` contains every task, sorted by stable ID. The boolean `in_core` -field is generated from the same field in each `case.toml`; -the corpus includes all currently qualified public cases, and changing this -selection never removes tasks from it. See the -[selection rationale](#core-selection-rationale). Participant experiments can choose -`name = "all"` and a `tasks` filter without changing core. -Core cases also declare a unique positive `core_order`. The evaluator inherits -this ascending dispatch order when selecting `core`, starting longer tasks early -and interleaving smaller circuits. Experiment configurations only need to select -`core`; an explicit `tasks` list can override the order. Maintain membership and -order in case metadata and regenerate the index together. - -Rows contain `id`, `in_core`, nullable integer `core_order`, `title`, `category`, `summary`, `pdk`, `collection`, `task_kind`, -`status`, `source_url`, `problem`, and relative paths/digests for task files, -netlists, process declarations and licenses. The typed, Zstd-compressed Parquet table is a generated view; -`case.toml` owns task metadata and requirements. - -For assets, use a local checkout or `huggingface_hub.snapshot_download` with -`repo_type="dataset"`. Pin the table and assets to the same repository commit -using `revision` in both loading calls. A local checkout is also supported. When reloading an edited local checkout directly through -`datasets`, pass `download_mode="reuse_cache_if_exists"` to refresh cached tables. - -## Contents +This loads the table, including the requirements text. It does not download the +netlists, GDS references or other files addressed by the table's paths. -```text -tasks// - pdk.toml # Pinned process resources and profiles - README.md # Process scope and limitations, where documented - / - LICENSE # Collection terms - NOTICE # Required attribution, where applicable - cases// - case.toml # Metadata, input identities and evaluation contract - problem.md # Complete participant-facing requirements - materials/ # Netlist, test stimuli and declared presentation assets - reference/ # Reference layout; excluded from standard solver inputs -data.parquet # Complete corpus with generated in_core membership -``` +To download the complete dataset and read a task's files, use +[`snapshot_download`](https://huggingface.co/docs/huggingface_hub/guides/download#download-an-entire-repository). +The example loads the Parquet table from the same downloaded directory as the +assets, keeping them at one revision: -Source attribution is in `case.toml`; process and collection follow the directory -hierarchy. - -## Licensing - -The root [LICENSE](LICENSE) covers original project metadata and documentation. -Task materials retain the terms in each `tasks///LICENSE` and, -where present, `NOTICE`; the table exposes the corresponding license paths. -Terms vary by collection, including noncommercial restrictions for analog-db -materials. Retain applicable licenses, notices, source attribution and modification -notices when redistributing materials. External PDKs and EDA tools have their own -licenses. Technical qualification does not establish redistribution permission. - -## Scope and validation - -The problem and contract specify each task's operating points, physical checks, -measurement definitions and score. Process scope for [GF180MCU](tasks/gf180mcuD/README.md), -[FreePDK45](tasks/freepdk45/README.md) and [SKY130A](tasks/sky130A/README.md) -describes resource assumptions and limitations. These are block-level benchmarks, not -manufacturing signoff or evidence of model performance. - -Earlier revisions of the selected core and bounded-error tasks passed the former -multi-run qualification protocol. Those reports remain historical; they do not -establish current qualification under the installed evaluator. The current -protocol needs one complete reference evaluation per changed evaluation contract. -Qualification reports and acceptance records stay with the author. References are -available for independent verification and excluded from standard solver inputs. - -Nonnegative error and residual metrics use the explicitly declared -`saturating_ratio` rule: `q = 2(b+s)/(b+x+2s)`, with candidate error `x`, -quality anchor `b`, and positive scale `s`. The anchor is the declared -`quality_target.value`, or the paired source observation when no target is -declared. Equality to the anchor has quality 1 and improvement approaches a -ceiling of 2. Source measurements remain independently frozen and paired; -engineering goals do not rewrite those observations. Selection follows the -measurement definition, including accuracy, recovery, hold error, curvature, -ripple and regulation aliases. Cost and loop-shape metrics keep their declared -rules. The task score remains a weighted product and may exceed 100; the bounded -rule limits individual error rewards rather than imposing a total-score cap. -The 100-point level denotes challenging electrical and footprint goals, not -the quality of the feasibility witness. A valid reference may score well below -100. Repeated or nearly invariant observations remain diagnostic when their -score weights are zero; all functional requirements continue to apply. -The fully differential CMFB amplifier separately scores static common-mode -accuracy and recovery relative to its own DC equilibria. Each problem declares -the scales, windows and weights; no extra PVT conditions are implied. - -Install the evaluator separately to run a reference: - -```bash -python -m benchmarking.engine.preview --dataset . run \ - --case freepdk45.nangate45-pdk.NAND2_X1 --output build/reference-check +```python +from pathlib import Path +from datasets import load_dataset +from huggingface_hub import snapshot_download + +revision = "main" # Use a full dataset commit hash for repeatable experiments. +dataset_root = Path(snapshot_download( + repo_id="MAI716/ICLayout-Bench", + repo_type="dataset", + revision=revision, + local_dir="iclayout-bench-dataset", +)).resolve() +tasks = load_dataset( + "parquet", + data_files={"test": str(dataset_root / "data.parquet")}, + split="test", +) +task = next(task for task in tasks if task["id"] == "freepdk45.nangate45-pdk.NAND2_X1") +print(task["problem"]) +print((dataset_root / task["netlist_path"]).read_text()) +print("Contract:", dataset_root / task["case_path"]) +print("Dataset root:", dataset_root) ``` -The command creates local reports under the requested output directory. Setup, -index generation and publication checks are documented in the evaluator's -[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md) -and [task qualification guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/CONTRIBUTING.md#task-qualification). - -## Core selection rationale - -The core is a secondary selection of the complete corpus, chosen for capability -coverage. Its size is not a limit on the available tasks. Select capabilities -from maintained netlists, testbenches and scoring contracts, rather than circuit -names or upstream performance claims. Prefer a representative within each PDK; -include related circuits when their measured requirements add distinct behavior. -Do not fill coefficient bands or process quotas merely for numerical balance. - -
-Detailed capabilities, alternatives and selection methodology - - -Case-level `in_core` flags and scoring contracts own membership and weights. This document -records the rationale for the secondary core selection from the full Dataset, -independently of engine releases. All accepted tasks remain available in the default `test` table; -being outside core does not mean a task is unfinished or excluded from Dataset. - -### Coefficient rubric - -The integer coefficient from 1 to 10 describes the capability required by the -circuit and its evaluated requirements. It is used when aggregating tasks, -separately from each task's score. - -| Coefficient | Capability scope | -|---:|---| -| 1 | A single local function, such as basic logic transitions or a current ratio at declared bias points | -| 2 | A small block with coupled paths or supply states, such as compound logic or reset release under specified ramps | -| 3 | Local analog or controlled driver behavior: bias, transfer or output states | -| 4 | A complete compact circuit coupling gain, accuracy, load or a physical passive network | -| 5 | Local feedback, clocked state or charge transfer with parasitic-dependent dynamics | -| 6 | Regenerative decisions, storage integrity, coupled startup behavior or a complete compensated loop | -| 7 | Multistage compensation or regulation maintaining frequency response and recovery across loads | -| 8 | Active auxiliary compensation, self-oscillation or broader return-ratio and startup requirements | -| 9 | Strongly interacting control goals or complex regulation combining startup, frequency response and recovery | -| 10 | Clock modulation, signal feedback and actual common-mode control operating together | - -The coefficient is declared before participant evaluation and explained in the -case documentation. It reflects measured requirements rather than the circuit -name, transistor count, simulator runtime or observed participant success rate. -A coefficient of 10 does not imply ten times the implementation effort of a -coefficient of 1. Changes to coefficients or benchmark membership produce a new -content identity through configuration and task-contract digests; no manual -version field is required. Archived results retain their original weights. See -[result aggregation](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/running.md#result-storage-and-presentation). - -### Selected capabilities - -The current set contains 21 cases across four PDKs: three FreePDK45, seven -GF180MCU, seven IHP SG13G2 and four SKY130A. Each link gives the full -requirements and coefficient rationale. Coefficients below are the existing -case coefficients, not new selection weights or estimates of solve time. - -| PDK | Selected case | Coefficient | Distinct contribution | -| --- | --- | ---: | --- | -| FreePDK45 | [NAND2](tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md) | 1 | Basic connectivity, loaded logic levels and timing; an entry-level anchor. | -| FreePDK45 | [SRAM write driver](tasks/freepdk45/OpenRAM/cases/write_driver/problem.md) | 3 | Complementary loaded outputs and enabled/disabled drive states. | -| FreePDK45 | [6T SRAM cell](tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md) | 6 | Storage integrity coupled to read and write access. | -| GF180MCU | [Five-transistor OTA](tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md) | 4 | Compact differential gain and bias with separately measured common-mode rejection. | -| GF180MCU | [Scan DFF](tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md) | 5 | Clocked state and scan/data selection, exercised around setup and hold with output timing and slew. | -| GF180MCU | [R-2R DAC](tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md) | 4 | A physical resistor ladder: full 256-code DC transfer with integral and differential nonlinearity, plus selected transient codes. | -| GF180MCU | [StrongARM comparator](tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md) | 6 | Regenerative decisions across four input common modes, both input polarities and two clock-edge rates, with precharge, delay and slew measurements. | -| GF180MCU | [Classic PTAT](tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md) | 6 | Temperature slope and curvature, startup time, isolated body connections and a coupled startup branch. | -| GF180MCU | [Feedforward PMOS LDO](tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md) | 7 | A larger pass-device array, feedback divider and feedforward compensation with regulation and recovery checks. | -| GF180MCU | [Four-phase VCO](tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md) | 8 | Self-oscillation, tuning and relative output phases across control settings, three temperatures and three output loads. | -| IHP SG13G2 | [NMOS track-and-hold](tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md) | 5 | Physical charge storage, pedestal, drift, feedthrough and reacquisition across input/temperature conditions. | -| IHP SG13G2 | [SiGe PAM4 driver](tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md) | 4 | Weighted HBT current steering with gain and port-reflection observations extending to 50 GHz. | -| IHP SG13G2 | [Output-controlled auxiliary-compensation OTA](tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md) | 8 | Three-stage routing and auxiliary compensation, with sampled return-ratio and recovery observations across loads and biases. | -| IHP SG13G2 | [Ramos PFC amplifier](tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md) | 7 | A large expanded device array and cross-stage compensation create the suite's upper layout-scale case. | -| IHP SG13G2 | [Fully differential two-stage OTA](tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md) | 9 | Coupled differential and common-mode control with compensation, transient response and a hot-temperature stability check. | -| IHP SG13G2 | [Mirror-OTA LDO](tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md) | 9 | Complex regulation combining return-ratio crossings, startup, line/load response, recovery and closed-loop PSRR. | -| IHP SG13G2 | [Chopper IA with CMFB](tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md) | 10 | Clock modulation, signal feedback and common-mode feedback, with common-mode-to-differential sensitivity under two loads. | -| SKY130A | [Current mirror](tasks/sky130A/OpenFASOC/cases/current_mirror/problem.md) | 1 | Current-ratio accuracy across three bias currents and an output-voltage sweep. | -| SKY130A | [Power-on reset](tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/problem.md) | 2 | Dual-supply startup and reset release under three ramp durations. | -| SKY130A | [Buffered sample and hold](tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/problem.md) | 4 | Tracking, held-value error under input reversal, droop and reacquisition. | -| SKY130A | [Eight-bit buffered resistor DAC](tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/problem.md) | 4 | Full 256-code transfer, monotonicity, INL/DNL, power and full-scale transition checks. | - -The selection retains distinct compact logic, storage, passive-network, sampled, -RF, oscillator and coupled-feedback problems. It reduces repeated compensated -amplifier and regulator cases without removing them from the complete corpus: - -- `amp_015_sau_cfcc` remains an alternative to `amp_006_leung_dfcfc1`; their - current contracts substantially overlap in load/bias sweeps, return-ratio - observations and step recovery. The core retains the latter's auxiliary loop. -- `amp_016_song_dacfc` remains available for its particular transient regime. - Its frozen source has about 44 mV late error and 152 mV ripple in the declared - windows. Those observations make it a less clear representative of settled - amplifier accuracy than the retained cases; they are not evidence that the - task is physically invalid. -- `ldo_001_analoggym_basic` remains a regulator alternative. The core retains the - GF180 pass-array/feedforward problem and the IHP mirror-OTA regulator with - explicit closed-loop PSRR, avoiding a third broadly overlapping LDO. - -`amp_014_ramos_pfc` stays for its large expanded physical array, while -`amp_023_fer_fd2s` and the chopper IA stay for distinct common-mode and switched -feedback behavior. The bare NMOS sampler and buffered SKY130 sample-and-hold -also remain separate: passive storage/feedthrough and active-buffer recovery -pose different layout tradeoffs. These choices describe capability coverage, -not an empirical ordering of difficulty. - -The RF driver remains coefficient 4 because its contract covers a compact -feedforward circuit; its specialized devices and extraction flow do not make -the coefficient an estimate of participant effort. Coefficients are capability -categories, not a measured difficulty scale. - -### Boundaries and alternatives - -The five-transistor OTA, fully differential OTA and compensated amplifiers -progress from compact gain/bias to interacting signal, common-mode and auxiliary -paths. The feedforward PMOS LDO and IHP mirror-OTA regulator add distinct -pass-array, recovery, loop and supply-rejection demands. The IHP-heavy demanding end follows -the available qualified contracts rather than a per-PDK quota; report results by -task and PDK so one toolchain does not obscure the rest of the suite. - -NAND2 supplies the basic logic anchor; the other simple logic cells remain in the -corpus. The separate SRAM sense amplifier overlaps the regenerative-decision -capability represented by StrongARM, whose contract includes precharge, slew, -four common modes and two clock-edge rates. The standalone chopper switch -overlaps clock modulation in the complete chopper IA. The small NMOS -track-and-hold remains because its charge retention and reacquisition checks are -distinct from the complete SKY130 buffered sample-and-hold. - -The GF180 R-2R DAC evaluates a physical resistor ladder over all 256 static -codes plus selected transient codes. The SKY130 DAC adds a complete buffered -interface and all-code monotonicity, INL and DNL gates. The MIM capacitor bank -remains in the corpus; its candidate RC extraction behavior needs clarification -before it returns to core. The basic GF180 PMOS LDO also remains available; the -selected feedforward version adds layout and compensation demands. Smaller gain -stages, bias/reference cells, variable resistors and standalone CMFB blocks -remain useful focused exercises outside core. - -The SiGe driver supplies explicitly measured high-frequency behavior. In -particular, the case named `DC_to_130_GHz_TIA.design_1` currently measures AC -behavior only through 100 MHz, so its name is not evidence of 130 GHz benchmark -coverage. The selected driver uses KLayout-PEX capacitance extraction; it does -not establish distributed interconnect resistance/inductance, eye quality or -complete RF signoff. Likewise, the VCO contract does not measure phase noise or -jitter. These limits apply when describing benchmark coverage. - -### Evidence and revision - -This selection is a structural coverage judgment grounded in published case -contracts and validation associations. It does not yet establish empirical -participant discrimination. Validate that separately with complete runs from -multiple participants and repeated trials: compare per-case success rates, -score spread, completion cost and correlations between related cases. Separate -tool errors from physical/electrical failures; do not treat unknown scores as -zero. A universally easy or hard case can still serve as an anchor, but it -should not dominate the suite through redundant companions. - -Revisit membership when evidence shows redundant outcomes or a missing -capability. Configuration and task-contract digests identify changes automatically; retain -archived definitions and avoid tuning case coefficients to obtain a preferred -ranking. - -
- -## Receiving authored tasks - -Task requirements, scoring, testbenches and reference assets are maintained in -Designs and exported as static files. This Dataset remains independently readable; -using it does not require the authoring package or a Designs checkout. - -After reviewing material rights and obtaining the affected author qualification, -stage one explicitly selected public case in a fresh directory. Set `case_id` to -its stable ID and `evidence` to the author-owned directory containing its -`qualification.json`; keep that evidence outside this Dataset. +A full dataset commit hash can also be passed as `revision` to +[`load_dataset`](https://huggingface.co/docs/datasets/loading#hugging-face-hub). +For comparisons, record that revision together with the evaluator version, +selected task IDs and evaluation environment. -```bash -case_id=freepdk45.nangate45-pdk.NAND2_X1 -bench_python=/path/to/installed-bench/bin/python -staging=/path/to/new-staging -dataset=/path/to/Dataset -evidence=/path/to/author-case/verification - -iclayout-designs export --case "$case_id" --root /path/to/Designs \ - --output "$staging" --bench-python "$bench_python" -"$bench_python" -I -m benchmarking.engine.qualification verify \ - --dataset "$staging" --case "$case_id" --output "$evidence" +## Files and table fields + +```text +README.md +LICENSE +data.parquet # One row per task +tasks// + pdk.toml # Pinned external resources and evaluation profiles + / + LICENSE # Collection and component terms + NOTICE # Attribution, where present + cases// + case.toml # Task metadata, inputs and evaluation contract + problem.md # Participant-facing requirements + materials/ # Netlist and test stimuli + reference/ # Reference layout ``` -Only after the staged reference and declared inputs pass verification, update -that selected case and verify the final recipient against the same evidence: +All table paths are relative to the **dataset root**. Paths inside `case.toml` +are resolved relative to the case directory as specified by the evaluator. +The table is a convenient view; the complete requirements and evaluation +contract are in `problem.md` and `case.toml`. + +| Field | Meaning | +| --- | --- | +| `id` | Stable task identifier used for selection and evaluation. | +| `title` | Human-readable task title. | +| `pdk`, `collection` | Process and source collection in the directory hierarchy. | +| `category`, `summary` | Presentation category and brief circuit description. | +| `in_core` | Boolean membership in the core benchmark. | +| `core_order` | Positive integer dispatch order for core tasks; null outside core. | +| `task_kind`, `status` | Task type and qualification status; current tasks are qualified layout tasks. | +| `source_url` | Original circuit or design source for attribution. | +| `problem` | Full English requirements text, also available through `description_path`. | +| `case_path`, `case_sha256` | Contract file path and SHA-256 of its bytes. | +| `pdk_path`, `pdk_sha256` | Process resource declaration path and SHA-256 of its bytes. | +| `description_path` | Path to the requirements file. | +| `netlist_path`, `netlist_sha256` | Input SPICE netlist path and SHA-256 of its bytes. | +| `license_path` | Path to the collection license; also read any accompanying `NOTICE`. | + +Reference layouts are available for inspection. +The standard benchmark runner provides only declared solver inputs and approved +process resources to a participant; reference layouts are excluded. Use that +runner when measuring participant performance to preserve the input boundary. + +## Evaluate a layout or check a reference + +Install and configure the evaluator using its +[setup and tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). +The dataset declares external PDK resources and evaluation profiles; it does +not bundle the installed PDKs or EDA executables. + +After preparing the required tools and resources, a reference check can use the +directory downloaded above. Run this from the directory containing +`iclayout-bench-dataset`, and choose a fresh output directory: ```bash -iclayout-designs export --case "$case_id" --root /path/to/Designs \ - --output "$dataset" --update --bench-python "$bench_python" -"$bench_python" -I -m benchmarking.engine.qualification verify \ - --dataset "$dataset" --case "$case_id" --output "$evidence" +python -m benchmarking.engine.preview --dataset ./iclayout-bench-dataset run \ + --case freepdk45.nangate45-pdk.NAND2_X1 --output ./reference-check ``` -Mark the accepted case `qualified` in its `case.toml`, then regenerate and check -the complete index: +This evaluates the supplied reference and writes local reports. It does not run +a participant. For submitting candidate layouts or configuring participant +experiments, see the +[evaluation guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/running.md) +and [participant examples](https://github.com/lizhangmai/ICLayout-Bench/tree/main/examples). + +Evaluation checks the submitted artifact, design rules (DRC), netlist equivalence +(LVS), declared geometry constraints and post-layout electrical requirements. +Scores range from **0 to 100** and combine declared electrical quality with +functional layout area. A valid reference demonstrates feasibility; it need not +score 100. Tool failures or unavailable measurements can leave a score unknown; +completed physical or functional rejections score zero. Exact checks, targets, +weights and operating conditions belong to each task contract. See the evaluator's +[scoring definition](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tasks.md#validity-and-quality). + +## Validation scope and limitations + +The supplied references have passed their declared qualification plans. This +establishes feasibility under the evaluated conditions. It does not measure +participant performance or establish manufacturing signoff. Supplies, loads, +temperatures, stimuli and observation windows vary by task; only the stated +conditions are covered. + +- **FreePDK45** uses predictive device models and estimated Magic RC extraction. + Its community physical-check deck has known coverage limits, including an + unimplemented different-potential well-spacing check. +- **GF180MCU** uses the declared variant-D block-level checks and extraction. + Chip-level density and seal-ring closure are outside this benchmark's scope. +- **IHP SG13G2** includes CMOS and SiGe tasks with case-specific extraction + profiles. The core SiGe driver uses capacitance extraction; its high-frequency + checks do not establish distributed resistance, inductance or complete RF signoff. +- **SKY130A** uses the declared TT, 27 °C fixtures and distributed RC extraction; + these tasks do not establish process-corner yield, mismatch or reliability. + +Circuit names are source identifiers, not frequency or performance guarantees. +For example, the case named `DC_to_130_GHz_TIA.design_1` evaluates AC behavior +only through 100 MHz. The VCO task evaluates the stated tuning and phase behavior, +without a phase-noise or jitter claim. Read each problem before interpreting a +result as evidence of circuit coverage. -```bash -iclayout-designs index --dataset "$dataset" -iclayout-designs index --dataset "$dataset" --check -``` +## Licensing -For several authorized cases, use repeated `--case` selections and verify each -case at both boundaries. The exporter -preserves recipient selection and presentation, including unselected tasks. Changed -inputs become candidates; complete affected qualification and verify the retained -external reports before accepting them. Export and local acceptance are separate -from publication. Task-semantic fixes return to the authoring source so subsequent -exports remain reproducible. Selection, corpus documentation and publication policy -continue to be maintained here. +The root [LICENSE](LICENSE) is MIT and covers original project metadata and +documentation. It does **not** replace the terms for task materials. Each row's +`license_path` points to the applicable collection terms. + +| Task materials | Tasks | Included terms | +| --- | ---: | --- | +| analog-db derivatives in [GF180MCU](tasks/gf180mcuD/analog-db/LICENSE) and [IHP SG13G2](tasks/ihp-sg13g2/analog-db/LICENSE) | 62 | PolyForm Noncommercial 1.0.0, with additional retained component terms where applicable. | +| [OpenRAM](tasks/freepdk45/OpenRAM/LICENSE) | 3 | GPL-3.0. | +| [CircuitOpt](tasks/freepdk45/CircuitOpt/LICENSE), [Jianxun-OTA](tasks/gf180mcuD/Jianxun-OTA/LICENSE) and [scan DFF](tasks/gf180mcuD/voidwalkers-scandff/LICENSE) | 3 | MIT. | +| Other collections | 24 | Apache-2.0; see each collection's `LICENSE` and `NOTICE`. | + +The dataset therefore uses component-specific license metadata on Hugging Face. +Read the included terms for your selected tasks and retain applicable licenses, +notices, attribution and modification notices when redistributing materials. +External PDKs and EDA tools have separate licenses. diff --git a/data.parquet b/data.parquet index f47196c83ebfae44890fa3ca1a10a38d0dad32f0..e2edef4e2c797a98207b65b6c024a1d42823b9af 100644 --- a/data.parquet +++ b/data.parquet @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8dd140d6c86e020af2696495b21793026fe0ce595335cfb6697365923a6d6a4d -size 168633 +oid sha256:95f50d45914c71bd207d49c5508104f0f74f4356a72228da925677207a211e10 +size 169850 diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml b/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml index b0c210d4640c16ab414ed26d438159ac232a9516..1b2ea0fe9a539263cc03db6b1c77b49015482591 100644 --- a/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml +++ b/tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 10 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "6335fd502eecee2e7657d6d74c543b98cf8191180bbb55a351191ed397631ee2" - [[assets]] path = "reference/cell_6t.gds" role = "reference" diff --git a/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/schematic.svg b/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/schematic.svg deleted file mode 100644 index 4467bd2ac1f418207f160d469525003bc0a41321..0000000000000000000000000000000000000000 --- a/tasks/freepdk45/OpenRAM/cases/cell_6t/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -cell_6t{"format":"iclayout-schematic","case_id":"freepdk45.OpenRAM.cell_6t","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/freepdk45/OpenRAM/","sheets":["cell_6t"],"banks":[],"source_netlist":"tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cell_6t"],"scope":"main-sheet","editable_project":"tasks/freepdk45/OpenRAM/cases/cell_6t/design/cell_6t.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.cell_6tnet10net4net10net4blbrwlvddgndcell_6t6T SRAM latch · W/L in µmMM50.09/0.05MM40.09/0.05MM10.205/0.05MM00.205/0.05MM30.135/0.05MM20.135/0.05 - diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml b/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml index 5354dccda8d61c1793f8b60a3a617f55090450ae..9dab0d83391f433fddd831d25bc40f171ce5cbac 100644 --- a/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml +++ b/tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml @@ -4,13 +4,6 @@ title = "Clocked SRAM Sense Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "e02a8bf40f0dc6c9e1dd9d90053c0d12edbdfef24f99ac34a997de03c2051dc7" - [[assets]] path = "reference/sense_amp.gds" role = "reference" diff --git a/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/schematic.svg b/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/schematic.svg deleted file mode 100644 index f8aa94b469da063b1a2cbff7ee683b0faae248f3..0000000000000000000000000000000000000000 --- a/tasks/freepdk45/OpenRAM/cases/sense_amp/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -sense_amp{"format":"iclayout-schematic","case_id":"freepdk45.OpenRAM.sense_amp","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/freepdk45/OpenRAM/","sheets":["sense_amp"],"banks":[],"source_netlist":"tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["sense_amp"],"scope":"main-sheet","editable_project":"tasks/freepdk45/OpenRAM/cases/sense_amp/design/sense_amp.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.sense_ampdoutnet_1sclknet_2net_1blbrdoutsclkvddgndsense_ampRegenerative sense latch · W/L in µmM_10.54/0.05M_30.54/0.05M_20.27/0.05M_80.27/0.05M_70.27/0.05M_50.72/0.05M_60.72/0.05 - diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml b/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml index 4f6f59ab3ef0696eb0e228dc45d48459efa1e3f9..4b667de823f52c527abe041f332624f1a3f773da 100644 --- a/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml +++ b/tasks/freepdk45/OpenRAM/cases/write_driver/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 12 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "cce2fe9d51a33854eea6b518c9ffcc666dec5a6f8610fed04468112a9f09d9d2" - [[assets]] path = "reference/write_driver.gds" role = "reference" diff --git a/tasks/freepdk45/OpenRAM/cases/write_driver/materials/schematic.svg b/tasks/freepdk45/OpenRAM/cases/write_driver/materials/schematic.svg deleted file mode 100644 index 5609f140deab97bb2bd6a60316dbfad1c6331e04..0000000000000000000000000000000000000000 --- a/tasks/freepdk45/OpenRAM/cases/write_driver/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -write_driver{"format":"iclayout-schematic","case_id":"freepdk45.OpenRAM.write_driver","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/freepdk45/OpenRAM/","sheets":["write_driver"],"banks":[],"source_netlist":"tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["write_driver"],"scope":"main-sheet","editable_project":"tasks/freepdk45/OpenRAM/cases/write_driver/design/write_driver.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.write_driverbl_barvdddinwen_barwengndbl_barwen_barwendinblbrwenvddgndwrite_driverDifferential SRAM write path · W/L in µmminP0.36/0.05moutP0.36/0.05minN0.18/0.05moutN0.18/0.05mout0P0.36/0.05mout1P0.36/0.05mout0P20.36/0.05mout1P20.36/0.05mout0N0.18/0.05mout1N0.18/0.05mout0N20.18/0.05mout1N20.18/0.05 - diff --git a/tasks/freepdk45/README.md b/tasks/freepdk45/README.md deleted file mode 100644 index 932896f300a1969a57783f584de0b5a7c8a7e784..0000000000000000000000000000000000000000 --- a/tasks/freepdk45/README.md +++ /dev/null @@ -1,58 +0,0 @@ -# FreePDK45 Process Scope - -Process manifests pin resources; each case contract defines its operating conditions. -For installation, caching and reference execution, use the evaluator -[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). - -The selected FreePDK45 tasks cover NAND logic, SRAM storage and write drive. -References use the nominal predictive BSIM4 models and candidate-derived Magic -RC under the conditions declared by each case. The -[process manifest](pdk.toml) owns pinned resources and profiles. - -Each problem is self-contained. Its configuration owns the exact devices, loads, -stimuli, observation times, bounds, dimensions and area anchors. Source simulation defines the electrical scoring baseline. Standard-cell area -uses the reference layout; other areas use the frozen compact estimate. Witnesses -are excluded from standard solver inputs. - -## Physical and extraction scope - -The KLayout profile enables all implemented DRC, manufacturing-grid and antenna -checks without waivers. The community deck's POLY.3 spacing is 50 nm, as documented -upstream for Nangate compatibility. The source deck explicitly lacks its different-potential -well-spacing check, so a pass is not complete manufacturing signoff. Strict LVS -flattens an isolated candidate copy with its labels, removes library-specific -`cheat` blocks and implicit/global rail joins, and compares models, W/L, named -ports and real well/tap connectivity. The upstream audit profile is separate and -retains the original library assumptions; it is not the task judge. - -The functional footprint includes drawing layers 1/0 through 29/0, including all -ten routing metals and nine vias. The same layer set supplies the hard 100 by -100 um envelope and scored bounding-box area. Annotation and pin-purpose shapes -are excluded; the contract requires functional routing on drawing layers. - -Magic imports the candidate on its exact DBU grid, filters electrical text to -poly/metal drawing layers and aliases case-insensitive SPICE port names. It -extracts resistances and capacitances from the GDS, with no schematic replacement. -Independent LVS selects the applicable VTG or VTL model class first. The native -RC topology is checked during qualification against the source after removing -capacitors and collapsing parasitic resistors. Simulation always uses the full, -unchanged extracted RC network. - -The predictive extraction uses the community Magic technology's estimated -resistance/capacitance coefficients and its native placement of coupling and -ground capacitance, with nominal VTG/VTL ngspice models at 27 C. Wells and substrate -are lumped connections. This is not calibrated field-solver extraction or a -foundry signoff claim; process variation, substrate noise and RF/EM are outside scope. - -Use `/resources/support/magic-vtg/freepdk45.tech` or the `magic-vtl` counterpart -for evaluation-equivalent extraction, as specified by the case problem. The unified -PDK directory retains the upstream views; reviewed profiles include the adaptations. - -The explicit manifest adaptations map MOS extraction to the LVS-selected model -class, import threshold/annotation markers as non-electrical comments, and correct -`lambda` from 0.025 to **2.5**. Magic expresses this length in centimicrons, so 2.5 -represents the technology's 25 nm internal grid; the upstream value otherwise -extracts a 50 nm gate as 0.5 nm. Upstream coefficients are retained. Qualification -checks the selected published layouts through the complete extraction and simulation -path. This does not establish stream-out equivalence between Magic and KLayout; -the community repository documents known via/metal stream-out differences. diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml index 0d5630013d62f9be73467a91a0e1b1715d51690d..90c00913e04ae1922c4c2af9bfabeb8f61773e49 100644 --- a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml +++ b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml @@ -11,13 +11,6 @@ visibility = "maintainer" format = "gds" sha256 = "1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "e9e418eff15b2d7ef5a99215c0288a8b104f0d1a21c2956586a21b1d675c4e62" - [task] hours = 3 kind = "netlist_to_gds" diff --git a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/schematic.svg b/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/schematic.svg deleted file mode 100644 index 934d66b8a40693b1b37da41c88c7490cc052074d..0000000000000000000000000000000000000000 --- a/tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -AOI21_X1{"format":"iclayout-schematic","case_id":"freepdk45.nangate45-pdk.AOI21_X1","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/freepdk45/nangate45-pdk/","sheets":["AOI21_X1"],"banks":[],"source_netlist":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice","known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["AOI21_X1"],"scope":"main-sheet","editable_project":"tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/design/AOI21_X1.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.AOI21_X1VSSB2VDDZNB1AM_i_0M_i_1M_i_2M_i_3M_i_4M_i_5AOI21_X1 / AND-OR-InvertZN = NOT (A OR (B1 AND B2))0.415/0.050.415/0.050.415/0.050.63/0.050.63/0.050.63/0.05 - diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml index 682d9d2beb2c7dd557b7590aa784ab2803f0f4f4..974c6651cc2bd527a3f3d8f540cd0b8ba53bbf0a 100644 --- a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml +++ b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml @@ -12,13 +12,6 @@ visibility = "maintainer" format = "gds" sha256 = "d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "f7f06cd9039e53754770235f69f15f0a0a01f202047caaf92cf9e82c13048f5c" - [task] hours = 1 kind = "netlist_to_gds" diff --git a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/schematic.svg b/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/schematic.svg deleted file mode 100644 index a4c6987c61b8c19dabc40ecb78db9c044574a69b..0000000000000000000000000000000000000000 --- a/tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -NAND2_X1{"format":"iclayout-schematic","case_id":"freepdk45.nangate45-pdk.NAND2_X1","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/freepdk45/nangate45-pdk/","sheets":["NAND2_X1"],"banks":[],"source_netlist":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice","known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["NAND2_X1"],"scope":"main-sheet","editable_project":"tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/design/NAND2_X1.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.NAND2_X1A2VDDA1ZNVSSM_i_0M_i_1M_i_2M_i_3NAND2_X1 / Two-input NANDZN = NOT (A1 AND A2)0.415/0.050.415/0.050.63/0.050.63/0.05 - diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml index 7a2a2ac87c5d662b19fe10b7e2976ee392a37740..ba2b63985a10e3e94c73bd46fad897796d5e3ca0 100644 --- a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml +++ b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml @@ -4,13 +4,6 @@ title = "Dummy-Compensated Track Switch" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "a9a5333989af2baaba17d6660a93510536810860dd53ac43161118419da2e692" - [[assets]] path = "reference/adc_tgate_dum.gds" role = "reference" diff --git a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/schematic.svg b/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/schematic.svg deleted file mode 100644 index 0749531c304ded88e16f9913906d6bdbde8df5a1..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -track_switch{"format":"iclayout-schematic","case_id":"gf180mcuD.2AMLogic-sar-adc.track_switch","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/2AMLogic-sar-adc/","sheets":["adc_tgate_dum"],"banks":[],"source_netlist":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["adc_tgate_dum"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/design/track_switch.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.adc_tgate_dumclkclkbvoutvinvoutclkclkbvddvsstrack_switchgf180mcuD · 2AMLogic-sar-adc | W/L in µm · display rounded to 3 significant figuresXP80/0.28XN40/0.28Bulk ties: PMOS → VDD · NMOS → VSSXDP35/0.28XDN17.5/0.28 - diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml index 582be86af19850ceccb4a7270158b4f79baae447..846fb031f9fdfbf18f9f4c787fee70e89888a293 100644 --- a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml +++ b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml @@ -4,13 +4,6 @@ title = "Dynamic Comparator" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "ffeab4b81b6f04616837c935feca4f5d8e6b1313cd1648c6b80e3e9740aded33" - [[assets]] path = "reference/comp_20240331.gds" role = "reference" diff --git a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/schematic.svg b/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/schematic.svg deleted file mode 100644 index 39ac7e644af9db2c060c98abee5e176a05684af5..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -comparator{"format":"iclayout-schematic","case_id":"gf180mcuD.Chipathon2023_ADC.comparator","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/Chipathon2023_ADC/","sheets":["comp_20240331"],"banks":[],"source_netlist":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["comp_20240331"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/design/comparator.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.comp_20240331net1net2net4VDDnet5VSSVOUTPVOUTNnet4net5net1net2VSSnet1net2net3VDDCLKVOUTPVOUTNVINPVINNVSScomparatorgf180mcuD · Chipathon2023_ADC | W/L in µm · display rounded to 3 significant figuresXM42.8/0.28XM52.8/0.28XM22.8/0.28XM32.8/0.28XM12.8/0.28Bulk ties: PMOS → VDD · NMOS → VSSXM62.8/0.28XM112.8/0.28XM72.8/0.28XM122.8/0.28XM102.8/0.28XM152.8/0.28XM82.8/0.28XM132.8/0.28XM92.8/0.28XM142.8/0.28 - diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml index ef5acf742ac7c0f11c158daed7adaaecd728d770..498367d98cf8da9d1f52ac088ea0936ed43d8944 100644 --- a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml +++ b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 8 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "a2f3f2d3d55c5224b39a37e59688fc586d284cb8c96cdc4ef8735b9016a752fc" - [[assets]] path = "reference/ota_5t.gds" role = "reference" diff --git a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/schematic.svg b/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/schematic.svg deleted file mode 100644 index cf59c5fe3a5ccc32b12d4a3da65335fda3ee689f..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ota_5t{"format":"iclayout-schematic","case_id":"gf180mcuD.Jianxun-OTA.ota_5t","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/Jianxun-OTA/","sheets":["ota_5t"],"banks":[],"source_netlist":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ota_5t"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/design/ota_5t.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.ota_5tin_pin_ni_biasvssvddoutnet2net1ota_5tgf180mcuD · Jianxun-OTA | W/L in µm · display rounded to 3 significant figuresM66/0.28 ×3 NF=2M56/0.28 ×3 NF=2M36/0.28 NF=2M46/0.28 NF=2M16/0.28 ×2 NF=2M26/0.28 NF=2M76/0.28 ×3 NF=2M86/0.28 ×2 NF=2 - diff --git a/tasks/gf180mcuD/README.md b/tasks/gf180mcuD/README.md deleted file mode 100644 index c5add3eb4803c0c3d7e7e81c20591d5e33db3c8c..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/README.md +++ /dev/null @@ -1,47 +0,0 @@ -# GF180MCU Process Scope - -Process manifests pin resources; each case contract defines its operating conditions. -For installation, caching and reference execution, use the evaluator -[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). - -The GF180 cases use the explicit operating conditions and frozen scoring anchors -in their task contracts. Core membership is defined by the `in_core` field in each case contract, reflected in the generated root [data.parquet](../../data.parquet), and -[selection rationale](../../README.md#core-selection-rationale) describes the represented circuit capabilities. - -The PDK manifest ([pdk.toml](pdk.toml)) binds `models`, `physical` and -`magic` profiles to one open-pdks installation. `models` uses nominal primitive -ngspice files; `physical` uses the qualified official KLayout rules for variant D, -including geometric/connectivity/off-grid DRC and antenna checks; `magic` uses the -upstream technology built for five metals, 1.1 um top metal and 1 kOhm/square poly. -The prebuilt release and library selection are explicit in the manifest. -The rule files and extraction coefficients come from that release; only the -SPICE reader adapter below modifies an upstream file. DRC runs all rule groups -except chip-level density, including dummy fill and 0.001 um database-unit checks. -The upstream isolated-worker mode keeps antenna connectivity changes separate -from the geometry/connectivity rule groups. -The KLayout reader adapter recognizes the official `nfet_03v3`, -`pfet_03v3` and `ppolyf_u_1k` X wrappers using their actual SI dimensions and MOS -total width. Named top-level pin correspondence is required independently of -KLayout's topology match. - -The Magic profile uses nominal `ngspice()` extraction and a 10-way subdivision -of its 0.05 um internal grid before GDS import. This preserves 5 nm geometry and -port locations during resistance extraction. Candidate-derived MOS/passive -parameters, coupled capacitance and distributed interconnect resistance feed the -same published testbench used for source calibration. Physically distinct -source/body nodes must remain distinct; the model boundary does not include a -distributed silicon substrate network. The standalone-block scope excludes -chip-level density and seal-ring closure, statistical yield and RF/EM analysis. -The isolated-body PTAT uses a physical `nfet_03v3_dn` primitive for native LVS, -with its corresponding four-terminal `nfet_03v3` simulator call. Its independent -witness retains an output-tied isolated P-well, supply-tied deep N-well and an -explicit N-well annulus. The annulus keeps Magic's extresist substrate filling -from joining that body to the outer substrate return. This is a validated -layout route with the existing decks, not a change to PDK extraction rules. -The case additionally qualifies zero-state startup at its declared 100 fF load, -temperatures and supply ramps; larger loads are not covered. - -StrongARM uses its declared 3.3 V CMOS binding and dynamic timing/decision -measurements. Other model families, such as GF180 BJTs, are outside these -published contracts. Use a compatible tool image as specified by the -[evaluator tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md). diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml index 5203a75043ecdd2de0f80b1da99c832f5ea7a483..2aa09dabbc2022f211f777c2701b84b15a612b82 100644 --- a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml @@ -4,13 +4,6 @@ title = "Externally Biased PMOS-Input Folded-Cascode OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "48c6706e3cae42f7b8557b9af4784ba8f43e4c0d4a3e92cd0f1e8146649924ef" - [[assets]] path = "reference/amp_004_folded_cascode.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/schematic.svg deleted file mode 100644 index 368b6cafb47c72e41f1a21e10601a4aa111eacf7..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_004_folded_cascode{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_004_folded_cascode","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["amp_004_folded_cascode"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_004_folded_cascode"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/design/amp_004_folded_cascode.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_004_folded_cascodefoldpfoldns9vdds10voutcascpvddnbiasibiasfoldpfoldnnbiasvsstailvinnvinpvoutvddibiasvssvb1vb2amp_004_folded_cascodegf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXM060/1 ×2XM196/0.5XM296/0.5XM360/1XM460/1P bulk → vddN bulk → vssXM982/1XM1082/1XM788/0.5XM888/0.5XM530/0.5XM630/0.5P bulk → vddN bulk → vssXM1160/1 ×2XM1260/1 ×2XM1360/1P bulk → vddN bulk → vssModels: pfet_03v3 · nfet_03v3 - diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml index a81a37ac402fd6b83f69a745d2b0807b6445ef7c..190f73b667a53980907608dca9fd5b65be499fb4 100644 --- a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml @@ -4,13 +4,6 @@ title = "Tan CLIA Three-Stage Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "96089d982396b1636c9585946b6ac3b7e1dd0d7ff5bf4e04949798cf8fc22fe3" - [[assets]] path = "reference/amp_017_tan_clia.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/schematic.svg deleted file mode 100644 index 2681ea5009727d05accfd7f2559840a323b584f8..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_017_tan_clia{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_017_tan_clia","source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["amp_017_tan_clia","Mm0_bank1","Mm1_bank2","Mm12_bank3","Mm13_bank4","Mm15_bank5","Mm16_bank6","Mm17_bank7","Mm18_bank8","Mm19_bank9","Mm2_bank10","Mm20_bank11","Mm3_bank12","Mm4_bank13_page1","Mm4_bank13_page2","Mm4_bank13","Mm5_bank14","Mm6_bank15","Mm61_bank16","Mm68_bank17","Mm73_bank18_page1","Mm73_bank18_page2","Mm73_bank18","Mm8_bank19","Mm9_bank20","XR0_bank21"],"banks":[{"name":"Mm0_bank1","devices":40,"source_references":["Mm0_0","Mm0_1","Mm0_2","Mm0_3","Mm0_4","Mm0_5","Mm0_6","Mm0_7","Mm0_8","Mm0_9","Mm0_10","Mm0_11","Mm0_12","Mm0_13","Mm0_14","Mm0_15","Mm0_16","Mm0_17","Mm0_18","Mm0_19","Mm0_20","Mm0_21","Mm0_22","Mm0_23","Mm0_24","Mm0_25","Mm0_26","Mm0_27","Mm0_28","Mm0_29","Mm0_30","Mm0_31","Mm0_32","Mm0_33","Mm0_34","Mm0_35","Mm0_36","Mm0_37","Mm0_38","Mm0_39"]},{"name":"Mm1_bank2","devices":40,"source_references":["Mm1_0","Mm1_1","Mm1_2","Mm1_3","Mm1_4","Mm1_5","Mm1_6","Mm1_7","Mm1_8","Mm1_9","Mm1_10","Mm1_11","Mm1_12","Mm1_13","Mm1_14","Mm1_15","Mm1_16","Mm1_17","Mm1_18","Mm1_19","Mm1_20","Mm1_21","Mm1_22","Mm1_23","Mm1_24","Mm1_25","Mm1_26","Mm1_27","Mm1_28","Mm1_29","Mm1_30","Mm1_31","Mm1_32","Mm1_33","Mm1_34","Mm1_35","Mm1_36","Mm1_37","Mm1_38","Mm1_39"]},{"name":"Mm12_bank3","devices":4,"source_references":["Mm12_0","Mm12_1","Mm12_2","Mm12_3"]},{"name":"Mm13_bank4","devices":4,"source_references":["Mm13_0","Mm13_1","Mm13_2","Mm13_3"]},{"name":"Mm15_bank5","devices":8,"source_references":["Mm15_0","Mm15_1","Mm15_2","Mm15_3","Mm15_4","Mm15_5","Mm15_6","Mm15_7"]},{"name":"Mm16_bank6","devices":8,"source_references":["Mm16_0","Mm16_1","Mm16_2","Mm16_3","Mm16_4","Mm16_5","Mm16_6","Mm16_7"]},{"name":"Mm17_bank7","devices":4,"source_references":["Mm17_0","Mm17_1","Mm17_2","Mm17_3"]},{"name":"Mm18_bank8","devices":4,"source_references":["Mm18_0","Mm18_1","Mm18_2","Mm18_3"]},{"name":"Mm19_bank9","devices":12,"source_references":["Mm19_0","Mm19_1","Mm19_2","Mm19_3","Mm19_4","Mm19_5","Mm19_6","Mm19_7","Mm19_8","Mm19_9","Mm19_10","Mm19_11"]},{"name":"Mm2_bank10","devices":40,"source_references":["Mm2_0","Mm2_1","Mm2_2","Mm2_3","Mm2_4","Mm2_5","Mm2_6","Mm2_7","Mm2_8","Mm2_9","Mm2_10","Mm2_11","Mm2_12","Mm2_13","Mm2_14","Mm2_15","Mm2_16","Mm2_17","Mm2_18","Mm2_19","Mm2_20","Mm2_21","Mm2_22","Mm2_23","Mm2_24","Mm2_25","Mm2_26","Mm2_27","Mm2_28","Mm2_29","Mm2_30","Mm2_31","Mm2_32","Mm2_33","Mm2_34","Mm2_35","Mm2_36","Mm2_37","Mm2_38","Mm2_39"]},{"name":"Mm20_bank11","devices":12,"source_references":["Mm20_0","Mm20_1","Mm20_2","Mm20_3","Mm20_4","Mm20_5","Mm20_6","Mm20_7","Mm20_8","Mm20_9","Mm20_10","Mm20_11"]},{"name":"Mm3_bank12","devices":40,"source_references":["Mm3_0","Mm3_1","Mm3_2","Mm3_3","Mm3_4","Mm3_5","Mm3_6","Mm3_7","Mm3_8","Mm3_9","Mm3_10","Mm3_11","Mm3_12","Mm3_13","Mm3_14","Mm3_15","Mm3_16","Mm3_17","Mm3_18","Mm3_19","Mm3_20","Mm3_21","Mm3_22","Mm3_23","Mm3_24","Mm3_25","Mm3_26","Mm3_27","Mm3_28","Mm3_29","Mm3_30","Mm3_31","Mm3_32","Mm3_33","Mm3_34","Mm3_35","Mm3_36","Mm3_37","Mm3_38","Mm3_39"]},{"name":"Mm4_bank13","devices":80,"source_references":["Mm4_0","Mm4_1","Mm4_2","Mm4_3","Mm4_4","Mm4_5","Mm4_6","Mm4_7","Mm4_8","Mm4_9","Mm4_10","Mm4_11","Mm4_12","Mm4_13","Mm4_14","Mm4_15","Mm4_16","Mm4_17","Mm4_18","Mm4_19","Mm4_20","Mm4_21","Mm4_22","Mm4_23","Mm4_24","Mm4_25","Mm4_26","Mm4_27","Mm4_28","Mm4_29","Mm4_30","Mm4_31","Mm4_32","Mm4_33","Mm4_34","Mm4_35","Mm4_36","Mm4_37","Mm4_38","Mm4_39","Mm4_40","Mm4_41","Mm4_42","Mm4_43","Mm4_44","Mm4_45","Mm4_46","Mm4_47","Mm4_48","Mm4_49","Mm4_50","Mm4_51","Mm4_52","Mm4_53","Mm4_54","Mm4_55","Mm4_56","Mm4_57","Mm4_58","Mm4_59","Mm4_60","Mm4_61","Mm4_62","Mm4_63","Mm4_64","Mm4_65","Mm4_66","Mm4_67","Mm4_68","Mm4_69","Mm4_70","Mm4_71","Mm4_72","Mm4_73","Mm4_74","Mm4_75","Mm4_76","Mm4_77","Mm4_78","Mm4_79"]},{"name":"Mm5_bank14","devices":25,"source_references":["Mm5_0","Mm5_1","Mm5_2","Mm5_3","Mm5_4","Mm5_5","Mm5_6","Mm5_7","Mm5_8","Mm5_9","Mm5_10","Mm5_11","Mm5_12","Mm5_13","Mm5_14","Mm5_15","Mm5_16","Mm5_17","Mm5_18","Mm5_19","Mm5_20","Mm5_21","Mm5_22","Mm5_23","Mm5_24"]},{"name":"Mm6_bank15","devices":25,"source_references":["Mm6_0","Mm6_1","Mm6_2","Mm6_3","Mm6_4","Mm6_5","Mm6_6","Mm6_7","Mm6_8","Mm6_9","Mm6_10","Mm6_11","Mm6_12","Mm6_13","Mm6_14","Mm6_15","Mm6_16","Mm6_17","Mm6_18","Mm6_19","Mm6_20","Mm6_21","Mm6_22","Mm6_23","Mm6_24"]},{"name":"Mm61_bank16","devices":6,"source_references":["Mm61_0","Mm61_1","Mm61_2","Mm61_3","Mm61_4","Mm61_5"]},{"name":"Mm68_bank17","devices":6,"source_references":["Mm68_0","Mm68_1","Mm68_2","Mm68_3","Mm68_4","Mm68_5"]},{"name":"Mm73_bank18","devices":120,"source_references":["Mm73_0","Mm73_1","Mm73_2","Mm73_3","Mm73_4","Mm73_5","Mm73_6","Mm73_7","Mm73_8","Mm73_9","Mm73_10","Mm73_11","Mm73_12","Mm73_13","Mm73_14","Mm73_15","Mm73_16","Mm73_17","Mm73_18","Mm73_19","Mm73_20","Mm73_21","Mm73_22","Mm73_23","Mm73_24","Mm73_25","Mm73_26","Mm73_27","Mm73_28","Mm73_29","Mm73_30","Mm73_31","Mm73_32","Mm73_33","Mm73_34","Mm73_35","Mm73_36","Mm73_37","Mm73_38","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main sheet follows the amplifier signal path; auxiliary bias nets remain label-connected.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Existing device banks and split detail sheets remain the editable hierarchy."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":18},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_017_tan_clia"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/design/amp_017_tan_clia.icproj.json"}}Main-sheet overview; 25 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_017_tan_cliavddnet1net31vdddm_1vddnet1vssnet8vb3net050vddnet1vb4vinpnet8net31vddvoutnnet050vssnet8vb4vssvb4dm_2vssvb4net3vssvb3dm_1net7vinndm_2net31vssvb4vb3net6vssnet2net5vddvoutnvssvb3voutndm_2vssvb4net6vssvb4net7vddnet1vb3vddnet5dm_1vddvoutnet050voutnet5vssvssvoutnet2net5vddvddnet050net3vddvddnet050net3vssnet3net3voutvssnet5net3vssnet5net3vssnet8net5net3vddvb4vssvb4vb3net6vssvb3dm_1voutnet7vssvb3dm_2vssvb3net8vssvb4net6vssvb4net7vssvb4dm_2vdddm_1vssnet8vb4vssvddvb3vddnet31vddvddvssnet050vssvb4net3vddvb3vddnet5dm_1dm_2net31net31vb3vssnet2net5vssvddvinnvinpvoutnet1vssvssvoutnet5vssvssamp_017_tan_cliaPMOS input pair → cascoded branches → current inversion → complementary output.C0_0cap_mim_2f0fFC1_0cap_mim_2f0fFC1_1cap_mim_2f0fFMm14_0nfet_03v3Mm69_0nfet_03v3Mm69_1nfet_03v3Mm69_2nfet_03v3Mm70_0pfet_03v3Mm70_1pfet_03v3Mm71_0nfet_03v3Mm72_0nfet_03v3Mm72_1nfet_03v3Mm72_2nfet_03v3XMm0_bank1XMm1_bank2XMm12_bank3XMm13_bank4XMm15_bank5XMm16_bank6XMm17_bank7XMm18_bank8XMm19_bank9XMm2_bank10XMm20_bank11XMm3_bank12XMm4_bank13XMm5_bank14XMm6_bank15XMm61_bank16XMm68_bank17XMm73_bank18XMm8_bank19XMm9_bank20XXR0_bank21 - diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml index 8fde0356c6e0ebbeb3f172428354ba7ffa086b53..7f98299478daac76ce207776e95039db5c577a3b 100644 --- a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml @@ -4,13 +4,6 @@ title = "Tail-Referenced Telescopic Cascode Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "a0c1cac7ee9169f75aee339de93ee5e66e2343f7b361e42733dd26143e611336" - [[assets]] path = "reference/amp_018_telescopic_cascode.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/schematic.svg deleted file mode 100644 index d6f51a35e4217010399fa74d5c0d2e1f3c6b8c8c..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_018_telescopic_cascode{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_018_telescopic_cascode","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["amp_018_telescopic_cascode"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_018_telescopic_cascode"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/design/amp_018_telescopic_cascode.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_018_telescopic_cascodes3s4d1d2gate_pvssibiasvddvoutvinpvinnibiasvssgate_pccasc_ntailamp_018_telescopic_cascodegf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXM34.7/0.5XM44.7/0.5XM3C7.2/0.5XM4C7.2/0.5XM1C5.7/0.5XM2C5.7/0.5XM123.3/1XM223.3/1XM54.95/0.5P bulk → vddN bulk → vssXM68.3/0.5N bulk → vss - diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml index a256d69631c8be8174d17d354fc8c17e7178218d..08ea6c08d276c2257e132b9f95cecfba96f0771e 100644 --- a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml @@ -4,13 +4,6 @@ title = "Externally Biased TI-Architecture Error Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "3877db1eacb0c847928306e6aafa5705ddc84e0e1c3f6eabba14d099838be54d" - [[assets]] path = "reference/amp_019_ti_ldo_error.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/schematic.svg deleted file mode 100644 index 1958e88a1dfdd34d3938867b1ea08204d3507a95..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_019_ti_ldo_error{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_019_ti_ldo_error","source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["amp_019_ti_ldo_error","XCC_bank1","XRND_bank2"],"banks":[{"name":"XCC_bank1","devices":32,"source_references":["CC_0","CC_1","CC_2","CC_3","CC_4","CC_5","CC_6","CC_7","CC_8","CC_9","CC_10","CC_11","CC_12","CC_13","CC_14","CC_15","CC_16","CC_17","CC_18","CC_19","CC_20","CC_21","CC_22","CC_23","CC_24","CC_25","CC_26","CC_27","CC_28","CC_29","CC_30","CC_31"]},{"name":"XRND_bank2","devices":10,"source_references":["RND_0","RND_1","RND_2","RND_3","RND_4","RND_5","RND_6","RND_7","RND_8","RND_9"]}],"limitations":["The SVG renders the main sheet. Capacitor and resistor-ladder source instances remain in editable child sheets.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":14},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_019_ti_ldo_error"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/design/amp_019_ti_ldo_error.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_019_ti_ldo_errorvoutnczvssnandibiasnanbnczndnenlevtailvddvinnvinpvoutvssvssvinpibiasvddvinnvssvoutamp_019_ti_ldo_errorDifferential error amplifier with programmable compensationMM1_0w=40u l=0.7uMM2_0w=40u l=0.7uMM3_0w=100u l=0.55uMM4_0w=10u l=0.55uMM5_0w=100u l=0.55uMM6_0w=100u l=0.55uMM7_0w=40u l=0.55uMMB0_0w=10u l=2uMMBC_0w=10u l=2uMMBE_0w=0.4u l=2uMMBF_0w=5u l=2uMMBO_0w=10u l=2uRZ0_0ppolyf_u_1kw=1u l=1.66uRZ substrate: B=vssRZ1_0ppolyf_u_1kw=1u l=1.66uRZ2_0ppolyf_u_1kw=1u l=1.66uRZ3_0ppolyf_u_1kw=1u l=1.66uXXCC_bank1XXRND_bank2 - diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml index 9f1b21f0a92894a342e82bea7ff20864c172a9e7..48e61d07e0e3c72574d0d4a4e3442a7ff381a237 100644 --- a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml @@ -4,13 +4,6 @@ title = "Self-Biased LDO Error Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "9712137b8c384eabead2a587c4d3edf430493ba35bd2c71997868b2e51089bc4" - [[assets]] path = "reference/amp_032_ti_ldo_error_selfbias.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/schematic.svg deleted file mode 100644 index 21f5919a817cd6aa120d088a689dfd69d92a9ba8..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_032_ti_ldo_error_selfbias{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_032_ti_ldo_error_selfbias","source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["amp_032_ti_ldo_error_selfbias","XCC_bank1","XRND_bank2"],"banks":[{"name":"XCC_bank1","devices":19,"source_references":["CC_0","CC_1","CC_2","CC_3","CC_4","CC_5","CC_6","CC_7","CC_8","CC_9","CC_10","CC_11","CC_12","CC_13","CC_14","CC_15","CC_16","CC_17","CC_18"]},{"name":"XRND_bank2","devices":10,"source_references":["RND_0","RND_1","RND_2","RND_3","RND_4","RND_5","RND_6","RND_7","RND_8","RND_9"]}],"limitations":["The SVG renders the main sheet. Capacitor and resistor-ladder source instances remain in editable child sheets.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":11},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_032_ti_ldo_error_selfbias"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/design/amp_032_ti_ldo_error_selfbias.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_032_ti_ldo_error_selfbiasvoutnczvssnandvssvssibiasnanbnczndnlevtailvddvinnvinpvoutvssvinpvddvssvinnvoutamp_032_ti_ldo_error_selfbiasSelf-biased LDO error amplifierRZ_0ppolyf_u_1kw=1u l=10uSubstrate: B=vssMM1_0w=68.54u l=0.7uMM2_0w=68.54u l=0.7uMM3_0w=69.545u l=0.55uMM4_0w=10u l=0.55uMM5_0w=69.545u l=0.55uMM6_0w=60u l=1uMMB0_0w=34.535u l=2uMMBC_0w=34.535u l=2uMMBF_0w=5u l=2uMMBO_0w=34.535u l=2uMMBP_0w=6.31u l=2uXXCC_bank1XCC_bank1XXRND_bank2 - diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml index 9a4d99bdf9c4a21c1114df741f27c83f7f7736b4..3189ba137e43bdffb3d2ffde7bb8d6037117079f 100644 --- a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml @@ -4,13 +4,6 @@ title = "Self-Biased LDO Reference Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "3a60e5ac289e157e6ceb21e205297bab3364801e6e6c0371740cd86005a74204" - [[assets]] path = "reference/amp_033_ti_ldo_ref_selfbias.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/schematic.svg deleted file mode 100644 index 6a5da4d443fed9ca7d15c69165f4cf7d40a016be..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_033_ti_ldo_ref_selfbias{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.amp_033_ti_ldo_ref_selfbias","source_netlist":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["amp_033_ti_ldo_ref_selfbias","XCC_bank1"],"banks":[{"name":"XCC_bank1","devices":6,"source_references":["CC_0","CC_1","CC_2","CC_3","CC_4","CC_5"]}],"limitations":["The SVG renders the main sheet. The six source capacitors remain on the editable child sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":1},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_033_ti_ldo_ref_selfbias"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/design/amp_033_ti_ldo_ref_selfbias.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_033_ti_ldo_ref_selfbiasvoutnczvoutnbibiasvinnvssnatailvinpvddnczvssvssvinpvinnvddvoutvssamp_033_ti_ldo_ref_selfbiasSelf-biased reference amplifierRZ_0ppolyf_u_1kw=1u l=30.855uSubstrate: B=vssMM1_0nfet_06v0w=86.42u l=0.7uMM2_0nfet_06v0w=86.42u l=0.7uMM3_0pfet_06v0w=20u l=1uMM4_0pfet_06v0w=20u l=1uMM5_0pfet_06v0w=37.76u l=2.645uMMB0_0nfet_06v0w=12u l=2uMMBC_0nfet_06v0w=8.315u l=2uMMBO_0nfet_06v0w=4u l=2uMMBP_0pfet_06v0w=10.845u l=2uXXCC_bank1XCC_bank1 - diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml index 5a9d3c3063aa19931d9b31f22592dca0682b0cb5..434693f760d4ae0f45e0135a4a2c6060482fa4f4 100644 --- a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml @@ -4,13 +4,6 @@ title = "Segmented-Resistor NMOS Common-Mode Controller" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "e72dd81bd5455bb1676402b03936c909f00cd6305e13b84ac78748749e690c7d" - [[assets]] path = "reference/cmfb_003_5t_nmos_input.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/schematic.svg deleted file mode 100644 index 1b240f005d05afd61ea7aac63cce03b7c74e3251..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -cmfb_003_5t_nmos_input{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.cmfb_003_5t_nmos_input","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["cmfb_003_5t_nmos_input","Bank1_20series_ppolyf_u_1k","Bank2_20series_ppolyf_u_1k"],"banks":[{"name":"Bank1_20series_ppolyf_u_1k","count":20,"model":"ppolyf_u_1k","kind":"series","members":["XRMN_0","XRMN_1","XRMN_2","XRMN_3","XRMN_4","XRMN_5","XRMN_6","XRMN_7","XRMN_8","XRMN_9","XRMN_10","XRMN_11","XRMN_12","XRMN_13","XRMN_14","XRMN_15","XRMN_16","XRMN_17","XRMN_18","XRMN_19"]},{"name":"Bank2_20series_ppolyf_u_1k","count":20,"model":"ppolyf_u_1k","kind":"series","members":["XRMP_0","XRMP_1","XRMP_2","XRMP_3","XRMP_4","XRMP_5","XRMP_6","XRMP_7","XRMP_8","XRMP_9","XRMP_10","XRMP_11","XRMP_12","XRMP_13","XRMP_14","XRMP_15","XRMP_16","XRMP_17","XRMP_18","XRMP_19"]}],"source_netlist":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":40},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cmfb_003_5t_nmos_input"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/design/cmfb_003_5t_nmos_input.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.cmfb_003_5t_nmos_inputvinncm_sensevsscm_sensevinpvssvddvssbiasvinncm_sensevsscm_sensevinpvsscm_sensevrefbiasvssvddvcmfbntailmirrvinpvinnvcmfbvrefvddvsscmfb_003_5t_nmos_inputCommon-mode error amplifierXM342/2XM442/2XM110/1XM210/1XM813/1Self-biased referenceXM61/2XM56.5/1Negative-output sensing stringXBANK1Bank1_20series_ppolyf_u_1kPositive-output sensing stringXBANK2Bank2_20series_ppolyf_u_1k - diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml index 37d005b1aca9fa29dd17c71f1110fe5af8008688..8a62420a1013f3da80129b65b7e0468bfa2602c4 100644 --- a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml @@ -4,13 +4,6 @@ title = "Resistive-Feedback Hysteretic Comparator" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "35ce9376096cd5be1cc888d88452a90b77c24fba5b1a30331911b6d50cf9ac07" - [[assets]] path = "reference/cmp_001_hyst_diffpair.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/schematic.svg deleted file mode 100644 index 7de866c66b2aea648b3c94abf0671f9ffc18beed..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -cmp_001_hyst_diffpair{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.cmp_001_hyst_diffpair","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["cmp_001_hyst_diffpair"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":3},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cmp_001_hyst_diffpair"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/design/cmp_001_hyst_diffpair.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.cmp_001_hyst_diffpairn1vddvssb1b2vsshpvoutn1hnvssvddn1tailn2vddvoutvinpvinnvsscmp_001_hyst_diffpairgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXMPLD10/0.3 ×4XMPLM10/0.3 ×4XMIN10/0.3 ×2XMIP10/0.3 ×2XRTW/L 2/12P bulk → vddN bulk → vssR substrate → vssXMB1P5/0.28XMB2P5/0.28 ×2XMB3P5/0.28 ×4XMB1N2/0.28XMB2N2/0.28 ×2XMB3N2/0.28 ×4P bulk → vddN bulk → vssXMHP1/0.3XRHPW/L 2/600XRHNW/L 2/600XMHN1/0.3P bulk → vddR substrate → vssN bulk → vssModels: ppolyf_u_1k · nfet_03v3 · pfet_03v3 - diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml index 3b087f85631627c330b89bfa01644fd1fb9ede63..77eed01dd4274e04c3953bdfc78a5c8d4735b8f9 100644 --- a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 18 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "5aad5646b68087127a52b264d5bf88ef61ca1f69ba8bdedc59ef93d76e63064a" - [[assets]] path = "reference/cmp_002_strongarm.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/schematic.svg deleted file mode 100644 index 0e83f625f67187d81dd8f7d7cc445f8e4e155549..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -cmp_002_strongarm{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.cmp_002_strongarm","source_netlist":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["cmp_002_strongarm"],"banks":[],"known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cmp_002_strongarm"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/design/cmp_002_strongarm.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.cmp_002_strongarmclklmlmlplpclkvddvinnvinpvoutnvoutpvsssnsnspspvddvddvddvddvssvssvssvssvssvssvssvsscmp_002_strongarmModels: nfet_03v3 and pfet_03v3; W/L is shown per device.MMINN_0w=8u l=0.28uMMINN_1w=8u l=0.28uMMINP_0w=8u l=0.28uMMINP_1w=8u l=0.28uMMLEM_0w=4u l=0.28uMMLEP_0w=4u l=0.28uMMLUM_0w=4u l=0.28uMMLUP_0w=4u l=0.28uMMOBN1_0w=1.5u l=0.28uMMOBN2_0w=1.5u l=0.28uMMOBP1_0w=3u l=0.28uMMOBP2_0w=3u l=0.28uMMPC1_0w=2u l=0.28uMMPC2_0w=2u l=0.28uMMPC3_0w=2u l=0.28uMMPC4_0w=2u l=0.28uMMTAIL_0w=4u l=0.28u - diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml index c49eb559a3cb5fb605d8f059db557488b8206ce1..0f1f8bddcf54a8bd5de6437f904644eafac12603 100644 --- a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml @@ -4,13 +4,6 @@ title = "Resistively Loaded Differential Pair" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "c0e54c8393f7decf7f5d56880180cd24066618738d7e45172c213919211632c6" - [[assets]] path = "reference/dp_001_resistive_load.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/schematic.svg deleted file mode 100644 index 0c08d1d8689e42b9984d5706d5d9177acf0300c0..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -dp_001_resistive_load{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.dp_001_resistive_load","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["dp_001_resistive_load"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":2},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["dp_001_resistive_load"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/design/dp_001_resistive_load.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.dp_001_resistive_loadtailvssibiasvoutpvoutnvinpvinnibiasvssvdddp_001_resistive_loadgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXRPW/L 2/44XRNW/L 2/44XMP12/0.3XMN12/0.3XMT24/0.3R substrate → vssN bulk → vssXMR24/0.3N bulk → vss - diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml index d4518586adc0d395bcc530431dd1501dac9f6c71..c3db2c8485b82e5901dbb6911bbc4adb4f4714cd 100644 --- a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml @@ -4,13 +4,6 @@ title = "Self-Biased Cascode Common-Source Gain Stage" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "963fd971e795de0261eff9e143ca95134293fbec4adbda8927a8c2fc97e16887" - [[assets]] path = "reference/gs_001_cascode_cs.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/schematic.svg deleted file mode 100644 index 00710c0acd15ce2a90abe0e3456aec1b992981fb..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -gs_001_cascode_cs{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.gs_001_cascode_cs","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["gs_001_cascode_cs"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["gs_001_cascode_cs"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/design/gs_001_cascode_cs.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.gs_001_cascode_csvddpbias1nbias2ibiasnbias1pbias1ibiasnbias2vsspintnintvddvoutvinibiasvssgs_001_cascode_csgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXMPLD10/0.5XMPCA10/0.5XMNCA4/0.3XMNIN4/0.3P bulk → vddN bulk → vssXMPB116/0.5XMPNR0.5/0.5XMPB216/0.5XMNB26/0.3XMNB16/0.3P bulk → vddN bulk → vssModels: nfet_03v3 · pfet_03v3 - diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml index 5f1bf46a68d5a77c5e03450aa5ccf2d16ebf92c5..37a5c507ae36d8493a343d25ca8e1e3cdb2d9426 100644 --- a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml @@ -4,13 +4,6 @@ title = "Folded-Cascode LDO" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "ad4eeffa3d8ecbe74a6b69a46af5e2067e640ea6e8b2c68d8019a7111d832110" - [[assets]] path = "reference/ldo_002_analoggym_folded_cascode.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/schematic.svg deleted file mode 100644 index 17d9d7ec16db0369a9fa6b43739eb272b38af149..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_002_analoggym_folded_cascode{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_002_analoggym_folded_cascode","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["ldo_002_analoggym_folded_cascode","MMP_bank1"],"banks":[{"name":"MMP_bank1","devices":250,"source_references":["MMP_0","MMP_1","MMP_2","MMP_3","MMP_4","MMP_5","MMP_6","MMP_7","MMP_8","MMP_9","MMP_10","MMP_11","MMP_12","MMP_13","MMP_14","MMP_15","MMP_16","MMP_17","MMP_18","MMP_19","MMP_20","MMP_21","MMP_22","MMP_23","MMP_24","MMP_25","MMP_26","MMP_27","MMP_28","MMP_29","MMP_30","MMP_31","MMP_32","MMP_33","MMP_34","MMP_35","MMP_36","MMP_37","MMP_38","MMP_39","MMP_40","MMP_41","MMP_42","MMP_43","MMP_44","MMP_45","MMP_46","MMP_47","MMP_48","MMP_49","MMP_50","MMP_51","MMP_52","MMP_53","MMP_54","MMP_55","MMP_56","MMP_57","MMP_58","MMP_59","MMP_60","MMP_61","MMP_62","MMP_63","MMP_64","MMP_65","MMP_66","MMP_67","MMP_68","MMP_69","MMP_70","MMP_71","MMP_72","MMP_73","MMP_74","MMP_75","MMP_76","MMP_77","MMP_78","MMP_79","MMP_80","MMP_81","MMP_82","MMP_83","MMP_84","MMP_85","MMP_86","MMP_87","MMP_88","MMP_89","MMP_90","MMP_91","MMP_92","MMP_93","MMP_94","MMP_95","MMP_96","MMP_97","MMP_98","MMP_99","MMP_100","MMP_101","MMP_102","MMP_103","MMP_104","MMP_105","MMP_106","MMP_107","MMP_108","MMP_109","MMP_110","MMP_111","MMP_112","MMP_113","MMP_114","MMP_115","MMP_116","MMP_117","MMP_118","MMP_119","MMP_120","MMP_121","MMP_122","MMP_123","MMP_124","MMP_125","MMP_126","MMP_127","MMP_128","MMP_129","MMP_130","MMP_131","MMP_132","MMP_133","MMP_134","MMP_135","MMP_136","MMP_137","MMP_138","MMP_139","MMP_140","MMP_141","MMP_142","MMP_143","MMP_144","MMP_145","MMP_146","MMP_147","MMP_148","MMP_149","MMP_150","MMP_151","MMP_152","MMP_153","MMP_154","MMP_155","MMP_156","MMP_157","MMP_158","MMP_159","MMP_160","MMP_161","MMP_162","MMP_163","MMP_164","MMP_165","MMP_166","MMP_167","MMP_168","MMP_169","MMP_170","MMP_171","MMP_172","MMP_173","MMP_174","MMP_175","MMP_176","MMP_177","MMP_178","MMP_179","MMP_180","MMP_181","MMP_182","MMP_183","MMP_184","MMP_185","MMP_186","MMP_187","MMP_188","MMP_189","MMP_190","MMP_191","MMP_192","MMP_193","MMP_194","MMP_195","MMP_196","MMP_197","MMP_198","MMP_199","MMP_200","MMP_201","MMP_202","MMP_203","MMP_204","MMP_205","MMP_206","MMP_207","MMP_208","MMP_209","MMP_210","MMP_211","MMP_212","MMP_213","MMP_214","MMP_215","MMP_216","MMP_217","MMP_218","MMP_219","MMP_220","MMP_221","MMP_222","MMP_223","MMP_224","MMP_225","MMP_226","MMP_227","MMP_228","MMP_229","MMP_230","MMP_231","MMP_232","MMP_233","MMP_234","MMP_235","MMP_236","MMP_237","MMP_238","MMP_239","MMP_240","MMP_241","MMP_242","MMP_243","MMP_244","MMP_245","MMP_246","MMP_247","MMP_248","MMP_249"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","MMP_bank1 is the detail sheet for the 250 individual parallel pass devices."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":3},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_002_analoggym_folded_cascode"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/design/ldo_002_analoggym_folded_cascode.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_002_analoggym_folded_cascodevddvoutngatevddR_BLEED_seg1vssvddvddn2n3n4nczngatenmirnmirnmirngatevb1vb1vb1vb2vb2vddvoutvrefvssldo_002_analoggym_folded_cascodeFolded-cascode error amplifier drives the 250-device PMOS pass bank; vout feeds back to MM1.MM1_0w=60u l=0.7uMM2_0w=60u l=0.7uMM3_0w=30u l=0.55uMM4_0w=30u l=0.55uMM5_0w=10u l=0.55uMM6_0w=10u l=0.55uMM7_0w=20u l=2uMM8_0w=20u l=2uMM9_0w=30u l=0.7uXMMP_bank1MMP_bank1 - diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml index 459b1d6cb167042a0a70deda0524f42b9bfe7792..a1ca1b45e3350f16b062a24083d9fc003c116103 100644 --- a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml @@ -4,13 +4,6 @@ title = "Simple Unity-Feedback LDO" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "a223a98879e607a78a8842a8df6b4cad3f6ef1e233084f6c7b152c566f46970a" - [[assets]] path = "reference/ldo_003_analoggym_simple.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/schematic.svg deleted file mode 100644 index 0a2043ef8c2db1a834843f9f39c819ff8877ce41..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_003_analoggym_simple{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_003_analoggym_simple","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["ldo_003_analoggym_simple","MMP_bank1_page1","MMP_bank1_page2","MMP_bank1_page3","MMP_bank1_page4","MMP_bank1_page5","MMP_bank1_page6","MMP_bank1"],"banks":[{"name":"MMP_bank1","devices":360,"source_references":["MMP_0","MMP_1","MMP_2","MMP_3","MMP_4","MMP_5","MMP_6","MMP_7","MMP_8","MMP_9","MMP_10","MMP_11","MMP_12","MMP_13","MMP_14","MMP_15","MMP_16","MMP_17","MMP_18","MMP_19","MMP_20","MMP_21","MMP_22","MMP_23","MMP_24","MMP_25","MMP_26","MMP_27","MMP_28","MMP_29","MMP_30","MMP_31","MMP_32","MMP_33","MMP_34","MMP_35","MMP_36","MMP_37","MMP_38","MMP_39","MMP_40","MMP_41","MMP_42","MMP_43","MMP_44","MMP_45","MMP_46","MMP_47","MMP_48","MMP_49","MMP_50","MMP_51","MMP_52","MMP_53","MMP_54","MMP_55","MMP_56","MMP_57","MMP_58","MMP_59","MMP_60","MMP_61","MMP_62","MMP_63","MMP_64","MMP_65","MMP_66","MMP_67","MMP_68","MMP_69","MMP_70","MMP_71","MMP_72","MMP_73","MMP_74","MMP_75","MMP_76","MMP_77","MMP_78","MMP_79","MMP_80","MMP_81","MMP_82","MMP_83","MMP_84","MMP_85","MMP_86","MMP_87","MMP_88","MMP_89","MMP_90","MMP_91","MMP_92","MMP_93","MMP_94","MMP_95","MMP_96","MMP_97","MMP_98","MMP_99","MMP_100","MMP_101","MMP_102","MMP_103","MMP_104","MMP_105","MMP_106","MMP_107","MMP_108","MMP_109","MMP_110","MMP_111","MMP_112","MMP_113","MMP_114","MMP_115","MMP_116","MMP_117","MMP_118","MMP_119","MMP_120","MMP_121","MMP_122","MMP_123","MMP_124","MMP_125","MMP_126","MMP_127","MMP_128","MMP_129","MMP_130","MMP_131","MMP_132","MMP_133","MMP_134","MMP_135","MMP_136","MMP_137","MMP_138","MMP_139","MMP_140","MMP_141","MMP_142","MMP_143","MMP_144","MMP_145","MMP_146","MMP_147","MMP_148","MMP_149","MMP_150","MMP_151","MMP_152","MMP_153","MMP_154","MMP_155","MMP_156","MMP_157","MMP_158","MMP_159","MMP_160","MMP_161","MMP_162","MMP_163","MMP_164","MMP_165","MMP_166","MMP_167","MMP_168","MMP_169","MMP_170","MMP_171","MMP_172","MMP_173","MMP_174","MMP_175","MMP_176","MMP_177","MMP_178","MMP_179","MMP_180","MMP_181","MMP_182","MMP_183","MMP_184","MMP_185","MMP_186","MMP_187","MMP_188","MMP_189","MMP_190","MMP_191","MMP_192","MMP_193","MMP_194","MMP_195","MMP_196","MMP_197","MMP_198","MMP_199","MMP_200","MMP_201","MMP_202","MMP_203","MMP_204","MMP_205","MMP_206","MMP_207","MMP_208","MMP_209","MMP_210","MMP_211","MMP_212","MMP_213","MMP_214","MMP_215","MMP_216","MMP_217","MMP_218","MMP_219","MMP_220","MMP_221","MMP_222","MMP_223","MMP_224","MMP_225","MMP_226","MMP_227","MMP_228","MMP_229","MMP_230","MMP_231","MMP_232","MMP_233","MMP_234","MMP_235","MMP_236","MMP_237","MMP_238","MMP_239","MMP_240","MMP_241","MMP_242","MMP_243","MMP_244","MMP_245","MMP_246","MMP_247","MMP_248","MMP_249","MMP_250","MMP_251","MMP_252","MMP_253","MMP_254","MMP_255","MMP_256","MMP_257","MMP_258","MMP_259","MMP_260","MMP_261","MMP_262","MMP_263","MMP_264","MMP_265","MMP_266","MMP_267","MMP_268","MMP_269","MMP_270","MMP_271","MMP_272","MMP_273","MMP_274","MMP_275","MMP_276","MMP_277","MMP_278","MMP_279","MMP_280","MMP_281","MMP_282","MMP_283","MMP_284","MMP_285","MMP_286","MMP_287","MMP_288","MMP_289","MMP_290","MMP_291","MMP_292","MMP_293","MMP_294","MMP_295","MMP_296","MMP_297","MMP_298","MMP_299","MMP_300","MMP_301","MMP_302","MMP_303","MMP_304","MMP_305","MMP_306","MMP_307","MMP_308","MMP_309","MMP_310","MMP_311","MMP_312","MMP_313","MMP_314","MMP_315","MMP_316","MMP_317","MMP_318","MMP_319","MMP_320","MMP_321","MMP_322","MMP_323","MMP_324","MMP_325","MMP_326","MMP_327","MMP_328","MMP_329","MMP_330","MMP_331","MMP_332","MMP_333","MMP_334","MMP_335","MMP_336","MMP_337","MMP_338","MMP_339","MMP_340","MMP_341","MMP_342","MMP_343","MMP_344","MMP_345","MMP_346","MMP_347","MMP_348","MMP_349","MMP_350","MMP_351","MMP_352","MMP_353","MMP_354","MMP_355","MMP_356","MMP_357","MMP_358","MMP_359"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":3},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_003_analoggym_simple"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/design/ldo_003_analoggym_simple.icproj.json"}}Main-sheet overview; 7 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_003_analoggym_simplevddvoutngatevddvoutvssvbvrefngatengatenczldo_003_analoggym_simpleCC_0cap_mim_2f0fFw=20u l=12.5uCC_1cap_mim_2f0fFw=20u l=12.5uRZ_0ppolyf_u_1kw=1u l=2.75uSubstrate: B=vssR_BLEED_0ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssR_BLEED_1ppolyf_u_1kw=1u l=48.44uSubstrate: B=vssMM1_0nfet_06v0w=2u l=2uMM2_0nfet_06v0w=2u l=2uMM3_0pfet_06v0w=80u l=0.55uMM4_0pfet_06v0w=80u l=0.55uMM5_0nfet_06v0w=100u l=0.7uXMMP_bank1MMP_bank1 - diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml index 0b0cbc4cdbca2fd86975b5ceeaa5e2992ce1ed20..e52b5d3b9bc45ae8ef8af2b85725b8b81be8821e 100644 --- a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml @@ -4,13 +4,6 @@ title = "Externally Biased 1.8 V PMOS Regulator Core" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "4db4e5eb0cf08e3391cf074eb290d28e680668fe3a70156a4ec40bc2313ef6e4" - [[assets]] path = "reference/ldo_004_basic_pmos.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/schematic.svg deleted file mode 100644 index 359b80f6ebea46bd55c99e309dc2c24f0e9091ec..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_004_basic_pmos{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_004_basic_pmos","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["ldo_004_basic_pmos"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":2},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_004_basic_pmos"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/design/ldo_004_basic_pmos.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.ldo_004_basic_pmosegatevddfbfbegatenoutmvddvoutvrefibiasvssldo_004_basic_pmosgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXM350/0.5XM450/0.5XM146/0.5XM246/0.5P bulk → vddN bulk → vssXMP10/0.3 ×100XR1W/L 2/200XR2W/L 2/200P bulk → vddR substrate → vss - diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml index 30c88c0c44c94f3dcf5e7e2c815e898f8db2b5b2..016f3dfd9389af137b6c4eabbeedd1ea82f0173f 100644 --- a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml @@ -4,13 +4,6 @@ title = "Buffered-Reference LDO" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "16844a2fe1c8dd18bb3176ab0e3510df7cbc8df9807b4cda3ecbe5d74787f4c1" - [[assets]] path = "reference/ldo_005_buffered_ref.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/schematic.svg deleted file mode 100644 index dce835378882a4b22af263cb493a987f58f614a8..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_005_buffered_ref{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_005_buffered_ref","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["ldo_005_buffered_ref","MMP_bank1","XC1_bank2","XCRAC_bank3","XC_LPF_bank4"],"banks":[{"name":"MMP_bank1","devices":7,"source_references":["MMP_0","MMP_1","MMP_2","MMP_3","MMP_4","MMP_5","MMP_6"]},{"name":"XC1_bank2","devices":13,"source_references":["C1_0","C1_1","C1_2","C1_3","C1_4","C1_5","C1_6","C1_7","C1_8","C1_9","C1_10","C1_11","C1_12"]},{"name":"XCRAC_bank3","devices":6,"source_references":["CRAC_0","CRAC_1","CRAC_2","CRAC_3","CRAC_4","CRAC_5"]},{"name":"XC_LPF_bank4","devices":13,"source_references":["C_LPF_0","C_LPF_1","C_LPF_2","C_LPF_3","C_LPF_4","C_LPF_5","C_LPF_6","C_LPF_7","C_LPF_8","C_LPF_9","C_LPF_10","C_LPF_11","C_LPF_12"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":9},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_005_buffered_ref"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/design/ldo_005_buffered_ref.icproj.json"}}Main-sheet overview; 4 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_005_buffered_refvoutvssvssv_lpf_outvddvoutea_outra_nczv_ref_outv_ref_outv_ref_outvddvssvssvssvssv_ref_outv_ref_outra_nbra_nbra_nczv_lpf_outea_nlevea_nlevldo_005_buffered_refCEAC_0w=10u l=10uR1_0w=1u l=50uSubstrate: B=vssR1_1w=1u l=50uSubstrate: B=vssR2_0w=1u l=50uSubstrate: B=vssR2_1w=1u l=50uSubstrate: B=vssR3_0w=1u l=10uSubstrate: B=vssREAND_0w=1u l=50uSubstrate: B=vssREAZ_0w=1u l=28.43uSubstrate: B=vssRRAZ_0w=1u l=30.855uSubstrate: B=vssR_LPF_0w=1u l=10uSubstrate: B=vssMMEA_1_0w=68.54u l=0.7uMMEA_2_0w=68.54u l=0.7uMMEA_3_0w=100u l=0.55uMMEA_4_0w=10u l=0.55uMMEA_5_0w=100u l=0.55uMMEA_6_0w=14u l=3.835uMMEA_B0_0w=34.535u l=2uMMEA_BC_0w=34.535u l=2uMMEA_BF_0w=5u l=2uMMEA_BO_0w=34.535u l=2uMMEA_BP_0w=6.31u l=2uMMRA_1_0w=86.42u l=0.7uMMRA_2_0w=86.42u l=0.7uMMRA_3_0w=20u l=1uMMRA_4_0w=20u l=1uMMRA_5_0w=37.76u l=2.645uMMRA_B0_0w=12u l=2uMMRA_BC_0w=8.315u l=2uMMRA_BO_0w=4u l=2uMMRA_BP_0w=10.845u l=2uXMMP_bank1XXC1_bank2XXCRAC_bank3XXC_LPF_bank4 - diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml index 7a072c2e80f246b49d37d40fa289a34c398ea03c..f728646e44665a3ee437679c0396deff8bff7704 100644 --- a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml @@ -4,13 +4,6 @@ title = "Divider-Biased NMOS Source Follower" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "93923bd3bcc77f6f7474c4088fb7b38c545be209e635f82c9c105ef76fb41ad1" - [[assets]] path = "reference/ldo_006_stub.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/schematic.svg deleted file mode 100644 index 52253ac7ef2948f4244546d5ffbfb3dda77ddbe8..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_006_stub{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_006_stub","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["ldo_006_stub"],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":4},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_006_stub"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_006_stub/design/ldo_006_stub.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.ldo_006_stubR1_seg1vrefR2_seg1vssvddvoutvssldo_006_stubR1_0ppolyf_u_1kw=1u l=48.44uR1_1ppolyf_u_1kw=1u l=48.44uR2_0ppolyf_u_1kw=1u l=48.44uR2_1ppolyf_u_1kw=1u l=48.44uResistor substrates: vssMM1_0nfet_03v3w=50u l=0.5u - diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml index c5b33b1ef56fb75d519dd6f65ef69445cd792e8e..0ca31618adfe1130314157cdd97ec2123f52d12f 100644 --- a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 11 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "d9f7de438d58cc73190744f4732f9cb7643fbb467b53612897cf1f1523aae638" - [[assets]] path = "reference/ldo_007_pmos.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/schematic.svg deleted file mode 100644 index 30695360c872cdee2da107db725f27a921a4c54b..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_007_pmos{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.ldo_007_pmos","source_netlist":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["ldo_007_pmos","MMP_bank1_page1","MMP_bank1_page2","MMP_bank1_page3","MMP_bank1","XCFF_bank2_page1","XCFF_bank2_page2","XCFF_bank2","XRZ_bank3"],"banks":[{"name":"MMP_bank1","devices":140,"source_references":["MMP_0","MMP_1","MMP_2","MMP_3","MMP_4","MMP_5","MMP_6","MMP_7","MMP_8","MMP_9","MMP_10","MMP_11","MMP_12","MMP_13","MMP_14","MMP_15","MMP_16","MMP_17","MMP_18","MMP_19","MMP_20","MMP_21","MMP_22","MMP_23","MMP_24","MMP_25","MMP_26","MMP_27","MMP_28","MMP_29","MMP_30","MMP_31","MMP_32","MMP_33","MMP_34","MMP_35","MMP_36","MMP_37","MMP_38","MMP_39","MMP_40","MMP_41","MMP_42","MMP_43","MMP_44","MMP_45","MMP_46","MMP_47","MMP_48","MMP_49","MMP_50","MMP_51","MMP_52","MMP_53","MMP_54","MMP_55","MMP_56","MMP_57","MMP_58","MMP_59","MMP_60","MMP_61","MMP_62","MMP_63","MMP_64","MMP_65","MMP_66","MMP_67","MMP_68","MMP_69","MMP_70","MMP_71","MMP_72","MMP_73","MMP_74","MMP_75","MMP_76","MMP_77","MMP_78","MMP_79","MMP_80","MMP_81","MMP_82","MMP_83","MMP_84","MMP_85","MMP_86","MMP_87","MMP_88","MMP_89","MMP_90","MMP_91","MMP_92","MMP_93","MMP_94","MMP_95","MMP_96","MMP_97","MMP_98","MMP_99","MMP_100","MMP_101","MMP_102","MMP_103","MMP_104","MMP_105","MMP_106","MMP_107","MMP_108","MMP_109","MMP_110","MMP_111","MMP_112","MMP_113","MMP_114","MMP_115","MMP_116","MMP_117","MMP_118","MMP_119","MMP_120","MMP_121","MMP_122","MMP_123","MMP_124","MMP_125","MMP_126","MMP_127","MMP_128","MMP_129","MMP_130","MMP_131","MMP_132","MMP_133","MMP_134","MMP_135","MMP_136","MMP_137","MMP_138","MMP_139"]},{"name":"XCFF_bank2","devices":75,"source_references":["CFF_0","CFF_1","CFF_2","CFF_3","CFF_4","CFF_5","CFF_6","CFF_7","CFF_8","CFF_9","CFF_10","CFF_11","CFF_12","CFF_13","CFF_14","CFF_15","CFF_16","CFF_17","CFF_18","CFF_19","CFF_20","CFF_21","CFF_22","CFF_23","CFF_24","CFF_25","CFF_26","CFF_27","CFF_28","CFF_29","CFF_30","CFF_31","CFF_32","CFF_33","CFF_34","CFF_35","CFF_36","CFF_37","CFF_38","CFF_39","CFF_40","CFF_41","CFF_42","CFF_43","CFF_44","CFF_45","CFF_46","CFF_47","CFF_48","CFF_49","CFF_50","CFF_51","CFF_52","CFF_53","CFF_54","CFF_55","CFF_56","CFF_57","CFF_58","CFF_59","CFF_60","CFF_61","CFF_62","CFF_63","CFF_64","CFF_65","CFF_66","CFF_67","CFF_68","CFF_69","CFF_70","CFF_71","CFF_72","CFF_73","CFF_74"]},{"name":"XRZ_bank3","devices":12,"source_references":["RZ_0","RZ_1","RZ_2","RZ_3","RZ_4","RZ_5","RZ_6","RZ_7","RZ_8","RZ_9","RZ_10","RZ_11"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":14},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_007_pmos"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/design/ldo_007_pmos.icproj.json"}}Main-sheet overview; 8 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_007_pmosvoutfbvssnczegatevddvoutegatevssvoutvssvoutvddnoutmegatefbebiasvddvoutvssebiasvrefPMOS LDO with feedforward compensationError amplifier → 140-unit pass array → regulated outputError amplifier and biasMM3_025/0.5MM4_025/0.5MM1_016/0.5MM2_016/0.5MM5_048/0.5MM6_048/0.5Pass device and outputMMP bank · 140 parallel PMOS unitsXMMP_bank1Feedback dividerR1_0 5 kΩR2_0 35 kΩFeedforward capacitor arrayXXCFF_bank2 · 60 pFSeries RZ / CC compensationXXRZ_bank3 · 12 parallel RZ unitsCC_0 0.05 pF - diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml index d0f55e6d11e32581746aeb0d4271dc2e7fe11aa9..91d5a3440028713ec65aae80a6fcde9a956f0637 100644 --- a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml @@ -4,13 +4,6 @@ title = "Passive Resistive Common-Mode Averager" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "703591b84841d3458b620ba02fd03e8bc1bd7cfd37400a007626fac3733e5694" - [[assets]] path = "reference/sup_001_vcm_detector.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/schematic.svg deleted file mode 100644 index 956050df4a93ebdfa963c0b480a182a3386b1a26..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -sup_001_vcm_detector{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.sup_001_vcm_detector","source_netlist":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["sup_001_vcm_detector","XRMN_bank1","XRMP_bank2"],"banks":[{"name":"XRMN_bank1","devices":20,"source_references":["RMN_0","RMN_1","RMN_2","RMN_3","RMN_4","RMN_5","RMN_6","RMN_7","RMN_8","RMN_9","RMN_10","RMN_11","RMN_12","RMN_13","RMN_14","RMN_15","RMN_16","RMN_17","RMN_18","RMN_19"]},{"name":"XRMP_bank2","devices":20,"source_references":["RMP_0","RMP_1","RMP_2","RMP_3","RMP_4","RMP_5","RMP_6","RMP_7","RMP_8","RMP_9","RMP_10","RMP_11","RMP_12","RMP_13","RMP_14","RMP_15","RMP_16","RMP_17","RMP_18","RMP_19"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":40},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["sup_001_vcm_detector"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/design/sup_001_vcm_detector.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.sup_001_vcm_detectorvcm_outvinnvssvcm_outvinpvssvcm_outvinpvinnvsssup_001_vcm_detectorN-side resistor bankP-side resistor bank - diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml index ddda1cf89ce7294c64ab2ac8383b1895cdf39d32..c8c8176ecfab975d6b8dff821363f5414a5ff008 100644 --- a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml @@ -4,13 +4,6 @@ title = "Two-NMOS Temperature-Response Core" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "d8b1096d0e2149bcfac54925a1cb7326c5ac9541abb247623cbbcd745e770037" - [[assets]] path = "reference/tsn_001_ptat_2t.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/schematic.svg deleted file mode 100644 index 39b176ced052aac3728b8848a5eaece7fc7987b4..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -tsn_001_ptat_2t{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.tsn_001_ptat_2t","source_netlist":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["tsn_001_ptat_2t","MM0_bank1","MM1_bank2"],"banks":[{"name":"MM0_bank1","devices":8,"source_references":["MM0_0","MM0_1","MM0_2","MM0_3","MM0_4","MM0_5","MM0_6","MM0_7"]},{"name":"MM1_bank2","devices":8,"source_references":["MM1_0","MM1_1","MM1_2","MM1_3","MM1_4","MM1_5","MM1_6","MM1_7"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["tsn_001_ptat_2t"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/design/tsn_001_ptat_2t.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.tsn_001_ptat_2tvoutvssvddvoutvssvddvoutvsstsn_001_ptat_2tMM0 arrayMM1 array - diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml index f99c9e3e84b23ec17d5571de46efb76cfdfa01e2..46fca6467a51e13368da4db28d123ea3fed628b5 100644 --- a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 14 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "687963e68c60fddd31fc77ef147529b2a268388a6e57c7313afefcac8ecb510e" - [[assets]] path = "reference/tsn_002_ptat_classic.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/schematic.svg deleted file mode 100644 index bb071e41d8025c18116f6ae25249b0d77f907303..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -tsn_002_ptat_classic{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.tsn_002_ptat_classic","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["tsn_002_ptat_classic"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":1},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["tsn_002_ptat_classic"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/design/tsn_002_ptat_classic.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.tsn_002_ptat_classicvssvddnet1startupvddvmirnet1vddvoutvsstsn_002_ptat_classicgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXM32/1XM42/1MM08/1XM12/1XR0W/L 2/40P bulk → vddMM0: B → voutXM1: B → vssR substrate → vssXSTARTP0.42/20XINJECT0.42/1XSTARTN2/0.28P bulk → vddN bulk → vssModels: ppolyf_u_1k · nfet_03v3_dn · nfet_03v3 · pfet_03v3 - diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/testbench.spice b/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/testbench.spice deleted file mode 100644 index 0c15eae8de85574105fe2b474bc668ebff1daa3f..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/testbench.spice +++ /dev/null @@ -1,47 +0,0 @@ -* Layout-Bench self-starting PTAT characterization. SPDX-License-Identifier: MIT -.include support/models.spice -.include dut.spice -.include parameters.spice -.temp {temperature_c} -.option method=gear maxord=2 -VDD vdd 0 DC {supply_v} PWL(0 0 {rise_s} {supply_v}) -CL vout 0 100f -XDUT vdd vout 0 tsn_002_ptat_classic -.save v(vdd) v(vout) i(vdd) -.control -set noaskquit -set numdgt=12 -op -let output_v=v(vout) -let power_w=-v(vdd)*i(vdd) -print output_v power_w -write op.raw all -dc temp -20 100 1 -let vv=v(vout) -let pp=-v(vdd)*i(vdd) -meas dc cold_v find vv at=-20 -meas dc hot_v find vv at=100 -let slope_v_per_c=(hot_v-cold_v)/120 -let error_v=abs(vv-(cold_v+slope_v_per_c*vector(length(vv)))) -meas dc curvature_v max error_v -let local_slope=deriv(vv) -meas dc minimum_slope min local_slope -meas dc maximum_slope max local_slope -meas dc peak_power_w max pp -print slope_v_per_c -write temperature.raw all -reset -tran 1n 100u 0 1n uic -let vv=v(vout) -let error=abs(vv-op1.output_v) -meas tran startup_error_v max error from=90u to=100u -meas tran late_min min vv from=90u to=100u -meas tran late_max max vv from=90u to=100u -let ripple_v=late_max-late_min -let pp=-v(vdd)*i(vdd) -meas tran final_power_w avg pp from=90u to=100u -print ripple_v -write startup.raw all -quit -.endc -.end diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml index d6b74a3a30b8b5237e9bbdcd8fa96084de43ccab..aa0a91df544e54fd52550814f61cb5211629f8f3 100644 --- a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml +++ b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml @@ -4,13 +4,6 @@ title = "Four-Transistor Positive-Temperature-Slope Core" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "9004de0d5b096f10ac99606f6e64326226593c1dde3f1eb07e1266feb2658501" - [[assets]] path = "reference/tsn_003_ptat_4t_xcoupled.gds" role = "physical-witness" diff --git a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/schematic.svg b/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/schematic.svg deleted file mode 100644 index 8eb8c3f29aeb6ca003ac1bf822fdb644c019cbb3..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -tsn_003_ptat_4t_xcoupled{"format":"iclayout-schematic","case_id":"gf180mcuD.analog-db.tsn_003_ptat_4t_xcoupled","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/analog-db/","sheets":["tsn_003_ptat_4t_xcoupled"],"banks":[],"source_netlist":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["tsn_003_ptat_4t_xcoupled"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/design/tsn_003_ptat_4t_xcoupled.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.tsn_003_ptat_4t_xcouplednavddvoutvsstsn_003_ptat_4t_xcoupledgf180mcuD · analog-db | W/L in µm · display rounded to 3 significant figuresXM32/3XM42/3XM04/3XM11/3P bulk → vddN bulk → vssModels: nfet_03v3 · pfet_03v3 - diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml index a8b1ec40462a3c73eae4eb19c320f72f42509444..7e3625012fecb530d48a97df3f7e8dc1b447fe8a 100644 --- a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml +++ b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 16 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "6607c242e01fc25284f56040628a6910ef5e237d9ecb60d7053c724be6c30d31" - [[assets]] path = "reference/r2r.gds" role = "reference" diff --git a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/schematic.svg b/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/schematic.svg deleted file mode 100644 index 10c3b22f954b9ec5026e693117aadec260aeb5d5..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -r2r{"format":"iclayout-schematic","case_id":"gf180mcuD.gf-r2r-dac.r2r","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/gf-r2r-dac/","sheets":["r2r"],"banks":[],"source_netlist":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":27},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["r2r"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/gf-r2r-dac/cases/r2r/design/r2r.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.r2rb0b1b2b3b4b5b6b7net2net1outnet5net7net9net11net13net15net16net4net6net8net10net12net14VGNDnet3VGNDr2rgf180mcuD · gf-r2r-dac | W/L in µm · display rounded to 3 significant figuresXR2W/L 2/50XR5W/L 2/50XR8W/L 2/50XR11W/L 2/50XR14W/L 2/50XR17W/L 2/50XR20W/L 2/50XR23W/L 2/50XR1W/L 2/50XR7W/L 2/50XR10W/L 2/50XR13W/L 2/50XR16W/L 2/50XR19W/L 2/50XR22W/L 2/50XR25W/L 2/50XR6W/L 2/50XR9W/L 2/50XR12W/L 2/50XR15W/L 2/50XR18W/L 2/50XR21W/L 2/50XR24W/L 2/50XR3W/L 2/50XR4W/L 2/50XR26W/L 2/50XR27W/L 2/50 - diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml index d79ed737585abb5ef427e07737e91ce33d43821b..fe871f49e02397e920b9ea4d65705871e8dee304 100644 --- a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml +++ b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 9 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "9e2d2c2f33145c3fc160880f069834e396b5f3fc8c90d97570ebfaf265aa9c67" - [[assets]] path = "reference/vco.gds" role = "reference" diff --git a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/schematic.svg b/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/schematic.svg deleted file mode 100644 index c0ff01305412839fa88342347271fb5182408856..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -vco{"format":"iclayout-schematic","case_id":"gf180mcuD.tt_tnt_gf_vco.vco","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/tt_tnt_gf_vco/","sheets":["vco","vco_dly","vco_out_p"],"banks":[],"source_netlist":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["The exported SVG shows the editable project's main sheet; child-cell transistor detail remains on its project sheets."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["vco"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/design/vco.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.vcoGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nbiasGNDVDDin_pin_nout_pout_nGNDVDDin_pin_nout_pout_ns0_ps0_ps0_ns0_ns1_ps1_ps1_ns2_ps2_ns3_ps3_ps3_nGNDGNDGNDGNDVDDbiasbiasbiasbiasbiasnet1s2_ps2_ns0_ps0_nGNDGNDVDDGNDVDDctrlout_0out_90out_180out_270vcogf180mcuD · tt_tnt_gf_vco | W/L in µm · display rounded to 3 significant figures01 Quadrature ringx1vco_dlyx2vco_dlyx4vco_dlyx3vco_dly02 Control-to-biasXM16/0.5 NF=2XM22/0.28 NF=2XM32/0.5 NF=2Bulk ties: PMOS → VDD · NMOS → GND03 Phase output buffersx5vco_out_px6vco_out_p - diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml index 3618d72198a66f18ad2acde73071fe390d2603db..48eefa14694a0d532ce463f04dda4c4f96d84dc6 100644 --- a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml +++ b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 17 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "cc82ad15dde6c3790aa2277e0b0c16487a74bfc864a207fa605cb022e15c4964" - [[assets]] path = "reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds" role = "reference" diff --git a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/schematic.svg b/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/schematic.svg deleted file mode 100644 index b119aa29ba11cc51e281c402ba9905fde8c14a1f..0000000000000000000000000000000000000000 --- a/tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -scan_dff{"format":"iclayout-schematic","case_id":"gf180mcuD.voidwalkers-scandff.scan_dff","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/gf180mcuD/voidwalkers-scandff/","sheets":["gf180mcu_voidwalkers_sc_sdffrnq_4","d_flip_flop_r","mux_toplevel_nobuffer","mux_tg","mux_inverter"],"banks":[],"source_netlist":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","PROBE[n] node names are retained; export verification uses the editor Spectre syntax encoder because its ngspice encoder rejects brackets. No Spectre simulator is required or used."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["gf180mcu_voidwalkers_sc_sdffrnq_4"],"scope":"main-sheet","editable_project":"tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/design/scan_dff.icproj.json"}}Main-sheet overview; 4 child sheets are available in the editable .icproj.json project. Equal net labels connect.gf180mcu_voidwalkers_sc_sdffrnq_4VDDVSSQDATACLKRNvddINPUT_1vssoutINPUT_2SELECTORVDDnet1SVDDQBCLKARNVSSscan_dffgf180mcuD · voidwalkers-scandff | W/L in µm · display rounded to 3 significant figuresx1mux_toplevel_nobufferx2d_flip_flop_r - diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml index 961ff39bcee3271f52ce368886e8456f0dc5162c..3afd76acd0a1906400ee2f0d55afca98b9c78b94 100644 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml @@ -4,13 +4,6 @@ title = "IHP AnalogAcademy comparator" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "cfc9095bb59e3408eab339880f64e488005f2861c257ea6ee942ef46a0aa85de" - [[assets]] path = "reference/DIFF_COMPARATOR.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/schematic.svg b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/schematic.svg deleted file mode 100644 index 5ed1e7c7f3b01c41a159bd40d043a157d42f3752..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -comparator{"format":"iclayout-schematic","case_id":"module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/IHP-AnalogAcademy/","sheets":["DIFF_COMPARATOR"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["DIFF_COMPARATOR"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/design/comparator.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.DIFF_COMPARATORvbiasvddv-v+net4net1clknet2net3gndout-net2vddout+net3gndgndvddwellgndsubcomparatorihp-sg13g2 · IHP-AnalogAcademy | W/L in µm · display rounded to 3 significant figuresMM918/0.3MM1318/0.3MM18/0.2 ×4MM28/0.2 ×4MM84/0.2MM64/0.2MM74/0.2MM104/0.2MM48/0.2MM58/0.2MM124/0.2MM114/0.2MM34/0.2 ×4RR1A=15.4 µm²RR2A=11.4 µm² - diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml index 1999590173c2499f486141cbd2cf147bbf3f1346..a3b5cc04c837068dce3981cffdcb2b891f5bdbaf 100644 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml @@ -4,13 +4,6 @@ title = "IHP AnalogAcademy full_OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "d0ffea6b17b397105057f93491c5f44dce93f8e3f7723c7202cd403569a5fd05" - [[assets]] path = "reference/two_stage_OTA_layout.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/schematic.svg b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/schematic.svg deleted file mode 100644 index 18f1bb85681515c4c8ea86daed5f81f64d316567..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -full_OTA{"format":"iclayout-schematic","case_id":"module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/IHP-AnalogAcademy/","sheets":["two_stage_OTA_layout"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["two_stage_OTA_layout"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/design/full_OTA.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.two_stage_OTA_layoutvssvdddn4ioutvoutdn4dn3dn2vddbulkbulk1bulk4vssbulk2vddioutvddv-v+dn4vssdn2dn3full_OTAihp-sg13g2 · IHP-AnalogAcademy | W/L in µm · display rounded to 3 significant figuresMM75.3/1.95MM13.64/3.7 ×2MM23.64/3.7 ×2MM30.72/9.75MM40.72/9.75MM7: B → bulk1MM1, MM2: B → bulkMM975/2.08MM575/2.08CC222.3/22.3MM628.8/9.75MM83.64/3.7 ×2MM103.64/3.7 ×2MM153.64/3.7 ×2MM163.64/3.7 ×2RR1A=28.1 µm²RR3A=6.96 µm²RR5A=26.8 µm²RR2A=8.56 µm²RR4A=30.3 µm² - diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml index e05f4a235b92669c7a2556fe6e3a28538ba9efb9..4d88a1f039395c9f61551724ea5c93c1f8705d99 100644 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml @@ -4,13 +4,6 @@ title = "IHP AnalogAcademy input_pair" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "1d79d6b9e0810b86b030f483c69745ef084caf776a9fc1670b627162b8022b53" - [[assets]] path = "reference/input_common_centroid.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/schematic.svg b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/schematic.svg deleted file mode 100644 index 2f66491cc84fb7ef3c502d50049de86003477c80..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -input_pair{"format":"iclayout-schematic","case_id":"module_1_bandgap_reference.part_3_layout.OTA_layout.input_pair","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/IHP-AnalogAcademy/","sheets":["input_common_centroid"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["input_common_centroid"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/design/input_pair.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.input_common_centroiddn4dn3tailvddvddbulkdn3v-dn4v+tailinput_pairihp-sg13g2 · IHP-AnalogAcademy | W/L in µm · display rounded to 3 significant figuresMM13.64/3.7 ×2MM23.64/3.7 ×2MM83.64/3.7 ×2MM103.64/3.7 ×2MM153.64/3.7 ×2MM163.64/3.7 ×2RR1A=442 µm² - diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml index 9ef4ff585aa17b26ff018408dd7f4ce446b25976..46dfd1d9456f9588aad789634009295d6ebf1073 100644 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml +++ b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml @@ -4,13 +4,6 @@ title = "IHP AnalogAcademy output_stage" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "a222ca439e61eb4ffe4f5f25b56e7f0d2d68236645ecc284c85941c824b0af50" - [[assets]] path = "reference/output_stage.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/schematic.svg b/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/schematic.svg deleted file mode 100644 index a3088c5a0442dddc11341ec6b806c2003734f668..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -output_stage{"format":"iclayout-schematic","case_id":"module_1_bandgap_reference.part_3_layout.OTA_layout.output_stage","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/IHP-AnalogAcademy/","sheets":["output_stage"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["output_stage"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/design/output_stage.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.output_stagebulk2vddbulk4vssvdddn4ioutvoutvssoutput_stageihp-sg13g2 · IHP-AnalogAcademy | W/L in µm · display rounded to 3 significant figuresMM975/2.08MM575/2.08CC222.3/22.3MM628.8/9.75RR4A=30.3 µm²RR5A=26.8 µm² - diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml b/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml index 7c8d1f3bd47ea50aeb6a2f3b7ab8a42cfef11393..23a626173d1e74c1f0ea332efd57fd237e4496ba 100644 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml +++ b/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml @@ -4,13 +4,6 @@ title = "TO_Apr2025 160-derived four-stage LNA at 100 MHz" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "3efe6d2ab9b53c7ed1d5c9647466b0447e0c2c3e41a6c864e00b3d8c686b7c5d" - [[assets]] path = "reference/LNA160_FOUR_STAGE.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/schematic.svg b/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/schematic.svg deleted file mode 100644 index ae3811c23d13a02f8e7a7992b966fceb0504a48e..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -160GHz_LNA{"format":"iclayout-schematic","case_id":"TO_Apr2025.160GHz_LNA","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/TO_Apr2025/","sheets":["LNA160_FOUR_STAGE"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":15},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["LNA160_FOUR_STAGE"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/design/160GHz_LNA.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.LNA160_FOUR_STAGEINOUTE1E2E3E4N1N2N3VDDVSSN1N2N3VBIASVSSSUBSTRATE160GHz_LNAihp-sg13g2 · TO_Apr2025 | W/L in µm · display rounded to 3 significant figuresRCL12/20RCL22/20RCL32/20RCL42/20QQ1WE/LE 0.07/0.9QQ2WE/LE 0.07/0.9QQ3WE/LE 0.07/0.9QQ4WE/LE 0.07/0.9REL14/20REL24/20REL34/20REL44/20RBIAS21/4RBIAS31/4RBIAS41/4RSUBA=4 µm² - diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml b/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml index 12677174b0cb07fc3c81c3a6431bb36d31a24e52..921d91c1cb38c0afbaa5384b9cfa07d92689020c 100644 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml +++ b/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml @@ -4,13 +4,6 @@ title = "TO_Apr2025 40 GHz low-noise single-ended TIA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "9d8bc219eccf04d45f518366d400222c9c33b1b78663e09c1aa846c60f9e688f" - [[assets]] path = "reference/FDM_QNC_00_LN_TIA.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/schematic.svg b/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/schematic.svg deleted file mode 100644 index a983ad3b72eb30592ac4fda37cbe47c912ffda1f..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -40_GHZ_LOW_NOISE_TIA{"format":"iclayout-schematic","case_id":"TO_Apr2025.40_GHZ_LOW_NOISE_TIA","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/TO_Apr2025/","sheets":["FDM_QNC_00_LN_TIA"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":8},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["FDM_QNC_00_LN_TIA"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/design/40_GHZ_LOW_NOISE_TIA.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.FDM_QNC_00_LN_TIAvcc3net2VSSRFoutnet3vcc1vcc2vcc3VSSVSSSUBSTRATEvcc1RFinVSSnet1vcc2net1RFinVSSnet240_GHZ_LOW_NOISE_TIAihp-sg13g2 · TO_Apr2025 | W/L in µm · display rounded to 3 significant figuresRRC18/4.5QQ1WE/LE 0.07/0.9 NX=5QQ2WE/LE 0.07/0.9 NX=10RRF2/6.5RRE23/6RRC34/14.5QQ3WE/LE 0.07/0.9 NX=10RRE34/3CC130/60 ×2CC230/60 ×2CC330/60 ×2RPTAPA=25 µm² - diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml b/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml index 1d4597bd6daf0886e69b1d949e87f1845d170afb..3196653222ec55dd170009da74c89ef15db4f7ff 100644 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml +++ b/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml @@ -4,13 +4,6 @@ title = "TO_Apr2025 97-derived multi-stage linear TIA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "f6f8324cd36acaac731164356ef72d80d3159bb1b4b750b14a3b0314229c0d12" - [[assets]] path = "reference/FMD_QNC_01_LIN_TIA.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/schematic.svg b/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/schematic.svg deleted file mode 100644 index 4a52567aeb322d7c825d42ec82692396d9bb4252..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -97_GHZ_LINEAR_TIA{"format":"iclayout-schematic","case_id":"TO_Apr2025.97_GHZ_LINEAR_TIA","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/TO_Apr2025/","sheets":["FMD_QNC_01_LIN_TIA"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":10},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["FMD_QNC_01_LIN_TIA"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/design/97_GHZ_LINEAR_TIA.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.FMD_QNC_01_LIN_TIAVCC3VCC2VSS$26$22$24RFOUTVCC1VCC2VCC3VSSVSS$1VCC1RFINVSS$10VCC2$10RFINVSS$2297_GHZ_LINEAR_TIAihp-sg13g2 · TO_Apr2025 | W/L in µm · display rounded to 3 significant figuresR$78/4.5Q$1WE/LE 0.07/0.9 NX=5Q$2WE/LE 0.07/0.9 NX=10R$82/6.5R$93/6R$64/14.5Q$4WE/LE 0.07/0.9 NX=5Q$3WE/LE 0.07/0.9 NX=10R$102/6.5R$54/3C$1130/60 ×2C$1330/60 ×2C$1530/60 ×2R$17A=4 µm² - diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml b/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml index b5b0b8156315b5a82a5cc9055b014842d19d55c5..08520befbeaf487bd687253b6d1db675ce9e1bd7 100644 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml +++ b/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml @@ -4,13 +4,6 @@ title = "Two-stage SiGe HBT TIA with nominal AC/DC requirements" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "5da14439984543b4e94085678796cca312b870ab4e582e6adb7adc02f4102090" - [[assets]] path = "reference/FMD_QNC_03a_TIA_1.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/schematic.svg b/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/schematic.svg deleted file mode 100644 index a865f110a7c1642c45336d0776a1020602ad002a..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -DC_to_130_GHz_TIA.design_1{"format":"iclayout-schematic","case_id":"TO_Apr2025.DC_to_130_GHz_TIA.design_1","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/TO_Apr2025/","sheets":["FMD_QNC_03a_TIA_1"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":5},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["FMD_QNC_03a_TIA_1"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/design/DC_to_130_GHz_TIA.design_1.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.FMD_QNC_03a_TIA_1VCC2VVCC2V1VEEVEEVCC2VVEEINPUTDN1VCC2V1DN1VEEOUTPUTDC_to_130_GHz_TIA.design_1ihp-sg13g2 · TO_Apr2025 | W/L in µm · display rounded to 3 significant figuresRRC115/4QQ1WE/LE 0.07/0.9 NX=5RRF29/6.3RRC211.5/2QQ2WE/LE 0.07/0.9 NX=4CC130/30CC230/30RRTAPA=3.65 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml index d43c7ec27578c7ff3c1e50d3f7f604999e0ff68b..420c40d5c23351163d7bcd512a781b809bb079fe 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml @@ -4,13 +4,6 @@ title = "CMOS Inverter Threshold Core" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "94c6b23ff178b3b7e18ecf9a0eed0734f0fbea0f84614a45bc4f57c8acf88643" - [[assets]] path = "reference/adc_001_inv1b.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "89ac70eab03942a80bef149eab104bc1c59bf84dde79fd0b873f0974d4505bc3" +sha256 = "eaf181c4dcf4c09f116f3bbb7dddd860d709265ef8ef47eb6af0c79eb76d66ac" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "adc_001_inv1b" -sha256 = "ac17dacdee7c373b47d4038a7318a7b0fedc024031b06f93011f8eaab684caf4" +sha256 = "abab97e938d458243277604a5dec9c2ac7a9648acc260d5012da4d4564b3c0ec" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "5b7039e6399c1336c9ed31405b0176f512f2981b51e1fa8ffae36fa8d51af7aa" +sha256 = "ee03d6f36d20c2d937b292d0246c72585e9c32999596a273f9782b3c9518aa08" [task.inputs.performance] path = "materials/testbench.spice" @@ -465,10 +458,10 @@ lower = 0.6 rationale = "The 1.2 V inverter threshold core requires at least the declared 0.6 V DC output swing to establish a meaningful logic transition; unique switching and transient crossings are independently required by the fixture." [task.evaluation.pre_layout] -source_report_sha256 = "37eef824221b8062d8969766eadf779825de51cd9327d080ebfaf05ccb020c7a" +source_report_sha256 = "1be6dab2568545479f1bf125feeb6978d5b6fe4f0efeb650de79f47c2b6a3b07" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5d384a76e9c131bac2ca2ea8519a17d0769e9ef6e93bd9cad97f6294738568db\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -498,14 +491,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "7305f7b68fdb3c41a8e397a24b229aa79cd228e6d8e261654e9803d208ff84c0" -dut = "5b7039e6399c1336c9ed31405b0176f512f2981b51e1fa8ffae36fa8d51af7aa" +dut = "ee03d6f36d20c2d937b292d0246c72585e9c32999596a273f9782b3c9518aa08" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.delay_s] -value = 6.921866e-11 +value = 6.921838e-11 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 1.879725e-06 +value = 1.879766e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.swing_v] @@ -517,14 +510,9 @@ value = 0.6299057 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.transition_s] -value = 7.341807e-11 +value = 7.33987e-11 unit = "s" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "974317db1b6ce6abb38ea59ab7f85ae70b26e31d7cde0e156d5f881d5582fd2d" -dc = "81d88d3270a73f9d61c931227248a726fb3b5ab9b9c239f2f7d1127ba2a8534e" -transient = "971ff7139ce4033900cb0b29e158a07a65900b3e67c7ee842bf4b1f5b17ebd2a" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -564,7 +552,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl index 787c653c442bfdf09bdab5c8610e18743da62f83..85550cf7de7dc6a243b6bff6843e17b96711a95c 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl @@ -1,9 +1,6 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt adc_001_inv1b vdd vin vout vss -RT0 vss sub ptap1 A=4e-12 P=8e-6 -MMN vout vin vss sub sg13_lv_nmos w=1u l=0.13u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MMP vout vin vdd well_1 sg13_lv_pmos w=2.5u l=0.13u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MMN vout vin vss vss sg13_lv_nmos w=1u l=0.13u m=1 +MMP vout vin vdd vdd sg13_lv_pmos w=2.5u l=0.13u m=1 .ends adc_001_inv1b diff --git a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.spice index 0a5c00825bf5afc59e4261477a8bc15db1993ab8..fcb6affb119c8975b24dd974a2fadf35366123ae 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.spice @@ -1,9 +1,6 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt adc_001_inv1b vdd vin vout vss -XT0 vss sub ptap1 A=4e-12 P=8e-6 -XMN vout vin vss sub sg13_lv_nmos w=1u l=0.13u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XMP vout vin vdd well_1 sg13_lv_pmos w=2.5u l=0.13u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XMN vout vin vss vss sg13_lv_nmos w=1u l=0.13u m=1 +XMP vout vin vdd vdd sg13_lv_pmos w=2.5u l=0.13u m=1 .ends adc_001_inv1b diff --git a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/schematic.svg deleted file mode 100644 index 31813d4874bd55036b02c3c34c98da6985191466..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -adc_001_inv1b{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.adc_001_inv1b","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["adc_001_inv1b"],"banks":[],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; the editable project retains the original terminals and model bindings. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["adc_001_inv1b"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/design/adc_001_inv1b.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.adc_001_inv1bvoutvsssubvinsubvddwell_1voutwell_1vssvsssubvddvinadc_001_inv1bRT0ptap1A=4e-12 P=8e-6MMNsg13_lv_nmosw=1u l=0.13um=1RT1ntap1A=4e-12 P=8e-6MMPsg13_lv_pmosw=2.5u l=0.13um=1RTSUBptap1A=4e-12 P=8e-6 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md index f938d160bcf6a176ef8a2e9d12db49ef219aa128..cd6c913bdbc5169e95661984a0fc632fad0c630c 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md @@ -6,7 +6,7 @@ The fixed binding is a CMOS inverter: one 1/0.13 um NMOS and one 2.5/0.13 um PMO ## Inputs and Interface -`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (1.2 V rail), vin (gate input), vout (drain output), vss (return). +`materials/circuit.cdl` is the authoritative logical circuit netlist; `materials/circuit.spice` is the same compact-device circuit for simulation. `materials/testbench.spice` supplies the external fixture. Both source and extracted candidate use the exact same deck, bias, loads, excitation, initial-state procedure and measurement windows. Ordered ports: vdd (1.2 V rail), vin (gate input), vout (drain output), vss (return). ## Operating Conditions @@ -61,3 +61,5 @@ Inverter threshold element: switching threshold 25.5%; delay 34%; transition 12. Solve budget: **6 hours**. Discover tools and feedback through the runtime task, protocol and reviewed resource bundle. Explicitly submit `/workspace/output/final.gds` through the protocol; writing a file alone does not submit it. Reference assets and maintainer source records are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml index 31c958a14ac7cc287404cd2acb91292a8b0cd2bd..800ea2b8edd107185ddf63c83e1aeae777bfed22 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml @@ -4,13 +4,6 @@ title = "Five-Transistor OTA Core with Bias Mirror" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "c0bc0afe7c4392b11e3b1836cae47240e81826274c39c7d59ee00f9eb73a87c3" - [[assets]] path = "reference/amp_001_5t.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/schematic.svg deleted file mode 100644 index 13455af1a073af49c1e57593548d022c4df17046..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_001_5t{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_001_5t","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_001_5t"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_001_5t"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/design/amp_001_5t.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_001_5tvssibiasvsssubvddwelltailoutmvddvoutvinpvinnibiasvssamp_001_5tihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM310/7MM410/7MM110/10MM210/10MM53.8/1P bulk → wellN bulk → subMM63.8/1N bulk → subRR1A=192 µm²RR2A=52 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml index 2fb89c387039e6d26539669100fc330afd956a22..a5a48d1e0fd3bf0a6bb1f68b63d6e42c1cab814c 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml @@ -4,13 +4,6 @@ title = "Current-Buffer and Active-Feedforward OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "5b5d6437261a850f444341f917763ee4e626f0ca646d906169d2a6ff91b7bde6" - [[assets]] path = "reference/amp_002_alfio_raffc.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/schematic.svg deleted file mode 100644 index da348f651204c78651f992654c667d829805f79b..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_002_alfio_raffc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_002_alfio_raffc","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_002_alfio_raffc"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_002_alfio_raffc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/design/amp_002_alfio_raffc.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_002_alfio_raffcvddnet050net31vb3vb4vssdm_2net063voutnnet013net050net1vssvddnet043net050net013dm_1net54net56net1vddvb4vb3net31vddnet050net013net063voutnet31well_net31vddwell_vddvsssubvssvddvinnvinpvoutnet1amp_002_alfio_raffcihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM55.74/6.12 ×8MM65.74/6.12 ×8MM810/3.15 ×3MM910/3.15 ×3MM158/1 ×2MM168/1 ×2MM192/8 ×8MM202/8 ×8MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subMM76.24/0.4MM05.74/6.12MM1110/0.8 ×2MM219/2 ×6MM229/2 ×6P bulk → well_vddN bulk → subMM15.74/6.12MM107.2/1MM25.74/6.12MM35.74/6.12MM122/8 ×4MM592/8 ×8MM132/8 ×4MM142/8MM172/8 ×4MM182/8 ×4P bulk → well_vddN bulk → subMM45.74/6.12 ×2P bulk → well_vddCC0_043.5/43.5CC0_143.5/43.5CC0_243.5/43.5CC1_036.5/36.5RRtap_net31A=110 µm²RRtap_vddA=595 µm²RRptapA=2130 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml index 38e92ed3643a2265d49c60ac77298dd184df5793..d6903e20faf1ba8cbf4eecaf5fc5ac2c63e6afaa 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml @@ -4,13 +4,6 @@ title = "Single-Capacitor Three-Stage Feedforward OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "d4387977bdd4e3bb1da3ac1cfc994e720dad199e2a58444823c6db30bbf65ed0" - [[assets]] path = "reference/amp_003_fan_smc.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/schematic.svg deleted file mode 100644 index 6bb8630eb4092675fd6bdd811052615d630fb840..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_003_fan_smc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_003_fan_smc","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_003_fan_smc"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_003_fan_smc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/design/amp_003_fan_smc.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_003_fan_smcvddnet050net31vb3vb4vssdm_2net063voutnnet013net050vddnet049vssnet043dm_1net54net56vssvddvb4net013vb3net31vddnet050voutnet31well_net31vddwell_vddvsssubvssvddvinnvinpvoutnet013amp_003_fan_smcihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM51/1 ×16MM61/1 ×16MM81/1 ×4MM91/1 ×4MM151/1 ×16MM161/1 ×16MM191/1 ×32MM201/1 ×32MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subMM101/1 ×8MM71/1 ×16MM111/1 ×32MM211/1 ×4MM221/1 ×4MM231/1 ×16P bulk → well_vddN bulk → subMM01/1 ×16MM11/1 ×16MM21/1 ×16MM31/1 ×16MM121/1 ×16MM131/1 ×16MM141/1 ×4MM171/1 ×16MM181/1 ×16P bulk → well_vddN bulk → subMM41/1 ×64P bulk → well_vddCC0_040.8/40.8CC0_140.8/40.8RRtap_net31A=108 µm²RRtap_vddA=2650 µm²RRptapA=5160 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml index 2c6404aa0b2bc0bab8034a0c32d80aa15bc23825..223ec43c0368901f656a349f001665de97cd3c5d 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml @@ -4,13 +4,6 @@ title = "Current-Buffered Compensation OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "bcac1ee26f540a192fa7d7c4145de0074b719a50c389c18d9fd72856b31ed960" - [[assets]] path = "reference/amp_005_hoilee_affc.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/materials/schematic.svg deleted file mode 100644 index 3ef892717eb19608cf4c17fc17a27fab5bf21b3d..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_005_hoilee_affc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_005_hoilee_affc","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_005_hoilee_affc"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_005_hoilee_affc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/design/amp_005_hoilee_affc.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_005_hoilee_affcnet050vddnet31vb3vb4vssnet063dm_2voutnnet050net013net1vb4vddnet049vssnet043net050vddnet049vssdm_1net54net56vssvddvb4net013vb3net31net1vb4vssnet050vb3net3vddnet2net1net049voutnet31well_net31vddwell_vddvsssubvssvddvinnvinpvoutnet013amp_005_hoilee_affcihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM62.17/6.86 ×4MM52.17/6.86 ×4MM109.88/0.77 ×4MM99.88/0.77 ×4MM172.9/8.24 ×16MM162.9/8.24 ×16MM210.21/3.15 ×32MM200.21/3.15 ×32MM6, MM5: B → well_vddMM10, MM9: B → well_net31N bulk → subMM112.79/1.37 ×4MM72.17/6.86 ×4MM226.34/9.33 ×4MM236.34/9.33 ×4MM640.21/3.15 ×16P bulk → well_vddN bulk → subMM128.69/0.6 ×4MM252.71/3.98 ×4P bulk → well_vddN bulk → subMM02.17/6.86 ×4MM12.17/6.86 ×4MM22.17/6.86 ×4MM32.17/6.86 ×4MM130.21/3.15 ×16MM140.21/3.15 ×16MM150.21/3.15 ×4MM180.21/3.15 ×16MM190.21/3.15 ×16P bulk → well_vddN bulk → subMM42.17/6.86 ×8MM594.58/4.37 ×4MM624.58/4.37 ×4MM602.92/0.77 ×4MM632.92/0.77 ×4MM610.21/3.15 ×16P bulk → well_vddN bulk → subCC0_044.8/44.8CC0_144.8/44.8CC0_244.8/44.8CC0_344.8/44.8CC1_050/50CC1_150/50CC1_250/50RRtap_net31A=104 µm²RRtap_vddA=1170 µm²RRptapA=5360 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml index 9d41840407bc5e1bddcd11e1472e52b783da1edb..0301766d44c7898397d6d93cf9ec9596403bb361 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 15 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "c3985f6133a0714e5adb3d2fd19e81907e4117f653360210366cd6cfeaf2c7cc" - [[assets]] path = "reference/amp_006_leung_dfcfc1.gds" role = "physical-witness" @@ -29,13 +22,13 @@ environment = "ihp-sg13g2-amp_006_leung_dfcfc1-nominal-rc" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "5d75c246fb634c9ab6465d018cf54735300972c83783ffcd08a37216497c30af" +sha256 = "5b1f11471e149417968b7f50508e4b8578d8f31f3585bfd817be8043b8db218e" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_006_leung_dfcfc1" -sha256 = "0bfae437fa4eb43463b0ddab03b7d1c9edbe3d7f08fde84a418d30cb3cc137b2" +sha256 = "bd35a8a0dd5ae4b3b413ee2074eaa9fb35c8393daed8a1c38a55582d9dc10cc8" [task.inputs.performance] path = "materials/testbench.spice" @@ -45,7 +38,7 @@ sha256 = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +sha256 = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.constraints] quality = [ @@ -249,7 +242,7 @@ mode = "post_layout" method = "layout" area_metric = "functional_area" area_target = 34000.0 -rationale = "The eleven fixed MIM plates occupy 26941.7246 um2. A 34000 um2 integration budget allocates about 79% to those plates and the balance to enclosures, 675 MOS fingers, taps and routing; it is not a process minimum. Area carries 30%, 100 ppm step-referred DC accuracy 15%, the worst bilateral normalized response integral 20%, bandwidth 10%, phase-margin preservation 10%, sampled return distance 5%, large-signal step gain 5% and mean power 5%. First/final crossing diagnostics and fully settled recovery errors are retained without duplicate weight. The source and extracted tap representations differ, so the source DC offset is not used as a loose accuracy goal." +rationale = "The eleven fixed MIM plates occupy 26941.7246 um2. A 34000 um2 integration budget allocates about 79% to those plates and the balance to enclosures, 675 MOS fingers, taps and routing; it is not a process minimum. Area carries 30%, 100 ppm step-referred DC accuracy 15%, the worst bilateral normalized response integral 20%, bandwidth 10%, phase-margin preservation 10%, sampled return distance 5%, large-signal step gain 5% and mean power 5%. First/final crossing diagnostics and fully settled recovery errors are retained without duplicate weight. Source and extraction share logical body-net semantics" [task.evaluation.scoring.weights] functional_area = 0.3 @@ -709,7 +702,7 @@ rationale = "The absolute error, voltage span, charge magnitude or recovery devi [task.evaluation.metrics.quality_target] value = 2e-05 -rationale = "Allocate 100 ppm of the declared 200 mV step, or 20 uV, to deterministic DC tracking error. This is an offset budget, not a noise or mismatch claim; finite-tap source offset is not the application accuracy target." +rationale = "Allocate 100 ppm of the declared 200 mV step, or 20 uV, to deterministic DC tracking error. This is an offset budget, not a noise or mismatch claim; source offset is not the application accuracy target." [[task.evaluation.metrics]] id = "bias_v" @@ -1235,10 +1228,10 @@ lower = 0.0 rationale = "An integral of an absolute voltage deviation divided by a positive commanded step is nonnegative; slower responses remain valid and receive lower quality." [task.evaluation.pre_layout] -source_report_sha256 = "7dae5f39049f9dd5e853b4c60946804c16d3e03a66a316fde838b6eb8d0fa075" +source_report_sha256 = "2c4e76de70f753888228e1df2685012387df54986aa51783abab3764298f1756" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4256875a12feacdc7b1c992999ca2d58c01501a4bc6f5ac8e9a9fa379d26502b\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"9c8e241b41ff142ce2c7d7a2e0dbda51e242895245875192bbc4831cb3695ad6\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1287,86 +1280,86 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" -dut = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +dut = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 0.6685239941756 +value = 0.6685237750285 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dc_gain_db] -value = 95.37677 +value = 95.51132 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_phase_margin_deg] -value = 81.57097 +value = 81.62758 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_unity_hz] -value = 563634.8 +value = 529676.5 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.hf_gain_db] -value = -44.95624 +value = -72.17841 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0001198889 +value = 0.0001145178 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_return_distance] -value = 0.8477296228892 +value = 0.8431158612759 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_error_v] -value = 0.002811865074393 +value = 0.002777053659362 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.5028118650744 +value = 0.5027770536594 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.peak_v] -value = 0.7029789 +value = 0.7029336 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin_deg] -value = 81.57097 +value = 81.62758 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0001201182928964 +value = 0.0001147648164198 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_down_v] -value = 0.002831263 +value = 0.002819678 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_up_v] -value = 0.002978925 +value = 0.002933586 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.response_down_s] -value = 4.92535e-07 +value = 5.28972e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.response_up_s] -value = 4.75752e-07 +value = 5.11063e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_phase_excursion_deg] -value = 89.55649866733 +value = 89.55866784604 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_gain] -value = 1.00084 +value = 1.000783 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.trough_v] -value = 0.5028109 +value = 0.502777 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] -value = 563634.8 +value = 529676.5 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_1] @@ -1416,86 +1409,86 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" -dut = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +dut = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] -value = 0.6685239941756 +value = 0.6685237750285 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_gain_db] -value = 95.37677 +value = 95.51132 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_phase_margin_deg] -value = 81.24316 +value = 81.26741 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_unity_hz] -value = 567067.8 +value = 533180.8 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.hf_gain_db] -value = -47.4381 +value = -74.33259 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] -value = 0.0001198895 +value = 0.0001145181 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_return_distance] -value = 0.8326349735475 +value = 0.8276762374123 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_error_v] -value = 0.002811865074393 +value = 0.002777053659362 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] -value = 0.5028118650744 +value = 0.5027770536594 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.peak_v] -value = 0.7029789 +value = 0.7029336 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin_deg] -value = 81.24316 +value = 81.26741 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0001201182928964 +value = 0.0001147648164198 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_down_v] -value = 0.00283325 +value = 0.002823612 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_up_v] -value = 0.002978926 +value = 0.002933586 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.response_down_s] -value = 4.93032e-07 +value = 5.29548e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.response_up_s] -value = 4.76466e-07 +value = 5.11914e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.return_phase_excursion_deg] -value = 89.55662774377 +value = 89.55879497872 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_gain] -value = 1.00084 +value = 1.000783 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.trough_v] -value = 0.5028109 +value = 0.502777 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] -value = 567067.8 +value = 533180.8 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_2] @@ -1545,86 +1538,86 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" -dut = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +dut = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] -value = 0.6685239941756 +value = 0.6685237750285 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_gain_db] -value = 95.37677 +value = 95.51132 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_phase_margin_deg] -value = 80.55115 +value = 80.50366 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_unity_hz] -value = 574201.7 +value = 540479.9 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.hf_gain_db] -value = -50.95392 +value = -77.49558 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] -value = 0.0001198912 +value = 0.0001145189 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_return_distance] -value = 0.8047942997885 +value = 0.7992007945533 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_error_v] -value = 0.002811865074393 +value = 0.002777053659362 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] -value = 0.5028118650744 +value = 0.5027770536594 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.peak_v] -value = 0.7029789 +value = 0.7029336 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_margin_deg] -value = 80.55115 +value = 80.50366 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 0.0001201182928964 +value = 0.0001147648164198 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_down_v] -value = 0.002837292 +value = 0.002830988 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_up_v] -value = 0.002978926 +value = 0.002933587 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.response_down_s] -value = 4.94143e-07 +value = 5.30825e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.response_up_s] -value = 4.78061e-07 +value = 5.13796e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.return_phase_excursion_deg] -value = 89.55688609971 +value = 89.55904924155 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_gain] -value = 1.00084 +value = 1.000783 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.trough_v] -value = 0.5028109 +value = 0.502777 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.unity_hz] -value = 574201.7 +value = 540479.9 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_3] @@ -1674,86 +1667,86 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" -dut = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +dut = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.bias_v] -value = 0.6685244210154 +value = 0.6685241940802 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dc_gain_db] -value = 98.19628 +value = 98.54179 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_phase_margin_deg] -value = 81.93171 +value = 81.98093 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_unity_hz] -value = 546056.4 +value = 513704.5 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.hf_gain_db] -value = -43.18098 +value = -69.45896 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.mean_power_w] -value = 0.0001198889 +value = 0.0001145178 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_return_distance] -value = 0.8464209642001 +value = 0.8422382446636 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_error_v] -value = 0.002979975389359 +value = 0.002933579773495 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] -value = 0.7029799753894 +value = 0.7029335797735 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.peak_v] -value = 0.7029789 +value = 0.7029336 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.phase_margin_deg] -value = 81.93171 +value = 81.98093 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 0.0001197195064094 +value = 0.0001143276099613 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_down_v] -value = 0.002831263 +value = 0.002819678 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_up_v] -value = 0.002978925 +value = 0.002933586 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.response_down_s] -value = 4.92535e-07 +value = 5.28972e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.response_up_s] -value = 4.75752e-07 +value = 5.11063e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.return_phase_excursion_deg] -value = 89.62167955537 +value = 89.62823422074 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_gain] -value = 1.00084 +value = 1.000783 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.trough_v] -value = 0.5028109 +value = 0.502777 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.unity_hz] -value = 546056.4 +value = 513704.5 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_4] @@ -1803,86 +1796,86 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] deck = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" -dut = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +dut = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.bias_v] -value = 0.6685244210154 +value = 0.6685241940802 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.dc_gain_db] -value = 98.19628 +value = 98.54179 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_phase_margin_deg] -value = 81.6339 +value = 81.65287 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_unity_hz] -value = 549210.3 +value = 516942.5 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.hf_gain_db] -value = -45.65557 +value = -71.60502 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.mean_power_w] -value = 0.0001198895 +value = 0.0001145181 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.minimum_return_distance] -value = 0.8316701984842 +value = 0.8271808591781 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_error_v] -value = 0.002979975389359 +value = 0.002933579773495 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] -value = 0.7029799753894 +value = 0.7029335797735 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.peak_v] -value = 0.7029789 +value = 0.7029336 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.phase_margin_deg] -value = 81.6339 +value = 81.65287 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] -value = 0.0001197195064094 +value = 0.0001143276099613 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_down_v] -value = 0.00283325 +value = 0.002823612 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_up_v] -value = 0.002978926 +value = 0.002933586 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.response_down_s] -value = 4.93032e-07 +value = 5.29548e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.response_up_s] -value = 4.76466e-07 +value = 5.11914e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.return_phase_excursion_deg] -value = 89.62178745122 +value = 89.6283378172 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.step_gain] -value = 1.00084 +value = 1.000783 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.trough_v] -value = 0.5028109 +value = 0.502777 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.unity_hz] -value = 549210.3 +value = 516942.5 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_5] @@ -1932,86 +1925,86 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] deck = "eeb2bab7c4fd942e7c2e9825ac8ded28d181b8a8c67a8e6a21ddc20e207801ad" -dut = "1f8a4bfd42e6b2cfd6173e2d95b2bc970d67ea10a04b9ba99b15fd0d6d38fd20" +dut = "c8f461164e1aef84e48c608e9a738aab28f8820c9bbdf954d27352749f7efbe5" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.bias_v] -value = 0.6685244210154 +value = 0.6685241940802 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.dc_gain_db] -value = 98.19628 +value = 98.54179 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_phase_margin_deg] -value = 81.00659 +value = 80.9585 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_unity_hz] -value = 555759.1 +value = 523686.9 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.hf_gain_db] -value = -49.1641 +value = -74.7592 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.mean_power_w] -value = 0.0001198912 +value = 0.0001145189 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.minimum_return_distance] -value = 0.8048477669791 +value = 0.7996263489462 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_error_v] -value = 0.002979975389359 +value = 0.002933579773495 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_v] -value = 0.7029799753894 +value = 0.7029335797735 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.peak_v] -value = 0.7029789 +value = 0.7029336 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.phase_margin_deg] -value = 81.00659 +value = 80.9585 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.power_w] -value = 0.0001197195064094 +value = 0.0001143276099613 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.recovery_down_v] -value = 0.002837292 +value = 0.002830988 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.recovery_up_v] -value = 0.002978926 +value = 0.002933587 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.response_down_s] -value = 4.94143e-07 +value = 5.30825e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.response_up_s] -value = 4.78061e-07 +value = 5.13796e-07 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.return_phase_excursion_deg] -value = 89.62200383564 +value = 89.62854500798 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.step_gain] -value = 1.00084 +value = 1.000783 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.trough_v] -value = 0.5028109 +value = 0.502777 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.unity_hz] -value = 555759.1 +value = 523686.9 unit = "Hz" [toolchain.bindings] @@ -2053,7 +2046,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/input-pair-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl index d7d6cc695dd9c78dce3352513fe22d9938a85193..0e980a6b4bdda1511002010a0df778f523b1831d 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl @@ -1,524 +1,32 @@ -* Derived from analog-db amp_006_leung_dfcfc1, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified by Layout-Bench: MOS rounded to 10 nm; equivalent regrouping preserves total W and L; -* physical MIM arrays, explicit bias port and body contacts. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_006_leung_dfcfc1 vss vdd vinn vinp vout net013 -MM13 vb4 vb3 net54 sub sg13_lv_nmos w=7.1u l=7.02u m=8 -MM14 dm_1 vb3 net56 sub sg13_lv_nmos w=7.1u l=7.02u m=8 -MM15 vb3 vb3 vss sub sg13_lv_nmos w=7.1u l=7.02u m=2 -MM16 voutn vb3 dm_2 sub sg13_lv_nmos w=5.76u l=1.59u m=2 -MM17 net050 vb3 net063 sub sg13_lv_nmos w=5.76u l=1.59u m=2 -MM18 net54 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=8 -MM19 net56 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=8 -MM20 dm_2 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=16 -MM21 net063 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=16 -MM22 net043 net043 vss sub sg13_lv_nmos w=5.5u l=8.08u m=4 -MM23 net049 net043 vss sub sg13_lv_nmos w=5.5u l=8.08u m=4 -MM24 net1 net049 vss sub sg13_lv_nmos w=6.8u l=4.49u m=1 -MM25 vout net049 vss sub sg13_lv_nmos w=9.5u l=0.89u m=16 -MM10 net063 vinp net31 well_net31 sg13_lv_pmos w=5.6u l=1.75u m=50 -MM9 dm_2 vinn net31 well_net31 sg13_lv_pmos w=5.6u l=1.75u m=50 -RRtap_net31_0 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_1 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_2 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_3 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_4 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_5 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_6 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_7 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_8 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_9 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_10 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_11 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_12 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_13 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_14 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_15 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_16 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_17 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_18 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_19 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_20 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_21 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_22 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_23 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_24 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_25 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_26 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_27 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_28 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_29 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_30 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_31 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_32 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_33 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_34 net31 well_net31 ntap1 A=4e-12 P=8e-6 -MM0 net013 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM1 vb4 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM11 net043 net050 vdd well_vdd sg13_lv_pmos w=7.55u l=0.7u m=40 -MM12 vout net050 vdd well_vdd sg13_lv_pmos w=7.49u l=2.04u m=400 -MM2 dm_1 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM3 vb3 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM4 net31 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=8 -MM5 voutn voutn vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM6 net050 voutn vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM7 net049 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -MM8 net1 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -RRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_18 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_19 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_20 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_21 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_22 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_23 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_24 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_25 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_26 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_27 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_28 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_29 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_30 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_31 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_32 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_33 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_34 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_35 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_36 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_37 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_38 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_39 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_40 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_41 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_42 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_43 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_44 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_45 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_46 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_47 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_48 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_49 vdd 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A=4e-12 P=8e-6 -RRptap_70 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_71 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_72 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_73 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_74 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_75 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_76 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_77 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_78 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_79 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_80 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_81 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_82 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_83 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_84 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_85 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_86 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_87 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_88 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_89 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_90 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_91 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_92 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_93 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_94 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_95 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_96 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_97 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_98 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_99 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_100 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_101 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_102 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_103 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_104 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_105 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_106 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_107 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_108 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_109 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_110 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_111 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_112 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_113 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_114 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_115 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_116 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_117 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_118 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_119 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_120 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_121 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_122 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_123 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_124 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_125 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_126 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_127 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_128 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_129 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_130 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_131 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_132 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_133 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_134 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_135 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_136 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_137 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_138 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_139 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_140 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_141 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_142 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_143 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_144 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_145 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_146 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_147 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_148 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_149 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_150 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_151 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_152 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_153 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_154 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_155 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_156 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_157 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_158 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_159 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_160 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_161 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_162 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_163 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_164 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_165 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_166 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_167 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_168 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_169 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_170 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_171 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_172 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_173 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_174 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_175 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_176 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_177 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_178 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_179 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_180 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_181 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_182 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_183 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_184 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_185 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_186 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_187 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_188 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_189 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_190 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_191 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_192 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_193 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_194 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_195 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_196 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_197 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_198 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_199 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_200 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_201 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_202 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_203 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_204 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_205 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_206 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_207 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_208 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_209 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_210 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_211 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_212 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_213 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_214 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_215 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_216 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_217 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_218 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_219 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_220 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_221 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_222 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_223 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_224 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_225 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_226 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_227 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_228 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_229 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_230 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_231 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_232 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_233 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_234 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_235 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_236 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_237 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_238 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_239 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_240 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_241 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_242 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_243 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_244 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_245 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_246 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_247 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_248 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_249 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_250 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_251 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_252 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_253 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_254 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_255 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_256 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_257 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_258 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_259 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_260 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_261 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_262 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_263 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_264 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_265 vss sub ptap1 A=4e-12 P=8e-6 -CC0_0 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_1 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_2 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_3 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_4 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_5 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_6 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC0_7 net050 vout cap_cmim w=48.935u l=48.935u m=1 -CC1_0 net049 net1 cap_cmim w=50.94u l=50.94u m=1 -CC1_1 net049 net1 cap_cmim w=50.94u l=50.94u m=1 -CC1_2 net049 net1 cap_cmim w=50.94u l=50.94u m=1 +MM0 net013 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM1 vb4 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM10 net063 vinp net31 net31 sg13_lv_pmos w=2.8u l=1.75u m=100 +MM11 net043 net050 vdd vdd sg13_lv_pmos w=1.51u l=0.7u m=200 +MM12 vout net050 vdd vdd sg13_lv_pmos w=7.49u l=2.04u m=400 +MM13 vb4 vb3 net54 vss sg13_lv_nmos w=3.55u l=7.02u m=16 +MM14 dm_1 vb3 net56 vss sg13_lv_nmos w=3.55u l=7.02u m=16 +MM15 vb3 vb3 vss vss sg13_lv_nmos w=3.55u l=7.02u m=4 +MM16 voutn vb3 dm_2 vss sg13_lv_nmos w=0.72u l=1.59u m=16 +MM17 net050 vb3 net063 vss sg13_lv_nmos w=0.72u l=1.59u m=16 +MM18 net54 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=16 +MM19 net56 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=16 +MM2 dm_1 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM20 dm_2 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=32 +MM21 net063 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=32 +MM22 net043 net043 vss vss sg13_lv_nmos w=5.5u l=8.08u m=4 +MM23 net049 net043 vss vss sg13_lv_nmos w=5.5u l=8.08u m=4 +MM24 net1 net049 vss vss sg13_lv_nmos w=6.8u l=4.49u m=1 +MM25 vout net049 vss vss sg13_lv_nmos w=0.38u l=0.89u m=400 +MM3 vb3 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM4 net31 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=8 +MM5 voutn voutn vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM6 net050 voutn vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM7 net049 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM8 net1 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +MM9 dm_2 vinn net31 net31 sg13_lv_pmos w=2.8u l=1.75u m=100 +C0_0 net050 vout cap_cmim w=48.935u l=48.935u m=8 +C1_0 net049 net1 cap_cmim w=50.94u l=50.94u m=3 .ends amp_006_leung_dfcfc1 diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.spice index 3b5efa8556e1b0462ef742de14805f9ba74a9c73..999f03ca56009dea4599cc4b23dc3ea281537321 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.spice @@ -1,524 +1,32 @@ -* Derived from analog-db amp_006_leung_dfcfc1, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified by Layout-Bench: MOS rounded to 10 nm; equivalent regrouping preserves total W and L; -* physical MIM arrays, explicit bias port and body contacts. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_006_leung_dfcfc1 vss vdd vinn vinp vout net013 -XM13 vb4 vb3 net54 sub sg13_lv_nmos w=7.1u l=7.02u m=8 -XM14 dm_1 vb3 net56 sub sg13_lv_nmos w=7.1u l=7.02u m=8 -XM15 vb3 vb3 vss sub sg13_lv_nmos w=7.1u l=7.02u m=2 -XM16 voutn vb3 dm_2 sub sg13_lv_nmos w=5.76u l=1.59u m=2 -XM17 net050 vb3 net063 sub sg13_lv_nmos w=5.76u l=1.59u m=2 -XM18 net54 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=8 -XM19 net56 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=8 -XM20 dm_2 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=16 -XM21 net063 vb4 vss sub sg13_lv_nmos w=7.1u l=7.02u m=16 -XM22 net043 net043 vss sub sg13_lv_nmos w=5.5u l=8.08u m=4 -XM23 net049 net043 vss sub sg13_lv_nmos w=5.5u l=8.08u m=4 -XM24 net1 net049 vss sub sg13_lv_nmos w=6.8u l=4.49u m=1 -XM25 vout net049 vss sub sg13_lv_nmos w=9.5u l=0.89u m=16 -XM10 net063 vinp net31 well_net31 sg13_lv_pmos w=5.6u l=1.75u m=50 -XM9 dm_2 vinn net31 well_net31 sg13_lv_pmos w=5.6u l=1.75u m=50 -XRtap_net31_0 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_1 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_2 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_3 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_4 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_5 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_6 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_7 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_8 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_9 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_10 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_11 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_12 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_13 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_14 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_15 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_16 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_17 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_18 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_19 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_20 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_21 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_22 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_23 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_24 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_25 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_26 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_27 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_28 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_29 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_30 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_31 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_32 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_33 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_34 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XM0 net013 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM1 vb4 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM11 net043 net050 vdd well_vdd sg13_lv_pmos w=7.55u l=0.7u m=40 -XM12 vout net050 vdd well_vdd sg13_lv_pmos w=7.49u l=2.04u m=400 -XM2 dm_1 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM3 vb3 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM4 net31 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=8 -XM5 voutn voutn vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM6 net050 voutn vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM7 net049 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XM8 net1 net013 vdd well_vdd sg13_lv_pmos w=6.73u l=6.14u m=4 -XRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_18 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_19 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_20 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_21 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_22 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_23 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_24 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_25 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_26 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_27 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_28 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_29 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_30 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_31 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_32 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_33 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_34 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_35 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_36 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_37 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_38 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_39 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_40 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_41 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_42 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_43 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_44 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_45 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_46 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_47 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_48 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_49 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_50 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_51 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_52 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_53 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_54 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_55 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_56 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_57 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_58 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_59 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_60 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_61 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_62 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_63 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_64 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_65 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_66 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_67 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_68 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_69 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_70 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_71 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_72 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_73 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_74 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_75 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_76 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_77 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_78 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_79 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_80 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_81 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_82 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_83 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_84 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_85 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_86 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_87 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_88 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_89 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_90 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_91 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_92 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_93 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_94 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_95 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_96 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_97 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_98 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_99 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_100 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_101 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_102 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_103 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_104 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_105 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_106 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_107 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_108 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_109 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_110 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_111 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_112 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_113 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_114 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_115 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_116 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_117 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_118 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_119 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_120 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_121 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_122 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_123 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_124 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_125 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_126 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_127 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_128 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_129 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_130 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_131 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_132 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_133 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_134 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_135 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_136 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_137 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_138 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_139 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_140 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_141 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_142 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_143 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_144 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_145 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_146 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_147 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_148 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_149 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_150 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_151 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_152 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_153 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_154 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_155 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_156 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_157 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_158 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_159 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_160 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_161 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_162 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_163 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_164 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_165 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_166 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_167 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_168 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_169 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_170 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_171 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_172 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_173 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_174 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_175 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_176 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRptap_0 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_1 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_2 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_3 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_4 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_5 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_6 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_7 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_8 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_9 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_10 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_11 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_12 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_13 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_14 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_15 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_16 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_17 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_18 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_19 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_20 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_21 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_22 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_23 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_24 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_25 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_26 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_27 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_28 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_29 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_30 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_31 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_32 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_33 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_34 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_35 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_36 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_37 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_38 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_39 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_40 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_41 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_42 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_43 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_44 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_45 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_46 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_47 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_48 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_49 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_50 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_51 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_52 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_53 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_54 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_55 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_56 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_57 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_58 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_59 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_60 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_61 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_62 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_63 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_64 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_65 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_66 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_67 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_68 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_69 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_70 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_71 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_72 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_73 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_74 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_75 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_76 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_77 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_78 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_79 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_80 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_81 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_82 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_83 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_84 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_85 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_86 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_87 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_88 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_89 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_90 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_91 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_92 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_93 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_94 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_95 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_96 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_97 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_98 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_99 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_100 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_101 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_102 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_103 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_104 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_105 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_106 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_107 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_108 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_109 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_110 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_111 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_112 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_113 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_114 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_115 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_116 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_117 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_118 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_119 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_120 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_121 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_122 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_123 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_124 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_125 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_126 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_127 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_128 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_129 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_130 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_131 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_132 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_133 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_134 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_135 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_136 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_137 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_138 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_139 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_140 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_141 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_142 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_143 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_144 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_145 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_146 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_147 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_148 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_149 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_150 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_151 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_152 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_153 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_154 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_155 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_156 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_157 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_158 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_159 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_160 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_161 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_162 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_163 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_164 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_165 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_166 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_167 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_168 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_169 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_170 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_171 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_172 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_173 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_174 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_175 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_176 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_177 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_178 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_179 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_180 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_181 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_182 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_183 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_184 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_185 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_186 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_187 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_188 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_189 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_190 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_191 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_192 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_193 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_194 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_195 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_196 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_197 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_198 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_199 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_200 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_201 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_202 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_203 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_204 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_205 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_206 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_207 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_208 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_209 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_210 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_211 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_212 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_213 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_214 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_215 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_216 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_217 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_218 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_219 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_220 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_221 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_222 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_223 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_224 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_225 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_226 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_227 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_228 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_229 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_230 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_231 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_232 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_233 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_234 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_235 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_236 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_237 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_238 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_239 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_240 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_241 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_242 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_243 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_244 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_245 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_246 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_247 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_248 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_249 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_250 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_251 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_252 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_253 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_254 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_255 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_256 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_257 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_258 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_259 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_260 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_261 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_262 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_263 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_264 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_265 vss sub ptap1 A=4e-12 P=8e-6 -XC0_0 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_1 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_2 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_3 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_4 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_5 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_6 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC0_7 net050 vout cap_cmim w=48.935u l=48.935u m=1 -XC1_0 net049 net1 cap_cmim w=50.94u l=50.94u m=1 -XC1_1 net049 net1 cap_cmim w=50.94u l=50.94u m=1 -XC1_2 net049 net1 cap_cmim w=50.94u l=50.94u m=1 +XM0 net013 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM1 vb4 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM10 net063 vinp net31 net31 sg13_lv_pmos w=2.8u l=1.75u m=100 +XM11 net043 net050 vdd vdd sg13_lv_pmos w=1.51u l=0.7u m=200 +XM12 vout net050 vdd vdd sg13_lv_pmos w=7.49u l=2.04u m=400 +XM13 vb4 vb3 net54 vss sg13_lv_nmos w=3.55u l=7.02u m=16 +XM14 dm_1 vb3 net56 vss sg13_lv_nmos w=3.55u l=7.02u m=16 +XM15 vb3 vb3 vss vss sg13_lv_nmos w=3.55u l=7.02u m=4 +XM16 voutn vb3 dm_2 vss sg13_lv_nmos w=0.72u l=1.59u m=16 +XM17 net050 vb3 net063 vss sg13_lv_nmos w=0.72u l=1.59u m=16 +XM18 net54 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=16 +XM19 net56 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=16 +XM2 dm_1 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM20 dm_2 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=32 +XM21 net063 vb4 vss vss sg13_lv_nmos w=3.55u l=7.02u m=32 +XM22 net043 net043 vss vss sg13_lv_nmos w=5.5u l=8.08u m=4 +XM23 net049 net043 vss vss sg13_lv_nmos w=5.5u l=8.08u m=4 +XM24 net1 net049 vss vss sg13_lv_nmos w=6.8u l=4.49u m=1 +XM25 vout net049 vss vss sg13_lv_nmos w=0.38u l=0.89u m=400 +XM3 vb3 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM4 net31 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=8 +XM5 voutn voutn vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM6 net050 voutn vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM7 net049 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM8 net1 net013 vdd vdd sg13_lv_pmos w=6.73u l=6.14u m=4 +XM9 dm_2 vinn net31 net31 sg13_lv_pmos w=2.8u l=1.75u m=100 +XC0_0 net050 vout cap_cmim w=48.935u l=48.935u m=8 +XC1_0 net049 net1 cap_cmim w=50.94u l=50.94u m=3 .ends amp_006_leung_dfcfc1 diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/schematic.svg deleted file mode 100644 index 6cff6740de77b7312fe0b3b47a6fbfecf857c8a9..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_006_leung_dfcfc1{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_006_leung_dfcfc1","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_006_leung_dfcfc1","Bank1_35x_ntap1","Bank2_177x_ntap1","Bank3_266x_ptap1","Bank4_8x_cap_cmim"],"banks":[{"name":"Bank1_35x_ntap1","count":35,"model":"ntap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank2_177x_ntap1","count":177,"model":"ntap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank3_266x_ptap1","count":266,"model":"ptap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank4_8x_cap_cmim","count":8,"model":"cap_cmim","params":{"w":"48.935u","l":"48.935u","m":"1"}}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_006_leung_dfcfc1"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/design/amp_006_leung_dfcfc1.icproj.json"}}Main-sheet overview; 4 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_006_leung_dfcfc1net31well_net31vddwell_vddvsssubnet050voutvinpvinnnet050vddnet31vb3vb4vssnet063dm_2voutnnet050net013net1vddnet049vssnet043net050vddnet049vssvoutdm_1net54net56vssvddvb4net013vb3net31net013vddnet049net1net31well_net31vddwell_vddvsssubnet050voutvssvddvinnvinpvoutnet013amp_006_leung_dfcfc1ihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresDifferential inputMM66.73/6.14 ×4MM56.73/6.14 ×4MM105.6/1.75 ×50MM95.6/1.75 ×50MM175.76/1.59 ×2MM165.76/1.59 ×2MM217.1/7.02 ×16MM207.1/7.02 ×16MM6, MM5: B → well_vddMM10, MM9: B → well_net31N bulk → subIntermediate gainMM117.55/0.7 ×40MM76.73/6.14 ×4MM86.73/6.14 ×4MM225.5/8.08 ×4MM235.5/8.08 ×4MM246.8/4.49P bulk → well_vddN bulk → subOutput and local feedbackMM127.49/2.04 ×400MM259.5/0.89 ×16P bulk → well_vddN bulk → subTail current biasMM06.73/6.14 ×4MM16.73/6.14 ×4MM26.73/6.14 ×4MM36.73/6.14 ×4MM137.1/7.02 ×8MM147.1/7.02 ×8MM157.1/7.02 ×2MM187.1/7.02 ×8MM197.1/7.02 ×8P bulk → well_vddN bulk → subBias referenceMM46.73/6.14 ×8P bulk → well_vddCompensationCC1_050.9/50.9CC1_150.9/50.9CC1_250.9/50.9Substrate tiesXBANK1Bank1_35x_ntap1XBANK2Bank2_177x_ntap1XBANK3Bank3_266x_ptap1XBANK4Bank4_8x_cap_cmimModels: sg13_lv_nmos · sg13_lv_pmos · cap_cmim - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md index f6698046c5ce978e0c0a8e98b1ff41af75468dd2..3d633fd4aeb66f1fd7be5112fcb817996e66a4b4 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md @@ -15,23 +15,18 @@ control node. In contrast, the separate AMP007 case's auxiliary PMOS senses ## Inputs and Interface - `materials/circuit.cdl`: authoritative native physical device graph. -- `materials/circuit.spice`: matching simulator representation with finite taps. +- `materials/circuit.spice`: matching simulator representation with logical body nets. - `materials/testbench.spice`: public bias, bilateral AC and step measurements. Ordered ports: `vss vdd vinn vinp vout net013`. VSS is return, VDD supply, VINN/VINP the inverting/noninverting inputs, VOUT output, and `net013` the external bias-sink connection. Input PMOS bodies connect to the separate `net31` source-tied well; other PMOS use the VDD well and NMOS use the VSS -substrate contact. Preserve all 26 MOS groups, 675 physical fingers, W/L/m, +substrate. Preserve all 26 MOS groups, W/L/m, body connections, and both internal capacitive branches. Native equivalent parallel fingering is allowed only when all physical and electrical checks pass. -The maintained MOS dimensions are rounded to the actual 10 nm PyCell grid; -the 1,413 rounded source fingers are regrouped within their original MOS -groups using integer factors, with <=10 um single width. Each group retains -exactly its rounded total W and L; individual W/m and diffusion perimeter -change. Every body connection remains intact. Distributed 2 x 2 um body -contacts at <=20 um pitch replace continuous tap strips. All capacitors are physical `cap_cmim`: +MOS dimensions retain the declared grid adaptation. All capacitors are physical `cap_cmim`: - `c0`: `net050` (top plate) to `vout` (bottom plate), 8 parallel 48.935 × 48.935 um MIM units. - `c1`: `net049` (top plate) to `net1` (bottom plate), 3 parallel 50.94 × 50.94 um MIM units. @@ -88,7 +83,7 @@ are outside this contract. Submit GDSII top cell `amp_006_leung_dfcfc1`, at most 32 MiB. Pass native IHP main/maximal DRC without waivers (standalone scope, density/antenna off), -strict named-interface LVS with explicit taps, and a 6400 × 130 um functional +strict named-interface LVS with physically verified body connections, and a 6400 × 130 um functional envelope. Every device/contact/interconnect drawing layer listed in the runtime `outline` constraint contributes to area; annotation/pin-purpose layers do not. Labels alone do not establish electrical connectivity. @@ -97,9 +92,8 @@ Post-layout simulation uses the submitted GDS's complete Magic RC, with physical MIM devices and interconnect resistances/capacitances. Half-grid import is explicit. Magic retains only Metal3 interface labels in its isolated extraction copy to avoid repeated internal well-name aliases, while native LVS -checks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics. -Magic idealizes well/substrate taps, whereas source simulation uses finite -physical tap models. Distributed substrate resistance/noise and fabrication +checks the original GDS and its actual body-contact connectivity. No resistance/capacitance threshold omits small parasitics. +Source simulation and extraction use the same logical body-net boundary. Distributed substrate resistance/noise and fabrication signoff remain unqualified. The long independent witness is a feasibility layout, not an area optimum. @@ -140,7 +134,7 @@ For metrics declaring `saturating_ratio`, q = 2(b+s)/(b+x+2*s), using the qualit | `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response | | `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response | -Area reference: **82915.92 um2**. The expanded circuit has 1164 device instances, a sum of device/contact envelopes 54901.4182 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. +Area reference: **82915.92 um2**. The reference engineering estimate used 1164 device instances, a sum of device/contact envelopes 54901.4182 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. Reference MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. The capability coefficient is **8**, independent of this task's reference-normalized score. @@ -148,7 +142,7 @@ The capability coefficient is **8**, independent of this task's reference-normal The area quality target is **34000 um2**. It is an integration budget, not a hard limit or a proven process minimum. -The eleven fixed MIM plates occupy 26941.7246 um2. A 34000 um2 integration budget allocates about 79% to those plates and the balance to enclosures, 675 MOS fingers, taps and routing; it is not a process minimum. Area carries 30%, 100 ppm step-referred DC accuracy 15%, the worst bilateral normalized response integral 20%, bandwidth 10%, phase-margin preservation 10%, sampled return distance 5%, large-signal step gain 5% and mean power 5%. First/final crossing diagnostics and fully settled recovery errors are retained without duplicate weight. The source and extracted tap representations differ, so the source DC offset is not used as a loose accuracy goal. +The eleven fixed MIM plates occupy 26941.7246 um2. A 34000 um2 integration budget allocates about 79% to those plates and the balance to enclosures, 675 MOS fingers, taps and routing; it is not a process minimum. Area carries 30%, 100 ppm step-referred DC accuracy 15%, the worst bilateral normalized response integral 20%, bandwidth 10%, phase-margin preservation 10%, sampled return distance 5%, large-signal step gain 5% and mean power 5%. First/final crossing diagnostics and fully settled recovery errors are retained without duplicate weight. Source and extraction use the same logical body-net boundary. `response_time_s` takes the worst of both normalized absolute-error integrals under every declared condition: integrate `abs(v(vout)-high_v)/0.2` over 2.02–9.5 us, and `abs(v(vout)-low_v)/0.2` over 10.04–17.5 us. `high_v` and `low_v` are the existing late-window means. The result is in seconds; a first-order exponential would integrate to its time constant over a sufficiently long window. The 500 ns budget leaves about 6 ns above the worst 494 ns source result. This finite-window response cost is not a measured settling time or a guarantee of later convergence. DC offset and large-signal step gain are scored separately, preventing a flat or wrong-amplitude response from satisfying all goals. @@ -176,3 +170,5 @@ Discover inputs/resources/feedback through `/protocol/task.json`, IHP primitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds` and explicitly submit via the harness protocol. Host configuration, source records and reference answers are outside solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml index 0f59c98fa3ed0fd62a362672b1123d7e444dc1be..01d913206eb3ec116a5190072c2a160f99091c4b 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml @@ -4,13 +4,6 @@ title = "Auxiliary-Stage Miller Compensation OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "5a70225d79ab55135e6cdf0cb3988c1d24b3977aed12b569c102e12d91803934" - [[assets]] path = "reference/amp_007_leung_dfcfc2.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/materials/schematic.svg deleted file mode 100644 index a25005b3c1533664ea7bd9b92815cfb4f10d480c..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_007_leung_dfcfc2{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_007_leung_dfcfc2","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_007_leung_dfcfc2","Bank1_5x_cap_cmim","Bank2_5x_cap_cmim"],"banks":[{"name":"Bank1_5x_cap_cmim","count":5,"model":"cap_cmim","params":{"w":"47.61u","l":"47.61u","m":"1"}},{"name":"Bank2_5x_cap_cmim","count":5,"model":"cap_cmim","params":{"w":"47.61u","l":"47.61u","m":"1"}}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_007_leung_dfcfc2"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/design/amp_007_leung_dfcfc2.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_007_leung_dfcfc2net050voutnet050net2vinnvinpvddnet050net31vb3vb4vssdm_2net063voutnnet050net049vssvddnet1net043net050vddnet049vssvoutnet050net2dm_1net54net56net1vddvssvb4vb3net31net1vddnet31well_net31vddwell_vddvsssubvoutnet2net050net050vssvddvinnvinpvoutnet1amp_007_leung_dfcfc2ihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresDifferential input and folded branchesMM51/1 ×4MM61/1 ×4MM81/1 ×100MM91/1 ×100MM161/1 ×16MM171/1 ×16MM201/1 ×32MM211/1 ×32MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subIntermediate gainMM111/1 ×4MM71/1 ×4MM01/1 ×4MM231/1 ×4MM241/1 ×4P bulk → well_vddN bulk → subOutput stageMM121/1 ×4MM251/1 ×4P bulk → well_vddN bulk → subTail-current biasMM11/1 ×4MM101/1 ×4MM21/1 ×4MM31/1 ×4MM131/1 ×16MM221/1 ×16MM141/1 ×16MM151/1 ×4MM181/1 ×16MM191/1 ×16P bulk → well_vddN bulk → subBias referenceMM41/1 ×8P bulk → well_vddBulk ties and device banksRRtap_net31A=2410 µm²RRtap_vddA=642 µm²RRptapA=5510 µm²XBANK1Bank1_5x_cap_cmimXBANK2Bank2_5x_cap_cmimModels: sg13_lv_nmos · sg13_lv_pmos · ntap1 · ptap1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml index e5e4da53ad6a7f319da0ab03e4031a734fd3a7e8..59edec1fc95d0e10d5cb63f35cf52fa4f965ebdd 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml @@ -4,13 +4,6 @@ title = "Dual-Capacitor Three-Stage OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "816e9bade872c6dbf33df99347772e550f50b4b416df2a6bf0fef253a4236831" - [[assets]] path = "reference/amp_008_leung_nmcf.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/materials/schematic.svg deleted file mode 100644 index 68ad342e30c9fe771aed965fa65edaafc2fe1615..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_008_leung_nmcf{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_008_leung_nmcf","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_008_leung_nmcf"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_008_leung_nmcf"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/design/amp_008_leung_nmcf.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_008_leung_nmcfvddnet050net31vb3vb4vssdm_2net063voutnnet013net050vddnet049vssnet043dm_1net54net56vssvddvb4net013vb3net31vddnet049net050voutnet31well_net31vddwell_vddvsssubvssvddvinnvinpvoutnet013amp_008_leung_nmcfihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM53.82/1.79 ×4MM63.82/1.79 ×4MM84.11/0.66 ×4MM94.11/0.66 ×4MM152.56/0.14 ×16MM162.56/0.14 ×16MM192.56/0.14 ×32MM202.56/0.14 ×32MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subMM107.44/4.42 ×4MM73.82/1.79 ×4MM117.14/0.22 ×4MM215.17/1.73 ×4MM225.17/1.73 ×4MM236.43/2.18 ×4P bulk → well_vddN bulk → subMM03.82/1.79 ×4MM13.82/1.79 ×4MM23.82/1.79 ×4MM33.82/1.79 ×4MM122.56/0.14 ×16MM132.56/0.14 ×16MM142.56/0.14 ×4MM172.56/0.14 ×16MM182.56/0.14 ×16P bulk → well_vddN bulk → subMM43.82/1.79 ×16P bulk → well_vddCC0_047/47CC0_147/47CC1_030.7/30.7RRtap_net31A=103 µm²RRtap_vddA=775 µm²RRptapA=2870 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml index 5a41aaf3f29ebf3f839f3ba5241141932da3aa7e..cf9af8494b50f0849e927958baf4f5b05629719c 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml @@ -4,13 +4,6 @@ title = "Shared-Nulling-Resistor Three-Stage OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "b6d72ff145569d5cb429b6197224fa79250fca2c7362eff697d29364eb738879" - [[assets]] path = "reference/amp_009_leung_nmcnr.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/materials/schematic.svg deleted file mode 100644 index 6c8c3953b6e9eb3c4c73d813ce72b9d593486126..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_009_leung_nmcnr{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_009_leung_nmcnr","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_009_leung_nmcnr"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/design/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":1},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_009_leung_nmcnr"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/design/amp_009_leung_nmcnr.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_009_leung_nmcnrvddnet050net31vb3vb4vssdm_2net063voutnnet050net013vddnet049vssnet043dm_1net54net56vssvddvb4net013vb3net31vddnet049voutnet050net044net31well_net31vddwell_vddvsssubvssvddvinnvinpvoutnet013amp_009_leung_nmcnrihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM51/1 ×4MM61/1 ×4MM81/1 ×4MM91/1 ×4MM151/1 ×16MM161/1 ×16MM191/1 ×32MM201/1 ×32MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subMM101/1 ×4MM71/1 ×4MM111/1 ×40MM211/1 ×4MM221/1 ×4MM231/1 ×4P bulk → well_vddN bulk → subMM01/1 ×4MM11/1 ×4MM21/1 ×4MM31/1 ×4MM121/1 ×16MM131/1 ×16MM141/1 ×4MM171/1 ×16MM181/1 ×16P bulk → well_vddN bulk → subMM41/1 ×16P bulk → well_vddCC0_040.8/40.8CC0_140.8/40.8CC1_044.7/44.7RR0_01/6.94R substrate → subRRtap_net31A=108 µm²RRtap_vddA=1120 µm²RRptapA=3480 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml index 5bc806b19a5e5c6308e76d0415b16185be3455c3..81f1db90f894128919f9c63cd8fa86fe2314f272 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml @@ -4,13 +4,6 @@ title = "Auxiliary-Branch Compensation OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "b9b9a322c8112e8c6aeaf500babc993faddf55b0a979e366eb98cfc626692453" - [[assets]] path = "reference/amp_010_peng_acbc.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/materials/schematic.svg deleted file mode 100644 index a076a2db5534149fc809fa013008793692d1b9ef..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_010_peng_acbc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_010_peng_acbc","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_010_peng_acbc"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_010_peng_acbc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/design/amp_010_peng_acbc.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_010_peng_acbcnet050vddnet31vb3vb4vssnet063dm_2voutnnet050net013net049vddnet1vssnet043net050vddnet049vssdm_1net54net56vssvddvb4vb3net31net1net013vddnet049net1net050voutnet31well_net31vddwell_vddvsssubvssvddvinnvinpvoutnet013amp_010_peng_acbcihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM62.69/1.29 ×4MM52.69/1.29 ×4MM104.25/1.07 ×4MM94.25/1.07 ×4MM173.55/0.5 ×16MM163.55/0.5 ×16MM215.53/0.62 ×32MM205.53/0.62 ×32MM6, MM5: B → well_vddMM10, MM9: B → well_net31N bulk → subMM116.4/1.24MM72.69/1.29 ×4MM594.98/7.88 ×4MM224.02/9.7 ×4MM234.02/9.7 ×4MM249.97/8.02 ×4P bulk → well_vddN bulk → subMM129.16/1.19 ×4MM253.52/1.91 ×4P bulk → well_vddN bulk → subMM02.69/1.29 ×4MM12.69/1.29 ×4MM22.69/1.29 ×4MM32.69/1.29 ×4MM135.53/0.62 ×16MM145.53/0.62 ×16MM155.53/0.62 ×4MM185.53/0.62 ×16MM195.53/0.62 ×16P bulk → well_vddN bulk → subMM42.69/1.29 ×8MM82.69/1.29 ×4P bulk → well_vddCC0_050.4/50.4CC0_150.4/50.4CC0_250.4/50.4CC0_350.4/50.4CC1_038.3/38.3CC1_138.3/38.3RRtap_net31A=109 µm²RRtap_vddA=740 µm²RRptapA=3230 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml index 5a574c8495b88e6a656c632cdd72503ae149891e..3f3633c70437c985e62289d6637b154fccba2f87 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml @@ -4,13 +4,6 @@ title = "Peng IAC Three-Stage Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "679fae5a249fedc6831d1810b021518151663db82d9be9ea935109998f9cd6b4" - [[assets]] path = "reference/amp_011_peng_iac.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "f29f1ef727f3da1b8ee039f271109c322bae2ad1777d2829b4d54a0552f1eed3" +sha256 = "1eedef0540272f39df60485ee86997943a0e13a0b6e497018d7d349bfe4dfd3e" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_011_peng_iac" -sha256 = "3d202284343734913c74c1436446a7dab16631757da8c617aaae8e6f67a2db15" +sha256 = "e96cbf2422a28df546809a5b96a0039dc081caef58fc61c63a65d622bd042fda" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "8ebd9567afb219eb76a2e127ce53ae66dccd1f357c22faa0fdf4f135541c26cd" +sha256 = "648c8e73a066f480669f9c769df43a897665f4d0d7dff2c3c6977f0fd538cac5" [task.inputs.performance] path = "materials/testbench.spice" @@ -686,10 +679,10 @@ upper = 1e-06 rationale = "The ideal external feedback/injection fixture must preserve its stated common mode and DC feedback; 1 uV is the numerical consistency allowance for this measurement fixture." [task.evaluation.pre_layout] -source_report_sha256 = "d9bd2052fa1c1e150404766a7e6da8715dd730448073cc94fb7f5cf732b23494" +source_report_sha256 = "41aba31e3c2fb8425eaeda966f2e7699dfb6eaffae0daa456a2e8c44cb86923b" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -729,65 +722,60 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "d45426dafee5833b944f1a54bc1a27877ae797d06922f2c6fa6a57c73a33cc90" -dut = "8ebd9567afb219eb76a2e127ce53ae66dccd1f357c22faa0fdf4f135541c26cd" +dut = "648c8e73a066f480669f9c769df43a897665f4d0d7dff2c3c6977f0fd538cac5" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 1.201005045878834 +value = 1.201012070769958 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = -0.0001530725 +value = -0.0001530608 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] -value = 0.3233982 +value = 0.3222678 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] -value = 0.09199888 +value = 0.092584 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] -value = 0.2284027 +value = 0.2284627 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 4.465819e-05 +value = 4.466838e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] -value = 0.4398818 +value = 0.439914 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] -value = 0.01305254 +value = 0.01294371 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.2397462794255175 +value = 0.2397464862843441 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 3.078441985545703e-05 +value = 3.077555246674978e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 0.07596886 +value = 0.07603494 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] -value = 0.3153995 +value = 0.3154704 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 0.4056972 +value = 0.4060901 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "69e9f6f48dafc205596450ce786ea44688c0fae3fabadd508abc3bc3d01b6bef" -ac = "fd47637f353b4247b72381b00554536e0194f856beb8972590a417f824d1a3f1" -transient = "9a5358792d469c49526a24337b682e23441426c1490dcfaf8ebcc22d3cbce508" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -814,28 +802,24 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "558697e9c13b7f453fab1289010b503b4332241b0bed67b121b74ad214848f3e" -dut = "8ebd9567afb219eb76a2e127ce53ae66dccd1f357c22faa0fdf4f135541c26cd" +dut = "648c8e73a066f480669f9c769df43a897665f4d0d7dff2c3c6977f0fd538cac5" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] -value = 5.88418203051333e-15 +value = 2.081668171172169e-15 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] -value = 5.421396006743842e-09 +value = 5.420802122834316e-09 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] -value = 44.64227 +value = 44.64068 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] -value = 112.63 +value = 112.6291 unit = "dB" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "7bf0807df6d720247e4af87cabda4981064d6e82defb0a6e610f34206b053e5e" -ac = "3741369be6a497ded1366cf3195379ef8cbf1016c833ddd07076124c6cf0c7be" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -875,7 +859,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl index 62a07388a323bc0c01682e28578f67e6be714077..3d22fc4e0da62f34ba872f5456c4fa34e6de051d 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl @@ -1,1024 +1,46 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_011_peng_iac vss vdd vinn vinp vout vb1 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM0_0 net2 vb1 vdd well_0 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM0_1 net2 vb1 vdd well_1 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM0_2 net2 vb1 vdd well_2 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM0_3 net2 vb1 vdd well_3 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM0_4 net2 vb1 vdd well_4 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM0_5 net2 vb1 vdd well_5 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -MM0_6 net2 vb1 vdd well_6 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM0_7 net2 vb1 vdd well_7 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM0_8 net2 vb1 vdd well_8 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM0_9 net2 vb1 vdd well_9 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM0_10 net2 vb1 vdd well_10 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM0_11 net2 vb1 vdd well_11 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM0_12 net2 vb1 vdd well_12 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM0_13 net2 vb1 vdd well_13 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM0_14 net2 vb1 vdd well_14 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM0_15 net2 vb1 vdd well_15 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -MM1_0 net3 vb1 vdd well_16 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM1_1 net3 vb1 vdd well_17 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -MM1_2 net3 vb1 vdd well_18 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM1_3 net3 vb1 vdd well_19 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM1_4 net3 vb1 vdd well_20 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM1_5 net3 vb1 vdd well_21 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM1_6 net3 vb1 vdd well_22 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -MM1_7 net3 vb1 vdd well_23 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -MM1_8 net3 vb1 vdd well_24 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -MM1_9 net3 vb1 vdd well_25 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -MM1_10 net3 vb1 vdd well_26 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -MM1_11 net3 vb1 vdd well_27 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -MM1_12 net3 vb1 vdd well_28 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -MM1_13 net3 vb1 vdd well_29 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -MM1_14 net3 vb1 vdd well_30 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -MM1_15 net3 vb1 vdd well_31 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -MM10_0 net043 voutp vdd well_32 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT33 vdd well_33 ntap1 A=4e-12 P=8e-6 -MM10_1 net043 voutp vdd well_33 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -MM10_2 net043 voutp vdd well_34 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -MM10_3 net043 voutp vdd well_35 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -MM10_4 net043 voutp vdd well_36 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -MM10_5 net043 voutp vdd well_37 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -MM10_6 net043 voutp vdd well_38 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -MM10_7 net043 voutp vdd well_39 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT40 vdd well_40 ntap1 A=4e-12 P=8e-6 -MM10_8 net043 voutp vdd well_40 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -MM10_9 net043 voutp vdd well_41 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT42 vdd well_42 ntap1 A=4e-12 P=8e-6 -MM10_10 net043 voutp vdd well_42 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -MM10_11 net043 voutp vdd well_43 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -MM10_12 net043 voutp vdd well_44 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -MM10_13 net043 voutp vdd well_45 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -MM10_14 net043 voutp vdd well_46 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -MM10_15 net043 voutp vdd well_47 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -MM10_16 net043 voutp vdd well_48 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -MM10_17 net043 voutp vdd well_49 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -MM10_18 net043 voutp vdd well_50 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -MM10_19 net043 voutp vdd well_51 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -MM10_20 net043 voutp vdd well_52 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -MM10_21 net043 voutp vdd well_53 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -MM10_22 net043 voutp vdd well_54 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -MM10_23 net043 voutp vdd well_55 sg13_lv_pmos w=4.88u l=2.36u m=1 -RT56 vdd well_56 ntap1 A=4e-12 P=8e-6 -MM11_0 vout voutp vdd well_56 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT57 vdd well_57 ntap1 A=4e-12 P=8e-6 -MM11_1 vout voutp vdd well_57 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT58 vdd well_58 ntap1 A=4e-12 P=8e-6 -MM11_2 vout voutp vdd well_58 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT59 vdd well_59 ntap1 A=4e-12 P=8e-6 -MM11_3 vout voutp vdd well_59 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT60 vdd well_60 ntap1 A=4e-12 P=8e-6 -MM11_4 vout voutp vdd well_60 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT61 vdd well_61 ntap1 A=4e-12 P=8e-6 -MM11_5 vout voutp vdd well_61 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT62 vdd well_62 ntap1 A=4e-12 P=8e-6 -MM11_6 vout voutp vdd well_62 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT63 vdd well_63 ntap1 A=4e-12 P=8e-6 -MM11_7 vout voutp vdd well_63 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT64 vdd well_64 ntap1 A=4e-12 P=8e-6 -MM11_8 vout voutp vdd well_64 sg13_lv_pmos w=4.46u l=0.98u m=1 -RT65 vss sub ptap1 A=4e-12 P=8e-6 -MM12_0 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT66 vss sub ptap1 A=4e-12 P=8e-6 -MM12_1 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT67 vss sub ptap1 A=4e-12 P=8e-6 -MM12_2 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT68 vss sub ptap1 A=4e-12 P=8e-6 -MM12_3 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT69 vss sub ptap1 A=4e-12 P=8e-6 -MM12_4 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT70 vss sub ptap1 A=4e-12 P=8e-6 -MM12_5 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT71 vss sub ptap1 A=4e-12 P=8e-6 -MM12_6 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT72 vss sub ptap1 A=4e-12 P=8e-6 -MM12_7 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT73 vss sub ptap1 A=4e-12 P=8e-6 -MM13_0 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT74 vss sub ptap1 A=4e-12 P=8e-6 -MM13_1 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT75 vss sub ptap1 A=4e-12 P=8e-6 -MM13_2 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT76 vss sub ptap1 A=4e-12 P=8e-6 -MM13_3 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT77 vss sub ptap1 A=4e-12 P=8e-6 -MM13_4 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT78 vss sub ptap1 A=4e-12 P=8e-6 -MM13_5 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT79 vss sub ptap1 A=4e-12 P=8e-6 -MM13_6 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT80 vss sub ptap1 A=4e-12 P=8e-6 -MM13_7 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT81 vss sub ptap1 A=4e-12 P=8e-6 -MM14_0 vb3 vb3 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT82 vss sub ptap1 A=4e-12 P=8e-6 -MM14_1 vb3 vb3 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT83 vss sub ptap1 A=4e-12 P=8e-6 -MM15_0 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT84 vss sub ptap1 A=4e-12 P=8e-6 -MM15_1 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT85 vss sub ptap1 A=4e-12 P=8e-6 -MM15_2 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT86 vss sub ptap1 A=4e-12 P=8e-6 -MM15_3 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT87 vss sub ptap1 A=4e-12 P=8e-6 -MM15_4 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT88 vss sub ptap1 A=4e-12 P=8e-6 -MM15_5 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT89 vss sub ptap1 A=4e-12 P=8e-6 -MM15_6 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT90 vss sub ptap1 A=4e-12 P=8e-6 -MM15_7 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT91 vss sub ptap1 A=4e-12 P=8e-6 -MM15_8 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT92 vss sub ptap1 A=4e-12 P=8e-6 -MM15_9 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT93 vss sub ptap1 A=4e-12 P=8e-6 -MM15_10 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT94 vss sub ptap1 A=4e-12 P=8e-6 -MM15_11 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT95 vss sub ptap1 A=4e-12 P=8e-6 -MM15_12 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT96 vss sub ptap1 A=4e-12 P=8e-6 -MM15_13 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT97 vss sub ptap1 A=4e-12 P=8e-6 -MM15_14 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT98 vss sub ptap1 A=4e-12 P=8e-6 -MM15_15 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT99 vss sub ptap1 A=4e-12 P=8e-6 -MM16_0 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT100 vss sub ptap1 A=4e-12 P=8e-6 -MM16_1 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT101 vss sub ptap1 A=4e-12 P=8e-6 -MM16_2 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT102 vss sub ptap1 A=4e-12 P=8e-6 -MM16_3 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT103 vss sub ptap1 A=4e-12 P=8e-6 -MM16_4 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT104 vss sub ptap1 A=4e-12 P=8e-6 -MM16_5 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT105 vss sub ptap1 A=4e-12 P=8e-6 -MM16_6 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT106 vss sub ptap1 A=4e-12 P=8e-6 -MM16_7 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT107 vss sub ptap1 A=4e-12 P=8e-6 -MM16_8 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT108 vss sub ptap1 A=4e-12 P=8e-6 -MM16_9 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT109 vss sub ptap1 A=4e-12 P=8e-6 -MM16_10 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT110 vss sub ptap1 A=4e-12 P=8e-6 -MM16_11 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT111 vss sub ptap1 A=4e-12 P=8e-6 -MM16_12 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT112 vss sub ptap1 A=4e-12 P=8e-6 -MM16_13 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT113 vss sub ptap1 A=4e-12 P=8e-6 -MM16_14 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT114 vss sub ptap1 A=4e-12 P=8e-6 -MM16_15 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT115 vss sub ptap1 A=4e-12 P=8e-6 -MM17_0 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT116 vss sub ptap1 A=4e-12 P=8e-6 -MM17_1 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT117 vss sub ptap1 A=4e-12 P=8e-6 -MM17_2 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT118 vss sub ptap1 A=4e-12 P=8e-6 -MM17_3 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT119 vss sub ptap1 A=4e-12 P=8e-6 -MM17_4 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT120 vss sub ptap1 A=4e-12 P=8e-6 -MM17_5 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT121 vss sub ptap1 A=4e-12 P=8e-6 -MM17_6 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT122 vss sub ptap1 A=4e-12 P=8e-6 -MM17_7 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT123 vss sub ptap1 A=4e-12 P=8e-6 -MM18_0 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT124 vss sub ptap1 A=4e-12 P=8e-6 -MM18_1 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT125 vss sub ptap1 A=4e-12 P=8e-6 -MM18_2 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT126 vss sub ptap1 A=4e-12 P=8e-6 -MM18_3 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT127 vss sub ptap1 A=4e-12 P=8e-6 -MM18_4 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT128 vss sub ptap1 A=4e-12 P=8e-6 -MM18_5 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT129 vss sub ptap1 A=4e-12 P=8e-6 -MM18_6 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT130 vss sub ptap1 A=4e-12 P=8e-6 -MM18_7 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT131 vss sub ptap1 A=4e-12 P=8e-6 -MM19_0 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT132 vss sub ptap1 A=4e-12 P=8e-6 -MM19_1 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT133 vss sub ptap1 A=4e-12 P=8e-6 -MM19_2 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT134 vss sub ptap1 A=4e-12 P=8e-6 -MM19_3 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT135 vss sub ptap1 A=4e-12 P=8e-6 -MM19_4 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT136 vss sub ptap1 A=4e-12 P=8e-6 -MM19_5 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT137 vss sub ptap1 A=4e-12 P=8e-6 -MM19_6 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT138 vss sub ptap1 A=4e-12 P=8e-6 -MM19_7 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT139 vss sub ptap1 A=4e-12 P=8e-6 -MM19_8 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT140 vss sub ptap1 A=4e-12 P=8e-6 -MM19_9 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT141 vss sub ptap1 A=4e-12 P=8e-6 -MM19_10 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT142 vss sub ptap1 A=4e-12 P=8e-6 -MM19_11 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT143 vss sub ptap1 A=4e-12 P=8e-6 -MM19_12 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT144 vss sub ptap1 A=4e-12 P=8e-6 -MM19_13 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT145 vss sub ptap1 A=4e-12 P=8e-6 -MM19_14 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT146 vss sub ptap1 A=4e-12 P=8e-6 -MM19_15 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT147 vdd well_147 ntap1 A=4e-12 P=8e-6 -MM2_0 net6 vb1 vdd well_147 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT148 vdd well_148 ntap1 A=4e-12 P=8e-6 -MM2_1 net6 vb1 vdd well_148 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT149 vdd well_149 ntap1 A=4e-12 P=8e-6 -MM2_2 net6 vb1 vdd well_149 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT150 vdd well_150 ntap1 A=4e-12 P=8e-6 -MM2_3 net6 vb1 vdd well_150 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT151 vdd well_151 ntap1 A=4e-12 P=8e-6 -MM2_4 net6 vb1 vdd well_151 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT152 vdd well_152 ntap1 A=4e-12 P=8e-6 -MM2_5 net6 vb1 vdd well_152 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT153 vdd well_153 ntap1 A=4e-12 P=8e-6 -MM2_6 net6 vb1 vdd well_153 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT154 vdd well_154 ntap1 A=4e-12 P=8e-6 -MM2_7 net6 vb1 vdd well_154 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT155 vdd well_155 ntap1 A=4e-12 P=8e-6 -MM2_8 net6 vb1 vdd well_155 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT156 vdd well_156 ntap1 A=4e-12 P=8e-6 -MM2_9 net6 vb1 vdd well_156 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT157 vdd well_157 ntap1 A=4e-12 P=8e-6 -MM2_10 net6 vb1 vdd well_157 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT158 vdd well_158 ntap1 A=4e-12 P=8e-6 -MM2_11 net6 vb1 vdd well_158 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT159 vdd well_159 ntap1 A=4e-12 P=8e-6 -MM2_12 net6 vb1 vdd well_159 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT160 vdd well_160 ntap1 A=4e-12 P=8e-6 -MM2_13 net6 vb1 vdd well_160 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT161 vdd well_161 ntap1 A=4e-12 P=8e-6 -MM2_14 net6 vb1 vdd well_161 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT162 vdd well_162 ntap1 A=4e-12 P=8e-6 -MM2_15 net6 vb1 vdd well_162 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT163 vss sub ptap1 A=4e-12 P=8e-6 -MM20_0 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT164 vss sub ptap1 A=4e-12 P=8e-6 -MM20_1 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT165 vss sub ptap1 A=4e-12 P=8e-6 -MM20_2 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT166 vss sub ptap1 A=4e-12 P=8e-6 -MM20_3 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT167 vss sub ptap1 A=4e-12 P=8e-6 -MM20_4 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT168 vss sub ptap1 A=4e-12 P=8e-6 -MM20_5 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT169 vss sub ptap1 A=4e-12 P=8e-6 -MM20_6 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT170 vss sub ptap1 A=4e-12 P=8e-6 -MM20_7 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT171 vss sub ptap1 A=4e-12 P=8e-6 -MM20_8 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT172 vss sub ptap1 A=4e-12 P=8e-6 -MM20_9 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT173 vss sub ptap1 A=4e-12 P=8e-6 -MM20_10 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT174 vss sub ptap1 A=4e-12 P=8e-6 -MM20_11 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT175 vss sub ptap1 A=4e-12 P=8e-6 -MM20_12 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT176 vss sub ptap1 A=4e-12 P=8e-6 -MM20_13 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT177 vss sub ptap1 A=4e-12 P=8e-6 -MM20_14 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT178 vss sub ptap1 A=4e-12 P=8e-6 -MM20_15 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT179 vss sub ptap1 A=4e-12 P=8e-6 -MM23_0 vout net10 vss sub sg13_lv_nmos w=9.59u l=0.51u m=1 -RT180 vss sub ptap1 A=4e-12 P=8e-6 -MM23_1 vout net10 vss sub sg13_lv_nmos w=9.59u l=0.51u m=1 -RT181 vss sub ptap1 A=4e-12 P=8e-6 -MM23_2 vout net10 vss sub sg13_lv_nmos w=9.59u l=0.51u m=1 -RT182 vdd well_182 ntap1 A=4e-12 P=8e-6 -MM3_0 net8 vb1 vdd well_182 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT183 vdd well_183 ntap1 A=4e-12 P=8e-6 -MM3_1 net8 vb1 vdd well_183 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT184 vdd well_184 ntap1 A=4e-12 P=8e-6 -MM3_2 net8 vb1 vdd well_184 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT185 vdd well_185 ntap1 A=4e-12 P=8e-6 -MM3_3 net8 vb1 vdd well_185 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT186 vdd well_186 ntap1 A=4e-12 P=8e-6 -MM3_4 net8 vb1 vdd well_186 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT187 vdd well_187 ntap1 A=4e-12 P=8e-6 -MM3_5 net8 vb1 vdd well_187 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT188 vdd well_188 ntap1 A=4e-12 P=8e-6 -MM3_6 net8 vb1 vdd well_188 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT189 vdd well_189 ntap1 A=4e-12 P=8e-6 -MM3_7 net8 vb1 vdd well_189 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT190 vdd well_190 ntap1 A=4e-12 P=8e-6 -MM3_8 net8 vb1 vdd well_190 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT191 vdd well_191 ntap1 A=4e-12 P=8e-6 -MM3_9 net8 vb1 vdd well_191 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT192 vdd well_192 ntap1 A=4e-12 P=8e-6 -MM3_10 net8 vb1 vdd well_192 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT193 vdd well_193 ntap1 A=4e-12 P=8e-6 -MM3_11 net8 vb1 vdd well_193 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT194 vdd well_194 ntap1 A=4e-12 P=8e-6 -MM3_12 net8 vb1 vdd well_194 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT195 vdd well_195 ntap1 A=4e-12 P=8e-6 -MM3_13 net8 vb1 vdd well_195 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT196 vdd well_196 ntap1 A=4e-12 P=8e-6 -MM3_14 net8 vb1 vdd well_196 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT197 vdd well_197 ntap1 A=4e-12 P=8e-6 -MM3_15 net8 vb1 vdd well_197 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT198 vdd well_198 ntap1 A=4e-12 P=8e-6 -MM4_0 net31 vb1 vdd well_198 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT199 vdd well_199 ntap1 A=4e-12 P=8e-6 -MM4_1 net31 vb1 vdd well_199 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT200 vdd well_200 ntap1 A=4e-12 P=8e-6 -MM4_2 net31 vb1 vdd well_200 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT201 vdd well_201 ntap1 A=4e-12 P=8e-6 -MM4_3 net31 vb1 vdd well_201 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT202 vdd well_202 ntap1 A=4e-12 P=8e-6 -MM4_4 net31 vb1 vdd well_202 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT203 vdd well_203 ntap1 A=4e-12 P=8e-6 -MM4_5 net31 vb1 vdd well_203 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT204 vdd well_204 ntap1 A=4e-12 P=8e-6 -MM4_6 net31 vb1 vdd well_204 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT205 vdd well_205 ntap1 A=4e-12 P=8e-6 -MM4_7 net31 vb1 vdd well_205 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT206 vdd well_206 ntap1 A=4e-12 P=8e-6 -MM4_8 net31 vb1 vdd well_206 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT207 vdd well_207 ntap1 A=4e-12 P=8e-6 -MM4_9 net31 vb1 vdd well_207 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT208 vdd well_208 ntap1 A=4e-12 P=8e-6 -MM4_10 net31 vb1 vdd well_208 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT209 vdd well_209 ntap1 A=4e-12 P=8e-6 -MM4_11 net31 vb1 vdd well_209 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT210 vdd well_210 ntap1 A=4e-12 P=8e-6 -MM4_12 net31 vb1 vdd well_210 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT211 vdd well_211 ntap1 A=4e-12 P=8e-6 -MM4_13 net31 vb1 vdd well_211 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT212 vdd well_212 ntap1 A=4e-12 P=8e-6 -MM4_14 net31 vb1 vdd well_212 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT213 vdd well_213 ntap1 A=4e-12 P=8e-6 -MM4_15 net31 vb1 vdd well_213 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT214 vdd well_214 ntap1 A=4e-12 P=8e-6 -MM4_16 net31 vb1 vdd well_214 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT215 vdd well_215 ntap1 A=4e-12 P=8e-6 -MM4_17 net31 vb1 vdd well_215 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT216 vdd well_216 ntap1 A=4e-12 P=8e-6 -MM4_18 net31 vb1 vdd well_216 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT217 vdd well_217 ntap1 A=4e-12 P=8e-6 -MM4_19 net31 vb1 vdd well_217 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT218 vdd well_218 ntap1 A=4e-12 P=8e-6 -MM4_20 net31 vb1 vdd well_218 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT219 vdd well_219 ntap1 A=4e-12 P=8e-6 -MM4_21 net31 vb1 vdd well_219 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT220 vdd well_220 ntap1 A=4e-12 P=8e-6 -MM4_22 net31 vb1 vdd well_220 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT221 vdd well_221 ntap1 A=4e-12 P=8e-6 -MM4_23 net31 vb1 vdd well_221 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT222 vdd well_222 ntap1 A=4e-12 P=8e-6 -MM4_24 net31 vb1 vdd well_222 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT223 vdd well_223 ntap1 A=4e-12 P=8e-6 -MM4_25 net31 vb1 vdd well_223 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT224 vdd well_224 ntap1 A=4e-12 P=8e-6 -MM4_26 net31 vb1 vdd well_224 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT225 vdd well_225 ntap1 A=4e-12 P=8e-6 -MM4_27 net31 vb1 vdd well_225 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT226 vdd well_226 ntap1 A=4e-12 P=8e-6 -MM4_28 net31 vb1 vdd well_226 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT227 vdd well_227 ntap1 A=4e-12 P=8e-6 -MM4_29 net31 vb1 vdd well_227 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT228 vdd well_228 ntap1 A=4e-12 P=8e-6 -MM4_30 net31 vb1 vdd well_228 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT229 vdd well_229 ntap1 A=4e-12 P=8e-6 -MM4_31 net31 vb1 vdd well_229 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT230 vdd well_230 ntap1 A=4e-12 P=8e-6 -MM5_0 voutn voutn vdd well_230 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT231 vdd well_231 ntap1 A=4e-12 P=8e-6 -MM5_1 voutn voutn vdd well_231 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT232 vdd well_232 ntap1 A=4e-12 P=8e-6 -MM5_2 voutn voutn vdd well_232 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT233 vdd well_233 ntap1 A=4e-12 P=8e-6 -MM5_3 voutn voutn vdd well_233 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT234 vdd well_234 ntap1 A=4e-12 P=8e-6 -MM5_4 voutn voutn vdd well_234 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT235 vdd well_235 ntap1 A=4e-12 P=8e-6 -MM5_5 voutn voutn vdd well_235 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT236 vdd well_236 ntap1 A=4e-12 P=8e-6 -MM5_6 voutn voutn vdd well_236 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT237 vdd well_237 ntap1 A=4e-12 P=8e-6 -MM5_7 voutn voutn vdd well_237 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT238 vdd well_238 ntap1 A=4e-12 P=8e-6 -MM5_8 voutn voutn vdd well_238 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT239 vdd well_239 ntap1 A=4e-12 P=8e-6 -MM5_9 voutn voutn vdd well_239 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT240 vdd well_240 ntap1 A=4e-12 P=8e-6 -MM5_10 voutn voutn vdd well_240 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT241 vdd well_241 ntap1 A=4e-12 P=8e-6 -MM5_11 voutn voutn vdd well_241 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT242 vdd well_242 ntap1 A=4e-12 P=8e-6 -MM5_12 voutn voutn vdd well_242 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT243 vdd well_243 ntap1 A=4e-12 P=8e-6 -MM5_13 voutn voutn vdd well_243 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT244 vdd well_244 ntap1 A=4e-12 P=8e-6 -MM5_14 voutn voutn vdd well_244 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT245 vdd well_245 ntap1 A=4e-12 P=8e-6 -MM5_15 voutn voutn vdd well_245 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT246 vdd well_246 ntap1 A=4e-12 P=8e-6 -MM57_0 vb1 vb2 net2 well_246 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT247 vdd well_247 ntap1 A=4e-12 P=8e-6 -MM57_1 vb1 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sg13_lv_pmos w=2.22u l=0.84u m=1 -RT267 vdd well_267 ntap1 A=4e-12 P=8e-6 -MM58_5 vb4 vb2 net3 well_267 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT268 vdd well_268 ntap1 A=4e-12 P=8e-6 -MM58_6 vb4 vb2 net3 well_268 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT269 vdd well_269 ntap1 A=4e-12 P=8e-6 -MM58_7 vb4 vb2 net3 well_269 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT270 vdd well_270 ntap1 A=4e-12 P=8e-6 -MM58_8 vb4 vb2 net3 well_270 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT271 vdd well_271 ntap1 A=4e-12 P=8e-6 -MM58_9 vb4 vb2 net3 well_271 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT272 vdd well_272 ntap1 A=4e-12 P=8e-6 -MM58_10 vb4 vb2 net3 well_272 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT273 vdd well_273 ntap1 A=4e-12 P=8e-6 -MM58_11 vb4 vb2 net3 well_273 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT274 vdd well_274 ntap1 A=4e-12 P=8e-6 -MM58_12 vb4 vb2 net3 well_274 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT275 vdd well_275 ntap1 A=4e-12 P=8e-6 -MM58_13 vb4 vb2 net3 well_275 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT276 vdd well_276 ntap1 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vdd well_295 ntap1 A=4e-12 P=8e-6 -MM61_1 net7 vb2 net6 well_295 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT296 vdd well_296 ntap1 A=4e-12 P=8e-6 -MM61_2 net7 vb2 net6 well_296 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT297 vdd well_297 ntap1 A=4e-12 P=8e-6 -MM61_3 net7 vb2 net6 well_297 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT298 vdd well_298 ntap1 A=4e-12 P=8e-6 -MM61_4 net7 vb2 net6 well_298 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT299 vdd well_299 ntap1 A=4e-12 P=8e-6 -MM61_5 net7 vb2 net6 well_299 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT300 vdd well_300 ntap1 A=4e-12 P=8e-6 -MM61_6 net7 vb2 net6 well_300 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT301 vdd well_301 ntap1 A=4e-12 P=8e-6 -MM61_7 net7 vb2 net6 well_301 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT302 vdd well_302 ntap1 A=4e-12 P=8e-6 -MM61_8 net7 vb2 net6 well_302 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT303 vdd well_303 ntap1 A=4e-12 P=8e-6 -MM61_9 net7 vb2 net6 well_303 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT304 vdd well_304 ntap1 A=4e-12 P=8e-6 -MM61_10 net7 vb2 net6 well_304 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT305 vdd well_305 ntap1 A=4e-12 P=8e-6 -MM61_11 net7 vb2 net6 well_305 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT306 vdd well_306 ntap1 A=4e-12 P=8e-6 -MM61_12 net7 vb2 net6 well_306 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT307 vdd well_307 ntap1 A=4e-12 P=8e-6 -MM61_13 net7 vb2 net6 well_307 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT308 vdd well_308 ntap1 A=4e-12 P=8e-6 -MM61_14 net7 vb2 net6 well_308 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT309 vdd well_309 ntap1 A=4e-12 P=8e-6 -MM61_15 net7 vb2 net6 well_309 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT310 vdd well_310 ntap1 A=4e-12 P=8e-6 -MM62_0 vb3 vb2 net8 well_310 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT311 vdd well_311 ntap1 A=4e-12 P=8e-6 -MM62_1 vb3 vb2 net8 well_311 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT312 vdd well_312 ntap1 A=4e-12 P=8e-6 -MM62_2 vb3 vb2 net8 well_312 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT313 vdd well_313 ntap1 A=4e-12 P=8e-6 -MM62_3 vb3 vb2 net8 well_313 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT314 vdd well_314 ntap1 A=4e-12 P=8e-6 -MM62_4 vb3 vb2 net8 well_314 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT315 vdd well_315 ntap1 A=4e-12 P=8e-6 -MM62_5 vb3 vb2 net8 well_315 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT316 vdd well_316 ntap1 A=4e-12 P=8e-6 -MM62_6 vb3 vb2 net8 well_316 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT317 vdd well_317 ntap1 A=4e-12 P=8e-6 -MM62_7 vb3 vb2 net8 well_317 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT318 vdd well_318 ntap1 A=4e-12 P=8e-6 -MM62_8 vb3 vb2 net8 well_318 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT319 vdd well_319 ntap1 A=4e-12 P=8e-6 -MM62_9 vb3 vb2 net8 well_319 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT320 vdd well_320 ntap1 A=4e-12 P=8e-6 -MM62_10 vb3 vb2 net8 well_320 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT321 vdd well_321 ntap1 A=4e-12 P=8e-6 -MM62_11 vb3 vb2 net8 well_321 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT322 vdd well_322 ntap1 A=4e-12 P=8e-6 -MM62_12 vb3 vb2 net8 well_322 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT323 vdd well_323 ntap1 A=4e-12 P=8e-6 -MM62_13 vb3 vb2 net8 well_323 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT324 vdd well_324 ntap1 A=4e-12 P=8e-6 -MM62_14 vb3 vb2 net8 well_324 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT325 vdd well_325 ntap1 A=4e-12 P=8e-6 -MM62_15 vb3 vb2 net8 well_325 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT326 vss sub ptap1 A=4e-12 P=8e-6 -MM63_0 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT327 vss sub ptap1 A=4e-12 P=8e-6 -MM63_1 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT328 vss sub ptap1 A=4e-12 P=8e-6 -MM63_2 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT329 vss sub ptap1 A=4e-12 P=8e-6 -MM63_3 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT330 vss sub ptap1 A=4e-12 P=8e-6 -MM63_4 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT331 vss sub ptap1 A=4e-12 P=8e-6 -MM63_5 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT332 vss sub ptap1 A=4e-12 P=8e-6 -MM63_6 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT333 vss sub ptap1 A=4e-12 P=8e-6 -MM63_7 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT334 vss sub ptap1 A=4e-12 P=8e-6 -MM64_0 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT335 vss sub ptap1 A=4e-12 P=8e-6 -MM64_1 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT336 vss sub ptap1 A=4e-12 P=8e-6 -MM64_2 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT337 vss sub ptap1 A=4e-12 P=8e-6 -MM64_3 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT338 vss sub ptap1 A=4e-12 P=8e-6 -MM64_4 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT339 vss sub ptap1 A=4e-12 P=8e-6 -MM64_5 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT340 vss sub ptap1 A=4e-12 P=8e-6 -MM64_6 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT341 vss sub ptap1 A=4e-12 P=8e-6 -MM64_7 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT342 vdd well_342 ntap1 A=4e-12 P=8e-6 -MM65_0 vb2 vb2 vdd well_342 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT343 vdd well_343 ntap1 A=4e-12 P=8e-6 -MM65_1 vb2 vb2 vdd well_343 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT344 vdd well_344 ntap1 A=4e-12 P=8e-6 -MM65_2 vb2 vb2 vdd well_344 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT345 vdd well_345 ntap1 A=4e-12 P=8e-6 -MM65_3 vb2 vb2 vdd well_345 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT346 vdd well_346 ntap1 A=4e-12 P=8e-6 -MM66_0 net10 vb2 net049 well_346 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT347 vdd well_347 ntap1 A=4e-12 P=8e-6 -MM66_1 net10 vb2 net049 well_347 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT348 vdd well_348 ntap1 A=4e-12 P=8e-6 -MM66_2 net10 vb2 net049 well_348 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT349 vdd well_349 ntap1 A=4e-12 P=8e-6 -MM66_3 net10 vb2 net049 well_349 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT350 vdd well_350 ntap1 A=4e-12 P=8e-6 -MM66_4 net10 vb2 net049 well_350 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT351 vdd well_351 ntap1 A=4e-12 P=8e-6 -MM66_5 net10 vb2 net049 well_351 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT352 vdd well_352 ntap1 A=4e-12 P=8e-6 -MM66_6 net10 vb2 net049 well_352 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT353 vdd well_353 ntap1 A=4e-12 P=8e-6 -MM66_7 net10 vb2 net049 well_353 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT354 vdd well_354 ntap1 A=4e-12 P=8e-6 -MM66_8 net10 vb2 net049 well_354 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT355 vdd well_355 ntap1 A=4e-12 P=8e-6 -MM66_9 net10 vb2 net049 well_355 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT356 vdd well_356 ntap1 A=4e-12 P=8e-6 -MM66_10 net10 vb2 net049 well_356 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT357 vdd well_357 ntap1 A=4e-12 P=8e-6 -MM66_11 net10 vb2 net049 well_357 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT358 vdd well_358 ntap1 A=4e-12 P=8e-6 -MM66_12 net10 vb2 net049 well_358 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT359 vdd well_359 ntap1 A=4e-12 P=8e-6 -MM66_13 net10 vb2 net049 well_359 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT360 vdd well_360 ntap1 A=4e-12 P=8e-6 -MM66_14 net10 vb2 net049 well_360 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT361 vdd well_361 ntap1 A=4e-12 P=8e-6 -MM66_15 net10 vb2 net049 well_361 sg13_lv_pmos w=0.97u l=0.81u m=1 -RT362 vss sub ptap1 A=4e-12 P=8e-6 -MM67_0 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT363 vss sub ptap1 A=4e-12 P=8e-6 -MM67_1 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT364 vss sub ptap1 A=4e-12 P=8e-6 -MM67_2 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT365 vss sub ptap1 A=4e-12 P=8e-6 -MM67_3 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT366 vss sub ptap1 A=4e-12 P=8e-6 -MM67_4 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT367 vss sub ptap1 A=4e-12 P=8e-6 -MM67_5 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT368 vss sub ptap1 A=4e-12 P=8e-6 -MM67_6 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT369 vss sub ptap1 A=4e-12 P=8e-6 -MM67_7 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT370 vss sub ptap1 A=4e-12 P=8e-6 -MM67_8 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT371 vss sub ptap1 A=4e-12 P=8e-6 -MM67_9 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT372 vss sub ptap1 A=4e-12 P=8e-6 -MM67_10 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT373 vss sub ptap1 A=4e-12 P=8e-6 -MM67_11 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT374 vss sub ptap1 A=4e-12 P=8e-6 -MM67_12 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT375 vss sub ptap1 A=4e-12 P=8e-6 -MM67_13 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT376 vss sub ptap1 A=4e-12 P=8e-6 -MM67_14 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT377 vss sub ptap1 A=4e-12 P=8e-6 -MM67_15 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT378 vss sub ptap1 A=4e-12 P=8e-6 -MM67_16 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT379 vss sub ptap1 A=4e-12 P=8e-6 -MM67_17 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT380 vss sub ptap1 A=4e-12 P=8e-6 -MM67_18 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT381 vss sub ptap1 A=4e-12 P=8e-6 -MM67_19 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT382 vss sub ptap1 A=4e-12 P=8e-6 -MM67_20 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT383 vss sub ptap1 A=4e-12 P=8e-6 -MM67_21 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT384 vss sub ptap1 A=4e-12 P=8e-6 -MM67_22 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT385 vss sub ptap1 A=4e-12 P=8e-6 -MM67_23 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT386 vss sub ptap1 A=4e-12 P=8e-6 -MM67_24 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT387 vss sub ptap1 A=4e-12 P=8e-6 -MM67_25 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT388 vss sub ptap1 A=4e-12 P=8e-6 -MM67_26 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT389 vss sub ptap1 A=4e-12 P=8e-6 -MM67_27 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT390 vss sub ptap1 A=4e-12 P=8e-6 -MM67_28 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT391 vss sub ptap1 A=4e-12 P=8e-6 -MM67_29 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT392 vss sub ptap1 A=4e-12 P=8e-6 -MM67_30 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT393 vss sub ptap1 A=4e-12 P=8e-6 -MM67_31 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT394 vss sub ptap1 A=4e-12 P=8e-6 -MM67_32 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT395 vss sub ptap1 A=4e-12 P=8e-6 -MM67_33 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT396 vss sub ptap1 A=4e-12 P=8e-6 -MM67_34 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT397 vss sub ptap1 A=4e-12 P=8e-6 -MM67_35 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT398 vss sub ptap1 A=4e-12 P=8e-6 -MM67_36 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT399 vss sub ptap1 A=4e-12 P=8e-6 -MM67_37 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT400 vss sub ptap1 A=4e-12 P=8e-6 -MM67_38 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT401 vss sub ptap1 A=4e-12 P=8e-6 -MM67_39 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT402 vss sub ptap1 A=4e-12 P=8e-6 -MM67_40 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT403 vss sub ptap1 A=4e-12 P=8e-6 -MM67_41 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT404 vss sub ptap1 A=4e-12 P=8e-6 -MM67_42 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT405 vss sub ptap1 A=4e-12 P=8e-6 -MM67_43 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT406 vss sub ptap1 A=4e-12 P=8e-6 -MM67_44 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT407 vss sub ptap1 A=4e-12 P=8e-6 -MM67_45 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT408 vss sub ptap1 A=4e-12 P=8e-6 -MM67_46 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT409 vss sub ptap1 A=4e-12 P=8e-6 -MM67_47 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT410 vss sub ptap1 A=4e-12 P=8e-6 -MM67_48 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT411 vss sub ptap1 A=4e-12 P=8e-6 -MM67_49 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT412 vss sub ptap1 A=4e-12 P=8e-6 -MM67_50 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT413 vss sub ptap1 A=4e-12 P=8e-6 -MM67_51 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT414 vss sub ptap1 A=4e-12 P=8e-6 -MM67_52 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT415 vss sub ptap1 A=4e-12 P=8e-6 -MM67_53 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT416 vss sub ptap1 A=4e-12 P=8e-6 -MM67_54 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT417 vss sub ptap1 A=4e-12 P=8e-6 -MM67_55 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT418 vss sub ptap1 A=4e-12 P=8e-6 -MM67_56 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT419 vss sub ptap1 A=4e-12 P=8e-6 -MM67_57 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT420 vss sub ptap1 A=4e-12 P=8e-6 -MM67_58 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT421 vss sub ptap1 A=4e-12 P=8e-6 -MM67_59 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT422 vss sub ptap1 A=4e-12 P=8e-6 -MM67_60 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT423 vss sub ptap1 A=4e-12 P=8e-6 -MM67_61 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT424 vss sub ptap1 A=4e-12 P=8e-6 -MM67_62 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT425 vss sub ptap1 A=4e-12 P=8e-6 -MM67_63 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -RT426 vss sub ptap1 A=4e-12 P=8e-6 -MM68_0 net1 vb4 vss sub sg13_lv_nmos w=8.71u l=2.9u m=1 -RT427 vss sub ptap1 A=4e-12 P=8e-6 -MM68_1 net1 vb4 vss sub sg13_lv_nmos w=8.71u l=2.9u m=1 -RT428 vss sub ptap1 A=4e-12 P=8e-6 -MM68_2 net1 vb4 vss sub sg13_lv_nmos w=8.71u l=2.9u m=1 -RT429 vss sub ptap1 A=4e-12 P=8e-6 -MM69_0 net10 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -RT430 vss sub ptap1 A=4e-12 P=8e-6 -MM69_1 net10 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -RT431 vss sub ptap1 A=4e-12 P=8e-6 -MM69_2 net10 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -RT432 vdd well_432 ntap1 A=4e-12 P=8e-6 -MM7_0 net049 vb1 vdd well_432 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT433 vdd well_433 ntap1 A=4e-12 P=8e-6 -MM7_1 net049 vb1 vdd well_433 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT434 vdd well_434 ntap1 A=4e-12 P=8e-6 -MM7_2 net049 vb1 vdd well_434 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT435 vdd well_435 ntap1 A=4e-12 P=8e-6 -MM7_3 net049 vb1 vdd well_435 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT436 vdd well_436 ntap1 A=4e-12 P=8e-6 -MM7_4 net049 vb1 vdd well_436 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT437 vdd well_437 ntap1 A=4e-12 P=8e-6 -MM7_5 net049 vb1 vdd well_437 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT438 vdd well_438 ntap1 A=4e-12 P=8e-6 -MM7_6 net049 vb1 vdd well_438 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT439 vdd well_439 ntap1 A=4e-12 P=8e-6 -MM7_7 net049 vb1 vdd well_439 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT440 vdd well_440 ntap1 A=4e-12 P=8e-6 -MM7_8 net049 vb1 vdd well_440 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT441 vdd well_441 ntap1 A=4e-12 P=8e-6 -MM7_9 net049 vb1 vdd well_441 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT442 vdd well_442 ntap1 A=4e-12 P=8e-6 -MM7_10 net049 vb1 vdd well_442 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT443 vdd well_443 ntap1 A=4e-12 P=8e-6 -MM7_11 net049 vb1 vdd well_443 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT444 vdd well_444 ntap1 A=4e-12 P=8e-6 -MM7_12 net049 vb1 vdd well_444 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT445 vdd well_445 ntap1 A=4e-12 P=8e-6 -MM7_13 net049 vb1 vdd well_445 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT446 vdd well_446 ntap1 A=4e-12 P=8e-6 -MM7_14 net049 vb1 vdd well_446 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT447 vdd well_447 ntap1 A=4e-12 P=8e-6 -MM7_15 net049 vb1 vdd well_447 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT448 vdd well_448 ntap1 A=4e-12 P=8e-6 -MM7_16 net049 vb1 vdd well_448 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT449 vdd well_449 ntap1 A=4e-12 P=8e-6 -MM7_17 net049 vb1 vdd well_449 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT450 vdd well_450 ntap1 A=4e-12 P=8e-6 -MM7_18 net049 vb1 vdd well_450 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT451 vdd well_451 ntap1 A=4e-12 P=8e-6 -MM7_19 net049 vb1 vdd well_451 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT452 vdd well_452 ntap1 A=4e-12 P=8e-6 -MM7_20 net049 vb1 vdd well_452 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT453 vdd well_453 ntap1 A=4e-12 P=8e-6 -MM7_21 net049 vb1 vdd well_453 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT454 vdd well_454 ntap1 A=4e-12 P=8e-6 -MM7_22 net049 vb1 vdd well_454 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT455 vdd well_455 ntap1 A=4e-12 P=8e-6 -MM7_23 net049 vb1 vdd well_455 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT456 vdd well_456 ntap1 A=4e-12 P=8e-6 -MM7_24 net049 vb1 vdd well_456 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT457 vdd well_457 ntap1 A=4e-12 P=8e-6 -MM7_25 net049 vb1 vdd well_457 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT458 vdd well_458 ntap1 A=4e-12 P=8e-6 -MM7_26 net049 vb1 vdd well_458 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT459 vdd well_459 ntap1 A=4e-12 P=8e-6 -MM7_27 net049 vb1 vdd well_459 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT460 vdd well_460 ntap1 A=4e-12 P=8e-6 -MM7_28 net049 vb1 vdd well_460 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT461 vdd well_461 ntap1 A=4e-12 P=8e-6 -MM7_29 net049 vb1 vdd well_461 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT462 vdd well_462 ntap1 A=4e-12 P=8e-6 -MM7_30 net049 vb1 vdd well_462 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT463 vdd well_463 ntap1 A=4e-12 P=8e-6 -MM7_31 net049 vb1 vdd well_463 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT464 vdd well_464 ntap1 A=4e-12 P=8e-6 -MM7_32 net049 vb1 vdd well_464 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT465 vdd well_465 ntap1 A=4e-12 P=8e-6 -MM7_33 net049 vb1 vdd well_465 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT466 vdd well_466 ntap1 A=4e-12 P=8e-6 -MM7_34 net049 vb1 vdd well_466 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT467 vdd well_467 ntap1 A=4e-12 P=8e-6 -MM7_35 net049 vb1 vdd well_467 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT468 vdd well_468 ntap1 A=4e-12 P=8e-6 -MM7_36 net049 vb1 vdd well_468 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT469 vdd well_469 ntap1 A=4e-12 P=8e-6 -MM7_37 net049 vb1 vdd well_469 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT470 vdd well_470 ntap1 A=4e-12 P=8e-6 -MM7_38 net049 vb1 vdd well_470 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT471 vdd well_471 ntap1 A=4e-12 P=8e-6 -MM7_39 net049 vb1 vdd well_471 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT472 vdd well_472 ntap1 A=4e-12 P=8e-6 -MM7_40 net049 vb1 vdd well_472 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT473 vdd well_473 ntap1 A=4e-12 P=8e-6 -MM7_41 net049 vb1 vdd well_473 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT474 vdd well_474 ntap1 A=4e-12 P=8e-6 -MM7_42 net049 vb1 vdd well_474 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT475 vdd well_475 ntap1 A=4e-12 P=8e-6 -MM7_43 net049 vb1 vdd well_475 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT476 vdd well_476 ntap1 A=4e-12 P=8e-6 -MM7_44 net049 vb1 vdd well_476 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT477 vdd well_477 ntap1 A=4e-12 P=8e-6 -MM7_45 net049 vb1 vdd well_477 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT478 vdd well_478 ntap1 A=4e-12 P=8e-6 -MM7_46 net049 vb1 vdd well_478 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT479 vdd well_479 ntap1 A=4e-12 P=8e-6 -MM7_47 net049 vb1 vdd well_479 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT480 vdd well_480 ntap1 A=4e-12 P=8e-6 -MM7_48 net049 vb1 vdd well_480 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT481 vdd well_481 ntap1 A=4e-12 P=8e-6 -MM7_49 net049 vb1 vdd well_481 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT482 vdd well_482 ntap1 A=4e-12 P=8e-6 -MM7_50 net049 vb1 vdd well_482 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT483 vdd well_483 ntap1 A=4e-12 P=8e-6 -MM7_51 net049 vb1 vdd well_483 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT484 vdd well_484 ntap1 A=4e-12 P=8e-6 -MM7_52 net049 vb1 vdd well_484 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT485 vdd well_485 ntap1 A=4e-12 P=8e-6 -MM7_53 net049 vb1 vdd well_485 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT486 vdd well_486 ntap1 A=4e-12 P=8e-6 -MM7_54 net049 vb1 vdd well_486 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT487 vdd well_487 ntap1 A=4e-12 P=8e-6 -MM7_55 net049 vb1 vdd well_487 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT488 vdd well_488 ntap1 A=4e-12 P=8e-6 -MM7_56 net049 vb1 vdd well_488 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT489 vdd well_489 ntap1 A=4e-12 P=8e-6 -MM7_57 net049 vb1 vdd well_489 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT490 vdd well_490 ntap1 A=4e-12 P=8e-6 -MM7_58 net049 vb1 vdd well_490 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT491 vdd well_491 ntap1 A=4e-12 P=8e-6 -MM7_59 net049 vb1 vdd well_491 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT492 vdd well_492 ntap1 A=4e-12 P=8e-6 -MM7_60 net049 vb1 vdd well_492 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT493 vdd well_493 ntap1 A=4e-12 P=8e-6 -MM7_61 net049 vb1 vdd well_493 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT494 vdd well_494 ntap1 A=4e-12 P=8e-6 -MM7_62 net049 vb1 vdd well_494 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT495 vdd well_495 ntap1 A=4e-12 P=8e-6 -MM7_63 net049 vb1 vdd well_495 sg13_lv_pmos w=2.22u l=0.84u m=1 -RT496 vss sub ptap1 A=4e-12 P=8e-6 -MM70_0 net1 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -RT497 vss sub ptap1 A=4e-12 P=8e-6 -MM70_1 net1 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -RT498 vss sub ptap1 A=4e-12 P=8e-6 -MM70_2 net1 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -RT499 net31 well_499 ntap1 A=4e-12 P=8e-6 -MM8_0 dm_2 vinn net31 well_499 sg13_lv_pmos w=9.9u l=1.89u m=1 -RT500 net31 well_500 ntap1 A=4e-12 P=8e-6 -MM8_1 dm_2 vinn net31 well_500 sg13_lv_pmos w=9.9u l=1.89u m=1 -RT501 net31 well_501 ntap1 A=4e-12 P=8e-6 -MM8_2 dm_2 vinn net31 well_501 sg13_lv_pmos w=9.9u l=1.89u m=1 -RT502 net31 well_502 ntap1 A=4e-12 P=8e-6 -MM9_0 net063 vinp net31 well_502 sg13_lv_pmos w=9.9u l=1.89u m=1 -RT503 net31 well_503 ntap1 A=4e-12 P=8e-6 -MM9_1 net063 vinp net31 well_503 sg13_lv_pmos w=9.9u l=1.89u m=1 -RT504 net31 well_504 ntap1 A=4e-12 P=8e-6 -MM9_2 net063 vinp net31 well_504 sg13_lv_pmos w=9.9u l=1.89u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM0 net2 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM1 net3 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM10 net043 voutp vdd vdd sg13_lv_pmos w=4.88u l=2.36u m=24 +MM11 vout voutp vdd vdd sg13_lv_pmos w=4.46u l=0.98u m=9 +MM12 vb4 vb3 net54 vss sg13_lv_nmos w=0.47u l=2.1u m=8 +MM13 net7 vb3 net56 vss sg13_lv_nmos w=0.47u l=2.1u m=8 +MM14 vb3 vb3 vss vss sg13_lv_nmos w=0.47u l=2.1u m=2 +MM15 voutn vb3 dm_2 vss sg13_lv_nmos w=0.47u l=2.1u m=16 +MM16 voutp vb3 net063 vss sg13_lv_nmos w=0.47u l=2.1u m=16 +MM17 net54 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=8 +MM18 net56 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=8 +MM19 dm_2 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=16 +MM2 net6 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM20 net063 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=16 +MM23 vout net10 vss vss sg13_lv_nmos w=9.59u l=0.51u m=3 +MM3 net8 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM4 net31 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=32 +MM5 voutn voutn vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM57 vb1 vb2 net2 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM58 vb4 vb2 net3 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM6 voutp voutn vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM61 net7 vb2 net6 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM62 vb3 vb2 net8 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +MM63 vb2 vb3 net9 vss sg13_lv_nmos w=0.47u l=2.1u m=8 +MM64 net9 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=8 +MM65 vb2 vb2 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=4 +MM66 net10 vb2 net049 vdd sg13_lv_pmos w=0.97u l=0.81u m=16 +MM67 net043 vb3 net1 vss sg13_lv_nmos w=0.47u l=2.1u m=64 +MM68 net1 vb4 vss vss sg13_lv_nmos w=8.71u l=2.9u m=3 +MM69 net10 net043 vss vss sg13_lv_nmos w=1.68u l=8.05u m=3 +MM7 net049 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=64 +MM70 net1 net043 vss vss sg13_lv_nmos w=1.68u l=8.05u m=3 +MM8 dm_2 vinn net31 net31 sg13_lv_pmos w=9.9u l=1.89u m=3 +MM9 net063 vinp net31 net31 sg13_lv_pmos w=9.9u l=1.89u m=3 C0_0 voutp vout cap_cmim w=36.06u l=36.06u m=1 -C1_0 net10 net4 cap_cmim w=37.96u l=37.96u m=1 -C1_1 net10 net4 cap_cmim w=37.96u l=37.96u m=1 -RR0_0 net4 R0_s1 sub rhigh w=.5u l=82.46u m=1 b=0 -RR0_1 R0_s1 R0_s2 sub rhigh w=.5u l=82.46u m=1 b=0 -RR0_2 R0_s2 R0_s3 sub rhigh w=.5u l=82.46u m=1 b=0 -RR0_3 R0_s3 R0_s4 sub rhigh w=.5u l=82.46u m=1 b=0 -RR0_4 R0_s4 R0_s5 sub rhigh w=.5u l=82.46u m=1 b=0 -RR0_5 R0_s5 vss sub rhigh w=.5u l=82.46u m=1 b=0 +C1_0 net10 net4 cap_cmim w=37.96u l=37.96u m=2 +RR0_0 net4 R0_s1 vss rhigh w=.5u l=82.46u m=1 b=0 +RR0_1 R0_s1 R0_s2 vss rhigh w=.5u l=82.46u m=1 b=0 +RR0_2 R0_s2 R0_s3 vss rhigh w=.5u l=82.46u m=1 b=0 +RR0_3 R0_s3 R0_s4 vss rhigh w=.5u l=82.46u m=1 b=0 +RR0_4 R0_s4 R0_s5 vss rhigh w=.5u l=82.46u m=1 b=0 +RR0_5 R0_s5 vss vss rhigh w=.5u l=82.46u m=1 b=0 .ends amp_011_peng_iac diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.spice index 613b59fc3c20b7c9b9316a88bc3052753915c1e3..50c242f07ac6cc319bbfcacbcb10cb80bd5e39af 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.spice @@ -1,1024 +1,46 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_011_peng_iac vss vdd vinn vinp vout vb1 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM0_0 net2 vb1 vdd well_0 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM0_1 net2 vb1 vdd well_1 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM0_2 net2 vb1 vdd well_2 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM0_3 net2 vb1 vdd well_3 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM0_4 net2 vb1 vdd well_4 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM0_5 net2 vb1 vdd well_5 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -XM0_6 net2 vb1 vdd well_6 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM0_7 net2 vb1 vdd well_7 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM0_8 net2 vb1 vdd well_8 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM0_9 net2 vb1 vdd well_9 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM0_10 net2 vb1 vdd well_10 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM0_11 net2 vb1 vdd well_11 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM0_12 net2 vb1 vdd well_12 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM0_13 net2 vb1 vdd well_13 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM0_14 net2 vb1 vdd well_14 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM0_15 net2 vb1 vdd well_15 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -XM1_0 net3 vb1 vdd well_16 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM1_1 net3 vb1 vdd well_17 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -XM1_2 net3 vb1 vdd well_18 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM1_3 net3 vb1 vdd well_19 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM1_4 net3 vb1 vdd well_20 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM1_5 net3 vb1 vdd well_21 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM1_6 net3 vb1 vdd well_22 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -XM1_7 net3 vb1 vdd well_23 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -XM1_8 net3 vb1 vdd well_24 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -XM1_9 net3 vb1 vdd well_25 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -XM1_10 net3 vb1 vdd well_26 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -XM1_11 net3 vb1 vdd well_27 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -XM1_12 net3 vb1 vdd well_28 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -XM1_13 net3 vb1 vdd well_29 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -XM1_14 net3 vb1 vdd well_30 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -XM1_15 net3 vb1 vdd well_31 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -XM10_0 net043 voutp vdd well_32 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT33 vdd well_33 ntap1 A=4e-12 P=8e-6 -XM10_1 net043 voutp vdd well_33 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -XM10_2 net043 voutp vdd well_34 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -XM10_3 net043 voutp vdd well_35 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -XM10_4 net043 voutp vdd well_36 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -XM10_5 net043 voutp vdd well_37 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -XM10_6 net043 voutp vdd well_38 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -XM10_7 net043 voutp vdd well_39 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT40 vdd well_40 ntap1 A=4e-12 P=8e-6 -XM10_8 net043 voutp vdd well_40 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -XM10_9 net043 voutp vdd well_41 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT42 vdd well_42 ntap1 A=4e-12 P=8e-6 -XM10_10 net043 voutp vdd well_42 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -XM10_11 net043 voutp vdd well_43 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -XM10_12 net043 voutp vdd well_44 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -XM10_13 net043 voutp vdd well_45 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -XM10_14 net043 voutp vdd well_46 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -XM10_15 net043 voutp vdd well_47 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -XM10_16 net043 voutp vdd well_48 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -XM10_17 net043 voutp vdd well_49 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -XM10_18 net043 voutp vdd well_50 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -XM10_19 net043 voutp vdd well_51 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -XM10_20 net043 voutp vdd well_52 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -XM10_21 net043 voutp vdd well_53 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -XM10_22 net043 voutp vdd well_54 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -XM10_23 net043 voutp vdd well_55 sg13_lv_pmos w=4.88u l=2.36u m=1 -XT56 vdd well_56 ntap1 A=4e-12 P=8e-6 -XM11_0 vout voutp vdd well_56 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT57 vdd well_57 ntap1 A=4e-12 P=8e-6 -XM11_1 vout voutp vdd well_57 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT58 vdd well_58 ntap1 A=4e-12 P=8e-6 -XM11_2 vout voutp vdd well_58 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT59 vdd well_59 ntap1 A=4e-12 P=8e-6 -XM11_3 vout voutp vdd well_59 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT60 vdd well_60 ntap1 A=4e-12 P=8e-6 -XM11_4 vout voutp vdd well_60 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT61 vdd well_61 ntap1 A=4e-12 P=8e-6 -XM11_5 vout voutp vdd well_61 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT62 vdd well_62 ntap1 A=4e-12 P=8e-6 -XM11_6 vout voutp vdd well_62 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT63 vdd well_63 ntap1 A=4e-12 P=8e-6 -XM11_7 vout voutp vdd well_63 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT64 vdd well_64 ntap1 A=4e-12 P=8e-6 -XM11_8 vout voutp vdd well_64 sg13_lv_pmos w=4.46u l=0.98u m=1 -XT65 vss sub ptap1 A=4e-12 P=8e-6 -XM12_0 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT66 vss sub ptap1 A=4e-12 P=8e-6 -XM12_1 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT67 vss sub ptap1 A=4e-12 P=8e-6 -XM12_2 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT68 vss sub ptap1 A=4e-12 P=8e-6 -XM12_3 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT69 vss sub ptap1 A=4e-12 P=8e-6 -XM12_4 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT70 vss sub ptap1 A=4e-12 P=8e-6 -XM12_5 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT71 vss sub ptap1 A=4e-12 P=8e-6 -XM12_6 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT72 vss sub ptap1 A=4e-12 P=8e-6 -XM12_7 vb4 vb3 net54 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT73 vss sub ptap1 A=4e-12 P=8e-6 -XM13_0 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT74 vss sub ptap1 A=4e-12 P=8e-6 -XM13_1 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT75 vss sub ptap1 A=4e-12 P=8e-6 -XM13_2 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT76 vss sub ptap1 A=4e-12 P=8e-6 -XM13_3 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT77 vss sub ptap1 A=4e-12 P=8e-6 -XM13_4 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT78 vss sub ptap1 A=4e-12 P=8e-6 -XM13_5 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT79 vss sub ptap1 A=4e-12 P=8e-6 -XM13_6 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT80 vss sub ptap1 A=4e-12 P=8e-6 -XM13_7 net7 vb3 net56 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT81 vss sub ptap1 A=4e-12 P=8e-6 -XM14_0 vb3 vb3 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT82 vss sub ptap1 A=4e-12 P=8e-6 -XM14_1 vb3 vb3 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT83 vss sub ptap1 A=4e-12 P=8e-6 -XM15_0 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT84 vss sub ptap1 A=4e-12 P=8e-6 -XM15_1 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT85 vss sub ptap1 A=4e-12 P=8e-6 -XM15_2 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT86 vss sub ptap1 A=4e-12 P=8e-6 -XM15_3 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT87 vss sub ptap1 A=4e-12 P=8e-6 -XM15_4 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT88 vss sub ptap1 A=4e-12 P=8e-6 -XM15_5 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT89 vss sub ptap1 A=4e-12 P=8e-6 -XM15_6 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT90 vss sub ptap1 A=4e-12 P=8e-6 -XM15_7 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT91 vss sub ptap1 A=4e-12 P=8e-6 -XM15_8 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT92 vss sub ptap1 A=4e-12 P=8e-6 -XM15_9 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT93 vss sub ptap1 A=4e-12 P=8e-6 -XM15_10 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT94 vss sub ptap1 A=4e-12 P=8e-6 -XM15_11 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT95 vss sub ptap1 A=4e-12 P=8e-6 -XM15_12 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT96 vss sub ptap1 A=4e-12 P=8e-6 -XM15_13 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT97 vss sub ptap1 A=4e-12 P=8e-6 -XM15_14 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT98 vss sub ptap1 A=4e-12 P=8e-6 -XM15_15 voutn vb3 dm_2 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT99 vss sub ptap1 A=4e-12 P=8e-6 -XM16_0 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT100 vss sub ptap1 A=4e-12 P=8e-6 -XM16_1 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT101 vss sub ptap1 A=4e-12 P=8e-6 -XM16_2 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT102 vss sub ptap1 A=4e-12 P=8e-6 -XM16_3 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT103 vss sub ptap1 A=4e-12 P=8e-6 -XM16_4 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT104 vss sub ptap1 A=4e-12 P=8e-6 -XM16_5 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT105 vss sub ptap1 A=4e-12 P=8e-6 -XM16_6 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT106 vss sub ptap1 A=4e-12 P=8e-6 -XM16_7 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT107 vss sub ptap1 A=4e-12 P=8e-6 -XM16_8 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT108 vss sub ptap1 A=4e-12 P=8e-6 -XM16_9 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT109 vss sub ptap1 A=4e-12 P=8e-6 -XM16_10 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT110 vss sub ptap1 A=4e-12 P=8e-6 -XM16_11 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT111 vss sub ptap1 A=4e-12 P=8e-6 -XM16_12 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT112 vss sub ptap1 A=4e-12 P=8e-6 -XM16_13 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT113 vss sub ptap1 A=4e-12 P=8e-6 -XM16_14 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT114 vss sub ptap1 A=4e-12 P=8e-6 -XM16_15 voutp vb3 net063 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT115 vss sub ptap1 A=4e-12 P=8e-6 -XM17_0 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT116 vss sub ptap1 A=4e-12 P=8e-6 -XM17_1 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT117 vss sub ptap1 A=4e-12 P=8e-6 -XM17_2 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT118 vss sub ptap1 A=4e-12 P=8e-6 -XM17_3 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT119 vss sub ptap1 A=4e-12 P=8e-6 -XM17_4 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT120 vss sub ptap1 A=4e-12 P=8e-6 -XM17_5 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT121 vss sub ptap1 A=4e-12 P=8e-6 -XM17_6 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT122 vss sub ptap1 A=4e-12 P=8e-6 -XM17_7 net54 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT123 vss sub ptap1 A=4e-12 P=8e-6 -XM18_0 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT124 vss sub ptap1 A=4e-12 P=8e-6 -XM18_1 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT125 vss sub ptap1 A=4e-12 P=8e-6 -XM18_2 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT126 vss sub ptap1 A=4e-12 P=8e-6 -XM18_3 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT127 vss sub ptap1 A=4e-12 P=8e-6 -XM18_4 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT128 vss sub ptap1 A=4e-12 P=8e-6 -XM18_5 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT129 vss sub ptap1 A=4e-12 P=8e-6 -XM18_6 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT130 vss sub ptap1 A=4e-12 P=8e-6 -XM18_7 net56 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT131 vss sub ptap1 A=4e-12 P=8e-6 -XM19_0 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT132 vss sub ptap1 A=4e-12 P=8e-6 -XM19_1 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT133 vss sub ptap1 A=4e-12 P=8e-6 -XM19_2 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT134 vss sub ptap1 A=4e-12 P=8e-6 -XM19_3 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT135 vss sub ptap1 A=4e-12 P=8e-6 -XM19_4 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT136 vss sub ptap1 A=4e-12 P=8e-6 -XM19_5 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT137 vss sub ptap1 A=4e-12 P=8e-6 -XM19_6 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT138 vss sub ptap1 A=4e-12 P=8e-6 -XM19_7 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT139 vss sub ptap1 A=4e-12 P=8e-6 -XM19_8 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT140 vss sub ptap1 A=4e-12 P=8e-6 -XM19_9 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT141 vss sub ptap1 A=4e-12 P=8e-6 -XM19_10 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT142 vss sub ptap1 A=4e-12 P=8e-6 -XM19_11 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT143 vss sub ptap1 A=4e-12 P=8e-6 -XM19_12 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT144 vss sub ptap1 A=4e-12 P=8e-6 -XM19_13 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT145 vss sub ptap1 A=4e-12 P=8e-6 -XM19_14 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT146 vss sub ptap1 A=4e-12 P=8e-6 -XM19_15 dm_2 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT147 vdd well_147 ntap1 A=4e-12 P=8e-6 -XM2_0 net6 vb1 vdd well_147 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT148 vdd well_148 ntap1 A=4e-12 P=8e-6 -XM2_1 net6 vb1 vdd well_148 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT149 vdd well_149 ntap1 A=4e-12 P=8e-6 -XM2_2 net6 vb1 vdd well_149 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT150 vdd well_150 ntap1 A=4e-12 P=8e-6 -XM2_3 net6 vb1 vdd well_150 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT151 vdd well_151 ntap1 A=4e-12 P=8e-6 -XM2_4 net6 vb1 vdd well_151 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT152 vdd well_152 ntap1 A=4e-12 P=8e-6 -XM2_5 net6 vb1 vdd well_152 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT153 vdd well_153 ntap1 A=4e-12 P=8e-6 -XM2_6 net6 vb1 vdd well_153 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT154 vdd well_154 ntap1 A=4e-12 P=8e-6 -XM2_7 net6 vb1 vdd well_154 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT155 vdd well_155 ntap1 A=4e-12 P=8e-6 -XM2_8 net6 vb1 vdd well_155 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT156 vdd well_156 ntap1 A=4e-12 P=8e-6 -XM2_9 net6 vb1 vdd well_156 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT157 vdd well_157 ntap1 A=4e-12 P=8e-6 -XM2_10 net6 vb1 vdd well_157 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT158 vdd well_158 ntap1 A=4e-12 P=8e-6 -XM2_11 net6 vb1 vdd well_158 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT159 vdd well_159 ntap1 A=4e-12 P=8e-6 -XM2_12 net6 vb1 vdd well_159 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT160 vdd well_160 ntap1 A=4e-12 P=8e-6 -XM2_13 net6 vb1 vdd well_160 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT161 vdd well_161 ntap1 A=4e-12 P=8e-6 -XM2_14 net6 vb1 vdd well_161 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT162 vdd well_162 ntap1 A=4e-12 P=8e-6 -XM2_15 net6 vb1 vdd well_162 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT163 vss sub ptap1 A=4e-12 P=8e-6 -XM20_0 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT164 vss sub ptap1 A=4e-12 P=8e-6 -XM20_1 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT165 vss sub ptap1 A=4e-12 P=8e-6 -XM20_2 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT166 vss sub ptap1 A=4e-12 P=8e-6 -XM20_3 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT167 vss sub ptap1 A=4e-12 P=8e-6 -XM20_4 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT168 vss sub ptap1 A=4e-12 P=8e-6 -XM20_5 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT169 vss sub ptap1 A=4e-12 P=8e-6 -XM20_6 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT170 vss sub ptap1 A=4e-12 P=8e-6 -XM20_7 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT171 vss sub ptap1 A=4e-12 P=8e-6 -XM20_8 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT172 vss sub ptap1 A=4e-12 P=8e-6 -XM20_9 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT173 vss sub ptap1 A=4e-12 P=8e-6 -XM20_10 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT174 vss sub ptap1 A=4e-12 P=8e-6 -XM20_11 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT175 vss sub ptap1 A=4e-12 P=8e-6 -XM20_12 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT176 vss sub ptap1 A=4e-12 P=8e-6 -XM20_13 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT177 vss sub ptap1 A=4e-12 P=8e-6 -XM20_14 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT178 vss sub ptap1 A=4e-12 P=8e-6 -XM20_15 net063 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT179 vss sub ptap1 A=4e-12 P=8e-6 -XM23_0 vout net10 vss sub sg13_lv_nmos w=9.59u l=0.51u m=1 -XT180 vss sub ptap1 A=4e-12 P=8e-6 -XM23_1 vout net10 vss sub sg13_lv_nmos w=9.59u l=0.51u m=1 -XT181 vss sub ptap1 A=4e-12 P=8e-6 -XM23_2 vout net10 vss sub sg13_lv_nmos w=9.59u l=0.51u m=1 -XT182 vdd well_182 ntap1 A=4e-12 P=8e-6 -XM3_0 net8 vb1 vdd well_182 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT183 vdd well_183 ntap1 A=4e-12 P=8e-6 -XM3_1 net8 vb1 vdd well_183 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT184 vdd well_184 ntap1 A=4e-12 P=8e-6 -XM3_2 net8 vb1 vdd well_184 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT185 vdd well_185 ntap1 A=4e-12 P=8e-6 -XM3_3 net8 vb1 vdd well_185 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT186 vdd well_186 ntap1 A=4e-12 P=8e-6 -XM3_4 net8 vb1 vdd well_186 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT187 vdd well_187 ntap1 A=4e-12 P=8e-6 -XM3_5 net8 vb1 vdd well_187 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT188 vdd well_188 ntap1 A=4e-12 P=8e-6 -XM3_6 net8 vb1 vdd well_188 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT189 vdd well_189 ntap1 A=4e-12 P=8e-6 -XM3_7 net8 vb1 vdd well_189 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT190 vdd well_190 ntap1 A=4e-12 P=8e-6 -XM3_8 net8 vb1 vdd well_190 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT191 vdd well_191 ntap1 A=4e-12 P=8e-6 -XM3_9 net8 vb1 vdd well_191 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT192 vdd well_192 ntap1 A=4e-12 P=8e-6 -XM3_10 net8 vb1 vdd well_192 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT193 vdd well_193 ntap1 A=4e-12 P=8e-6 -XM3_11 net8 vb1 vdd well_193 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT194 vdd well_194 ntap1 A=4e-12 P=8e-6 -XM3_12 net8 vb1 vdd well_194 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT195 vdd well_195 ntap1 A=4e-12 P=8e-6 -XM3_13 net8 vb1 vdd well_195 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT196 vdd well_196 ntap1 A=4e-12 P=8e-6 -XM3_14 net8 vb1 vdd well_196 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT197 vdd well_197 ntap1 A=4e-12 P=8e-6 -XM3_15 net8 vb1 vdd well_197 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT198 vdd well_198 ntap1 A=4e-12 P=8e-6 -XM4_0 net31 vb1 vdd well_198 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT199 vdd well_199 ntap1 A=4e-12 P=8e-6 -XM4_1 net31 vb1 vdd well_199 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT200 vdd well_200 ntap1 A=4e-12 P=8e-6 -XM4_2 net31 vb1 vdd well_200 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT201 vdd well_201 ntap1 A=4e-12 P=8e-6 -XM4_3 net31 vb1 vdd well_201 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT202 vdd well_202 ntap1 A=4e-12 P=8e-6 -XM4_4 net31 vb1 vdd well_202 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT203 vdd well_203 ntap1 A=4e-12 P=8e-6 -XM4_5 net31 vb1 vdd well_203 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT204 vdd well_204 ntap1 A=4e-12 P=8e-6 -XM4_6 net31 vb1 vdd well_204 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT205 vdd well_205 ntap1 A=4e-12 P=8e-6 -XM4_7 net31 vb1 vdd well_205 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT206 vdd well_206 ntap1 A=4e-12 P=8e-6 -XM4_8 net31 vb1 vdd well_206 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT207 vdd well_207 ntap1 A=4e-12 P=8e-6 -XM4_9 net31 vb1 vdd well_207 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT208 vdd well_208 ntap1 A=4e-12 P=8e-6 -XM4_10 net31 vb1 vdd well_208 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT209 vdd well_209 ntap1 A=4e-12 P=8e-6 -XM4_11 net31 vb1 vdd well_209 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT210 vdd well_210 ntap1 A=4e-12 P=8e-6 -XM4_12 net31 vb1 vdd well_210 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT211 vdd well_211 ntap1 A=4e-12 P=8e-6 -XM4_13 net31 vb1 vdd well_211 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT212 vdd well_212 ntap1 A=4e-12 P=8e-6 -XM4_14 net31 vb1 vdd well_212 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT213 vdd well_213 ntap1 A=4e-12 P=8e-6 -XM4_15 net31 vb1 vdd well_213 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT214 vdd well_214 ntap1 A=4e-12 P=8e-6 -XM4_16 net31 vb1 vdd well_214 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT215 vdd well_215 ntap1 A=4e-12 P=8e-6 -XM4_17 net31 vb1 vdd well_215 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT216 vdd well_216 ntap1 A=4e-12 P=8e-6 -XM4_18 net31 vb1 vdd well_216 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT217 vdd well_217 ntap1 A=4e-12 P=8e-6 -XM4_19 net31 vb1 vdd well_217 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT218 vdd well_218 ntap1 A=4e-12 P=8e-6 -XM4_20 net31 vb1 vdd well_218 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT219 vdd well_219 ntap1 A=4e-12 P=8e-6 -XM4_21 net31 vb1 vdd well_219 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT220 vdd well_220 ntap1 A=4e-12 P=8e-6 -XM4_22 net31 vb1 vdd well_220 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT221 vdd well_221 ntap1 A=4e-12 P=8e-6 -XM4_23 net31 vb1 vdd well_221 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT222 vdd well_222 ntap1 A=4e-12 P=8e-6 -XM4_24 net31 vb1 vdd well_222 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT223 vdd well_223 ntap1 A=4e-12 P=8e-6 -XM4_25 net31 vb1 vdd well_223 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT224 vdd well_224 ntap1 A=4e-12 P=8e-6 -XM4_26 net31 vb1 vdd well_224 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT225 vdd well_225 ntap1 A=4e-12 P=8e-6 -XM4_27 net31 vb1 vdd well_225 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT226 vdd well_226 ntap1 A=4e-12 P=8e-6 -XM4_28 net31 vb1 vdd well_226 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT227 vdd well_227 ntap1 A=4e-12 P=8e-6 -XM4_29 net31 vb1 vdd well_227 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT228 vdd well_228 ntap1 A=4e-12 P=8e-6 -XM4_30 net31 vb1 vdd well_228 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT229 vdd well_229 ntap1 A=4e-12 P=8e-6 -XM4_31 net31 vb1 vdd well_229 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT230 vdd well_230 ntap1 A=4e-12 P=8e-6 -XM5_0 voutn voutn vdd well_230 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT231 vdd well_231 ntap1 A=4e-12 P=8e-6 -XM5_1 voutn voutn vdd well_231 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT232 vdd well_232 ntap1 A=4e-12 P=8e-6 -XM5_2 voutn voutn vdd well_232 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT233 vdd well_233 ntap1 A=4e-12 P=8e-6 -XM5_3 voutn voutn vdd well_233 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT234 vdd well_234 ntap1 A=4e-12 P=8e-6 -XM5_4 voutn voutn vdd well_234 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT235 vdd well_235 ntap1 A=4e-12 P=8e-6 -XM5_5 voutn voutn vdd well_235 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT236 vdd well_236 ntap1 A=4e-12 P=8e-6 -XM5_6 voutn voutn vdd well_236 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT237 vdd well_237 ntap1 A=4e-12 P=8e-6 -XM5_7 voutn voutn vdd well_237 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT238 vdd well_238 ntap1 A=4e-12 P=8e-6 -XM5_8 voutn voutn vdd well_238 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT239 vdd well_239 ntap1 A=4e-12 P=8e-6 -XM5_9 voutn voutn vdd well_239 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT240 vdd well_240 ntap1 A=4e-12 P=8e-6 -XM5_10 voutn voutn vdd well_240 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT241 vdd well_241 ntap1 A=4e-12 P=8e-6 -XM5_11 voutn voutn vdd well_241 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT242 vdd well_242 ntap1 A=4e-12 P=8e-6 -XM5_12 voutn voutn vdd well_242 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT243 vdd well_243 ntap1 A=4e-12 P=8e-6 -XM5_13 voutn voutn vdd well_243 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT244 vdd well_244 ntap1 A=4e-12 P=8e-6 -XM5_14 voutn voutn vdd well_244 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT245 vdd well_245 ntap1 A=4e-12 P=8e-6 -XM5_15 voutn voutn vdd well_245 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT246 vdd well_246 ntap1 A=4e-12 P=8e-6 -XM57_0 vb1 vb2 net2 well_246 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT247 vdd well_247 ntap1 A=4e-12 P=8e-6 -XM57_1 vb1 vb2 net2 well_247 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT248 vdd well_248 ntap1 A=4e-12 P=8e-6 -XM57_2 vb1 vb2 net2 well_248 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT249 vdd well_249 ntap1 A=4e-12 P=8e-6 -XM57_3 vb1 vb2 net2 well_249 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT250 vdd well_250 ntap1 A=4e-12 P=8e-6 -XM57_4 vb1 vb2 net2 well_250 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT251 vdd well_251 ntap1 A=4e-12 P=8e-6 -XM57_5 vb1 vb2 net2 well_251 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT252 vdd well_252 ntap1 A=4e-12 P=8e-6 -XM57_6 vb1 vb2 net2 well_252 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT253 vdd well_253 ntap1 A=4e-12 P=8e-6 -XM57_7 vb1 vb2 net2 well_253 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT254 vdd well_254 ntap1 A=4e-12 P=8e-6 -XM57_8 vb1 vb2 net2 well_254 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT255 vdd well_255 ntap1 A=4e-12 P=8e-6 -XM57_9 vb1 vb2 net2 well_255 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT256 vdd well_256 ntap1 A=4e-12 P=8e-6 -XM57_10 vb1 vb2 net2 well_256 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT257 vdd well_257 ntap1 A=4e-12 P=8e-6 -XM57_11 vb1 vb2 net2 well_257 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT258 vdd well_258 ntap1 A=4e-12 P=8e-6 -XM57_12 vb1 vb2 net2 well_258 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT259 vdd well_259 ntap1 A=4e-12 P=8e-6 -XM57_13 vb1 vb2 net2 well_259 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT260 vdd well_260 ntap1 A=4e-12 P=8e-6 -XM57_14 vb1 vb2 net2 well_260 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT261 vdd well_261 ntap1 A=4e-12 P=8e-6 -XM57_15 vb1 vb2 net2 well_261 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT262 vdd well_262 ntap1 A=4e-12 P=8e-6 -XM58_0 vb4 vb2 net3 well_262 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT263 vdd well_263 ntap1 A=4e-12 P=8e-6 -XM58_1 vb4 vb2 net3 well_263 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT264 vdd well_264 ntap1 A=4e-12 P=8e-6 -XM58_2 vb4 vb2 net3 well_264 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT265 vdd well_265 ntap1 A=4e-12 P=8e-6 -XM58_3 vb4 vb2 net3 well_265 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT266 vdd well_266 ntap1 A=4e-12 P=8e-6 -XM58_4 vb4 vb2 net3 well_266 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT267 vdd well_267 ntap1 A=4e-12 P=8e-6 -XM58_5 vb4 vb2 net3 well_267 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT268 vdd well_268 ntap1 A=4e-12 P=8e-6 -XM58_6 vb4 vb2 net3 well_268 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT269 vdd well_269 ntap1 A=4e-12 P=8e-6 -XM58_7 vb4 vb2 net3 well_269 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT270 vdd well_270 ntap1 A=4e-12 P=8e-6 -XM58_8 vb4 vb2 net3 well_270 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT271 vdd well_271 ntap1 A=4e-12 P=8e-6 -XM58_9 vb4 vb2 net3 well_271 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT272 vdd well_272 ntap1 A=4e-12 P=8e-6 -XM58_10 vb4 vb2 net3 well_272 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT273 vdd well_273 ntap1 A=4e-12 P=8e-6 -XM58_11 vb4 vb2 net3 well_273 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT274 vdd well_274 ntap1 A=4e-12 P=8e-6 -XM58_12 vb4 vb2 net3 well_274 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT275 vdd well_275 ntap1 A=4e-12 P=8e-6 -XM58_13 vb4 vb2 net3 well_275 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT276 vdd well_276 ntap1 A=4e-12 P=8e-6 -XM58_14 vb4 vb2 net3 well_276 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT277 vdd well_277 ntap1 A=4e-12 P=8e-6 -XM58_15 vb4 vb2 net3 well_277 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT278 vdd well_278 ntap1 A=4e-12 P=8e-6 -XM6_0 voutp voutn vdd well_278 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT279 vdd well_279 ntap1 A=4e-12 P=8e-6 -XM6_1 voutp voutn vdd well_279 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT280 vdd well_280 ntap1 A=4e-12 P=8e-6 -XM6_2 voutp voutn vdd well_280 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT281 vdd well_281 ntap1 A=4e-12 P=8e-6 -XM6_3 voutp voutn vdd well_281 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT282 vdd well_282 ntap1 A=4e-12 P=8e-6 -XM6_4 voutp voutn vdd well_282 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT283 vdd well_283 ntap1 A=4e-12 P=8e-6 -XM6_5 voutp voutn vdd well_283 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT284 vdd well_284 ntap1 A=4e-12 P=8e-6 -XM6_6 voutp voutn vdd well_284 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT285 vdd well_285 ntap1 A=4e-12 P=8e-6 -XM6_7 voutp voutn vdd well_285 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT286 vdd well_286 ntap1 A=4e-12 P=8e-6 -XM6_8 voutp voutn vdd well_286 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT287 vdd well_287 ntap1 A=4e-12 P=8e-6 -XM6_9 voutp voutn vdd well_287 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT288 vdd well_288 ntap1 A=4e-12 P=8e-6 -XM6_10 voutp voutn vdd well_288 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT289 vdd well_289 ntap1 A=4e-12 P=8e-6 -XM6_11 voutp voutn vdd well_289 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT290 vdd well_290 ntap1 A=4e-12 P=8e-6 -XM6_12 voutp voutn vdd well_290 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT291 vdd well_291 ntap1 A=4e-12 P=8e-6 -XM6_13 voutp voutn vdd well_291 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT292 vdd well_292 ntap1 A=4e-12 P=8e-6 -XM6_14 voutp voutn vdd well_292 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT293 vdd well_293 ntap1 A=4e-12 P=8e-6 -XM6_15 voutp voutn vdd well_293 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT294 vdd well_294 ntap1 A=4e-12 P=8e-6 -XM61_0 net7 vb2 net6 well_294 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT295 vdd well_295 ntap1 A=4e-12 P=8e-6 -XM61_1 net7 vb2 net6 well_295 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT296 vdd well_296 ntap1 A=4e-12 P=8e-6 -XM61_2 net7 vb2 net6 well_296 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT297 vdd well_297 ntap1 A=4e-12 P=8e-6 -XM61_3 net7 vb2 net6 well_297 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT298 vdd well_298 ntap1 A=4e-12 P=8e-6 -XM61_4 net7 vb2 net6 well_298 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT299 vdd well_299 ntap1 A=4e-12 P=8e-6 -XM61_5 net7 vb2 net6 well_299 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT300 vdd well_300 ntap1 A=4e-12 P=8e-6 -XM61_6 net7 vb2 net6 well_300 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT301 vdd well_301 ntap1 A=4e-12 P=8e-6 -XM61_7 net7 vb2 net6 well_301 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT302 vdd well_302 ntap1 A=4e-12 P=8e-6 -XM61_8 net7 vb2 net6 well_302 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT303 vdd well_303 ntap1 A=4e-12 P=8e-6 -XM61_9 net7 vb2 net6 well_303 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT304 vdd well_304 ntap1 A=4e-12 P=8e-6 -XM61_10 net7 vb2 net6 well_304 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT305 vdd well_305 ntap1 A=4e-12 P=8e-6 -XM61_11 net7 vb2 net6 well_305 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT306 vdd well_306 ntap1 A=4e-12 P=8e-6 -XM61_12 net7 vb2 net6 well_306 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT307 vdd well_307 ntap1 A=4e-12 P=8e-6 -XM61_13 net7 vb2 net6 well_307 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT308 vdd well_308 ntap1 A=4e-12 P=8e-6 -XM61_14 net7 vb2 net6 well_308 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT309 vdd well_309 ntap1 A=4e-12 P=8e-6 -XM61_15 net7 vb2 net6 well_309 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT310 vdd well_310 ntap1 A=4e-12 P=8e-6 -XM62_0 vb3 vb2 net8 well_310 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT311 vdd well_311 ntap1 A=4e-12 P=8e-6 -XM62_1 vb3 vb2 net8 well_311 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT312 vdd well_312 ntap1 A=4e-12 P=8e-6 -XM62_2 vb3 vb2 net8 well_312 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT313 vdd well_313 ntap1 A=4e-12 P=8e-6 -XM62_3 vb3 vb2 net8 well_313 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT314 vdd well_314 ntap1 A=4e-12 P=8e-6 -XM62_4 vb3 vb2 net8 well_314 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT315 vdd well_315 ntap1 A=4e-12 P=8e-6 -XM62_5 vb3 vb2 net8 well_315 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT316 vdd well_316 ntap1 A=4e-12 P=8e-6 -XM62_6 vb3 vb2 net8 well_316 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT317 vdd well_317 ntap1 A=4e-12 P=8e-6 -XM62_7 vb3 vb2 net8 well_317 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT318 vdd well_318 ntap1 A=4e-12 P=8e-6 -XM62_8 vb3 vb2 net8 well_318 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT319 vdd well_319 ntap1 A=4e-12 P=8e-6 -XM62_9 vb3 vb2 net8 well_319 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT320 vdd well_320 ntap1 A=4e-12 P=8e-6 -XM62_10 vb3 vb2 net8 well_320 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT321 vdd well_321 ntap1 A=4e-12 P=8e-6 -XM62_11 vb3 vb2 net8 well_321 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT322 vdd well_322 ntap1 A=4e-12 P=8e-6 -XM62_12 vb3 vb2 net8 well_322 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT323 vdd well_323 ntap1 A=4e-12 P=8e-6 -XM62_13 vb3 vb2 net8 well_323 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT324 vdd well_324 ntap1 A=4e-12 P=8e-6 -XM62_14 vb3 vb2 net8 well_324 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT325 vdd well_325 ntap1 A=4e-12 P=8e-6 -XM62_15 vb3 vb2 net8 well_325 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT326 vss sub ptap1 A=4e-12 P=8e-6 -XM63_0 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT327 vss sub ptap1 A=4e-12 P=8e-6 -XM63_1 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT328 vss sub ptap1 A=4e-12 P=8e-6 -XM63_2 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT329 vss sub ptap1 A=4e-12 P=8e-6 -XM63_3 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT330 vss sub ptap1 A=4e-12 P=8e-6 -XM63_4 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT331 vss sub ptap1 A=4e-12 P=8e-6 -XM63_5 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT332 vss sub ptap1 A=4e-12 P=8e-6 -XM63_6 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT333 vss sub ptap1 A=4e-12 P=8e-6 -XM63_7 vb2 vb3 net9 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT334 vss sub ptap1 A=4e-12 P=8e-6 -XM64_0 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT335 vss sub ptap1 A=4e-12 P=8e-6 -XM64_1 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT336 vss sub ptap1 A=4e-12 P=8e-6 -XM64_2 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT337 vss sub ptap1 A=4e-12 P=8e-6 -XM64_3 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT338 vss sub ptap1 A=4e-12 P=8e-6 -XM64_4 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT339 vss sub ptap1 A=4e-12 P=8e-6 -XM64_5 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT340 vss sub ptap1 A=4e-12 P=8e-6 -XM64_6 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT341 vss sub ptap1 A=4e-12 P=8e-6 -XM64_7 net9 vb4 vss sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT342 vdd well_342 ntap1 A=4e-12 P=8e-6 -XM65_0 vb2 vb2 vdd well_342 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT343 vdd well_343 ntap1 A=4e-12 P=8e-6 -XM65_1 vb2 vb2 vdd well_343 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT344 vdd well_344 ntap1 A=4e-12 P=8e-6 -XM65_2 vb2 vb2 vdd well_344 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT345 vdd well_345 ntap1 A=4e-12 P=8e-6 -XM65_3 vb2 vb2 vdd well_345 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT346 vdd well_346 ntap1 A=4e-12 P=8e-6 -XM66_0 net10 vb2 net049 well_346 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT347 vdd well_347 ntap1 A=4e-12 P=8e-6 -XM66_1 net10 vb2 net049 well_347 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT348 vdd well_348 ntap1 A=4e-12 P=8e-6 -XM66_2 net10 vb2 net049 well_348 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT349 vdd well_349 ntap1 A=4e-12 P=8e-6 -XM66_3 net10 vb2 net049 well_349 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT350 vdd well_350 ntap1 A=4e-12 P=8e-6 -XM66_4 net10 vb2 net049 well_350 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT351 vdd well_351 ntap1 A=4e-12 P=8e-6 -XM66_5 net10 vb2 net049 well_351 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT352 vdd well_352 ntap1 A=4e-12 P=8e-6 -XM66_6 net10 vb2 net049 well_352 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT353 vdd well_353 ntap1 A=4e-12 P=8e-6 -XM66_7 net10 vb2 net049 well_353 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT354 vdd well_354 ntap1 A=4e-12 P=8e-6 -XM66_8 net10 vb2 net049 well_354 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT355 vdd well_355 ntap1 A=4e-12 P=8e-6 -XM66_9 net10 vb2 net049 well_355 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT356 vdd well_356 ntap1 A=4e-12 P=8e-6 -XM66_10 net10 vb2 net049 well_356 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT357 vdd well_357 ntap1 A=4e-12 P=8e-6 -XM66_11 net10 vb2 net049 well_357 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT358 vdd well_358 ntap1 A=4e-12 P=8e-6 -XM66_12 net10 vb2 net049 well_358 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT359 vdd well_359 ntap1 A=4e-12 P=8e-6 -XM66_13 net10 vb2 net049 well_359 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT360 vdd well_360 ntap1 A=4e-12 P=8e-6 -XM66_14 net10 vb2 net049 well_360 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT361 vdd well_361 ntap1 A=4e-12 P=8e-6 -XM66_15 net10 vb2 net049 well_361 sg13_lv_pmos w=0.97u l=0.81u m=1 -XT362 vss sub ptap1 A=4e-12 P=8e-6 -XM67_0 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT363 vss sub ptap1 A=4e-12 P=8e-6 -XM67_1 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT364 vss sub ptap1 A=4e-12 P=8e-6 -XM67_2 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT365 vss sub ptap1 A=4e-12 P=8e-6 -XM67_3 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT366 vss sub ptap1 A=4e-12 P=8e-6 -XM67_4 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT367 vss sub ptap1 A=4e-12 P=8e-6 -XM67_5 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT368 vss sub ptap1 A=4e-12 P=8e-6 -XM67_6 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT369 vss sub ptap1 A=4e-12 P=8e-6 -XM67_7 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT370 vss sub ptap1 A=4e-12 P=8e-6 -XM67_8 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT371 vss sub ptap1 A=4e-12 P=8e-6 -XM67_9 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT372 vss sub ptap1 A=4e-12 P=8e-6 -XM67_10 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT373 vss sub ptap1 A=4e-12 P=8e-6 -XM67_11 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT374 vss sub ptap1 A=4e-12 P=8e-6 -XM67_12 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT375 vss sub ptap1 A=4e-12 P=8e-6 -XM67_13 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT376 vss sub ptap1 A=4e-12 P=8e-6 -XM67_14 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT377 vss sub ptap1 A=4e-12 P=8e-6 -XM67_15 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT378 vss sub ptap1 A=4e-12 P=8e-6 -XM67_16 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT379 vss sub ptap1 A=4e-12 P=8e-6 -XM67_17 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT380 vss sub ptap1 A=4e-12 P=8e-6 -XM67_18 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT381 vss sub ptap1 A=4e-12 P=8e-6 -XM67_19 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT382 vss sub ptap1 A=4e-12 P=8e-6 -XM67_20 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT383 vss sub ptap1 A=4e-12 P=8e-6 -XM67_21 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT384 vss sub ptap1 A=4e-12 P=8e-6 -XM67_22 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT385 vss sub ptap1 A=4e-12 P=8e-6 -XM67_23 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT386 vss sub ptap1 A=4e-12 P=8e-6 -XM67_24 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT387 vss sub ptap1 A=4e-12 P=8e-6 -XM67_25 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT388 vss sub ptap1 A=4e-12 P=8e-6 -XM67_26 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT389 vss sub ptap1 A=4e-12 P=8e-6 -XM67_27 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT390 vss sub ptap1 A=4e-12 P=8e-6 -XM67_28 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT391 vss sub ptap1 A=4e-12 P=8e-6 -XM67_29 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT392 vss sub ptap1 A=4e-12 P=8e-6 -XM67_30 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT393 vss sub ptap1 A=4e-12 P=8e-6 -XM67_31 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT394 vss sub ptap1 A=4e-12 P=8e-6 -XM67_32 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT395 vss sub ptap1 A=4e-12 P=8e-6 -XM67_33 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT396 vss sub ptap1 A=4e-12 P=8e-6 -XM67_34 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT397 vss sub ptap1 A=4e-12 P=8e-6 -XM67_35 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT398 vss sub ptap1 A=4e-12 P=8e-6 -XM67_36 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT399 vss sub ptap1 A=4e-12 P=8e-6 -XM67_37 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT400 vss sub ptap1 A=4e-12 P=8e-6 -XM67_38 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT401 vss sub ptap1 A=4e-12 P=8e-6 -XM67_39 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT402 vss sub ptap1 A=4e-12 P=8e-6 -XM67_40 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT403 vss sub ptap1 A=4e-12 P=8e-6 -XM67_41 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT404 vss sub ptap1 A=4e-12 P=8e-6 -XM67_42 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT405 vss sub ptap1 A=4e-12 P=8e-6 -XM67_43 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT406 vss sub ptap1 A=4e-12 P=8e-6 -XM67_44 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT407 vss sub ptap1 A=4e-12 P=8e-6 -XM67_45 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT408 vss sub ptap1 A=4e-12 P=8e-6 -XM67_46 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT409 vss sub ptap1 A=4e-12 P=8e-6 -XM67_47 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT410 vss sub ptap1 A=4e-12 P=8e-6 -XM67_48 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT411 vss sub ptap1 A=4e-12 P=8e-6 -XM67_49 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT412 vss sub ptap1 A=4e-12 P=8e-6 -XM67_50 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT413 vss sub ptap1 A=4e-12 P=8e-6 -XM67_51 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT414 vss sub ptap1 A=4e-12 P=8e-6 -XM67_52 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT415 vss sub ptap1 A=4e-12 P=8e-6 -XM67_53 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT416 vss sub ptap1 A=4e-12 P=8e-6 -XM67_54 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT417 vss sub ptap1 A=4e-12 P=8e-6 -XM67_55 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT418 vss sub ptap1 A=4e-12 P=8e-6 -XM67_56 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT419 vss sub ptap1 A=4e-12 P=8e-6 -XM67_57 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT420 vss sub ptap1 A=4e-12 P=8e-6 -XM67_58 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT421 vss sub ptap1 A=4e-12 P=8e-6 -XM67_59 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT422 vss sub ptap1 A=4e-12 P=8e-6 -XM67_60 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT423 vss sub ptap1 A=4e-12 P=8e-6 -XM67_61 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT424 vss sub ptap1 A=4e-12 P=8e-6 -XM67_62 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT425 vss sub ptap1 A=4e-12 P=8e-6 -XM67_63 net043 vb3 net1 sub sg13_lv_nmos w=0.47u l=2.1u m=1 -XT426 vss sub ptap1 A=4e-12 P=8e-6 -XM68_0 net1 vb4 vss sub sg13_lv_nmos w=8.71u l=2.9u m=1 -XT427 vss sub ptap1 A=4e-12 P=8e-6 -XM68_1 net1 vb4 vss sub sg13_lv_nmos w=8.71u l=2.9u m=1 -XT428 vss sub ptap1 A=4e-12 P=8e-6 -XM68_2 net1 vb4 vss sub sg13_lv_nmos w=8.71u l=2.9u m=1 -XT429 vss sub ptap1 A=4e-12 P=8e-6 -XM69_0 net10 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -XT430 vss sub ptap1 A=4e-12 P=8e-6 -XM69_1 net10 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -XT431 vss sub ptap1 A=4e-12 P=8e-6 -XM69_2 net10 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -XT432 vdd well_432 ntap1 A=4e-12 P=8e-6 -XM7_0 net049 vb1 vdd well_432 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT433 vdd well_433 ntap1 A=4e-12 P=8e-6 -XM7_1 net049 vb1 vdd well_433 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT434 vdd well_434 ntap1 A=4e-12 P=8e-6 -XM7_2 net049 vb1 vdd well_434 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT435 vdd well_435 ntap1 A=4e-12 P=8e-6 -XM7_3 net049 vb1 vdd well_435 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT436 vdd well_436 ntap1 A=4e-12 P=8e-6 -XM7_4 net049 vb1 vdd well_436 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT437 vdd well_437 ntap1 A=4e-12 P=8e-6 -XM7_5 net049 vb1 vdd well_437 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT438 vdd well_438 ntap1 A=4e-12 P=8e-6 -XM7_6 net049 vb1 vdd well_438 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT439 vdd well_439 ntap1 A=4e-12 P=8e-6 -XM7_7 net049 vb1 vdd well_439 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT440 vdd well_440 ntap1 A=4e-12 P=8e-6 -XM7_8 net049 vb1 vdd well_440 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT441 vdd well_441 ntap1 A=4e-12 P=8e-6 -XM7_9 net049 vb1 vdd well_441 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT442 vdd well_442 ntap1 A=4e-12 P=8e-6 -XM7_10 net049 vb1 vdd well_442 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT443 vdd well_443 ntap1 A=4e-12 P=8e-6 -XM7_11 net049 vb1 vdd well_443 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT444 vdd well_444 ntap1 A=4e-12 P=8e-6 -XM7_12 net049 vb1 vdd well_444 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT445 vdd well_445 ntap1 A=4e-12 P=8e-6 -XM7_13 net049 vb1 vdd well_445 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT446 vdd well_446 ntap1 A=4e-12 P=8e-6 -XM7_14 net049 vb1 vdd well_446 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT447 vdd well_447 ntap1 A=4e-12 P=8e-6 -XM7_15 net049 vb1 vdd well_447 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT448 vdd well_448 ntap1 A=4e-12 P=8e-6 -XM7_16 net049 vb1 vdd well_448 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT449 vdd well_449 ntap1 A=4e-12 P=8e-6 -XM7_17 net049 vb1 vdd well_449 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT450 vdd well_450 ntap1 A=4e-12 P=8e-6 -XM7_18 net049 vb1 vdd well_450 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT451 vdd well_451 ntap1 A=4e-12 P=8e-6 -XM7_19 net049 vb1 vdd well_451 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT452 vdd well_452 ntap1 A=4e-12 P=8e-6 -XM7_20 net049 vb1 vdd well_452 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT453 vdd well_453 ntap1 A=4e-12 P=8e-6 -XM7_21 net049 vb1 vdd well_453 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT454 vdd well_454 ntap1 A=4e-12 P=8e-6 -XM7_22 net049 vb1 vdd well_454 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT455 vdd well_455 ntap1 A=4e-12 P=8e-6 -XM7_23 net049 vb1 vdd well_455 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT456 vdd well_456 ntap1 A=4e-12 P=8e-6 -XM7_24 net049 vb1 vdd well_456 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT457 vdd well_457 ntap1 A=4e-12 P=8e-6 -XM7_25 net049 vb1 vdd well_457 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT458 vdd well_458 ntap1 A=4e-12 P=8e-6 -XM7_26 net049 vb1 vdd well_458 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT459 vdd well_459 ntap1 A=4e-12 P=8e-6 -XM7_27 net049 vb1 vdd well_459 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT460 vdd well_460 ntap1 A=4e-12 P=8e-6 -XM7_28 net049 vb1 vdd well_460 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT461 vdd well_461 ntap1 A=4e-12 P=8e-6 -XM7_29 net049 vb1 vdd well_461 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT462 vdd well_462 ntap1 A=4e-12 P=8e-6 -XM7_30 net049 vb1 vdd well_462 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT463 vdd well_463 ntap1 A=4e-12 P=8e-6 -XM7_31 net049 vb1 vdd well_463 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT464 vdd well_464 ntap1 A=4e-12 P=8e-6 -XM7_32 net049 vb1 vdd well_464 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT465 vdd well_465 ntap1 A=4e-12 P=8e-6 -XM7_33 net049 vb1 vdd well_465 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT466 vdd well_466 ntap1 A=4e-12 P=8e-6 -XM7_34 net049 vb1 vdd well_466 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT467 vdd well_467 ntap1 A=4e-12 P=8e-6 -XM7_35 net049 vb1 vdd well_467 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT468 vdd well_468 ntap1 A=4e-12 P=8e-6 -XM7_36 net049 vb1 vdd well_468 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT469 vdd well_469 ntap1 A=4e-12 P=8e-6 -XM7_37 net049 vb1 vdd well_469 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT470 vdd well_470 ntap1 A=4e-12 P=8e-6 -XM7_38 net049 vb1 vdd well_470 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT471 vdd well_471 ntap1 A=4e-12 P=8e-6 -XM7_39 net049 vb1 vdd well_471 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT472 vdd well_472 ntap1 A=4e-12 P=8e-6 -XM7_40 net049 vb1 vdd well_472 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT473 vdd well_473 ntap1 A=4e-12 P=8e-6 -XM7_41 net049 vb1 vdd well_473 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT474 vdd well_474 ntap1 A=4e-12 P=8e-6 -XM7_42 net049 vb1 vdd well_474 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT475 vdd well_475 ntap1 A=4e-12 P=8e-6 -XM7_43 net049 vb1 vdd well_475 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT476 vdd well_476 ntap1 A=4e-12 P=8e-6 -XM7_44 net049 vb1 vdd well_476 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT477 vdd well_477 ntap1 A=4e-12 P=8e-6 -XM7_45 net049 vb1 vdd well_477 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT478 vdd well_478 ntap1 A=4e-12 P=8e-6 -XM7_46 net049 vb1 vdd well_478 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT479 vdd well_479 ntap1 A=4e-12 P=8e-6 -XM7_47 net049 vb1 vdd well_479 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT480 vdd well_480 ntap1 A=4e-12 P=8e-6 -XM7_48 net049 vb1 vdd well_480 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT481 vdd well_481 ntap1 A=4e-12 P=8e-6 -XM7_49 net049 vb1 vdd well_481 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT482 vdd well_482 ntap1 A=4e-12 P=8e-6 -XM7_50 net049 vb1 vdd well_482 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT483 vdd well_483 ntap1 A=4e-12 P=8e-6 -XM7_51 net049 vb1 vdd well_483 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT484 vdd well_484 ntap1 A=4e-12 P=8e-6 -XM7_52 net049 vb1 vdd well_484 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT485 vdd well_485 ntap1 A=4e-12 P=8e-6 -XM7_53 net049 vb1 vdd well_485 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT486 vdd well_486 ntap1 A=4e-12 P=8e-6 -XM7_54 net049 vb1 vdd well_486 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT487 vdd well_487 ntap1 A=4e-12 P=8e-6 -XM7_55 net049 vb1 vdd well_487 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT488 vdd well_488 ntap1 A=4e-12 P=8e-6 -XM7_56 net049 vb1 vdd well_488 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT489 vdd well_489 ntap1 A=4e-12 P=8e-6 -XM7_57 net049 vb1 vdd well_489 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT490 vdd well_490 ntap1 A=4e-12 P=8e-6 -XM7_58 net049 vb1 vdd well_490 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT491 vdd well_491 ntap1 A=4e-12 P=8e-6 -XM7_59 net049 vb1 vdd well_491 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT492 vdd well_492 ntap1 A=4e-12 P=8e-6 -XM7_60 net049 vb1 vdd well_492 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT493 vdd well_493 ntap1 A=4e-12 P=8e-6 -XM7_61 net049 vb1 vdd well_493 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT494 vdd well_494 ntap1 A=4e-12 P=8e-6 -XM7_62 net049 vb1 vdd well_494 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT495 vdd well_495 ntap1 A=4e-12 P=8e-6 -XM7_63 net049 vb1 vdd well_495 sg13_lv_pmos w=2.22u l=0.84u m=1 -XT496 vss sub ptap1 A=4e-12 P=8e-6 -XM70_0 net1 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -XT497 vss sub ptap1 A=4e-12 P=8e-6 -XM70_1 net1 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -XT498 vss sub ptap1 A=4e-12 P=8e-6 -XM70_2 net1 net043 vss sub sg13_lv_nmos w=1.68u l=8.05u m=1 -XT499 net31 well_499 ntap1 A=4e-12 P=8e-6 -XM8_0 dm_2 vinn net31 well_499 sg13_lv_pmos w=9.9u l=1.89u m=1 -XT500 net31 well_500 ntap1 A=4e-12 P=8e-6 -XM8_1 dm_2 vinn net31 well_500 sg13_lv_pmos w=9.9u l=1.89u m=1 -XT501 net31 well_501 ntap1 A=4e-12 P=8e-6 -XM8_2 dm_2 vinn net31 well_501 sg13_lv_pmos w=9.9u l=1.89u m=1 -XT502 net31 well_502 ntap1 A=4e-12 P=8e-6 -XM9_0 net063 vinp net31 well_502 sg13_lv_pmos w=9.9u l=1.89u m=1 -XT503 net31 well_503 ntap1 A=4e-12 P=8e-6 -XM9_1 net063 vinp net31 well_503 sg13_lv_pmos w=9.9u l=1.89u m=1 -XT504 net31 well_504 ntap1 A=4e-12 P=8e-6 -XM9_2 net063 vinp net31 well_504 sg13_lv_pmos w=9.9u l=1.89u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM0 net2 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM1 net3 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM10 net043 voutp vdd vdd sg13_lv_pmos w=4.88u l=2.36u m=24 +XM11 vout voutp vdd vdd sg13_lv_pmos w=4.46u l=0.98u m=9 +XM12 vb4 vb3 net54 vss sg13_lv_nmos w=0.47u l=2.1u m=8 +XM13 net7 vb3 net56 vss sg13_lv_nmos w=0.47u l=2.1u m=8 +XM14 vb3 vb3 vss vss sg13_lv_nmos w=0.47u l=2.1u m=2 +XM15 voutn vb3 dm_2 vss sg13_lv_nmos w=0.47u l=2.1u m=16 +XM16 voutp vb3 net063 vss sg13_lv_nmos w=0.47u l=2.1u m=16 +XM17 net54 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=8 +XM18 net56 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=8 +XM19 dm_2 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=16 +XM2 net6 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM20 net063 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=16 +XM23 vout net10 vss vss sg13_lv_nmos w=9.59u l=0.51u m=3 +XM3 net8 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM4 net31 vb1 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=32 +XM5 voutn voutn vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM57 vb1 vb2 net2 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM58 vb4 vb2 net3 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM6 voutp voutn vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM61 net7 vb2 net6 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM62 vb3 vb2 net8 vdd sg13_lv_pmos w=2.22u l=0.84u m=16 +XM63 vb2 vb3 net9 vss sg13_lv_nmos w=0.47u l=2.1u m=8 +XM64 net9 vb4 vss vss sg13_lv_nmos w=0.47u l=2.1u m=8 +XM65 vb2 vb2 vdd vdd sg13_lv_pmos w=2.22u l=0.84u m=4 +XM66 net10 vb2 net049 vdd sg13_lv_pmos w=0.97u l=0.81u m=16 +XM67 net043 vb3 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main sheet follows the circuit stages; repeated net names identify matching terminals within each sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Repeated source devices remain individually represented. Large banks use contiguous source-order detail ranges only where needed for responsive editing."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":6},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_011_peng_iac"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/design/amp_011_peng_iac.icproj.json"}}Main-sheet overview; 31 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_011_peng_iacvddvb1net3vddvb1net8vddvb1net2vddvb1net31vsssubvddnet10vb2net049vddnet3vb4vb2vsssubvb4net9vddvb1net049vsssubvb4net063subvb3voutndm_2vddvoutvoutpvddnet043voutpvddvb1net6vsssubvb4net54vddnet7net6vb2vsssubvb4net56subvb3net7net56vddvoutpvoutnvddvb3net8vb2vddvb1net2vb2subvb4vb3net54vsssubvb4dm_2subvb3vb2net9vddvb2vsssubnet4vddvoutnvoutpsubvb3net063net043subvb3net1vddvddvssvssvinnvinpnet31net31dm_2net063net7net7vddvb2vb3vb4voutnvoutpvoutpnet043net043net043net10vddnet10voutnet1net1net4vb1vb1vb1vssvssvssamp_011_peng_iacBIAS AND CURRENT MIRRORSINPUT STAGEOUTPUT AND COMPENSATIONMM14_0MM14_1MM23_0MM23_1MM23_2MM68_0MM68_1MM68_2MM69_0MM69_1MM69_2MM70_0MM70_1MM70_2RT499MM8_0RT500MM8_1RT501MM8_2RT502MM9_0RT503MM9_1RT504MM9_2C0_0C1_0C1_1XMM0_bank1XMM1_bank2XMM10_bank3XMM11_bank4XMM12_bank5XMM13_bank6XMM15_bank7XMM16_bank8XMM17_bank9XMM18_bank10XMM19_bank11XMM2_bank12XMM20_bank13XMM3_bank14XMM4_bank15XMM5_bank16XMM57_bank17XMM58_bank18XMM6_bank19XMM61_bank20XMM62_bank21XMM63_bank22XMM64_bank23XMM65_bank24XMM66_bank25XMM67_bank26XMM7_bank27XXRT65_bank28XXRR0_bank29 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md index d665bc0899fe6e5964109b145a702c29db2b7883..ae2937023758287e2c10051ae06394b992808424 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md @@ -4,7 +4,7 @@ Implement `amp_011_peng_iac` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded branches feed voutn/voutp. The PMOS bias mirror is cascoded with vb2, generated by XM65/XM63/XM64. XM10 drives net043; XM67/XM68 and XM70 retain the auxiliary current path, with XM69 driving net10 against XM66. XM11/XM23 drive vout. Compensation retains 1.95593 pF between voutp and vout, and 4.33595 pF between net10 and net4 with 1.46466 Mohm from net4 to vss. Do not replace the circuit, delete compensation, or add a servo. The physical core -contains 505 MOS after expanding explicit upstream multiplicities. Each PMOS +contains 34 logical MOS groups with upstream multiplicities. Each PMOS input body remains tied to its own tail node through its physical well contact. ## Inputs and Interface @@ -15,7 +15,7 @@ observations and `materials/ac.spice` defines balanced differential AC excitatio Ordered ports: `vss vdd vinn vinp vout vb1`. `vss` is ground, `vdd` supply, `vinn/vinp` negative/positive input, `vout` the single-ended output, and `vb1` the external bias-current sink. Bias, input drivers, feedback wiring and load are -external test apparatus; taps and all internal R/C are physical DUT elements. +external test apparatus; all internal R/C and actual body contacts are physical DUT elements. ## Operating Conditions @@ -42,10 +42,10 @@ response. No voltage-transfer estimate is labeled a loop return ratio. Supply a GDS <=64 MiB with top cell `amp_011_peng_iac`, within 20000 by 2000 um (the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS and functional-area measurement must pass; no marker waivers apply. Preserve -MOS dimensions, multiplicities, body connections, all physical R/C and tap geometry. +MOS dimensions, multiplicities, body connections, all physical R/C and logical body connectivity. Functional layers in the published task include active, implant, wells, gates, contacts, passive plates, vias and routing; annotation/text-only layers are excluded. -IHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job. +IHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation uses the declared logical body connections. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job. ## Electrical Requirements and Scoring @@ -115,3 +115,5 @@ Finite-window amplifier response: tracking error 36%, ripple 22.5%, AC transfer Solve budget: **8 hours**. Use reviewed IHP SG13G2 resources and the ngspice 45 environment; see `/protocol/task.json` for frozen requirements and resource bindings. Explicitly submit `/workspace/output/final.gds` through the session tool; writing a file alone is insufficient. Evaluation checks files, native DRC/LVS, geometry, candidate RC, independent source simulation and post-layout simulation; source baselines, reference solutions and the author repository are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml index dd8bbf42452e4cf7c450423518fe36e888725e56..10d62f140abe6fee162107e0c35d815160a1bf25 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml @@ -4,13 +4,6 @@ title = "Auxiliary Source-Driven Output-Control OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "e2aa03430577486bb4ab3cff663970c0616cd2f736ba111af9b4b7fb18dd3d79" - [[assets]] path = "reference/amp_012_peng_tcfc.gds" role = "physical-witness" @@ -28,13 +21,13 @@ environment = "ihp-sg13g2-amp_012_peng_tcfc-nominal-rc" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "3ac44eae2237b0ac994525fc1e56422853206c8cab427a2a261ca7e5642ec40f" +sha256 = "aa9aa9b0cc751fa95fb715aa8186d4d426d4b41c7abce40e01f3399ad5938514" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_012_peng_tcfc" -sha256 = "5d1695a711afd0ce2ecc5a85c10c5c4cb632b5771cc6b7963d4993e28a1edba9" +sha256 = "164eba92a9ddf29a58abf956176b9008d07e746968e502e3c0a5926c888b08a2" [task.inputs.performance] path = "materials/testbench.spice" @@ -44,7 +37,7 @@ sha256 = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +sha256 = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.constraints] quality = [ @@ -1163,10 +1156,10 @@ upper = 1.2 rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective." [task.evaluation.pre_layout] -source_report_sha256 = "e8b9d8481f7fffc86c2d89f808c364dd6bb829c90d5e142fb66a97ddb67903df" +source_report_sha256 = "53414f02ccf1fee1822e1ce8e4536f7b84b3f9749581fb41c579e573d74da9f2" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1213,86 +1206,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" -dut = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +dut = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 0.8310178748682 +value = 0.8449057653251 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dc_gain_db] -value = 101.3742 +value = 101.3311 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_phase_margin_deg] -value = 64.2898 +value = 65.2953 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_unity_hz] -value = 369038.2 +value = 362475.8 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.hf_gain_db] -value = -51.84824 +value = -61.96276 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 9.743154e-06 +value = 9.897576e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_return_distance] -value = 0.6715942668209 +value = 0.6836357698391 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_error_v] -value = 0.0004852514341811 +value = 0.0003455730380925 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.5004852514342 +value = 0.5003455730381 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.peak_v] -value = 0.7011561 +value = 0.7008233 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin_deg] -value = 64.2898 +value = 65.2953 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 9.757284897999e-06 +value = 9.911830457935e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_down_v] -value = 0.0004853186 +value = 0.0003456188 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_up_v] -value = 0.00049289 +value = 0.0003491929 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_phase_excursion_deg] -value = 89.75791273697 +value = 89.7515952214 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_gain] -value = 1.000038 +value = 1.000018 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.trough_v] -value = 0.4981424 +value = 0.4986327 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] -value = 369038.2 +value = 362475.8 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "00e36142adaf44e7a5bedbfd7b5ba7451ba62259394be0875a5b78f932a49eaf" -ac = "2ec6ac215d65378128b643ed2088e5252c134c9b58b62fe9032cc7fea6099be1" -transient = "5d22b917fa6ba0f6fcd5376d187657a18999b8dc29b9aa0e1aadd8e45ddcae37" -voltage = "5e79d847740ebd851a9ec04fb6a80b272ea19b80eef314a0111587a4e8ec69f5" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1338,86 +1325,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" -dut = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +dut = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] -value = 0.8310178748682 +value = 0.8449057653251 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_gain_db] -value = 101.3742 +value = 101.3311 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_phase_margin_deg] -value = 62.5961 +value = 63.7662 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_unity_hz] -value = 382006.8 +value = 374354.1 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.hf_gain_db] -value = -57.23659 +value = -67.21468 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] -value = 9.74481e-06 +value = 9.899081e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_return_distance] -value = 0.57447652815 +value = 0.5911825144319 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_error_v] -value = 0.0004852514341811 +value = 0.0003455730380925 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] -value = 0.5004852514342 +value = 0.5003455730381 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.peak_v] -value = 0.7009345 +value = 0.7006809 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin_deg] -value = 62.5961 +value = 63.7662 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 9.757284897999e-06 +value = 9.911830457935e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_down_v] -value = 0.0004853169 +value = 0.0003456177 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_up_v] -value = 0.0004928907 +value = 0.0003491927 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.return_phase_excursion_deg] -value = 89.75869472383 +value = 89.75233061463 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_gain] -value = 1.000038 +value = 1.000018 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.trough_v] -value = 0.4979397 +value = 0.4986376 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] -value = 382006.8 +value = 374354.1 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "00e36142adaf44e7a5bedbfd7b5ba7451ba62259394be0875a5b78f932a49eaf" -ac = "65ae6e33acf92df3387b9ca87262467636e01bb12c050b392f5fe96abbb2f1d3" -transient = "351f43b2f6da4b1ddf8d0832aa696caa299a7f0dc8e0263ff5c506ec261d9b08" -voltage = "78a8b2c460d270a6496cb603c6fdc3ebdb3e890b9dac557d6d7f2bdc33df9c48" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1463,86 +1444,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" -dut = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +dut = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] -value = 0.8310178748682 +value = 0.8449057653251 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_gain_db] -value = 101.3742 +value = 101.3311 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_phase_margin_deg] -value = 60.4251 +value = 61.8402 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_unity_hz] -value = 398205.7 +value = 388964.7 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.hf_gain_db] -value = -60.53757 +value = -70.46438 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] -value = 9.749601e-06 +value = 9.902665e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_return_distance] -value = 0.4632038272759 +value = 0.4851334350641 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_error_v] -value = 0.0004852514341811 +value = 0.0003455730380925 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] -value = 0.5004852514342 +value = 0.5003455730381 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.peak_v] -value = 0.7034029 +value = 0.7017873 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_margin_deg] -value = 60.4251 +value = 61.8402 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 9.757284897999e-06 +value = 9.911830457935e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_down_v] -value = 0.000485335 +value = 0.0003456681 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_up_v] -value = 0.0004928885 +value = 0.0003491928 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.return_phase_excursion_deg] -value = 89.75947938665 +value = 89.75307021242 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_gain] -value = 1.000038 +value = 1.000018 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.trough_v] -value = 0.4972896 +value = 0.498141 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.unity_hz] -value = 398205.7 +value = 388964.7 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "00e36142adaf44e7a5bedbfd7b5ba7451ba62259394be0875a5b78f932a49eaf" -ac = "7baa91f9a54ee22761bbac4c86e466d0d58d46aee0b3ebc2bee39527aee6d742" -transient = "6a5085016afd117d2b6efc8c6a2062ffd90de4cfa895a42201d32a9a9bef6201" -voltage = "66c43c0fa2892d47bc342b332b046001bd65c7f26834702194f9d1f2d1906ee5" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -1588,86 +1563,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" -dut = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +dut = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.bias_v] -value = 0.8310181587503 +value = 0.8449060135788 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dc_gain_db] -value = 103.6586 +value = 103.6553 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_phase_margin_deg] -value = 64.5516 +value = 65.4947 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_unity_hz] -value = 366723.5 +value = 360968.8 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.hf_gain_db] -value = -51.79715 +value = -62.0066 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.mean_power_w] -value = 9.743154e-06 +value = 9.897576e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_return_distance] -value = 0.6719657002798 +value = 0.6833377590739 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_error_v] -value = 0.0004928816822619 +value = 0.0003491914165008 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] -value = 0.7004928816823 +value = 0.7003491914165 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.peak_v] -value = 0.7011561 +value = 0.7008233 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.phase_margin_deg] -value = 64.5516 +value = 65.4947 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 9.724546869294e-06 +value = 9.878475226905e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_down_v] -value = 0.0004853186 +value = 0.0003456188 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_up_v] -value = 0.00049289 +value = 0.0003491929 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.return_phase_excursion_deg] -value = 89.78656002993 +value = 89.78180210532 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_gain] -value = 1.000038 +value = 1.000018 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.trough_v] -value = 0.4981424 +value = 0.4986327 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.unity_hz] -value = 366723.5 +value = 360968.8 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "70da35e9a311b05761a5c2856ae58caba87dfa070c090cbe1fa7da4e1f80da41" -ac = "bd99ddba72aef59bd05c28a5e8c3911b84a0bdd86054e40795b0f37a7dcdc209" -transient = "5d22b917fa6ba0f6fcd5376d187657a18999b8dc29b9aa0e1aadd8e45ddcae37" -voltage = "cdf857d54949d3be9009ffa74ed3919d49c3fe7e812ae0e4c08404d1e8908784" - [task.evaluation.pre_layout.jobs.source_condition_4] operation = "circuit.simulate" @@ -1713,86 +1682,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] deck = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" -dut = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +dut = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.bias_v] -value = 0.8310181587503 +value = 0.8449060135788 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.dc_gain_db] -value = 103.6586 +value = 103.6553 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_phase_margin_deg] -value = 62.8947 +value = 63.9898 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_unity_hz] -value = 379512.4 +value = 372757.0 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.hf_gain_db] -value = -57.18602 +value = -67.25882 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.mean_power_w] -value = 9.74481e-06 +value = 9.899081e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.minimum_return_distance] -value = 0.57317409413 +value = 0.5891009844109 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_error_v] -value = 0.0004928816822619 +value = 0.0003491914165008 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] -value = 0.7004928816823 +value = 0.7003491914165 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.peak_v] -value = 0.7009345 +value = 0.7006809 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.phase_margin_deg] -value = 62.8947 +value = 63.9898 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] -value = 9.724546869294e-06 +value = 9.878475226905e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_down_v] -value = 0.0004853169 +value = 0.0003456177 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_up_v] -value = 0.0004928907 +value = 0.0003491927 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.return_phase_excursion_deg] -value = 89.7872422489 +value = 89.78244459997 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.step_gain] -value = 1.000038 +value = 1.000018 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.trough_v] -value = 0.4979397 +value = 0.4986376 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.unity_hz] -value = 379512.4 +value = 372757.0 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_4.output_sha256] -op = "70da35e9a311b05761a5c2856ae58caba87dfa070c090cbe1fa7da4e1f80da41" -ac = "36b9564f38f85e964a3935cdd1f315a9edcd6e476b2f2981cba8fea1a12c2d25" -transient = "351f43b2f6da4b1ddf8d0832aa696caa299a7f0dc8e0263ff5c506ec261d9b08" -voltage = "73c2b5c2e7dffb6d018146e5d3006996301ae9e7a945752a041ddd3a777899fa" - [task.evaluation.pre_layout.jobs.source_condition_5] operation = "circuit.simulate" @@ -1838,86 +1801,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] deck = "71a6cf9e24749b49c887f59c5de978c42191951e74b066c265d8c99ade94f1a4" -dut = "2cba47ee86ea264c9f7c183c4820923cc1ffe6a257a51f27c6bbff4160d06628" +dut = "956dbf3786a54cf70df7740e85583627191450120902623b9b2715271eb03d52" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.bias_v] -value = 0.8310181587503 +value = 0.8449060135788 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.dc_gain_db] -value = 103.6586 +value = 103.6553 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_phase_margin_deg] -value = 60.7746 +value = 62.0962 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_unity_hz] -value = 395477.9 +value = 387254.4 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.hf_gain_db] -value = -60.48718 +value = -70.50863 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.mean_power_w] -value = 9.749601e-06 +value = 9.902665e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.minimum_return_distance] -value = 0.4602952062528 +value = 0.4813506833554 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_error_v] -value = 0.0004928816822619 +value = 0.0003491914165008 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_v] -value = 0.7004928816823 +value = 0.7003491914165 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.peak_v] -value = 0.7034029 +value = 0.7017873 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.phase_margin_deg] -value = 60.7746 +value = 62.0962 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.power_w] -value = 9.724546869294e-06 +value = 9.878475226905e-06 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.recovery_down_v] -value = 0.000485335 +value = 0.0003456681 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.recovery_up_v] -value = 0.0004928885 +value = 0.0003491928 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.return_phase_excursion_deg] -value = 89.78792543148 +value = 89.7830894866 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.step_gain] -value = 1.000038 +value = 1.000018 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.trough_v] -value = 0.4972896 +value = 0.498141 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.unity_hz] -value = 395477.9 +value = 387254.4 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_5.output_sha256] -op = "70da35e9a311b05761a5c2856ae58caba87dfa070c090cbe1fa7da4e1f80da41" -ac = "5b9b49ea97b0e6fe3ac25585465f54fcb6b9bf0d26e138c77fd716304f1ac433" -transient = "6a5085016afd117d2b6efc8c6a2062ffd90de4cfa895a42201d32a9a9bef6201" -voltage = "4b8201b4d14e0593aa26de5a10ac19c583de8ab011d6994b2594788cff32c479" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1957,7 +1914,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/input-pair-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl index 240fe8ec40eef8661313534c207675f67905b6e2..fd988de388734ace45fe79c9a38807a5c9a14f72 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl @@ -1,113 +1,39 @@ -* Derived from analog-db amp_012_peng_tcfc, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified: 10 nm MOS grid, equivalent parallel regrouping, explicit physical MIM/taps; -* disclosed bias and added physical compensation calibration. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_012_peng_tcfc vss vdd vinn vinp vout vb1 -MM12 vb4 vb3 net54 sub sg13_lv_nmos w=6.84u l=0.43u m=4 -MM13 net7 vb3 net56 sub sg13_lv_nmos w=6.84u l=0.43u m=4 -MM14 vb3 vb3 vss sub sg13_lv_nmos w=6.84u l=0.43u m=1 -MM15 voutn vb3 dm_2 sub sg13_lv_nmos w=6.84u l=0.43u m=8 -MM16 voutp vb3 net063 sub sg13_lv_nmos w=6.84u l=0.43u m=8 -MM17 net54 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=4 -MM18 net56 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=4 -MM19 dm_2 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=8 -MM20 net063 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=8 -MM23 vout net10 vss sub sg13_lv_nmos w=5.58u l=0.61u m=2 -MM63 vb2 vb3 net9 sub sg13_lv_nmos w=6.84u l=0.43u m=4 -MM64 net9 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=4 -MM69 net10 net043 vss sub sg13_lv_nmos w=9.3u l=9.14u m=2 -MM70 net043 net043 vss sub sg13_lv_nmos w=9.3u l=9.14u m=2 -MM8 dm_2 vinn net31 well_net31 sg13_lv_pmos w=5.5u l=2.06u m=4 -MM9 net063 vinp net31 well_net31 sg13_lv_pmos w=5.5u l=2.06u m=4 -RRtap_net31_0 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_1 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_2 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_3 net31 well_net31 ntap1 A=4e-12 P=8e-6 -MM0 net2 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM1 net3 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM10 net043 voutp vdd well_vdd sg13_lv_pmos w=7.83u l=0.75u m=4 -MM11 vout voutp vdd well_vdd sg13_lv_pmos w=9.06u l=0.54u m=4 -MM2 net6 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM3 net8 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM4 net31 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=2 -MM5 voutn voutn vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM57 vb1 vb2 net2 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM58 vb4 vb2 net3 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM6 voutp voutn vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM61 net7 vb2 net6 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM62 vb3 vb2 net8 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -MM65 vb2 vb2 vdd well_vdd sg13_lv_pmos w=1.44u l=4.94u m=1 -MM66 net10 vb2 net049 well_vdd sg13_lv_pmos w=8.64u l=4.94u m=8 -MM7 net049 vb1 vdd well_vdd sg13_lv_pmos w=8.64u l=4.94u m=8 -RRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_18 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_19 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRptap_0 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_1 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_2 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_3 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_4 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_5 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_6 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_7 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_8 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_9 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_10 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_11 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_12 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_13 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_14 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_15 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_16 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_17 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_18 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_19 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_20 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_21 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_22 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_23 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_24 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_25 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_26 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_27 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_28 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_29 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_30 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_31 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_32 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_33 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_34 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_35 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_36 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_37 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_38 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_39 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_40 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_41 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_42 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_43 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_44 vss sub ptap1 A=4e-12 P=8e-6 -CC0_0 voutp vout cap_cmim w=35.325u l=35.325u m=1 -CC1_0 net049 vout cap_cmim w=41.2u l=41.2u m=1 -CCLOCAL_0 net10 vout cap_cmim w=51.64u l=51.64u m=1 +MM0 net2 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM1 net3 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM10 net043 voutp vdd vdd sg13_lv_pmos w=7.83u l=0.75u m=4 +MM11 vout voutp vdd vdd sg13_lv_pmos w=9.06u l=0.54u m=4 +MM12 vb4 vb3 net54 vss sg13_lv_nmos w=1.71u l=0.43u m=16 +MM13 net7 vb3 net56 vss sg13_lv_nmos w=1.71u l=0.43u m=16 +MM14 vb3 vb3 vss vss sg13_lv_nmos w=1.71u l=0.43u m=4 +MM15 voutn vb3 dm_2 vss sg13_lv_nmos w=1.71u l=0.43u m=32 +MM16 voutp vb3 net063 vss sg13_lv_nmos w=1.71u l=0.43u m=32 +MM17 net54 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=16 +MM18 net56 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=16 +MM19 dm_2 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=32 +MM2 net6 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM20 net063 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=32 +MM23 vout net10 vss vss sg13_lv_nmos w=2.79u l=0.61u m=4 +MM3 net8 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM4 net31 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=32 +MM5 voutn voutn vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM57 vb1 vb2 net2 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM58 vb4 vb2 net3 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM6 voutp voutn vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM61 net7 vb2 net6 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM62 vb3 vb2 net8 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +MM63 vb2 vb3 net9 vss sg13_lv_nmos w=1.71u l=0.43u m=16 +MM64 net9 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=16 +MM65 vb2 vb2 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=4 +MM66 net10 vb2 net049 vdd sg13_lv_pmos w=0.36u l=4.94u m=192 +MM69 net10 net043 vss vss sg13_lv_nmos w=4.65u l=9.14u m=4 +MM7 net049 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=192 +MM70 net043 net043 vss vss sg13_lv_nmos w=4.65u l=9.14u m=4 +MM8 dm_2 vinn net31 net31 sg13_lv_pmos w=5.5u l=2.06u m=4 +MM9 net063 vinp net31 net31 sg13_lv_pmos w=5.5u l=2.06u m=4 +C0_0 voutp vout cap_cmim w=35.325u l=35.325u m=1 +C1_0 net049 vout cap_cmim w=41.2u l=41.2u m=1 +CLOCAL_0 net10 vout cap_cmim w=51.64u l=51.64u m=1 .ends amp_012_peng_tcfc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.spice index f675ac38e9ffcd9d28eee57a45bed693f86f0af9..368a16b735e17de4e57e21fa72ed07591e0d9395 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.spice @@ -1,112 +1,38 @@ -* Derived from analog-db amp_012_peng_tcfc, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified: 10 nm MOS grid, equivalent parallel regrouping, explicit physical MIM/taps; -* disclosed bias and added physical compensation calibration. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_012_peng_tcfc vss vdd vinn vinp vout vb1 -XM12 vb4 vb3 net54 sub sg13_lv_nmos w=6.84u l=0.43u m=4 -XM13 net7 vb3 net56 sub sg13_lv_nmos w=6.84u l=0.43u m=4 -XM14 vb3 vb3 vss sub sg13_lv_nmos w=6.84u l=0.43u m=1 -XM15 voutn vb3 dm_2 sub sg13_lv_nmos w=6.84u l=0.43u m=8 -XM16 voutp vb3 net063 sub sg13_lv_nmos w=6.84u l=0.43u m=8 -XM17 net54 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=4 -XM18 net56 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=4 -XM19 dm_2 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=8 -XM20 net063 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=8 -XM23 vout net10 vss sub sg13_lv_nmos w=5.58u l=0.61u m=2 -XM63 vb2 vb3 net9 sub sg13_lv_nmos w=6.84u l=0.43u m=4 -XM64 net9 vb4 vss sub sg13_lv_nmos w=6.84u l=0.43u m=4 -XM69 net10 net043 vss sub sg13_lv_nmos w=9.3u l=9.14u m=2 -XM70 net043 net043 vss sub sg13_lv_nmos w=9.3u l=9.14u m=2 -XM8 dm_2 vinn net31 well_net31 sg13_lv_pmos w=5.5u l=2.06u m=4 -XM9 net063 vinp net31 well_net31 sg13_lv_pmos w=5.5u l=2.06u m=4 -XRtap_net31_0 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_1 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_2 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_3 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XM0 net2 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM1 net3 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM10 net043 voutp vdd well_vdd sg13_lv_pmos w=7.83u l=0.75u m=4 -XM11 vout voutp vdd well_vdd sg13_lv_pmos w=9.06u l=0.54u m=4 -XM2 net6 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM3 net8 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM4 net31 vb1 vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=2 -XM5 voutn voutn vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM57 vb1 vb2 net2 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM58 vb4 vb2 net3 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM6 voutp voutn vdd well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM61 net7 vb2 net6 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM62 vb3 vb2 net8 well_vdd sg13_lv_pmos w=5.76u l=4.94u m=1 -XM65 vb2 vb2 vdd well_vdd sg13_lv_pmos w=1.44u l=4.94u m=1 -XM66 net10 vb2 net049 well_vdd sg13_lv_pmos w=8.64u l=4.94u m=8 -XM7 net049 vb1 vdd well_vdd sg13_lv_pmos w=8.64u l=4.94u m=8 -XRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_18 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_19 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRptap_0 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_1 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_2 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_3 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_4 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_5 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_6 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_7 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_8 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_9 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_10 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_11 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_12 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_13 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_14 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_15 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_16 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_17 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_18 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_19 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_20 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_21 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_22 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_23 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_24 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_25 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_26 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_27 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_28 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_29 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_30 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_31 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_32 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_33 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_34 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_35 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_36 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_37 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_38 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_39 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_40 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_41 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_42 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_43 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_44 vss sub ptap1 A=4e-12 P=8e-6 +XM0 net2 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM1 net3 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM10 net043 voutp vdd vdd sg13_lv_pmos w=7.83u l=0.75u m=4 +XM11 vout voutp vdd vdd sg13_lv_pmos w=9.06u l=0.54u m=4 +XM12 vb4 vb3 net54 vss sg13_lv_nmos w=1.71u l=0.43u m=16 +XM13 net7 vb3 net56 vss sg13_lv_nmos w=1.71u l=0.43u m=16 +XM14 vb3 vb3 vss vss sg13_lv_nmos w=1.71u l=0.43u m=4 +XM15 voutn vb3 dm_2 vss sg13_lv_nmos w=1.71u l=0.43u m=32 +XM16 voutp vb3 net063 vss sg13_lv_nmos w=1.71u l=0.43u m=32 +XM17 net54 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=16 +XM18 net56 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=16 +XM19 dm_2 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=32 +XM2 net6 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM20 net063 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=32 +XM23 vout net10 vss vss sg13_lv_nmos w=2.79u l=0.61u m=4 +XM3 net8 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM4 net31 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=32 +XM5 voutn voutn vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM57 vb1 vb2 net2 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM58 vb4 vb2 net3 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM6 voutp voutn vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM61 net7 vb2 net6 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM62 vb3 vb2 net8 vdd sg13_lv_pmos w=0.36u l=4.94u m=16 +XM63 vb2 vb3 net9 vss sg13_lv_nmos w=1.71u l=0.43u m=16 +XM64 net9 vb4 vss vss sg13_lv_nmos w=1.71u l=0.43u m=16 +XM65 vb2 vb2 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=4 +XM66 net10 vb2 net049 vdd sg13_lv_pmos w=0.36u l=4.94u m=192 +XM69 net10 net043 vss vss sg13_lv_nmos w=4.65u l=9.14u m=4 +XM7 net049 vb1 vdd vdd sg13_lv_pmos w=0.36u l=4.94u m=192 +XM70 net043 net043 vss vss sg13_lv_nmos w=4.65u l=9.14u m=4 +XM8 dm_2 vinn net31 net31 sg13_lv_pmos w=5.5u l=2.06u m=4 +XM9 net063 vinp net31 net31 sg13_lv_pmos w=5.5u l=2.06u m=4 XC0_0 voutp vout cap_cmim w=35.325u l=35.325u m=1 XC1_0 net049 vout cap_cmim w=41.2u l=41.2u m=1 XCLOCAL_0 net10 vout cap_cmim w=51.64u l=51.64u m=1 diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/schematic.svg deleted file mode 100644 index 414b5439cecb4e6b54a103333f2f072808e4d05f..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_012_peng_tcfc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_012_peng_tcfc","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_012_peng_tcfc","Bank1_20x_ntap1","Bank2_45x_ptap1"],"banks":[{"name":"Bank1_20x_ntap1","count":20,"model":"ntap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank2_45x_ptap1","count":45,"model":"ptap1","params":{"a":"4e-12","p":"8e-6"}}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_012_peng_tcfc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/design/amp_012_peng_tcfc.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_012_peng_tcfcvddwell_vddvsssubvinnvinpvddvoutpnet31vb3vb4vssdm_2net063voutnvoutpvb1vb2vddnet049net10vssnet043vb2net6voutpvddvb3net56net10vssnet7voutnet6net2net3net8net54vssvb2vb4vddvb3vb1net31vb1net56vb3vddvb4vssnet9vb2voutpnet049net10voutvddwell_vddvsssubnet31well_net31vssvddvinnvinpvoutvb1amp_012_peng_tcfcihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresDifferential input and folded branchesMM55.76/4.94MM65.76/4.94MM85.5/2.06 ×4MM95.5/2.06 ×4MM156.84/0.43 ×8MM166.84/0.43 ×8MM196.84/0.43 ×8MM206.84/0.43 ×8MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subIntermediate gainMM107.83/0.75 ×4MM78.64/4.94 ×8MM668.64/4.94 ×8MM709.3/9.14 ×2MM699.3/9.14 ×2P bulk → well_vddN bulk → subOutput stageMM615.76/4.94MM119.06/0.54 ×4MM136.84/0.43 ×4MM235.58/0.61 ×2P bulk → well_vddN bulk → subTail-current biasMM05.76/4.94MM15.76/4.94MM25.76/4.94MM35.76/4.94MM575.76/4.94MM585.76/4.94MM625.76/4.94MM126.84/0.43 ×4MM146.84/0.43MM176.84/0.43 ×4P bulk → well_vddN bulk → subBias networkMM45.76/4.94 ×2MM651.44/4.94MM186.84/0.43 ×4MM636.84/0.43 ×4MM646.84/0.43 ×4P bulk → well_vddN bulk → subCompensation capacitorsCC0_035.3/35.3CC1_041.2/41.2CCLOCAL_051.6/51.6Bulk ties and device banksRRtap_net31_0A=4 µm²RRtap_net31_1A=4 µm²RRtap_net31_2A=4 µm²RRtap_net31_3A=4 µm²XBANK1Bank1_20x_ntap1XBANK2Bank2_45x_ptap1Models: sg13_lv_nmos · sg13_lv_pmos · ntap1 · cap_cmim - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md index a4631bbc93bac9758f1379faea7782b035f21139..59dbbe3e87603b4326c2597419c9f7ce05793309 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md @@ -13,17 +13,17 @@ source-driven auxiliary PMOS and a separate `net10` control node. ## Inputs and Interface - `materials/circuit.cdl`: authoritative native physical connectivity. -- `materials/circuit.spice`: equivalent simulation connectivity including finite body contacts. +- `materials/circuit.spice`: equivalent simulation connectivity with logical body nets. - `materials/testbench.spice`: DC, bilateral-loop and sustained-step measurements. Ordered ports: `vss vdd vinn vinp vout vb1`. VSS/VDD are return/supply; VINN/VINP are inverting/noninverting inputs; VOUT is output; `vb1` connects to the external bias sink. Input PMOS bodies use the separate `net31` source-tied well; other PMOS use VDD and NMOS use the VSS substrate. -Preserve all 32 MOS groups, 108 physical fingers, +Preserve all 32 MOS groups, W/L/m, every body connection and all physical passive devices. -MOS dimensions are rounded to the 10 nm physical grid. Parallel regrouping within each original group preserves rounded total W and L, with each finger at most 10 um wide; individual widths/multiplicities and diffusion perimeters change accordingly. Distributed 2 × 2 um body contacts have spacing at most 20 um. All internal capacitors use `cap_cmim`: +MOS dimensions retain the declared grid adaptation. All internal capacitors use `cap_cmim`: - `c0`: `voutp` (top) to `vout` (bottom), 1 parallel 35.325 × 35.325 um MIM units. - `c1`: `net049` (top) to `vout` (bottom), 1 parallel 41.2 × 41.2 um MIM units. @@ -59,9 +59,8 @@ Post-layout simulation uses the submitted GDS's complete Magic RC, with physical MIM devices and interconnect resistances/capacitances. Half-grid import is explicit. Magic retains only Metal3 interface labels in its isolated extraction copy to avoid repeated internal well-name aliases, while native LVS -checks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics. -Magic idealizes well/substrate taps, whereas source simulation uses finite -physical tap models. Distributed substrate resistance/noise and fabrication +checks the original GDS and its actual body-contact connectivity. No resistance/capacitance threshold omits small parasitics. +Source simulation and extraction use the same logical body-net boundary. Distributed substrate resistance/noise and fabrication signoff remain unqualified. The long independent witness is a feasibility layout, not an area optimum. @@ -102,7 +101,7 @@ The measurements below use the supplied SPICE node and source names. `v(n)` is a | `peak_v` | TRAN: Maximum of `v(vout) from=2u to=20u`. | V | target / target | 0 … 1.2 | 1.2 | response | | `trough_v` | TRAN: Minimum of `v(vout) from=20.04u to=40u`. | V | target / target | 0 … 1.2 | 1.2 | response | -Area reference: **14710.04 um2**. The expanded circuit has 180 device instances, a sum of device/contact envelopes 9648.5648 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. +Area reference: **14710.04 um2**. The reference engineering estimate used 180 device instances, a sum of device/contact envelopes 9648.5648 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. Reference MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. The capability coefficient is **8**, independent of this task's reference-normalized score. @@ -137,3 +136,5 @@ Multiple-crossing feedback amplifier: loaded recovery 28.6%, loop stability 24.5 Solve budget: **3 hours**. Discover inputs, resources and feedback through `/protocol/task.json`, `/protocol/resources.json`, `/protocol/harness.json`. Use supplied IHP primitives and KLayout, Magic and ngspice; explicitly submit after writing `/workspace/output/final.gds`. Host configuration, source records and reference solutions are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml index 506913836d6ccb044a3bf5ed28f7685f24656cd1..bca8a0ee61906fc518e28225d3a03842a1804ae7 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml @@ -4,13 +4,6 @@ title = "Qu AZC Three-Stage Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "df99e8e154f6d2e13707f707f2d7a656ea5493085068be197198cae52dbed55e" - [[assets]] path = "reference/amp_013_qu2017_azc.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "2270686e30b94f981b2fee7ff05c987a07897d4dd178b4bc243ca42a0cbbb341" +sha256 = "42f20d1cd5f4a0a8009523dfb405c4a21f0504bb43a845f57b913e789b56bd46" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_013_qu2017_azc" -sha256 = "482f6b9455334bd331c08b6de22220b5256182a28ee463283da40ab2867df6a6" +sha256 = "f1c405743131712ff44eafdf85b9f6e40c61ac65c538182a4bec0cf44579e616" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "63f1c84d74c2ec03057cf2ab513dfbbc173266fc403a331981deaa66e6e33551" +sha256 = "2f1a9caf95517f4c602959f192e6ff099282069f497f868c5f49d9e7357e328b" [task.inputs.performance] path = "materials/testbench.spice" @@ -686,10 +679,10 @@ upper = 1e-06 rationale = "The ideal external feedback/injection fixture must preserve its stated common mode and DC feedback; 1 uV is the numerical consistency allowance for this measurement fixture." [task.evaluation.pre_layout] -source_report_sha256 = "105e0e26ab525de12941a695279c8a98d4d66febfa49db7b5bf5b5f987db7f5a" +source_report_sha256 = "5de55949e3327462b8a38db423235a28170d2dfa6317807d36b13f407e90757a" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 1800.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 1800.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -729,65 +722,60 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "c160b300a8f070147997df2a000cbfd7ef09ffe28ce93aa2b4d5d33a828d00ff" -dut = "63f1c84d74c2ec03057cf2ab513dfbbc173266fc403a331981deaa66e6e33551" +dut = "2f1a9caf95517f4c602959f192e6ff099282069f497f868c5f49d9e7357e328b" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 1.106408136361689 +value = 1.106410555268603 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = -0.0006658398 +value = -0.0006657897 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] -value = 0.3938931706107707 +value = 0.3940250246805287 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] -value = 0.02909861622344614 +value = 0.02906201638790085 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] -value = 0.29507192800025 +value = 0.2950464364374132 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0003398277773450229 +value = 0.0003398613629894957 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] -value = 0.4332952725833847 +value = 0.4333186941545583 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] -value = 0.2366318588599606 +value = 0.2365602863304346 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.2992326076073368 +value = 0.2992325664171176 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 7.228702551803354e-05 +value = 7.228401952144102e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 0.0257629279228255 +value = 0.02582645927647871 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] -value = 0.09314135562037715 +value = 0.09324935689532668 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 0.1068905197572205 +value = 0.1070134476773065 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "277023e2145aba32ef850c096695b2e65593c38b53d97c0687814c6af8ace460" -ac = "3daef6f7893ad6dc980b07cdafffbe768c840639d13cb549c4d0b1b60697d862" -transient = "2b1b21a6e906f221a52471196a04c92b1821cd9c0f5015b35b970d7a09516d43" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -814,28 +802,24 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "758aa46451c448bb5ea8b6fcbcd40695197aafcfa5df33384de2ddc79eb2ebf1" -dut = "63f1c84d74c2ec03057cf2ab513dfbbc173266fc403a331981deaa66e6e33551" +dut = "2f1a9caf95517f4c602959f192e6ff099282069f497f868c5f49d9e7357e328b" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] -value = 0.0 +value = 5.551115123125783e-17 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] -value = 1.209647588703213e-10 +value = 1.214851671311152e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] -value = 51.5633 +value = 51.56303 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] -value = 79.63834 +value = 79.63867 unit = "dB" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "4d518c78bdb66e730bd4a5713638c3aedb2dbce43a91a5c708c40a96ebdf2f66" -ac = "4ba69474fd966c7506aa6e10e4f40fd5f0c2f2bd643613693155cd26ae9998a6" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -875,7 +859,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl index a05179e28a477a0c9f804f66e02139dac987cc39..02d17c4a461681f0f6db9e6803f2e02b3692dacd 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl @@ -1,317 +1,37 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_013_qu2017_azc vss vdd vinn vinp vout vb1 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM0_0 vb1 vb1 vdd well_0 sg13_lv_pmos w=1u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM0_1 vb1 vb1 vdd well_1 sg13_lv_pmos w=1u l=1u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM0_2 vb1 vb1 vdd well_2 sg13_lv_pmos w=1u l=1u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM0_3 vb1 vb1 vdd well_3 sg13_lv_pmos w=1u l=1u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM1_0 vb4 vb1 vdd well_4 sg13_lv_pmos w=1u l=1u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM1_1 vb4 vb1 vdd well_5 sg13_lv_pmos w=1u l=1u m=1 -RT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -MM1_2 vb4 vb1 vdd well_6 sg13_lv_pmos w=1u l=1u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM1_3 vb4 vb1 vdd well_7 sg13_lv_pmos w=1u l=1u m=1 -RT8 net019 well_8 ntap1 A=4e-12 P=8e-6 -MM10_0 net063 vinp net019 well_8 sg13_lv_pmos w=1u l=1u m=1 -RT9 net019 well_9 ntap1 A=4e-12 P=8e-6 -MM10_1 net063 vinp net019 well_9 sg13_lv_pmos w=1u l=1u m=1 -RT10 net019 well_10 ntap1 A=4e-12 P=8e-6 -MM10_2 net063 vinp net019 well_10 sg13_lv_pmos w=1u l=1u m=1 -RT11 net019 well_11 ntap1 A=4e-12 P=8e-6 -MM10_3 net063 vinp net019 well_11 sg13_lv_pmos w=1u l=1u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM11_0 net094 net050 vdd well_12 sg13_lv_pmos w=1u l=1u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM11_1 net094 net050 vdd well_13 sg13_lv_pmos w=1u l=1u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM11_2 net094 net050 vdd well_14 sg13_lv_pmos w=1u l=1u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM11_3 net094 net050 vdd well_15 sg13_lv_pmos w=1u l=1u m=1 -RT16 vss sub ptap1 A=4e-12 P=8e-6 -MM12_0 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT17 vss sub ptap1 A=4e-12 P=8e-6 -MM12_1 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT18 vss sub ptap1 A=4e-12 P=8e-6 -MM12_2 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT19 vss sub ptap1 A=4e-12 P=8e-6 -MM12_3 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM13_0 vout net050 vdd well_20 sg13_lv_pmos w=1u l=1u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM13_1 vout net050 vdd well_21 sg13_lv_pmos w=1u l=1u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM13_2 vout net050 vdd well_22 sg13_lv_pmos w=1u l=1u m=1 -RT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -MM13_3 vout net050 vdd well_23 sg13_lv_pmos w=1u l=1u m=1 -RT24 vss sub ptap1 A=4e-12 P=8e-6 -MM14_0 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT25 vss sub ptap1 A=4e-12 P=8e-6 -MM14_1 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT26 vss sub ptap1 A=4e-12 P=8e-6 -MM14_2 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT27 vss sub ptap1 A=4e-12 P=8e-6 -MM14_3 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT28 vss sub ptap1 A=4e-12 P=8e-6 -MM15_0 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT29 vss sub ptap1 A=4e-12 P=8e-6 -MM15_1 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT30 vss sub ptap1 A=4e-12 P=8e-6 -MM15_2 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT31 vss sub ptap1 A=4e-12 P=8e-6 -MM15_3 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT32 vss sub ptap1 A=4e-12 P=8e-6 -MM16_0 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT33 vss sub ptap1 A=4e-12 P=8e-6 -MM16_1 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT34 vss sub ptap1 A=4e-12 P=8e-6 -MM16_2 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT35 vss sub ptap1 A=4e-12 P=8e-6 -MM16_3 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT36 vss sub ptap1 A=4e-12 P=8e-6 -MM17_0 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT37 vss sub ptap1 A=4e-12 P=8e-6 -MM17_1 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT38 vss sub ptap1 A=4e-12 P=8e-6 -MM17_2 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT39 vss sub ptap1 A=4e-12 P=8e-6 -MM17_3 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT40 vss sub ptap1 A=4e-12 P=8e-6 -MM18_0 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT41 vss sub ptap1 A=4e-12 P=8e-6 -MM18_1 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT42 vss sub ptap1 A=4e-12 P=8e-6 -MM18_2 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT43 vss sub ptap1 A=4e-12 P=8e-6 -MM18_3 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT44 vss sub ptap1 A=4e-12 P=8e-6 -MM19_0 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -RT45 vss sub ptap1 A=4e-12 P=8e-6 -MM19_1 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -RT46 vss sub ptap1 A=4e-12 P=8e-6 -MM19_2 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -RT47 vss sub ptap1 A=4e-12 P=8e-6 -MM19_3 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -RT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -MM2_0 net019 vb1 vdd well_48 sg13_lv_pmos w=1u l=1u m=1 -RT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -MM2_1 net019 vb1 vdd well_49 sg13_lv_pmos w=1u l=1u m=1 -RT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -MM2_2 net019 vb1 vdd well_50 sg13_lv_pmos w=1u l=1u m=1 -RT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -MM2_3 net019 vb1 vdd well_51 sg13_lv_pmos w=1u l=1u m=1 -RT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -MM2_4 net019 vb1 vdd well_52 sg13_lv_pmos w=1u l=1u m=1 -RT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -MM2_5 net019 vb1 vdd well_53 sg13_lv_pmos w=1u l=1u m=1 -RT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -MM2_6 net019 vb1 vdd well_54 sg13_lv_pmos w=1u l=1u m=1 -RT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -MM2_7 net019 vb1 vdd well_55 sg13_lv_pmos w=1u l=1u m=1 -RT56 vss sub ptap1 A=4e-12 P=8e-6 -MM20_0 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT57 vss sub ptap1 A=4e-12 P=8e-6 -MM20_1 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT58 vss sub ptap1 A=4e-12 P=8e-6 -MM20_2 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT59 vss sub ptap1 A=4e-12 P=8e-6 -MM20_3 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT60 vss sub ptap1 A=4e-12 P=8e-6 -MM21_0 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT61 vss sub ptap1 A=4e-12 P=8e-6 -MM21_1 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT62 vss sub ptap1 A=4e-12 P=8e-6 -MM21_2 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT63 vss sub ptap1 A=4e-12 P=8e-6 -MM21_3 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -RT64 vss sub ptap1 A=4e-12 P=8e-6 -MM22_0 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT65 vss sub ptap1 A=4e-12 P=8e-6 -MM22_1 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT66 vss sub ptap1 A=4e-12 P=8e-6 -MM22_2 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT67 vss sub ptap1 A=4e-12 P=8e-6 -MM22_3 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT68 vss sub ptap1 A=4e-12 P=8e-6 -MM22_4 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT69 vss sub ptap1 A=4e-12 P=8e-6 -MM22_5 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT70 vss sub ptap1 A=4e-12 P=8e-6 -MM22_6 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT71 vss sub ptap1 A=4e-12 P=8e-6 -MM22_7 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT72 vss sub ptap1 A=4e-12 P=8e-6 -MM22_8 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT73 vss sub ptap1 A=4e-12 P=8e-6 -MM22_9 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT74 vss sub ptap1 A=4e-12 P=8e-6 -MM22_10 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT75 vss sub ptap1 A=4e-12 P=8e-6 -MM22_11 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT76 vss sub ptap1 A=4e-12 P=8e-6 -MM22_12 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT77 vss sub ptap1 A=4e-12 P=8e-6 -MM22_13 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT78 vss sub ptap1 A=4e-12 P=8e-6 -MM22_14 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT79 vss sub ptap1 A=4e-12 P=8e-6 -MM22_15 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT80 vss sub ptap1 A=4e-12 P=8e-6 -MM23_0 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT81 vss sub ptap1 A=4e-12 P=8e-6 -MM23_1 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT82 vss sub ptap1 A=4e-12 P=8e-6 -MM23_2 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT83 vss sub ptap1 A=4e-12 P=8e-6 -MM23_3 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT84 vss sub ptap1 A=4e-12 P=8e-6 -MM23_4 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT85 vss sub ptap1 A=4e-12 P=8e-6 -MM23_5 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT86 vss sub ptap1 A=4e-12 P=8e-6 -MM23_6 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT87 vss sub ptap1 A=4e-12 P=8e-6 -MM23_7 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT88 vss sub ptap1 A=4e-12 P=8e-6 -MM23_8 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT89 vss sub ptap1 A=4e-12 P=8e-6 -MM23_9 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT90 vss sub ptap1 A=4e-12 P=8e-6 -MM23_10 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT91 vss sub ptap1 A=4e-12 P=8e-6 -MM23_11 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT92 vss sub ptap1 A=4e-12 P=8e-6 -MM24_0 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT93 vss sub ptap1 A=4e-12 P=8e-6 -MM24_1 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT94 vss sub ptap1 A=4e-12 P=8e-6 -MM24_2 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT95 vss sub ptap1 A=4e-12 P=8e-6 -MM24_3 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT96 vdd well_96 ntap1 A=4e-12 P=8e-6 -MM3_0 net078 vb1 vdd well_96 sg13_lv_pmos w=1u l=1u m=1 -RT97 vdd well_97 ntap1 A=4e-12 P=8e-6 -MM3_1 net078 vb1 vdd well_97 sg13_lv_pmos w=1u l=1u m=1 -RT98 vdd well_98 ntap1 A=4e-12 P=8e-6 -MM3_2 net078 vb1 vdd well_98 sg13_lv_pmos w=1u l=1u m=1 -RT99 vdd well_99 ntap1 A=4e-12 P=8e-6 -MM3_3 net078 vb1 vdd well_99 sg13_lv_pmos w=1u l=1u m=1 -RT100 vdd well_100 ntap1 A=4e-12 P=8e-6 -MM3_4 net078 vb1 vdd well_100 sg13_lv_pmos w=1u l=1u m=1 -RT101 vdd well_101 ntap1 A=4e-12 P=8e-6 -MM3_5 net078 vb1 vdd well_101 sg13_lv_pmos w=1u l=1u m=1 -RT102 vdd well_102 ntap1 A=4e-12 P=8e-6 -MM3_6 net078 vb1 vdd well_102 sg13_lv_pmos w=1u l=1u m=1 -RT103 vdd well_103 ntap1 A=4e-12 P=8e-6 -MM3_7 net078 vb1 vdd well_103 sg13_lv_pmos w=1u l=1u m=1 -RT104 vdd well_104 ntap1 A=4e-12 P=8e-6 -MM3_8 net078 vb1 vdd well_104 sg13_lv_pmos w=1u l=1u m=1 -RT105 vdd well_105 ntap1 A=4e-12 P=8e-6 -MM3_9 net078 vb1 vdd well_105 sg13_lv_pmos w=1u l=1u m=1 -RT106 vdd well_106 ntap1 A=4e-12 P=8e-6 -MM3_10 net078 vb1 vdd well_106 sg13_lv_pmos w=1u l=1u m=1 -RT107 vdd well_107 ntap1 A=4e-12 P=8e-6 -MM3_11 net078 vb1 vdd well_107 sg13_lv_pmos w=1u l=1u m=1 -RT108 vdd well_108 ntap1 A=4e-12 P=8e-6 -MM3_12 net078 vb1 vdd well_108 sg13_lv_pmos w=1u l=1u m=1 -RT109 vdd well_109 ntap1 A=4e-12 P=8e-6 -MM3_13 net078 vb1 vdd well_109 sg13_lv_pmos w=1u l=1u m=1 -RT110 vdd well_110 ntap1 A=4e-12 P=8e-6 -MM3_14 net078 vb1 vdd well_110 sg13_lv_pmos w=1u l=1u m=1 -RT111 vdd well_111 ntap1 A=4e-12 P=8e-6 -MM3_15 net078 vb1 vdd well_111 sg13_lv_pmos w=1u l=1u m=1 -RT112 vdd well_112 ntap1 A=4e-12 P=8e-6 -MM3_16 net078 vb1 vdd well_112 sg13_lv_pmos w=1u l=1u m=1 -RT113 vdd well_113 ntap1 A=4e-12 P=8e-6 -MM3_17 net078 vb1 vdd well_113 sg13_lv_pmos w=1u l=1u m=1 -RT114 vdd well_114 ntap1 A=4e-12 P=8e-6 -MM3_18 net078 vb1 vdd well_114 sg13_lv_pmos w=1u l=1u m=1 -RT115 vdd well_115 ntap1 A=4e-12 P=8e-6 -MM3_19 net078 vb1 vdd well_115 sg13_lv_pmos w=1u l=1u m=1 -RT116 vdd well_116 ntap1 A=4e-12 P=8e-6 -MM3_20 net078 vb1 vdd well_116 sg13_lv_pmos w=1u l=1u m=1 -RT117 vdd well_117 ntap1 A=4e-12 P=8e-6 -MM3_21 net078 vb1 vdd well_117 sg13_lv_pmos w=1u l=1u m=1 -RT118 vdd well_118 ntap1 A=4e-12 P=8e-6 -MM3_22 net078 vb1 vdd well_118 sg13_lv_pmos w=1u l=1u m=1 -RT119 vdd well_119 ntap1 A=4e-12 P=8e-6 -MM3_23 net078 vb1 vdd well_119 sg13_lv_pmos w=1u l=1u m=1 -RT120 vdd well_120 ntap1 A=4e-12 P=8e-6 -MM4_0 voutn voutn vdd well_120 sg13_lv_pmos w=1u l=1u m=1 -RT121 vdd well_121 ntap1 A=4e-12 P=8e-6 -MM4_1 voutn voutn vdd well_121 sg13_lv_pmos w=1u l=1u m=1 -RT122 vdd well_122 ntap1 A=4e-12 P=8e-6 -MM4_2 voutn voutn vdd well_122 sg13_lv_pmos w=1u l=1u m=1 -RT123 vdd well_123 ntap1 A=4e-12 P=8e-6 -MM4_3 voutn voutn vdd well_123 sg13_lv_pmos w=1u l=1u m=1 -RT124 vdd well_124 ntap1 A=4e-12 P=8e-6 -MM5_0 net050 voutn vdd well_124 sg13_lv_pmos w=1u l=1u m=1 -RT125 vdd well_125 ntap1 A=4e-12 P=8e-6 -MM5_1 net050 voutn vdd well_125 sg13_lv_pmos w=1u l=1u m=1 -RT126 vdd well_126 ntap1 A=4e-12 P=8e-6 -MM5_2 net050 voutn vdd well_126 sg13_lv_pmos w=1u l=1u m=1 -RT127 vdd well_127 ntap1 A=4e-12 P=8e-6 -MM5_3 net050 voutn vdd well_127 sg13_lv_pmos w=1u l=1u m=1 -RT128 vdd well_128 ntap1 A=4e-12 P=8e-6 -MM6_0 net055 net055 vdd well_128 sg13_lv_pmos w=1u l=1u m=1 -RT129 vdd well_129 ntap1 A=4e-12 P=8e-6 -MM6_1 net055 net055 vdd well_129 sg13_lv_pmos w=1u l=1u m=1 -RT130 vdd well_130 ntap1 A=4e-12 P=8e-6 -MM6_2 net055 net055 vdd well_130 sg13_lv_pmos w=1u l=1u m=1 -RT131 vdd well_131 ntap1 A=4e-12 P=8e-6 -MM6_3 net055 net055 vdd well_131 sg13_lv_pmos w=1u l=1u m=1 -RT132 vdd well_132 ntap1 A=4e-12 P=8e-6 -MM7_0 net057 net055 vdd well_132 sg13_lv_pmos w=1u l=1u m=1 -RT133 vdd well_133 ntap1 A=4e-12 P=8e-6 -MM7_1 net057 net055 vdd well_133 sg13_lv_pmos w=1u l=1u m=1 -RT134 vdd well_134 ntap1 A=4e-12 P=8e-6 -MM7_2 net057 net055 vdd well_134 sg13_lv_pmos w=1u l=1u m=1 -RT135 vdd well_135 ntap1 A=4e-12 P=8e-6 -MM7_3 net057 net055 vdd well_135 sg13_lv_pmos w=1u l=1u m=1 -RT136 vdd well_136 ntap1 A=4e-12 P=8e-6 -MM7_4 net057 net055 vdd well_136 sg13_lv_pmos w=1u l=1u m=1 -RT137 vdd well_137 ntap1 A=4e-12 P=8e-6 -MM7_5 net057 net055 vdd well_137 sg13_lv_pmos w=1u l=1u m=1 -RT138 vdd well_138 ntap1 A=4e-12 P=8e-6 -MM7_6 net057 net055 vdd well_138 sg13_lv_pmos w=1u l=1u m=1 -RT139 vdd well_139 ntap1 A=4e-12 P=8e-6 -MM7_7 net057 net055 vdd well_139 sg13_lv_pmos w=1u l=1u m=1 -RT140 vdd well_140 ntap1 A=4e-12 P=8e-6 -MM8_0 net049 vb1 vdd well_140 sg13_lv_pmos w=1u l=1u m=1 -RT141 vdd well_141 ntap1 A=4e-12 P=8e-6 -MM8_1 net049 vb1 vdd well_141 sg13_lv_pmos w=1u l=1u m=1 -RT142 vdd well_142 ntap1 A=4e-12 P=8e-6 -MM8_2 net049 vb1 vdd well_142 sg13_lv_pmos w=1u l=1u m=1 -RT143 vdd well_143 ntap1 A=4e-12 P=8e-6 -MM8_3 net049 vb1 vdd well_143 sg13_lv_pmos w=1u l=1u m=1 -RT144 vdd well_144 ntap1 A=4e-12 P=8e-6 -MM8_4 net049 vb1 vdd well_144 sg13_lv_pmos w=1u l=1u m=1 -RT145 vdd well_145 ntap1 A=4e-12 P=8e-6 -MM8_5 net049 vb1 vdd well_145 sg13_lv_pmos w=1u l=1u m=1 -RT146 vdd well_146 ntap1 A=4e-12 P=8e-6 -MM8_6 net049 vb1 vdd well_146 sg13_lv_pmos w=1u l=1u m=1 -RT147 vdd well_147 ntap1 A=4e-12 P=8e-6 -MM8_7 net049 vb1 vdd well_147 sg13_lv_pmos w=1u l=1u m=1 -RT148 net019 well_148 ntap1 A=4e-12 P=8e-6 -MM9_0 dm_2 vinn net019 well_148 sg13_lv_pmos w=1u l=1u m=1 -RT149 net019 well_149 ntap1 A=4e-12 P=8e-6 -MM9_1 dm_2 vinn net019 well_149 sg13_lv_pmos w=1u l=1u m=1 -RT150 net019 well_150 ntap1 A=4e-12 P=8e-6 -MM9_2 dm_2 vinn net019 well_150 sg13_lv_pmos w=1u l=1u m=1 -RT151 net019 well_151 ntap1 A=4e-12 P=8e-6 -MM9_3 dm_2 vinn net019 well_151 sg13_lv_pmos w=1u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM0 vb1 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM1 vb4 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM10 net063 vinp net019 net019 sg13_lv_pmos w=1u l=1u m=4 +MM11 net094 net050 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM12 net055 net094 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM13 vout net050 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM14 voutn net077 dm_2 vss sg13_lv_nmos w=1u l=1u m=4 +MM15 net050 net082 net063 vss sg13_lv_nmos w=1u l=1u m=4 +MM16 net077 dm_2 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM17 net082 net063 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM18 vout net049 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM19 vb4 vb4 vss vss sg13_lv_nmos w=2u l=1u m=4 +MM2 net019 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +MM20 dm_2 vb4 vss vss sg13_lv_nmos w=7u l=1u m=4 +MM21 net063 vb4 vss vss sg13_lv_nmos w=7u l=1u m=4 +MM22 net094 net051 vss vss sg13_lv_nmos w=1u l=1u m=16 +MM23 net057 net043 vss vss sg13_lv_nmos w=1u l=1u m=12 +MM24 net049 net057 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM3 net078 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=24 +MM4 voutn voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM5 net050 voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM6 net055 net055 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM7 net057 net055 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +MM8 net049 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +MM9 dm_2 vinn net019 net019 sg13_lv_pmos w=1u l=1u m=4 C0_0 net063 vout cap_cmim w=23.18u l=23.18u m=1 C1_0 net051 vss cap_cmim w=16.36u l=16.36u m=1 C2_0 net043 vss cap_cmim w=14.32u l=14.32u m=1 -RR0_0 net078 net077 sub rhigh w=.5u l=11.73u m=1 b=0 -RR1_0 net078 net082 sub rhigh w=.5u l=11.73u m=1 b=0 -RR2_0 net057 R2_s1 sub rhigh w=.5u l=59.08u m=1 b=0 -RR2_1 R2_s1 net051 sub rhigh w=.5u l=59.08u m=1 b=0 -RR3_0 net057 net043 sub rhigh w=.5u l=13.42u m=1 b=0 +RR0_0 net078 net077 vss rhigh w=.5u l=11.73u m=1 b=0 +RR1_0 net078 net082 vss rhigh w=.5u l=11.73u m=1 b=0 +RR2_0 net057 R2_s1 vss rhigh w=.5u l=59.08u m=1 b=0 +RR2_1 R2_s1 net051 vss rhigh w=.5u l=59.08u m=1 b=0 +RR3_0 net057 net043 vss rhigh w=.5u l=13.42u m=1 b=0 .ends amp_013_qu2017_azc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.spice index c4e3596dc36ee546befd568652682e0d40ef87c5..d2f406136e583955b09d9af31e9817ce9f72d1f4 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.spice @@ -1,317 +1,37 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_013_qu2017_azc vss vdd vinn vinp vout vb1 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM0_0 vb1 vb1 vdd well_0 sg13_lv_pmos w=1u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM0_1 vb1 vb1 vdd well_1 sg13_lv_pmos w=1u l=1u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM0_2 vb1 vb1 vdd well_2 sg13_lv_pmos w=1u l=1u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM0_3 vb1 vb1 vdd well_3 sg13_lv_pmos w=1u l=1u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM1_0 vb4 vb1 vdd well_4 sg13_lv_pmos w=1u l=1u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM1_1 vb4 vb1 vdd well_5 sg13_lv_pmos w=1u l=1u m=1 -XT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -XM1_2 vb4 vb1 vdd well_6 sg13_lv_pmos w=1u l=1u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM1_3 vb4 vb1 vdd well_7 sg13_lv_pmos w=1u l=1u m=1 -XT8 net019 well_8 ntap1 A=4e-12 P=8e-6 -XM10_0 net063 vinp net019 well_8 sg13_lv_pmos w=1u l=1u m=1 -XT9 net019 well_9 ntap1 A=4e-12 P=8e-6 -XM10_1 net063 vinp net019 well_9 sg13_lv_pmos w=1u l=1u m=1 -XT10 net019 well_10 ntap1 A=4e-12 P=8e-6 -XM10_2 net063 vinp net019 well_10 sg13_lv_pmos w=1u l=1u m=1 -XT11 net019 well_11 ntap1 A=4e-12 P=8e-6 -XM10_3 net063 vinp net019 well_11 sg13_lv_pmos w=1u l=1u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM11_0 net094 net050 vdd well_12 sg13_lv_pmos w=1u l=1u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM11_1 net094 net050 vdd well_13 sg13_lv_pmos w=1u l=1u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM11_2 net094 net050 vdd well_14 sg13_lv_pmos w=1u l=1u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM11_3 net094 net050 vdd well_15 sg13_lv_pmos w=1u l=1u m=1 -XT16 vss sub ptap1 A=4e-12 P=8e-6 -XM12_0 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT17 vss sub ptap1 A=4e-12 P=8e-6 -XM12_1 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT18 vss sub ptap1 A=4e-12 P=8e-6 -XM12_2 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT19 vss sub ptap1 A=4e-12 P=8e-6 -XM12_3 net055 net094 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM13_0 vout net050 vdd well_20 sg13_lv_pmos w=1u l=1u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM13_1 vout net050 vdd well_21 sg13_lv_pmos w=1u l=1u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM13_2 vout net050 vdd well_22 sg13_lv_pmos w=1u l=1u m=1 -XT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -XM13_3 vout net050 vdd well_23 sg13_lv_pmos w=1u l=1u m=1 -XT24 vss sub ptap1 A=4e-12 P=8e-6 -XM14_0 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT25 vss sub ptap1 A=4e-12 P=8e-6 -XM14_1 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT26 vss sub ptap1 A=4e-12 P=8e-6 -XM14_2 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT27 vss sub ptap1 A=4e-12 P=8e-6 -XM14_3 voutn net077 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT28 vss sub ptap1 A=4e-12 P=8e-6 -XM15_0 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT29 vss sub ptap1 A=4e-12 P=8e-6 -XM15_1 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT30 vss sub ptap1 A=4e-12 P=8e-6 -XM15_2 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT31 vss sub ptap1 A=4e-12 P=8e-6 -XM15_3 net050 net082 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT32 vss sub ptap1 A=4e-12 P=8e-6 -XM16_0 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT33 vss sub ptap1 A=4e-12 P=8e-6 -XM16_1 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT34 vss sub ptap1 A=4e-12 P=8e-6 -XM16_2 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT35 vss sub ptap1 A=4e-12 P=8e-6 -XM16_3 net077 dm_2 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT36 vss sub ptap1 A=4e-12 P=8e-6 -XM17_0 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT37 vss sub ptap1 A=4e-12 P=8e-6 -XM17_1 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT38 vss sub ptap1 A=4e-12 P=8e-6 -XM17_2 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT39 vss sub ptap1 A=4e-12 P=8e-6 -XM17_3 net082 net063 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT40 vss sub ptap1 A=4e-12 P=8e-6 -XM18_0 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT41 vss sub ptap1 A=4e-12 P=8e-6 -XM18_1 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT42 vss sub ptap1 A=4e-12 P=8e-6 -XM18_2 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT43 vss sub ptap1 A=4e-12 P=8e-6 -XM18_3 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT44 vss sub ptap1 A=4e-12 P=8e-6 -XM19_0 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -XT45 vss sub ptap1 A=4e-12 P=8e-6 -XM19_1 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -XT46 vss sub ptap1 A=4e-12 P=8e-6 -XM19_2 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -XT47 vss sub ptap1 A=4e-12 P=8e-6 -XM19_3 vb4 vb4 vss sub sg13_lv_nmos w=2u l=1u m=1 -XT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -XM2_0 net019 vb1 vdd well_48 sg13_lv_pmos w=1u l=1u m=1 -XT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -XM2_1 net019 vb1 vdd well_49 sg13_lv_pmos w=1u l=1u m=1 -XT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -XM2_2 net019 vb1 vdd well_50 sg13_lv_pmos w=1u l=1u m=1 -XT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -XM2_3 net019 vb1 vdd well_51 sg13_lv_pmos w=1u l=1u m=1 -XT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -XM2_4 net019 vb1 vdd well_52 sg13_lv_pmos w=1u l=1u m=1 -XT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -XM2_5 net019 vb1 vdd well_53 sg13_lv_pmos w=1u l=1u m=1 -XT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -XM2_6 net019 vb1 vdd well_54 sg13_lv_pmos w=1u l=1u m=1 -XT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -XM2_7 net019 vb1 vdd well_55 sg13_lv_pmos w=1u l=1u m=1 -XT56 vss sub ptap1 A=4e-12 P=8e-6 -XM20_0 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT57 vss sub ptap1 A=4e-12 P=8e-6 -XM20_1 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT58 vss sub ptap1 A=4e-12 P=8e-6 -XM20_2 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT59 vss sub ptap1 A=4e-12 P=8e-6 -XM20_3 dm_2 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT60 vss sub ptap1 A=4e-12 P=8e-6 -XM21_0 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT61 vss sub ptap1 A=4e-12 P=8e-6 -XM21_1 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT62 vss sub ptap1 A=4e-12 P=8e-6 -XM21_2 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT63 vss sub ptap1 A=4e-12 P=8e-6 -XM21_3 net063 vb4 vss sub sg13_lv_nmos w=7u l=1u m=1 -XT64 vss sub ptap1 A=4e-12 P=8e-6 -XM22_0 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT65 vss sub ptap1 A=4e-12 P=8e-6 -XM22_1 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT66 vss sub ptap1 A=4e-12 P=8e-6 -XM22_2 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT67 vss sub ptap1 A=4e-12 P=8e-6 -XM22_3 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT68 vss sub ptap1 A=4e-12 P=8e-6 -XM22_4 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT69 vss sub ptap1 A=4e-12 P=8e-6 -XM22_5 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT70 vss sub ptap1 A=4e-12 P=8e-6 -XM22_6 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT71 vss sub ptap1 A=4e-12 P=8e-6 -XM22_7 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT72 vss sub ptap1 A=4e-12 P=8e-6 -XM22_8 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT73 vss sub ptap1 A=4e-12 P=8e-6 -XM22_9 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT74 vss sub ptap1 A=4e-12 P=8e-6 -XM22_10 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT75 vss sub ptap1 A=4e-12 P=8e-6 -XM22_11 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT76 vss sub ptap1 A=4e-12 P=8e-6 -XM22_12 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT77 vss sub ptap1 A=4e-12 P=8e-6 -XM22_13 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT78 vss sub ptap1 A=4e-12 P=8e-6 -XM22_14 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT79 vss sub ptap1 A=4e-12 P=8e-6 -XM22_15 net094 net051 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT80 vss sub ptap1 A=4e-12 P=8e-6 -XM23_0 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT81 vss sub ptap1 A=4e-12 P=8e-6 -XM23_1 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT82 vss sub ptap1 A=4e-12 P=8e-6 -XM23_2 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT83 vss sub ptap1 A=4e-12 P=8e-6 -XM23_3 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT84 vss sub ptap1 A=4e-12 P=8e-6 -XM23_4 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT85 vss sub ptap1 A=4e-12 P=8e-6 -XM23_5 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT86 vss sub ptap1 A=4e-12 P=8e-6 -XM23_6 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT87 vss sub ptap1 A=4e-12 P=8e-6 -XM23_7 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT88 vss sub ptap1 A=4e-12 P=8e-6 -XM23_8 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT89 vss sub ptap1 A=4e-12 P=8e-6 -XM23_9 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT90 vss sub ptap1 A=4e-12 P=8e-6 -XM23_10 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT91 vss sub ptap1 A=4e-12 P=8e-6 -XM23_11 net057 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT92 vss sub ptap1 A=4e-12 P=8e-6 -XM24_0 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT93 vss sub ptap1 A=4e-12 P=8e-6 -XM24_1 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT94 vss sub ptap1 A=4e-12 P=8e-6 -XM24_2 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT95 vss sub ptap1 A=4e-12 P=8e-6 -XM24_3 net049 net057 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT96 vdd well_96 ntap1 A=4e-12 P=8e-6 -XM3_0 net078 vb1 vdd well_96 sg13_lv_pmos w=1u l=1u m=1 -XT97 vdd well_97 ntap1 A=4e-12 P=8e-6 -XM3_1 net078 vb1 vdd well_97 sg13_lv_pmos w=1u l=1u m=1 -XT98 vdd well_98 ntap1 A=4e-12 P=8e-6 -XM3_2 net078 vb1 vdd well_98 sg13_lv_pmos w=1u l=1u m=1 -XT99 vdd well_99 ntap1 A=4e-12 P=8e-6 -XM3_3 net078 vb1 vdd well_99 sg13_lv_pmos w=1u l=1u m=1 -XT100 vdd well_100 ntap1 A=4e-12 P=8e-6 -XM3_4 net078 vb1 vdd well_100 sg13_lv_pmos w=1u l=1u m=1 -XT101 vdd well_101 ntap1 A=4e-12 P=8e-6 -XM3_5 net078 vb1 vdd well_101 sg13_lv_pmos w=1u l=1u m=1 -XT102 vdd well_102 ntap1 A=4e-12 P=8e-6 -XM3_6 net078 vb1 vdd well_102 sg13_lv_pmos w=1u l=1u m=1 -XT103 vdd well_103 ntap1 A=4e-12 P=8e-6 -XM3_7 net078 vb1 vdd well_103 sg13_lv_pmos w=1u l=1u m=1 -XT104 vdd well_104 ntap1 A=4e-12 P=8e-6 -XM3_8 net078 vb1 vdd well_104 sg13_lv_pmos w=1u l=1u m=1 -XT105 vdd well_105 ntap1 A=4e-12 P=8e-6 -XM3_9 net078 vb1 vdd well_105 sg13_lv_pmos w=1u l=1u m=1 -XT106 vdd well_106 ntap1 A=4e-12 P=8e-6 -XM3_10 net078 vb1 vdd well_106 sg13_lv_pmos w=1u l=1u m=1 -XT107 vdd well_107 ntap1 A=4e-12 P=8e-6 -XM3_11 net078 vb1 vdd well_107 sg13_lv_pmos w=1u l=1u m=1 -XT108 vdd well_108 ntap1 A=4e-12 P=8e-6 -XM3_12 net078 vb1 vdd well_108 sg13_lv_pmos w=1u l=1u m=1 -XT109 vdd well_109 ntap1 A=4e-12 P=8e-6 -XM3_13 net078 vb1 vdd well_109 sg13_lv_pmos w=1u l=1u m=1 -XT110 vdd well_110 ntap1 A=4e-12 P=8e-6 -XM3_14 net078 vb1 vdd well_110 sg13_lv_pmos w=1u l=1u m=1 -XT111 vdd well_111 ntap1 A=4e-12 P=8e-6 -XM3_15 net078 vb1 vdd well_111 sg13_lv_pmos w=1u l=1u m=1 -XT112 vdd well_112 ntap1 A=4e-12 P=8e-6 -XM3_16 net078 vb1 vdd well_112 sg13_lv_pmos w=1u l=1u m=1 -XT113 vdd well_113 ntap1 A=4e-12 P=8e-6 -XM3_17 net078 vb1 vdd well_113 sg13_lv_pmos w=1u l=1u m=1 -XT114 vdd well_114 ntap1 A=4e-12 P=8e-6 -XM3_18 net078 vb1 vdd well_114 sg13_lv_pmos w=1u l=1u m=1 -XT115 vdd well_115 ntap1 A=4e-12 P=8e-6 -XM3_19 net078 vb1 vdd well_115 sg13_lv_pmos w=1u l=1u m=1 -XT116 vdd well_116 ntap1 A=4e-12 P=8e-6 -XM3_20 net078 vb1 vdd well_116 sg13_lv_pmos w=1u l=1u m=1 -XT117 vdd well_117 ntap1 A=4e-12 P=8e-6 -XM3_21 net078 vb1 vdd well_117 sg13_lv_pmos w=1u l=1u m=1 -XT118 vdd well_118 ntap1 A=4e-12 P=8e-6 -XM3_22 net078 vb1 vdd well_118 sg13_lv_pmos w=1u l=1u m=1 -XT119 vdd well_119 ntap1 A=4e-12 P=8e-6 -XM3_23 net078 vb1 vdd well_119 sg13_lv_pmos w=1u l=1u m=1 -XT120 vdd well_120 ntap1 A=4e-12 P=8e-6 -XM4_0 voutn voutn vdd well_120 sg13_lv_pmos w=1u l=1u m=1 -XT121 vdd well_121 ntap1 A=4e-12 P=8e-6 -XM4_1 voutn voutn vdd well_121 sg13_lv_pmos w=1u l=1u m=1 -XT122 vdd well_122 ntap1 A=4e-12 P=8e-6 -XM4_2 voutn voutn vdd well_122 sg13_lv_pmos w=1u l=1u m=1 -XT123 vdd well_123 ntap1 A=4e-12 P=8e-6 -XM4_3 voutn voutn vdd well_123 sg13_lv_pmos w=1u l=1u m=1 -XT124 vdd well_124 ntap1 A=4e-12 P=8e-6 -XM5_0 net050 voutn vdd well_124 sg13_lv_pmos w=1u l=1u m=1 -XT125 vdd well_125 ntap1 A=4e-12 P=8e-6 -XM5_1 net050 voutn vdd well_125 sg13_lv_pmos w=1u l=1u m=1 -XT126 vdd well_126 ntap1 A=4e-12 P=8e-6 -XM5_2 net050 voutn vdd well_126 sg13_lv_pmos w=1u l=1u m=1 -XT127 vdd well_127 ntap1 A=4e-12 P=8e-6 -XM5_3 net050 voutn vdd well_127 sg13_lv_pmos w=1u l=1u m=1 -XT128 vdd well_128 ntap1 A=4e-12 P=8e-6 -XM6_0 net055 net055 vdd well_128 sg13_lv_pmos w=1u l=1u m=1 -XT129 vdd well_129 ntap1 A=4e-12 P=8e-6 -XM6_1 net055 net055 vdd well_129 sg13_lv_pmos w=1u l=1u m=1 -XT130 vdd well_130 ntap1 A=4e-12 P=8e-6 -XM6_2 net055 net055 vdd well_130 sg13_lv_pmos w=1u l=1u m=1 -XT131 vdd well_131 ntap1 A=4e-12 P=8e-6 -XM6_3 net055 net055 vdd well_131 sg13_lv_pmos w=1u l=1u m=1 -XT132 vdd well_132 ntap1 A=4e-12 P=8e-6 -XM7_0 net057 net055 vdd well_132 sg13_lv_pmos w=1u l=1u m=1 -XT133 vdd well_133 ntap1 A=4e-12 P=8e-6 -XM7_1 net057 net055 vdd well_133 sg13_lv_pmos w=1u l=1u m=1 -XT134 vdd well_134 ntap1 A=4e-12 P=8e-6 -XM7_2 net057 net055 vdd well_134 sg13_lv_pmos w=1u l=1u m=1 -XT135 vdd well_135 ntap1 A=4e-12 P=8e-6 -XM7_3 net057 net055 vdd well_135 sg13_lv_pmos w=1u l=1u m=1 -XT136 vdd well_136 ntap1 A=4e-12 P=8e-6 -XM7_4 net057 net055 vdd well_136 sg13_lv_pmos w=1u l=1u m=1 -XT137 vdd well_137 ntap1 A=4e-12 P=8e-6 -XM7_5 net057 net055 vdd well_137 sg13_lv_pmos w=1u l=1u m=1 -XT138 vdd well_138 ntap1 A=4e-12 P=8e-6 -XM7_6 net057 net055 vdd well_138 sg13_lv_pmos w=1u l=1u m=1 -XT139 vdd well_139 ntap1 A=4e-12 P=8e-6 -XM7_7 net057 net055 vdd well_139 sg13_lv_pmos w=1u l=1u m=1 -XT140 vdd well_140 ntap1 A=4e-12 P=8e-6 -XM8_0 net049 vb1 vdd well_140 sg13_lv_pmos w=1u l=1u m=1 -XT141 vdd well_141 ntap1 A=4e-12 P=8e-6 -XM8_1 net049 vb1 vdd well_141 sg13_lv_pmos w=1u l=1u m=1 -XT142 vdd well_142 ntap1 A=4e-12 P=8e-6 -XM8_2 net049 vb1 vdd well_142 sg13_lv_pmos w=1u l=1u m=1 -XT143 vdd well_143 ntap1 A=4e-12 P=8e-6 -XM8_3 net049 vb1 vdd well_143 sg13_lv_pmos w=1u l=1u m=1 -XT144 vdd well_144 ntap1 A=4e-12 P=8e-6 -XM8_4 net049 vb1 vdd well_144 sg13_lv_pmos w=1u l=1u m=1 -XT145 vdd well_145 ntap1 A=4e-12 P=8e-6 -XM8_5 net049 vb1 vdd well_145 sg13_lv_pmos w=1u l=1u m=1 -XT146 vdd well_146 ntap1 A=4e-12 P=8e-6 -XM8_6 net049 vb1 vdd well_146 sg13_lv_pmos w=1u l=1u m=1 -XT147 vdd well_147 ntap1 A=4e-12 P=8e-6 -XM8_7 net049 vb1 vdd well_147 sg13_lv_pmos w=1u l=1u m=1 -XT148 net019 well_148 ntap1 A=4e-12 P=8e-6 -XM9_0 dm_2 vinn net019 well_148 sg13_lv_pmos w=1u l=1u m=1 -XT149 net019 well_149 ntap1 A=4e-12 P=8e-6 -XM9_1 dm_2 vinn net019 well_149 sg13_lv_pmos w=1u l=1u m=1 -XT150 net019 well_150 ntap1 A=4e-12 P=8e-6 -XM9_2 dm_2 vinn net019 well_150 sg13_lv_pmos w=1u l=1u m=1 -XT151 net019 well_151 ntap1 A=4e-12 P=8e-6 -XM9_3 dm_2 vinn net019 well_151 sg13_lv_pmos w=1u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM0 vb1 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM1 vb4 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM10 net063 vinp net019 net019 sg13_lv_pmos w=1u l=1u m=4 +XM11 net094 net050 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM12 net055 net094 vss vss sg13_lv_nmos w=1u l=1u m=4 +XM13 vout net050 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM14 voutn net077 dm_2 vss sg13_lv_nmos w=1u l=1u m=4 +XM15 net050 net082 net063 vss sg13_lv_nmos w=1u l=1u m=4 +XM16 net077 dm_2 vss vss sg13_lv_nmos w=1u l=1u m=4 +XM17 net082 net063 vss vss sg13_lv_nmos w=1u l=1u m=4 +XM18 vout net049 vss vss sg13_lv_nmos w=1u l=1u m=4 +XM19 vb4 vb4 vss vss sg13_lv_nmos w=2u l=1u m=4 +XM2 net019 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +XM20 dm_2 vb4 vss vss sg13_lv_nmos w=7u l=1u m=4 +XM21 net063 vb4 vss vss sg13_lv_nmos w=7u l=1u m=4 +XM22 net094 net051 vss vss sg13_lv_nmos w=1u l=1u m=16 +XM23 net057 net043 vss vss sg13_lv_nmos w=1u l=1u m=12 +XM24 net049 net057 vss vss sg13_lv_nmos w=1u l=1u m=4 +XM3 net078 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=24 +XM4 voutn voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM5 net050 voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM6 net055 net055 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +XM7 net057 net055 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +XM8 net049 vb1 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +XM9 dm_2 vinn net019 net019 sg13_lv_pmos w=1u l=1u m=4 XC0_0 net063 vout cap_cmim w=23.18u l=23.18u m=1 XC1_0 net051 vss cap_cmim w=16.36u l=16.36u m=1 XC2_0 net043 vss cap_cmim w=14.32u l=14.32u m=1 -XR0_0 net078 net077 sub rhigh w=.5u l=11.73u m=1 b=0 -XR1_0 net078 net082 sub rhigh w=.5u l=11.73u m=1 b=0 -XR2_0 net057 R2_s1 sub rhigh w=.5u l=59.08u m=1 b=0 -XR2_1 R2_s1 net051 sub rhigh w=.5u l=59.08u m=1 b=0 -XR3_0 net057 net043 sub rhigh w=.5u l=13.42u m=1 b=0 +XR0_0 net078 net077 vss rhigh w=.5u l=11.73u m=1 b=0 +XR1_0 net078 net082 vss rhigh w=.5u l=11.73u m=1 b=0 +XR2_0 net057 R2_s1 vss rhigh w=.5u l=59.08u m=1 b=0 +XR2_1 R2_s1 net051 vss rhigh w=.5u l=59.08u m=1 b=0 +XR3_0 net057 net043 vss rhigh w=.5u l=13.42u m=1 b=0 .ends amp_013_qu2017_azc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/schematic.svg deleted file mode 100644 index ef7d128393aed82d40202a045ac71ff10af81f64..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_013_qu2017_azc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_013_qu2017_azc","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_013_qu2017_azc","MM0_bank1","MM1_bank2","MM10_bank3","MM11_bank4","MM12_bank5","MM13_bank6","MM14_bank7","MM15_bank8","MM16_bank9","MM17_bank10","MM18_bank11","MM19_bank12","MM2_bank13","MM20_bank14","MM21_bank15","MM22_bank16","MM23_bank17","MM24_bank18","MM3_bank19","MM4_bank20","MM5_bank21","MM6_bank22","MM7_bank23","MM8_bank24","MM9_bank25","XRT16_bank26_devices_0001-0069","XRT16_bank26"],"banks":[{"name":"MM0_bank1","devices":8,"source_references":["RT0","MM0_0","RT1","MM0_1","RT2","MM0_2","RT3","MM0_3"]},{"name":"MM1_bank2","devices":8,"source_references":["RT4","MM1_0","RT5","MM1_1","RT6","MM1_2","RT7","MM1_3"]},{"name":"MM10_bank3","devices":8,"source_references":["RT8","MM10_0","RT9","MM10_1","RT10","MM10_2","RT11","MM10_3"]},{"name":"MM11_bank4","devices":8,"source_references":["RT12","MM11_0","RT13","MM11_1","RT14","MM11_2","RT15","MM11_3"]},{"name":"MM12_bank5","devices":4,"source_references":["MM12_0","MM12_1","MM12_2","MM12_3"]},{"name":"MM13_bank6","devices":8,"source_references":["RT20","MM13_0","RT21","MM13_1","RT22","MM13_2","RT23","MM13_3"]},{"name":"MM14_bank7","devices":4,"source_references":["MM14_0","MM14_1","MM14_2","MM14_3"]},{"name":"MM15_bank8","devices":4,"source_references":["MM15_0","MM15_1","MM15_2","MM15_3"]},{"name":"MM16_bank9","devices":4,"source_references":["MM16_0","MM16_1","MM16_2","MM16_3"]},{"name":"MM17_bank10","devices":4,"source_references":["MM17_0","MM17_1","MM17_2","MM17_3"]},{"name":"MM18_bank11","devices":4,"source_references":["MM18_0","MM18_1","MM18_2","MM18_3"]},{"name":"MM19_bank12","devices":4,"source_references":["MM19_0","MM19_1","MM19_2","MM19_3"]},{"name":"MM2_bank13","devices":16,"source_references":["RT48","MM2_0","RT49","MM2_1","RT50","MM2_2","RT51","MM2_3","RT52","MM2_4","RT53","MM2_5","RT54","MM2_6","RT55","MM2_7"]},{"name":"MM20_bank14","devices":4,"source_references":["MM20_0","MM20_1","MM20_2","MM20_3"]},{"name":"MM21_bank15","devices":4,"source_references":["MM21_0","MM21_1","MM21_2","MM21_3"]},{"name":"MM22_bank16","devices":16,"source_references":["MM22_0","MM22_1","MM22_2","MM22_3","MM22_4","MM22_5","MM22_6","MM22_7","MM22_8","MM22_9","MM22_10","MM22_11","MM22_12","MM22_13","MM22_14","MM22_15"]},{"name":"MM23_bank17","devices":12,"source_references":["MM23_0","MM23_1","MM23_2","MM23_3","MM23_4","MM23_5","MM23_6","MM23_7","MM23_8","MM23_9","MM23_10","MM23_11"]},{"name":"MM24_bank18","devices":4,"source_references":["MM24_0","MM24_1","MM24_2","MM24_3"]},{"name":"MM3_bank19","devices":48,"source_references":["RT96","MM3_0","RT97","MM3_1","RT98","MM3_2","RT99","MM3_3","RT100","MM3_4","RT101","MM3_5","RT102","MM3_6","RT103","MM3_7","RT104","MM3_8","RT105","MM3_9","RT106","MM3_10","RT107","MM3_11","RT108","MM3_12","RT109","MM3_13","RT110","MM3_14","RT111","MM3_15","RT112","MM3_16","RT113","MM3_17","RT114","MM3_18","RT115","MM3_19","RT116","MM3_20","RT117","MM3_21","RT118","MM3_22","RT119","MM3_23"]},{"name":"MM4_bank20","devices":8,"source_references":["RT120","MM4_0","RT121","MM4_1","RT122","MM4_2","RT123","MM4_3"]},{"name":"MM5_bank21","devices":8,"source_references":["RT124","MM5_0","RT125","MM5_1","RT126","MM5_2","RT127","MM5_3"]},{"name":"MM6_bank22","devices":8,"source_references":["RT128","MM6_0","RT129","MM6_1","RT130","MM6_2","RT131","MM6_3"]},{"name":"MM7_bank23","devices":16,"source_references":["RT132","MM7_0","RT133","MM7_1","RT134","MM7_2","RT135","MM7_3","RT136","MM7_4","RT137","MM7_5","RT138","MM7_6","RT139","MM7_7"]},{"name":"MM8_bank24","devices":16,"source_references":["RT140","MM8_0","RT141","MM8_1","RT142","MM8_2","RT143","MM8_3","RT144","MM8_4","RT145","MM8_5","RT146","MM8_6","RT147","MM8_7"]},{"name":"MM9_bank25","devices":8,"source_references":["RT148","MM9_0","RT149","MM9_1","RT150","MM9_2","RT151","MM9_3"]},{"name":"XRT16_bank26","devices":69,"source_references":["RT16","RT17","RT18","RT19","RT24","RT25","RT26","RT27","RT28","RT29","RT30","RT31","RT32","RT33","RT34","RT35","RT36","RT37","RT38","RT39","RT40","RT41","RT42","RT43","RT44","RT45","RT46","RT47","RT56","RT57","RT58","RT59","RT60","RT61","RT62","RT63","RT64","RT65","RT66","RT67","RT68","RT69","RT70","RT71","RT72","RT73","RT74","RT75","RT76","RT77","RT78","RT79","RT80","RT81","RT82","RT83","RT84","RT85","RT86","RT87","RT88","RT89","RT90","RT91","RT92","RT93","RT94","RT95","RTSUB"]}],"limitations":["The main sheet follows the circuit stages; repeated net names identify matching terminals within each sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Repeated source devices remain individually represented. Large banks use contiguous source-order detail ranges only where needed for responsive editing."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":5},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_013_qu2017_azc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/design/amp_013_qu2017_azc.icproj.json"}}Main-sheet overview; 27 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_013_qu2017_azcvddvb1vb4vddvb1net049vddvb1net078vssnet063subnet082vddvb1vddvoutnvsssubnet049net057vddnet055net057vssvb4subdm_2net063net050subnet082vddnet094net050vinpnet019net063vsssubvddvb1net019vssvoutsubnet049vddvoutnet050vddnet055vssnet094subnet055vsssubnet057net043vssvb4subvssvb4net063subvinnnet019dm_2vssnet094subnet051vddnet050voutnvsssubnet077dm_2subvoutnnet077dm_2vddvinnvinpvoutvoutvb1net063vssnet077net082net051net051net057net057net043net043net078net078R2_s1R2_s1vssvssamp_013_qu2017_azcXMM0_bank1XMM1_bank2XMM10_bank3XMM11_bank4XMM12_bank5XMM13_bank6XMM14_bank7XMM15_bank8XMM16_bank9XMM17_bank10XMM18_bank11XMM19_bank12XMM2_bank13XMM20_bank14XMM21_bank15XMM22_bank16XMM23_bank17XMM24_bank18XMM3_bank19XMM4_bank20XMM5_bank21XMM6_bank22XMM7_bank23XMM8_bank24XMM9_bank25XXRT16_bank26XC0_0 · cap_cmimXC1_0 · cap_cmimXC2_0 · cap_cmimXRR0_0 · rhighXRR1_0 · rhighXRR2_0 · rhighXRR2_1 · rhighXRR3_0 · rhigh - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md index f827ed78c01f4cfb197aa065618de8fc934a101f..f60784a6f73269d10659f386de1cea60c288163e 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md @@ -8,7 +8,7 @@ Implement `amp_013_qu2017_azc` without changing the declared circuit. XM9/XM10 f `materials/circuit.cdl` is the authoritative physical circuit and `materials/circuit.spice` its equivalent simulation representation; `materials/testbench.spice` and `materials/ac.spice` define transient/closed-loop AC and balanced open-loop AC, respectively. This statement is the description input. Ordered interface is `vss vdd vinn vinp vout vb1`: `vss`/`vdd` are supply rails; all other signals, bias/reference and unloaded monitor ports retain netlist connections. Independent bias sources and loads remain outside the physical core. -The integer-micrometre MOS dimensions are unchanged. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. +The integer-micrometre MOS dimensions are unchanged. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source and extraction use logical body nets. Native LVS checks actual body-contact connectivity. Distributed substrate behavior is outside this model boundary. ## Operating Conditions @@ -89,3 +89,5 @@ Finite-window amplifier response: tracking error 36%, ripple 22.5%, AC transfer Solve budget: **8 hours**. Use the reviewed SG13G2 resources and ngspice 45 environment. Frozen inputs, requirements and tool bindings are in `/protocol/task.json`. Explicitly submit `/workspace/output/final.gds` through the session submission tool; file generation alone is not submission. Evaluation performs native checks, candidate RC extraction and independent paired source/post-layout simulation. Reference GDS, maintainer README and development sources are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml index dd627212b21aa2ad286488a943ed204f4cf8c322..3375ff653d2427963e84f61fc9587a730bbef797 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 3 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "5f892f1bd3cdcf27688ca816a553fd32f10720ccc554b3a9ed53588417af253e" - [[assets]] path = "reference/amp_014_ramos_pfc.gds" role = "physical-witness" @@ -29,18 +22,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "a7e390d0e9b196a9b0d74aefc413469f95c4eb1f6492d4dfceb42645bc471409" +sha256 = "51280c40c14c6795feeb43175ecd2937c8b8abeb68727884552b046d2ce5fe60" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_014_ramos_pfc" -sha256 = "397c4c086e2c70372a03c3e1e0be1323519379a0f9ea38be34814434aff0122c" +sha256 = "e68e4f2e2edd7f40f8c8087573462ffe9bbaa53f3e47db84932e0880233677c1" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "d0555336f3073be55dcf967df72d86b9fbc3e56889c824083866f441296b6eba" +sha256 = "d914949e92bae3b144dea0fee043cdbea2caf84ac1d745d604287256d61aea23" [task.inputs.performance] path = "materials/testbench.spice" @@ -254,7 +247,7 @@ mode = "post_layout" method = "layout" area_metric = "functional_area" area_target = 70000.0 -rationale = "The 23 fixed MIM plates occupy 58539.3916 um2. A 70000 um2 integration budget allocates about 84% to those plates, leaving 11460.6084 um2 for enclosures, the expanded MOS array, taps and interconnect; it is not a minimum-area theorem. Area carries 35%, 100 ppm step-referred late accuracy 15%, the worst bilateral normalized response integral 20%, 10 kHz gain 15%, DC gain 10% and mean power 5%. The response integral removes each final plateau offset, so dynamic response and static accuracy are distinct. Repeated return offset, ripple and operating-point summaries remain diagnostic." +rationale = "The 23 fixed MIM plates occupy 58539.3916 um2. A 70000 um2 integration budget allocates about 84% to those plates, leaving 11460.6084 um2 for enclosures, MOS devices, body contacts and interconnect; it is not a minimum-area theorem. Area carries 35%, 100 ppm step-referred late accuracy 15%, the worst bilateral normalized response integral 20%, 10 kHz gain 15%, DC gain 10% and mean power 5%. The response integral removes each final plateau offset, so dynamic response and static accuracy are distinct. Repeated return offset, ripple and operating-point summaries remain diagnostic." [task.evaluation.scoring.weights] functional_area = 0.35 @@ -531,7 +524,7 @@ rationale = "The absolute error, voltage span, charge magnitude or recovery devi [task.evaluation.metrics.quality_target] value = 1e-05 -rationale = "Allocate 100 ppm of the declared 100 mV step, or 10 uV, to late-window deterministic tracking error. This is independent of the approximately 139 uV finite-tap source offset and makes no noise or mismatch claim." +rationale = "Allocate 100 ppm of the declared 100 mV step, or 10 uV, to late-window deterministic tracking error. This target makes no noise or mismatch claim." [[task.evaluation.metrics]] id = "return_error_v" @@ -713,17 +706,17 @@ scale = 1e-09 [task.evaluation.metrics.quality_target] value = 7.5e-08 -rationale = "A 75 ns normalized response-integral budget leaves about 5.6 ns for layout delay above the worst 69.4 ns source response to the 100 mV step at 10 pF. Static plateau error is scored independently; this is not a threshold-crossing settling time." +rationale = "A 75 ns normalized response-integral budget is an integration quality target for the declared 100 mV step at 10 pF; it is not a functional acceptance threshold. Static plateau error is scored independently; this is not a threshold-crossing settling time." [task.evaluation.metrics.requirement] lower = 0.0 rationale = "An integral of an absolute voltage deviation divided by a positive commanded step is nonnegative; slower responses remain valid and receive lower quality." [task.evaluation.pre_layout] -source_report_sha256 = "f468f678db202c4045c881981a16d91a40ff20c99b31efe8725ea313e4fb3104" +source_report_sha256 = "405ace1106a7c05bf2ebfbbb57f28acdd0f5471664e8dbbc7855d6f7db4886f3" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4256875a12feacdc7b1c992999ca2d58c01501a4bc6f5ac8e9a9fa379d26502b\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"c9894056a0f2ead5a621749eac89cea0f90d36093b04ac41c6642822b319032e\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5d384a76e9c131bac2ca2ea8519a17d0769e9ef6e93bd9cad97f6294738568db\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -765,14 +758,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "6dafd1581086352b90146a1231038dc3a965b02523c7824d4a9bdf369a9d0a34" -dut = "d0555336f3073be55dcf967df72d86b9fbc3e56889c824083866f441296b6eba" +dut = "d914949e92bae3b144dea0fee043cdbea2caf84ac1d745d604287256d61aea23" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 1.089958522988665 +value = 1.089958455717587 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = -0.000155305 +value = -0.0001553167 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] @@ -780,7 +773,7 @@ value = 0.4998609 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] -value = 0.0001391378 +value = 0.0001391171 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] @@ -788,43 +781,43 @@ value = 0.3998609 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.000622618 +value = 0.0006226162 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] -value = 0.5003946 +value = 0.5004822 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] -value = 0.3993451 +value = 0.3992587 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.3998609416891861 +value = 0.399860917948638 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0006226051526952075 +value = 0.0006226035534764181 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.response_down_s] -value = 6.91965e-08 +value = 6.90302e-08 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.response_up_s] -value = 6.93713e-08 +value = 6.918e-08 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 0.000139065 +value = 0.000139082 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] -value = 1.578036e-09 +value = 2.314624e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 2.743934e-09 +value = 4.930675e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1] @@ -853,22 +846,22 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "a9369ade66569d730d74f7a5061966effa5efc27829392e1dfa21cc73712f12f" -dut = "d0555336f3073be55dcf967df72d86b9fbc3e56889c824083866f441296b6eba" +dut = "d914949e92bae3b144dea0fee043cdbea2caf84ac1d745d604287256d61aea23" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] -value = 1.282307593442056e-14 +value = 2.331468351712829e-15 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] -value = 1.393976490420342e-09 +value = 1.394041239281952e-09 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] -value = 44.53335 +value = 44.53336 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] -value = 100.8461 +value = 100.8465 unit = "dB" [toolchain.bindings] @@ -910,7 +903,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl index 5a2edccb5b52ba0c45bcd74a7dbc34a9b4ca3073..ce9fcd241cbf17d8bf1d53626b2ca125bfd5fa95 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl @@ -1,5194 +1,30 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Pinned upstream MOS W/L/m and body nets; native MIM binding. .subckt amp_014_ramos_pfc vss vdd vinn vinp vout net1 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM0_0 net1 net1 vdd well_0 sg13_lv_pmos w=1u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM0_1 net1 net1 vdd well_1 sg13_lv_pmos w=1u l=1u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM0_2 net1 net1 vdd well_2 sg13_lv_pmos w=1u l=1u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM0_3 net1 net1 vdd well_3 sg13_lv_pmos w=1u l=1u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM0_4 net1 net1 vdd well_4 sg13_lv_pmos w=1u l=1u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM0_5 net1 net1 vdd well_5 sg13_lv_pmos w=1u l=1u m=1 -RT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -MM0_6 net1 net1 vdd well_6 sg13_lv_pmos w=1u l=1u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM0_7 net1 net1 vdd well_7 sg13_lv_pmos w=1u l=1u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM0_8 net1 net1 vdd well_8 sg13_lv_pmos w=1u l=1u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM0_9 net1 net1 vdd well_9 sg13_lv_pmos w=1u l=1u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM0_10 net1 net1 vdd well_10 sg13_lv_pmos w=1u l=1u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM0_11 net1 net1 vdd well_11 sg13_lv_pmos w=1u l=1u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM0_12 net1 net1 vdd well_12 sg13_lv_pmos w=1u l=1u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM0_13 net1 net1 vdd well_13 sg13_lv_pmos w=1u l=1u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM0_14 net1 net1 vdd well_14 sg13_lv_pmos w=1u l=1u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM0_15 net1 net1 vdd well_15 sg13_lv_pmos w=1u l=1u m=1 -RT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -MM0_16 net1 net1 vdd well_16 sg13_lv_pmos w=1u l=1u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM0_17 net1 net1 vdd well_17 sg13_lv_pmos w=1u l=1u m=1 -RT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -MM0_18 net1 net1 vdd well_18 sg13_lv_pmos w=1u l=1u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM0_19 net1 net1 vdd well_19 sg13_lv_pmos w=1u l=1u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM0_20 net1 net1 vdd well_20 sg13_lv_pmos w=1u l=1u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM0_21 net1 net1 vdd well_21 sg13_lv_pmos w=1u l=1u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM0_22 net1 net1 vdd well_22 sg13_lv_pmos w=1u l=1u m=1 -RT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -MM0_23 net1 net1 vdd well_23 sg13_lv_pmos w=1u l=1u m=1 -RT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -MM0_24 net1 net1 vdd well_24 sg13_lv_pmos w=1u l=1u m=1 -RT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -MM0_25 net1 net1 vdd well_25 sg13_lv_pmos w=1u l=1u m=1 -RT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -MM0_26 net1 net1 vdd well_26 sg13_lv_pmos w=1u l=1u m=1 -RT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -MM0_27 net1 net1 vdd well_27 sg13_lv_pmos w=1u l=1u m=1 -RT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -MM0_28 net1 net1 vdd well_28 sg13_lv_pmos w=1u l=1u m=1 -RT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -MM0_29 net1 net1 vdd well_29 sg13_lv_pmos w=1u l=1u m=1 -RT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -MM0_30 net1 net1 vdd well_30 sg13_lv_pmos w=1u l=1u m=1 -RT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -MM0_31 net1 net1 vdd well_31 sg13_lv_pmos w=1u l=1u m=1 -RT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -MM0_32 net1 net1 vdd well_32 sg13_lv_pmos w=1u l=1u m=1 -RT33 vdd well_33 ntap1 A=4e-12 P=8e-6 -MM0_33 net1 net1 vdd well_33 sg13_lv_pmos w=1u l=1u m=1 -RT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -MM0_34 net1 net1 vdd well_34 sg13_lv_pmos w=1u l=1u m=1 -RT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -MM0_35 net1 net1 vdd well_35 sg13_lv_pmos w=1u l=1u m=1 -RT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -MM0_36 net1 net1 vdd well_36 sg13_lv_pmos w=1u l=1u m=1 -RT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -MM0_37 net1 net1 vdd well_37 sg13_lv_pmos w=1u l=1u m=1 -RT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -MM0_38 net1 net1 vdd well_38 sg13_lv_pmos w=1u l=1u m=1 -RT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -MM0_39 net1 net1 vdd well_39 sg13_lv_pmos w=1u l=1u m=1 -RT40 vdd well_40 ntap1 A=4e-12 P=8e-6 -MM0_40 net1 net1 vdd well_40 sg13_lv_pmos w=1u l=1u m=1 -RT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -MM0_41 net1 net1 vdd well_41 sg13_lv_pmos w=1u l=1u m=1 -RT42 vdd well_42 ntap1 A=4e-12 P=8e-6 -MM0_42 net1 net1 vdd well_42 sg13_lv_pmos w=1u l=1u m=1 -RT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -MM0_43 net1 net1 vdd well_43 sg13_lv_pmos w=1u l=1u m=1 -RT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -MM0_44 net1 net1 vdd well_44 sg13_lv_pmos w=1u l=1u m=1 -RT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -MM0_45 net1 net1 vdd well_45 sg13_lv_pmos w=1u l=1u m=1 -RT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -MM0_46 net1 net1 vdd well_46 sg13_lv_pmos w=1u l=1u m=1 -RT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -MM0_47 net1 net1 vdd well_47 sg13_lv_pmos w=1u l=1u m=1 -RT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -MM0_48 net1 net1 vdd well_48 sg13_lv_pmos w=1u l=1u m=1 -RT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -MM0_49 net1 net1 vdd well_49 sg13_lv_pmos w=1u l=1u m=1 -RT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -MM0_50 net1 net1 vdd well_50 sg13_lv_pmos w=1u l=1u m=1 -RT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -MM0_51 net1 net1 vdd well_51 sg13_lv_pmos w=1u l=1u m=1 -RT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -MM0_52 net1 net1 vdd well_52 sg13_lv_pmos w=1u l=1u m=1 -RT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -MM0_53 net1 net1 vdd well_53 sg13_lv_pmos w=1u l=1u m=1 -RT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -MM0_54 net1 net1 vdd well_54 sg13_lv_pmos w=1u l=1u m=1 -RT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -MM0_55 net1 net1 vdd well_55 sg13_lv_pmos w=1u l=1u m=1 -RT56 vdd well_56 ntap1 A=4e-12 P=8e-6 -MM0_56 net1 net1 vdd well_56 sg13_lv_pmos w=1u l=1u m=1 -RT57 vdd well_57 ntap1 A=4e-12 P=8e-6 -MM0_57 net1 net1 vdd well_57 sg13_lv_pmos w=1u l=1u m=1 -RT58 vdd well_58 ntap1 A=4e-12 P=8e-6 -MM0_58 net1 net1 vdd well_58 sg13_lv_pmos w=1u l=1u m=1 -RT59 vdd well_59 ntap1 A=4e-12 P=8e-6 -MM0_59 net1 net1 vdd well_59 sg13_lv_pmos w=1u l=1u m=1 -RT60 vdd well_60 ntap1 A=4e-12 P=8e-6 -MM0_60 net1 net1 vdd well_60 sg13_lv_pmos w=1u l=1u m=1 -RT61 vdd well_61 ntap1 A=4e-12 P=8e-6 -MM0_61 net1 net1 vdd well_61 sg13_lv_pmos w=1u l=1u m=1 -RT62 vdd well_62 ntap1 A=4e-12 P=8e-6 -MM0_62 net1 net1 vdd well_62 sg13_lv_pmos w=1u l=1u m=1 -RT63 vdd well_63 ntap1 A=4e-12 P=8e-6 -MM0_63 net1 net1 vdd well_63 sg13_lv_pmos w=1u l=1u m=1 -RT64 vdd well_64 ntap1 A=4e-12 P=8e-6 -MM0_64 net1 net1 vdd well_64 sg13_lv_pmos w=1u l=1u m=1 -RT65 vdd well_65 ntap1 A=4e-12 P=8e-6 -MM0_65 net1 net1 vdd well_65 sg13_lv_pmos w=1u l=1u m=1 -RT66 vdd well_66 ntap1 A=4e-12 P=8e-6 -MM0_66 net1 net1 vdd well_66 sg13_lv_pmos w=1u l=1u m=1 -RT67 vdd well_67 ntap1 A=4e-12 P=8e-6 -MM0_67 net1 net1 vdd well_67 sg13_lv_pmos w=1u l=1u m=1 -RT68 vdd well_68 ntap1 A=4e-12 P=8e-6 -MM0_68 net1 net1 vdd well_68 sg13_lv_pmos w=1u l=1u m=1 -RT69 vdd well_69 ntap1 A=4e-12 P=8e-6 -MM0_69 net1 net1 vdd well_69 sg13_lv_pmos w=1u l=1u m=1 -RT70 vdd well_70 ntap1 A=4e-12 P=8e-6 -MM0_70 net1 net1 vdd well_70 sg13_lv_pmos w=1u l=1u m=1 -RT71 vdd well_71 ntap1 A=4e-12 P=8e-6 -MM1_0 vb4 net1 vdd well_71 sg13_lv_pmos w=1u l=1u m=1 -RT72 vdd well_72 ntap1 A=4e-12 P=8e-6 -MM1_1 vb4 net1 vdd well_72 sg13_lv_pmos w=1u l=1u m=1 -RT73 vdd well_73 ntap1 A=4e-12 P=8e-6 -MM1_2 vb4 net1 vdd well_73 sg13_lv_pmos w=1u l=1u m=1 -RT74 vdd well_74 ntap1 A=4e-12 P=8e-6 -MM1_3 vb4 net1 vdd well_74 sg13_lv_pmos w=1u l=1u m=1 -RT75 vdd well_75 ntap1 A=4e-12 P=8e-6 -MM1_4 vb4 net1 vdd well_75 sg13_lv_pmos w=1u l=1u m=1 -RT76 vdd well_76 ntap1 A=4e-12 P=8e-6 -MM1_5 vb4 net1 vdd well_76 sg13_lv_pmos w=1u l=1u m=1 -RT77 vdd well_77 ntap1 A=4e-12 P=8e-6 -MM1_6 vb4 net1 vdd well_77 sg13_lv_pmos w=1u l=1u m=1 -RT78 vdd well_78 ntap1 A=4e-12 P=8e-6 -MM1_7 vb4 net1 vdd well_78 sg13_lv_pmos w=1u l=1u m=1 -RT79 vdd well_79 ntap1 A=4e-12 P=8e-6 -MM1_8 vb4 net1 vdd well_79 sg13_lv_pmos w=1u l=1u m=1 -RT80 vdd well_80 ntap1 A=4e-12 P=8e-6 -MM1_9 vb4 net1 vdd well_80 sg13_lv_pmos w=1u l=1u m=1 -RT81 vdd well_81 ntap1 A=4e-12 P=8e-6 -MM1_10 vb4 net1 vdd well_81 sg13_lv_pmos w=1u l=1u m=1 -RT82 vdd well_82 ntap1 A=4e-12 P=8e-6 -MM1_11 vb4 net1 vdd well_82 sg13_lv_pmos w=1u l=1u m=1 -RT83 vdd well_83 ntap1 A=4e-12 P=8e-6 -MM1_12 vb4 net1 vdd well_83 sg13_lv_pmos w=1u l=1u m=1 -RT84 vdd well_84 ntap1 A=4e-12 P=8e-6 -MM1_13 vb4 net1 vdd well_84 sg13_lv_pmos w=1u l=1u m=1 -RT85 vdd well_85 ntap1 A=4e-12 P=8e-6 -MM1_14 vb4 net1 vdd well_85 sg13_lv_pmos w=1u l=1u m=1 -RT86 vdd well_86 ntap1 A=4e-12 P=8e-6 -MM1_15 vb4 net1 vdd well_86 sg13_lv_pmos w=1u l=1u m=1 -RT87 vdd well_87 ntap1 A=4e-12 P=8e-6 -MM1_16 vb4 net1 vdd well_87 sg13_lv_pmos w=1u l=1u m=1 -RT88 vdd well_88 ntap1 A=4e-12 P=8e-6 -MM1_17 vb4 net1 vdd well_88 sg13_lv_pmos w=1u l=1u m=1 -RT89 vdd well_89 ntap1 A=4e-12 P=8e-6 -MM1_18 vb4 net1 vdd well_89 sg13_lv_pmos w=1u l=1u m=1 -RT90 vdd well_90 ntap1 A=4e-12 P=8e-6 -MM1_19 vb4 net1 vdd well_90 sg13_lv_pmos w=1u l=1u m=1 -RT91 vdd well_91 ntap1 A=4e-12 P=8e-6 -MM1_20 vb4 net1 vdd well_91 sg13_lv_pmos w=1u l=1u m=1 -RT92 vdd well_92 ntap1 A=4e-12 P=8e-6 -MM1_21 vb4 net1 vdd well_92 sg13_lv_pmos w=1u l=1u m=1 -RT93 vdd well_93 ntap1 A=4e-12 P=8e-6 -MM1_22 vb4 net1 vdd well_93 sg13_lv_pmos w=1u l=1u m=1 -RT94 vdd well_94 ntap1 A=4e-12 P=8e-6 -MM1_23 vb4 net1 vdd well_94 sg13_lv_pmos w=1u l=1u m=1 -RT95 vdd well_95 ntap1 A=4e-12 P=8e-6 -MM1_24 vb4 net1 vdd well_95 sg13_lv_pmos w=1u l=1u m=1 -RT96 vdd well_96 ntap1 A=4e-12 P=8e-6 -MM1_25 vb4 net1 vdd well_96 sg13_lv_pmos w=1u l=1u m=1 -RT97 vdd well_97 ntap1 A=4e-12 P=8e-6 -MM1_26 vb4 net1 vdd well_97 sg13_lv_pmos w=1u l=1u m=1 -RT98 vdd well_98 ntap1 A=4e-12 P=8e-6 -MM1_27 vb4 net1 vdd well_98 sg13_lv_pmos w=1u l=1u m=1 -RT99 vdd well_99 ntap1 A=4e-12 P=8e-6 -MM1_28 vb4 net1 vdd well_99 sg13_lv_pmos w=1u l=1u m=1 -RT100 vdd well_100 ntap1 A=4e-12 P=8e-6 -MM1_29 vb4 net1 vdd well_100 sg13_lv_pmos w=1u l=1u m=1 -RT101 vdd well_101 ntap1 A=4e-12 P=8e-6 -MM1_30 vb4 net1 vdd well_101 sg13_lv_pmos w=1u l=1u m=1 -RT102 vdd well_102 ntap1 A=4e-12 P=8e-6 -MM1_31 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ntap1 A=4e-12 P=8e-6 -MM11_75 vout net050 vdd well_298 sg13_lv_pmos w=1u l=1u m=1 -RT299 vdd well_299 ntap1 A=4e-12 P=8e-6 -MM11_76 vout net050 vdd well_299 sg13_lv_pmos w=1u l=1u m=1 -RT300 vdd well_300 ntap1 A=4e-12 P=8e-6 -MM11_77 vout net050 vdd well_300 sg13_lv_pmos w=1u l=1u m=1 -RT301 vdd well_301 ntap1 A=4e-12 P=8e-6 -MM11_78 vout net050 vdd well_301 sg13_lv_pmos w=1u l=1u m=1 -RT302 vdd well_302 ntap1 A=4e-12 P=8e-6 -MM11_79 vout net050 vdd well_302 sg13_lv_pmos w=1u l=1u m=1 -RT303 vdd well_303 ntap1 A=4e-12 P=8e-6 -MM11_80 vout net050 vdd well_303 sg13_lv_pmos w=1u l=1u m=1 -RT304 vdd well_304 ntap1 A=4e-12 P=8e-6 -MM11_81 vout net050 vdd well_304 sg13_lv_pmos w=1u l=1u m=1 -RT305 vdd well_305 ntap1 A=4e-12 P=8e-6 -MM11_82 vout net050 vdd well_305 sg13_lv_pmos w=1u l=1u m=1 -RT306 vdd well_306 ntap1 A=4e-12 P=8e-6 -MM11_83 vout net050 vdd well_306 sg13_lv_pmos w=1u l=1u m=1 -RT307 vdd well_307 ntap1 A=4e-12 P=8e-6 -MM11_84 vout net050 vdd well_307 sg13_lv_pmos w=1u l=1u m=1 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l=1u m=1 -RT347 vdd well_347 ntap1 A=4e-12 P=8e-6 -MM11_124 vout net050 vdd well_347 sg13_lv_pmos w=1u l=1u m=1 -RT348 vdd well_348 ntap1 A=4e-12 P=8e-6 -MM11_125 vout net050 vdd well_348 sg13_lv_pmos w=1u l=1u m=1 -RT349 vdd well_349 ntap1 A=4e-12 P=8e-6 -MM11_126 vout net050 vdd well_349 sg13_lv_pmos w=1u l=1u m=1 -RT350 vdd well_350 ntap1 A=4e-12 P=8e-6 -MM11_127 vout net050 vdd well_350 sg13_lv_pmos w=1u l=1u m=1 -RT351 vdd well_351 ntap1 A=4e-12 P=8e-6 -MM11_128 vout net050 vdd well_351 sg13_lv_pmos w=1u l=1u m=1 -RT352 vdd well_352 ntap1 A=4e-12 P=8e-6 -MM11_129 vout net050 vdd well_352 sg13_lv_pmos w=1u l=1u m=1 -RT353 vdd well_353 ntap1 A=4e-12 P=8e-6 -MM11_130 vout net050 vdd well_353 sg13_lv_pmos w=1u l=1u m=1 -RT354 vdd well_354 ntap1 A=4e-12 P=8e-6 -MM11_131 vout net050 vdd well_354 sg13_lv_pmos w=1u l=1u m=1 -RT355 vdd well_355 ntap1 A=4e-12 P=8e-6 -MM11_132 vout net050 vdd well_355 sg13_lv_pmos w=1u l=1u m=1 -RT356 vdd well_356 ntap1 A=4e-12 P=8e-6 -MM11_133 vout net050 vdd well_356 sg13_lv_pmos w=1u l=1u m=1 -RT357 vdd well_357 ntap1 A=4e-12 P=8e-6 -MM11_134 vout net050 vdd well_357 sg13_lv_pmos w=1u l=1u m=1 -RT358 vdd well_358 ntap1 A=4e-12 P=8e-6 -MM11_135 vout net050 vdd well_358 sg13_lv_pmos w=1u l=1u m=1 -RT359 vdd well_359 ntap1 A=4e-12 P=8e-6 -MM11_136 vout net050 vdd well_359 sg13_lv_pmos w=1u l=1u m=1 -RT360 vdd well_360 ntap1 A=4e-12 P=8e-6 -MM11_137 vout net050 vdd well_360 sg13_lv_pmos w=1u l=1u m=1 -RT361 vdd well_361 ntap1 A=4e-12 P=8e-6 -MM11_138 vout net050 vdd well_361 sg13_lv_pmos w=1u l=1u m=1 -RT362 vdd well_362 ntap1 A=4e-12 P=8e-6 -MM11_139 vout net050 vdd well_362 sg13_lv_pmos w=1u l=1u m=1 -RT363 vdd well_363 ntap1 A=4e-12 P=8e-6 -MM11_140 vout net050 vdd well_363 sg13_lv_pmos w=1u l=1u m=1 -RT364 vdd well_364 ntap1 A=4e-12 P=8e-6 -MM11_141 vout net050 vdd well_364 sg13_lv_pmos w=1u l=1u m=1 -RT365 vdd well_365 ntap1 A=4e-12 P=8e-6 -MM11_142 vout net050 vdd well_365 sg13_lv_pmos w=1u l=1u m=1 -RT366 vdd well_366 ntap1 A=4e-12 P=8e-6 -MM11_143 vout net050 vdd well_366 sg13_lv_pmos w=1u l=1u m=1 -RT367 vdd well_367 ntap1 A=4e-12 P=8e-6 -MM11_144 vout net050 vdd well_367 sg13_lv_pmos w=1u l=1u m=1 -RT368 vdd well_368 ntap1 A=4e-12 P=8e-6 -MM11_145 vout net050 vdd well_368 sg13_lv_pmos w=1u l=1u m=1 -RT369 vdd well_369 ntap1 A=4e-12 P=8e-6 -MM11_146 vout net050 vdd well_369 sg13_lv_pmos w=1u l=1u m=1 -RT370 vdd well_370 ntap1 A=4e-12 P=8e-6 -MM11_147 vout net050 vdd well_370 sg13_lv_pmos w=1u l=1u m=1 -RT371 vdd well_371 ntap1 A=4e-12 P=8e-6 -MM11_148 vout net050 vdd well_371 sg13_lv_pmos w=1u l=1u m=1 -RT372 vdd well_372 ntap1 A=4e-12 P=8e-6 -MM11_149 vout net050 vdd well_372 sg13_lv_pmos w=1u l=1u m=1 -RT373 vdd well_373 ntap1 A=4e-12 P=8e-6 -MM11_150 vout net050 vdd well_373 sg13_lv_pmos w=1u l=1u m=1 -RT374 vdd well_374 ntap1 A=4e-12 P=8e-6 -MM11_151 vout net050 vdd well_374 sg13_lv_pmos w=1u l=1u m=1 -RT375 vdd well_375 ntap1 A=4e-12 P=8e-6 -MM11_152 vout net050 vdd well_375 sg13_lv_pmos w=1u l=1u m=1 -RT376 vdd well_376 ntap1 A=4e-12 P=8e-6 -MM11_153 vout net050 vdd well_376 sg13_lv_pmos w=1u l=1u m=1 -RT377 vdd well_377 ntap1 A=4e-12 P=8e-6 -MM11_154 vout net050 vdd well_377 sg13_lv_pmos w=1u l=1u m=1 -RT378 vdd well_378 ntap1 A=4e-12 P=8e-6 -MM11_155 vout net050 vdd well_378 sg13_lv_pmos w=1u l=1u m=1 -RT379 vdd well_379 ntap1 A=4e-12 P=8e-6 -MM11_156 vout net050 vdd well_379 sg13_lv_pmos w=1u l=1u m=1 -RT380 vdd well_380 ntap1 A=4e-12 P=8e-6 -MM11_157 vout net050 vdd well_380 sg13_lv_pmos w=1u l=1u m=1 -RT381 vdd well_381 ntap1 A=4e-12 P=8e-6 -MM11_158 vout net050 vdd well_381 sg13_lv_pmos w=1u l=1u m=1 -RT382 vdd well_382 ntap1 A=4e-12 P=8e-6 -MM11_159 vout net050 vdd well_382 sg13_lv_pmos w=1u l=1u m=1 -RT383 vdd well_383 ntap1 A=4e-12 P=8e-6 -MM11_160 vout net050 vdd well_383 sg13_lv_pmos w=1u l=1u m=1 -RT384 vdd well_384 ntap1 A=4e-12 P=8e-6 -MM11_161 vout net050 vdd well_384 sg13_lv_pmos w=1u l=1u m=1 -RT385 vdd well_385 ntap1 A=4e-12 P=8e-6 -MM11_162 vout net050 vdd well_385 sg13_lv_pmos w=1u l=1u m=1 -RT386 vdd well_386 ntap1 A=4e-12 P=8e-6 -MM11_163 vout net050 vdd well_386 sg13_lv_pmos w=1u l=1u m=1 -RT387 vdd well_387 ntap1 A=4e-12 P=8e-6 -MM11_164 vout net050 vdd well_387 sg13_lv_pmos w=1u l=1u m=1 -RT388 vdd well_388 ntap1 A=4e-12 P=8e-6 -MM11_165 vout net050 vdd well_388 sg13_lv_pmos w=1u l=1u m=1 -RT389 vdd well_389 ntap1 A=4e-12 P=8e-6 -MM11_166 vout net050 vdd well_389 sg13_lv_pmos w=1u l=1u m=1 -RT390 vdd well_390 ntap1 A=4e-12 P=8e-6 -MM11_167 vout net050 vdd well_390 sg13_lv_pmos w=1u l=1u m=1 -RT391 vdd well_391 ntap1 A=4e-12 P=8e-6 -MM11_168 vout net050 vdd well_391 sg13_lv_pmos w=1u l=1u m=1 -RT392 vdd well_392 ntap1 A=4e-12 P=8e-6 -MM11_169 vout net050 vdd well_392 sg13_lv_pmos w=1u l=1u m=1 -RT393 vdd well_393 ntap1 A=4e-12 P=8e-6 -MM11_170 vout net050 vdd well_393 sg13_lv_pmos w=1u l=1u m=1 -RT394 vdd well_394 ntap1 A=4e-12 P=8e-6 -MM11_171 vout net050 vdd well_394 sg13_lv_pmos w=1u l=1u m=1 -RT395 vdd well_395 ntap1 A=4e-12 P=8e-6 -MM11_172 vout net050 vdd well_395 sg13_lv_pmos w=1u l=1u m=1 -RT396 vdd well_396 ntap1 A=4e-12 P=8e-6 -MM11_173 vout net050 vdd well_396 sg13_lv_pmos w=1u l=1u m=1 -RT397 vdd well_397 ntap1 A=4e-12 P=8e-6 -MM11_174 vout net050 vdd well_397 sg13_lv_pmos w=1u l=1u m=1 -RT398 vdd well_398 ntap1 A=4e-12 P=8e-6 -MM11_175 vout net050 vdd well_398 sg13_lv_pmos w=1u l=1u m=1 -RT399 vdd well_399 ntap1 A=4e-12 P=8e-6 -MM11_176 vout net050 vdd well_399 sg13_lv_pmos w=1u l=1u m=1 -RT400 vdd well_400 ntap1 A=4e-12 P=8e-6 -MM11_177 vout net050 vdd well_400 sg13_lv_pmos w=1u l=1u m=1 -RT401 vdd well_401 ntap1 A=4e-12 P=8e-6 -MM11_178 vout net050 vdd well_401 sg13_lv_pmos w=1u l=1u m=1 -RT402 vdd well_402 ntap1 A=4e-12 P=8e-6 -MM11_179 vout net050 vdd well_402 sg13_lv_pmos w=1u l=1u m=1 -RT403 vdd well_403 ntap1 A=4e-12 P=8e-6 -MM11_180 vout net050 vdd well_403 sg13_lv_pmos w=1u l=1u m=1 -RT404 vdd well_404 ntap1 A=4e-12 P=8e-6 -MM11_181 vout net050 vdd well_404 sg13_lv_pmos w=1u l=1u m=1 -RT405 vdd well_405 ntap1 A=4e-12 P=8e-6 -MM11_182 vout net050 vdd well_405 sg13_lv_pmos w=1u l=1u m=1 -RT406 vdd well_406 ntap1 A=4e-12 P=8e-6 -MM11_183 vout net050 vdd well_406 sg13_lv_pmos w=1u l=1u m=1 -RT407 vdd well_407 ntap1 A=4e-12 P=8e-6 -MM11_184 vout net050 vdd well_407 sg13_lv_pmos w=1u l=1u m=1 -RT408 vdd well_408 ntap1 A=4e-12 P=8e-6 -MM11_185 vout net050 vdd well_408 sg13_lv_pmos w=1u l=1u m=1 -RT409 vdd well_409 ntap1 A=4e-12 P=8e-6 -MM11_186 vout net050 vdd well_409 sg13_lv_pmos w=1u l=1u m=1 -RT410 vdd well_410 ntap1 A=4e-12 P=8e-6 -MM11_187 vout net050 vdd well_410 sg13_lv_pmos w=1u l=1u m=1 -RT411 vdd well_411 ntap1 A=4e-12 P=8e-6 -MM11_188 vout net050 vdd well_411 sg13_lv_pmos w=1u l=1u m=1 -RT412 vdd well_412 ntap1 A=4e-12 P=8e-6 -MM11_189 vout net050 vdd well_412 sg13_lv_pmos w=1u l=1u m=1 -RT413 vdd well_413 ntap1 A=4e-12 P=8e-6 -MM11_190 vout net050 vdd well_413 sg13_lv_pmos w=1u l=1u m=1 -RT414 vdd well_414 ntap1 A=4e-12 P=8e-6 -MM11_191 vout net050 vdd well_414 sg13_lv_pmos w=1u l=1u m=1 -RT415 vdd well_415 ntap1 A=4e-12 P=8e-6 -MM11_192 vout net050 vdd well_415 sg13_lv_pmos w=1u l=1u m=1 -RT416 vdd well_416 ntap1 A=4e-12 P=8e-6 -MM11_193 vout net050 vdd well_416 sg13_lv_pmos w=1u l=1u m=1 -RT417 vdd well_417 ntap1 A=4e-12 P=8e-6 -MM11_194 vout net050 vdd well_417 sg13_lv_pmos w=1u l=1u m=1 -RT418 vdd well_418 ntap1 A=4e-12 P=8e-6 -MM11_195 vout net050 vdd well_418 sg13_lv_pmos w=1u l=1u m=1 -RT419 vdd well_419 ntap1 A=4e-12 P=8e-6 -MM11_196 vout net050 vdd well_419 sg13_lv_pmos w=1u l=1u m=1 -RT420 vdd well_420 ntap1 A=4e-12 P=8e-6 -MM11_197 vout net050 vdd well_420 sg13_lv_pmos w=1u l=1u m=1 -RT421 vdd well_421 ntap1 A=4e-12 P=8e-6 -MM11_198 vout net050 vdd well_421 sg13_lv_pmos w=1u l=1u m=1 -RT422 vdd well_422 ntap1 A=4e-12 P=8e-6 -MM11_199 vout net050 vdd well_422 sg13_lv_pmos w=1u l=1u m=1 -RT423 vdd well_423 ntap1 A=4e-12 P=8e-6 -MM11_200 vout net050 vdd well_423 sg13_lv_pmos w=1u l=1u m=1 -RT424 vdd well_424 ntap1 A=4e-12 P=8e-6 -MM11_201 vout net050 vdd well_424 sg13_lv_pmos w=1u l=1u m=1 -RT425 vdd well_425 ntap1 A=4e-12 P=8e-6 -MM11_202 vout net050 vdd well_425 sg13_lv_pmos w=1u l=1u m=1 -RT426 vdd well_426 ntap1 A=4e-12 P=8e-6 -MM11_203 vout net050 vdd well_426 sg13_lv_pmos w=1u l=1u m=1 -RT427 vdd well_427 ntap1 A=4e-12 P=8e-6 -MM11_204 vout net050 vdd well_427 sg13_lv_pmos w=1u l=1u m=1 -RT428 vdd well_428 ntap1 A=4e-12 P=8e-6 -MM11_205 vout net050 vdd well_428 sg13_lv_pmos w=1u l=1u m=1 -RT429 vdd well_429 ntap1 A=4e-12 P=8e-6 -MM11_206 vout net050 vdd well_429 sg13_lv_pmos w=1u l=1u m=1 -RT430 vdd well_430 ntap1 A=4e-12 P=8e-6 -MM11_207 vout net050 vdd well_430 sg13_lv_pmos w=1u l=1u m=1 -RT431 vdd well_431 ntap1 A=4e-12 P=8e-6 -MM11_208 vout net050 vdd well_431 sg13_lv_pmos w=1u l=1u m=1 -RT432 vdd well_432 ntap1 A=4e-12 P=8e-6 -MM11_209 vout net050 vdd well_432 sg13_lv_pmos w=1u l=1u m=1 -RT433 vdd well_433 ntap1 A=4e-12 P=8e-6 -MM11_210 vout net050 vdd well_433 sg13_lv_pmos w=1u l=1u m=1 -RT434 vdd well_434 ntap1 A=4e-12 P=8e-6 -MM11_211 vout net050 vdd well_434 sg13_lv_pmos w=1u l=1u m=1 -RT435 vdd well_435 ntap1 A=4e-12 P=8e-6 -MM11_212 vout net050 vdd well_435 sg13_lv_pmos w=1u l=1u m=1 -RT436 vdd well_436 ntap1 A=4e-12 P=8e-6 -MM11_213 vout net050 vdd well_436 sg13_lv_pmos w=1u l=1u m=1 -RT437 vdd well_437 ntap1 A=4e-12 P=8e-6 -MM11_214 vout net050 vdd well_437 sg13_lv_pmos w=1u l=1u m=1 -RT438 vdd well_438 ntap1 A=4e-12 P=8e-6 -MM11_215 vout net050 vdd well_438 sg13_lv_pmos w=1u l=1u m=1 -RT439 vdd well_439 ntap1 A=4e-12 P=8e-6 -MM11_216 vout net050 vdd well_439 sg13_lv_pmos w=1u l=1u m=1 -RT440 vdd well_440 ntap1 A=4e-12 P=8e-6 -MM11_217 vout net050 vdd well_440 sg13_lv_pmos w=1u l=1u m=1 -RT441 vdd well_441 ntap1 A=4e-12 P=8e-6 -MM11_218 vout net050 vdd well_441 sg13_lv_pmos w=1u l=1u m=1 -RT442 vdd well_442 ntap1 A=4e-12 P=8e-6 -MM11_219 vout net050 vdd well_442 sg13_lv_pmos w=1u l=1u m=1 -RT443 vdd well_443 ntap1 A=4e-12 P=8e-6 -MM11_220 vout net050 vdd well_443 sg13_lv_pmos w=1u l=1u m=1 -RT444 vdd well_444 ntap1 A=4e-12 P=8e-6 -MM11_221 vout net050 vdd well_444 sg13_lv_pmos w=1u l=1u m=1 -RT445 vdd well_445 ntap1 A=4e-12 P=8e-6 -MM11_222 vout net050 vdd well_445 sg13_lv_pmos w=1u l=1u m=1 -RT446 vdd well_446 ntap1 A=4e-12 P=8e-6 -MM11_223 vout net050 vdd well_446 sg13_lv_pmos w=1u l=1u m=1 -RT447 vdd well_447 ntap1 A=4e-12 P=8e-6 -MM11_224 vout net050 vdd well_447 sg13_lv_pmos w=1u l=1u m=1 -RT448 vdd well_448 ntap1 A=4e-12 P=8e-6 -MM11_225 vout net050 vdd well_448 sg13_lv_pmos w=1u l=1u m=1 -RT449 vdd well_449 ntap1 A=4e-12 P=8e-6 -MM11_226 vout net050 vdd well_449 sg13_lv_pmos w=1u l=1u m=1 -RT450 vdd well_450 ntap1 A=4e-12 P=8e-6 -MM11_227 vout net050 vdd well_450 sg13_lv_pmos w=1u l=1u m=1 -RT451 vdd well_451 ntap1 A=4e-12 P=8e-6 -MM11_228 vout net050 vdd well_451 sg13_lv_pmos w=1u l=1u m=1 -RT452 vdd well_452 ntap1 A=4e-12 P=8e-6 -MM11_229 vout net050 vdd well_452 sg13_lv_pmos w=1u l=1u m=1 -RT453 vdd well_453 ntap1 A=4e-12 P=8e-6 -MM11_230 vout net050 vdd well_453 sg13_lv_pmos w=1u l=1u m=1 -RT454 vdd well_454 ntap1 A=4e-12 P=8e-6 -MM11_231 vout net050 vdd well_454 sg13_lv_pmos w=1u l=1u m=1 -RT455 vdd well_455 ntap1 A=4e-12 P=8e-6 -MM11_232 vout net050 vdd well_455 sg13_lv_pmos w=1u l=1u m=1 -RT456 vdd well_456 ntap1 A=4e-12 P=8e-6 -MM11_233 vout net050 vdd well_456 sg13_lv_pmos w=1u l=1u m=1 -RT457 vdd well_457 ntap1 A=4e-12 P=8e-6 -MM11_234 vout net050 vdd well_457 sg13_lv_pmos w=1u l=1u m=1 -RT458 vdd well_458 ntap1 A=4e-12 P=8e-6 -MM11_235 vout net050 vdd well_458 sg13_lv_pmos w=1u l=1u m=1 -RT459 vdd well_459 ntap1 A=4e-12 P=8e-6 -MM11_236 vout net050 vdd well_459 sg13_lv_pmos w=1u l=1u m=1 -RT460 vdd well_460 ntap1 A=4e-12 P=8e-6 -MM11_237 vout net050 vdd well_460 sg13_lv_pmos w=1u l=1u m=1 -RT461 vdd well_461 ntap1 A=4e-12 P=8e-6 -MM11_238 vout net050 vdd well_461 sg13_lv_pmos w=1u l=1u m=1 -RT462 vdd well_462 ntap1 A=4e-12 P=8e-6 -MM11_239 vout net050 vdd well_462 sg13_lv_pmos w=1u l=1u m=1 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P=8e-6 -MM11_259 vout net050 vdd well_482 sg13_lv_pmos w=1u l=1u m=1 -RT483 vdd well_483 ntap1 A=4e-12 P=8e-6 -MM11_260 vout net050 vdd well_483 sg13_lv_pmos w=1u l=1u m=1 -RT484 vdd well_484 ntap1 A=4e-12 P=8e-6 -MM11_261 vout net050 vdd well_484 sg13_lv_pmos w=1u l=1u m=1 -RT485 vdd well_485 ntap1 A=4e-12 P=8e-6 -MM11_262 vout net050 vdd well_485 sg13_lv_pmos w=1u l=1u m=1 -RT486 vdd well_486 ntap1 A=4e-12 P=8e-6 -MM11_263 vout net050 vdd well_486 sg13_lv_pmos w=1u l=1u m=1 -RT487 vdd well_487 ntap1 A=4e-12 P=8e-6 -MM11_264 vout net050 vdd well_487 sg13_lv_pmos w=1u l=1u m=1 -RT488 vdd well_488 ntap1 A=4e-12 P=8e-6 -MM11_265 vout net050 vdd well_488 sg13_lv_pmos w=1u l=1u m=1 -RT489 vdd well_489 ntap1 A=4e-12 P=8e-6 -MM11_266 vout net050 vdd well_489 sg13_lv_pmos w=1u l=1u m=1 -RT490 vdd well_490 ntap1 A=4e-12 P=8e-6 -MM11_267 vout net050 vdd well_490 sg13_lv_pmos w=1u l=1u m=1 -RT491 vdd well_491 ntap1 A=4e-12 P=8e-6 -MM11_268 vout net050 vdd well_491 sg13_lv_pmos w=1u l=1u m=1 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well_559 sg13_lv_pmos w=1u l=1u m=1 -RT560 vdd well_560 ntap1 A=4e-12 P=8e-6 -MM11_337 vout net050 vdd well_560 sg13_lv_pmos w=1u l=1u m=1 -RT561 vdd well_561 ntap1 A=4e-12 P=8e-6 -MM11_338 vout net050 vdd well_561 sg13_lv_pmos w=1u l=1u m=1 -RT562 vdd well_562 ntap1 A=4e-12 P=8e-6 -MM11_339 vout net050 vdd well_562 sg13_lv_pmos w=1u l=1u m=1 -RT563 vdd well_563 ntap1 A=4e-12 P=8e-6 -MM11_340 vout net050 vdd well_563 sg13_lv_pmos w=1u l=1u m=1 -RT564 vdd well_564 ntap1 A=4e-12 P=8e-6 -MM11_341 vout net050 vdd well_564 sg13_lv_pmos w=1u l=1u m=1 -RT565 vdd well_565 ntap1 A=4e-12 P=8e-6 -MM11_342 vout net050 vdd well_565 sg13_lv_pmos w=1u l=1u m=1 -RT566 vdd well_566 ntap1 A=4e-12 P=8e-6 -MM11_343 vout net050 vdd well_566 sg13_lv_pmos w=1u l=1u m=1 -RT567 vdd well_567 ntap1 A=4e-12 P=8e-6 -MM11_344 vout net050 vdd well_567 sg13_lv_pmos w=1u l=1u m=1 -RT568 vdd well_568 ntap1 A=4e-12 P=8e-6 -MM11_345 vout net050 vdd well_568 sg13_lv_pmos w=1u l=1u m=1 -RT569 vdd well_569 ntap1 A=4e-12 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-RT579 vdd well_579 ntap1 A=4e-12 P=8e-6 -MM11_356 vout net050 vdd well_579 sg13_lv_pmos w=1u l=1u m=1 -RT580 vdd well_580 ntap1 A=4e-12 P=8e-6 -MM11_357 vout net050 vdd well_580 sg13_lv_pmos w=1u l=1u m=1 -RT581 vdd well_581 ntap1 A=4e-12 P=8e-6 -MM11_358 vout net050 vdd well_581 sg13_lv_pmos w=1u l=1u m=1 -RT582 vdd well_582 ntap1 A=4e-12 P=8e-6 -MM11_359 vout net050 vdd well_582 sg13_lv_pmos w=1u l=1u m=1 -RT583 vdd well_583 ntap1 A=4e-12 P=8e-6 -MM11_360 vout net050 vdd well_583 sg13_lv_pmos w=1u l=1u m=1 -RT584 vdd well_584 ntap1 A=4e-12 P=8e-6 -MM11_361 vout net050 vdd well_584 sg13_lv_pmos w=1u l=1u m=1 -RT585 vdd well_585 ntap1 A=4e-12 P=8e-6 -MM11_362 vout net050 vdd well_585 sg13_lv_pmos w=1u l=1u m=1 -RT586 vdd well_586 ntap1 A=4e-12 P=8e-6 -MM11_363 vout net050 vdd well_586 sg13_lv_pmos w=1u l=1u m=1 -RT587 vdd well_587 ntap1 A=4e-12 P=8e-6 -MM11_364 vout net050 vdd well_587 sg13_lv_pmos w=1u l=1u m=1 -RT588 vdd well_588 ntap1 A=4e-12 P=8e-6 -MM11_365 vout net050 vdd well_588 sg13_lv_pmos w=1u l=1u m=1 -RT589 vdd well_589 ntap1 A=4e-12 P=8e-6 -MM11_366 vout net050 vdd well_589 sg13_lv_pmos w=1u l=1u m=1 -RT590 vdd well_590 ntap1 A=4e-12 P=8e-6 -MM11_367 vout net050 vdd well_590 sg13_lv_pmos w=1u l=1u m=1 -RT591 vdd well_591 ntap1 A=4e-12 P=8e-6 -MM11_368 vout net050 vdd well_591 sg13_lv_pmos w=1u l=1u m=1 -RT592 vdd well_592 ntap1 A=4e-12 P=8e-6 -MM11_369 vout net050 vdd well_592 sg13_lv_pmos w=1u l=1u m=1 -RT593 vdd well_593 ntap1 A=4e-12 P=8e-6 -MM11_370 vout net050 vdd well_593 sg13_lv_pmos w=1u l=1u m=1 -RT594 vdd well_594 ntap1 A=4e-12 P=8e-6 -MM11_371 vout net050 vdd well_594 sg13_lv_pmos w=1u l=1u m=1 -RT595 vdd well_595 ntap1 A=4e-12 P=8e-6 -MM11_372 vout net050 vdd well_595 sg13_lv_pmos w=1u l=1u m=1 -RT596 vdd well_596 ntap1 A=4e-12 P=8e-6 -MM11_373 vout net050 vdd well_596 sg13_lv_pmos w=1u l=1u m=1 -RT597 vdd well_597 ntap1 A=4e-12 P=8e-6 -MM11_374 vout net050 vdd well_597 sg13_lv_pmos w=1u l=1u m=1 -RT598 vdd well_598 ntap1 A=4e-12 P=8e-6 -MM11_375 vout net050 vdd well_598 sg13_lv_pmos w=1u l=1u m=1 -RT599 vdd well_599 ntap1 A=4e-12 P=8e-6 -MM11_376 vout net050 vdd well_599 sg13_lv_pmos w=1u l=1u m=1 -RT600 vdd well_600 ntap1 A=4e-12 P=8e-6 -MM11_377 vout net050 vdd well_600 sg13_lv_pmos w=1u l=1u m=1 -RT601 vdd well_601 ntap1 A=4e-12 P=8e-6 -MM11_378 vout net050 vdd well_601 sg13_lv_pmos w=1u l=1u m=1 -RT602 vdd well_602 ntap1 A=4e-12 P=8e-6 -MM11_379 vout net050 vdd well_602 sg13_lv_pmos w=1u l=1u m=1 -RT603 vdd well_603 ntap1 A=4e-12 P=8e-6 -MM11_380 vout net050 vdd well_603 sg13_lv_pmos w=1u l=1u m=1 -RT604 vdd well_604 ntap1 A=4e-12 P=8e-6 -MM11_381 vout net050 vdd well_604 sg13_lv_pmos w=1u l=1u m=1 -RT605 vdd well_605 ntap1 A=4e-12 P=8e-6 -MM11_382 vout net050 vdd well_605 sg13_lv_pmos w=1u l=1u m=1 -RT606 vdd well_606 ntap1 A=4e-12 P=8e-6 -MM11_383 vout net050 vdd well_606 sg13_lv_pmos w=1u l=1u m=1 -RT607 vdd well_607 ntap1 A=4e-12 P=8e-6 -MM11_384 vout net050 vdd well_607 sg13_lv_pmos w=1u l=1u m=1 -RT608 vdd well_608 ntap1 A=4e-12 P=8e-6 -MM11_385 vout net050 vdd well_608 sg13_lv_pmos w=1u l=1u m=1 -RT609 vdd well_609 ntap1 A=4e-12 P=8e-6 -MM11_386 vout net050 vdd well_609 sg13_lv_pmos w=1u l=1u m=1 -RT610 vdd well_610 ntap1 A=4e-12 P=8e-6 -MM11_387 vout net050 vdd well_610 sg13_lv_pmos w=1u l=1u m=1 -RT611 vdd well_611 ntap1 A=4e-12 P=8e-6 -MM11_388 vout net050 vdd well_611 sg13_lv_pmos w=1u l=1u m=1 -RT612 vdd well_612 ntap1 A=4e-12 P=8e-6 -MM11_389 vout net050 vdd well_612 sg13_lv_pmos w=1u l=1u m=1 -RT613 vdd well_613 ntap1 A=4e-12 P=8e-6 -MM11_390 vout net050 vdd well_613 sg13_lv_pmos w=1u l=1u m=1 -RT614 vdd well_614 ntap1 A=4e-12 P=8e-6 -MM11_391 vout net050 vdd well_614 sg13_lv_pmos w=1u l=1u m=1 -RT615 vdd well_615 ntap1 A=4e-12 P=8e-6 -MM11_392 vout net050 vdd well_615 sg13_lv_pmos w=1u l=1u m=1 -RT616 vdd well_616 ntap1 A=4e-12 P=8e-6 -MM11_393 vout net050 vdd well_616 sg13_lv_pmos w=1u l=1u m=1 -RT617 vdd well_617 ntap1 A=4e-12 P=8e-6 -MM11_394 vout net050 vdd well_617 sg13_lv_pmos w=1u l=1u m=1 -RT618 vdd well_618 ntap1 A=4e-12 P=8e-6 -MM11_395 vout net050 vdd well_618 sg13_lv_pmos w=1u l=1u m=1 -RT619 vdd well_619 ntap1 A=4e-12 P=8e-6 -MM11_396 vout net050 vdd well_619 sg13_lv_pmos w=1u l=1u m=1 -RT620 vdd well_620 ntap1 A=4e-12 P=8e-6 -MM11_397 vout net050 vdd well_620 sg13_lv_pmos w=1u l=1u m=1 -RT621 vdd well_621 ntap1 A=4e-12 P=8e-6 -MM11_398 vout net050 vdd well_621 sg13_lv_pmos w=1u l=1u m=1 -RT622 vdd well_622 ntap1 A=4e-12 P=8e-6 -MM11_399 vout net050 vdd well_622 sg13_lv_pmos w=1u l=1u m=1 -RT623 vss sub ptap1 A=4e-12 P=8e-6 -MM12_0 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT624 vss sub ptap1 A=4e-12 P=8e-6 -MM12_1 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT625 vss sub ptap1 A=4e-12 P=8e-6 -MM12_2 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT626 vss sub ptap1 A=4e-12 P=8e-6 -MM12_3 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT627 vss sub ptap1 A=4e-12 P=8e-6 -MM12_4 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT628 vss sub ptap1 A=4e-12 P=8e-6 -MM12_5 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT629 vss sub ptap1 A=4e-12 P=8e-6 -MM12_6 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT630 vss sub ptap1 A=4e-12 P=8e-6 -MM12_7 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT631 vss sub ptap1 A=4e-12 P=8e-6 -MM12_8 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT632 vss sub ptap1 A=4e-12 P=8e-6 -MM12_9 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT633 vss sub ptap1 A=4e-12 P=8e-6 -MM12_10 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT634 vss sub ptap1 A=4e-12 P=8e-6 -MM12_11 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT635 vss sub ptap1 A=4e-12 P=8e-6 -MM12_12 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT636 vss sub ptap1 A=4e-12 P=8e-6 -MM12_13 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT637 vss sub ptap1 A=4e-12 P=8e-6 -MM12_14 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT638 vss sub ptap1 A=4e-12 P=8e-6 -MM12_15 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT639 vss sub ptap1 A=4e-12 P=8e-6 -MM12_16 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT640 vss sub ptap1 A=4e-12 P=8e-6 -MM12_17 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT641 vss sub ptap1 A=4e-12 P=8e-6 -MM12_18 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT642 vss sub ptap1 A=4e-12 P=8e-6 -MM12_19 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT643 vss sub ptap1 A=4e-12 P=8e-6 -MM12_20 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT644 vss sub ptap1 A=4e-12 P=8e-6 -MM12_21 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT645 vss sub ptap1 A=4e-12 P=8e-6 -MM12_22 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT646 vss sub ptap1 A=4e-12 P=8e-6 -MM12_23 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT647 vss sub ptap1 A=4e-12 P=8e-6 -MM12_24 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT648 vss sub ptap1 A=4e-12 P=8e-6 -MM12_25 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT649 vss sub ptap1 A=4e-12 P=8e-6 -MM12_26 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT650 vss sub ptap1 A=4e-12 P=8e-6 -MM12_27 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT651 vss sub ptap1 A=4e-12 P=8e-6 -MM12_28 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT652 vss sub ptap1 A=4e-12 P=8e-6 -MM12_29 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT653 vss sub ptap1 A=4e-12 P=8e-6 -MM12_30 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT654 vss sub ptap1 A=4e-12 P=8e-6 -MM12_31 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT655 vss sub ptap1 A=4e-12 P=8e-6 -MM12_32 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT656 vss sub ptap1 A=4e-12 P=8e-6 -MM12_33 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT657 vss sub ptap1 A=4e-12 P=8e-6 -MM12_34 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT658 vss sub ptap1 A=4e-12 P=8e-6 -MM12_35 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT659 vss sub ptap1 A=4e-12 P=8e-6 -MM12_36 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT660 vss sub ptap1 A=4e-12 P=8e-6 -MM12_37 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT661 vss sub ptap1 A=4e-12 P=8e-6 -MM12_38 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT662 vss sub ptap1 A=4e-12 P=8e-6 -MM12_39 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT663 vss sub ptap1 A=4e-12 P=8e-6 -MM12_40 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT664 vss sub ptap1 A=4e-12 P=8e-6 -MM12_41 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT665 vss sub ptap1 A=4e-12 P=8e-6 -MM12_42 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT666 vss sub ptap1 A=4e-12 P=8e-6 -MM12_43 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT667 vss sub ptap1 A=4e-12 P=8e-6 -MM12_44 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT668 vss sub ptap1 A=4e-12 P=8e-6 -MM12_45 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT669 vss sub ptap1 A=4e-12 P=8e-6 -MM12_46 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT670 vss sub ptap1 A=4e-12 P=8e-6 -MM12_47 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT671 vss sub ptap1 A=4e-12 P=8e-6 -MM12_48 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT672 vss sub ptap1 A=4e-12 P=8e-6 -MM12_49 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT673 vss sub ptap1 A=4e-12 P=8e-6 -MM12_50 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT674 vss sub ptap1 A=4e-12 P=8e-6 -MM12_51 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT675 vss sub ptap1 A=4e-12 P=8e-6 -MM12_52 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT676 vss sub ptap1 A=4e-12 P=8e-6 -MM12_53 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT677 vss sub ptap1 A=4e-12 P=8e-6 -MM12_54 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT678 vss sub ptap1 A=4e-12 P=8e-6 -MM12_55 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT679 vss sub ptap1 A=4e-12 P=8e-6 -MM12_56 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT680 vss sub ptap1 A=4e-12 P=8e-6 -MM12_57 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT681 vss sub ptap1 A=4e-12 P=8e-6 -MM12_58 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT682 vss sub ptap1 A=4e-12 P=8e-6 -MM12_59 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT683 vss sub ptap1 A=4e-12 P=8e-6 -MM12_60 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT684 vss sub ptap1 A=4e-12 P=8e-6 -MM12_61 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT685 vss sub ptap1 A=4e-12 P=8e-6 -MM12_62 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT686 vss sub ptap1 A=4e-12 P=8e-6 -MM12_63 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT687 vss sub ptap1 A=4e-12 P=8e-6 -MM12_64 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT688 vss sub ptap1 A=4e-12 P=8e-6 -MM12_65 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT689 vss sub ptap1 A=4e-12 P=8e-6 -MM12_66 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT690 vss sub ptap1 A=4e-12 P=8e-6 -MM12_67 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT691 vss sub ptap1 A=4e-12 P=8e-6 -MM12_68 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT692 vss sub ptap1 A=4e-12 P=8e-6 -MM12_69 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT693 vss sub ptap1 A=4e-12 P=8e-6 -MM12_70 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT694 vss sub ptap1 A=4e-12 P=8e-6 -MM12_71 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT695 vss sub ptap1 A=4e-12 P=8e-6 -MM12_72 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT696 vss sub ptap1 A=4e-12 P=8e-6 -MM12_73 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT697 vss sub ptap1 A=4e-12 P=8e-6 -MM12_74 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT698 vss sub ptap1 A=4e-12 P=8e-6 -MM12_75 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT699 vss sub ptap1 A=4e-12 P=8e-6 -MM12_76 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT700 vss sub ptap1 A=4e-12 P=8e-6 -MM12_77 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT701 vss sub ptap1 A=4e-12 P=8e-6 -MM12_78 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT702 vss sub ptap1 A=4e-12 P=8e-6 -MM12_79 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT703 vss sub ptap1 A=4e-12 P=8e-6 -MM13_0 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT704 vss sub ptap1 A=4e-12 P=8e-6 -MM13_1 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT705 vss sub ptap1 A=4e-12 P=8e-6 -MM13_2 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT706 vss sub ptap1 A=4e-12 P=8e-6 -MM13_3 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT707 vss sub ptap1 A=4e-12 P=8e-6 -MM13_4 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT708 vss sub ptap1 A=4e-12 P=8e-6 -MM13_5 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT709 vss sub ptap1 A=4e-12 P=8e-6 -MM13_6 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT710 vss sub ptap1 A=4e-12 P=8e-6 -MM13_7 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT711 vss sub ptap1 A=4e-12 P=8e-6 -MM13_8 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT712 vss sub ptap1 A=4e-12 P=8e-6 -MM13_9 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT713 vss sub ptap1 A=4e-12 P=8e-6 -MM13_10 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT714 vss sub ptap1 A=4e-12 P=8e-6 -MM13_11 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT715 vss sub ptap1 A=4e-12 P=8e-6 -MM13_12 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT716 vss sub ptap1 A=4e-12 P=8e-6 -MM13_13 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT717 vss sub ptap1 A=4e-12 P=8e-6 -MM13_14 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT718 vss sub ptap1 A=4e-12 P=8e-6 -MM13_15 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT719 vss sub ptap1 A=4e-12 P=8e-6 -MM13_16 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT720 vss sub ptap1 A=4e-12 P=8e-6 -MM13_17 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT721 vss sub ptap1 A=4e-12 P=8e-6 -MM13_18 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT722 vss sub ptap1 A=4e-12 P=8e-6 -MM13_19 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT723 vss sub ptap1 A=4e-12 P=8e-6 -MM13_20 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT724 vss sub ptap1 A=4e-12 P=8e-6 -MM13_21 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT725 vss sub ptap1 A=4e-12 P=8e-6 -MM13_22 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT726 vss sub ptap1 A=4e-12 P=8e-6 -MM13_23 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT727 vss sub ptap1 A=4e-12 P=8e-6 -MM13_24 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT728 vss sub ptap1 A=4e-12 P=8e-6 -MM13_25 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT729 vss sub ptap1 A=4e-12 P=8e-6 -MM13_26 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT730 vss sub ptap1 A=4e-12 P=8e-6 -MM13_27 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT731 vss sub ptap1 A=4e-12 P=8e-6 -MM13_28 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT732 vss sub ptap1 A=4e-12 P=8e-6 -MM13_29 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT733 vss sub ptap1 A=4e-12 P=8e-6 -MM13_30 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT734 vss sub ptap1 A=4e-12 P=8e-6 -MM13_31 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT735 vss sub ptap1 A=4e-12 P=8e-6 -MM13_32 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT736 vss sub ptap1 A=4e-12 P=8e-6 -MM13_33 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT737 vss sub ptap1 A=4e-12 P=8e-6 -MM13_34 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT738 vss sub ptap1 A=4e-12 P=8e-6 -MM13_35 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT739 vss sub ptap1 A=4e-12 P=8e-6 -MM13_36 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT740 vss sub ptap1 A=4e-12 P=8e-6 -MM13_37 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT741 vss sub ptap1 A=4e-12 P=8e-6 -MM13_38 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT742 vss sub ptap1 A=4e-12 P=8e-6 -MM13_39 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT743 vss sub ptap1 A=4e-12 P=8e-6 -MM13_40 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT744 vss sub ptap1 A=4e-12 P=8e-6 -MM13_41 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT745 vss sub ptap1 A=4e-12 P=8e-6 -MM13_42 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT746 vss sub ptap1 A=4e-12 P=8e-6 -MM13_43 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT747 vss sub ptap1 A=4e-12 P=8e-6 -MM13_44 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT748 vss sub ptap1 A=4e-12 P=8e-6 -MM13_45 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT749 vss sub ptap1 A=4e-12 P=8e-6 -MM13_46 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT750 vss sub ptap1 A=4e-12 P=8e-6 -MM13_47 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT751 vss sub ptap1 A=4e-12 P=8e-6 -MM13_48 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT752 vss sub ptap1 A=4e-12 P=8e-6 -MM13_49 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT753 vss sub ptap1 A=4e-12 P=8e-6 -MM13_50 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT754 vss sub ptap1 A=4e-12 P=8e-6 -MM13_51 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT755 vss sub ptap1 A=4e-12 P=8e-6 -MM13_52 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT756 vss sub ptap1 A=4e-12 P=8e-6 -MM13_53 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT757 vss sub ptap1 A=4e-12 P=8e-6 -MM13_54 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT758 vss sub ptap1 A=4e-12 P=8e-6 -MM13_55 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT759 vss sub ptap1 A=4e-12 P=8e-6 -MM13_56 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT760 vss sub ptap1 A=4e-12 P=8e-6 -MM13_57 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT761 vss sub ptap1 A=4e-12 P=8e-6 -MM13_58 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT762 vss sub ptap1 A=4e-12 P=8e-6 -MM13_59 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT763 vss sub ptap1 A=4e-12 P=8e-6 -MM13_60 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT764 vss sub ptap1 A=4e-12 P=8e-6 -MM13_61 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT765 vss sub ptap1 A=4e-12 P=8e-6 -MM13_62 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT766 vss sub ptap1 A=4e-12 P=8e-6 -MM13_63 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT767 vss sub ptap1 A=4e-12 P=8e-6 -MM13_64 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT768 vss sub ptap1 A=4e-12 P=8e-6 -MM13_65 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT769 vss sub ptap1 A=4e-12 P=8e-6 -MM13_66 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT770 vss sub ptap1 A=4e-12 P=8e-6 -MM13_67 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT771 vss sub ptap1 A=4e-12 P=8e-6 -MM13_68 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT772 vss sub ptap1 A=4e-12 P=8e-6 -MM13_69 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT773 vss sub ptap1 A=4e-12 P=8e-6 -MM13_70 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT774 vss sub ptap1 A=4e-12 P=8e-6 -MM13_71 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT775 vss sub ptap1 A=4e-12 P=8e-6 -MM13_72 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT776 vss sub ptap1 A=4e-12 P=8e-6 -MM13_73 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT777 vss sub ptap1 A=4e-12 P=8e-6 -MM13_74 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT778 vss sub ptap1 A=4e-12 P=8e-6 -MM13_75 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT779 vss sub ptap1 A=4e-12 P=8e-6 -MM13_76 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT780 vss sub ptap1 A=4e-12 P=8e-6 -MM13_77 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT781 vss sub ptap1 A=4e-12 P=8e-6 -MM13_78 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT782 vss sub ptap1 A=4e-12 P=8e-6 -MM13_79 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT783 vss sub ptap1 A=4e-12 P=8e-6 -MM14_0 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT784 vss sub ptap1 A=4e-12 P=8e-6 -MM14_1 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT785 vss sub ptap1 A=4e-12 P=8e-6 -MM14_2 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT786 vss sub ptap1 A=4e-12 P=8e-6 -MM14_3 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT787 vss sub ptap1 A=4e-12 P=8e-6 -MM14_4 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT788 vss sub ptap1 A=4e-12 P=8e-6 -MM14_5 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT789 vss sub ptap1 A=4e-12 P=8e-6 -MM14_6 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT790 vss sub ptap1 A=4e-12 P=8e-6 -MM14_7 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT791 vss sub ptap1 A=4e-12 P=8e-6 -MM14_8 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT792 vss sub ptap1 A=4e-12 P=8e-6 -MM14_9 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT793 vss sub ptap1 A=4e-12 P=8e-6 -MM14_10 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT794 vss sub ptap1 A=4e-12 P=8e-6 -MM14_11 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT795 vss sub ptap1 A=4e-12 P=8e-6 -MM14_12 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT796 vss sub ptap1 A=4e-12 P=8e-6 -MM14_13 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT797 vss sub ptap1 A=4e-12 P=8e-6 -MM14_14 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT798 vss sub ptap1 A=4e-12 P=8e-6 -MM14_15 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT799 vss sub ptap1 A=4e-12 P=8e-6 -MM14_16 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT800 vss sub ptap1 A=4e-12 P=8e-6 -MM14_17 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT801 vss sub ptap1 A=4e-12 P=8e-6 -MM14_18 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT802 vss sub ptap1 A=4e-12 P=8e-6 -MM14_19 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT803 vss sub ptap1 A=4e-12 P=8e-6 -MM15_0 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT804 vss sub ptap1 A=4e-12 P=8e-6 -MM15_1 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT805 vss sub ptap1 A=4e-12 P=8e-6 -MM15_2 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT806 vss sub ptap1 A=4e-12 P=8e-6 -MM15_3 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT807 vss sub ptap1 A=4e-12 P=8e-6 -MM15_4 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT808 vss sub ptap1 A=4e-12 P=8e-6 -MM15_5 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT809 vss sub ptap1 A=4e-12 P=8e-6 -MM15_6 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT810 vss sub ptap1 A=4e-12 P=8e-6 -MM15_7 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT811 vss sub ptap1 A=4e-12 P=8e-6 -MM15_8 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT812 vss sub ptap1 A=4e-12 P=8e-6 -MM15_9 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT813 vss sub ptap1 A=4e-12 P=8e-6 -MM15_10 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT814 vss sub ptap1 A=4e-12 P=8e-6 -MM15_11 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT815 vss sub ptap1 A=4e-12 P=8e-6 -MM15_12 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT816 vss sub ptap1 A=4e-12 P=8e-6 -MM15_13 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT817 vss sub ptap1 A=4e-12 P=8e-6 -MM15_14 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT818 vss sub ptap1 A=4e-12 P=8e-6 -MM15_15 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT819 vss sub ptap1 A=4e-12 P=8e-6 -MM15_16 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT820 vss sub ptap1 A=4e-12 P=8e-6 -MM15_17 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT821 vss sub ptap1 A=4e-12 P=8e-6 -MM15_18 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT822 vss sub ptap1 A=4e-12 P=8e-6 -MM15_19 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT823 vss sub ptap1 A=4e-12 P=8e-6 -MM15_20 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT824 vss sub ptap1 A=4e-12 P=8e-6 -MM15_21 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT825 vss sub ptap1 A=4e-12 P=8e-6 -MM15_22 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT826 vss sub ptap1 A=4e-12 P=8e-6 -MM15_23 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT827 vss sub ptap1 A=4e-12 P=8e-6 -MM15_24 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT828 vss sub ptap1 A=4e-12 P=8e-6 -MM15_25 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT829 vss sub ptap1 A=4e-12 P=8e-6 -MM15_26 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT830 vss sub ptap1 A=4e-12 P=8e-6 -MM15_27 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT831 vss sub ptap1 A=4e-12 P=8e-6 -MM15_28 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT832 vss sub ptap1 A=4e-12 P=8e-6 -MM15_29 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT833 vss sub ptap1 A=4e-12 P=8e-6 -MM15_30 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT834 vss sub ptap1 A=4e-12 P=8e-6 -MM15_31 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT835 vss sub ptap1 A=4e-12 P=8e-6 -MM15_32 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT836 vss sub ptap1 A=4e-12 P=8e-6 -MM15_33 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT837 vss sub ptap1 A=4e-12 P=8e-6 -MM15_34 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT838 vss sub ptap1 A=4e-12 P=8e-6 -MM15_35 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT839 vss sub ptap1 A=4e-12 P=8e-6 -MM15_36 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT840 vss sub ptap1 A=4e-12 P=8e-6 -MM15_37 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT841 vss sub ptap1 A=4e-12 P=8e-6 -MM15_38 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT842 vss sub ptap1 A=4e-12 P=8e-6 -MM15_39 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT843 vss sub ptap1 A=4e-12 P=8e-6 -MM15_40 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT844 vss sub ptap1 A=4e-12 P=8e-6 -MM15_41 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT845 vss sub ptap1 A=4e-12 P=8e-6 -MM15_42 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT846 vss sub ptap1 A=4e-12 P=8e-6 -MM15_43 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT847 vss sub ptap1 A=4e-12 P=8e-6 -MM15_44 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT848 vss sub ptap1 A=4e-12 P=8e-6 -MM15_45 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT849 vss sub ptap1 A=4e-12 P=8e-6 -MM15_46 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT850 vss sub ptap1 A=4e-12 P=8e-6 -MM15_47 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT851 vss sub ptap1 A=4e-12 P=8e-6 -MM15_48 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT852 vss sub ptap1 A=4e-12 P=8e-6 -MM15_49 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT853 vss sub ptap1 A=4e-12 P=8e-6 -MM15_50 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT854 vss sub ptap1 A=4e-12 P=8e-6 -MM15_51 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT855 vss sub ptap1 A=4e-12 P=8e-6 -MM15_52 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT856 vss sub ptap1 A=4e-12 P=8e-6 -MM15_53 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT857 vss sub ptap1 A=4e-12 P=8e-6 -MM15_54 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT858 vss sub ptap1 A=4e-12 P=8e-6 -MM15_55 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT859 vss sub ptap1 A=4e-12 P=8e-6 -MM15_56 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT860 vss sub ptap1 A=4e-12 P=8e-6 -MM15_57 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT861 vss sub ptap1 A=4e-12 P=8e-6 -MM15_58 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT862 vss sub ptap1 A=4e-12 P=8e-6 -MM15_59 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT863 vss sub ptap1 A=4e-12 P=8e-6 -MM15_60 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT864 vss sub ptap1 A=4e-12 P=8e-6 -MM15_61 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT865 vss sub ptap1 A=4e-12 P=8e-6 -MM15_62 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT866 vss sub ptap1 A=4e-12 P=8e-6 -MM15_63 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT867 vss sub ptap1 A=4e-12 P=8e-6 -MM15_64 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT868 vss sub ptap1 A=4e-12 P=8e-6 -MM15_65 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT869 vss sub ptap1 A=4e-12 P=8e-6 -MM15_66 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT870 vss sub ptap1 A=4e-12 P=8e-6 -MM15_67 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT871 vss sub ptap1 A=4e-12 P=8e-6 -MM15_68 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT872 vss sub ptap1 A=4e-12 P=8e-6 -MM15_69 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT873 vss sub ptap1 A=4e-12 P=8e-6 -MM15_70 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT874 vss sub ptap1 A=4e-12 P=8e-6 -MM15_71 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT875 vss sub ptap1 A=4e-12 P=8e-6 -MM15_72 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT876 vss sub ptap1 A=4e-12 P=8e-6 -MM15_73 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT877 vss sub ptap1 A=4e-12 P=8e-6 -MM15_74 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT878 vss sub ptap1 A=4e-12 P=8e-6 -MM15_75 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT879 vss sub ptap1 A=4e-12 P=8e-6 -MM15_76 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT880 vss sub ptap1 A=4e-12 P=8e-6 -MM15_77 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT881 vss sub ptap1 A=4e-12 P=8e-6 -MM15_78 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT882 vss sub ptap1 A=4e-12 P=8e-6 -MM15_79 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT883 vss sub ptap1 A=4e-12 P=8e-6 -MM16_0 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT884 vss sub ptap1 A=4e-12 P=8e-6 -MM16_1 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT885 vss sub ptap1 A=4e-12 P=8e-6 -MM16_2 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT886 vss sub ptap1 A=4e-12 P=8e-6 -MM16_3 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT887 vss sub ptap1 A=4e-12 P=8e-6 -MM16_4 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT888 vss sub ptap1 A=4e-12 P=8e-6 -MM16_5 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT889 vss sub ptap1 A=4e-12 P=8e-6 -MM16_6 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT890 vss sub ptap1 A=4e-12 P=8e-6 -MM16_7 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT891 vss sub ptap1 A=4e-12 P=8e-6 -MM16_8 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT892 vss sub ptap1 A=4e-12 P=8e-6 -MM16_9 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT893 vss sub ptap1 A=4e-12 P=8e-6 -MM16_10 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT894 vss sub ptap1 A=4e-12 P=8e-6 -MM16_11 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT895 vss sub ptap1 A=4e-12 P=8e-6 -MM16_12 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT896 vss sub ptap1 A=4e-12 P=8e-6 -MM16_13 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT897 vss sub ptap1 A=4e-12 P=8e-6 -MM16_14 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT898 vss sub ptap1 A=4e-12 P=8e-6 -MM16_15 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT899 vss sub ptap1 A=4e-12 P=8e-6 -MM16_16 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT900 vss sub ptap1 A=4e-12 P=8e-6 -MM16_17 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT901 vss sub ptap1 A=4e-12 P=8e-6 -MM16_18 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT902 vss sub ptap1 A=4e-12 P=8e-6 -MM16_19 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT903 vss sub ptap1 A=4e-12 P=8e-6 -MM16_20 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT904 vss sub ptap1 A=4e-12 P=8e-6 -MM16_21 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT905 vss sub ptap1 A=4e-12 P=8e-6 -MM16_22 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT906 vss sub ptap1 A=4e-12 P=8e-6 -MM16_23 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT907 vss sub ptap1 A=4e-12 P=8e-6 -MM16_24 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT908 vss sub ptap1 A=4e-12 P=8e-6 -MM16_25 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT909 vss sub ptap1 A=4e-12 P=8e-6 -MM16_26 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT910 vss sub ptap1 A=4e-12 P=8e-6 -MM16_27 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT911 vss sub ptap1 A=4e-12 P=8e-6 -MM16_28 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT912 vss sub ptap1 A=4e-12 P=8e-6 -MM16_29 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT913 vss sub ptap1 A=4e-12 P=8e-6 -MM16_30 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT914 vss sub ptap1 A=4e-12 P=8e-6 -MM16_31 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT915 vss sub ptap1 A=4e-12 P=8e-6 -MM16_32 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT916 vss sub ptap1 A=4e-12 P=8e-6 -MM16_33 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT917 vss sub ptap1 A=4e-12 P=8e-6 -MM16_34 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT918 vss sub ptap1 A=4e-12 P=8e-6 -MM16_35 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT919 vss sub ptap1 A=4e-12 P=8e-6 -MM16_36 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT920 vss sub ptap1 A=4e-12 P=8e-6 -MM16_37 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT921 vss sub ptap1 A=4e-12 P=8e-6 -MM16_38 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT922 vss sub ptap1 A=4e-12 P=8e-6 -MM16_39 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT923 vss sub ptap1 A=4e-12 P=8e-6 -MM16_40 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT924 vss sub ptap1 A=4e-12 P=8e-6 -MM16_41 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT925 vss sub ptap1 A=4e-12 P=8e-6 -MM16_42 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT926 vss sub ptap1 A=4e-12 P=8e-6 -MM16_43 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT927 vss sub ptap1 A=4e-12 P=8e-6 -MM16_44 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT928 vss sub ptap1 A=4e-12 P=8e-6 -MM16_45 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT929 vss sub ptap1 A=4e-12 P=8e-6 -MM16_46 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT930 vss sub ptap1 A=4e-12 P=8e-6 -MM16_47 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT931 vss sub ptap1 A=4e-12 P=8e-6 -MM16_48 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT932 vss sub ptap1 A=4e-12 P=8e-6 -MM16_49 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT933 vss sub ptap1 A=4e-12 P=8e-6 -MM16_50 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT934 vss sub ptap1 A=4e-12 P=8e-6 -MM16_51 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT935 vss sub ptap1 A=4e-12 P=8e-6 -MM16_52 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT936 vss sub ptap1 A=4e-12 P=8e-6 -MM16_53 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT937 vss sub ptap1 A=4e-12 P=8e-6 -MM16_54 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT938 vss sub ptap1 A=4e-12 P=8e-6 -MM16_55 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT939 vss sub ptap1 A=4e-12 P=8e-6 -MM16_56 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT940 vss sub ptap1 A=4e-12 P=8e-6 -MM16_57 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT941 vss sub ptap1 A=4e-12 P=8e-6 -MM16_58 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT942 vss sub ptap1 A=4e-12 P=8e-6 -MM16_59 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT943 vss sub ptap1 A=4e-12 P=8e-6 -MM16_60 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT944 vss sub ptap1 A=4e-12 P=8e-6 -MM16_61 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT945 vss sub ptap1 A=4e-12 P=8e-6 -MM16_62 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT946 vss sub ptap1 A=4e-12 P=8e-6 -MM16_63 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT947 vss sub ptap1 A=4e-12 P=8e-6 -MM16_64 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT948 vss sub ptap1 A=4e-12 P=8e-6 -MM16_65 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT949 vss sub ptap1 A=4e-12 P=8e-6 -MM16_66 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT950 vss sub ptap1 A=4e-12 P=8e-6 -MM16_67 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT951 vss sub ptap1 A=4e-12 P=8e-6 -MM16_68 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT952 vss sub ptap1 A=4e-12 P=8e-6 -MM16_69 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT953 vss sub ptap1 A=4e-12 P=8e-6 -MM16_70 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT954 vss sub ptap1 A=4e-12 P=8e-6 -MM16_71 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT955 vss sub ptap1 A=4e-12 P=8e-6 -MM16_72 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT956 vss sub ptap1 A=4e-12 P=8e-6 -MM16_73 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT957 vss sub ptap1 A=4e-12 P=8e-6 -MM16_74 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT958 vss sub ptap1 A=4e-12 P=8e-6 -MM16_75 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT959 vss sub ptap1 A=4e-12 P=8e-6 -MM16_76 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT960 vss sub ptap1 A=4e-12 P=8e-6 -MM16_77 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT961 vss sub ptap1 A=4e-12 P=8e-6 -MM16_78 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT962 vss sub ptap1 A=4e-12 P=8e-6 -MM16_79 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT963 vss sub ptap1 A=4e-12 P=8e-6 -MM17_0 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT964 vss sub ptap1 A=4e-12 P=8e-6 -MM17_1 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT965 vss sub ptap1 A=4e-12 P=8e-6 -MM17_2 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT966 vss sub ptap1 A=4e-12 P=8e-6 -MM17_3 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT967 vss sub ptap1 A=4e-12 P=8e-6 -MM17_4 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT968 vss sub ptap1 A=4e-12 P=8e-6 -MM17_5 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT969 vss sub ptap1 A=4e-12 P=8e-6 -MM17_6 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT970 vss sub ptap1 A=4e-12 P=8e-6 -MM17_7 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT971 vss sub ptap1 A=4e-12 P=8e-6 -MM17_8 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT972 vss sub ptap1 A=4e-12 P=8e-6 -MM17_9 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT973 vss sub ptap1 A=4e-12 P=8e-6 -MM17_10 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT974 vss sub ptap1 A=4e-12 P=8e-6 -MM17_11 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT975 vss sub ptap1 A=4e-12 P=8e-6 -MM17_12 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT976 vss sub ptap1 A=4e-12 P=8e-6 -MM17_13 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT977 vss sub ptap1 A=4e-12 P=8e-6 -MM17_14 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT978 vss sub ptap1 A=4e-12 P=8e-6 -MM17_15 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT979 vss sub ptap1 A=4e-12 P=8e-6 -MM17_16 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT980 vss sub ptap1 A=4e-12 P=8e-6 -MM17_17 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT981 vss sub ptap1 A=4e-12 P=8e-6 -MM17_18 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT982 vss sub ptap1 A=4e-12 P=8e-6 -MM17_19 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT983 vss sub ptap1 A=4e-12 P=8e-6 -MM17_20 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT984 vss sub ptap1 A=4e-12 P=8e-6 -MM17_21 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT985 vss sub ptap1 A=4e-12 P=8e-6 -MM17_22 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT986 vss sub ptap1 A=4e-12 P=8e-6 -MM17_23 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT987 vss sub ptap1 A=4e-12 P=8e-6 -MM17_24 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT988 vss sub ptap1 A=4e-12 P=8e-6 -MM17_25 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT989 vss sub ptap1 A=4e-12 P=8e-6 -MM17_26 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT990 vss sub ptap1 A=4e-12 P=8e-6 -MM17_27 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT991 vss sub ptap1 A=4e-12 P=8e-6 -MM17_28 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT992 vss sub ptap1 A=4e-12 P=8e-6 -MM17_29 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT993 vss sub ptap1 A=4e-12 P=8e-6 -MM17_30 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT994 vss sub ptap1 A=4e-12 P=8e-6 -MM17_31 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT995 vss sub ptap1 A=4e-12 P=8e-6 -MM17_32 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT996 vss sub ptap1 A=4e-12 P=8e-6 -MM17_33 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT997 vss sub ptap1 A=4e-12 P=8e-6 -MM17_34 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT998 vss sub ptap1 A=4e-12 P=8e-6 -MM17_35 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT999 vss sub ptap1 A=4e-12 P=8e-6 -MM17_36 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1000 vss sub ptap1 A=4e-12 P=8e-6 -MM17_37 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1001 vss sub ptap1 A=4e-12 P=8e-6 -MM17_38 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1002 vss sub ptap1 A=4e-12 P=8e-6 -MM17_39 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1003 vss sub ptap1 A=4e-12 P=8e-6 -MM17_40 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1004 vss sub ptap1 A=4e-12 P=8e-6 -MM17_41 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1005 vss sub ptap1 A=4e-12 P=8e-6 -MM17_42 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1006 vss sub ptap1 A=4e-12 P=8e-6 -MM17_43 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1007 vss sub ptap1 A=4e-12 P=8e-6 -MM17_44 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1008 vss sub ptap1 A=4e-12 P=8e-6 -MM17_45 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1009 vss sub ptap1 A=4e-12 P=8e-6 -MM17_46 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1010 vss sub ptap1 A=4e-12 P=8e-6 -MM17_47 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1011 vss sub ptap1 A=4e-12 P=8e-6 -MM17_48 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1012 vss sub ptap1 A=4e-12 P=8e-6 -MM17_49 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1013 vss sub ptap1 A=4e-12 P=8e-6 -MM17_50 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1014 vss sub ptap1 A=4e-12 P=8e-6 -MM17_51 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1015 vss sub ptap1 A=4e-12 P=8e-6 -MM17_52 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1016 vss sub ptap1 A=4e-12 P=8e-6 -MM17_53 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1017 vss sub ptap1 A=4e-12 P=8e-6 -MM17_54 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1018 vss sub ptap1 A=4e-12 P=8e-6 -MM17_55 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1019 vss sub ptap1 A=4e-12 P=8e-6 -MM17_56 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1020 vss sub ptap1 A=4e-12 P=8e-6 -MM17_57 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1021 vss sub ptap1 A=4e-12 P=8e-6 -MM17_58 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1022 vss sub ptap1 A=4e-12 P=8e-6 -MM17_59 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1023 vss sub ptap1 A=4e-12 P=8e-6 -MM17_60 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1024 vss sub ptap1 A=4e-12 P=8e-6 -MM17_61 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1025 vss sub ptap1 A=4e-12 P=8e-6 -MM17_62 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1026 vss sub ptap1 A=4e-12 P=8e-6 -MM17_63 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1027 vss sub ptap1 A=4e-12 P=8e-6 -MM17_64 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1028 vss sub ptap1 A=4e-12 P=8e-6 -MM17_65 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1029 vss sub ptap1 A=4e-12 P=8e-6 -MM17_66 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1030 vss sub ptap1 A=4e-12 P=8e-6 -MM17_67 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1031 vss sub ptap1 A=4e-12 P=8e-6 -MM17_68 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1032 vss sub ptap1 A=4e-12 P=8e-6 -MM17_69 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1033 vss sub ptap1 A=4e-12 P=8e-6 -MM17_70 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1034 vss sub ptap1 A=4e-12 P=8e-6 -MM17_71 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1035 vss sub ptap1 A=4e-12 P=8e-6 -MM17_72 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1036 vss sub ptap1 A=4e-12 P=8e-6 -MM17_73 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1037 vss sub ptap1 A=4e-12 P=8e-6 -MM17_74 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1038 vss sub ptap1 A=4e-12 P=8e-6 -MM17_75 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1039 vss sub ptap1 A=4e-12 P=8e-6 -MM17_76 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1040 vss sub ptap1 A=4e-12 P=8e-6 -MM17_77 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1041 vss sub ptap1 A=4e-12 P=8e-6 -MM17_78 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1042 vss sub ptap1 A=4e-12 P=8e-6 -MM17_79 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1043 vss sub ptap1 A=4e-12 P=8e-6 -MM18_0 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1044 vss sub ptap1 A=4e-12 P=8e-6 -MM18_1 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1045 vss sub ptap1 A=4e-12 P=8e-6 -MM18_2 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1046 vss sub ptap1 A=4e-12 P=8e-6 -MM18_3 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1047 vss sub ptap1 A=4e-12 P=8e-6 -MM18_4 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1048 vss sub ptap1 A=4e-12 P=8e-6 -MM18_5 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1049 vss sub ptap1 A=4e-12 P=8e-6 -MM18_6 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1050 vss sub ptap1 A=4e-12 P=8e-6 -MM18_7 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1051 vss sub ptap1 A=4e-12 P=8e-6 -MM18_8 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1052 vss sub ptap1 A=4e-12 P=8e-6 -MM18_9 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1053 vss sub ptap1 A=4e-12 P=8e-6 -MM18_10 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1054 vss sub ptap1 A=4e-12 P=8e-6 -MM18_11 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1055 vss sub ptap1 A=4e-12 P=8e-6 -MM18_12 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1056 vss sub ptap1 A=4e-12 P=8e-6 -MM18_13 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1057 vss sub ptap1 A=4e-12 P=8e-6 -MM18_14 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1058 vss sub ptap1 A=4e-12 P=8e-6 -MM18_15 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1059 vss sub ptap1 A=4e-12 P=8e-6 -MM18_16 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1060 vss sub ptap1 A=4e-12 P=8e-6 -MM18_17 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1061 vss sub ptap1 A=4e-12 P=8e-6 -MM18_18 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1062 vss sub ptap1 A=4e-12 P=8e-6 -MM18_19 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1063 vss sub ptap1 A=4e-12 P=8e-6 -MM18_20 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1064 vss sub ptap1 A=4e-12 P=8e-6 -MM18_21 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1065 vss sub ptap1 A=4e-12 P=8e-6 -MM18_22 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1066 vss sub ptap1 A=4e-12 P=8e-6 -MM18_23 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1067 vss sub ptap1 A=4e-12 P=8e-6 -MM18_24 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1068 vss sub ptap1 A=4e-12 P=8e-6 -MM18_25 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1069 vss sub ptap1 A=4e-12 P=8e-6 -MM18_26 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1070 vss sub ptap1 A=4e-12 P=8e-6 -MM18_27 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1071 vss sub ptap1 A=4e-12 P=8e-6 -MM18_28 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1072 vss sub ptap1 A=4e-12 P=8e-6 -MM18_29 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1073 vss sub ptap1 A=4e-12 P=8e-6 -MM18_30 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1074 vss sub ptap1 A=4e-12 P=8e-6 -MM18_31 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1075 vss sub ptap1 A=4e-12 P=8e-6 -MM18_32 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1076 vss sub ptap1 A=4e-12 P=8e-6 -MM18_33 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1077 vss sub ptap1 A=4e-12 P=8e-6 -MM18_34 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1078 vss sub ptap1 A=4e-12 P=8e-6 -MM18_35 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1079 vss sub ptap1 A=4e-12 P=8e-6 -MM18_36 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1080 vss sub ptap1 A=4e-12 P=8e-6 -MM18_37 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1081 vss sub ptap1 A=4e-12 P=8e-6 -MM18_38 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1082 vss sub ptap1 A=4e-12 P=8e-6 -MM18_39 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1083 vss sub ptap1 A=4e-12 P=8e-6 -MM18_40 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1084 vss sub ptap1 A=4e-12 P=8e-6 -MM18_41 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1085 vss sub ptap1 A=4e-12 P=8e-6 -MM18_42 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1086 vss sub ptap1 A=4e-12 P=8e-6 -MM18_43 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1087 vss sub ptap1 A=4e-12 P=8e-6 -MM18_44 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1088 vss sub ptap1 A=4e-12 P=8e-6 -MM18_45 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1089 vss sub ptap1 A=4e-12 P=8e-6 -MM18_46 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1090 vss sub ptap1 A=4e-12 P=8e-6 -MM18_47 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1091 vss sub ptap1 A=4e-12 P=8e-6 -MM18_48 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1092 vss sub ptap1 A=4e-12 P=8e-6 -MM18_49 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1093 vss sub ptap1 A=4e-12 P=8e-6 -MM18_50 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1094 vss sub ptap1 A=4e-12 P=8e-6 -MM18_51 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1095 vss sub ptap1 A=4e-12 P=8e-6 -MM18_52 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1096 vss sub ptap1 A=4e-12 P=8e-6 -MM18_53 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1097 vss sub ptap1 A=4e-12 P=8e-6 -MM18_54 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1098 vss sub ptap1 A=4e-12 P=8e-6 -MM18_55 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1099 vss sub ptap1 A=4e-12 P=8e-6 -MM18_56 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1100 vss sub ptap1 A=4e-12 P=8e-6 -MM18_57 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1101 vss sub ptap1 A=4e-12 P=8e-6 -MM18_58 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1102 vss sub ptap1 A=4e-12 P=8e-6 -MM18_59 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1103 vss sub ptap1 A=4e-12 P=8e-6 -MM18_60 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1104 vss sub ptap1 A=4e-12 P=8e-6 -MM18_61 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1105 vss sub ptap1 A=4e-12 P=8e-6 -MM18_62 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1106 vss sub ptap1 A=4e-12 P=8e-6 -MM18_63 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1107 vss sub ptap1 A=4e-12 P=8e-6 -MM18_64 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1108 vss sub ptap1 A=4e-12 P=8e-6 -MM18_65 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1109 vss sub ptap1 A=4e-12 P=8e-6 -MM18_66 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1110 vss sub ptap1 A=4e-12 P=8e-6 -MM18_67 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1111 vss sub ptap1 A=4e-12 P=8e-6 -MM18_68 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1112 vss sub ptap1 A=4e-12 P=8e-6 -MM18_69 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1113 vss sub ptap1 A=4e-12 P=8e-6 -MM18_70 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1114 vss sub ptap1 A=4e-12 P=8e-6 -MM18_71 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1115 vss sub ptap1 A=4e-12 P=8e-6 -MM18_72 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1116 vss sub ptap1 A=4e-12 P=8e-6 -MM18_73 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1117 vss sub ptap1 A=4e-12 P=8e-6 -MM18_74 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1118 vss sub ptap1 A=4e-12 P=8e-6 -MM18_75 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1119 vss sub ptap1 A=4e-12 P=8e-6 -MM18_76 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1120 vss sub ptap1 A=4e-12 P=8e-6 -MM18_77 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1121 vss sub ptap1 A=4e-12 P=8e-6 -MM18_78 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1122 vss sub ptap1 A=4e-12 P=8e-6 -MM18_79 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1123 vss sub ptap1 A=4e-12 P=8e-6 -MM19_0 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1124 vss sub ptap1 A=4e-12 P=8e-6 -MM19_1 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1125 vss sub ptap1 A=4e-12 P=8e-6 -MM19_2 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1126 vss sub ptap1 A=4e-12 P=8e-6 -MM19_3 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1127 vss sub ptap1 A=4e-12 P=8e-6 -MM19_4 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1128 vss sub ptap1 A=4e-12 P=8e-6 -MM19_5 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1129 vss sub ptap1 A=4e-12 P=8e-6 -MM19_6 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1130 vss sub ptap1 A=4e-12 P=8e-6 -MM19_7 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1131 vss sub ptap1 A=4e-12 P=8e-6 -MM19_8 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1132 vss sub ptap1 A=4e-12 P=8e-6 -MM19_9 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1133 vss sub ptap1 A=4e-12 P=8e-6 -MM19_10 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1134 vss sub ptap1 A=4e-12 P=8e-6 -MM19_11 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1135 vss sub ptap1 A=4e-12 P=8e-6 -MM19_12 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1136 vss sub ptap1 A=4e-12 P=8e-6 -MM19_13 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1137 vss sub ptap1 A=4e-12 P=8e-6 -MM19_14 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1138 vss sub ptap1 A=4e-12 P=8e-6 -MM19_15 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1139 vss sub ptap1 A=4e-12 P=8e-6 -MM19_16 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1140 vss sub ptap1 A=4e-12 P=8e-6 -MM19_17 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1141 vss sub ptap1 A=4e-12 P=8e-6 -MM19_18 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1142 vss sub ptap1 A=4e-12 P=8e-6 -MM19_19 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1143 vss sub ptap1 A=4e-12 P=8e-6 -MM19_20 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1144 vss sub ptap1 A=4e-12 P=8e-6 -MM19_21 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1145 vss sub ptap1 A=4e-12 P=8e-6 -MM19_22 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1146 vss sub ptap1 A=4e-12 P=8e-6 -MM19_23 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1147 vss sub ptap1 A=4e-12 P=8e-6 -MM19_24 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1148 vss sub ptap1 A=4e-12 P=8e-6 -MM19_25 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1149 vss sub ptap1 A=4e-12 P=8e-6 -MM19_26 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1150 vss sub ptap1 A=4e-12 P=8e-6 -MM19_27 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1151 vss sub ptap1 A=4e-12 P=8e-6 -MM19_28 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1152 vss sub ptap1 A=4e-12 P=8e-6 -MM19_29 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1153 vss sub ptap1 A=4e-12 P=8e-6 -MM19_30 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1154 vss sub ptap1 A=4e-12 P=8e-6 -MM19_31 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1155 vss sub ptap1 A=4e-12 P=8e-6 -MM19_32 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1156 vss sub ptap1 A=4e-12 P=8e-6 -MM19_33 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1157 vss sub ptap1 A=4e-12 P=8e-6 -MM19_34 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1158 vss sub ptap1 A=4e-12 P=8e-6 -MM19_35 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1159 vss sub ptap1 A=4e-12 P=8e-6 -MM19_36 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1160 vss sub ptap1 A=4e-12 P=8e-6 -MM19_37 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1161 vss sub ptap1 A=4e-12 P=8e-6 -MM19_38 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1162 vss sub ptap1 A=4e-12 P=8e-6 -MM19_39 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1163 vss sub ptap1 A=4e-12 P=8e-6 -MM19_40 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1164 vss sub ptap1 A=4e-12 P=8e-6 -MM19_41 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1165 vss sub ptap1 A=4e-12 P=8e-6 -MM19_42 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1166 vss sub ptap1 A=4e-12 P=8e-6 -MM19_43 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1167 vss sub ptap1 A=4e-12 P=8e-6 -MM19_44 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1168 vss sub ptap1 A=4e-12 P=8e-6 -MM19_45 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1169 vss sub ptap1 A=4e-12 P=8e-6 -MM19_46 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1170 vss sub ptap1 A=4e-12 P=8e-6 -MM19_47 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1171 vss sub ptap1 A=4e-12 P=8e-6 -MM19_48 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1172 vss sub ptap1 A=4e-12 P=8e-6 -MM19_49 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1173 vss sub ptap1 A=4e-12 P=8e-6 -MM19_50 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1174 vss sub ptap1 A=4e-12 P=8e-6 -MM19_51 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1175 vss sub ptap1 A=4e-12 P=8e-6 -MM19_52 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1176 vss sub ptap1 A=4e-12 P=8e-6 -MM19_53 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1177 vss sub ptap1 A=4e-12 P=8e-6 -MM19_54 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1178 vss sub ptap1 A=4e-12 P=8e-6 -MM19_55 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1179 vss sub ptap1 A=4e-12 P=8e-6 -MM19_56 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1180 vss sub ptap1 A=4e-12 P=8e-6 -MM19_57 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1181 vss sub ptap1 A=4e-12 P=8e-6 -MM19_58 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1182 vss sub ptap1 A=4e-12 P=8e-6 -MM19_59 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1183 vss sub ptap1 A=4e-12 P=8e-6 -MM19_60 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1184 vss sub ptap1 A=4e-12 P=8e-6 -MM19_61 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1185 vss sub ptap1 A=4e-12 P=8e-6 -MM19_62 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1186 vss sub ptap1 A=4e-12 P=8e-6 -MM19_63 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1187 vss sub ptap1 A=4e-12 P=8e-6 -MM19_64 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1188 vss sub ptap1 A=4e-12 P=8e-6 -MM19_65 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1189 vss sub ptap1 A=4e-12 P=8e-6 -MM19_66 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1190 vss sub ptap1 A=4e-12 P=8e-6 -MM19_67 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1191 vss sub ptap1 A=4e-12 P=8e-6 -MM19_68 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1192 vss sub ptap1 A=4e-12 P=8e-6 -MM19_69 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1193 vss sub ptap1 A=4e-12 P=8e-6 -MM19_70 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1194 vss sub ptap1 A=4e-12 P=8e-6 -MM19_71 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1195 vss sub ptap1 A=4e-12 P=8e-6 -MM19_72 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1196 vss sub ptap1 A=4e-12 P=8e-6 -MM19_73 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1197 vss sub ptap1 A=4e-12 P=8e-6 -MM19_74 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1198 vss sub ptap1 A=4e-12 P=8e-6 -MM19_75 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1199 vss sub ptap1 A=4e-12 P=8e-6 -MM19_76 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1200 vss sub ptap1 A=4e-12 P=8e-6 -MM19_77 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1201 vss sub ptap1 A=4e-12 P=8e-6 -MM19_78 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1202 vss sub ptap1 A=4e-12 P=8e-6 -MM19_79 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1203 vss sub ptap1 A=4e-12 P=8e-6 -MM19_80 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1204 vss sub ptap1 A=4e-12 P=8e-6 -MM19_81 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1205 vss sub ptap1 A=4e-12 P=8e-6 -MM19_82 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1206 vss sub ptap1 A=4e-12 P=8e-6 -MM19_83 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1207 vss sub ptap1 A=4e-12 P=8e-6 -MM19_84 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1208 vss sub ptap1 A=4e-12 P=8e-6 -MM19_85 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1209 vss sub ptap1 A=4e-12 P=8e-6 -MM19_86 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1210 vss sub ptap1 A=4e-12 P=8e-6 -MM19_87 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1211 vss sub ptap1 A=4e-12 P=8e-6 -MM19_88 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1212 vss sub ptap1 A=4e-12 P=8e-6 -MM19_89 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1213 vss sub ptap1 A=4e-12 P=8e-6 -MM19_90 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1214 vss sub ptap1 A=4e-12 P=8e-6 -MM19_91 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1215 vss sub ptap1 A=4e-12 P=8e-6 -MM19_92 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1216 vss sub ptap1 A=4e-12 P=8e-6 -MM19_93 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1217 vss sub ptap1 A=4e-12 P=8e-6 -MM19_94 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1218 vss sub ptap1 A=4e-12 P=8e-6 -MM19_95 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1219 vss sub ptap1 A=4e-12 P=8e-6 -MM19_96 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1220 vss sub ptap1 A=4e-12 P=8e-6 -MM19_97 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1221 vss sub ptap1 A=4e-12 P=8e-6 -MM19_98 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1222 vss sub ptap1 A=4e-12 P=8e-6 -MM19_99 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1223 vss sub ptap1 A=4e-12 P=8e-6 -MM19_100 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1224 vss sub ptap1 A=4e-12 P=8e-6 -MM19_101 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1225 vss sub ptap1 A=4e-12 P=8e-6 -MM19_102 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1226 vss sub ptap1 A=4e-12 P=8e-6 -MM19_103 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1227 vss sub ptap1 A=4e-12 P=8e-6 -MM19_104 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1228 vss sub ptap1 A=4e-12 P=8e-6 -MM19_105 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1229 vss sub ptap1 A=4e-12 P=8e-6 -MM19_106 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1230 vss sub ptap1 A=4e-12 P=8e-6 -MM19_107 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1231 vss sub ptap1 A=4e-12 P=8e-6 -MM19_108 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1232 vss sub ptap1 A=4e-12 P=8e-6 -MM19_109 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1233 vss sub ptap1 A=4e-12 P=8e-6 -MM19_110 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1234 vss sub ptap1 A=4e-12 P=8e-6 -MM19_111 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1235 vss sub ptap1 A=4e-12 P=8e-6 -MM19_112 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1236 vss sub ptap1 A=4e-12 P=8e-6 -MM19_113 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1237 vss sub ptap1 A=4e-12 P=8e-6 -MM19_114 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1238 vss sub ptap1 A=4e-12 P=8e-6 -MM19_115 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1239 vss sub ptap1 A=4e-12 P=8e-6 -MM19_116 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1240 vss sub ptap1 A=4e-12 P=8e-6 -MM19_117 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1241 vss sub ptap1 A=4e-12 P=8e-6 -MM19_118 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1242 vss sub ptap1 A=4e-12 P=8e-6 -MM19_119 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1243 vss sub ptap1 A=4e-12 P=8e-6 -MM19_120 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1244 vss sub ptap1 A=4e-12 P=8e-6 -MM19_121 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1245 vss sub ptap1 A=4e-12 P=8e-6 -MM19_122 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1246 vss sub ptap1 A=4e-12 P=8e-6 -MM19_123 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1247 vss sub ptap1 A=4e-12 P=8e-6 -MM19_124 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1248 vss sub ptap1 A=4e-12 P=8e-6 -MM19_125 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1249 vss sub ptap1 A=4e-12 P=8e-6 -MM19_126 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1250 vss sub ptap1 A=4e-12 P=8e-6 -MM19_127 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1251 vss sub ptap1 A=4e-12 P=8e-6 -MM19_128 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1252 vss sub ptap1 A=4e-12 P=8e-6 -MM19_129 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1253 vss sub ptap1 A=4e-12 P=8e-6 -MM19_130 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1254 vss sub ptap1 A=4e-12 P=8e-6 -MM19_131 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1255 vss sub ptap1 A=4e-12 P=8e-6 -MM19_132 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1256 vss sub ptap1 A=4e-12 P=8e-6 -MM19_133 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1257 vss sub ptap1 A=4e-12 P=8e-6 -MM19_134 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1258 vss sub ptap1 A=4e-12 P=8e-6 -MM19_135 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1259 vss sub ptap1 A=4e-12 P=8e-6 -MM19_136 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1260 vss sub ptap1 A=4e-12 P=8e-6 -MM19_137 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1261 vss sub ptap1 A=4e-12 P=8e-6 -MM19_138 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1262 vss sub ptap1 A=4e-12 P=8e-6 -MM19_139 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1263 vss sub ptap1 A=4e-12 P=8e-6 -MM19_140 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1264 vss sub ptap1 A=4e-12 P=8e-6 -MM19_141 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1265 vss sub ptap1 A=4e-12 P=8e-6 -MM19_142 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1266 vss sub ptap1 A=4e-12 P=8e-6 -MM19_143 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1267 vss sub ptap1 A=4e-12 P=8e-6 -MM19_144 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1268 vss sub ptap1 A=4e-12 P=8e-6 -MM19_145 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1269 vss sub ptap1 A=4e-12 P=8e-6 -MM19_146 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1270 vss sub ptap1 A=4e-12 P=8e-6 -MM19_147 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1271 vss sub ptap1 A=4e-12 P=8e-6 -MM19_148 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1272 vss sub ptap1 A=4e-12 P=8e-6 -MM19_149 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1273 vss sub ptap1 A=4e-12 P=8e-6 -MM19_150 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1274 vss sub ptap1 A=4e-12 P=8e-6 -MM19_151 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1275 vss sub ptap1 A=4e-12 P=8e-6 -MM19_152 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1276 vss sub ptap1 A=4e-12 P=8e-6 -MM19_153 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1277 vss sub ptap1 A=4e-12 P=8e-6 -MM19_154 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1278 vss sub ptap1 A=4e-12 P=8e-6 -MM19_155 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1279 vss sub ptap1 A=4e-12 P=8e-6 -MM19_156 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1280 vss sub ptap1 A=4e-12 P=8e-6 -MM19_157 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1281 vss sub ptap1 A=4e-12 P=8e-6 -MM19_158 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1282 vss sub ptap1 A=4e-12 P=8e-6 -MM19_159 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1283 vdd well_1283 ntap1 A=4e-12 P=8e-6 -MM2_0 dm_1 net1 vdd well_1283 sg13_lv_pmos w=1u l=1u m=1 -RT1284 vdd well_1284 ntap1 A=4e-12 P=8e-6 -MM2_1 dm_1 net1 vdd well_1284 sg13_lv_pmos w=1u l=1u m=1 -RT1285 vdd well_1285 ntap1 A=4e-12 P=8e-6 -MM2_2 dm_1 net1 vdd well_1285 sg13_lv_pmos w=1u l=1u m=1 -RT1286 vdd well_1286 ntap1 A=4e-12 P=8e-6 -MM2_3 dm_1 net1 vdd well_1286 sg13_lv_pmos w=1u l=1u m=1 -RT1287 vdd well_1287 ntap1 A=4e-12 P=8e-6 -MM2_4 dm_1 net1 vdd well_1287 sg13_lv_pmos w=1u l=1u m=1 -RT1288 vdd well_1288 ntap1 A=4e-12 P=8e-6 -MM2_5 dm_1 net1 vdd well_1288 sg13_lv_pmos w=1u l=1u m=1 -RT1289 vdd well_1289 ntap1 A=4e-12 P=8e-6 -MM2_6 dm_1 net1 vdd well_1289 sg13_lv_pmos w=1u l=1u m=1 -RT1290 vdd well_1290 ntap1 A=4e-12 P=8e-6 -MM2_7 dm_1 net1 vdd well_1290 sg13_lv_pmos w=1u l=1u m=1 -RT1291 vdd well_1291 ntap1 A=4e-12 P=8e-6 -MM2_8 dm_1 net1 vdd well_1291 sg13_lv_pmos w=1u l=1u m=1 -RT1292 vdd well_1292 ntap1 A=4e-12 P=8e-6 -MM2_9 dm_1 net1 vdd well_1292 sg13_lv_pmos w=1u l=1u m=1 -RT1293 vdd well_1293 ntap1 A=4e-12 P=8e-6 -MM2_10 dm_1 net1 vdd well_1293 sg13_lv_pmos w=1u l=1u m=1 -RT1294 vdd well_1294 ntap1 A=4e-12 P=8e-6 -MM2_11 dm_1 net1 vdd well_1294 sg13_lv_pmos w=1u l=1u m=1 -RT1295 vdd well_1295 ntap1 A=4e-12 P=8e-6 -MM2_12 dm_1 net1 vdd well_1295 sg13_lv_pmos w=1u l=1u m=1 -RT1296 vdd well_1296 ntap1 A=4e-12 P=8e-6 -MM2_13 dm_1 net1 vdd well_1296 sg13_lv_pmos w=1u l=1u m=1 -RT1297 vdd well_1297 ntap1 A=4e-12 P=8e-6 -MM2_14 dm_1 net1 vdd well_1297 sg13_lv_pmos w=1u l=1u m=1 -RT1298 vdd well_1298 ntap1 A=4e-12 P=8e-6 -MM2_15 dm_1 net1 vdd well_1298 sg13_lv_pmos w=1u l=1u m=1 -RT1299 vdd well_1299 ntap1 A=4e-12 P=8e-6 -MM2_16 dm_1 net1 vdd well_1299 sg13_lv_pmos w=1u l=1u m=1 -RT1300 vdd well_1300 ntap1 A=4e-12 P=8e-6 -MM2_17 dm_1 net1 vdd well_1300 sg13_lv_pmos w=1u l=1u m=1 -RT1301 vdd well_1301 ntap1 A=4e-12 P=8e-6 -MM2_18 dm_1 net1 vdd well_1301 sg13_lv_pmos w=1u l=1u m=1 -RT1302 vdd well_1302 ntap1 A=4e-12 P=8e-6 -MM2_19 dm_1 net1 vdd well_1302 sg13_lv_pmos w=1u l=1u m=1 -RT1303 vdd well_1303 ntap1 A=4e-12 P=8e-6 -MM2_20 dm_1 net1 vdd well_1303 sg13_lv_pmos w=1u l=1u m=1 -RT1304 vdd well_1304 ntap1 A=4e-12 P=8e-6 -MM2_21 dm_1 net1 vdd well_1304 sg13_lv_pmos w=1u l=1u m=1 -RT1305 vdd well_1305 ntap1 A=4e-12 P=8e-6 -MM2_22 dm_1 net1 vdd well_1305 sg13_lv_pmos w=1u l=1u m=1 -RT1306 vdd well_1306 ntap1 A=4e-12 P=8e-6 -MM2_23 dm_1 net1 vdd well_1306 sg13_lv_pmos w=1u l=1u m=1 -RT1307 vdd well_1307 ntap1 A=4e-12 P=8e-6 -MM2_24 dm_1 net1 vdd well_1307 sg13_lv_pmos w=1u l=1u m=1 -RT1308 vdd well_1308 ntap1 A=4e-12 P=8e-6 -MM2_25 dm_1 net1 vdd well_1308 sg13_lv_pmos w=1u l=1u m=1 -RT1309 vdd well_1309 ntap1 A=4e-12 P=8e-6 -MM2_26 dm_1 net1 vdd well_1309 sg13_lv_pmos w=1u l=1u m=1 -RT1310 vdd well_1310 ntap1 A=4e-12 P=8e-6 -MM2_27 dm_1 net1 vdd well_1310 sg13_lv_pmos w=1u l=1u m=1 -RT1311 vdd well_1311 ntap1 A=4e-12 P=8e-6 -MM2_28 dm_1 net1 vdd well_1311 sg13_lv_pmos w=1u l=1u m=1 -RT1312 vdd well_1312 ntap1 A=4e-12 P=8e-6 -MM2_29 dm_1 net1 vdd well_1312 sg13_lv_pmos w=1u l=1u m=1 -RT1313 vdd well_1313 ntap1 A=4e-12 P=8e-6 -MM2_30 dm_1 net1 vdd well_1313 sg13_lv_pmos w=1u l=1u m=1 -RT1314 vdd well_1314 ntap1 A=4e-12 P=8e-6 -MM2_31 dm_1 net1 vdd well_1314 sg13_lv_pmos w=1u l=1u m=1 -RT1315 vdd well_1315 ntap1 A=4e-12 P=8e-6 -MM2_32 dm_1 net1 vdd well_1315 sg13_lv_pmos w=1u l=1u m=1 -RT1316 vdd well_1316 ntap1 A=4e-12 P=8e-6 -MM2_33 dm_1 net1 vdd well_1316 sg13_lv_pmos w=1u l=1u m=1 -RT1317 vdd well_1317 ntap1 A=4e-12 P=8e-6 -MM2_34 dm_1 net1 vdd well_1317 sg13_lv_pmos w=1u l=1u m=1 -RT1318 vdd well_1318 ntap1 A=4e-12 P=8e-6 -MM2_35 dm_1 net1 vdd well_1318 sg13_lv_pmos w=1u l=1u m=1 -RT1319 vdd well_1319 ntap1 A=4e-12 P=8e-6 -MM2_36 dm_1 net1 vdd well_1319 sg13_lv_pmos w=1u l=1u m=1 -RT1320 vdd well_1320 ntap1 A=4e-12 P=8e-6 -MM2_37 dm_1 net1 vdd well_1320 sg13_lv_pmos w=1u l=1u m=1 -RT1321 vdd well_1321 ntap1 A=4e-12 P=8e-6 -MM2_38 dm_1 net1 vdd well_1321 sg13_lv_pmos w=1u l=1u m=1 -RT1322 vdd well_1322 ntap1 A=4e-12 P=8e-6 -MM2_39 dm_1 net1 vdd well_1322 sg13_lv_pmos w=1u l=1u m=1 -RT1323 vdd well_1323 ntap1 A=4e-12 P=8e-6 -MM2_40 dm_1 net1 vdd well_1323 sg13_lv_pmos w=1u l=1u m=1 -RT1324 vdd well_1324 ntap1 A=4e-12 P=8e-6 -MM2_41 dm_1 net1 vdd well_1324 sg13_lv_pmos w=1u l=1u m=1 -RT1325 vdd well_1325 ntap1 A=4e-12 P=8e-6 -MM2_42 dm_1 net1 vdd well_1325 sg13_lv_pmos w=1u l=1u m=1 -RT1326 vdd well_1326 ntap1 A=4e-12 P=8e-6 -MM2_43 dm_1 net1 vdd well_1326 sg13_lv_pmos w=1u l=1u m=1 -RT1327 vdd well_1327 ntap1 A=4e-12 P=8e-6 -MM2_44 dm_1 net1 vdd well_1327 sg13_lv_pmos w=1u l=1u m=1 -RT1328 vdd well_1328 ntap1 A=4e-12 P=8e-6 -MM2_45 dm_1 net1 vdd well_1328 sg13_lv_pmos w=1u l=1u m=1 -RT1329 vdd well_1329 ntap1 A=4e-12 P=8e-6 -MM2_46 dm_1 net1 vdd well_1329 sg13_lv_pmos w=1u l=1u m=1 -RT1330 vdd well_1330 ntap1 A=4e-12 P=8e-6 -MM2_47 dm_1 net1 vdd well_1330 sg13_lv_pmos w=1u l=1u m=1 -RT1331 vdd well_1331 ntap1 A=4e-12 P=8e-6 -MM2_48 dm_1 net1 vdd well_1331 sg13_lv_pmos w=1u l=1u m=1 -RT1332 vdd well_1332 ntap1 A=4e-12 P=8e-6 -MM2_49 dm_1 net1 vdd well_1332 sg13_lv_pmos w=1u l=1u m=1 -RT1333 vdd well_1333 ntap1 A=4e-12 P=8e-6 -MM2_50 dm_1 net1 vdd well_1333 sg13_lv_pmos w=1u l=1u m=1 -RT1334 vdd well_1334 ntap1 A=4e-12 P=8e-6 -MM2_51 dm_1 net1 vdd well_1334 sg13_lv_pmos w=1u l=1u m=1 -RT1335 vdd well_1335 ntap1 A=4e-12 P=8e-6 -MM2_52 dm_1 net1 vdd well_1335 sg13_lv_pmos w=1u l=1u m=1 -RT1336 vdd well_1336 ntap1 A=4e-12 P=8e-6 -MM2_53 dm_1 net1 vdd well_1336 sg13_lv_pmos w=1u l=1u m=1 -RT1337 vdd well_1337 ntap1 A=4e-12 P=8e-6 -MM2_54 dm_1 net1 vdd well_1337 sg13_lv_pmos w=1u l=1u m=1 -RT1338 vdd well_1338 ntap1 A=4e-12 P=8e-6 -MM2_55 dm_1 net1 vdd well_1338 sg13_lv_pmos w=1u l=1u m=1 -RT1339 vdd well_1339 ntap1 A=4e-12 P=8e-6 -MM2_56 dm_1 net1 vdd well_1339 sg13_lv_pmos w=1u l=1u m=1 -RT1340 vdd well_1340 ntap1 A=4e-12 P=8e-6 -MM2_57 dm_1 net1 vdd well_1340 sg13_lv_pmos w=1u l=1u m=1 -RT1341 vdd well_1341 ntap1 A=4e-12 P=8e-6 -MM2_58 dm_1 net1 vdd well_1341 sg13_lv_pmos w=1u l=1u m=1 -RT1342 vdd well_1342 ntap1 A=4e-12 P=8e-6 -MM2_59 dm_1 net1 vdd well_1342 sg13_lv_pmos w=1u l=1u m=1 -RT1343 vdd well_1343 ntap1 A=4e-12 P=8e-6 -MM2_60 dm_1 net1 vdd well_1343 sg13_lv_pmos w=1u l=1u m=1 -RT1344 vdd well_1344 ntap1 A=4e-12 P=8e-6 -MM2_61 dm_1 net1 vdd well_1344 sg13_lv_pmos w=1u l=1u m=1 -RT1345 vdd well_1345 ntap1 A=4e-12 P=8e-6 -MM2_62 dm_1 net1 vdd well_1345 sg13_lv_pmos w=1u l=1u m=1 -RT1346 vdd well_1346 ntap1 A=4e-12 P=8e-6 -MM2_63 dm_1 net1 vdd well_1346 sg13_lv_pmos w=1u l=1u m=1 -RT1347 vdd well_1347 ntap1 A=4e-12 P=8e-6 -MM2_64 dm_1 net1 vdd well_1347 sg13_lv_pmos w=1u l=1u m=1 -RT1348 vdd well_1348 ntap1 A=4e-12 P=8e-6 -MM2_65 dm_1 net1 vdd well_1348 sg13_lv_pmos w=1u l=1u m=1 -RT1349 vdd well_1349 ntap1 A=4e-12 P=8e-6 -MM2_66 dm_1 net1 vdd well_1349 sg13_lv_pmos w=1u l=1u m=1 -RT1350 vdd well_1350 ntap1 A=4e-12 P=8e-6 -MM2_67 dm_1 net1 vdd well_1350 sg13_lv_pmos w=1u l=1u m=1 -RT1351 vdd well_1351 ntap1 A=4e-12 P=8e-6 -MM2_68 dm_1 net1 vdd well_1351 sg13_lv_pmos w=1u l=1u m=1 -RT1352 vdd well_1352 ntap1 A=4e-12 P=8e-6 -MM2_69 dm_1 net1 vdd well_1352 sg13_lv_pmos w=1u l=1u m=1 -RT1353 vdd well_1353 ntap1 A=4e-12 P=8e-6 -MM2_70 dm_1 net1 vdd well_1353 sg13_lv_pmos w=1u l=1u m=1 -RT1354 vss sub ptap1 A=4e-12 P=8e-6 -MM20_0 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1355 vss sub ptap1 A=4e-12 P=8e-6 -MM20_1 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1356 vss sub ptap1 A=4e-12 P=8e-6 -MM20_2 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1357 vss sub ptap1 A=4e-12 P=8e-6 -MM20_3 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1358 vss sub ptap1 A=4e-12 P=8e-6 -MM20_4 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1359 vss sub ptap1 A=4e-12 P=8e-6 -MM20_5 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1360 vss sub ptap1 A=4e-12 P=8e-6 -MM20_6 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1361 vss sub ptap1 A=4e-12 P=8e-6 -MM20_7 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1362 vss sub ptap1 A=4e-12 P=8e-6 -MM20_8 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1363 vss sub ptap1 A=4e-12 P=8e-6 -MM20_9 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1364 vss sub ptap1 A=4e-12 P=8e-6 -MM20_10 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1365 vss sub ptap1 A=4e-12 P=8e-6 -MM20_11 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1366 vss sub ptap1 A=4e-12 P=8e-6 -MM20_12 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1367 vss sub ptap1 A=4e-12 P=8e-6 -MM20_13 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1368 vss sub ptap1 A=4e-12 P=8e-6 -MM20_14 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1369 vss sub ptap1 A=4e-12 P=8e-6 -MM20_15 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1370 vss sub ptap1 A=4e-12 P=8e-6 -MM20_16 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1371 vss sub ptap1 A=4e-12 P=8e-6 -MM20_17 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1372 vss sub ptap1 A=4e-12 P=8e-6 -MM20_18 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1373 vss sub ptap1 A=4e-12 P=8e-6 -MM20_19 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1374 vss sub ptap1 A=4e-12 P=8e-6 -MM20_20 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1375 vss sub ptap1 A=4e-12 P=8e-6 -MM20_21 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1376 vss sub ptap1 A=4e-12 P=8e-6 -MM20_22 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1377 vss sub ptap1 A=4e-12 P=8e-6 -MM20_23 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1378 vss sub ptap1 A=4e-12 P=8e-6 -MM20_24 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1379 vss sub ptap1 A=4e-12 P=8e-6 -MM20_25 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1380 vss sub ptap1 A=4e-12 P=8e-6 -MM20_26 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1381 vss sub ptap1 A=4e-12 P=8e-6 -MM20_27 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1382 vss sub ptap1 A=4e-12 P=8e-6 -MM20_28 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1383 vss sub ptap1 A=4e-12 P=8e-6 -MM20_29 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1384 vss sub ptap1 A=4e-12 P=8e-6 -MM20_30 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1385 vss sub ptap1 A=4e-12 P=8e-6 -MM20_31 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1386 vss sub ptap1 A=4e-12 P=8e-6 -MM20_32 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1387 vss sub ptap1 A=4e-12 P=8e-6 -MM20_33 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1388 vss sub ptap1 A=4e-12 P=8e-6 -MM20_34 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1389 vss sub ptap1 A=4e-12 P=8e-6 -MM20_35 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1390 vss sub ptap1 A=4e-12 P=8e-6 -MM20_36 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1391 vss sub ptap1 A=4e-12 P=8e-6 -MM20_37 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1392 vss sub ptap1 A=4e-12 P=8e-6 -MM20_38 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1393 vss sub ptap1 A=4e-12 P=8e-6 -MM20_39 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1394 vss sub ptap1 A=4e-12 P=8e-6 -MM20_40 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1395 vss sub ptap1 A=4e-12 P=8e-6 -MM20_41 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1396 vss sub ptap1 A=4e-12 P=8e-6 -MM20_42 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1397 vss sub ptap1 A=4e-12 P=8e-6 -MM20_43 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1398 vss sub ptap1 A=4e-12 P=8e-6 -MM20_44 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1399 vss sub ptap1 A=4e-12 P=8e-6 -MM20_45 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1400 vss sub ptap1 A=4e-12 P=8e-6 -MM20_46 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1401 vss sub ptap1 A=4e-12 P=8e-6 -MM20_47 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1402 vss sub ptap1 A=4e-12 P=8e-6 -MM20_48 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1403 vss sub ptap1 A=4e-12 P=8e-6 -MM20_49 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1404 vss sub ptap1 A=4e-12 P=8e-6 -MM20_50 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1405 vss sub ptap1 A=4e-12 P=8e-6 -MM20_51 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1406 vss sub ptap1 A=4e-12 P=8e-6 -MM20_52 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1407 vss sub ptap1 A=4e-12 P=8e-6 -MM20_53 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1408 vss sub ptap1 A=4e-12 P=8e-6 -MM20_54 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1409 vss sub ptap1 A=4e-12 P=8e-6 -MM20_55 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1410 vss sub ptap1 A=4e-12 P=8e-6 -MM20_56 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1411 vss sub ptap1 A=4e-12 P=8e-6 -MM20_57 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1412 vss sub ptap1 A=4e-12 P=8e-6 -MM20_58 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1413 vss sub ptap1 A=4e-12 P=8e-6 -MM20_59 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1414 vss sub ptap1 A=4e-12 P=8e-6 -MM20_60 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1415 vss sub ptap1 A=4e-12 P=8e-6 -MM20_61 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1416 vss sub ptap1 A=4e-12 P=8e-6 -MM20_62 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1417 vss sub ptap1 A=4e-12 P=8e-6 -MM20_63 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1418 vss sub ptap1 A=4e-12 P=8e-6 -MM20_64 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1419 vss sub ptap1 A=4e-12 P=8e-6 -MM20_65 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1420 vss sub ptap1 A=4e-12 P=8e-6 -MM20_66 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1421 vss sub ptap1 A=4e-12 P=8e-6 -MM20_67 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1422 vss sub ptap1 A=4e-12 P=8e-6 -MM20_68 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1423 vss sub ptap1 A=4e-12 P=8e-6 -MM20_69 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1424 vss sub ptap1 A=4e-12 P=8e-6 -MM20_70 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1425 vss sub ptap1 A=4e-12 P=8e-6 -MM20_71 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1426 vss sub ptap1 A=4e-12 P=8e-6 -MM20_72 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1427 vss sub ptap1 A=4e-12 P=8e-6 -MM20_73 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1428 vss sub ptap1 A=4e-12 P=8e-6 -MM20_74 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1429 vss sub ptap1 A=4e-12 P=8e-6 -MM20_75 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1430 vss sub ptap1 A=4e-12 P=8e-6 -MM20_76 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1431 vss sub ptap1 A=4e-12 P=8e-6 -MM20_77 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1432 vss sub ptap1 A=4e-12 P=8e-6 -MM20_78 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1433 vss sub ptap1 A=4e-12 P=8e-6 -MM20_79 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1434 vss sub ptap1 A=4e-12 P=8e-6 -MM20_80 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1435 vss sub ptap1 A=4e-12 P=8e-6 -MM20_81 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1436 vss sub ptap1 A=4e-12 P=8e-6 -MM20_82 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1437 vss sub ptap1 A=4e-12 P=8e-6 -MM20_83 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1438 vss sub ptap1 A=4e-12 P=8e-6 -MM20_84 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1439 vss sub ptap1 A=4e-12 P=8e-6 -MM20_85 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1440 vss sub ptap1 A=4e-12 P=8e-6 -MM20_86 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1441 vss sub ptap1 A=4e-12 P=8e-6 -MM20_87 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1442 vss sub ptap1 A=4e-12 P=8e-6 -MM20_88 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1443 vss sub ptap1 A=4e-12 P=8e-6 -MM20_89 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1444 vss sub ptap1 A=4e-12 P=8e-6 -MM20_90 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1445 vss sub ptap1 A=4e-12 P=8e-6 -MM20_91 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1446 vss sub ptap1 A=4e-12 P=8e-6 -MM20_92 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1447 vss sub ptap1 A=4e-12 P=8e-6 -MM20_93 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1448 vss sub ptap1 A=4e-12 P=8e-6 -MM20_94 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1449 vss sub ptap1 A=4e-12 P=8e-6 -MM20_95 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1450 vss sub ptap1 A=4e-12 P=8e-6 -MM20_96 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1451 vss sub ptap1 A=4e-12 P=8e-6 -MM20_97 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1452 vss sub ptap1 A=4e-12 P=8e-6 -MM20_98 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1453 vss sub ptap1 A=4e-12 P=8e-6 -MM20_99 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1454 vss sub ptap1 A=4e-12 P=8e-6 -MM20_100 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1455 vss sub ptap1 A=4e-12 P=8e-6 -MM20_101 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1456 vss sub ptap1 A=4e-12 P=8e-6 -MM20_102 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1457 vss sub ptap1 A=4e-12 P=8e-6 -MM20_103 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1458 vss sub ptap1 A=4e-12 P=8e-6 -MM20_104 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1459 vss sub ptap1 A=4e-12 P=8e-6 -MM20_105 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1460 vss sub ptap1 A=4e-12 P=8e-6 -MM20_106 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1461 vss sub ptap1 A=4e-12 P=8e-6 -MM20_107 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1462 vss sub ptap1 A=4e-12 P=8e-6 -MM20_108 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1463 vss sub ptap1 A=4e-12 P=8e-6 -MM20_109 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1464 vss sub ptap1 A=4e-12 P=8e-6 -MM20_110 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1465 vss sub ptap1 A=4e-12 P=8e-6 -MM20_111 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1466 vss sub ptap1 A=4e-12 P=8e-6 -MM20_112 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1467 vss sub ptap1 A=4e-12 P=8e-6 -MM20_113 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1468 vss sub ptap1 A=4e-12 P=8e-6 -MM20_114 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1469 vss sub ptap1 A=4e-12 P=8e-6 -MM20_115 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1470 vss sub ptap1 A=4e-12 P=8e-6 -MM20_116 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1471 vss sub ptap1 A=4e-12 P=8e-6 -MM20_117 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1472 vss sub ptap1 A=4e-12 P=8e-6 -MM20_118 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1473 vss sub ptap1 A=4e-12 P=8e-6 -MM20_119 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1474 vss sub ptap1 A=4e-12 P=8e-6 -MM20_120 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1475 vss sub ptap1 A=4e-12 P=8e-6 -MM20_121 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1476 vss sub ptap1 A=4e-12 P=8e-6 -MM20_122 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1477 vss sub ptap1 A=4e-12 P=8e-6 -MM20_123 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1478 vss sub ptap1 A=4e-12 P=8e-6 -MM20_124 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1479 vss sub ptap1 A=4e-12 P=8e-6 -MM20_125 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1480 vss sub ptap1 A=4e-12 P=8e-6 -MM20_126 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1481 vss sub ptap1 A=4e-12 P=8e-6 -MM20_127 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1482 vss sub ptap1 A=4e-12 P=8e-6 -MM20_128 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1483 vss sub ptap1 A=4e-12 P=8e-6 -MM20_129 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1484 vss sub ptap1 A=4e-12 P=8e-6 -MM20_130 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1485 vss sub ptap1 A=4e-12 P=8e-6 -MM20_131 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1486 vss sub ptap1 A=4e-12 P=8e-6 -MM20_132 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1487 vss sub ptap1 A=4e-12 P=8e-6 -MM20_133 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1488 vss sub ptap1 A=4e-12 P=8e-6 -MM20_134 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1489 vss sub ptap1 A=4e-12 P=8e-6 -MM20_135 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1490 vss sub ptap1 A=4e-12 P=8e-6 -MM20_136 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1491 vss sub ptap1 A=4e-12 P=8e-6 -MM20_137 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1492 vss sub ptap1 A=4e-12 P=8e-6 -MM20_138 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1493 vss sub ptap1 A=4e-12 P=8e-6 -MM20_139 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1494 vss sub ptap1 A=4e-12 P=8e-6 -MM20_140 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1495 vss sub ptap1 A=4e-12 P=8e-6 -MM20_141 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1496 vss sub ptap1 A=4e-12 P=8e-6 -MM20_142 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1497 vss sub ptap1 A=4e-12 P=8e-6 -MM20_143 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1498 vss sub ptap1 A=4e-12 P=8e-6 -MM20_144 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1499 vss sub ptap1 A=4e-12 P=8e-6 -MM20_145 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1500 vss sub ptap1 A=4e-12 P=8e-6 -MM20_146 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1501 vss sub ptap1 A=4e-12 P=8e-6 -MM20_147 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1502 vss sub ptap1 A=4e-12 P=8e-6 -MM20_148 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1503 vss sub ptap1 A=4e-12 P=8e-6 -MM20_149 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1504 vss sub ptap1 A=4e-12 P=8e-6 -MM20_150 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1505 vss sub ptap1 A=4e-12 P=8e-6 -MM20_151 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1506 vss sub ptap1 A=4e-12 P=8e-6 -MM20_152 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1507 vss sub ptap1 A=4e-12 P=8e-6 -MM20_153 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1508 vss sub ptap1 A=4e-12 P=8e-6 -MM20_154 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1509 vss sub ptap1 A=4e-12 P=8e-6 -MM20_155 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1510 vss sub ptap1 A=4e-12 P=8e-6 -MM20_156 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1511 vss sub ptap1 A=4e-12 P=8e-6 -MM20_157 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1512 vss sub ptap1 A=4e-12 P=8e-6 -MM20_158 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1513 vss sub ptap1 A=4e-12 P=8e-6 -MM20_159 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1514 vss sub ptap1 A=4e-12 P=8e-6 -MM21 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1515 vss sub ptap1 A=4e-12 P=8e-6 -MM22 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1516 vss sub ptap1 A=4e-12 P=8e-6 -MM23_0 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1517 vss sub ptap1 A=4e-12 P=8e-6 -MM23_1 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1518 vss sub ptap1 A=4e-12 P=8e-6 -MM23_2 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1519 vss sub ptap1 A=4e-12 P=8e-6 -MM23_3 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1520 vss sub ptap1 A=4e-12 P=8e-6 -MM23_4 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1521 vss sub ptap1 A=4e-12 P=8e-6 -MM23_5 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1522 vss sub ptap1 A=4e-12 P=8e-6 -MM23_6 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1523 vss sub ptap1 A=4e-12 P=8e-6 -MM23_7 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1524 vss sub ptap1 A=4e-12 P=8e-6 -MM23_8 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1525 vss sub ptap1 A=4e-12 P=8e-6 -MM23_9 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1526 vss sub ptap1 A=4e-12 P=8e-6 -MM23_10 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1527 vss sub ptap1 A=4e-12 P=8e-6 -MM23_11 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1528 vss sub ptap1 A=4e-12 P=8e-6 -MM23_12 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1529 vss sub ptap1 A=4e-12 P=8e-6 -MM23_13 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1530 vss sub ptap1 A=4e-12 P=8e-6 -MM23_14 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1531 vss sub ptap1 A=4e-12 P=8e-6 -MM23_15 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1532 vss sub ptap1 A=4e-12 P=8e-6 -MM23_16 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1533 vss sub ptap1 A=4e-12 P=8e-6 -MM23_17 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1534 vss sub ptap1 A=4e-12 P=8e-6 -MM23_18 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1535 vss sub ptap1 A=4e-12 P=8e-6 -MM23_19 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1536 vss sub ptap1 A=4e-12 P=8e-6 -MM23_20 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1537 vss sub ptap1 A=4e-12 P=8e-6 -MM23_21 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1538 vss sub ptap1 A=4e-12 P=8e-6 -MM23_22 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1539 vss sub ptap1 A=4e-12 P=8e-6 -MM23_23 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1540 vss sub ptap1 A=4e-12 P=8e-6 -MM23_24 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1541 vss sub ptap1 A=4e-12 P=8e-6 -MM23_25 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1542 vss sub ptap1 A=4e-12 P=8e-6 -MM23_26 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1543 vss sub ptap1 A=4e-12 P=8e-6 -MM23_27 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1544 vss sub ptap1 A=4e-12 P=8e-6 -MM23_28 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1545 vss sub ptap1 A=4e-12 P=8e-6 -MM23_29 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1546 vss sub ptap1 A=4e-12 P=8e-6 -MM23_30 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1547 vss sub ptap1 A=4e-12 P=8e-6 -MM23_31 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1548 vss sub ptap1 A=4e-12 P=8e-6 -MM23_32 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1549 vss sub ptap1 A=4e-12 P=8e-6 -MM23_33 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1550 vss sub ptap1 A=4e-12 P=8e-6 -MM23_34 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1551 vss sub ptap1 A=4e-12 P=8e-6 -MM23_35 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1552 vss sub ptap1 A=4e-12 P=8e-6 -MM23_36 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1553 vss sub ptap1 A=4e-12 P=8e-6 -MM23_37 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1554 vss sub ptap1 A=4e-12 P=8e-6 -MM23_38 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1555 vss sub ptap1 A=4e-12 P=8e-6 -MM23_39 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1556 vss sub ptap1 A=4e-12 P=8e-6 -MM23_40 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1557 vss sub ptap1 A=4e-12 P=8e-6 -MM23_41 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1558 vss sub ptap1 A=4e-12 P=8e-6 -MM23_42 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1559 vss sub ptap1 A=4e-12 P=8e-6 -MM23_43 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1560 vss sub ptap1 A=4e-12 P=8e-6 -MM23_44 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1561 vss sub ptap1 A=4e-12 P=8e-6 -MM23_45 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1562 vss sub ptap1 A=4e-12 P=8e-6 -MM23_46 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1563 vss sub ptap1 A=4e-12 P=8e-6 -MM23_47 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1564 vss sub ptap1 A=4e-12 P=8e-6 -MM23_48 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1565 vss sub ptap1 A=4e-12 P=8e-6 -MM23_49 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1566 vss sub ptap1 A=4e-12 P=8e-6 -MM23_50 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1567 vss sub ptap1 A=4e-12 P=8e-6 -MM23_51 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1568 vss sub ptap1 A=4e-12 P=8e-6 -MM23_52 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1569 vss sub ptap1 A=4e-12 P=8e-6 -MM23_53 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1570 vss sub ptap1 A=4e-12 P=8e-6 -MM23_54 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1571 vss sub ptap1 A=4e-12 P=8e-6 -MM23_55 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1572 vss sub ptap1 A=4e-12 P=8e-6 -MM23_56 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1573 vss sub ptap1 A=4e-12 P=8e-6 -MM23_57 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1574 vss sub ptap1 A=4e-12 P=8e-6 -MM23_58 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1575 vss sub ptap1 A=4e-12 P=8e-6 -MM23_59 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1576 vss sub ptap1 A=4e-12 P=8e-6 -MM23_60 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1577 vss sub ptap1 A=4e-12 P=8e-6 -MM23_61 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1578 vss sub ptap1 A=4e-12 P=8e-6 -MM23_62 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1579 vss sub ptap1 A=4e-12 P=8e-6 -MM23_63 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1580 vss sub ptap1 A=4e-12 P=8e-6 -MM23_64 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1581 vss sub ptap1 A=4e-12 P=8e-6 -MM23_65 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1582 vss sub ptap1 A=4e-12 P=8e-6 -MM23_66 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1583 vss sub ptap1 A=4e-12 P=8e-6 -MM23_67 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1584 vss sub ptap1 A=4e-12 P=8e-6 -MM23_68 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1585 vss sub ptap1 A=4e-12 P=8e-6 -MM23_69 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1586 vss sub ptap1 A=4e-12 P=8e-6 -MM23_70 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1587 vss sub ptap1 A=4e-12 P=8e-6 -MM23_71 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1588 vss sub ptap1 A=4e-12 P=8e-6 -MM23_72 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1589 vss sub ptap1 A=4e-12 P=8e-6 -MM23_73 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1590 vss sub ptap1 A=4e-12 P=8e-6 -MM23_74 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1591 vss sub ptap1 A=4e-12 P=8e-6 -MM23_75 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1592 vss sub ptap1 A=4e-12 P=8e-6 -MM23_76 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1593 vss sub ptap1 A=4e-12 P=8e-6 -MM23_77 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1594 vss sub ptap1 A=4e-12 P=8e-6 -MM23_78 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1595 vss sub ptap1 A=4e-12 P=8e-6 -MM23_79 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1596 vss sub ptap1 A=4e-12 P=8e-6 -MM23_80 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1597 vss sub ptap1 A=4e-12 P=8e-6 -MM23_81 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1598 vss sub ptap1 A=4e-12 P=8e-6 -MM23_82 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1599 vss sub ptap1 A=4e-12 P=8e-6 -MM23_83 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1600 vss sub ptap1 A=4e-12 P=8e-6 -MM23_84 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1601 vss sub ptap1 A=4e-12 P=8e-6 -MM23_85 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1602 vss sub ptap1 A=4e-12 P=8e-6 -MM23_86 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1603 vss sub ptap1 A=4e-12 P=8e-6 -MM23_87 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1604 vss sub ptap1 A=4e-12 P=8e-6 -MM23_88 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1605 vss sub ptap1 A=4e-12 P=8e-6 -MM23_89 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1606 vss sub ptap1 A=4e-12 P=8e-6 -MM23_90 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1607 vss sub ptap1 A=4e-12 P=8e-6 -MM23_91 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1608 vss sub ptap1 A=4e-12 P=8e-6 -MM23_92 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1609 vss sub ptap1 A=4e-12 P=8e-6 -MM23_93 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1610 vss sub ptap1 A=4e-12 P=8e-6 -MM23_94 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1611 vss sub ptap1 A=4e-12 P=8e-6 -MM23_95 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1612 vss sub ptap1 A=4e-12 P=8e-6 -MM23_96 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1613 vss sub ptap1 A=4e-12 P=8e-6 -MM23_97 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1614 vss sub ptap1 A=4e-12 P=8e-6 -MM23_98 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1615 vss sub ptap1 A=4e-12 P=8e-6 -MM23_99 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1616 vss sub ptap1 A=4e-12 P=8e-6 -MM23_100 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1617 vss sub ptap1 A=4e-12 P=8e-6 -MM23_101 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1618 vss sub ptap1 A=4e-12 P=8e-6 -MM23_102 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1619 vss sub ptap1 A=4e-12 P=8e-6 -MM23_103 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1620 vss sub ptap1 A=4e-12 P=8e-6 -MM23_104 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1621 vss sub ptap1 A=4e-12 P=8e-6 -MM23_105 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1622 vss sub ptap1 A=4e-12 P=8e-6 -MM23_106 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1623 vss sub ptap1 A=4e-12 P=8e-6 -MM23_107 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1624 vss sub ptap1 A=4e-12 P=8e-6 -MM23_108 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1625 vss sub ptap1 A=4e-12 P=8e-6 -MM23_109 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1626 vss sub ptap1 A=4e-12 P=8e-6 -MM23_110 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1627 vss sub ptap1 A=4e-12 P=8e-6 -MM23_111 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1628 vss sub ptap1 A=4e-12 P=8e-6 -MM23_112 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1629 vss sub ptap1 A=4e-12 P=8e-6 -MM23_113 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1630 vss sub ptap1 A=4e-12 P=8e-6 -MM23_114 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1631 vss sub ptap1 A=4e-12 P=8e-6 -MM23_115 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1632 vss sub ptap1 A=4e-12 P=8e-6 -MM23_116 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1633 vss sub ptap1 A=4e-12 P=8e-6 -MM23_117 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1634 vss sub ptap1 A=4e-12 P=8e-6 -MM23_118 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1635 vss sub ptap1 A=4e-12 P=8e-6 -MM23_119 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1636 vss sub ptap1 A=4e-12 P=8e-6 -MM23_120 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1637 vss sub ptap1 A=4e-12 P=8e-6 -MM23_121 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1638 vss sub ptap1 A=4e-12 P=8e-6 -MM23_122 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1639 vss sub ptap1 A=4e-12 P=8e-6 -MM23_123 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1640 vss sub ptap1 A=4e-12 P=8e-6 -MM23_124 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1641 vss sub ptap1 A=4e-12 P=8e-6 -MM23_125 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1642 vss sub ptap1 A=4e-12 P=8e-6 -MM23_126 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1643 vss sub ptap1 A=4e-12 P=8e-6 -MM23_127 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1644 vss sub ptap1 A=4e-12 P=8e-6 -MM23_128 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1645 vss sub ptap1 A=4e-12 P=8e-6 -MM23_129 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1646 vss sub ptap1 A=4e-12 P=8e-6 -MM23_130 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1647 vss sub ptap1 A=4e-12 P=8e-6 -MM23_131 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1648 vss sub ptap1 A=4e-12 P=8e-6 -MM23_132 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1649 vss sub ptap1 A=4e-12 P=8e-6 -MM23_133 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1650 vss sub ptap1 A=4e-12 P=8e-6 -MM23_134 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1651 vss sub ptap1 A=4e-12 P=8e-6 -MM23_135 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1652 vss sub ptap1 A=4e-12 P=8e-6 -MM23_136 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1653 vss sub ptap1 A=4e-12 P=8e-6 -MM23_137 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1654 vss sub ptap1 A=4e-12 P=8e-6 -MM23_138 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1655 vss sub ptap1 A=4e-12 P=8e-6 -MM23_139 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1656 vss sub ptap1 A=4e-12 P=8e-6 -MM23_140 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1657 vss sub ptap1 A=4e-12 P=8e-6 -MM23_141 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1658 vss sub ptap1 A=4e-12 P=8e-6 -MM23_142 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1659 vss sub ptap1 A=4e-12 P=8e-6 -MM23_143 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1660 vss sub ptap1 A=4e-12 P=8e-6 -MM23_144 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1661 vss sub ptap1 A=4e-12 P=8e-6 -MM23_145 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1662 vss sub ptap1 A=4e-12 P=8e-6 -MM23_146 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1663 vss sub ptap1 A=4e-12 P=8e-6 -MM23_147 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1664 vss sub ptap1 A=4e-12 P=8e-6 -MM23_148 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1665 vss sub ptap1 A=4e-12 P=8e-6 -MM23_149 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1666 vss sub ptap1 A=4e-12 P=8e-6 -MM23_150 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1667 vss sub ptap1 A=4e-12 P=8e-6 -MM23_151 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1668 vss sub ptap1 A=4e-12 P=8e-6 -MM23_152 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1669 vss sub ptap1 A=4e-12 P=8e-6 -MM23_153 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1670 vss sub ptap1 A=4e-12 P=8e-6 -MM23_154 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1671 vss sub ptap1 A=4e-12 P=8e-6 -MM23_155 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1672 vss sub ptap1 A=4e-12 P=8e-6 -MM23_156 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1673 vss sub ptap1 A=4e-12 P=8e-6 -MM23_157 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1674 vss sub ptap1 A=4e-12 P=8e-6 -MM23_158 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1675 vss sub ptap1 A=4e-12 P=8e-6 -MM23_159 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1676 vss sub ptap1 A=4e-12 P=8e-6 -MM23_160 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1677 vss sub ptap1 A=4e-12 P=8e-6 -MM23_161 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1678 vss sub ptap1 A=4e-12 P=8e-6 -MM23_162 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1679 vss sub ptap1 A=4e-12 P=8e-6 -MM23_163 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1680 vss sub ptap1 A=4e-12 P=8e-6 -MM23_164 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1681 vss sub ptap1 A=4e-12 P=8e-6 -MM23_165 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1682 vss sub ptap1 A=4e-12 P=8e-6 -MM23_166 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1683 vss sub ptap1 A=4e-12 P=8e-6 -MM23_167 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1684 vss sub ptap1 A=4e-12 P=8e-6 -MM23_168 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1685 vss sub ptap1 A=4e-12 P=8e-6 -MM23_169 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1686 vss sub ptap1 A=4e-12 P=8e-6 -MM23_170 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1687 vss sub ptap1 A=4e-12 P=8e-6 -MM23_171 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1688 vss sub ptap1 A=4e-12 P=8e-6 -MM23_172 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1689 vss sub ptap1 A=4e-12 P=8e-6 -MM23_173 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1690 vss sub ptap1 A=4e-12 P=8e-6 -MM23_174 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1691 vss sub ptap1 A=4e-12 P=8e-6 -MM23_175 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1692 vss sub ptap1 A=4e-12 P=8e-6 -MM23_176 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1693 vss sub ptap1 A=4e-12 P=8e-6 -MM23_177 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1694 vss sub ptap1 A=4e-12 P=8e-6 -MM23_178 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1695 vss sub ptap1 A=4e-12 P=8e-6 -MM23_179 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1696 vss sub ptap1 A=4e-12 P=8e-6 -MM23_180 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1697 vss sub ptap1 A=4e-12 P=8e-6 -MM23_181 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1698 vss sub ptap1 A=4e-12 P=8e-6 -MM23_182 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1699 vss sub ptap1 A=4e-12 P=8e-6 -MM23_183 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1700 vss sub ptap1 A=4e-12 P=8e-6 -MM23_184 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1701 vss sub ptap1 A=4e-12 P=8e-6 -MM23_185 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1702 vss sub ptap1 A=4e-12 P=8e-6 -MM23_186 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1703 vss sub ptap1 A=4e-12 P=8e-6 -MM23_187 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1704 vss sub ptap1 A=4e-12 P=8e-6 -MM23_188 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1705 vss sub ptap1 A=4e-12 P=8e-6 -MM23_189 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1706 vss sub ptap1 A=4e-12 P=8e-6 -MM23_190 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1707 vss sub ptap1 A=4e-12 P=8e-6 -MM23_191 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1708 vss sub ptap1 A=4e-12 P=8e-6 -MM23_192 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1709 vss sub ptap1 A=4e-12 P=8e-6 -MM23_193 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1710 vss sub ptap1 A=4e-12 P=8e-6 -MM23_194 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1711 vss sub ptap1 A=4e-12 P=8e-6 -MM23_195 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1712 vss sub ptap1 A=4e-12 P=8e-6 -MM23_196 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1713 vss sub ptap1 A=4e-12 P=8e-6 -MM23_197 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1714 vss sub ptap1 A=4e-12 P=8e-6 -MM23_198 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1715 vss sub ptap1 A=4e-12 P=8e-6 -MM23_199 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1716 vss sub ptap1 A=4e-12 P=8e-6 -MM23_200 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1717 vss sub ptap1 A=4e-12 P=8e-6 -MM23_201 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1718 vss sub ptap1 A=4e-12 P=8e-6 -MM23_202 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT1719 vdd well_1719 ntap1 A=4e-12 P=8e-6 -MM3_0 vb3 net1 vdd well_1719 sg13_lv_pmos w=1u l=1u m=1 -RT1720 vdd well_1720 ntap1 A=4e-12 P=8e-6 -MM3_1 vb3 net1 vdd well_1720 sg13_lv_pmos w=1u l=1u m=1 -RT1721 vdd well_1721 ntap1 A=4e-12 P=8e-6 -MM3_2 vb3 net1 vdd well_1721 sg13_lv_pmos w=1u l=1u m=1 -RT1722 vdd well_1722 ntap1 A=4e-12 P=8e-6 -MM3_3 vb3 net1 vdd well_1722 sg13_lv_pmos w=1u l=1u m=1 -RT1723 vdd well_1723 ntap1 A=4e-12 P=8e-6 -MM3_4 vb3 net1 vdd well_1723 sg13_lv_pmos w=1u l=1u m=1 -RT1724 vdd well_1724 ntap1 A=4e-12 P=8e-6 -MM3_5 vb3 net1 vdd well_1724 sg13_lv_pmos w=1u l=1u m=1 -RT1725 vdd well_1725 ntap1 A=4e-12 P=8e-6 -MM3_6 vb3 net1 vdd well_1725 sg13_lv_pmos w=1u l=1u m=1 -RT1726 vdd well_1726 ntap1 A=4e-12 P=8e-6 -MM3_7 vb3 net1 vdd well_1726 sg13_lv_pmos w=1u l=1u m=1 -RT1727 vdd well_1727 ntap1 A=4e-12 P=8e-6 -MM3_8 vb3 net1 vdd well_1727 sg13_lv_pmos w=1u l=1u m=1 -RT1728 vdd well_1728 ntap1 A=4e-12 P=8e-6 -MM3_9 vb3 net1 vdd well_1728 sg13_lv_pmos w=1u l=1u m=1 -RT1729 vdd well_1729 ntap1 A=4e-12 P=8e-6 -MM3_10 vb3 net1 vdd well_1729 sg13_lv_pmos w=1u l=1u m=1 -RT1730 vdd well_1730 ntap1 A=4e-12 P=8e-6 -MM3_11 vb3 net1 vdd well_1730 sg13_lv_pmos w=1u l=1u m=1 -RT1731 vdd well_1731 ntap1 A=4e-12 P=8e-6 -MM3_12 vb3 net1 vdd well_1731 sg13_lv_pmos w=1u l=1u m=1 -RT1732 vdd well_1732 ntap1 A=4e-12 P=8e-6 -MM3_13 vb3 net1 vdd well_1732 sg13_lv_pmos w=1u l=1u m=1 -RT1733 vdd well_1733 ntap1 A=4e-12 P=8e-6 -MM3_14 vb3 net1 vdd well_1733 sg13_lv_pmos w=1u l=1u m=1 -RT1734 vdd well_1734 ntap1 A=4e-12 P=8e-6 -MM3_15 vb3 net1 vdd well_1734 sg13_lv_pmos w=1u l=1u m=1 -RT1735 vdd well_1735 ntap1 A=4e-12 P=8e-6 -MM3_16 vb3 net1 vdd well_1735 sg13_lv_pmos w=1u l=1u m=1 -RT1736 vdd well_1736 ntap1 A=4e-12 P=8e-6 -MM3_17 vb3 net1 vdd well_1736 sg13_lv_pmos w=1u l=1u m=1 -RT1737 vdd well_1737 ntap1 A=4e-12 P=8e-6 -MM3_18 vb3 net1 vdd well_1737 sg13_lv_pmos w=1u l=1u m=1 -RT1738 vdd well_1738 ntap1 A=4e-12 P=8e-6 -MM3_19 vb3 net1 vdd well_1738 sg13_lv_pmos w=1u l=1u m=1 -RT1739 vdd well_1739 ntap1 A=4e-12 P=8e-6 -MM3_20 vb3 net1 vdd well_1739 sg13_lv_pmos w=1u l=1u m=1 -RT1740 vdd well_1740 ntap1 A=4e-12 P=8e-6 -MM3_21 vb3 net1 vdd well_1740 sg13_lv_pmos w=1u l=1u m=1 -RT1741 vdd well_1741 ntap1 A=4e-12 P=8e-6 -MM3_22 vb3 net1 vdd well_1741 sg13_lv_pmos w=1u l=1u m=1 -RT1742 vdd well_1742 ntap1 A=4e-12 P=8e-6 -MM3_23 vb3 net1 vdd well_1742 sg13_lv_pmos w=1u l=1u m=1 -RT1743 vdd well_1743 ntap1 A=4e-12 P=8e-6 -MM3_24 vb3 net1 vdd well_1743 sg13_lv_pmos w=1u l=1u m=1 -RT1744 vdd well_1744 ntap1 A=4e-12 P=8e-6 -MM3_25 vb3 net1 vdd well_1744 sg13_lv_pmos w=1u l=1u m=1 -RT1745 vdd well_1745 ntap1 A=4e-12 P=8e-6 -MM3_26 vb3 net1 vdd well_1745 sg13_lv_pmos w=1u l=1u m=1 -RT1746 vdd well_1746 ntap1 A=4e-12 P=8e-6 -MM3_27 vb3 net1 vdd well_1746 sg13_lv_pmos w=1u l=1u m=1 -RT1747 vdd well_1747 ntap1 A=4e-12 P=8e-6 -MM3_28 vb3 net1 vdd well_1747 sg13_lv_pmos w=1u l=1u m=1 -RT1748 vdd well_1748 ntap1 A=4e-12 P=8e-6 -MM3_29 vb3 net1 vdd well_1748 sg13_lv_pmos w=1u l=1u m=1 -RT1749 vdd well_1749 ntap1 A=4e-12 P=8e-6 -MM3_30 vb3 net1 vdd well_1749 sg13_lv_pmos w=1u l=1u m=1 -RT1750 vdd well_1750 ntap1 A=4e-12 P=8e-6 -MM3_31 vb3 net1 vdd well_1750 sg13_lv_pmos w=1u l=1u m=1 -RT1751 vdd well_1751 ntap1 A=4e-12 P=8e-6 -MM3_32 vb3 net1 vdd well_1751 sg13_lv_pmos w=1u l=1u m=1 -RT1752 vdd well_1752 ntap1 A=4e-12 P=8e-6 -MM3_33 vb3 net1 vdd well_1752 sg13_lv_pmos w=1u l=1u m=1 -RT1753 vdd well_1753 ntap1 A=4e-12 P=8e-6 -MM3_34 vb3 net1 vdd well_1753 sg13_lv_pmos w=1u l=1u m=1 -RT1754 vdd well_1754 ntap1 A=4e-12 P=8e-6 -MM3_35 vb3 net1 vdd well_1754 sg13_lv_pmos w=1u l=1u m=1 -RT1755 vdd well_1755 ntap1 A=4e-12 P=8e-6 -MM3_36 vb3 net1 vdd well_1755 sg13_lv_pmos w=1u l=1u m=1 -RT1756 vdd well_1756 ntap1 A=4e-12 P=8e-6 -MM3_37 vb3 net1 vdd well_1756 sg13_lv_pmos w=1u l=1u m=1 -RT1757 vdd well_1757 ntap1 A=4e-12 P=8e-6 -MM3_38 vb3 net1 vdd well_1757 sg13_lv_pmos w=1u l=1u m=1 -RT1758 vdd well_1758 ntap1 A=4e-12 P=8e-6 -MM3_39 vb3 net1 vdd well_1758 sg13_lv_pmos w=1u l=1u m=1 -RT1759 vdd well_1759 ntap1 A=4e-12 P=8e-6 -MM3_40 vb3 net1 vdd well_1759 sg13_lv_pmos w=1u l=1u m=1 -RT1760 vdd well_1760 ntap1 A=4e-12 P=8e-6 -MM3_41 vb3 net1 vdd well_1760 sg13_lv_pmos w=1u l=1u m=1 -RT1761 vdd well_1761 ntap1 A=4e-12 P=8e-6 -MM3_42 vb3 net1 vdd well_1761 sg13_lv_pmos w=1u l=1u m=1 -RT1762 vdd well_1762 ntap1 A=4e-12 P=8e-6 -MM3_43 vb3 net1 vdd well_1762 sg13_lv_pmos w=1u l=1u m=1 -RT1763 vdd well_1763 ntap1 A=4e-12 P=8e-6 -MM3_44 vb3 net1 vdd well_1763 sg13_lv_pmos w=1u l=1u m=1 -RT1764 vdd well_1764 ntap1 A=4e-12 P=8e-6 -MM3_45 vb3 net1 vdd well_1764 sg13_lv_pmos w=1u l=1u m=1 -RT1765 vdd well_1765 ntap1 A=4e-12 P=8e-6 -MM3_46 vb3 net1 vdd well_1765 sg13_lv_pmos w=1u l=1u m=1 -RT1766 vdd well_1766 ntap1 A=4e-12 P=8e-6 -MM3_47 vb3 net1 vdd well_1766 sg13_lv_pmos w=1u l=1u m=1 -RT1767 vdd well_1767 ntap1 A=4e-12 P=8e-6 -MM3_48 vb3 net1 vdd well_1767 sg13_lv_pmos w=1u l=1u m=1 -RT1768 vdd well_1768 ntap1 A=4e-12 P=8e-6 -MM3_49 vb3 net1 vdd well_1768 sg13_lv_pmos w=1u l=1u m=1 -RT1769 vdd well_1769 ntap1 A=4e-12 P=8e-6 -MM3_50 vb3 net1 vdd well_1769 sg13_lv_pmos w=1u l=1u m=1 -RT1770 vdd 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-RT1780 vdd well_1780 ntap1 A=4e-12 P=8e-6 -MM3_61 vb3 net1 vdd well_1780 sg13_lv_pmos w=1u l=1u m=1 -RT1781 vdd well_1781 ntap1 A=4e-12 P=8e-6 -MM3_62 vb3 net1 vdd well_1781 sg13_lv_pmos w=1u l=1u m=1 -RT1782 vdd well_1782 ntap1 A=4e-12 P=8e-6 -MM3_63 vb3 net1 vdd well_1782 sg13_lv_pmos w=1u l=1u m=1 -RT1783 vdd well_1783 ntap1 A=4e-12 P=8e-6 -MM3_64 vb3 net1 vdd well_1783 sg13_lv_pmos w=1u l=1u m=1 -RT1784 vdd well_1784 ntap1 A=4e-12 P=8e-6 -MM3_65 vb3 net1 vdd well_1784 sg13_lv_pmos w=1u l=1u m=1 -RT1785 vdd well_1785 ntap1 A=4e-12 P=8e-6 -MM3_66 vb3 net1 vdd well_1785 sg13_lv_pmos w=1u l=1u m=1 -RT1786 vdd well_1786 ntap1 A=4e-12 P=8e-6 -MM3_67 vb3 net1 vdd well_1786 sg13_lv_pmos w=1u l=1u m=1 -RT1787 vdd well_1787 ntap1 A=4e-12 P=8e-6 -MM3_68 vb3 net1 vdd well_1787 sg13_lv_pmos w=1u l=1u m=1 -RT1788 vdd well_1788 ntap1 A=4e-12 P=8e-6 -MM3_69 vb3 net1 vdd well_1788 sg13_lv_pmos w=1u l=1u m=1 -RT1789 vdd well_1789 ntap1 A=4e-12 P=8e-6 -MM3_70 vb3 net1 vdd well_1789 sg13_lv_pmos w=1u l=1u m=1 -RT1790 vdd well_1790 ntap1 A=4e-12 P=8e-6 -MM4_0 net31 net1 vdd well_1790 sg13_lv_pmos w=1u l=1u m=1 -RT1791 vdd well_1791 ntap1 A=4e-12 P=8e-6 -MM4_1 net31 net1 vdd well_1791 sg13_lv_pmos w=1u l=1u m=1 -RT1792 vdd well_1792 ntap1 A=4e-12 P=8e-6 -MM4_2 net31 net1 vdd well_1792 sg13_lv_pmos w=1u l=1u m=1 -RT1793 vdd well_1793 ntap1 A=4e-12 P=8e-6 -MM4_3 net31 net1 vdd well_1793 sg13_lv_pmos w=1u l=1u m=1 -RT1794 vdd well_1794 ntap1 A=4e-12 P=8e-6 -MM4_4 net31 net1 vdd well_1794 sg13_lv_pmos w=1u l=1u m=1 -RT1795 vdd well_1795 ntap1 A=4e-12 P=8e-6 -MM4_5 net31 net1 vdd well_1795 sg13_lv_pmos w=1u l=1u m=1 -RT1796 vdd well_1796 ntap1 A=4e-12 P=8e-6 -MM4_6 net31 net1 vdd well_1796 sg13_lv_pmos w=1u l=1u m=1 -RT1797 vdd well_1797 ntap1 A=4e-12 P=8e-6 -MM4_7 net31 net1 vdd well_1797 sg13_lv_pmos w=1u l=1u m=1 -RT1798 vdd well_1798 ntap1 A=4e-12 P=8e-6 -MM4_8 net31 net1 vdd well_1798 sg13_lv_pmos w=1u l=1u m=1 -RT1799 vdd well_1799 ntap1 A=4e-12 P=8e-6 -MM4_9 net31 net1 vdd well_1799 sg13_lv_pmos w=1u l=1u m=1 -RT1800 vdd well_1800 ntap1 A=4e-12 P=8e-6 -MM4_10 net31 net1 vdd well_1800 sg13_lv_pmos w=1u l=1u m=1 -RT1801 vdd well_1801 ntap1 A=4e-12 P=8e-6 -MM4_11 net31 net1 vdd well_1801 sg13_lv_pmos w=1u l=1u m=1 -RT1802 vdd well_1802 ntap1 A=4e-12 P=8e-6 -MM4_12 net31 net1 vdd well_1802 sg13_lv_pmos w=1u l=1u m=1 -RT1803 vdd well_1803 ntap1 A=4e-12 P=8e-6 -MM4_13 net31 net1 vdd well_1803 sg13_lv_pmos w=1u l=1u m=1 -RT1804 vdd well_1804 ntap1 A=4e-12 P=8e-6 -MM4_14 net31 net1 vdd well_1804 sg13_lv_pmos w=1u l=1u m=1 -RT1805 vdd well_1805 ntap1 A=4e-12 P=8e-6 -MM4_15 net31 net1 vdd well_1805 sg13_lv_pmos w=1u l=1u m=1 -RT1806 vdd well_1806 ntap1 A=4e-12 P=8e-6 -MM4_16 net31 net1 vdd well_1806 sg13_lv_pmos w=1u l=1u m=1 -RT1807 vdd well_1807 ntap1 A=4e-12 P=8e-6 -MM4_17 net31 net1 vdd well_1807 sg13_lv_pmos w=1u l=1u m=1 -RT1808 vdd well_1808 ntap1 A=4e-12 P=8e-6 -MM4_18 net31 net1 vdd well_1808 sg13_lv_pmos w=1u l=1u m=1 -RT1809 vdd well_1809 ntap1 A=4e-12 P=8e-6 -MM4_19 net31 net1 vdd well_1809 sg13_lv_pmos w=1u l=1u m=1 -RT1810 vdd well_1810 ntap1 A=4e-12 P=8e-6 -MM4_20 net31 net1 vdd well_1810 sg13_lv_pmos w=1u l=1u m=1 -RT1811 vdd well_1811 ntap1 A=4e-12 P=8e-6 -MM4_21 net31 net1 vdd well_1811 sg13_lv_pmos w=1u l=1u m=1 -RT1812 vdd well_1812 ntap1 A=4e-12 P=8e-6 -MM4_22 net31 net1 vdd well_1812 sg13_lv_pmos w=1u l=1u m=1 -RT1813 vdd well_1813 ntap1 A=4e-12 P=8e-6 -MM4_23 net31 net1 vdd well_1813 sg13_lv_pmos w=1u l=1u m=1 -RT1814 vdd well_1814 ntap1 A=4e-12 P=8e-6 -MM4_24 net31 net1 vdd well_1814 sg13_lv_pmos w=1u l=1u m=1 -RT1815 vdd well_1815 ntap1 A=4e-12 P=8e-6 -MM4_25 net31 net1 vdd well_1815 sg13_lv_pmos w=1u l=1u m=1 -RT1816 vdd well_1816 ntap1 A=4e-12 P=8e-6 -MM4_26 net31 net1 vdd well_1816 sg13_lv_pmos w=1u l=1u m=1 -RT1817 vdd well_1817 ntap1 A=4e-12 P=8e-6 -MM4_27 net31 net1 vdd well_1817 sg13_lv_pmos w=1u l=1u m=1 -RT1818 vdd well_1818 ntap1 A=4e-12 P=8e-6 -MM4_28 net31 net1 vdd well_1818 sg13_lv_pmos w=1u l=1u m=1 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vinp net31 well_2550 sg13_lv_pmos w=1u l=1u m=1 -RT2551 net31 well_2551 ntap1 A=4e-12 P=8e-6 -MM9_116 net063 vinp net31 well_2551 sg13_lv_pmos w=1u l=1u m=1 -RT2552 net31 well_2552 ntap1 A=4e-12 P=8e-6 -MM9_117 net063 vinp net31 well_2552 sg13_lv_pmos w=1u l=1u m=1 -RT2553 net31 well_2553 ntap1 A=4e-12 P=8e-6 -MM9_118 net063 vinp net31 well_2553 sg13_lv_pmos w=1u l=1u m=1 -RT2554 net31 well_2554 ntap1 A=4e-12 P=8e-6 -MM9_119 net063 vinp net31 well_2554 sg13_lv_pmos w=1u l=1u m=1 -RT2555 net31 well_2555 ntap1 A=4e-12 P=8e-6 -MM9_120 net063 vinp net31 well_2555 sg13_lv_pmos w=1u l=1u m=1 -RT2556 net31 well_2556 ntap1 A=4e-12 P=8e-6 -MM9_121 net063 vinp net31 well_2556 sg13_lv_pmos w=1u l=1u m=1 -RT2557 net31 well_2557 ntap1 A=4e-12 P=8e-6 -MM9_122 net063 vinp net31 well_2557 sg13_lv_pmos w=1u l=1u m=1 -RT2558 net31 well_2558 ntap1 A=4e-12 P=8e-6 -MM9_123 net063 vinp net31 well_2558 sg13_lv_pmos w=1u l=1u m=1 -RT2559 net31 well_2559 ntap1 A=4e-12 P=8e-6 -MM9_124 net063 vinp net31 well_2559 sg13_lv_pmos w=1u l=1u m=1 -RT2560 net31 well_2560 ntap1 A=4e-12 P=8e-6 -MM9_125 net063 vinp net31 well_2560 sg13_lv_pmos w=1u l=1u m=1 -RT2561 net31 well_2561 ntap1 A=4e-12 P=8e-6 -MM9_126 net063 vinp net31 well_2561 sg13_lv_pmos w=1u l=1u m=1 -RT2562 net31 well_2562 ntap1 A=4e-12 P=8e-6 -MM9_127 net063 vinp net31 well_2562 sg13_lv_pmos w=1u l=1u m=1 -RT2563 net31 well_2563 ntap1 A=4e-12 P=8e-6 -MM9_128 net063 vinp net31 well_2563 sg13_lv_pmos w=1u l=1u m=1 -RT2564 net31 well_2564 ntap1 A=4e-12 P=8e-6 -MM9_129 net063 vinp net31 well_2564 sg13_lv_pmos w=1u l=1u m=1 -RT2565 net31 well_2565 ntap1 A=4e-12 P=8e-6 -MM9_130 net063 vinp net31 well_2565 sg13_lv_pmos w=1u l=1u m=1 -RT2566 net31 well_2566 ntap1 A=4e-12 P=8e-6 -MM9_131 net063 vinp net31 well_2566 sg13_lv_pmos w=1u l=1u m=1 -RT2567 net31 well_2567 ntap1 A=4e-12 P=8e-6 -MM9_132 net063 vinp net31 well_2567 sg13_lv_pmos w=1u l=1u m=1 -RT2568 net31 well_2568 ntap1 A=4e-12 P=8e-6 -MM9_133 net063 vinp net31 well_2568 sg13_lv_pmos w=1u l=1u m=1 -RT2569 net31 well_2569 ntap1 A=4e-12 P=8e-6 -MM9_134 net063 vinp net31 well_2569 sg13_lv_pmos w=1u l=1u m=1 -RT2570 net31 well_2570 ntap1 A=4e-12 P=8e-6 -MM9_135 net063 vinp net31 well_2570 sg13_lv_pmos w=1u l=1u m=1 -RT2571 net31 well_2571 ntap1 A=4e-12 P=8e-6 -MM9_136 net063 vinp net31 well_2571 sg13_lv_pmos w=1u l=1u m=1 -RT2572 net31 well_2572 ntap1 A=4e-12 P=8e-6 -MM9_137 net063 vinp net31 well_2572 sg13_lv_pmos w=1u l=1u m=1 -RT2573 net31 well_2573 ntap1 A=4e-12 P=8e-6 -MM9_138 net063 vinp net31 well_2573 sg13_lv_pmos w=1u l=1u m=1 -RT2574 net31 well_2574 ntap1 A=4e-12 P=8e-6 -MM9_139 net063 vinp net31 well_2574 sg13_lv_pmos w=1u l=1u m=1 -RT2575 net31 well_2575 ntap1 A=4e-12 P=8e-6 -MM9_140 net063 vinp net31 well_2575 sg13_lv_pmos w=1u l=1u m=1 -RT2576 net31 well_2576 ntap1 A=4e-12 P=8e-6 -MM9_141 net063 vinp net31 well_2576 sg13_lv_pmos w=1u l=1u m=1 -RT2577 net31 well_2577 ntap1 A=4e-12 P=8e-6 -MM9_142 net063 vinp net31 well_2577 sg13_lv_pmos w=1u l=1u m=1 -RT2578 net31 well_2578 ntap1 A=4e-12 P=8e-6 -MM9_143 net063 vinp net31 well_2578 sg13_lv_pmos w=1u l=1u m=1 -RT2579 net31 well_2579 ntap1 A=4e-12 P=8e-6 -MM9_144 net063 vinp net31 well_2579 sg13_lv_pmos w=1u l=1u m=1 -RT2580 net31 well_2580 ntap1 A=4e-12 P=8e-6 -MM9_145 net063 vinp net31 well_2580 sg13_lv_pmos w=1u l=1u m=1 -RT2581 net31 well_2581 ntap1 A=4e-12 P=8e-6 -MM9_146 net063 vinp net31 well_2581 sg13_lv_pmos w=1u l=1u m=1 -RT2582 net31 well_2582 ntap1 A=4e-12 P=8e-6 -MM9_147 net063 vinp net31 well_2582 sg13_lv_pmos w=1u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 -C0_0 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_1 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_2 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_3 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_4 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_5 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_6 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_7 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_8 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_9 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_10 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_11 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_12 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_13 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_14 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C0_15 net050 vout cap_cmim w=51.18u l=51.18u m=1 -C1_0 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -C1_1 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -C1_2 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -C1_3 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -C1_4 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -C1_5 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -C1_6 net050 net049 cap_cmim w=48.74u l=48.74u m=1 +C0 net050 vout cap_cmim w=51.18u l=51.18u m=16 +C1 net050 net049 cap_cmim w=48.74u l=48.74u m=7 +MM0 net1 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM1 vb4 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM10 net043 net050 vdd vdd sg13_lv_pmos w=1u l=1u m=81 +MM11 vout net050 vdd vdd sg13_lv_pmos w=1u l=1u m=400 +MM12 vb4 vb3 net54 vss sg13_lv_nmos w=1u l=1u m=80 +MM13 dm_1 vb3 net56 vss sg13_lv_nmos w=1u l=1u m=80 +MM14 vb3 vb3 vss vss sg13_lv_nmos w=1u l=1u m=20 +MM15 voutn vb3 dm_2 vss sg13_lv_nmos w=1u l=1u m=80 +MM16 net050 vb3 net063 vss sg13_lv_nmos w=1u l=1u m=80 +MM17 net54 vb4 vss vss sg13_lv_nmos w=1u l=1u m=80 +MM18 net56 vb4 vss vss sg13_lv_nmos w=1u l=1u m=80 +MM19 dm_2 vb4 vss vss sg13_lv_nmos w=1u l=1u m=160 +MM2 dm_1 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM20 net063 vb4 vss vss sg13_lv_nmos w=1u l=1u m=160 +MM21 net043 net043 vss vss sg13_lv_nmos w=1u l=1u m=1 +MM22 net049 net043 vss vss sg13_lv_nmos w=1u l=1u m=1 +MM23 vout net049 vss vss sg13_lv_nmos w=1u l=1u m=203 +MM3 vb3 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM4 net31 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=284 +MM5 voutn voutn vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM6 net050 voutn vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM7 net049 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +MM8 dm_2 vinn net31 net31 sg13_lv_pmos w=1u l=1u m=148 +MM9 net063 vinp net31 net31 sg13_lv_pmos w=1u l=1u m=148 .ends amp_014_ramos_pfc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.spice index 7492ed1cd76fee999089e4ecba5b09ca4a923182..f462a2e1b95df9c7ef1418e659d8a90b06a2337f 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.spice @@ -1,5194 +1,30 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Pinned upstream MOS W/L/m and body nets; native MIM binding. .subckt amp_014_ramos_pfc vss vdd vinn vinp vout net1 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM0_0 net1 net1 vdd well_0 sg13_lv_pmos w=1u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM0_1 net1 net1 vdd well_1 sg13_lv_pmos w=1u l=1u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM0_2 net1 net1 vdd well_2 sg13_lv_pmos w=1u l=1u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM0_3 net1 net1 vdd well_3 sg13_lv_pmos w=1u l=1u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM0_4 net1 net1 vdd well_4 sg13_lv_pmos w=1u l=1u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM0_5 net1 net1 vdd well_5 sg13_lv_pmos w=1u l=1u m=1 -XT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -XM0_6 net1 net1 vdd well_6 sg13_lv_pmos w=1u l=1u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM0_7 net1 net1 vdd well_7 sg13_lv_pmos w=1u l=1u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM0_8 net1 net1 vdd well_8 sg13_lv_pmos w=1u l=1u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM0_9 net1 net1 vdd well_9 sg13_lv_pmos w=1u l=1u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM0_10 net1 net1 vdd well_10 sg13_lv_pmos w=1u l=1u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM0_11 net1 net1 vdd well_11 sg13_lv_pmos w=1u l=1u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM0_12 net1 net1 vdd well_12 sg13_lv_pmos w=1u l=1u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM0_13 net1 net1 vdd well_13 sg13_lv_pmos w=1u l=1u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM0_14 net1 net1 vdd well_14 sg13_lv_pmos w=1u l=1u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM0_15 net1 net1 vdd well_15 sg13_lv_pmos w=1u l=1u m=1 -XT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -XM0_16 net1 net1 vdd well_16 sg13_lv_pmos w=1u l=1u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM0_17 net1 net1 vdd well_17 sg13_lv_pmos w=1u l=1u m=1 -XT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -XM0_18 net1 net1 vdd well_18 sg13_lv_pmos w=1u l=1u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM0_19 net1 net1 vdd well_19 sg13_lv_pmos w=1u l=1u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM0_20 net1 net1 vdd well_20 sg13_lv_pmos w=1u l=1u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM0_21 net1 net1 vdd well_21 sg13_lv_pmos w=1u l=1u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM0_22 net1 net1 vdd well_22 sg13_lv_pmos w=1u l=1u m=1 -XT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -XM0_23 net1 net1 vdd well_23 sg13_lv_pmos w=1u l=1u m=1 -XT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -XM0_24 net1 net1 vdd well_24 sg13_lv_pmos w=1u l=1u m=1 -XT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -XM0_25 net1 net1 vdd well_25 sg13_lv_pmos w=1u l=1u m=1 -XT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -XM0_26 net1 net1 vdd well_26 sg13_lv_pmos w=1u l=1u m=1 -XT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -XM0_27 net1 net1 vdd well_27 sg13_lv_pmos w=1u l=1u m=1 -XT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -XM0_28 net1 net1 vdd well_28 sg13_lv_pmos w=1u l=1u m=1 -XT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -XM0_29 net1 net1 vdd well_29 sg13_lv_pmos w=1u l=1u m=1 -XT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -XM0_30 net1 net1 vdd well_30 sg13_lv_pmos w=1u l=1u m=1 -XT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -XM0_31 net1 net1 vdd well_31 sg13_lv_pmos w=1u l=1u m=1 -XT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -XM0_32 net1 net1 vdd well_32 sg13_lv_pmos w=1u l=1u m=1 -XT33 vdd well_33 ntap1 A=4e-12 P=8e-6 -XM0_33 net1 net1 vdd well_33 sg13_lv_pmos w=1u l=1u m=1 -XT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -XM0_34 net1 net1 vdd well_34 sg13_lv_pmos w=1u l=1u m=1 -XT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -XM0_35 net1 net1 vdd well_35 sg13_lv_pmos w=1u l=1u m=1 -XT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -XM0_36 net1 net1 vdd well_36 sg13_lv_pmos w=1u l=1u m=1 -XT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -XM0_37 net1 net1 vdd well_37 sg13_lv_pmos w=1u l=1u m=1 -XT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -XM0_38 net1 net1 vdd well_38 sg13_lv_pmos w=1u l=1u m=1 -XT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -XM0_39 net1 net1 vdd well_39 sg13_lv_pmos w=1u l=1u m=1 -XT40 vdd well_40 ntap1 A=4e-12 P=8e-6 -XM0_40 net1 net1 vdd well_40 sg13_lv_pmos w=1u l=1u m=1 -XT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -XM0_41 net1 net1 vdd well_41 sg13_lv_pmos w=1u l=1u m=1 -XT42 vdd well_42 ntap1 A=4e-12 P=8e-6 -XM0_42 net1 net1 vdd well_42 sg13_lv_pmos w=1u l=1u m=1 -XT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -XM0_43 net1 net1 vdd well_43 sg13_lv_pmos w=1u l=1u m=1 -XT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -XM0_44 net1 net1 vdd well_44 sg13_lv_pmos w=1u l=1u m=1 -XT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -XM0_45 net1 net1 vdd well_45 sg13_lv_pmos w=1u l=1u m=1 -XT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -XM0_46 net1 net1 vdd well_46 sg13_lv_pmos w=1u l=1u m=1 -XT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -XM0_47 net1 net1 vdd well_47 sg13_lv_pmos w=1u l=1u m=1 -XT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -XM0_48 net1 net1 vdd well_48 sg13_lv_pmos w=1u l=1u m=1 -XT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -XM0_49 net1 net1 vdd well_49 sg13_lv_pmos w=1u l=1u m=1 -XT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -XM0_50 net1 net1 vdd well_50 sg13_lv_pmos w=1u l=1u m=1 -XT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -XM0_51 net1 net1 vdd well_51 sg13_lv_pmos w=1u l=1u m=1 -XT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -XM0_52 net1 net1 vdd well_52 sg13_lv_pmos w=1u l=1u m=1 -XT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -XM0_53 net1 net1 vdd well_53 sg13_lv_pmos w=1u l=1u m=1 -XT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -XM0_54 net1 net1 vdd well_54 sg13_lv_pmos w=1u l=1u m=1 -XT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -XM0_55 net1 net1 vdd well_55 sg13_lv_pmos w=1u l=1u m=1 -XT56 vdd well_56 ntap1 A=4e-12 P=8e-6 -XM0_56 net1 net1 vdd well_56 sg13_lv_pmos w=1u l=1u m=1 -XT57 vdd well_57 ntap1 A=4e-12 P=8e-6 -XM0_57 net1 net1 vdd well_57 sg13_lv_pmos w=1u l=1u m=1 -XT58 vdd well_58 ntap1 A=4e-12 P=8e-6 -XM0_58 net1 net1 vdd well_58 sg13_lv_pmos w=1u l=1u m=1 -XT59 vdd well_59 ntap1 A=4e-12 P=8e-6 -XM0_59 net1 net1 vdd well_59 sg13_lv_pmos w=1u l=1u m=1 -XT60 vdd well_60 ntap1 A=4e-12 P=8e-6 -XM0_60 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P=8e-6 -XM10_20 net043 net050 vdd well_162 sg13_lv_pmos w=1u l=1u m=1 -XT163 vdd well_163 ntap1 A=4e-12 P=8e-6 -XM10_21 net043 net050 vdd well_163 sg13_lv_pmos w=1u l=1u m=1 -XT164 vdd well_164 ntap1 A=4e-12 P=8e-6 -XM10_22 net043 net050 vdd well_164 sg13_lv_pmos w=1u l=1u m=1 -XT165 vdd well_165 ntap1 A=4e-12 P=8e-6 -XM10_23 net043 net050 vdd well_165 sg13_lv_pmos w=1u l=1u m=1 -XT166 vdd well_166 ntap1 A=4e-12 P=8e-6 -XM10_24 net043 net050 vdd well_166 sg13_lv_pmos w=1u l=1u m=1 -XT167 vdd well_167 ntap1 A=4e-12 P=8e-6 -XM10_25 net043 net050 vdd well_167 sg13_lv_pmos w=1u l=1u m=1 -XT168 vdd well_168 ntap1 A=4e-12 P=8e-6 -XM10_26 net043 net050 vdd well_168 sg13_lv_pmos w=1u l=1u m=1 -XT169 vdd well_169 ntap1 A=4e-12 P=8e-6 -XM10_27 net043 net050 vdd well_169 sg13_lv_pmos w=1u l=1u m=1 -XT170 vdd well_170 ntap1 A=4e-12 P=8e-6 -XM10_28 net043 net050 vdd well_170 sg13_lv_pmos w=1u l=1u m=1 -XT171 vdd well_171 ntap1 A=4e-12 P=8e-6 -XM10_29 net043 net050 vdd well_171 sg13_lv_pmos w=1u l=1u m=1 -XT172 vdd well_172 ntap1 A=4e-12 P=8e-6 -XM10_30 net043 net050 vdd well_172 sg13_lv_pmos w=1u l=1u m=1 -XT173 vdd well_173 ntap1 A=4e-12 P=8e-6 -XM10_31 net043 net050 vdd well_173 sg13_lv_pmos w=1u l=1u m=1 -XT174 vdd well_174 ntap1 A=4e-12 P=8e-6 -XM10_32 net043 net050 vdd well_174 sg13_lv_pmos w=1u l=1u m=1 -XT175 vdd well_175 ntap1 A=4e-12 P=8e-6 -XM10_33 net043 net050 vdd well_175 sg13_lv_pmos w=1u l=1u m=1 -XT176 vdd well_176 ntap1 A=4e-12 P=8e-6 -XM10_34 net043 net050 vdd well_176 sg13_lv_pmos w=1u l=1u m=1 -XT177 vdd well_177 ntap1 A=4e-12 P=8e-6 -XM10_35 net043 net050 vdd well_177 sg13_lv_pmos w=1u l=1u m=1 -XT178 vdd well_178 ntap1 A=4e-12 P=8e-6 -XM10_36 net043 net050 vdd well_178 sg13_lv_pmos w=1u l=1u m=1 -XT179 vdd well_179 ntap1 A=4e-12 P=8e-6 -XM10_37 net043 net050 vdd well_179 sg13_lv_pmos w=1u l=1u m=1 -XT180 vdd well_180 ntap1 A=4e-12 P=8e-6 -XM10_38 net043 net050 vdd well_180 sg13_lv_pmos w=1u l=1u m=1 -XT181 vdd well_181 ntap1 A=4e-12 P=8e-6 -XM10_39 net043 net050 vdd well_181 sg13_lv_pmos w=1u l=1u m=1 -XT182 vdd well_182 ntap1 A=4e-12 P=8e-6 -XM10_40 net043 net050 vdd well_182 sg13_lv_pmos w=1u l=1u m=1 -XT183 vdd well_183 ntap1 A=4e-12 P=8e-6 -XM10_41 net043 net050 vdd well_183 sg13_lv_pmos w=1u l=1u m=1 -XT184 vdd well_184 ntap1 A=4e-12 P=8e-6 -XM10_42 net043 net050 vdd well_184 sg13_lv_pmos w=1u l=1u m=1 -XT185 vdd well_185 ntap1 A=4e-12 P=8e-6 -XM10_43 net043 net050 vdd well_185 sg13_lv_pmos w=1u l=1u m=1 -XT186 vdd well_186 ntap1 A=4e-12 P=8e-6 -XM10_44 net043 net050 vdd well_186 sg13_lv_pmos w=1u l=1u m=1 -XT187 vdd well_187 ntap1 A=4e-12 P=8e-6 -XM10_45 net043 net050 vdd well_187 sg13_lv_pmos w=1u l=1u m=1 -XT188 vdd well_188 ntap1 A=4e-12 P=8e-6 -XM10_46 net043 net050 vdd well_188 sg13_lv_pmos w=1u l=1u m=1 -XT189 vdd well_189 ntap1 A=4e-12 P=8e-6 -XM10_47 net043 net050 vdd well_189 sg13_lv_pmos w=1u l=1u m=1 -XT190 vdd well_190 ntap1 A=4e-12 P=8e-6 -XM10_48 net043 net050 vdd well_190 sg13_lv_pmos w=1u l=1u m=1 -XT191 vdd well_191 ntap1 A=4e-12 P=8e-6 -XM10_49 net043 net050 vdd well_191 sg13_lv_pmos w=1u l=1u m=1 -XT192 vdd well_192 ntap1 A=4e-12 P=8e-6 -XM10_50 net043 net050 vdd well_192 sg13_lv_pmos w=1u l=1u m=1 -XT193 vdd well_193 ntap1 A=4e-12 P=8e-6 -XM10_51 net043 net050 vdd well_193 sg13_lv_pmos w=1u l=1u m=1 -XT194 vdd well_194 ntap1 A=4e-12 P=8e-6 -XM10_52 net043 net050 vdd well_194 sg13_lv_pmos w=1u l=1u m=1 -XT195 vdd well_195 ntap1 A=4e-12 P=8e-6 -XM10_53 net043 net050 vdd well_195 sg13_lv_pmos w=1u l=1u m=1 -XT196 vdd well_196 ntap1 A=4e-12 P=8e-6 -XM10_54 net043 net050 vdd well_196 sg13_lv_pmos w=1u l=1u m=1 -XT197 vdd well_197 ntap1 A=4e-12 P=8e-6 -XM10_55 net043 net050 vdd well_197 sg13_lv_pmos w=1u l=1u m=1 -XT198 vdd well_198 ntap1 A=4e-12 P=8e-6 -XM10_56 net043 net050 vdd well_198 sg13_lv_pmos w=1u l=1u m=1 -XT199 vdd well_199 ntap1 A=4e-12 P=8e-6 -XM10_57 net043 net050 vdd well_199 sg13_lv_pmos w=1u l=1u m=1 -XT200 vdd well_200 ntap1 A=4e-12 P=8e-6 -XM10_58 net043 net050 vdd well_200 sg13_lv_pmos w=1u l=1u m=1 -XT201 vdd well_201 ntap1 A=4e-12 P=8e-6 -XM10_59 net043 net050 vdd well_201 sg13_lv_pmos w=1u l=1u m=1 -XT202 vdd well_202 ntap1 A=4e-12 P=8e-6 -XM10_60 net043 net050 vdd well_202 sg13_lv_pmos w=1u l=1u m=1 -XT203 vdd well_203 ntap1 A=4e-12 P=8e-6 -XM10_61 net043 net050 vdd well_203 sg13_lv_pmos w=1u l=1u m=1 -XT204 vdd well_204 ntap1 A=4e-12 P=8e-6 -XM10_62 net043 net050 vdd well_204 sg13_lv_pmos w=1u l=1u m=1 -XT205 vdd well_205 ntap1 A=4e-12 P=8e-6 -XM10_63 net043 net050 vdd well_205 sg13_lv_pmos w=1u l=1u m=1 -XT206 vdd well_206 ntap1 A=4e-12 P=8e-6 -XM10_64 net043 net050 vdd well_206 sg13_lv_pmos w=1u l=1u m=1 -XT207 vdd well_207 ntap1 A=4e-12 P=8e-6 -XM10_65 net043 net050 vdd well_207 sg13_lv_pmos w=1u l=1u m=1 -XT208 vdd well_208 ntap1 A=4e-12 P=8e-6 -XM10_66 net043 net050 vdd well_208 sg13_lv_pmos w=1u l=1u m=1 -XT209 vdd well_209 ntap1 A=4e-12 P=8e-6 -XM10_67 net043 net050 vdd well_209 sg13_lv_pmos w=1u l=1u m=1 -XT210 vdd well_210 ntap1 A=4e-12 P=8e-6 -XM10_68 net043 net050 vdd well_210 sg13_lv_pmos w=1u l=1u m=1 -XT211 vdd well_211 ntap1 A=4e-12 P=8e-6 -XM10_69 net043 net050 vdd well_211 sg13_lv_pmos w=1u l=1u m=1 -XT212 vdd well_212 ntap1 A=4e-12 P=8e-6 -XM10_70 net043 net050 vdd well_212 sg13_lv_pmos w=1u l=1u m=1 -XT213 vdd well_213 ntap1 A=4e-12 P=8e-6 -XM10_71 net043 net050 vdd well_213 sg13_lv_pmos w=1u l=1u m=1 -XT214 vdd well_214 ntap1 A=4e-12 P=8e-6 -XM10_72 net043 net050 vdd well_214 sg13_lv_pmos w=1u l=1u m=1 -XT215 vdd well_215 ntap1 A=4e-12 P=8e-6 -XM10_73 net043 net050 vdd well_215 sg13_lv_pmos w=1u l=1u m=1 -XT216 vdd well_216 ntap1 A=4e-12 P=8e-6 -XM10_74 net043 net050 vdd well_216 sg13_lv_pmos w=1u l=1u m=1 -XT217 vdd well_217 ntap1 A=4e-12 P=8e-6 -XM10_75 net043 net050 vdd well_217 sg13_lv_pmos w=1u l=1u m=1 -XT218 vdd well_218 ntap1 A=4e-12 P=8e-6 -XM10_76 net043 net050 vdd well_218 sg13_lv_pmos w=1u l=1u m=1 -XT219 vdd well_219 ntap1 A=4e-12 P=8e-6 -XM10_77 net043 net050 vdd well_219 sg13_lv_pmos w=1u l=1u m=1 -XT220 vdd well_220 ntap1 A=4e-12 P=8e-6 -XM10_78 net043 net050 vdd well_220 sg13_lv_pmos w=1u l=1u m=1 -XT221 vdd well_221 ntap1 A=4e-12 P=8e-6 -XM10_79 net043 net050 vdd well_221 sg13_lv_pmos w=1u l=1u m=1 -XT222 vdd well_222 ntap1 A=4e-12 P=8e-6 -XM10_80 net043 net050 vdd well_222 sg13_lv_pmos w=1u l=1u m=1 -XT223 vdd well_223 ntap1 A=4e-12 P=8e-6 -XM11_0 vout net050 vdd well_223 sg13_lv_pmos w=1u l=1u m=1 -XT224 vdd well_224 ntap1 A=4e-12 P=8e-6 -XM11_1 vout net050 vdd well_224 sg13_lv_pmos w=1u l=1u m=1 -XT225 vdd well_225 ntap1 A=4e-12 P=8e-6 -XM11_2 vout net050 vdd well_225 sg13_lv_pmos w=1u l=1u m=1 -XT226 vdd well_226 ntap1 A=4e-12 P=8e-6 -XM11_3 vout net050 vdd well_226 sg13_lv_pmos w=1u l=1u m=1 -XT227 vdd well_227 ntap1 A=4e-12 P=8e-6 -XM11_4 vout net050 vdd well_227 sg13_lv_pmos w=1u l=1u m=1 -XT228 vdd well_228 ntap1 A=4e-12 P=8e-6 -XM11_5 vout net050 vdd well_228 sg13_lv_pmos w=1u l=1u m=1 -XT229 vdd well_229 ntap1 A=4e-12 P=8e-6 -XM11_6 vout net050 vdd well_229 sg13_lv_pmos w=1u l=1u m=1 -XT230 vdd well_230 ntap1 A=4e-12 P=8e-6 -XM11_7 vout net050 vdd well_230 sg13_lv_pmos w=1u l=1u m=1 -XT231 vdd well_231 ntap1 A=4e-12 P=8e-6 -XM11_8 vout net050 vdd well_231 sg13_lv_pmos w=1u l=1u m=1 -XT232 vdd well_232 ntap1 A=4e-12 P=8e-6 -XM11_9 vout net050 vdd well_232 sg13_lv_pmos w=1u l=1u m=1 -XT233 vdd well_233 ntap1 A=4e-12 P=8e-6 -XM11_10 vout net050 vdd well_233 sg13_lv_pmos w=1u l=1u m=1 -XT234 vdd well_234 ntap1 A=4e-12 P=8e-6 -XM11_11 vout net050 vdd well_234 sg13_lv_pmos w=1u l=1u m=1 -XT235 vdd well_235 ntap1 A=4e-12 P=8e-6 -XM11_12 vout net050 vdd well_235 sg13_lv_pmos w=1u l=1u m=1 -XT236 vdd well_236 ntap1 A=4e-12 P=8e-6 -XM11_13 vout net050 vdd well_236 sg13_lv_pmos w=1u l=1u m=1 -XT237 vdd well_237 ntap1 A=4e-12 P=8e-6 -XM11_14 vout net050 vdd well_237 sg13_lv_pmos w=1u l=1u m=1 -XT238 vdd well_238 ntap1 A=4e-12 P=8e-6 -XM11_15 vout net050 vdd well_238 sg13_lv_pmos w=1u l=1u m=1 -XT239 vdd well_239 ntap1 A=4e-12 P=8e-6 -XM11_16 vout net050 vdd well_239 sg13_lv_pmos w=1u l=1u m=1 -XT240 vdd well_240 ntap1 A=4e-12 P=8e-6 -XM11_17 vout net050 vdd well_240 sg13_lv_pmos w=1u l=1u m=1 -XT241 vdd well_241 ntap1 A=4e-12 P=8e-6 -XM11_18 vout net050 vdd well_241 sg13_lv_pmos w=1u l=1u m=1 -XT242 vdd well_242 ntap1 A=4e-12 P=8e-6 -XM11_19 vout net050 vdd well_242 sg13_lv_pmos w=1u l=1u m=1 -XT243 vdd well_243 ntap1 A=4e-12 P=8e-6 -XM11_20 vout net050 vdd well_243 sg13_lv_pmos w=1u l=1u m=1 -XT244 vdd well_244 ntap1 A=4e-12 P=8e-6 -XM11_21 vout net050 vdd well_244 sg13_lv_pmos w=1u l=1u m=1 -XT245 vdd well_245 ntap1 A=4e-12 P=8e-6 -XM11_22 vout net050 vdd well_245 sg13_lv_pmos w=1u l=1u m=1 -XT246 vdd well_246 ntap1 A=4e-12 P=8e-6 -XM11_23 vout net050 vdd well_246 sg13_lv_pmos w=1u l=1u m=1 -XT247 vdd well_247 ntap1 A=4e-12 P=8e-6 -XM11_24 vout net050 vdd well_247 sg13_lv_pmos w=1u l=1u m=1 -XT248 vdd well_248 ntap1 A=4e-12 P=8e-6 -XM11_25 vout net050 vdd well_248 sg13_lv_pmos w=1u l=1u m=1 -XT249 vdd well_249 ntap1 A=4e-12 P=8e-6 -XM11_26 vout net050 vdd well_249 sg13_lv_pmos w=1u l=1u m=1 -XT250 vdd well_250 ntap1 A=4e-12 P=8e-6 -XM11_27 vout net050 vdd well_250 sg13_lv_pmos w=1u l=1u m=1 -XT251 vdd well_251 ntap1 A=4e-12 P=8e-6 -XM11_28 vout net050 vdd well_251 sg13_lv_pmos w=1u l=1u m=1 -XT252 vdd well_252 ntap1 A=4e-12 P=8e-6 -XM11_29 vout net050 vdd well_252 sg13_lv_pmos w=1u l=1u m=1 -XT253 vdd well_253 ntap1 A=4e-12 P=8e-6 -XM11_30 vout net050 vdd well_253 sg13_lv_pmos w=1u l=1u m=1 -XT254 vdd well_254 ntap1 A=4e-12 P=8e-6 -XM11_31 vout net050 vdd well_254 sg13_lv_pmos w=1u l=1u m=1 -XT255 vdd well_255 ntap1 A=4e-12 P=8e-6 -XM11_32 vout net050 vdd well_255 sg13_lv_pmos w=1u l=1u m=1 -XT256 vdd well_256 ntap1 A=4e-12 P=8e-6 -XM11_33 vout net050 vdd well_256 sg13_lv_pmos w=1u l=1u m=1 -XT257 vdd well_257 ntap1 A=4e-12 P=8e-6 -XM11_34 vout net050 vdd well_257 sg13_lv_pmos w=1u l=1u m=1 -XT258 vdd well_258 ntap1 A=4e-12 P=8e-6 -XM11_35 vout net050 vdd well_258 sg13_lv_pmos w=1u l=1u m=1 -XT259 vdd well_259 ntap1 A=4e-12 P=8e-6 -XM11_36 vout net050 vdd well_259 sg13_lv_pmos w=1u l=1u m=1 -XT260 vdd well_260 ntap1 A=4e-12 P=8e-6 -XM11_37 vout net050 vdd well_260 sg13_lv_pmos w=1u l=1u m=1 -XT261 vdd well_261 ntap1 A=4e-12 P=8e-6 -XM11_38 vout net050 vdd well_261 sg13_lv_pmos w=1u l=1u m=1 -XT262 vdd well_262 ntap1 A=4e-12 P=8e-6 -XM11_39 vout net050 vdd well_262 sg13_lv_pmos w=1u l=1u m=1 -XT263 vdd well_263 ntap1 A=4e-12 P=8e-6 -XM11_40 vout net050 vdd well_263 sg13_lv_pmos w=1u l=1u m=1 -XT264 vdd well_264 ntap1 A=4e-12 P=8e-6 -XM11_41 vout net050 vdd well_264 sg13_lv_pmos w=1u l=1u m=1 -XT265 vdd well_265 ntap1 A=4e-12 P=8e-6 -XM11_42 vout net050 vdd well_265 sg13_lv_pmos w=1u l=1u m=1 -XT266 vdd well_266 ntap1 A=4e-12 P=8e-6 -XM11_43 vout net050 vdd well_266 sg13_lv_pmos w=1u l=1u m=1 -XT267 vdd well_267 ntap1 A=4e-12 P=8e-6 -XM11_44 vout net050 vdd well_267 sg13_lv_pmos w=1u l=1u m=1 -XT268 vdd well_268 ntap1 A=4e-12 P=8e-6 -XM11_45 vout net050 vdd well_268 sg13_lv_pmos w=1u l=1u m=1 -XT269 vdd well_269 ntap1 A=4e-12 P=8e-6 -XM11_46 vout net050 vdd well_269 sg13_lv_pmos w=1u l=1u m=1 -XT270 vdd well_270 ntap1 A=4e-12 P=8e-6 -XM11_47 vout net050 vdd well_270 sg13_lv_pmos w=1u l=1u m=1 -XT271 vdd well_271 ntap1 A=4e-12 P=8e-6 -XM11_48 vout net050 vdd well_271 sg13_lv_pmos w=1u l=1u m=1 -XT272 vdd well_272 ntap1 A=4e-12 P=8e-6 -XM11_49 vout net050 vdd well_272 sg13_lv_pmos w=1u l=1u m=1 -XT273 vdd well_273 ntap1 A=4e-12 P=8e-6 -XM11_50 vout net050 vdd well_273 sg13_lv_pmos w=1u l=1u m=1 -XT274 vdd well_274 ntap1 A=4e-12 P=8e-6 -XM11_51 vout net050 vdd well_274 sg13_lv_pmos w=1u l=1u m=1 -XT275 vdd well_275 ntap1 A=4e-12 P=8e-6 -XM11_52 vout net050 vdd well_275 sg13_lv_pmos w=1u l=1u m=1 -XT276 vdd well_276 ntap1 A=4e-12 P=8e-6 -XM11_53 vout net050 vdd well_276 sg13_lv_pmos w=1u l=1u m=1 -XT277 vdd well_277 ntap1 A=4e-12 P=8e-6 -XM11_54 vout net050 vdd well_277 sg13_lv_pmos w=1u l=1u m=1 -XT278 vdd well_278 ntap1 A=4e-12 P=8e-6 -XM11_55 vout net050 vdd well_278 sg13_lv_pmos w=1u l=1u m=1 -XT279 vdd well_279 ntap1 A=4e-12 P=8e-6 -XM11_56 vout net050 vdd well_279 sg13_lv_pmos w=1u l=1u m=1 -XT280 vdd well_280 ntap1 A=4e-12 P=8e-6 -XM11_57 vout net050 vdd well_280 sg13_lv_pmos w=1u l=1u m=1 -XT281 vdd well_281 ntap1 A=4e-12 P=8e-6 -XM11_58 vout net050 vdd well_281 sg13_lv_pmos w=1u l=1u m=1 -XT282 vdd well_282 ntap1 A=4e-12 P=8e-6 -XM11_59 vout net050 vdd well_282 sg13_lv_pmos w=1u l=1u m=1 -XT283 vdd well_283 ntap1 A=4e-12 P=8e-6 -XM11_60 vout net050 vdd well_283 sg13_lv_pmos w=1u l=1u m=1 -XT284 vdd well_284 ntap1 A=4e-12 P=8e-6 -XM11_61 vout net050 vdd well_284 sg13_lv_pmos w=1u l=1u m=1 -XT285 vdd well_285 ntap1 A=4e-12 P=8e-6 -XM11_62 vout net050 vdd well_285 sg13_lv_pmos w=1u l=1u m=1 -XT286 vdd well_286 ntap1 A=4e-12 P=8e-6 -XM11_63 vout net050 vdd well_286 sg13_lv_pmos w=1u l=1u m=1 -XT287 vdd well_287 ntap1 A=4e-12 P=8e-6 -XM11_64 vout net050 vdd well_287 sg13_lv_pmos w=1u l=1u m=1 -XT288 vdd well_288 ntap1 A=4e-12 P=8e-6 -XM11_65 vout net050 vdd well_288 sg13_lv_pmos w=1u l=1u m=1 -XT289 vdd well_289 ntap1 A=4e-12 P=8e-6 -XM11_66 vout net050 vdd well_289 sg13_lv_pmos w=1u l=1u m=1 -XT290 vdd well_290 ntap1 A=4e-12 P=8e-6 -XM11_67 vout net050 vdd well_290 sg13_lv_pmos w=1u l=1u m=1 -XT291 vdd well_291 ntap1 A=4e-12 P=8e-6 -XM11_68 vout net050 vdd well_291 sg13_lv_pmos w=1u l=1u m=1 -XT292 vdd well_292 ntap1 A=4e-12 P=8e-6 -XM11_69 vout net050 vdd well_292 sg13_lv_pmos w=1u l=1u m=1 -XT293 vdd well_293 ntap1 A=4e-12 P=8e-6 -XM11_70 vout net050 vdd well_293 sg13_lv_pmos w=1u l=1u m=1 -XT294 vdd well_294 ntap1 A=4e-12 P=8e-6 -XM11_71 vout net050 vdd well_294 sg13_lv_pmos w=1u l=1u m=1 -XT295 vdd well_295 ntap1 A=4e-12 P=8e-6 -XM11_72 vout net050 vdd well_295 sg13_lv_pmos w=1u l=1u m=1 -XT296 vdd well_296 ntap1 A=4e-12 P=8e-6 -XM11_73 vout net050 vdd well_296 sg13_lv_pmos w=1u l=1u m=1 -XT297 vdd well_297 ntap1 A=4e-12 P=8e-6 -XM11_74 vout net050 vdd well_297 sg13_lv_pmos w=1u l=1u m=1 -XT298 vdd well_298 ntap1 A=4e-12 P=8e-6 -XM11_75 vout net050 vdd well_298 sg13_lv_pmos w=1u l=1u m=1 -XT299 vdd well_299 ntap1 A=4e-12 P=8e-6 -XM11_76 vout net050 vdd well_299 sg13_lv_pmos w=1u l=1u m=1 -XT300 vdd well_300 ntap1 A=4e-12 P=8e-6 -XM11_77 vout net050 vdd well_300 sg13_lv_pmos w=1u l=1u m=1 -XT301 vdd well_301 ntap1 A=4e-12 P=8e-6 -XM11_78 vout net050 vdd well_301 sg13_lv_pmos w=1u l=1u m=1 -XT302 vdd well_302 ntap1 A=4e-12 P=8e-6 -XM11_79 vout net050 vdd well_302 sg13_lv_pmos w=1u l=1u m=1 -XT303 vdd well_303 ntap1 A=4e-12 P=8e-6 -XM11_80 vout net050 vdd well_303 sg13_lv_pmos w=1u l=1u m=1 -XT304 vdd well_304 ntap1 A=4e-12 P=8e-6 -XM11_81 vout net050 vdd well_304 sg13_lv_pmos w=1u l=1u m=1 -XT305 vdd well_305 ntap1 A=4e-12 P=8e-6 -XM11_82 vout net050 vdd well_305 sg13_lv_pmos w=1u l=1u m=1 -XT306 vdd well_306 ntap1 A=4e-12 P=8e-6 -XM11_83 vout net050 vdd well_306 sg13_lv_pmos w=1u l=1u m=1 -XT307 vdd well_307 ntap1 A=4e-12 P=8e-6 -XM11_84 vout net050 vdd well_307 sg13_lv_pmos w=1u l=1u m=1 -XT308 vdd well_308 ntap1 A=4e-12 P=8e-6 -XM11_85 vout net050 vdd well_308 sg13_lv_pmos w=1u l=1u m=1 -XT309 vdd well_309 ntap1 A=4e-12 P=8e-6 -XM11_86 vout net050 vdd well_309 sg13_lv_pmos w=1u l=1u m=1 -XT310 vdd well_310 ntap1 A=4e-12 P=8e-6 -XM11_87 vout net050 vdd well_310 sg13_lv_pmos w=1u l=1u m=1 -XT311 vdd well_311 ntap1 A=4e-12 P=8e-6 -XM11_88 vout net050 vdd well_311 sg13_lv_pmos w=1u l=1u m=1 -XT312 vdd well_312 ntap1 A=4e-12 P=8e-6 -XM11_89 vout net050 vdd well_312 sg13_lv_pmos w=1u l=1u m=1 -XT313 vdd well_313 ntap1 A=4e-12 P=8e-6 -XM11_90 vout net050 vdd well_313 sg13_lv_pmos w=1u l=1u m=1 -XT314 vdd well_314 ntap1 A=4e-12 P=8e-6 -XM11_91 vout net050 vdd well_314 sg13_lv_pmos w=1u l=1u m=1 -XT315 vdd well_315 ntap1 A=4e-12 P=8e-6 -XM11_92 vout net050 vdd well_315 sg13_lv_pmos w=1u l=1u m=1 -XT316 vdd well_316 ntap1 A=4e-12 P=8e-6 -XM11_93 vout net050 vdd well_316 sg13_lv_pmos w=1u l=1u m=1 -XT317 vdd well_317 ntap1 A=4e-12 P=8e-6 -XM11_94 vout net050 vdd well_317 sg13_lv_pmos w=1u l=1u m=1 -XT318 vdd well_318 ntap1 A=4e-12 P=8e-6 -XM11_95 vout net050 vdd well_318 sg13_lv_pmos w=1u l=1u m=1 -XT319 vdd well_319 ntap1 A=4e-12 P=8e-6 -XM11_96 vout net050 vdd well_319 sg13_lv_pmos w=1u l=1u m=1 -XT320 vdd well_320 ntap1 A=4e-12 P=8e-6 -XM11_97 vout net050 vdd well_320 sg13_lv_pmos w=1u l=1u m=1 -XT321 vdd well_321 ntap1 A=4e-12 P=8e-6 -XM11_98 vout net050 vdd well_321 sg13_lv_pmos w=1u l=1u m=1 -XT322 vdd well_322 ntap1 A=4e-12 P=8e-6 -XM11_99 vout net050 vdd well_322 sg13_lv_pmos w=1u l=1u m=1 -XT323 vdd well_323 ntap1 A=4e-12 P=8e-6 -XM11_100 vout net050 vdd well_323 sg13_lv_pmos w=1u l=1u m=1 -XT324 vdd well_324 ntap1 A=4e-12 P=8e-6 -XM11_101 vout net050 vdd well_324 sg13_lv_pmos w=1u l=1u m=1 -XT325 vdd well_325 ntap1 A=4e-12 P=8e-6 -XM11_102 vout net050 vdd well_325 sg13_lv_pmos w=1u l=1u m=1 -XT326 vdd well_326 ntap1 A=4e-12 P=8e-6 -XM11_103 vout net050 vdd well_326 sg13_lv_pmos w=1u l=1u m=1 -XT327 vdd well_327 ntap1 A=4e-12 P=8e-6 -XM11_104 vout net050 vdd well_327 sg13_lv_pmos w=1u l=1u m=1 -XT328 vdd well_328 ntap1 A=4e-12 P=8e-6 -XM11_105 vout net050 vdd well_328 sg13_lv_pmos w=1u l=1u m=1 -XT329 vdd well_329 ntap1 A=4e-12 P=8e-6 -XM11_106 vout net050 vdd well_329 sg13_lv_pmos w=1u l=1u m=1 -XT330 vdd well_330 ntap1 A=4e-12 P=8e-6 -XM11_107 vout net050 vdd well_330 sg13_lv_pmos w=1u l=1u m=1 -XT331 vdd well_331 ntap1 A=4e-12 P=8e-6 -XM11_108 vout net050 vdd well_331 sg13_lv_pmos w=1u l=1u m=1 -XT332 vdd well_332 ntap1 A=4e-12 P=8e-6 -XM11_109 vout net050 vdd well_332 sg13_lv_pmos w=1u l=1u m=1 -XT333 vdd well_333 ntap1 A=4e-12 P=8e-6 -XM11_110 vout net050 vdd well_333 sg13_lv_pmos w=1u l=1u m=1 -XT334 vdd well_334 ntap1 A=4e-12 P=8e-6 -XM11_111 vout net050 vdd well_334 sg13_lv_pmos w=1u l=1u m=1 -XT335 vdd well_335 ntap1 A=4e-12 P=8e-6 -XM11_112 vout net050 vdd well_335 sg13_lv_pmos w=1u l=1u m=1 -XT336 vdd well_336 ntap1 A=4e-12 P=8e-6 -XM11_113 vout net050 vdd well_336 sg13_lv_pmos w=1u l=1u m=1 -XT337 vdd well_337 ntap1 A=4e-12 P=8e-6 -XM11_114 vout net050 vdd well_337 sg13_lv_pmos w=1u l=1u m=1 -XT338 vdd well_338 ntap1 A=4e-12 P=8e-6 -XM11_115 vout net050 vdd well_338 sg13_lv_pmos w=1u l=1u m=1 -XT339 vdd well_339 ntap1 A=4e-12 P=8e-6 -XM11_116 vout net050 vdd well_339 sg13_lv_pmos w=1u l=1u m=1 -XT340 vdd well_340 ntap1 A=4e-12 P=8e-6 -XM11_117 vout net050 vdd well_340 sg13_lv_pmos w=1u l=1u m=1 -XT341 vdd well_341 ntap1 A=4e-12 P=8e-6 -XM11_118 vout net050 vdd well_341 sg13_lv_pmos w=1u l=1u m=1 -XT342 vdd well_342 ntap1 A=4e-12 P=8e-6 -XM11_119 vout net050 vdd well_342 sg13_lv_pmos w=1u l=1u m=1 -XT343 vdd well_343 ntap1 A=4e-12 P=8e-6 -XM11_120 vout net050 vdd well_343 sg13_lv_pmos w=1u l=1u m=1 -XT344 vdd well_344 ntap1 A=4e-12 P=8e-6 -XM11_121 vout net050 vdd well_344 sg13_lv_pmos w=1u l=1u m=1 -XT345 vdd well_345 ntap1 A=4e-12 P=8e-6 -XM11_122 vout net050 vdd well_345 sg13_lv_pmos w=1u l=1u m=1 -XT346 vdd well_346 ntap1 A=4e-12 P=8e-6 -XM11_123 vout net050 vdd well_346 sg13_lv_pmos w=1u l=1u m=1 -XT347 vdd well_347 ntap1 A=4e-12 P=8e-6 -XM11_124 vout net050 vdd well_347 sg13_lv_pmos w=1u l=1u m=1 -XT348 vdd well_348 ntap1 A=4e-12 P=8e-6 -XM11_125 vout net050 vdd well_348 sg13_lv_pmos w=1u l=1u m=1 -XT349 vdd well_349 ntap1 A=4e-12 P=8e-6 -XM11_126 vout net050 vdd well_349 sg13_lv_pmos w=1u l=1u m=1 -XT350 vdd well_350 ntap1 A=4e-12 P=8e-6 -XM11_127 vout net050 vdd well_350 sg13_lv_pmos w=1u l=1u m=1 -XT351 vdd well_351 ntap1 A=4e-12 P=8e-6 -XM11_128 vout net050 vdd well_351 sg13_lv_pmos w=1u l=1u m=1 -XT352 vdd well_352 ntap1 A=4e-12 P=8e-6 -XM11_129 vout net050 vdd well_352 sg13_lv_pmos w=1u l=1u m=1 -XT353 vdd well_353 ntap1 A=4e-12 P=8e-6 -XM11_130 vout net050 vdd well_353 sg13_lv_pmos w=1u l=1u m=1 -XT354 vdd well_354 ntap1 A=4e-12 P=8e-6 -XM11_131 vout net050 vdd well_354 sg13_lv_pmos w=1u l=1u m=1 -XT355 vdd well_355 ntap1 A=4e-12 P=8e-6 -XM11_132 vout net050 vdd well_355 sg13_lv_pmos w=1u l=1u m=1 -XT356 vdd well_356 ntap1 A=4e-12 P=8e-6 -XM11_133 vout net050 vdd well_356 sg13_lv_pmos w=1u l=1u m=1 -XT357 vdd well_357 ntap1 A=4e-12 P=8e-6 -XM11_134 vout net050 vdd well_357 sg13_lv_pmos w=1u l=1u m=1 -XT358 vdd well_358 ntap1 A=4e-12 P=8e-6 -XM11_135 vout net050 vdd well_358 sg13_lv_pmos w=1u l=1u m=1 -XT359 vdd well_359 ntap1 A=4e-12 P=8e-6 -XM11_136 vout net050 vdd well_359 sg13_lv_pmos w=1u l=1u m=1 -XT360 vdd well_360 ntap1 A=4e-12 P=8e-6 -XM11_137 vout net050 vdd well_360 sg13_lv_pmos w=1u l=1u m=1 -XT361 vdd well_361 ntap1 A=4e-12 P=8e-6 -XM11_138 vout net050 vdd well_361 sg13_lv_pmos w=1u l=1u m=1 -XT362 vdd well_362 ntap1 A=4e-12 P=8e-6 -XM11_139 vout net050 vdd well_362 sg13_lv_pmos w=1u l=1u m=1 -XT363 vdd well_363 ntap1 A=4e-12 P=8e-6 -XM11_140 vout net050 vdd well_363 sg13_lv_pmos w=1u l=1u m=1 -XT364 vdd well_364 ntap1 A=4e-12 P=8e-6 -XM11_141 vout net050 vdd well_364 sg13_lv_pmos w=1u l=1u m=1 -XT365 vdd well_365 ntap1 A=4e-12 P=8e-6 -XM11_142 vout net050 vdd well_365 sg13_lv_pmos w=1u l=1u m=1 -XT366 vdd well_366 ntap1 A=4e-12 P=8e-6 -XM11_143 vout net050 vdd well_366 sg13_lv_pmos w=1u l=1u m=1 -XT367 vdd well_367 ntap1 A=4e-12 P=8e-6 -XM11_144 vout net050 vdd well_367 sg13_lv_pmos w=1u l=1u m=1 -XT368 vdd well_368 ntap1 A=4e-12 P=8e-6 -XM11_145 vout net050 vdd well_368 sg13_lv_pmos w=1u l=1u m=1 -XT369 vdd well_369 ntap1 A=4e-12 P=8e-6 -XM11_146 vout net050 vdd well_369 sg13_lv_pmos w=1u l=1u m=1 -XT370 vdd well_370 ntap1 A=4e-12 P=8e-6 -XM11_147 vout net050 vdd well_370 sg13_lv_pmos w=1u l=1u m=1 -XT371 vdd well_371 ntap1 A=4e-12 P=8e-6 -XM11_148 vout net050 vdd well_371 sg13_lv_pmos w=1u l=1u m=1 -XT372 vdd well_372 ntap1 A=4e-12 P=8e-6 -XM11_149 vout net050 vdd well_372 sg13_lv_pmos w=1u l=1u m=1 -XT373 vdd well_373 ntap1 A=4e-12 P=8e-6 -XM11_150 vout net050 vdd well_373 sg13_lv_pmos w=1u l=1u m=1 -XT374 vdd well_374 ntap1 A=4e-12 P=8e-6 -XM11_151 vout net050 vdd well_374 sg13_lv_pmos w=1u l=1u m=1 -XT375 vdd well_375 ntap1 A=4e-12 P=8e-6 -XM11_152 vout net050 vdd well_375 sg13_lv_pmos w=1u l=1u m=1 -XT376 vdd well_376 ntap1 A=4e-12 P=8e-6 -XM11_153 vout net050 vdd well_376 sg13_lv_pmos w=1u l=1u m=1 -XT377 vdd well_377 ntap1 A=4e-12 P=8e-6 -XM11_154 vout net050 vdd well_377 sg13_lv_pmos w=1u l=1u m=1 -XT378 vdd well_378 ntap1 A=4e-12 P=8e-6 -XM11_155 vout net050 vdd well_378 sg13_lv_pmos w=1u l=1u m=1 -XT379 vdd well_379 ntap1 A=4e-12 P=8e-6 -XM11_156 vout net050 vdd well_379 sg13_lv_pmos w=1u l=1u m=1 -XT380 vdd well_380 ntap1 A=4e-12 P=8e-6 -XM11_157 vout net050 vdd well_380 sg13_lv_pmos w=1u l=1u m=1 -XT381 vdd well_381 ntap1 A=4e-12 P=8e-6 -XM11_158 vout net050 vdd well_381 sg13_lv_pmos w=1u l=1u m=1 -XT382 vdd well_382 ntap1 A=4e-12 P=8e-6 -XM11_159 vout net050 vdd well_382 sg13_lv_pmos w=1u l=1u m=1 -XT383 vdd well_383 ntap1 A=4e-12 P=8e-6 -XM11_160 vout net050 vdd well_383 sg13_lv_pmos w=1u l=1u m=1 -XT384 vdd well_384 ntap1 A=4e-12 P=8e-6 -XM11_161 vout net050 vdd well_384 sg13_lv_pmos w=1u l=1u m=1 -XT385 vdd well_385 ntap1 A=4e-12 P=8e-6 -XM11_162 vout net050 vdd well_385 sg13_lv_pmos w=1u l=1u m=1 -XT386 vdd well_386 ntap1 A=4e-12 P=8e-6 -XM11_163 vout net050 vdd well_386 sg13_lv_pmos w=1u l=1u m=1 -XT387 vdd well_387 ntap1 A=4e-12 P=8e-6 -XM11_164 vout net050 vdd well_387 sg13_lv_pmos w=1u l=1u m=1 -XT388 vdd well_388 ntap1 A=4e-12 P=8e-6 -XM11_165 vout net050 vdd well_388 sg13_lv_pmos w=1u l=1u m=1 -XT389 vdd well_389 ntap1 A=4e-12 P=8e-6 -XM11_166 vout net050 vdd well_389 sg13_lv_pmos w=1u l=1u m=1 -XT390 vdd well_390 ntap1 A=4e-12 P=8e-6 -XM11_167 vout net050 vdd well_390 sg13_lv_pmos w=1u l=1u m=1 -XT391 vdd well_391 ntap1 A=4e-12 P=8e-6 -XM11_168 vout net050 vdd well_391 sg13_lv_pmos w=1u l=1u m=1 -XT392 vdd well_392 ntap1 A=4e-12 P=8e-6 -XM11_169 vout net050 vdd well_392 sg13_lv_pmos w=1u l=1u m=1 -XT393 vdd well_393 ntap1 A=4e-12 P=8e-6 -XM11_170 vout net050 vdd well_393 sg13_lv_pmos w=1u l=1u m=1 -XT394 vdd well_394 ntap1 A=4e-12 P=8e-6 -XM11_171 vout net050 vdd well_394 sg13_lv_pmos w=1u l=1u m=1 -XT395 vdd well_395 ntap1 A=4e-12 P=8e-6 -XM11_172 vout net050 vdd well_395 sg13_lv_pmos w=1u l=1u m=1 -XT396 vdd well_396 ntap1 A=4e-12 P=8e-6 -XM11_173 vout net050 vdd well_396 sg13_lv_pmos w=1u l=1u m=1 -XT397 vdd well_397 ntap1 A=4e-12 P=8e-6 -XM11_174 vout net050 vdd well_397 sg13_lv_pmos w=1u l=1u m=1 -XT398 vdd well_398 ntap1 A=4e-12 P=8e-6 -XM11_175 vout net050 vdd well_398 sg13_lv_pmos w=1u l=1u m=1 -XT399 vdd well_399 ntap1 A=4e-12 P=8e-6 -XM11_176 vout net050 vdd well_399 sg13_lv_pmos w=1u l=1u m=1 -XT400 vdd well_400 ntap1 A=4e-12 P=8e-6 -XM11_177 vout net050 vdd well_400 sg13_lv_pmos w=1u l=1u m=1 -XT401 vdd well_401 ntap1 A=4e-12 P=8e-6 -XM11_178 vout net050 vdd well_401 sg13_lv_pmos w=1u l=1u m=1 -XT402 vdd well_402 ntap1 A=4e-12 P=8e-6 -XM11_179 vout net050 vdd well_402 sg13_lv_pmos w=1u l=1u m=1 -XT403 vdd well_403 ntap1 A=4e-12 P=8e-6 -XM11_180 vout net050 vdd well_403 sg13_lv_pmos w=1u l=1u m=1 -XT404 vdd well_404 ntap1 A=4e-12 P=8e-6 -XM11_181 vout net050 vdd well_404 sg13_lv_pmos w=1u l=1u m=1 -XT405 vdd well_405 ntap1 A=4e-12 P=8e-6 -XM11_182 vout net050 vdd well_405 sg13_lv_pmos w=1u l=1u m=1 -XT406 vdd well_406 ntap1 A=4e-12 P=8e-6 -XM11_183 vout net050 vdd well_406 sg13_lv_pmos w=1u l=1u m=1 -XT407 vdd well_407 ntap1 A=4e-12 P=8e-6 -XM11_184 vout net050 vdd well_407 sg13_lv_pmos w=1u l=1u m=1 -XT408 vdd well_408 ntap1 A=4e-12 P=8e-6 -XM11_185 vout net050 vdd well_408 sg13_lv_pmos w=1u l=1u m=1 -XT409 vdd well_409 ntap1 A=4e-12 P=8e-6 -XM11_186 vout net050 vdd well_409 sg13_lv_pmos w=1u l=1u m=1 -XT410 vdd well_410 ntap1 A=4e-12 P=8e-6 -XM11_187 vout net050 vdd well_410 sg13_lv_pmos w=1u l=1u m=1 -XT411 vdd well_411 ntap1 A=4e-12 P=8e-6 -XM11_188 vout net050 vdd well_411 sg13_lv_pmos w=1u l=1u m=1 -XT412 vdd well_412 ntap1 A=4e-12 P=8e-6 -XM11_189 vout net050 vdd well_412 sg13_lv_pmos w=1u l=1u m=1 -XT413 vdd well_413 ntap1 A=4e-12 P=8e-6 -XM11_190 vout net050 vdd well_413 sg13_lv_pmos w=1u l=1u m=1 -XT414 vdd well_414 ntap1 A=4e-12 P=8e-6 -XM11_191 vout net050 vdd well_414 sg13_lv_pmos w=1u l=1u m=1 -XT415 vdd well_415 ntap1 A=4e-12 P=8e-6 -XM11_192 vout net050 vdd well_415 sg13_lv_pmos w=1u l=1u m=1 -XT416 vdd well_416 ntap1 A=4e-12 P=8e-6 -XM11_193 vout net050 vdd well_416 sg13_lv_pmos w=1u l=1u m=1 -XT417 vdd well_417 ntap1 A=4e-12 P=8e-6 -XM11_194 vout net050 vdd well_417 sg13_lv_pmos w=1u l=1u m=1 -XT418 vdd well_418 ntap1 A=4e-12 P=8e-6 -XM11_195 vout net050 vdd well_418 sg13_lv_pmos w=1u l=1u m=1 -XT419 vdd well_419 ntap1 A=4e-12 P=8e-6 -XM11_196 vout net050 vdd well_419 sg13_lv_pmos w=1u l=1u m=1 -XT420 vdd well_420 ntap1 A=4e-12 P=8e-6 -XM11_197 vout net050 vdd well_420 sg13_lv_pmos w=1u l=1u m=1 -XT421 vdd well_421 ntap1 A=4e-12 P=8e-6 -XM11_198 vout net050 vdd well_421 sg13_lv_pmos w=1u l=1u m=1 -XT422 vdd well_422 ntap1 A=4e-12 P=8e-6 -XM11_199 vout net050 vdd well_422 sg13_lv_pmos w=1u l=1u m=1 -XT423 vdd well_423 ntap1 A=4e-12 P=8e-6 -XM11_200 vout net050 vdd well_423 sg13_lv_pmos w=1u l=1u m=1 -XT424 vdd well_424 ntap1 A=4e-12 P=8e-6 -XM11_201 vout net050 vdd well_424 sg13_lv_pmos w=1u l=1u m=1 -XT425 vdd well_425 ntap1 A=4e-12 P=8e-6 -XM11_202 vout net050 vdd well_425 sg13_lv_pmos w=1u l=1u m=1 -XT426 vdd well_426 ntap1 A=4e-12 P=8e-6 -XM11_203 vout net050 vdd well_426 sg13_lv_pmos w=1u l=1u m=1 -XT427 vdd well_427 ntap1 A=4e-12 P=8e-6 -XM11_204 vout net050 vdd well_427 sg13_lv_pmos w=1u l=1u m=1 -XT428 vdd well_428 ntap1 A=4e-12 P=8e-6 -XM11_205 vout net050 vdd well_428 sg13_lv_pmos w=1u l=1u m=1 -XT429 vdd well_429 ntap1 A=4e-12 P=8e-6 -XM11_206 vout net050 vdd well_429 sg13_lv_pmos w=1u l=1u m=1 -XT430 vdd well_430 ntap1 A=4e-12 P=8e-6 -XM11_207 vout net050 vdd well_430 sg13_lv_pmos w=1u l=1u m=1 -XT431 vdd well_431 ntap1 A=4e-12 P=8e-6 -XM11_208 vout net050 vdd well_431 sg13_lv_pmos w=1u l=1u m=1 -XT432 vdd well_432 ntap1 A=4e-12 P=8e-6 -XM11_209 vout net050 vdd well_432 sg13_lv_pmos w=1u l=1u m=1 -XT433 vdd well_433 ntap1 A=4e-12 P=8e-6 -XM11_210 vout net050 vdd well_433 sg13_lv_pmos w=1u l=1u m=1 -XT434 vdd well_434 ntap1 A=4e-12 P=8e-6 -XM11_211 vout net050 vdd well_434 sg13_lv_pmos w=1u l=1u m=1 -XT435 vdd well_435 ntap1 A=4e-12 P=8e-6 -XM11_212 vout net050 vdd well_435 sg13_lv_pmos w=1u l=1u m=1 -XT436 vdd well_436 ntap1 A=4e-12 P=8e-6 -XM11_213 vout net050 vdd well_436 sg13_lv_pmos w=1u l=1u m=1 -XT437 vdd well_437 ntap1 A=4e-12 P=8e-6 -XM11_214 vout net050 vdd well_437 sg13_lv_pmos w=1u l=1u m=1 -XT438 vdd well_438 ntap1 A=4e-12 P=8e-6 -XM11_215 vout net050 vdd well_438 sg13_lv_pmos w=1u l=1u m=1 -XT439 vdd well_439 ntap1 A=4e-12 P=8e-6 -XM11_216 vout net050 vdd well_439 sg13_lv_pmos w=1u l=1u m=1 -XT440 vdd well_440 ntap1 A=4e-12 P=8e-6 -XM11_217 vout net050 vdd well_440 sg13_lv_pmos w=1u l=1u m=1 -XT441 vdd well_441 ntap1 A=4e-12 P=8e-6 -XM11_218 vout net050 vdd well_441 sg13_lv_pmos w=1u l=1u m=1 -XT442 vdd well_442 ntap1 A=4e-12 P=8e-6 -XM11_219 vout net050 vdd well_442 sg13_lv_pmos w=1u l=1u m=1 -XT443 vdd well_443 ntap1 A=4e-12 P=8e-6 -XM11_220 vout net050 vdd well_443 sg13_lv_pmos w=1u l=1u m=1 -XT444 vdd well_444 ntap1 A=4e-12 P=8e-6 -XM11_221 vout net050 vdd well_444 sg13_lv_pmos w=1u l=1u m=1 -XT445 vdd well_445 ntap1 A=4e-12 P=8e-6 -XM11_222 vout net050 vdd well_445 sg13_lv_pmos w=1u l=1u m=1 -XT446 vdd well_446 ntap1 A=4e-12 P=8e-6 -XM11_223 vout net050 vdd well_446 sg13_lv_pmos w=1u l=1u m=1 -XT447 vdd well_447 ntap1 A=4e-12 P=8e-6 -XM11_224 vout net050 vdd well_447 sg13_lv_pmos w=1u l=1u m=1 -XT448 vdd well_448 ntap1 A=4e-12 P=8e-6 -XM11_225 vout net050 vdd well_448 sg13_lv_pmos w=1u l=1u m=1 -XT449 vdd well_449 ntap1 A=4e-12 P=8e-6 -XM11_226 vout net050 vdd well_449 sg13_lv_pmos w=1u l=1u m=1 -XT450 vdd well_450 ntap1 A=4e-12 P=8e-6 -XM11_227 vout net050 vdd well_450 sg13_lv_pmos w=1u l=1u m=1 -XT451 vdd well_451 ntap1 A=4e-12 P=8e-6 -XM11_228 vout net050 vdd well_451 sg13_lv_pmos w=1u l=1u m=1 -XT452 vdd well_452 ntap1 A=4e-12 P=8e-6 -XM11_229 vout net050 vdd well_452 sg13_lv_pmos w=1u l=1u m=1 -XT453 vdd well_453 ntap1 A=4e-12 P=8e-6 -XM11_230 vout net050 vdd well_453 sg13_lv_pmos w=1u l=1u m=1 -XT454 vdd well_454 ntap1 A=4e-12 P=8e-6 -XM11_231 vout net050 vdd well_454 sg13_lv_pmos w=1u l=1u m=1 -XT455 vdd well_455 ntap1 A=4e-12 P=8e-6 -XM11_232 vout net050 vdd well_455 sg13_lv_pmos w=1u l=1u m=1 -XT456 vdd well_456 ntap1 A=4e-12 P=8e-6 -XM11_233 vout net050 vdd well_456 sg13_lv_pmos w=1u l=1u m=1 -XT457 vdd well_457 ntap1 A=4e-12 P=8e-6 -XM11_234 vout net050 vdd well_457 sg13_lv_pmos w=1u l=1u m=1 -XT458 vdd well_458 ntap1 A=4e-12 P=8e-6 -XM11_235 vout net050 vdd well_458 sg13_lv_pmos w=1u l=1u m=1 -XT459 vdd well_459 ntap1 A=4e-12 P=8e-6 -XM11_236 vout net050 vdd well_459 sg13_lv_pmos w=1u l=1u m=1 -XT460 vdd well_460 ntap1 A=4e-12 P=8e-6 -XM11_237 vout net050 vdd well_460 sg13_lv_pmos w=1u l=1u m=1 -XT461 vdd well_461 ntap1 A=4e-12 P=8e-6 -XM11_238 vout net050 vdd well_461 sg13_lv_pmos w=1u l=1u m=1 -XT462 vdd well_462 ntap1 A=4e-12 P=8e-6 -XM11_239 vout net050 vdd well_462 sg13_lv_pmos w=1u l=1u m=1 -XT463 vdd well_463 ntap1 A=4e-12 P=8e-6 -XM11_240 vout net050 vdd well_463 sg13_lv_pmos w=1u l=1u m=1 -XT464 vdd well_464 ntap1 A=4e-12 P=8e-6 -XM11_241 vout net050 vdd well_464 sg13_lv_pmos w=1u l=1u m=1 -XT465 vdd well_465 ntap1 A=4e-12 P=8e-6 -XM11_242 vout net050 vdd well_465 sg13_lv_pmos w=1u l=1u m=1 -XT466 vdd well_466 ntap1 A=4e-12 P=8e-6 -XM11_243 vout net050 vdd well_466 sg13_lv_pmos w=1u l=1u m=1 -XT467 vdd well_467 ntap1 A=4e-12 P=8e-6 -XM11_244 vout net050 vdd well_467 sg13_lv_pmos w=1u l=1u m=1 -XT468 vdd well_468 ntap1 A=4e-12 P=8e-6 -XM11_245 vout net050 vdd well_468 sg13_lv_pmos w=1u l=1u m=1 -XT469 vdd well_469 ntap1 A=4e-12 P=8e-6 -XM11_246 vout net050 vdd well_469 sg13_lv_pmos w=1u l=1u m=1 -XT470 vdd well_470 ntap1 A=4e-12 P=8e-6 -XM11_247 vout net050 vdd well_470 sg13_lv_pmos w=1u l=1u m=1 -XT471 vdd well_471 ntap1 A=4e-12 P=8e-6 -XM11_248 vout net050 vdd well_471 sg13_lv_pmos w=1u l=1u m=1 -XT472 vdd well_472 ntap1 A=4e-12 P=8e-6 -XM11_249 vout net050 vdd well_472 sg13_lv_pmos w=1u l=1u m=1 -XT473 vdd well_473 ntap1 A=4e-12 P=8e-6 -XM11_250 vout net050 vdd well_473 sg13_lv_pmos w=1u l=1u m=1 -XT474 vdd well_474 ntap1 A=4e-12 P=8e-6 -XM11_251 vout net050 vdd well_474 sg13_lv_pmos w=1u l=1u m=1 -XT475 vdd well_475 ntap1 A=4e-12 P=8e-6 -XM11_252 vout net050 vdd well_475 sg13_lv_pmos w=1u l=1u m=1 -XT476 vdd well_476 ntap1 A=4e-12 P=8e-6 -XM11_253 vout net050 vdd well_476 sg13_lv_pmos w=1u l=1u m=1 -XT477 vdd well_477 ntap1 A=4e-12 P=8e-6 -XM11_254 vout net050 vdd well_477 sg13_lv_pmos w=1u l=1u m=1 -XT478 vdd well_478 ntap1 A=4e-12 P=8e-6 -XM11_255 vout net050 vdd well_478 sg13_lv_pmos w=1u l=1u m=1 -XT479 vdd well_479 ntap1 A=4e-12 P=8e-6 -XM11_256 vout net050 vdd well_479 sg13_lv_pmos w=1u l=1u m=1 -XT480 vdd well_480 ntap1 A=4e-12 P=8e-6 -XM11_257 vout net050 vdd well_480 sg13_lv_pmos w=1u l=1u m=1 -XT481 vdd well_481 ntap1 A=4e-12 P=8e-6 -XM11_258 vout net050 vdd well_481 sg13_lv_pmos w=1u l=1u m=1 -XT482 vdd well_482 ntap1 A=4e-12 P=8e-6 -XM11_259 vout net050 vdd well_482 sg13_lv_pmos w=1u l=1u m=1 -XT483 vdd well_483 ntap1 A=4e-12 P=8e-6 -XM11_260 vout net050 vdd well_483 sg13_lv_pmos w=1u l=1u m=1 -XT484 vdd well_484 ntap1 A=4e-12 P=8e-6 -XM11_261 vout net050 vdd well_484 sg13_lv_pmos w=1u l=1u m=1 -XT485 vdd well_485 ntap1 A=4e-12 P=8e-6 -XM11_262 vout net050 vdd well_485 sg13_lv_pmos w=1u l=1u m=1 -XT486 vdd well_486 ntap1 A=4e-12 P=8e-6 -XM11_263 vout net050 vdd well_486 sg13_lv_pmos w=1u l=1u m=1 -XT487 vdd well_487 ntap1 A=4e-12 P=8e-6 -XM11_264 vout net050 vdd well_487 sg13_lv_pmos w=1u l=1u m=1 -XT488 vdd well_488 ntap1 A=4e-12 P=8e-6 -XM11_265 vout net050 vdd well_488 sg13_lv_pmos w=1u l=1u m=1 -XT489 vdd well_489 ntap1 A=4e-12 P=8e-6 -XM11_266 vout net050 vdd well_489 sg13_lv_pmos w=1u l=1u m=1 -XT490 vdd well_490 ntap1 A=4e-12 P=8e-6 -XM11_267 vout net050 vdd well_490 sg13_lv_pmos w=1u l=1u m=1 -XT491 vdd well_491 ntap1 A=4e-12 P=8e-6 -XM11_268 vout net050 vdd well_491 sg13_lv_pmos w=1u l=1u m=1 -XT492 vdd well_492 ntap1 A=4e-12 P=8e-6 -XM11_269 vout net050 vdd well_492 sg13_lv_pmos w=1u l=1u m=1 -XT493 vdd well_493 ntap1 A=4e-12 P=8e-6 -XM11_270 vout net050 vdd well_493 sg13_lv_pmos w=1u l=1u m=1 -XT494 vdd well_494 ntap1 A=4e-12 P=8e-6 -XM11_271 vout net050 vdd well_494 sg13_lv_pmos w=1u l=1u m=1 -XT495 vdd well_495 ntap1 A=4e-12 P=8e-6 -XM11_272 vout net050 vdd well_495 sg13_lv_pmos w=1u l=1u m=1 -XT496 vdd well_496 ntap1 A=4e-12 P=8e-6 -XM11_273 vout net050 vdd well_496 sg13_lv_pmos w=1u l=1u m=1 -XT497 vdd well_497 ntap1 A=4e-12 P=8e-6 -XM11_274 vout net050 vdd well_497 sg13_lv_pmos w=1u l=1u m=1 -XT498 vdd well_498 ntap1 A=4e-12 P=8e-6 -XM11_275 vout net050 vdd well_498 sg13_lv_pmos w=1u l=1u m=1 -XT499 vdd well_499 ntap1 A=4e-12 P=8e-6 -XM11_276 vout net050 vdd well_499 sg13_lv_pmos w=1u l=1u m=1 -XT500 vdd well_500 ntap1 A=4e-12 P=8e-6 -XM11_277 vout net050 vdd well_500 sg13_lv_pmos w=1u l=1u m=1 -XT501 vdd well_501 ntap1 A=4e-12 P=8e-6 -XM11_278 vout net050 vdd well_501 sg13_lv_pmos w=1u l=1u m=1 -XT502 vdd well_502 ntap1 A=4e-12 P=8e-6 -XM11_279 vout net050 vdd well_502 sg13_lv_pmos w=1u l=1u m=1 -XT503 vdd well_503 ntap1 A=4e-12 P=8e-6 -XM11_280 vout net050 vdd well_503 sg13_lv_pmos w=1u l=1u m=1 -XT504 vdd well_504 ntap1 A=4e-12 P=8e-6 -XM11_281 vout net050 vdd well_504 sg13_lv_pmos w=1u l=1u m=1 -XT505 vdd well_505 ntap1 A=4e-12 P=8e-6 -XM11_282 vout net050 vdd well_505 sg13_lv_pmos w=1u l=1u m=1 -XT506 vdd well_506 ntap1 A=4e-12 P=8e-6 -XM11_283 vout net050 vdd well_506 sg13_lv_pmos w=1u l=1u m=1 -XT507 vdd well_507 ntap1 A=4e-12 P=8e-6 -XM11_284 vout net050 vdd well_507 sg13_lv_pmos w=1u l=1u m=1 -XT508 vdd well_508 ntap1 A=4e-12 P=8e-6 -XM11_285 vout net050 vdd well_508 sg13_lv_pmos w=1u l=1u m=1 -XT509 vdd well_509 ntap1 A=4e-12 P=8e-6 -XM11_286 vout net050 vdd well_509 sg13_lv_pmos w=1u l=1u m=1 -XT510 vdd well_510 ntap1 A=4e-12 P=8e-6 -XM11_287 vout net050 vdd well_510 sg13_lv_pmos w=1u l=1u m=1 -XT511 vdd well_511 ntap1 A=4e-12 P=8e-6 -XM11_288 vout net050 vdd well_511 sg13_lv_pmos w=1u l=1u m=1 -XT512 vdd well_512 ntap1 A=4e-12 P=8e-6 -XM11_289 vout net050 vdd well_512 sg13_lv_pmos w=1u l=1u m=1 -XT513 vdd well_513 ntap1 A=4e-12 P=8e-6 -XM11_290 vout net050 vdd well_513 sg13_lv_pmos w=1u l=1u m=1 -XT514 vdd well_514 ntap1 A=4e-12 P=8e-6 -XM11_291 vout net050 vdd well_514 sg13_lv_pmos w=1u l=1u m=1 -XT515 vdd well_515 ntap1 A=4e-12 P=8e-6 -XM11_292 vout net050 vdd well_515 sg13_lv_pmos w=1u l=1u m=1 -XT516 vdd well_516 ntap1 A=4e-12 P=8e-6 -XM11_293 vout net050 vdd well_516 sg13_lv_pmos w=1u l=1u m=1 -XT517 vdd well_517 ntap1 A=4e-12 P=8e-6 -XM11_294 vout net050 vdd well_517 sg13_lv_pmos w=1u l=1u m=1 -XT518 vdd well_518 ntap1 A=4e-12 P=8e-6 -XM11_295 vout net050 vdd well_518 sg13_lv_pmos w=1u l=1u m=1 -XT519 vdd well_519 ntap1 A=4e-12 P=8e-6 -XM11_296 vout net050 vdd well_519 sg13_lv_pmos w=1u l=1u m=1 -XT520 vdd well_520 ntap1 A=4e-12 P=8e-6 -XM11_297 vout net050 vdd well_520 sg13_lv_pmos w=1u l=1u m=1 -XT521 vdd well_521 ntap1 A=4e-12 P=8e-6 -XM11_298 vout net050 vdd well_521 sg13_lv_pmos w=1u l=1u m=1 -XT522 vdd well_522 ntap1 A=4e-12 P=8e-6 -XM11_299 vout net050 vdd well_522 sg13_lv_pmos w=1u l=1u m=1 -XT523 vdd well_523 ntap1 A=4e-12 P=8e-6 -XM11_300 vout net050 vdd well_523 sg13_lv_pmos w=1u l=1u m=1 -XT524 vdd well_524 ntap1 A=4e-12 P=8e-6 -XM11_301 vout net050 vdd well_524 sg13_lv_pmos w=1u l=1u m=1 -XT525 vdd well_525 ntap1 A=4e-12 P=8e-6 -XM11_302 vout net050 vdd well_525 sg13_lv_pmos w=1u l=1u m=1 -XT526 vdd well_526 ntap1 A=4e-12 P=8e-6 -XM11_303 vout net050 vdd well_526 sg13_lv_pmos w=1u l=1u m=1 -XT527 vdd well_527 ntap1 A=4e-12 P=8e-6 -XM11_304 vout net050 vdd well_527 sg13_lv_pmos w=1u l=1u m=1 -XT528 vdd well_528 ntap1 A=4e-12 P=8e-6 -XM11_305 vout net050 vdd well_528 sg13_lv_pmos w=1u l=1u m=1 -XT529 vdd well_529 ntap1 A=4e-12 P=8e-6 -XM11_306 vout net050 vdd well_529 sg13_lv_pmos w=1u l=1u m=1 -XT530 vdd well_530 ntap1 A=4e-12 P=8e-6 -XM11_307 vout net050 vdd well_530 sg13_lv_pmos w=1u l=1u m=1 -XT531 vdd well_531 ntap1 A=4e-12 P=8e-6 -XM11_308 vout net050 vdd well_531 sg13_lv_pmos w=1u l=1u m=1 -XT532 vdd well_532 ntap1 A=4e-12 P=8e-6 -XM11_309 vout net050 vdd well_532 sg13_lv_pmos w=1u l=1u m=1 -XT533 vdd well_533 ntap1 A=4e-12 P=8e-6 -XM11_310 vout net050 vdd well_533 sg13_lv_pmos w=1u l=1u m=1 -XT534 vdd well_534 ntap1 A=4e-12 P=8e-6 -XM11_311 vout net050 vdd well_534 sg13_lv_pmos w=1u l=1u m=1 -XT535 vdd well_535 ntap1 A=4e-12 P=8e-6 -XM11_312 vout net050 vdd well_535 sg13_lv_pmos w=1u l=1u m=1 -XT536 vdd well_536 ntap1 A=4e-12 P=8e-6 -XM11_313 vout net050 vdd well_536 sg13_lv_pmos w=1u l=1u m=1 -XT537 vdd well_537 ntap1 A=4e-12 P=8e-6 -XM11_314 vout net050 vdd well_537 sg13_lv_pmos w=1u l=1u m=1 -XT538 vdd well_538 ntap1 A=4e-12 P=8e-6 -XM11_315 vout net050 vdd well_538 sg13_lv_pmos w=1u l=1u m=1 -XT539 vdd well_539 ntap1 A=4e-12 P=8e-6 -XM11_316 vout net050 vdd well_539 sg13_lv_pmos w=1u l=1u m=1 -XT540 vdd well_540 ntap1 A=4e-12 P=8e-6 -XM11_317 vout net050 vdd well_540 sg13_lv_pmos w=1u l=1u m=1 -XT541 vdd well_541 ntap1 A=4e-12 P=8e-6 -XM11_318 vout net050 vdd well_541 sg13_lv_pmos w=1u l=1u m=1 -XT542 vdd well_542 ntap1 A=4e-12 P=8e-6 -XM11_319 vout net050 vdd well_542 sg13_lv_pmos w=1u l=1u m=1 -XT543 vdd well_543 ntap1 A=4e-12 P=8e-6 -XM11_320 vout net050 vdd well_543 sg13_lv_pmos w=1u l=1u m=1 -XT544 vdd well_544 ntap1 A=4e-12 P=8e-6 -XM11_321 vout net050 vdd well_544 sg13_lv_pmos w=1u l=1u m=1 -XT545 vdd well_545 ntap1 A=4e-12 P=8e-6 -XM11_322 vout net050 vdd well_545 sg13_lv_pmos w=1u l=1u m=1 -XT546 vdd well_546 ntap1 A=4e-12 P=8e-6 -XM11_323 vout net050 vdd well_546 sg13_lv_pmos w=1u l=1u m=1 -XT547 vdd well_547 ntap1 A=4e-12 P=8e-6 -XM11_324 vout net050 vdd well_547 sg13_lv_pmos w=1u l=1u m=1 -XT548 vdd well_548 ntap1 A=4e-12 P=8e-6 -XM11_325 vout net050 vdd well_548 sg13_lv_pmos w=1u l=1u m=1 -XT549 vdd well_549 ntap1 A=4e-12 P=8e-6 -XM11_326 vout net050 vdd well_549 sg13_lv_pmos w=1u l=1u m=1 -XT550 vdd well_550 ntap1 A=4e-12 P=8e-6 -XM11_327 vout net050 vdd well_550 sg13_lv_pmos w=1u l=1u m=1 -XT551 vdd well_551 ntap1 A=4e-12 P=8e-6 -XM11_328 vout net050 vdd well_551 sg13_lv_pmos w=1u l=1u m=1 -XT552 vdd well_552 ntap1 A=4e-12 P=8e-6 -XM11_329 vout net050 vdd well_552 sg13_lv_pmos w=1u l=1u m=1 -XT553 vdd well_553 ntap1 A=4e-12 P=8e-6 -XM11_330 vout net050 vdd well_553 sg13_lv_pmos w=1u l=1u m=1 -XT554 vdd well_554 ntap1 A=4e-12 P=8e-6 -XM11_331 vout net050 vdd well_554 sg13_lv_pmos w=1u l=1u m=1 -XT555 vdd well_555 ntap1 A=4e-12 P=8e-6 -XM11_332 vout net050 vdd well_555 sg13_lv_pmos w=1u l=1u m=1 -XT556 vdd well_556 ntap1 A=4e-12 P=8e-6 -XM11_333 vout net050 vdd well_556 sg13_lv_pmos w=1u l=1u m=1 -XT557 vdd well_557 ntap1 A=4e-12 P=8e-6 -XM11_334 vout net050 vdd well_557 sg13_lv_pmos w=1u l=1u m=1 -XT558 vdd well_558 ntap1 A=4e-12 P=8e-6 -XM11_335 vout net050 vdd well_558 sg13_lv_pmos w=1u l=1u m=1 -XT559 vdd well_559 ntap1 A=4e-12 P=8e-6 -XM11_336 vout net050 vdd well_559 sg13_lv_pmos w=1u l=1u m=1 -XT560 vdd well_560 ntap1 A=4e-12 P=8e-6 -XM11_337 vout net050 vdd well_560 sg13_lv_pmos w=1u l=1u m=1 -XT561 vdd well_561 ntap1 A=4e-12 P=8e-6 -XM11_338 vout net050 vdd well_561 sg13_lv_pmos w=1u l=1u m=1 -XT562 vdd well_562 ntap1 A=4e-12 P=8e-6 -XM11_339 vout net050 vdd well_562 sg13_lv_pmos w=1u l=1u m=1 -XT563 vdd well_563 ntap1 A=4e-12 P=8e-6 -XM11_340 vout net050 vdd well_563 sg13_lv_pmos w=1u l=1u m=1 -XT564 vdd well_564 ntap1 A=4e-12 P=8e-6 -XM11_341 vout net050 vdd well_564 sg13_lv_pmos w=1u l=1u m=1 -XT565 vdd well_565 ntap1 A=4e-12 P=8e-6 -XM11_342 vout net050 vdd well_565 sg13_lv_pmos w=1u l=1u m=1 -XT566 vdd well_566 ntap1 A=4e-12 P=8e-6 -XM11_343 vout net050 vdd well_566 sg13_lv_pmos w=1u l=1u m=1 -XT567 vdd well_567 ntap1 A=4e-12 P=8e-6 -XM11_344 vout net050 vdd well_567 sg13_lv_pmos w=1u l=1u m=1 -XT568 vdd well_568 ntap1 A=4e-12 P=8e-6 -XM11_345 vout net050 vdd well_568 sg13_lv_pmos w=1u l=1u m=1 -XT569 vdd well_569 ntap1 A=4e-12 P=8e-6 -XM11_346 vout net050 vdd well_569 sg13_lv_pmos w=1u l=1u m=1 -XT570 vdd well_570 ntap1 A=4e-12 P=8e-6 -XM11_347 vout net050 vdd well_570 sg13_lv_pmos w=1u l=1u m=1 -XT571 vdd well_571 ntap1 A=4e-12 P=8e-6 -XM11_348 vout net050 vdd well_571 sg13_lv_pmos w=1u l=1u m=1 -XT572 vdd well_572 ntap1 A=4e-12 P=8e-6 -XM11_349 vout net050 vdd well_572 sg13_lv_pmos w=1u l=1u m=1 -XT573 vdd well_573 ntap1 A=4e-12 P=8e-6 -XM11_350 vout net050 vdd well_573 sg13_lv_pmos w=1u l=1u m=1 -XT574 vdd well_574 ntap1 A=4e-12 P=8e-6 -XM11_351 vout net050 vdd well_574 sg13_lv_pmos w=1u l=1u m=1 -XT575 vdd well_575 ntap1 A=4e-12 P=8e-6 -XM11_352 vout net050 vdd well_575 sg13_lv_pmos w=1u l=1u m=1 -XT576 vdd well_576 ntap1 A=4e-12 P=8e-6 -XM11_353 vout net050 vdd well_576 sg13_lv_pmos w=1u l=1u m=1 -XT577 vdd well_577 ntap1 A=4e-12 P=8e-6 -XM11_354 vout net050 vdd well_577 sg13_lv_pmos w=1u l=1u m=1 -XT578 vdd well_578 ntap1 A=4e-12 P=8e-6 -XM11_355 vout net050 vdd well_578 sg13_lv_pmos w=1u l=1u m=1 -XT579 vdd well_579 ntap1 A=4e-12 P=8e-6 -XM11_356 vout net050 vdd well_579 sg13_lv_pmos w=1u l=1u m=1 -XT580 vdd well_580 ntap1 A=4e-12 P=8e-6 -XM11_357 vout net050 vdd well_580 sg13_lv_pmos w=1u l=1u m=1 -XT581 vdd well_581 ntap1 A=4e-12 P=8e-6 -XM11_358 vout net050 vdd well_581 sg13_lv_pmos w=1u l=1u m=1 -XT582 vdd well_582 ntap1 A=4e-12 P=8e-6 -XM11_359 vout net050 vdd well_582 sg13_lv_pmos w=1u l=1u m=1 -XT583 vdd well_583 ntap1 A=4e-12 P=8e-6 -XM11_360 vout net050 vdd well_583 sg13_lv_pmos w=1u l=1u m=1 -XT584 vdd well_584 ntap1 A=4e-12 P=8e-6 -XM11_361 vout net050 vdd well_584 sg13_lv_pmos w=1u l=1u m=1 -XT585 vdd well_585 ntap1 A=4e-12 P=8e-6 -XM11_362 vout net050 vdd well_585 sg13_lv_pmos w=1u l=1u m=1 -XT586 vdd well_586 ntap1 A=4e-12 P=8e-6 -XM11_363 vout net050 vdd well_586 sg13_lv_pmos w=1u l=1u m=1 -XT587 vdd well_587 ntap1 A=4e-12 P=8e-6 -XM11_364 vout net050 vdd well_587 sg13_lv_pmos w=1u l=1u m=1 -XT588 vdd well_588 ntap1 A=4e-12 P=8e-6 -XM11_365 vout net050 vdd well_588 sg13_lv_pmos w=1u l=1u m=1 -XT589 vdd well_589 ntap1 A=4e-12 P=8e-6 -XM11_366 vout net050 vdd well_589 sg13_lv_pmos w=1u l=1u m=1 -XT590 vdd well_590 ntap1 A=4e-12 P=8e-6 -XM11_367 vout net050 vdd well_590 sg13_lv_pmos w=1u l=1u m=1 -XT591 vdd well_591 ntap1 A=4e-12 P=8e-6 -XM11_368 vout net050 vdd well_591 sg13_lv_pmos w=1u l=1u m=1 -XT592 vdd well_592 ntap1 A=4e-12 P=8e-6 -XM11_369 vout net050 vdd well_592 sg13_lv_pmos w=1u l=1u m=1 -XT593 vdd well_593 ntap1 A=4e-12 P=8e-6 -XM11_370 vout net050 vdd well_593 sg13_lv_pmos w=1u l=1u m=1 -XT594 vdd well_594 ntap1 A=4e-12 P=8e-6 -XM11_371 vout net050 vdd well_594 sg13_lv_pmos w=1u l=1u m=1 -XT595 vdd well_595 ntap1 A=4e-12 P=8e-6 -XM11_372 vout net050 vdd well_595 sg13_lv_pmos w=1u l=1u m=1 -XT596 vdd well_596 ntap1 A=4e-12 P=8e-6 -XM11_373 vout net050 vdd well_596 sg13_lv_pmos w=1u l=1u m=1 -XT597 vdd well_597 ntap1 A=4e-12 P=8e-6 -XM11_374 vout net050 vdd well_597 sg13_lv_pmos w=1u l=1u m=1 -XT598 vdd well_598 ntap1 A=4e-12 P=8e-6 -XM11_375 vout net050 vdd well_598 sg13_lv_pmos w=1u l=1u m=1 -XT599 vdd well_599 ntap1 A=4e-12 P=8e-6 -XM11_376 vout net050 vdd well_599 sg13_lv_pmos w=1u l=1u m=1 -XT600 vdd well_600 ntap1 A=4e-12 P=8e-6 -XM11_377 vout net050 vdd well_600 sg13_lv_pmos w=1u l=1u m=1 -XT601 vdd well_601 ntap1 A=4e-12 P=8e-6 -XM11_378 vout net050 vdd well_601 sg13_lv_pmos w=1u l=1u m=1 -XT602 vdd well_602 ntap1 A=4e-12 P=8e-6 -XM11_379 vout net050 vdd well_602 sg13_lv_pmos w=1u l=1u m=1 -XT603 vdd well_603 ntap1 A=4e-12 P=8e-6 -XM11_380 vout net050 vdd well_603 sg13_lv_pmos w=1u l=1u m=1 -XT604 vdd well_604 ntap1 A=4e-12 P=8e-6 -XM11_381 vout net050 vdd well_604 sg13_lv_pmos w=1u l=1u m=1 -XT605 vdd well_605 ntap1 A=4e-12 P=8e-6 -XM11_382 vout net050 vdd well_605 sg13_lv_pmos w=1u l=1u m=1 -XT606 vdd well_606 ntap1 A=4e-12 P=8e-6 -XM11_383 vout net050 vdd well_606 sg13_lv_pmos w=1u l=1u m=1 -XT607 vdd well_607 ntap1 A=4e-12 P=8e-6 -XM11_384 vout net050 vdd well_607 sg13_lv_pmos w=1u l=1u m=1 -XT608 vdd well_608 ntap1 A=4e-12 P=8e-6 -XM11_385 vout net050 vdd well_608 sg13_lv_pmos w=1u l=1u m=1 -XT609 vdd well_609 ntap1 A=4e-12 P=8e-6 -XM11_386 vout net050 vdd well_609 sg13_lv_pmos w=1u l=1u m=1 -XT610 vdd well_610 ntap1 A=4e-12 P=8e-6 -XM11_387 vout net050 vdd well_610 sg13_lv_pmos w=1u l=1u m=1 -XT611 vdd well_611 ntap1 A=4e-12 P=8e-6 -XM11_388 vout net050 vdd well_611 sg13_lv_pmos w=1u l=1u m=1 -XT612 vdd well_612 ntap1 A=4e-12 P=8e-6 -XM11_389 vout net050 vdd well_612 sg13_lv_pmos w=1u l=1u m=1 -XT613 vdd well_613 ntap1 A=4e-12 P=8e-6 -XM11_390 vout net050 vdd well_613 sg13_lv_pmos w=1u l=1u m=1 -XT614 vdd well_614 ntap1 A=4e-12 P=8e-6 -XM11_391 vout net050 vdd well_614 sg13_lv_pmos w=1u l=1u m=1 -XT615 vdd well_615 ntap1 A=4e-12 P=8e-6 -XM11_392 vout net050 vdd well_615 sg13_lv_pmos w=1u l=1u m=1 -XT616 vdd well_616 ntap1 A=4e-12 P=8e-6 -XM11_393 vout net050 vdd well_616 sg13_lv_pmos w=1u l=1u m=1 -XT617 vdd well_617 ntap1 A=4e-12 P=8e-6 -XM11_394 vout net050 vdd well_617 sg13_lv_pmos w=1u l=1u m=1 -XT618 vdd well_618 ntap1 A=4e-12 P=8e-6 -XM11_395 vout net050 vdd well_618 sg13_lv_pmos w=1u l=1u m=1 -XT619 vdd well_619 ntap1 A=4e-12 P=8e-6 -XM11_396 vout net050 vdd well_619 sg13_lv_pmos w=1u l=1u m=1 -XT620 vdd well_620 ntap1 A=4e-12 P=8e-6 -XM11_397 vout net050 vdd well_620 sg13_lv_pmos w=1u l=1u m=1 -XT621 vdd well_621 ntap1 A=4e-12 P=8e-6 -XM11_398 vout net050 vdd well_621 sg13_lv_pmos w=1u l=1u m=1 -XT622 vdd well_622 ntap1 A=4e-12 P=8e-6 -XM11_399 vout net050 vdd well_622 sg13_lv_pmos w=1u l=1u m=1 -XT623 vss sub ptap1 A=4e-12 P=8e-6 -XM12_0 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT624 vss sub ptap1 A=4e-12 P=8e-6 -XM12_1 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT625 vss sub ptap1 A=4e-12 P=8e-6 -XM12_2 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT626 vss sub ptap1 A=4e-12 P=8e-6 -XM12_3 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT627 vss sub ptap1 A=4e-12 P=8e-6 -XM12_4 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT628 vss sub ptap1 A=4e-12 P=8e-6 -XM12_5 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT629 vss sub ptap1 A=4e-12 P=8e-6 -XM12_6 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT630 vss sub ptap1 A=4e-12 P=8e-6 -XM12_7 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT631 vss sub ptap1 A=4e-12 P=8e-6 -XM12_8 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT632 vss sub ptap1 A=4e-12 P=8e-6 -XM12_9 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT633 vss sub ptap1 A=4e-12 P=8e-6 -XM12_10 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT634 vss sub ptap1 A=4e-12 P=8e-6 -XM12_11 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT635 vss sub ptap1 A=4e-12 P=8e-6 -XM12_12 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT636 vss sub ptap1 A=4e-12 P=8e-6 -XM12_13 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT637 vss sub ptap1 A=4e-12 P=8e-6 -XM12_14 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT638 vss sub ptap1 A=4e-12 P=8e-6 -XM12_15 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT639 vss sub ptap1 A=4e-12 P=8e-6 -XM12_16 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT640 vss sub ptap1 A=4e-12 P=8e-6 -XM12_17 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT641 vss sub ptap1 A=4e-12 P=8e-6 -XM12_18 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT642 vss sub ptap1 A=4e-12 P=8e-6 -XM12_19 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT643 vss sub ptap1 A=4e-12 P=8e-6 -XM12_20 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT644 vss sub ptap1 A=4e-12 P=8e-6 -XM12_21 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT645 vss sub ptap1 A=4e-12 P=8e-6 -XM12_22 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT646 vss sub ptap1 A=4e-12 P=8e-6 -XM12_23 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT647 vss sub ptap1 A=4e-12 P=8e-6 -XM12_24 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT648 vss sub ptap1 A=4e-12 P=8e-6 -XM12_25 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT649 vss sub ptap1 A=4e-12 P=8e-6 -XM12_26 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT650 vss sub ptap1 A=4e-12 P=8e-6 -XM12_27 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT651 vss sub ptap1 A=4e-12 P=8e-6 -XM12_28 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT652 vss sub ptap1 A=4e-12 P=8e-6 -XM12_29 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT653 vss sub ptap1 A=4e-12 P=8e-6 -XM12_30 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT654 vss sub ptap1 A=4e-12 P=8e-6 -XM12_31 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT655 vss sub ptap1 A=4e-12 P=8e-6 -XM12_32 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT656 vss sub ptap1 A=4e-12 P=8e-6 -XM12_33 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT657 vss sub ptap1 A=4e-12 P=8e-6 -XM12_34 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT658 vss sub ptap1 A=4e-12 P=8e-6 -XM12_35 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT659 vss sub ptap1 A=4e-12 P=8e-6 -XM12_36 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT660 vss sub ptap1 A=4e-12 P=8e-6 -XM12_37 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT661 vss sub ptap1 A=4e-12 P=8e-6 -XM12_38 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT662 vss sub ptap1 A=4e-12 P=8e-6 -XM12_39 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT663 vss sub ptap1 A=4e-12 P=8e-6 -XM12_40 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT664 vss sub ptap1 A=4e-12 P=8e-6 -XM12_41 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT665 vss sub ptap1 A=4e-12 P=8e-6 -XM12_42 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT666 vss sub ptap1 A=4e-12 P=8e-6 -XM12_43 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT667 vss sub ptap1 A=4e-12 P=8e-6 -XM12_44 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT668 vss sub ptap1 A=4e-12 P=8e-6 -XM12_45 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT669 vss sub ptap1 A=4e-12 P=8e-6 -XM12_46 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT670 vss sub ptap1 A=4e-12 P=8e-6 -XM12_47 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT671 vss sub ptap1 A=4e-12 P=8e-6 -XM12_48 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT672 vss sub ptap1 A=4e-12 P=8e-6 -XM12_49 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT673 vss sub ptap1 A=4e-12 P=8e-6 -XM12_50 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT674 vss sub ptap1 A=4e-12 P=8e-6 -XM12_51 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT675 vss sub ptap1 A=4e-12 P=8e-6 -XM12_52 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT676 vss sub ptap1 A=4e-12 P=8e-6 -XM12_53 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT677 vss sub ptap1 A=4e-12 P=8e-6 -XM12_54 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT678 vss sub ptap1 A=4e-12 P=8e-6 -XM12_55 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT679 vss sub ptap1 A=4e-12 P=8e-6 -XM12_56 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT680 vss sub ptap1 A=4e-12 P=8e-6 -XM12_57 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT681 vss sub ptap1 A=4e-12 P=8e-6 -XM12_58 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT682 vss sub ptap1 A=4e-12 P=8e-6 -XM12_59 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT683 vss sub ptap1 A=4e-12 P=8e-6 -XM12_60 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT684 vss sub ptap1 A=4e-12 P=8e-6 -XM12_61 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT685 vss sub ptap1 A=4e-12 P=8e-6 -XM12_62 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT686 vss sub ptap1 A=4e-12 P=8e-6 -XM12_63 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT687 vss sub ptap1 A=4e-12 P=8e-6 -XM12_64 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT688 vss sub ptap1 A=4e-12 P=8e-6 -XM12_65 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT689 vss sub ptap1 A=4e-12 P=8e-6 -XM12_66 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT690 vss sub ptap1 A=4e-12 P=8e-6 -XM12_67 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT691 vss sub ptap1 A=4e-12 P=8e-6 -XM12_68 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT692 vss sub ptap1 A=4e-12 P=8e-6 -XM12_69 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT693 vss sub ptap1 A=4e-12 P=8e-6 -XM12_70 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT694 vss sub ptap1 A=4e-12 P=8e-6 -XM12_71 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT695 vss sub ptap1 A=4e-12 P=8e-6 -XM12_72 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT696 vss sub ptap1 A=4e-12 P=8e-6 -XM12_73 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT697 vss sub ptap1 A=4e-12 P=8e-6 -XM12_74 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT698 vss sub ptap1 A=4e-12 P=8e-6 -XM12_75 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT699 vss sub ptap1 A=4e-12 P=8e-6 -XM12_76 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT700 vss sub ptap1 A=4e-12 P=8e-6 -XM12_77 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT701 vss sub ptap1 A=4e-12 P=8e-6 -XM12_78 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT702 vss sub ptap1 A=4e-12 P=8e-6 -XM12_79 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT703 vss sub ptap1 A=4e-12 P=8e-6 -XM13_0 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT704 vss sub ptap1 A=4e-12 P=8e-6 -XM13_1 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT705 vss sub ptap1 A=4e-12 P=8e-6 -XM13_2 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT706 vss sub ptap1 A=4e-12 P=8e-6 -XM13_3 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT707 vss sub ptap1 A=4e-12 P=8e-6 -XM13_4 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT708 vss sub ptap1 A=4e-12 P=8e-6 -XM13_5 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT709 vss sub ptap1 A=4e-12 P=8e-6 -XM13_6 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT710 vss sub ptap1 A=4e-12 P=8e-6 -XM13_7 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT711 vss sub ptap1 A=4e-12 P=8e-6 -XM13_8 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT712 vss sub ptap1 A=4e-12 P=8e-6 -XM13_9 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT713 vss sub ptap1 A=4e-12 P=8e-6 -XM13_10 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT714 vss sub ptap1 A=4e-12 P=8e-6 -XM13_11 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT715 vss sub ptap1 A=4e-12 P=8e-6 -XM13_12 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT716 vss sub ptap1 A=4e-12 P=8e-6 -XM13_13 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT717 vss sub ptap1 A=4e-12 P=8e-6 -XM13_14 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT718 vss sub ptap1 A=4e-12 P=8e-6 -XM13_15 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT719 vss sub ptap1 A=4e-12 P=8e-6 -XM13_16 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT720 vss sub ptap1 A=4e-12 P=8e-6 -XM13_17 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT721 vss sub ptap1 A=4e-12 P=8e-6 -XM13_18 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT722 vss sub ptap1 A=4e-12 P=8e-6 -XM13_19 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT723 vss sub ptap1 A=4e-12 P=8e-6 -XM13_20 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT724 vss sub ptap1 A=4e-12 P=8e-6 -XM13_21 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT725 vss sub ptap1 A=4e-12 P=8e-6 -XM13_22 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT726 vss sub ptap1 A=4e-12 P=8e-6 -XM13_23 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT727 vss sub ptap1 A=4e-12 P=8e-6 -XM13_24 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT728 vss sub ptap1 A=4e-12 P=8e-6 -XM13_25 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT729 vss sub ptap1 A=4e-12 P=8e-6 -XM13_26 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT730 vss sub ptap1 A=4e-12 P=8e-6 -XM13_27 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT731 vss sub ptap1 A=4e-12 P=8e-6 -XM13_28 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT732 vss sub ptap1 A=4e-12 P=8e-6 -XM13_29 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT733 vss sub ptap1 A=4e-12 P=8e-6 -XM13_30 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT734 vss sub ptap1 A=4e-12 P=8e-6 -XM13_31 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT735 vss sub ptap1 A=4e-12 P=8e-6 -XM13_32 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT736 vss sub ptap1 A=4e-12 P=8e-6 -XM13_33 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT737 vss sub ptap1 A=4e-12 P=8e-6 -XM13_34 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT738 vss sub ptap1 A=4e-12 P=8e-6 -XM13_35 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT739 vss sub ptap1 A=4e-12 P=8e-6 -XM13_36 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT740 vss sub ptap1 A=4e-12 P=8e-6 -XM13_37 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT741 vss sub ptap1 A=4e-12 P=8e-6 -XM13_38 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT742 vss sub ptap1 A=4e-12 P=8e-6 -XM13_39 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT743 vss sub ptap1 A=4e-12 P=8e-6 -XM13_40 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT744 vss sub ptap1 A=4e-12 P=8e-6 -XM13_41 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT745 vss sub ptap1 A=4e-12 P=8e-6 -XM13_42 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT746 vss sub ptap1 A=4e-12 P=8e-6 -XM13_43 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT747 vss sub ptap1 A=4e-12 P=8e-6 -XM13_44 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT748 vss sub ptap1 A=4e-12 P=8e-6 -XM13_45 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT749 vss sub ptap1 A=4e-12 P=8e-6 -XM13_46 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT750 vss sub ptap1 A=4e-12 P=8e-6 -XM13_47 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT751 vss sub ptap1 A=4e-12 P=8e-6 -XM13_48 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT752 vss sub ptap1 A=4e-12 P=8e-6 -XM13_49 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT753 vss sub ptap1 A=4e-12 P=8e-6 -XM13_50 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT754 vss sub ptap1 A=4e-12 P=8e-6 -XM13_51 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT755 vss sub ptap1 A=4e-12 P=8e-6 -XM13_52 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT756 vss sub ptap1 A=4e-12 P=8e-6 -XM13_53 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT757 vss sub ptap1 A=4e-12 P=8e-6 -XM13_54 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT758 vss sub ptap1 A=4e-12 P=8e-6 -XM13_55 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT759 vss sub ptap1 A=4e-12 P=8e-6 -XM13_56 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT760 vss sub ptap1 A=4e-12 P=8e-6 -XM13_57 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT761 vss sub ptap1 A=4e-12 P=8e-6 -XM13_58 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT762 vss sub ptap1 A=4e-12 P=8e-6 -XM13_59 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT763 vss sub ptap1 A=4e-12 P=8e-6 -XM13_60 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT764 vss sub ptap1 A=4e-12 P=8e-6 -XM13_61 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT765 vss sub ptap1 A=4e-12 P=8e-6 -XM13_62 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT766 vss sub ptap1 A=4e-12 P=8e-6 -XM13_63 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT767 vss sub ptap1 A=4e-12 P=8e-6 -XM13_64 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT768 vss sub ptap1 A=4e-12 P=8e-6 -XM13_65 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT769 vss sub ptap1 A=4e-12 P=8e-6 -XM13_66 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT770 vss sub ptap1 A=4e-12 P=8e-6 -XM13_67 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT771 vss sub ptap1 A=4e-12 P=8e-6 -XM13_68 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT772 vss sub ptap1 A=4e-12 P=8e-6 -XM13_69 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT773 vss sub ptap1 A=4e-12 P=8e-6 -XM13_70 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT774 vss sub ptap1 A=4e-12 P=8e-6 -XM13_71 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT775 vss sub ptap1 A=4e-12 P=8e-6 -XM13_72 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT776 vss sub ptap1 A=4e-12 P=8e-6 -XM13_73 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT777 vss sub ptap1 A=4e-12 P=8e-6 -XM13_74 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT778 vss sub ptap1 A=4e-12 P=8e-6 -XM13_75 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT779 vss sub ptap1 A=4e-12 P=8e-6 -XM13_76 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT780 vss sub ptap1 A=4e-12 P=8e-6 -XM13_77 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT781 vss sub ptap1 A=4e-12 P=8e-6 -XM13_78 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT782 vss sub ptap1 A=4e-12 P=8e-6 -XM13_79 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT783 vss sub ptap1 A=4e-12 P=8e-6 -XM14_0 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT784 vss sub ptap1 A=4e-12 P=8e-6 -XM14_1 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT785 vss sub ptap1 A=4e-12 P=8e-6 -XM14_2 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT786 vss sub ptap1 A=4e-12 P=8e-6 -XM14_3 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT787 vss sub ptap1 A=4e-12 P=8e-6 -XM14_4 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT788 vss sub ptap1 A=4e-12 P=8e-6 -XM14_5 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT789 vss sub ptap1 A=4e-12 P=8e-6 -XM14_6 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT790 vss sub ptap1 A=4e-12 P=8e-6 -XM14_7 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT791 vss sub ptap1 A=4e-12 P=8e-6 -XM14_8 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT792 vss sub ptap1 A=4e-12 P=8e-6 -XM14_9 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT793 vss sub ptap1 A=4e-12 P=8e-6 -XM14_10 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT794 vss sub ptap1 A=4e-12 P=8e-6 -XM14_11 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT795 vss sub ptap1 A=4e-12 P=8e-6 -XM14_12 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT796 vss sub ptap1 A=4e-12 P=8e-6 -XM14_13 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT797 vss sub ptap1 A=4e-12 P=8e-6 -XM14_14 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT798 vss sub ptap1 A=4e-12 P=8e-6 -XM14_15 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT799 vss sub ptap1 A=4e-12 P=8e-6 -XM14_16 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT800 vss sub ptap1 A=4e-12 P=8e-6 -XM14_17 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT801 vss sub ptap1 A=4e-12 P=8e-6 -XM14_18 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT802 vss sub ptap1 A=4e-12 P=8e-6 -XM14_19 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT803 vss sub ptap1 A=4e-12 P=8e-6 -XM15_0 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT804 vss sub ptap1 A=4e-12 P=8e-6 -XM15_1 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT805 vss sub ptap1 A=4e-12 P=8e-6 -XM15_2 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT806 vss sub ptap1 A=4e-12 P=8e-6 -XM15_3 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT807 vss sub ptap1 A=4e-12 P=8e-6 -XM15_4 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT808 vss sub ptap1 A=4e-12 P=8e-6 -XM15_5 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT809 vss sub ptap1 A=4e-12 P=8e-6 -XM15_6 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT810 vss sub ptap1 A=4e-12 P=8e-6 -XM15_7 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT811 vss sub ptap1 A=4e-12 P=8e-6 -XM15_8 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT812 vss sub ptap1 A=4e-12 P=8e-6 -XM15_9 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT813 vss sub ptap1 A=4e-12 P=8e-6 -XM15_10 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT814 vss sub ptap1 A=4e-12 P=8e-6 -XM15_11 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT815 vss sub ptap1 A=4e-12 P=8e-6 -XM15_12 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT816 vss sub ptap1 A=4e-12 P=8e-6 -XM15_13 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT817 vss sub ptap1 A=4e-12 P=8e-6 -XM15_14 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT818 vss sub ptap1 A=4e-12 P=8e-6 -XM15_15 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT819 vss sub ptap1 A=4e-12 P=8e-6 -XM15_16 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT820 vss sub ptap1 A=4e-12 P=8e-6 -XM15_17 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT821 vss sub ptap1 A=4e-12 P=8e-6 -XM15_18 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT822 vss sub ptap1 A=4e-12 P=8e-6 -XM15_19 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT823 vss sub ptap1 A=4e-12 P=8e-6 -XM15_20 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT824 vss sub ptap1 A=4e-12 P=8e-6 -XM15_21 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT825 vss sub ptap1 A=4e-12 P=8e-6 -XM15_22 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT826 vss sub ptap1 A=4e-12 P=8e-6 -XM15_23 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT827 vss sub ptap1 A=4e-12 P=8e-6 -XM15_24 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT828 vss sub ptap1 A=4e-12 P=8e-6 -XM15_25 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT829 vss sub ptap1 A=4e-12 P=8e-6 -XM15_26 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT830 vss sub ptap1 A=4e-12 P=8e-6 -XM15_27 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT831 vss sub ptap1 A=4e-12 P=8e-6 -XM15_28 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT832 vss sub ptap1 A=4e-12 P=8e-6 -XM15_29 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT833 vss sub ptap1 A=4e-12 P=8e-6 -XM15_30 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT834 vss sub ptap1 A=4e-12 P=8e-6 -XM15_31 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT835 vss sub ptap1 A=4e-12 P=8e-6 -XM15_32 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT836 vss sub ptap1 A=4e-12 P=8e-6 -XM15_33 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT837 vss sub ptap1 A=4e-12 P=8e-6 -XM15_34 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT838 vss sub ptap1 A=4e-12 P=8e-6 -XM15_35 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT839 vss sub ptap1 A=4e-12 P=8e-6 -XM15_36 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT840 vss sub ptap1 A=4e-12 P=8e-6 -XM15_37 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT841 vss sub ptap1 A=4e-12 P=8e-6 -XM15_38 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT842 vss sub ptap1 A=4e-12 P=8e-6 -XM15_39 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT843 vss sub ptap1 A=4e-12 P=8e-6 -XM15_40 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT844 vss sub ptap1 A=4e-12 P=8e-6 -XM15_41 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT845 vss sub ptap1 A=4e-12 P=8e-6 -XM15_42 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT846 vss sub ptap1 A=4e-12 P=8e-6 -XM15_43 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT847 vss sub ptap1 A=4e-12 P=8e-6 -XM15_44 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT848 vss sub ptap1 A=4e-12 P=8e-6 -XM15_45 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT849 vss sub ptap1 A=4e-12 P=8e-6 -XM15_46 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT850 vss sub ptap1 A=4e-12 P=8e-6 -XM15_47 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT851 vss sub ptap1 A=4e-12 P=8e-6 -XM15_48 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT852 vss sub ptap1 A=4e-12 P=8e-6 -XM15_49 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT853 vss sub ptap1 A=4e-12 P=8e-6 -XM15_50 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT854 vss sub ptap1 A=4e-12 P=8e-6 -XM15_51 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT855 vss sub ptap1 A=4e-12 P=8e-6 -XM15_52 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT856 vss sub ptap1 A=4e-12 P=8e-6 -XM15_53 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT857 vss sub ptap1 A=4e-12 P=8e-6 -XM15_54 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT858 vss sub ptap1 A=4e-12 P=8e-6 -XM15_55 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT859 vss sub ptap1 A=4e-12 P=8e-6 -XM15_56 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT860 vss sub ptap1 A=4e-12 P=8e-6 -XM15_57 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT861 vss sub ptap1 A=4e-12 P=8e-6 -XM15_58 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT862 vss sub ptap1 A=4e-12 P=8e-6 -XM15_59 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT863 vss sub ptap1 A=4e-12 P=8e-6 -XM15_60 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT864 vss sub ptap1 A=4e-12 P=8e-6 -XM15_61 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT865 vss sub ptap1 A=4e-12 P=8e-6 -XM15_62 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT866 vss sub ptap1 A=4e-12 P=8e-6 -XM15_63 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT867 vss sub ptap1 A=4e-12 P=8e-6 -XM15_64 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT868 vss sub ptap1 A=4e-12 P=8e-6 -XM15_65 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT869 vss sub ptap1 A=4e-12 P=8e-6 -XM15_66 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT870 vss sub ptap1 A=4e-12 P=8e-6 -XM15_67 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT871 vss sub ptap1 A=4e-12 P=8e-6 -XM15_68 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT872 vss sub ptap1 A=4e-12 P=8e-6 -XM15_69 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT873 vss sub ptap1 A=4e-12 P=8e-6 -XM15_70 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT874 vss sub ptap1 A=4e-12 P=8e-6 -XM15_71 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT875 vss sub ptap1 A=4e-12 P=8e-6 -XM15_72 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT876 vss sub ptap1 A=4e-12 P=8e-6 -XM15_73 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT877 vss sub ptap1 A=4e-12 P=8e-6 -XM15_74 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT878 vss sub ptap1 A=4e-12 P=8e-6 -XM15_75 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT879 vss sub ptap1 A=4e-12 P=8e-6 -XM15_76 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT880 vss sub ptap1 A=4e-12 P=8e-6 -XM15_77 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT881 vss sub ptap1 A=4e-12 P=8e-6 -XM15_78 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT882 vss sub ptap1 A=4e-12 P=8e-6 -XM15_79 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT883 vss sub ptap1 A=4e-12 P=8e-6 -XM16_0 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT884 vss sub ptap1 A=4e-12 P=8e-6 -XM16_1 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT885 vss sub ptap1 A=4e-12 P=8e-6 -XM16_2 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT886 vss sub ptap1 A=4e-12 P=8e-6 -XM16_3 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT887 vss sub ptap1 A=4e-12 P=8e-6 -XM16_4 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT888 vss sub ptap1 A=4e-12 P=8e-6 -XM16_5 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT889 vss sub ptap1 A=4e-12 P=8e-6 -XM16_6 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT890 vss sub ptap1 A=4e-12 P=8e-6 -XM16_7 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT891 vss sub ptap1 A=4e-12 P=8e-6 -XM16_8 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT892 vss sub ptap1 A=4e-12 P=8e-6 -XM16_9 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT893 vss sub ptap1 A=4e-12 P=8e-6 -XM16_10 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT894 vss sub ptap1 A=4e-12 P=8e-6 -XM16_11 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT895 vss sub ptap1 A=4e-12 P=8e-6 -XM16_12 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT896 vss sub ptap1 A=4e-12 P=8e-6 -XM16_13 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT897 vss sub ptap1 A=4e-12 P=8e-6 -XM16_14 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT898 vss sub ptap1 A=4e-12 P=8e-6 -XM16_15 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT899 vss sub ptap1 A=4e-12 P=8e-6 -XM16_16 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT900 vss sub ptap1 A=4e-12 P=8e-6 -XM16_17 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT901 vss sub ptap1 A=4e-12 P=8e-6 -XM16_18 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT902 vss sub ptap1 A=4e-12 P=8e-6 -XM16_19 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT903 vss sub ptap1 A=4e-12 P=8e-6 -XM16_20 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT904 vss sub ptap1 A=4e-12 P=8e-6 -XM16_21 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT905 vss sub ptap1 A=4e-12 P=8e-6 -XM16_22 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT906 vss sub ptap1 A=4e-12 P=8e-6 -XM16_23 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT907 vss sub ptap1 A=4e-12 P=8e-6 -XM16_24 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT908 vss sub ptap1 A=4e-12 P=8e-6 -XM16_25 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT909 vss sub ptap1 A=4e-12 P=8e-6 -XM16_26 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT910 vss sub ptap1 A=4e-12 P=8e-6 -XM16_27 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT911 vss sub ptap1 A=4e-12 P=8e-6 -XM16_28 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT912 vss sub ptap1 A=4e-12 P=8e-6 -XM16_29 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT913 vss sub ptap1 A=4e-12 P=8e-6 -XM16_30 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT914 vss sub ptap1 A=4e-12 P=8e-6 -XM16_31 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT915 vss sub ptap1 A=4e-12 P=8e-6 -XM16_32 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT916 vss sub ptap1 A=4e-12 P=8e-6 -XM16_33 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT917 vss sub ptap1 A=4e-12 P=8e-6 -XM16_34 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT918 vss sub ptap1 A=4e-12 P=8e-6 -XM16_35 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT919 vss sub ptap1 A=4e-12 P=8e-6 -XM16_36 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT920 vss sub ptap1 A=4e-12 P=8e-6 -XM16_37 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT921 vss sub ptap1 A=4e-12 P=8e-6 -XM16_38 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT922 vss sub ptap1 A=4e-12 P=8e-6 -XM16_39 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT923 vss sub ptap1 A=4e-12 P=8e-6 -XM16_40 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT924 vss sub ptap1 A=4e-12 P=8e-6 -XM16_41 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT925 vss sub ptap1 A=4e-12 P=8e-6 -XM16_42 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT926 vss sub ptap1 A=4e-12 P=8e-6 -XM16_43 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT927 vss sub ptap1 A=4e-12 P=8e-6 -XM16_44 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT928 vss sub ptap1 A=4e-12 P=8e-6 -XM16_45 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT929 vss sub ptap1 A=4e-12 P=8e-6 -XM16_46 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT930 vss sub ptap1 A=4e-12 P=8e-6 -XM16_47 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT931 vss sub ptap1 A=4e-12 P=8e-6 -XM16_48 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT932 vss sub ptap1 A=4e-12 P=8e-6 -XM16_49 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT933 vss sub ptap1 A=4e-12 P=8e-6 -XM16_50 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT934 vss sub ptap1 A=4e-12 P=8e-6 -XM16_51 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT935 vss sub ptap1 A=4e-12 P=8e-6 -XM16_52 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT936 vss sub ptap1 A=4e-12 P=8e-6 -XM16_53 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT937 vss sub ptap1 A=4e-12 P=8e-6 -XM16_54 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT938 vss sub ptap1 A=4e-12 P=8e-6 -XM16_55 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT939 vss sub ptap1 A=4e-12 P=8e-6 -XM16_56 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT940 vss sub ptap1 A=4e-12 P=8e-6 -XM16_57 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT941 vss sub ptap1 A=4e-12 P=8e-6 -XM16_58 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT942 vss sub ptap1 A=4e-12 P=8e-6 -XM16_59 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT943 vss sub ptap1 A=4e-12 P=8e-6 -XM16_60 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT944 vss sub ptap1 A=4e-12 P=8e-6 -XM16_61 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT945 vss sub ptap1 A=4e-12 P=8e-6 -XM16_62 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT946 vss sub ptap1 A=4e-12 P=8e-6 -XM16_63 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT947 vss sub ptap1 A=4e-12 P=8e-6 -XM16_64 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT948 vss sub ptap1 A=4e-12 P=8e-6 -XM16_65 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT949 vss sub ptap1 A=4e-12 P=8e-6 -XM16_66 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT950 vss sub ptap1 A=4e-12 P=8e-6 -XM16_67 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT951 vss sub ptap1 A=4e-12 P=8e-6 -XM16_68 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT952 vss sub ptap1 A=4e-12 P=8e-6 -XM16_69 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT953 vss sub ptap1 A=4e-12 P=8e-6 -XM16_70 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT954 vss sub ptap1 A=4e-12 P=8e-6 -XM16_71 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT955 vss sub ptap1 A=4e-12 P=8e-6 -XM16_72 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT956 vss sub ptap1 A=4e-12 P=8e-6 -XM16_73 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT957 vss sub ptap1 A=4e-12 P=8e-6 -XM16_74 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT958 vss sub ptap1 A=4e-12 P=8e-6 -XM16_75 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT959 vss sub ptap1 A=4e-12 P=8e-6 -XM16_76 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT960 vss sub ptap1 A=4e-12 P=8e-6 -XM16_77 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT961 vss sub ptap1 A=4e-12 P=8e-6 -XM16_78 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT962 vss sub ptap1 A=4e-12 P=8e-6 -XM16_79 net050 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT963 vss sub ptap1 A=4e-12 P=8e-6 -XM17_0 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT964 vss sub ptap1 A=4e-12 P=8e-6 -XM17_1 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT965 vss sub ptap1 A=4e-12 P=8e-6 -XM17_2 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT966 vss sub ptap1 A=4e-12 P=8e-6 -XM17_3 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT967 vss sub ptap1 A=4e-12 P=8e-6 -XM17_4 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT968 vss sub ptap1 A=4e-12 P=8e-6 -XM17_5 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT969 vss sub ptap1 A=4e-12 P=8e-6 -XM17_6 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT970 vss sub ptap1 A=4e-12 P=8e-6 -XM17_7 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT971 vss sub ptap1 A=4e-12 P=8e-6 -XM17_8 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT972 vss sub ptap1 A=4e-12 P=8e-6 -XM17_9 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT973 vss sub ptap1 A=4e-12 P=8e-6 -XM17_10 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT974 vss sub ptap1 A=4e-12 P=8e-6 -XM17_11 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT975 vss sub ptap1 A=4e-12 P=8e-6 -XM17_12 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT976 vss sub ptap1 A=4e-12 P=8e-6 -XM17_13 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT977 vss sub ptap1 A=4e-12 P=8e-6 -XM17_14 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT978 vss sub ptap1 A=4e-12 P=8e-6 -XM17_15 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT979 vss sub ptap1 A=4e-12 P=8e-6 -XM17_16 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT980 vss sub ptap1 A=4e-12 P=8e-6 -XM17_17 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT981 vss sub ptap1 A=4e-12 P=8e-6 -XM17_18 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT982 vss sub ptap1 A=4e-12 P=8e-6 -XM17_19 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT983 vss sub ptap1 A=4e-12 P=8e-6 -XM17_20 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT984 vss sub ptap1 A=4e-12 P=8e-6 -XM17_21 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT985 vss sub ptap1 A=4e-12 P=8e-6 -XM17_22 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT986 vss sub ptap1 A=4e-12 P=8e-6 -XM17_23 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT987 vss sub ptap1 A=4e-12 P=8e-6 -XM17_24 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT988 vss sub ptap1 A=4e-12 P=8e-6 -XM17_25 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT989 vss sub ptap1 A=4e-12 P=8e-6 -XM17_26 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT990 vss sub ptap1 A=4e-12 P=8e-6 -XM17_27 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT991 vss sub ptap1 A=4e-12 P=8e-6 -XM17_28 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT992 vss sub ptap1 A=4e-12 P=8e-6 -XM17_29 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT993 vss sub ptap1 A=4e-12 P=8e-6 -XM17_30 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT994 vss sub ptap1 A=4e-12 P=8e-6 -XM17_31 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT995 vss sub ptap1 A=4e-12 P=8e-6 -XM17_32 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT996 vss sub ptap1 A=4e-12 P=8e-6 -XM17_33 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT997 vss sub ptap1 A=4e-12 P=8e-6 -XM17_34 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT998 vss sub ptap1 A=4e-12 P=8e-6 -XM17_35 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT999 vss sub ptap1 A=4e-12 P=8e-6 -XM17_36 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1000 vss sub ptap1 A=4e-12 P=8e-6 -XM17_37 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1001 vss sub ptap1 A=4e-12 P=8e-6 -XM17_38 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1002 vss sub ptap1 A=4e-12 P=8e-6 -XM17_39 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1003 vss sub ptap1 A=4e-12 P=8e-6 -XM17_40 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1004 vss sub ptap1 A=4e-12 P=8e-6 -XM17_41 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1005 vss sub ptap1 A=4e-12 P=8e-6 -XM17_42 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1006 vss sub ptap1 A=4e-12 P=8e-6 -XM17_43 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1007 vss sub ptap1 A=4e-12 P=8e-6 -XM17_44 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1008 vss sub ptap1 A=4e-12 P=8e-6 -XM17_45 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1009 vss sub ptap1 A=4e-12 P=8e-6 -XM17_46 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1010 vss sub ptap1 A=4e-12 P=8e-6 -XM17_47 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1011 vss sub ptap1 A=4e-12 P=8e-6 -XM17_48 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1012 vss sub ptap1 A=4e-12 P=8e-6 -XM17_49 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1013 vss sub ptap1 A=4e-12 P=8e-6 -XM17_50 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1014 vss sub ptap1 A=4e-12 P=8e-6 -XM17_51 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1015 vss sub ptap1 A=4e-12 P=8e-6 -XM17_52 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1016 vss sub ptap1 A=4e-12 P=8e-6 -XM17_53 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1017 vss sub ptap1 A=4e-12 P=8e-6 -XM17_54 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1018 vss sub ptap1 A=4e-12 P=8e-6 -XM17_55 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1019 vss sub ptap1 A=4e-12 P=8e-6 -XM17_56 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1020 vss sub ptap1 A=4e-12 P=8e-6 -XM17_57 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1021 vss sub ptap1 A=4e-12 P=8e-6 -XM17_58 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1022 vss sub ptap1 A=4e-12 P=8e-6 -XM17_59 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1023 vss sub ptap1 A=4e-12 P=8e-6 -XM17_60 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1024 vss sub ptap1 A=4e-12 P=8e-6 -XM17_61 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1025 vss sub ptap1 A=4e-12 P=8e-6 -XM17_62 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1026 vss sub ptap1 A=4e-12 P=8e-6 -XM17_63 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1027 vss sub ptap1 A=4e-12 P=8e-6 -XM17_64 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1028 vss sub ptap1 A=4e-12 P=8e-6 -XM17_65 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1029 vss sub ptap1 A=4e-12 P=8e-6 -XM17_66 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1030 vss sub ptap1 A=4e-12 P=8e-6 -XM17_67 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1031 vss sub ptap1 A=4e-12 P=8e-6 -XM17_68 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1032 vss sub ptap1 A=4e-12 P=8e-6 -XM17_69 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1033 vss sub ptap1 A=4e-12 P=8e-6 -XM17_70 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1034 vss sub ptap1 A=4e-12 P=8e-6 -XM17_71 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1035 vss sub ptap1 A=4e-12 P=8e-6 -XM17_72 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1036 vss sub ptap1 A=4e-12 P=8e-6 -XM17_73 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1037 vss sub ptap1 A=4e-12 P=8e-6 -XM17_74 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1038 vss sub ptap1 A=4e-12 P=8e-6 -XM17_75 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1039 vss sub ptap1 A=4e-12 P=8e-6 -XM17_76 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1040 vss sub ptap1 A=4e-12 P=8e-6 -XM17_77 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1041 vss sub ptap1 A=4e-12 P=8e-6 -XM17_78 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1042 vss sub ptap1 A=4e-12 P=8e-6 -XM17_79 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1043 vss sub ptap1 A=4e-12 P=8e-6 -XM18_0 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1044 vss sub ptap1 A=4e-12 P=8e-6 -XM18_1 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1045 vss sub ptap1 A=4e-12 P=8e-6 -XM18_2 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1046 vss sub ptap1 A=4e-12 P=8e-6 -XM18_3 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1047 vss sub ptap1 A=4e-12 P=8e-6 -XM18_4 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1048 vss sub ptap1 A=4e-12 P=8e-6 -XM18_5 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1049 vss sub ptap1 A=4e-12 P=8e-6 -XM18_6 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1050 vss sub ptap1 A=4e-12 P=8e-6 -XM18_7 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1051 vss sub ptap1 A=4e-12 P=8e-6 -XM18_8 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1052 vss sub ptap1 A=4e-12 P=8e-6 -XM18_9 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1053 vss sub ptap1 A=4e-12 P=8e-6 -XM18_10 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1054 vss sub ptap1 A=4e-12 P=8e-6 -XM18_11 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1055 vss sub ptap1 A=4e-12 P=8e-6 -XM18_12 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1056 vss sub ptap1 A=4e-12 P=8e-6 -XM18_13 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1057 vss sub ptap1 A=4e-12 P=8e-6 -XM18_14 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1058 vss sub ptap1 A=4e-12 P=8e-6 -XM18_15 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1059 vss sub ptap1 A=4e-12 P=8e-6 -XM18_16 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1060 vss sub ptap1 A=4e-12 P=8e-6 -XM18_17 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1061 vss sub ptap1 A=4e-12 P=8e-6 -XM18_18 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1062 vss sub ptap1 A=4e-12 P=8e-6 -XM18_19 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1063 vss sub ptap1 A=4e-12 P=8e-6 -XM18_20 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1064 vss sub ptap1 A=4e-12 P=8e-6 -XM18_21 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1065 vss sub ptap1 A=4e-12 P=8e-6 -XM18_22 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1066 vss sub ptap1 A=4e-12 P=8e-6 -XM18_23 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1067 vss sub ptap1 A=4e-12 P=8e-6 -XM18_24 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1068 vss sub ptap1 A=4e-12 P=8e-6 -XM18_25 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1069 vss sub ptap1 A=4e-12 P=8e-6 -XM18_26 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1070 vss sub ptap1 A=4e-12 P=8e-6 -XM18_27 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1071 vss sub ptap1 A=4e-12 P=8e-6 -XM18_28 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1072 vss sub ptap1 A=4e-12 P=8e-6 -XM18_29 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1073 vss sub ptap1 A=4e-12 P=8e-6 -XM18_30 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1074 vss sub ptap1 A=4e-12 P=8e-6 -XM18_31 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1075 vss sub ptap1 A=4e-12 P=8e-6 -XM18_32 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1076 vss sub ptap1 A=4e-12 P=8e-6 -XM18_33 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1077 vss sub ptap1 A=4e-12 P=8e-6 -XM18_34 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1078 vss sub ptap1 A=4e-12 P=8e-6 -XM18_35 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1079 vss sub ptap1 A=4e-12 P=8e-6 -XM18_36 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1080 vss sub ptap1 A=4e-12 P=8e-6 -XM18_37 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1081 vss sub ptap1 A=4e-12 P=8e-6 -XM18_38 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1082 vss sub ptap1 A=4e-12 P=8e-6 -XM18_39 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1083 vss sub ptap1 A=4e-12 P=8e-6 -XM18_40 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1084 vss sub ptap1 A=4e-12 P=8e-6 -XM18_41 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1085 vss sub ptap1 A=4e-12 P=8e-6 -XM18_42 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1086 vss sub ptap1 A=4e-12 P=8e-6 -XM18_43 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1087 vss sub ptap1 A=4e-12 P=8e-6 -XM18_44 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1088 vss sub ptap1 A=4e-12 P=8e-6 -XM18_45 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1089 vss sub ptap1 A=4e-12 P=8e-6 -XM18_46 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1090 vss sub ptap1 A=4e-12 P=8e-6 -XM18_47 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1091 vss sub ptap1 A=4e-12 P=8e-6 -XM18_48 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1092 vss sub ptap1 A=4e-12 P=8e-6 -XM18_49 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1093 vss sub ptap1 A=4e-12 P=8e-6 -XM18_50 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1094 vss sub ptap1 A=4e-12 P=8e-6 -XM18_51 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1095 vss sub ptap1 A=4e-12 P=8e-6 -XM18_52 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1096 vss sub ptap1 A=4e-12 P=8e-6 -XM18_53 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1097 vss sub ptap1 A=4e-12 P=8e-6 -XM18_54 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1098 vss sub ptap1 A=4e-12 P=8e-6 -XM18_55 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1099 vss sub ptap1 A=4e-12 P=8e-6 -XM18_56 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1100 vss sub ptap1 A=4e-12 P=8e-6 -XM18_57 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1101 vss sub ptap1 A=4e-12 P=8e-6 -XM18_58 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1102 vss sub ptap1 A=4e-12 P=8e-6 -XM18_59 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1103 vss sub ptap1 A=4e-12 P=8e-6 -XM18_60 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1104 vss sub ptap1 A=4e-12 P=8e-6 -XM18_61 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1105 vss sub ptap1 A=4e-12 P=8e-6 -XM18_62 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1106 vss sub ptap1 A=4e-12 P=8e-6 -XM18_63 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1107 vss sub ptap1 A=4e-12 P=8e-6 -XM18_64 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1108 vss sub ptap1 A=4e-12 P=8e-6 -XM18_65 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1109 vss sub ptap1 A=4e-12 P=8e-6 -XM18_66 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1110 vss sub ptap1 A=4e-12 P=8e-6 -XM18_67 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1111 vss sub ptap1 A=4e-12 P=8e-6 -XM18_68 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1112 vss sub ptap1 A=4e-12 P=8e-6 -XM18_69 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1113 vss sub ptap1 A=4e-12 P=8e-6 -XM18_70 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1114 vss sub ptap1 A=4e-12 P=8e-6 -XM18_71 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1115 vss sub ptap1 A=4e-12 P=8e-6 -XM18_72 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1116 vss sub ptap1 A=4e-12 P=8e-6 -XM18_73 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1117 vss sub ptap1 A=4e-12 P=8e-6 -XM18_74 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1118 vss sub ptap1 A=4e-12 P=8e-6 -XM18_75 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1119 vss sub ptap1 A=4e-12 P=8e-6 -XM18_76 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1120 vss sub ptap1 A=4e-12 P=8e-6 -XM18_77 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1121 vss sub ptap1 A=4e-12 P=8e-6 -XM18_78 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1122 vss sub ptap1 A=4e-12 P=8e-6 -XM18_79 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1123 vss sub ptap1 A=4e-12 P=8e-6 -XM19_0 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1124 vss sub ptap1 A=4e-12 P=8e-6 -XM19_1 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1125 vss sub ptap1 A=4e-12 P=8e-6 -XM19_2 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1126 vss sub ptap1 A=4e-12 P=8e-6 -XM19_3 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1127 vss sub ptap1 A=4e-12 P=8e-6 -XM19_4 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1128 vss sub ptap1 A=4e-12 P=8e-6 -XM19_5 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1129 vss sub ptap1 A=4e-12 P=8e-6 -XM19_6 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1130 vss sub ptap1 A=4e-12 P=8e-6 -XM19_7 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1131 vss sub ptap1 A=4e-12 P=8e-6 -XM19_8 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1132 vss sub ptap1 A=4e-12 P=8e-6 -XM19_9 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1133 vss sub ptap1 A=4e-12 P=8e-6 -XM19_10 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1134 vss sub ptap1 A=4e-12 P=8e-6 -XM19_11 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1135 vss sub ptap1 A=4e-12 P=8e-6 -XM19_12 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1136 vss sub ptap1 A=4e-12 P=8e-6 -XM19_13 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1137 vss sub ptap1 A=4e-12 P=8e-6 -XM19_14 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1138 vss sub ptap1 A=4e-12 P=8e-6 -XM19_15 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1139 vss sub ptap1 A=4e-12 P=8e-6 -XM19_16 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1140 vss sub ptap1 A=4e-12 P=8e-6 -XM19_17 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1141 vss sub ptap1 A=4e-12 P=8e-6 -XM19_18 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1142 vss sub ptap1 A=4e-12 P=8e-6 -XM19_19 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1143 vss sub ptap1 A=4e-12 P=8e-6 -XM19_20 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1144 vss sub ptap1 A=4e-12 P=8e-6 -XM19_21 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1145 vss sub ptap1 A=4e-12 P=8e-6 -XM19_22 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1146 vss sub ptap1 A=4e-12 P=8e-6 -XM19_23 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1147 vss sub ptap1 A=4e-12 P=8e-6 -XM19_24 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1148 vss sub ptap1 A=4e-12 P=8e-6 -XM19_25 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1149 vss sub ptap1 A=4e-12 P=8e-6 -XM19_26 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1150 vss sub ptap1 A=4e-12 P=8e-6 -XM19_27 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1151 vss sub ptap1 A=4e-12 P=8e-6 -XM19_28 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1152 vss sub ptap1 A=4e-12 P=8e-6 -XM19_29 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1153 vss sub ptap1 A=4e-12 P=8e-6 -XM19_30 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1154 vss sub ptap1 A=4e-12 P=8e-6 -XM19_31 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1155 vss sub ptap1 A=4e-12 P=8e-6 -XM19_32 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1156 vss sub ptap1 A=4e-12 P=8e-6 -XM19_33 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1157 vss sub ptap1 A=4e-12 P=8e-6 -XM19_34 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1158 vss sub ptap1 A=4e-12 P=8e-6 -XM19_35 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1159 vss sub ptap1 A=4e-12 P=8e-6 -XM19_36 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1160 vss sub ptap1 A=4e-12 P=8e-6 -XM19_37 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1161 vss sub ptap1 A=4e-12 P=8e-6 -XM19_38 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1162 vss sub ptap1 A=4e-12 P=8e-6 -XM19_39 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1163 vss sub ptap1 A=4e-12 P=8e-6 -XM19_40 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1164 vss sub ptap1 A=4e-12 P=8e-6 -XM19_41 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1165 vss sub ptap1 A=4e-12 P=8e-6 -XM19_42 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1166 vss sub ptap1 A=4e-12 P=8e-6 -XM19_43 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1167 vss sub ptap1 A=4e-12 P=8e-6 -XM19_44 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1168 vss sub ptap1 A=4e-12 P=8e-6 -XM19_45 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1169 vss sub ptap1 A=4e-12 P=8e-6 -XM19_46 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1170 vss sub ptap1 A=4e-12 P=8e-6 -XM19_47 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1171 vss sub ptap1 A=4e-12 P=8e-6 -XM19_48 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1172 vss sub ptap1 A=4e-12 P=8e-6 -XM19_49 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1173 vss sub ptap1 A=4e-12 P=8e-6 -XM19_50 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1174 vss sub ptap1 A=4e-12 P=8e-6 -XM19_51 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1175 vss sub ptap1 A=4e-12 P=8e-6 -XM19_52 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1176 vss sub ptap1 A=4e-12 P=8e-6 -XM19_53 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1177 vss sub ptap1 A=4e-12 P=8e-6 -XM19_54 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1178 vss sub ptap1 A=4e-12 P=8e-6 -XM19_55 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1179 vss sub ptap1 A=4e-12 P=8e-6 -XM19_56 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1180 vss sub ptap1 A=4e-12 P=8e-6 -XM19_57 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1181 vss sub ptap1 A=4e-12 P=8e-6 -XM19_58 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1182 vss sub ptap1 A=4e-12 P=8e-6 -XM19_59 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1183 vss sub ptap1 A=4e-12 P=8e-6 -XM19_60 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1184 vss sub ptap1 A=4e-12 P=8e-6 -XM19_61 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1185 vss sub ptap1 A=4e-12 P=8e-6 -XM19_62 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1186 vss sub ptap1 A=4e-12 P=8e-6 -XM19_63 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1187 vss sub ptap1 A=4e-12 P=8e-6 -XM19_64 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1188 vss sub ptap1 A=4e-12 P=8e-6 -XM19_65 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1189 vss sub ptap1 A=4e-12 P=8e-6 -XM19_66 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1190 vss sub ptap1 A=4e-12 P=8e-6 -XM19_67 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1191 vss sub ptap1 A=4e-12 P=8e-6 -XM19_68 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1192 vss sub ptap1 A=4e-12 P=8e-6 -XM19_69 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1193 vss sub ptap1 A=4e-12 P=8e-6 -XM19_70 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1194 vss sub ptap1 A=4e-12 P=8e-6 -XM19_71 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1195 vss sub ptap1 A=4e-12 P=8e-6 -XM19_72 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1196 vss sub ptap1 A=4e-12 P=8e-6 -XM19_73 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1197 vss sub ptap1 A=4e-12 P=8e-6 -XM19_74 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1198 vss sub ptap1 A=4e-12 P=8e-6 -XM19_75 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1199 vss sub ptap1 A=4e-12 P=8e-6 -XM19_76 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1200 vss sub ptap1 A=4e-12 P=8e-6 -XM19_77 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1201 vss sub ptap1 A=4e-12 P=8e-6 -XM19_78 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1202 vss sub ptap1 A=4e-12 P=8e-6 -XM19_79 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1203 vss sub ptap1 A=4e-12 P=8e-6 -XM19_80 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1204 vss sub ptap1 A=4e-12 P=8e-6 -XM19_81 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1205 vss sub ptap1 A=4e-12 P=8e-6 -XM19_82 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1206 vss sub ptap1 A=4e-12 P=8e-6 -XM19_83 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1207 vss sub ptap1 A=4e-12 P=8e-6 -XM19_84 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1208 vss sub ptap1 A=4e-12 P=8e-6 -XM19_85 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1209 vss sub ptap1 A=4e-12 P=8e-6 -XM19_86 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1210 vss sub ptap1 A=4e-12 P=8e-6 -XM19_87 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1211 vss sub ptap1 A=4e-12 P=8e-6 -XM19_88 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1212 vss sub ptap1 A=4e-12 P=8e-6 -XM19_89 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1213 vss sub ptap1 A=4e-12 P=8e-6 -XM19_90 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1214 vss sub ptap1 A=4e-12 P=8e-6 -XM19_91 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1215 vss sub ptap1 A=4e-12 P=8e-6 -XM19_92 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1216 vss sub ptap1 A=4e-12 P=8e-6 -XM19_93 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1217 vss sub ptap1 A=4e-12 P=8e-6 -XM19_94 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1218 vss sub ptap1 A=4e-12 P=8e-6 -XM19_95 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1219 vss sub ptap1 A=4e-12 P=8e-6 -XM19_96 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1220 vss sub ptap1 A=4e-12 P=8e-6 -XM19_97 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1221 vss sub ptap1 A=4e-12 P=8e-6 -XM19_98 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1222 vss sub ptap1 A=4e-12 P=8e-6 -XM19_99 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1223 vss sub ptap1 A=4e-12 P=8e-6 -XM19_100 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1224 vss sub ptap1 A=4e-12 P=8e-6 -XM19_101 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1225 vss sub ptap1 A=4e-12 P=8e-6 -XM19_102 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1226 vss sub ptap1 A=4e-12 P=8e-6 -XM19_103 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1227 vss sub ptap1 A=4e-12 P=8e-6 -XM19_104 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1228 vss sub ptap1 A=4e-12 P=8e-6 -XM19_105 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1229 vss sub ptap1 A=4e-12 P=8e-6 -XM19_106 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1230 vss sub ptap1 A=4e-12 P=8e-6 -XM19_107 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1231 vss sub ptap1 A=4e-12 P=8e-6 -XM19_108 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1232 vss sub ptap1 A=4e-12 P=8e-6 -XM19_109 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1233 vss sub ptap1 A=4e-12 P=8e-6 -XM19_110 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1234 vss sub ptap1 A=4e-12 P=8e-6 -XM19_111 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1235 vss sub ptap1 A=4e-12 P=8e-6 -XM19_112 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1236 vss sub ptap1 A=4e-12 P=8e-6 -XM19_113 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1237 vss sub ptap1 A=4e-12 P=8e-6 -XM19_114 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1238 vss sub ptap1 A=4e-12 P=8e-6 -XM19_115 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1239 vss sub ptap1 A=4e-12 P=8e-6 -XM19_116 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1240 vss sub ptap1 A=4e-12 P=8e-6 -XM19_117 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1241 vss sub ptap1 A=4e-12 P=8e-6 -XM19_118 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1242 vss sub ptap1 A=4e-12 P=8e-6 -XM19_119 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1243 vss sub ptap1 A=4e-12 P=8e-6 -XM19_120 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1244 vss sub ptap1 A=4e-12 P=8e-6 -XM19_121 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1245 vss sub ptap1 A=4e-12 P=8e-6 -XM19_122 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1246 vss sub ptap1 A=4e-12 P=8e-6 -XM19_123 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1247 vss sub ptap1 A=4e-12 P=8e-6 -XM19_124 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1248 vss sub ptap1 A=4e-12 P=8e-6 -XM19_125 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1249 vss sub ptap1 A=4e-12 P=8e-6 -XM19_126 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1250 vss sub ptap1 A=4e-12 P=8e-6 -XM19_127 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1251 vss sub ptap1 A=4e-12 P=8e-6 -XM19_128 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1252 vss sub ptap1 A=4e-12 P=8e-6 -XM19_129 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1253 vss sub ptap1 A=4e-12 P=8e-6 -XM19_130 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1254 vss sub ptap1 A=4e-12 P=8e-6 -XM19_131 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1255 vss sub ptap1 A=4e-12 P=8e-6 -XM19_132 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1256 vss sub ptap1 A=4e-12 P=8e-6 -XM19_133 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1257 vss sub ptap1 A=4e-12 P=8e-6 -XM19_134 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1258 vss sub ptap1 A=4e-12 P=8e-6 -XM19_135 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1259 vss sub ptap1 A=4e-12 P=8e-6 -XM19_136 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1260 vss sub ptap1 A=4e-12 P=8e-6 -XM19_137 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1261 vss sub ptap1 A=4e-12 P=8e-6 -XM19_138 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1262 vss sub ptap1 A=4e-12 P=8e-6 -XM19_139 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1263 vss sub ptap1 A=4e-12 P=8e-6 -XM19_140 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1264 vss sub ptap1 A=4e-12 P=8e-6 -XM19_141 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1265 vss sub ptap1 A=4e-12 P=8e-6 -XM19_142 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1266 vss sub ptap1 A=4e-12 P=8e-6 -XM19_143 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1267 vss sub ptap1 A=4e-12 P=8e-6 -XM19_144 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1268 vss sub ptap1 A=4e-12 P=8e-6 -XM19_145 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1269 vss sub ptap1 A=4e-12 P=8e-6 -XM19_146 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1270 vss sub ptap1 A=4e-12 P=8e-6 -XM19_147 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1271 vss sub ptap1 A=4e-12 P=8e-6 -XM19_148 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1272 vss sub ptap1 A=4e-12 P=8e-6 -XM19_149 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1273 vss sub ptap1 A=4e-12 P=8e-6 -XM19_150 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1274 vss sub ptap1 A=4e-12 P=8e-6 -XM19_151 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1275 vss sub ptap1 A=4e-12 P=8e-6 -XM19_152 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1276 vss sub ptap1 A=4e-12 P=8e-6 -XM19_153 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1277 vss sub ptap1 A=4e-12 P=8e-6 -XM19_154 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1278 vss sub ptap1 A=4e-12 P=8e-6 -XM19_155 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1279 vss sub ptap1 A=4e-12 P=8e-6 -XM19_156 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1280 vss sub ptap1 A=4e-12 P=8e-6 -XM19_157 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1281 vss sub ptap1 A=4e-12 P=8e-6 -XM19_158 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1282 vss sub ptap1 A=4e-12 P=8e-6 -XM19_159 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1283 vdd well_1283 ntap1 A=4e-12 P=8e-6 -XM2_0 dm_1 net1 vdd well_1283 sg13_lv_pmos w=1u l=1u m=1 -XT1284 vdd well_1284 ntap1 A=4e-12 P=8e-6 -XM2_1 dm_1 net1 vdd well_1284 sg13_lv_pmos w=1u l=1u m=1 -XT1285 vdd well_1285 ntap1 A=4e-12 P=8e-6 -XM2_2 dm_1 net1 vdd well_1285 sg13_lv_pmos w=1u l=1u m=1 -XT1286 vdd well_1286 ntap1 A=4e-12 P=8e-6 -XM2_3 dm_1 net1 vdd well_1286 sg13_lv_pmos w=1u l=1u m=1 -XT1287 vdd well_1287 ntap1 A=4e-12 P=8e-6 -XM2_4 dm_1 net1 vdd well_1287 sg13_lv_pmos w=1u l=1u m=1 -XT1288 vdd well_1288 ntap1 A=4e-12 P=8e-6 -XM2_5 dm_1 net1 vdd well_1288 sg13_lv_pmos w=1u l=1u m=1 -XT1289 vdd well_1289 ntap1 A=4e-12 P=8e-6 -XM2_6 dm_1 net1 vdd well_1289 sg13_lv_pmos w=1u l=1u m=1 -XT1290 vdd well_1290 ntap1 A=4e-12 P=8e-6 -XM2_7 dm_1 net1 vdd well_1290 sg13_lv_pmos w=1u l=1u m=1 -XT1291 vdd well_1291 ntap1 A=4e-12 P=8e-6 -XM2_8 dm_1 net1 vdd well_1291 sg13_lv_pmos w=1u l=1u m=1 -XT1292 vdd well_1292 ntap1 A=4e-12 P=8e-6 -XM2_9 dm_1 net1 vdd well_1292 sg13_lv_pmos w=1u l=1u m=1 -XT1293 vdd well_1293 ntap1 A=4e-12 P=8e-6 -XM2_10 dm_1 net1 vdd well_1293 sg13_lv_pmos w=1u l=1u m=1 -XT1294 vdd well_1294 ntap1 A=4e-12 P=8e-6 -XM2_11 dm_1 net1 vdd well_1294 sg13_lv_pmos w=1u l=1u m=1 -XT1295 vdd well_1295 ntap1 A=4e-12 P=8e-6 -XM2_12 dm_1 net1 vdd well_1295 sg13_lv_pmos w=1u l=1u m=1 -XT1296 vdd well_1296 ntap1 A=4e-12 P=8e-6 -XM2_13 dm_1 net1 vdd well_1296 sg13_lv_pmos w=1u l=1u m=1 -XT1297 vdd well_1297 ntap1 A=4e-12 P=8e-6 -XM2_14 dm_1 net1 vdd well_1297 sg13_lv_pmos w=1u l=1u m=1 -XT1298 vdd well_1298 ntap1 A=4e-12 P=8e-6 -XM2_15 dm_1 net1 vdd well_1298 sg13_lv_pmos w=1u l=1u m=1 -XT1299 vdd well_1299 ntap1 A=4e-12 P=8e-6 -XM2_16 dm_1 net1 vdd well_1299 sg13_lv_pmos w=1u l=1u m=1 -XT1300 vdd well_1300 ntap1 A=4e-12 P=8e-6 -XM2_17 dm_1 net1 vdd well_1300 sg13_lv_pmos w=1u l=1u m=1 -XT1301 vdd well_1301 ntap1 A=4e-12 P=8e-6 -XM2_18 dm_1 net1 vdd well_1301 sg13_lv_pmos w=1u l=1u m=1 -XT1302 vdd well_1302 ntap1 A=4e-12 P=8e-6 -XM2_19 dm_1 net1 vdd well_1302 sg13_lv_pmos w=1u l=1u m=1 -XT1303 vdd well_1303 ntap1 A=4e-12 P=8e-6 -XM2_20 dm_1 net1 vdd well_1303 sg13_lv_pmos w=1u l=1u m=1 -XT1304 vdd well_1304 ntap1 A=4e-12 P=8e-6 -XM2_21 dm_1 net1 vdd well_1304 sg13_lv_pmos w=1u l=1u m=1 -XT1305 vdd well_1305 ntap1 A=4e-12 P=8e-6 -XM2_22 dm_1 net1 vdd well_1305 sg13_lv_pmos w=1u l=1u m=1 -XT1306 vdd well_1306 ntap1 A=4e-12 P=8e-6 -XM2_23 dm_1 net1 vdd well_1306 sg13_lv_pmos w=1u l=1u m=1 -XT1307 vdd well_1307 ntap1 A=4e-12 P=8e-6 -XM2_24 dm_1 net1 vdd well_1307 sg13_lv_pmos w=1u l=1u m=1 -XT1308 vdd well_1308 ntap1 A=4e-12 P=8e-6 -XM2_25 dm_1 net1 vdd well_1308 sg13_lv_pmos w=1u l=1u m=1 -XT1309 vdd well_1309 ntap1 A=4e-12 P=8e-6 -XM2_26 dm_1 net1 vdd well_1309 sg13_lv_pmos w=1u l=1u m=1 -XT1310 vdd well_1310 ntap1 A=4e-12 P=8e-6 -XM2_27 dm_1 net1 vdd well_1310 sg13_lv_pmos w=1u l=1u m=1 -XT1311 vdd well_1311 ntap1 A=4e-12 P=8e-6 -XM2_28 dm_1 net1 vdd well_1311 sg13_lv_pmos w=1u l=1u m=1 -XT1312 vdd well_1312 ntap1 A=4e-12 P=8e-6 -XM2_29 dm_1 net1 vdd well_1312 sg13_lv_pmos w=1u l=1u m=1 -XT1313 vdd well_1313 ntap1 A=4e-12 P=8e-6 -XM2_30 dm_1 net1 vdd well_1313 sg13_lv_pmos w=1u l=1u m=1 -XT1314 vdd well_1314 ntap1 A=4e-12 P=8e-6 -XM2_31 dm_1 net1 vdd well_1314 sg13_lv_pmos w=1u l=1u m=1 -XT1315 vdd well_1315 ntap1 A=4e-12 P=8e-6 -XM2_32 dm_1 net1 vdd well_1315 sg13_lv_pmos w=1u l=1u m=1 -XT1316 vdd well_1316 ntap1 A=4e-12 P=8e-6 -XM2_33 dm_1 net1 vdd well_1316 sg13_lv_pmos w=1u l=1u m=1 -XT1317 vdd well_1317 ntap1 A=4e-12 P=8e-6 -XM2_34 dm_1 net1 vdd well_1317 sg13_lv_pmos w=1u l=1u m=1 -XT1318 vdd well_1318 ntap1 A=4e-12 P=8e-6 -XM2_35 dm_1 net1 vdd well_1318 sg13_lv_pmos w=1u l=1u m=1 -XT1319 vdd well_1319 ntap1 A=4e-12 P=8e-6 -XM2_36 dm_1 net1 vdd well_1319 sg13_lv_pmos w=1u l=1u m=1 -XT1320 vdd well_1320 ntap1 A=4e-12 P=8e-6 -XM2_37 dm_1 net1 vdd well_1320 sg13_lv_pmos w=1u l=1u m=1 -XT1321 vdd well_1321 ntap1 A=4e-12 P=8e-6 -XM2_38 dm_1 net1 vdd well_1321 sg13_lv_pmos w=1u l=1u m=1 -XT1322 vdd well_1322 ntap1 A=4e-12 P=8e-6 -XM2_39 dm_1 net1 vdd well_1322 sg13_lv_pmos w=1u l=1u m=1 -XT1323 vdd well_1323 ntap1 A=4e-12 P=8e-6 -XM2_40 dm_1 net1 vdd well_1323 sg13_lv_pmos w=1u l=1u m=1 -XT1324 vdd well_1324 ntap1 A=4e-12 P=8e-6 -XM2_41 dm_1 net1 vdd well_1324 sg13_lv_pmos w=1u l=1u m=1 -XT1325 vdd well_1325 ntap1 A=4e-12 P=8e-6 -XM2_42 dm_1 net1 vdd well_1325 sg13_lv_pmos w=1u l=1u m=1 -XT1326 vdd well_1326 ntap1 A=4e-12 P=8e-6 -XM2_43 dm_1 net1 vdd well_1326 sg13_lv_pmos w=1u l=1u m=1 -XT1327 vdd well_1327 ntap1 A=4e-12 P=8e-6 -XM2_44 dm_1 net1 vdd well_1327 sg13_lv_pmos w=1u l=1u m=1 -XT1328 vdd well_1328 ntap1 A=4e-12 P=8e-6 -XM2_45 dm_1 net1 vdd well_1328 sg13_lv_pmos w=1u l=1u m=1 -XT1329 vdd well_1329 ntap1 A=4e-12 P=8e-6 -XM2_46 dm_1 net1 vdd well_1329 sg13_lv_pmos w=1u l=1u m=1 -XT1330 vdd well_1330 ntap1 A=4e-12 P=8e-6 -XM2_47 dm_1 net1 vdd well_1330 sg13_lv_pmos w=1u l=1u m=1 -XT1331 vdd well_1331 ntap1 A=4e-12 P=8e-6 -XM2_48 dm_1 net1 vdd well_1331 sg13_lv_pmos w=1u l=1u m=1 -XT1332 vdd well_1332 ntap1 A=4e-12 P=8e-6 -XM2_49 dm_1 net1 vdd well_1332 sg13_lv_pmos w=1u l=1u m=1 -XT1333 vdd well_1333 ntap1 A=4e-12 P=8e-6 -XM2_50 dm_1 net1 vdd well_1333 sg13_lv_pmos w=1u l=1u m=1 -XT1334 vdd well_1334 ntap1 A=4e-12 P=8e-6 -XM2_51 dm_1 net1 vdd well_1334 sg13_lv_pmos w=1u l=1u m=1 -XT1335 vdd well_1335 ntap1 A=4e-12 P=8e-6 -XM2_52 dm_1 net1 vdd well_1335 sg13_lv_pmos w=1u l=1u m=1 -XT1336 vdd well_1336 ntap1 A=4e-12 P=8e-6 -XM2_53 dm_1 net1 vdd well_1336 sg13_lv_pmos w=1u l=1u m=1 -XT1337 vdd well_1337 ntap1 A=4e-12 P=8e-6 -XM2_54 dm_1 net1 vdd well_1337 sg13_lv_pmos w=1u l=1u m=1 -XT1338 vdd well_1338 ntap1 A=4e-12 P=8e-6 -XM2_55 dm_1 net1 vdd well_1338 sg13_lv_pmos w=1u l=1u m=1 -XT1339 vdd well_1339 ntap1 A=4e-12 P=8e-6 -XM2_56 dm_1 net1 vdd well_1339 sg13_lv_pmos w=1u l=1u m=1 -XT1340 vdd well_1340 ntap1 A=4e-12 P=8e-6 -XM2_57 dm_1 net1 vdd well_1340 sg13_lv_pmos w=1u l=1u m=1 -XT1341 vdd well_1341 ntap1 A=4e-12 P=8e-6 -XM2_58 dm_1 net1 vdd well_1341 sg13_lv_pmos w=1u l=1u m=1 -XT1342 vdd well_1342 ntap1 A=4e-12 P=8e-6 -XM2_59 dm_1 net1 vdd well_1342 sg13_lv_pmos w=1u l=1u m=1 -XT1343 vdd well_1343 ntap1 A=4e-12 P=8e-6 -XM2_60 dm_1 net1 vdd well_1343 sg13_lv_pmos w=1u l=1u m=1 -XT1344 vdd well_1344 ntap1 A=4e-12 P=8e-6 -XM2_61 dm_1 net1 vdd well_1344 sg13_lv_pmos w=1u l=1u m=1 -XT1345 vdd well_1345 ntap1 A=4e-12 P=8e-6 -XM2_62 dm_1 net1 vdd well_1345 sg13_lv_pmos w=1u l=1u m=1 -XT1346 vdd well_1346 ntap1 A=4e-12 P=8e-6 -XM2_63 dm_1 net1 vdd well_1346 sg13_lv_pmos w=1u l=1u m=1 -XT1347 vdd well_1347 ntap1 A=4e-12 P=8e-6 -XM2_64 dm_1 net1 vdd well_1347 sg13_lv_pmos w=1u l=1u m=1 -XT1348 vdd well_1348 ntap1 A=4e-12 P=8e-6 -XM2_65 dm_1 net1 vdd well_1348 sg13_lv_pmos w=1u l=1u m=1 -XT1349 vdd well_1349 ntap1 A=4e-12 P=8e-6 -XM2_66 dm_1 net1 vdd well_1349 sg13_lv_pmos w=1u l=1u m=1 -XT1350 vdd well_1350 ntap1 A=4e-12 P=8e-6 -XM2_67 dm_1 net1 vdd well_1350 sg13_lv_pmos w=1u l=1u m=1 -XT1351 vdd well_1351 ntap1 A=4e-12 P=8e-6 -XM2_68 dm_1 net1 vdd well_1351 sg13_lv_pmos w=1u l=1u m=1 -XT1352 vdd well_1352 ntap1 A=4e-12 P=8e-6 -XM2_69 dm_1 net1 vdd well_1352 sg13_lv_pmos w=1u l=1u m=1 -XT1353 vdd well_1353 ntap1 A=4e-12 P=8e-6 -XM2_70 dm_1 net1 vdd well_1353 sg13_lv_pmos w=1u l=1u m=1 -XT1354 vss sub ptap1 A=4e-12 P=8e-6 -XM20_0 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1355 vss sub ptap1 A=4e-12 P=8e-6 -XM20_1 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1356 vss sub ptap1 A=4e-12 P=8e-6 -XM20_2 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1357 vss sub ptap1 A=4e-12 P=8e-6 -XM20_3 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1358 vss sub ptap1 A=4e-12 P=8e-6 -XM20_4 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1359 vss sub ptap1 A=4e-12 P=8e-6 -XM20_5 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1360 vss sub ptap1 A=4e-12 P=8e-6 -XM20_6 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1361 vss sub ptap1 A=4e-12 P=8e-6 -XM20_7 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1362 vss sub ptap1 A=4e-12 P=8e-6 -XM20_8 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1363 vss sub ptap1 A=4e-12 P=8e-6 -XM20_9 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1364 vss sub ptap1 A=4e-12 P=8e-6 -XM20_10 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1365 vss sub ptap1 A=4e-12 P=8e-6 -XM20_11 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1366 vss sub ptap1 A=4e-12 P=8e-6 -XM20_12 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1367 vss sub ptap1 A=4e-12 P=8e-6 -XM20_13 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1368 vss sub ptap1 A=4e-12 P=8e-6 -XM20_14 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1369 vss sub ptap1 A=4e-12 P=8e-6 -XM20_15 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1370 vss sub ptap1 A=4e-12 P=8e-6 -XM20_16 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1371 vss sub ptap1 A=4e-12 P=8e-6 -XM20_17 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1372 vss sub ptap1 A=4e-12 P=8e-6 -XM20_18 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1373 vss sub ptap1 A=4e-12 P=8e-6 -XM20_19 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1374 vss sub ptap1 A=4e-12 P=8e-6 -XM20_20 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1375 vss sub ptap1 A=4e-12 P=8e-6 -XM20_21 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1376 vss sub ptap1 A=4e-12 P=8e-6 -XM20_22 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1377 vss sub ptap1 A=4e-12 P=8e-6 -XM20_23 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1378 vss sub ptap1 A=4e-12 P=8e-6 -XM20_24 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1379 vss sub ptap1 A=4e-12 P=8e-6 -XM20_25 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1380 vss sub ptap1 A=4e-12 P=8e-6 -XM20_26 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1381 vss sub ptap1 A=4e-12 P=8e-6 -XM20_27 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1382 vss sub ptap1 A=4e-12 P=8e-6 -XM20_28 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1383 vss sub ptap1 A=4e-12 P=8e-6 -XM20_29 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1384 vss sub ptap1 A=4e-12 P=8e-6 -XM20_30 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1385 vss sub ptap1 A=4e-12 P=8e-6 -XM20_31 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1386 vss sub ptap1 A=4e-12 P=8e-6 -XM20_32 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1387 vss sub ptap1 A=4e-12 P=8e-6 -XM20_33 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1388 vss sub ptap1 A=4e-12 P=8e-6 -XM20_34 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1389 vss sub ptap1 A=4e-12 P=8e-6 -XM20_35 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1390 vss sub ptap1 A=4e-12 P=8e-6 -XM20_36 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1391 vss sub ptap1 A=4e-12 P=8e-6 -XM20_37 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1392 vss sub ptap1 A=4e-12 P=8e-6 -XM20_38 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1393 vss sub ptap1 A=4e-12 P=8e-6 -XM20_39 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1394 vss sub ptap1 A=4e-12 P=8e-6 -XM20_40 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1395 vss sub ptap1 A=4e-12 P=8e-6 -XM20_41 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1396 vss sub ptap1 A=4e-12 P=8e-6 -XM20_42 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1397 vss sub ptap1 A=4e-12 P=8e-6 -XM20_43 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1398 vss sub ptap1 A=4e-12 P=8e-6 -XM20_44 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1399 vss sub ptap1 A=4e-12 P=8e-6 -XM20_45 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1400 vss sub ptap1 A=4e-12 P=8e-6 -XM20_46 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1401 vss sub ptap1 A=4e-12 P=8e-6 -XM20_47 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1402 vss sub ptap1 A=4e-12 P=8e-6 -XM20_48 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1403 vss sub ptap1 A=4e-12 P=8e-6 -XM20_49 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1404 vss sub ptap1 A=4e-12 P=8e-6 -XM20_50 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1405 vss sub ptap1 A=4e-12 P=8e-6 -XM20_51 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1406 vss sub ptap1 A=4e-12 P=8e-6 -XM20_52 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1407 vss sub ptap1 A=4e-12 P=8e-6 -XM20_53 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1408 vss sub ptap1 A=4e-12 P=8e-6 -XM20_54 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1409 vss sub ptap1 A=4e-12 P=8e-6 -XM20_55 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1410 vss sub ptap1 A=4e-12 P=8e-6 -XM20_56 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1411 vss sub ptap1 A=4e-12 P=8e-6 -XM20_57 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1412 vss sub ptap1 A=4e-12 P=8e-6 -XM20_58 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1413 vss sub ptap1 A=4e-12 P=8e-6 -XM20_59 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1414 vss sub ptap1 A=4e-12 P=8e-6 -XM20_60 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1415 vss sub ptap1 A=4e-12 P=8e-6 -XM20_61 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1416 vss sub ptap1 A=4e-12 P=8e-6 -XM20_62 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1417 vss sub ptap1 A=4e-12 P=8e-6 -XM20_63 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1418 vss sub ptap1 A=4e-12 P=8e-6 -XM20_64 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1419 vss sub ptap1 A=4e-12 P=8e-6 -XM20_65 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1420 vss sub ptap1 A=4e-12 P=8e-6 -XM20_66 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1421 vss sub ptap1 A=4e-12 P=8e-6 -XM20_67 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1422 vss sub ptap1 A=4e-12 P=8e-6 -XM20_68 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1423 vss sub ptap1 A=4e-12 P=8e-6 -XM20_69 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1424 vss sub ptap1 A=4e-12 P=8e-6 -XM20_70 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1425 vss sub ptap1 A=4e-12 P=8e-6 -XM20_71 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1426 vss sub ptap1 A=4e-12 P=8e-6 -XM20_72 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1427 vss sub ptap1 A=4e-12 P=8e-6 -XM20_73 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1428 vss sub ptap1 A=4e-12 P=8e-6 -XM20_74 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1429 vss sub ptap1 A=4e-12 P=8e-6 -XM20_75 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1430 vss sub ptap1 A=4e-12 P=8e-6 -XM20_76 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1431 vss sub ptap1 A=4e-12 P=8e-6 -XM20_77 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1432 vss sub ptap1 A=4e-12 P=8e-6 -XM20_78 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1433 vss sub ptap1 A=4e-12 P=8e-6 -XM20_79 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1434 vss sub ptap1 A=4e-12 P=8e-6 -XM20_80 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1435 vss sub ptap1 A=4e-12 P=8e-6 -XM20_81 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1436 vss sub ptap1 A=4e-12 P=8e-6 -XM20_82 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1437 vss sub ptap1 A=4e-12 P=8e-6 -XM20_83 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1438 vss sub ptap1 A=4e-12 P=8e-6 -XM20_84 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1439 vss sub ptap1 A=4e-12 P=8e-6 -XM20_85 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1440 vss sub ptap1 A=4e-12 P=8e-6 -XM20_86 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1441 vss sub ptap1 A=4e-12 P=8e-6 -XM20_87 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1442 vss sub ptap1 A=4e-12 P=8e-6 -XM20_88 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1443 vss sub ptap1 A=4e-12 P=8e-6 -XM20_89 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1444 vss sub ptap1 A=4e-12 P=8e-6 -XM20_90 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1445 vss sub ptap1 A=4e-12 P=8e-6 -XM20_91 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1446 vss sub ptap1 A=4e-12 P=8e-6 -XM20_92 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1447 vss sub ptap1 A=4e-12 P=8e-6 -XM20_93 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1448 vss sub ptap1 A=4e-12 P=8e-6 -XM20_94 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1449 vss sub ptap1 A=4e-12 P=8e-6 -XM20_95 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1450 vss sub ptap1 A=4e-12 P=8e-6 -XM20_96 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1451 vss sub ptap1 A=4e-12 P=8e-6 -XM20_97 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1452 vss sub ptap1 A=4e-12 P=8e-6 -XM20_98 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1453 vss sub ptap1 A=4e-12 P=8e-6 -XM20_99 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1454 vss sub ptap1 A=4e-12 P=8e-6 -XM20_100 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1455 vss sub ptap1 A=4e-12 P=8e-6 -XM20_101 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1456 vss sub ptap1 A=4e-12 P=8e-6 -XM20_102 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1457 vss sub ptap1 A=4e-12 P=8e-6 -XM20_103 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1458 vss sub ptap1 A=4e-12 P=8e-6 -XM20_104 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1459 vss sub ptap1 A=4e-12 P=8e-6 -XM20_105 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1460 vss sub ptap1 A=4e-12 P=8e-6 -XM20_106 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1461 vss sub ptap1 A=4e-12 P=8e-6 -XM20_107 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1462 vss sub ptap1 A=4e-12 P=8e-6 -XM20_108 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1463 vss sub ptap1 A=4e-12 P=8e-6 -XM20_109 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1464 vss sub ptap1 A=4e-12 P=8e-6 -XM20_110 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1465 vss sub ptap1 A=4e-12 P=8e-6 -XM20_111 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1466 vss sub ptap1 A=4e-12 P=8e-6 -XM20_112 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1467 vss sub ptap1 A=4e-12 P=8e-6 -XM20_113 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1468 vss sub ptap1 A=4e-12 P=8e-6 -XM20_114 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1469 vss sub ptap1 A=4e-12 P=8e-6 -XM20_115 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1470 vss sub ptap1 A=4e-12 P=8e-6 -XM20_116 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1471 vss sub ptap1 A=4e-12 P=8e-6 -XM20_117 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1472 vss sub ptap1 A=4e-12 P=8e-6 -XM20_118 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1473 vss sub ptap1 A=4e-12 P=8e-6 -XM20_119 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1474 vss sub ptap1 A=4e-12 P=8e-6 -XM20_120 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1475 vss sub ptap1 A=4e-12 P=8e-6 -XM20_121 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1476 vss sub ptap1 A=4e-12 P=8e-6 -XM20_122 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1477 vss sub ptap1 A=4e-12 P=8e-6 -XM20_123 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1478 vss sub ptap1 A=4e-12 P=8e-6 -XM20_124 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1479 vss sub ptap1 A=4e-12 P=8e-6 -XM20_125 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1480 vss sub ptap1 A=4e-12 P=8e-6 -XM20_126 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1481 vss sub ptap1 A=4e-12 P=8e-6 -XM20_127 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1482 vss sub ptap1 A=4e-12 P=8e-6 -XM20_128 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1483 vss sub ptap1 A=4e-12 P=8e-6 -XM20_129 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1484 vss sub ptap1 A=4e-12 P=8e-6 -XM20_130 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1485 vss sub ptap1 A=4e-12 P=8e-6 -XM20_131 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1486 vss sub ptap1 A=4e-12 P=8e-6 -XM20_132 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1487 vss sub ptap1 A=4e-12 P=8e-6 -XM20_133 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1488 vss sub ptap1 A=4e-12 P=8e-6 -XM20_134 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1489 vss sub ptap1 A=4e-12 P=8e-6 -XM20_135 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1490 vss sub ptap1 A=4e-12 P=8e-6 -XM20_136 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1491 vss sub ptap1 A=4e-12 P=8e-6 -XM20_137 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1492 vss sub ptap1 A=4e-12 P=8e-6 -XM20_138 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1493 vss sub ptap1 A=4e-12 P=8e-6 -XM20_139 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1494 vss sub ptap1 A=4e-12 P=8e-6 -XM20_140 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1495 vss sub ptap1 A=4e-12 P=8e-6 -XM20_141 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1496 vss sub ptap1 A=4e-12 P=8e-6 -XM20_142 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1497 vss sub ptap1 A=4e-12 P=8e-6 -XM20_143 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1498 vss sub ptap1 A=4e-12 P=8e-6 -XM20_144 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1499 vss sub ptap1 A=4e-12 P=8e-6 -XM20_145 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1500 vss sub ptap1 A=4e-12 P=8e-6 -XM20_146 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1501 vss sub ptap1 A=4e-12 P=8e-6 -XM20_147 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1502 vss sub ptap1 A=4e-12 P=8e-6 -XM20_148 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1503 vss sub ptap1 A=4e-12 P=8e-6 -XM20_149 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1504 vss sub ptap1 A=4e-12 P=8e-6 -XM20_150 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1505 vss sub ptap1 A=4e-12 P=8e-6 -XM20_151 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1506 vss sub ptap1 A=4e-12 P=8e-6 -XM20_152 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1507 vss sub ptap1 A=4e-12 P=8e-6 -XM20_153 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1508 vss sub ptap1 A=4e-12 P=8e-6 -XM20_154 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1509 vss sub ptap1 A=4e-12 P=8e-6 -XM20_155 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1510 vss sub ptap1 A=4e-12 P=8e-6 -XM20_156 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1511 vss sub ptap1 A=4e-12 P=8e-6 -XM20_157 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1512 vss sub ptap1 A=4e-12 P=8e-6 -XM20_158 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1513 vss sub ptap1 A=4e-12 P=8e-6 -XM20_159 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1514 vss sub ptap1 A=4e-12 P=8e-6 -XM21 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1515 vss sub ptap1 A=4e-12 P=8e-6 -XM22 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1516 vss sub ptap1 A=4e-12 P=8e-6 -XM23_0 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1517 vss sub ptap1 A=4e-12 P=8e-6 -XM23_1 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1518 vss sub ptap1 A=4e-12 P=8e-6 -XM23_2 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1519 vss sub ptap1 A=4e-12 P=8e-6 -XM23_3 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1520 vss sub ptap1 A=4e-12 P=8e-6 -XM23_4 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1521 vss sub ptap1 A=4e-12 P=8e-6 -XM23_5 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1522 vss sub ptap1 A=4e-12 P=8e-6 -XM23_6 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1523 vss sub ptap1 A=4e-12 P=8e-6 -XM23_7 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1524 vss sub ptap1 A=4e-12 P=8e-6 -XM23_8 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1525 vss sub ptap1 A=4e-12 P=8e-6 -XM23_9 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1526 vss sub ptap1 A=4e-12 P=8e-6 -XM23_10 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1527 vss sub ptap1 A=4e-12 P=8e-6 -XM23_11 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1528 vss sub ptap1 A=4e-12 P=8e-6 -XM23_12 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1529 vss sub ptap1 A=4e-12 P=8e-6 -XM23_13 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1530 vss sub ptap1 A=4e-12 P=8e-6 -XM23_14 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1531 vss sub ptap1 A=4e-12 P=8e-6 -XM23_15 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1532 vss sub ptap1 A=4e-12 P=8e-6 -XM23_16 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1533 vss sub ptap1 A=4e-12 P=8e-6 -XM23_17 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1534 vss sub ptap1 A=4e-12 P=8e-6 -XM23_18 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1535 vss sub ptap1 A=4e-12 P=8e-6 -XM23_19 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1536 vss sub ptap1 A=4e-12 P=8e-6 -XM23_20 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1537 vss sub ptap1 A=4e-12 P=8e-6 -XM23_21 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1538 vss sub ptap1 A=4e-12 P=8e-6 -XM23_22 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1539 vss sub ptap1 A=4e-12 P=8e-6 -XM23_23 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1540 vss sub ptap1 A=4e-12 P=8e-6 -XM23_24 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1541 vss sub ptap1 A=4e-12 P=8e-6 -XM23_25 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1542 vss sub ptap1 A=4e-12 P=8e-6 -XM23_26 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1543 vss sub ptap1 A=4e-12 P=8e-6 -XM23_27 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1544 vss sub ptap1 A=4e-12 P=8e-6 -XM23_28 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1545 vss sub ptap1 A=4e-12 P=8e-6 -XM23_29 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1546 vss sub ptap1 A=4e-12 P=8e-6 -XM23_30 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1547 vss sub ptap1 A=4e-12 P=8e-6 -XM23_31 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1548 vss sub ptap1 A=4e-12 P=8e-6 -XM23_32 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1549 vss sub ptap1 A=4e-12 P=8e-6 -XM23_33 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1550 vss sub ptap1 A=4e-12 P=8e-6 -XM23_34 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1551 vss sub ptap1 A=4e-12 P=8e-6 -XM23_35 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1552 vss sub ptap1 A=4e-12 P=8e-6 -XM23_36 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1553 vss sub ptap1 A=4e-12 P=8e-6 -XM23_37 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1554 vss sub ptap1 A=4e-12 P=8e-6 -XM23_38 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1555 vss sub ptap1 A=4e-12 P=8e-6 -XM23_39 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1556 vss sub ptap1 A=4e-12 P=8e-6 -XM23_40 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1557 vss sub ptap1 A=4e-12 P=8e-6 -XM23_41 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1558 vss sub ptap1 A=4e-12 P=8e-6 -XM23_42 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1559 vss sub ptap1 A=4e-12 P=8e-6 -XM23_43 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1560 vss sub ptap1 A=4e-12 P=8e-6 -XM23_44 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1561 vss sub ptap1 A=4e-12 P=8e-6 -XM23_45 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1562 vss sub ptap1 A=4e-12 P=8e-6 -XM23_46 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1563 vss sub ptap1 A=4e-12 P=8e-6 -XM23_47 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1564 vss sub ptap1 A=4e-12 P=8e-6 -XM23_48 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1565 vss sub ptap1 A=4e-12 P=8e-6 -XM23_49 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1566 vss sub ptap1 A=4e-12 P=8e-6 -XM23_50 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1567 vss sub ptap1 A=4e-12 P=8e-6 -XM23_51 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1568 vss sub ptap1 A=4e-12 P=8e-6 -XM23_52 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1569 vss sub ptap1 A=4e-12 P=8e-6 -XM23_53 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1570 vss sub ptap1 A=4e-12 P=8e-6 -XM23_54 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1571 vss sub ptap1 A=4e-12 P=8e-6 -XM23_55 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1572 vss sub ptap1 A=4e-12 P=8e-6 -XM23_56 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1573 vss sub ptap1 A=4e-12 P=8e-6 -XM23_57 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1574 vss sub ptap1 A=4e-12 P=8e-6 -XM23_58 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1575 vss sub ptap1 A=4e-12 P=8e-6 -XM23_59 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1576 vss sub ptap1 A=4e-12 P=8e-6 -XM23_60 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1577 vss sub ptap1 A=4e-12 P=8e-6 -XM23_61 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1578 vss sub ptap1 A=4e-12 P=8e-6 -XM23_62 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1579 vss sub ptap1 A=4e-12 P=8e-6 -XM23_63 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1580 vss sub ptap1 A=4e-12 P=8e-6 -XM23_64 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1581 vss sub ptap1 A=4e-12 P=8e-6 -XM23_65 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1582 vss sub ptap1 A=4e-12 P=8e-6 -XM23_66 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1583 vss sub ptap1 A=4e-12 P=8e-6 -XM23_67 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1584 vss sub ptap1 A=4e-12 P=8e-6 -XM23_68 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1585 vss sub ptap1 A=4e-12 P=8e-6 -XM23_69 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1586 vss sub ptap1 A=4e-12 P=8e-6 -XM23_70 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1587 vss sub ptap1 A=4e-12 P=8e-6 -XM23_71 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1588 vss sub ptap1 A=4e-12 P=8e-6 -XM23_72 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1589 vss sub ptap1 A=4e-12 P=8e-6 -XM23_73 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1590 vss sub ptap1 A=4e-12 P=8e-6 -XM23_74 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1591 vss sub ptap1 A=4e-12 P=8e-6 -XM23_75 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1592 vss sub ptap1 A=4e-12 P=8e-6 -XM23_76 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1593 vss sub ptap1 A=4e-12 P=8e-6 -XM23_77 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1594 vss sub ptap1 A=4e-12 P=8e-6 -XM23_78 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1595 vss sub ptap1 A=4e-12 P=8e-6 -XM23_79 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1596 vss sub ptap1 A=4e-12 P=8e-6 -XM23_80 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1597 vss sub ptap1 A=4e-12 P=8e-6 -XM23_81 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1598 vss sub ptap1 A=4e-12 P=8e-6 -XM23_82 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1599 vss sub ptap1 A=4e-12 P=8e-6 -XM23_83 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1600 vss sub ptap1 A=4e-12 P=8e-6 -XM23_84 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1601 vss sub ptap1 A=4e-12 P=8e-6 -XM23_85 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1602 vss sub ptap1 A=4e-12 P=8e-6 -XM23_86 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1603 vss sub ptap1 A=4e-12 P=8e-6 -XM23_87 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1604 vss sub ptap1 A=4e-12 P=8e-6 -XM23_88 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1605 vss sub ptap1 A=4e-12 P=8e-6 -XM23_89 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1606 vss sub ptap1 A=4e-12 P=8e-6 -XM23_90 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1607 vss sub ptap1 A=4e-12 P=8e-6 -XM23_91 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1608 vss sub ptap1 A=4e-12 P=8e-6 -XM23_92 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1609 vss sub ptap1 A=4e-12 P=8e-6 -XM23_93 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1610 vss sub ptap1 A=4e-12 P=8e-6 -XM23_94 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1611 vss sub ptap1 A=4e-12 P=8e-6 -XM23_95 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1612 vss sub ptap1 A=4e-12 P=8e-6 -XM23_96 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1613 vss sub ptap1 A=4e-12 P=8e-6 -XM23_97 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1614 vss sub ptap1 A=4e-12 P=8e-6 -XM23_98 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1615 vss sub ptap1 A=4e-12 P=8e-6 -XM23_99 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1616 vss sub ptap1 A=4e-12 P=8e-6 -XM23_100 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1617 vss sub ptap1 A=4e-12 P=8e-6 -XM23_101 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1618 vss sub ptap1 A=4e-12 P=8e-6 -XM23_102 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1619 vss sub ptap1 A=4e-12 P=8e-6 -XM23_103 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1620 vss sub ptap1 A=4e-12 P=8e-6 -XM23_104 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1621 vss sub ptap1 A=4e-12 P=8e-6 -XM23_105 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1622 vss sub ptap1 A=4e-12 P=8e-6 -XM23_106 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1623 vss sub ptap1 A=4e-12 P=8e-6 -XM23_107 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1624 vss sub ptap1 A=4e-12 P=8e-6 -XM23_108 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1625 vss sub ptap1 A=4e-12 P=8e-6 -XM23_109 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1626 vss sub ptap1 A=4e-12 P=8e-6 -XM23_110 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1627 vss sub ptap1 A=4e-12 P=8e-6 -XM23_111 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1628 vss sub ptap1 A=4e-12 P=8e-6 -XM23_112 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1629 vss sub ptap1 A=4e-12 P=8e-6 -XM23_113 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1630 vss sub ptap1 A=4e-12 P=8e-6 -XM23_114 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1631 vss sub ptap1 A=4e-12 P=8e-6 -XM23_115 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1632 vss sub ptap1 A=4e-12 P=8e-6 -XM23_116 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1633 vss sub ptap1 A=4e-12 P=8e-6 -XM23_117 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1634 vss sub ptap1 A=4e-12 P=8e-6 -XM23_118 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1635 vss sub ptap1 A=4e-12 P=8e-6 -XM23_119 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1636 vss sub ptap1 A=4e-12 P=8e-6 -XM23_120 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1637 vss sub ptap1 A=4e-12 P=8e-6 -XM23_121 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1638 vss sub ptap1 A=4e-12 P=8e-6 -XM23_122 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1639 vss sub ptap1 A=4e-12 P=8e-6 -XM23_123 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1640 vss sub ptap1 A=4e-12 P=8e-6 -XM23_124 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1641 vss sub ptap1 A=4e-12 P=8e-6 -XM23_125 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1642 vss sub ptap1 A=4e-12 P=8e-6 -XM23_126 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1643 vss sub ptap1 A=4e-12 P=8e-6 -XM23_127 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1644 vss sub ptap1 A=4e-12 P=8e-6 -XM23_128 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1645 vss sub ptap1 A=4e-12 P=8e-6 -XM23_129 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1646 vss sub ptap1 A=4e-12 P=8e-6 -XM23_130 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1647 vss sub ptap1 A=4e-12 P=8e-6 -XM23_131 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1648 vss sub ptap1 A=4e-12 P=8e-6 -XM23_132 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1649 vss sub ptap1 A=4e-12 P=8e-6 -XM23_133 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1650 vss sub ptap1 A=4e-12 P=8e-6 -XM23_134 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1651 vss sub ptap1 A=4e-12 P=8e-6 -XM23_135 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1652 vss sub ptap1 A=4e-12 P=8e-6 -XM23_136 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1653 vss sub ptap1 A=4e-12 P=8e-6 -XM23_137 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1654 vss sub ptap1 A=4e-12 P=8e-6 -XM23_138 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1655 vss sub ptap1 A=4e-12 P=8e-6 -XM23_139 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1656 vss sub ptap1 A=4e-12 P=8e-6 -XM23_140 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1657 vss sub ptap1 A=4e-12 P=8e-6 -XM23_141 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1658 vss sub ptap1 A=4e-12 P=8e-6 -XM23_142 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1659 vss sub ptap1 A=4e-12 P=8e-6 -XM23_143 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1660 vss sub ptap1 A=4e-12 P=8e-6 -XM23_144 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1661 vss sub ptap1 A=4e-12 P=8e-6 -XM23_145 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1662 vss sub ptap1 A=4e-12 P=8e-6 -XM23_146 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1663 vss sub ptap1 A=4e-12 P=8e-6 -XM23_147 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1664 vss sub ptap1 A=4e-12 P=8e-6 -XM23_148 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1665 vss sub ptap1 A=4e-12 P=8e-6 -XM23_149 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1666 vss sub ptap1 A=4e-12 P=8e-6 -XM23_150 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1667 vss sub ptap1 A=4e-12 P=8e-6 -XM23_151 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1668 vss sub ptap1 A=4e-12 P=8e-6 -XM23_152 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1669 vss sub ptap1 A=4e-12 P=8e-6 -XM23_153 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1670 vss sub ptap1 A=4e-12 P=8e-6 -XM23_154 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1671 vss sub ptap1 A=4e-12 P=8e-6 -XM23_155 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1672 vss sub ptap1 A=4e-12 P=8e-6 -XM23_156 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1673 vss sub ptap1 A=4e-12 P=8e-6 -XM23_157 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1674 vss sub ptap1 A=4e-12 P=8e-6 -XM23_158 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1675 vss sub ptap1 A=4e-12 P=8e-6 -XM23_159 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1676 vss sub ptap1 A=4e-12 P=8e-6 -XM23_160 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1677 vss sub ptap1 A=4e-12 P=8e-6 -XM23_161 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1678 vss sub ptap1 A=4e-12 P=8e-6 -XM23_162 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1679 vss sub ptap1 A=4e-12 P=8e-6 -XM23_163 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1680 vss sub ptap1 A=4e-12 P=8e-6 -XM23_164 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1681 vss sub ptap1 A=4e-12 P=8e-6 -XM23_165 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1682 vss sub ptap1 A=4e-12 P=8e-6 -XM23_166 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1683 vss sub ptap1 A=4e-12 P=8e-6 -XM23_167 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1684 vss sub ptap1 A=4e-12 P=8e-6 -XM23_168 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1685 vss sub ptap1 A=4e-12 P=8e-6 -XM23_169 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1686 vss sub ptap1 A=4e-12 P=8e-6 -XM23_170 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1687 vss sub ptap1 A=4e-12 P=8e-6 -XM23_171 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1688 vss sub ptap1 A=4e-12 P=8e-6 -XM23_172 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1689 vss sub ptap1 A=4e-12 P=8e-6 -XM23_173 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1690 vss sub ptap1 A=4e-12 P=8e-6 -XM23_174 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1691 vss sub ptap1 A=4e-12 P=8e-6 -XM23_175 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1692 vss sub ptap1 A=4e-12 P=8e-6 -XM23_176 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1693 vss sub ptap1 A=4e-12 P=8e-6 -XM23_177 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1694 vss sub ptap1 A=4e-12 P=8e-6 -XM23_178 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1695 vss sub ptap1 A=4e-12 P=8e-6 -XM23_179 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1696 vss sub ptap1 A=4e-12 P=8e-6 -XM23_180 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1697 vss sub ptap1 A=4e-12 P=8e-6 -XM23_181 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1698 vss sub ptap1 A=4e-12 P=8e-6 -XM23_182 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1699 vss sub ptap1 A=4e-12 P=8e-6 -XM23_183 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1700 vss sub ptap1 A=4e-12 P=8e-6 -XM23_184 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1701 vss sub ptap1 A=4e-12 P=8e-6 -XM23_185 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1702 vss sub ptap1 A=4e-12 P=8e-6 -XM23_186 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1703 vss sub ptap1 A=4e-12 P=8e-6 -XM23_187 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1704 vss sub ptap1 A=4e-12 P=8e-6 -XM23_188 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1705 vss sub ptap1 A=4e-12 P=8e-6 -XM23_189 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1706 vss sub ptap1 A=4e-12 P=8e-6 -XM23_190 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1707 vss sub ptap1 A=4e-12 P=8e-6 -XM23_191 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1708 vss sub ptap1 A=4e-12 P=8e-6 -XM23_192 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1709 vss sub ptap1 A=4e-12 P=8e-6 -XM23_193 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1710 vss sub ptap1 A=4e-12 P=8e-6 -XM23_194 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1711 vss sub ptap1 A=4e-12 P=8e-6 -XM23_195 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1712 vss sub ptap1 A=4e-12 P=8e-6 -XM23_196 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1713 vss sub ptap1 A=4e-12 P=8e-6 -XM23_197 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1714 vss sub ptap1 A=4e-12 P=8e-6 -XM23_198 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1715 vss sub ptap1 A=4e-12 P=8e-6 -XM23_199 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1716 vss sub ptap1 A=4e-12 P=8e-6 -XM23_200 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1717 vss sub ptap1 A=4e-12 P=8e-6 -XM23_201 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1718 vss sub ptap1 A=4e-12 P=8e-6 -XM23_202 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT1719 vdd well_1719 ntap1 A=4e-12 P=8e-6 -XM3_0 vb3 net1 vdd well_1719 sg13_lv_pmos w=1u l=1u m=1 -XT1720 vdd well_1720 ntap1 A=4e-12 P=8e-6 -XM3_1 vb3 net1 vdd well_1720 sg13_lv_pmos w=1u l=1u m=1 -XT1721 vdd well_1721 ntap1 A=4e-12 P=8e-6 -XM3_2 vb3 net1 vdd well_1721 sg13_lv_pmos w=1u l=1u m=1 -XT1722 vdd well_1722 ntap1 A=4e-12 P=8e-6 -XM3_3 vb3 net1 vdd well_1722 sg13_lv_pmos w=1u l=1u m=1 -XT1723 vdd well_1723 ntap1 A=4e-12 P=8e-6 -XM3_4 vb3 net1 vdd well_1723 sg13_lv_pmos w=1u l=1u m=1 -XT1724 vdd well_1724 ntap1 A=4e-12 P=8e-6 -XM3_5 vb3 net1 vdd well_1724 sg13_lv_pmos w=1u l=1u m=1 -XT1725 vdd well_1725 ntap1 A=4e-12 P=8e-6 -XM3_6 vb3 net1 vdd well_1725 sg13_lv_pmos w=1u l=1u m=1 -XT1726 vdd well_1726 ntap1 A=4e-12 P=8e-6 -XM3_7 vb3 net1 vdd well_1726 sg13_lv_pmos w=1u l=1u m=1 -XT1727 vdd well_1727 ntap1 A=4e-12 P=8e-6 -XM3_8 vb3 net1 vdd well_1727 sg13_lv_pmos w=1u l=1u m=1 -XT1728 vdd well_1728 ntap1 A=4e-12 P=8e-6 -XM3_9 vb3 net1 vdd well_1728 sg13_lv_pmos w=1u l=1u m=1 -XT1729 vdd well_1729 ntap1 A=4e-12 P=8e-6 -XM3_10 vb3 net1 vdd well_1729 sg13_lv_pmos w=1u l=1u m=1 -XT1730 vdd well_1730 ntap1 A=4e-12 P=8e-6 -XM3_11 vb3 net1 vdd well_1730 sg13_lv_pmos w=1u l=1u m=1 -XT1731 vdd well_1731 ntap1 A=4e-12 P=8e-6 -XM3_12 vb3 net1 vdd well_1731 sg13_lv_pmos w=1u l=1u m=1 -XT1732 vdd well_1732 ntap1 A=4e-12 P=8e-6 -XM3_13 vb3 net1 vdd well_1732 sg13_lv_pmos w=1u l=1u m=1 -XT1733 vdd well_1733 ntap1 A=4e-12 P=8e-6 -XM3_14 vb3 net1 vdd well_1733 sg13_lv_pmos w=1u l=1u m=1 -XT1734 vdd well_1734 ntap1 A=4e-12 P=8e-6 -XM3_15 vb3 net1 vdd well_1734 sg13_lv_pmos w=1u l=1u m=1 -XT1735 vdd well_1735 ntap1 A=4e-12 P=8e-6 -XM3_16 vb3 net1 vdd well_1735 sg13_lv_pmos w=1u l=1u m=1 -XT1736 vdd well_1736 ntap1 A=4e-12 P=8e-6 -XM3_17 vb3 net1 vdd well_1736 sg13_lv_pmos w=1u l=1u m=1 -XT1737 vdd well_1737 ntap1 A=4e-12 P=8e-6 -XM3_18 vb3 net1 vdd well_1737 sg13_lv_pmos w=1u l=1u m=1 -XT1738 vdd well_1738 ntap1 A=4e-12 P=8e-6 -XM3_19 vb3 net1 vdd well_1738 sg13_lv_pmos w=1u l=1u m=1 -XT1739 vdd well_1739 ntap1 A=4e-12 P=8e-6 -XM3_20 vb3 net1 vdd well_1739 sg13_lv_pmos w=1u l=1u m=1 -XT1740 vdd well_1740 ntap1 A=4e-12 P=8e-6 -XM3_21 vb3 net1 vdd well_1740 sg13_lv_pmos w=1u l=1u m=1 -XT1741 vdd well_1741 ntap1 A=4e-12 P=8e-6 -XM3_22 vb3 net1 vdd well_1741 sg13_lv_pmos w=1u l=1u m=1 -XT1742 vdd well_1742 ntap1 A=4e-12 P=8e-6 -XM3_23 vb3 net1 vdd well_1742 sg13_lv_pmos w=1u l=1u m=1 -XT1743 vdd well_1743 ntap1 A=4e-12 P=8e-6 -XM3_24 vb3 net1 vdd well_1743 sg13_lv_pmos w=1u l=1u m=1 -XT1744 vdd well_1744 ntap1 A=4e-12 P=8e-6 -XM3_25 vb3 net1 vdd well_1744 sg13_lv_pmos w=1u l=1u m=1 -XT1745 vdd well_1745 ntap1 A=4e-12 P=8e-6 -XM3_26 vb3 net1 vdd well_1745 sg13_lv_pmos w=1u l=1u m=1 -XT1746 vdd well_1746 ntap1 A=4e-12 P=8e-6 -XM3_27 vb3 net1 vdd well_1746 sg13_lv_pmos w=1u l=1u m=1 -XT1747 vdd well_1747 ntap1 A=4e-12 P=8e-6 -XM3_28 vb3 net1 vdd well_1747 sg13_lv_pmos w=1u l=1u m=1 -XT1748 vdd well_1748 ntap1 A=4e-12 P=8e-6 -XM3_29 vb3 net1 vdd well_1748 sg13_lv_pmos w=1u l=1u m=1 -XT1749 vdd well_1749 ntap1 A=4e-12 P=8e-6 -XM3_30 vb3 net1 vdd well_1749 sg13_lv_pmos w=1u l=1u m=1 -XT1750 vdd well_1750 ntap1 A=4e-12 P=8e-6 -XM3_31 vb3 net1 vdd well_1750 sg13_lv_pmos w=1u l=1u m=1 -XT1751 vdd well_1751 ntap1 A=4e-12 P=8e-6 -XM3_32 vb3 net1 vdd well_1751 sg13_lv_pmos w=1u l=1u m=1 -XT1752 vdd well_1752 ntap1 A=4e-12 P=8e-6 -XM3_33 vb3 net1 vdd well_1752 sg13_lv_pmos w=1u l=1u m=1 -XT1753 vdd well_1753 ntap1 A=4e-12 P=8e-6 -XM3_34 vb3 net1 vdd well_1753 sg13_lv_pmos w=1u l=1u m=1 -XT1754 vdd well_1754 ntap1 A=4e-12 P=8e-6 -XM3_35 vb3 net1 vdd well_1754 sg13_lv_pmos w=1u l=1u m=1 -XT1755 vdd well_1755 ntap1 A=4e-12 P=8e-6 -XM3_36 vb3 net1 vdd well_1755 sg13_lv_pmos w=1u l=1u m=1 -XT1756 vdd well_1756 ntap1 A=4e-12 P=8e-6 -XM3_37 vb3 net1 vdd well_1756 sg13_lv_pmos w=1u l=1u m=1 -XT1757 vdd well_1757 ntap1 A=4e-12 P=8e-6 -XM3_38 vb3 net1 vdd well_1757 sg13_lv_pmos w=1u l=1u m=1 -XT1758 vdd well_1758 ntap1 A=4e-12 P=8e-6 -XM3_39 vb3 net1 vdd well_1758 sg13_lv_pmos w=1u l=1u m=1 -XT1759 vdd well_1759 ntap1 A=4e-12 P=8e-6 -XM3_40 vb3 net1 vdd well_1759 sg13_lv_pmos w=1u l=1u m=1 -XT1760 vdd well_1760 ntap1 A=4e-12 P=8e-6 -XM3_41 vb3 net1 vdd well_1760 sg13_lv_pmos w=1u l=1u m=1 -XT1761 vdd well_1761 ntap1 A=4e-12 P=8e-6 -XM3_42 vb3 net1 vdd well_1761 sg13_lv_pmos w=1u l=1u m=1 -XT1762 vdd well_1762 ntap1 A=4e-12 P=8e-6 -XM3_43 vb3 net1 vdd well_1762 sg13_lv_pmos w=1u l=1u m=1 -XT1763 vdd well_1763 ntap1 A=4e-12 P=8e-6 -XM3_44 vb3 net1 vdd well_1763 sg13_lv_pmos w=1u l=1u m=1 -XT1764 vdd well_1764 ntap1 A=4e-12 P=8e-6 -XM3_45 vb3 net1 vdd well_1764 sg13_lv_pmos w=1u l=1u m=1 -XT1765 vdd well_1765 ntap1 A=4e-12 P=8e-6 -XM3_46 vb3 net1 vdd well_1765 sg13_lv_pmos w=1u l=1u m=1 -XT1766 vdd well_1766 ntap1 A=4e-12 P=8e-6 -XM3_47 vb3 net1 vdd well_1766 sg13_lv_pmos w=1u l=1u m=1 -XT1767 vdd well_1767 ntap1 A=4e-12 P=8e-6 -XM3_48 vb3 net1 vdd well_1767 sg13_lv_pmos w=1u l=1u m=1 -XT1768 vdd well_1768 ntap1 A=4e-12 P=8e-6 -XM3_49 vb3 net1 vdd well_1768 sg13_lv_pmos w=1u l=1u m=1 -XT1769 vdd well_1769 ntap1 A=4e-12 P=8e-6 -XM3_50 vb3 net1 vdd well_1769 sg13_lv_pmos w=1u l=1u m=1 -XT1770 vdd well_1770 ntap1 A=4e-12 P=8e-6 -XM3_51 vb3 net1 vdd well_1770 sg13_lv_pmos w=1u l=1u m=1 -XT1771 vdd well_1771 ntap1 A=4e-12 P=8e-6 -XM3_52 vb3 net1 vdd well_1771 sg13_lv_pmos w=1u l=1u m=1 -XT1772 vdd well_1772 ntap1 A=4e-12 P=8e-6 -XM3_53 vb3 net1 vdd well_1772 sg13_lv_pmos w=1u l=1u m=1 -XT1773 vdd well_1773 ntap1 A=4e-12 P=8e-6 -XM3_54 vb3 net1 vdd well_1773 sg13_lv_pmos w=1u l=1u m=1 -XT1774 vdd well_1774 ntap1 A=4e-12 P=8e-6 -XM3_55 vb3 net1 vdd well_1774 sg13_lv_pmos w=1u l=1u m=1 -XT1775 vdd well_1775 ntap1 A=4e-12 P=8e-6 -XM3_56 vb3 net1 vdd well_1775 sg13_lv_pmos w=1u l=1u m=1 -XT1776 vdd well_1776 ntap1 A=4e-12 P=8e-6 -XM3_57 vb3 net1 vdd well_1776 sg13_lv_pmos w=1u l=1u m=1 -XT1777 vdd well_1777 ntap1 A=4e-12 P=8e-6 -XM3_58 vb3 net1 vdd well_1777 sg13_lv_pmos w=1u l=1u m=1 -XT1778 vdd well_1778 ntap1 A=4e-12 P=8e-6 -XM3_59 vb3 net1 vdd well_1778 sg13_lv_pmos w=1u l=1u m=1 -XT1779 vdd well_1779 ntap1 A=4e-12 P=8e-6 -XM3_60 vb3 net1 vdd well_1779 sg13_lv_pmos w=1u l=1u m=1 -XT1780 vdd well_1780 ntap1 A=4e-12 P=8e-6 -XM3_61 vb3 net1 vdd well_1780 sg13_lv_pmos w=1u l=1u m=1 -XT1781 vdd well_1781 ntap1 A=4e-12 P=8e-6 -XM3_62 vb3 net1 vdd well_1781 sg13_lv_pmos w=1u l=1u m=1 -XT1782 vdd well_1782 ntap1 A=4e-12 P=8e-6 -XM3_63 vb3 net1 vdd well_1782 sg13_lv_pmos w=1u l=1u m=1 -XT1783 vdd well_1783 ntap1 A=4e-12 P=8e-6 -XM3_64 vb3 net1 vdd well_1783 sg13_lv_pmos w=1u l=1u m=1 -XT1784 vdd well_1784 ntap1 A=4e-12 P=8e-6 -XM3_65 vb3 net1 vdd well_1784 sg13_lv_pmos w=1u l=1u m=1 -XT1785 vdd well_1785 ntap1 A=4e-12 P=8e-6 -XM3_66 vb3 net1 vdd well_1785 sg13_lv_pmos w=1u l=1u m=1 -XT1786 vdd well_1786 ntap1 A=4e-12 P=8e-6 -XM3_67 vb3 net1 vdd well_1786 sg13_lv_pmos w=1u l=1u m=1 -XT1787 vdd well_1787 ntap1 A=4e-12 P=8e-6 -XM3_68 vb3 net1 vdd well_1787 sg13_lv_pmos w=1u l=1u m=1 -XT1788 vdd well_1788 ntap1 A=4e-12 P=8e-6 -XM3_69 vb3 net1 vdd well_1788 sg13_lv_pmos w=1u l=1u m=1 -XT1789 vdd well_1789 ntap1 A=4e-12 P=8e-6 -XM3_70 vb3 net1 vdd well_1789 sg13_lv_pmos w=1u l=1u m=1 -XT1790 vdd well_1790 ntap1 A=4e-12 P=8e-6 -XM4_0 net31 net1 vdd well_1790 sg13_lv_pmos w=1u l=1u m=1 -XT1791 vdd well_1791 ntap1 A=4e-12 P=8e-6 -XM4_1 net31 net1 vdd well_1791 sg13_lv_pmos w=1u l=1u m=1 -XT1792 vdd well_1792 ntap1 A=4e-12 P=8e-6 -XM4_2 net31 net1 vdd well_1792 sg13_lv_pmos w=1u l=1u m=1 -XT1793 vdd well_1793 ntap1 A=4e-12 P=8e-6 -XM4_3 net31 net1 vdd well_1793 sg13_lv_pmos w=1u l=1u m=1 -XT1794 vdd well_1794 ntap1 A=4e-12 P=8e-6 -XM4_4 net31 net1 vdd well_1794 sg13_lv_pmos w=1u l=1u m=1 -XT1795 vdd well_1795 ntap1 A=4e-12 P=8e-6 -XM4_5 net31 net1 vdd well_1795 sg13_lv_pmos w=1u l=1u m=1 -XT1796 vdd well_1796 ntap1 A=4e-12 P=8e-6 -XM4_6 net31 net1 vdd well_1796 sg13_lv_pmos w=1u l=1u m=1 -XT1797 vdd well_1797 ntap1 A=4e-12 P=8e-6 -XM4_7 net31 net1 vdd well_1797 sg13_lv_pmos w=1u l=1u m=1 -XT1798 vdd well_1798 ntap1 A=4e-12 P=8e-6 -XM4_8 net31 net1 vdd well_1798 sg13_lv_pmos w=1u l=1u m=1 -XT1799 vdd well_1799 ntap1 A=4e-12 P=8e-6 -XM4_9 net31 net1 vdd well_1799 sg13_lv_pmos w=1u l=1u m=1 -XT1800 vdd well_1800 ntap1 A=4e-12 P=8e-6 -XM4_10 net31 net1 vdd well_1800 sg13_lv_pmos w=1u l=1u m=1 -XT1801 vdd well_1801 ntap1 A=4e-12 P=8e-6 -XM4_11 net31 net1 vdd well_1801 sg13_lv_pmos w=1u l=1u m=1 -XT1802 vdd well_1802 ntap1 A=4e-12 P=8e-6 -XM4_12 net31 net1 vdd well_1802 sg13_lv_pmos w=1u l=1u m=1 -XT1803 vdd well_1803 ntap1 A=4e-12 P=8e-6 -XM4_13 net31 net1 vdd well_1803 sg13_lv_pmos w=1u l=1u m=1 -XT1804 vdd well_1804 ntap1 A=4e-12 P=8e-6 -XM4_14 net31 net1 vdd well_1804 sg13_lv_pmos w=1u l=1u m=1 -XT1805 vdd well_1805 ntap1 A=4e-12 P=8e-6 -XM4_15 net31 net1 vdd well_1805 sg13_lv_pmos w=1u l=1u m=1 -XT1806 vdd well_1806 ntap1 A=4e-12 P=8e-6 -XM4_16 net31 net1 vdd well_1806 sg13_lv_pmos w=1u l=1u m=1 -XT1807 vdd well_1807 ntap1 A=4e-12 P=8e-6 -XM4_17 net31 net1 vdd well_1807 sg13_lv_pmos w=1u l=1u m=1 -XT1808 vdd well_1808 ntap1 A=4e-12 P=8e-6 -XM4_18 net31 net1 vdd well_1808 sg13_lv_pmos w=1u l=1u m=1 -XT1809 vdd well_1809 ntap1 A=4e-12 P=8e-6 -XM4_19 net31 net1 vdd well_1809 sg13_lv_pmos w=1u l=1u m=1 -XT1810 vdd well_1810 ntap1 A=4e-12 P=8e-6 -XM4_20 net31 net1 vdd well_1810 sg13_lv_pmos w=1u l=1u m=1 -XT1811 vdd well_1811 ntap1 A=4e-12 P=8e-6 -XM4_21 net31 net1 vdd well_1811 sg13_lv_pmos w=1u l=1u m=1 -XT1812 vdd well_1812 ntap1 A=4e-12 P=8e-6 -XM4_22 net31 net1 vdd well_1812 sg13_lv_pmos w=1u l=1u m=1 -XT1813 vdd well_1813 ntap1 A=4e-12 P=8e-6 -XM4_23 net31 net1 vdd well_1813 sg13_lv_pmos w=1u l=1u m=1 -XT1814 vdd well_1814 ntap1 A=4e-12 P=8e-6 -XM4_24 net31 net1 vdd well_1814 sg13_lv_pmos w=1u l=1u m=1 -XT1815 vdd well_1815 ntap1 A=4e-12 P=8e-6 -XM4_25 net31 net1 vdd well_1815 sg13_lv_pmos w=1u l=1u m=1 -XT1816 vdd well_1816 ntap1 A=4e-12 P=8e-6 -XM4_26 net31 net1 vdd well_1816 sg13_lv_pmos w=1u l=1u m=1 -XT1817 vdd well_1817 ntap1 A=4e-12 P=8e-6 -XM4_27 net31 net1 vdd well_1817 sg13_lv_pmos w=1u l=1u m=1 -XT1818 vdd well_1818 ntap1 A=4e-12 P=8e-6 -XM4_28 net31 net1 vdd well_1818 sg13_lv_pmos w=1u l=1u m=1 -XT1819 vdd well_1819 ntap1 A=4e-12 P=8e-6 -XM4_29 net31 net1 vdd well_1819 sg13_lv_pmos w=1u l=1u m=1 -XT1820 vdd well_1820 ntap1 A=4e-12 P=8e-6 -XM4_30 net31 net1 vdd well_1820 sg13_lv_pmos w=1u l=1u m=1 -XT1821 vdd well_1821 ntap1 A=4e-12 P=8e-6 -XM4_31 net31 net1 vdd well_1821 sg13_lv_pmos w=1u l=1u m=1 -XT1822 vdd well_1822 ntap1 A=4e-12 P=8e-6 -XM4_32 net31 net1 vdd well_1822 sg13_lv_pmos w=1u l=1u m=1 -XT1823 vdd well_1823 ntap1 A=4e-12 P=8e-6 -XM4_33 net31 net1 vdd well_1823 sg13_lv_pmos w=1u l=1u m=1 -XT1824 vdd well_1824 ntap1 A=4e-12 P=8e-6 -XM4_34 net31 net1 vdd well_1824 sg13_lv_pmos w=1u l=1u m=1 -XT1825 vdd well_1825 ntap1 A=4e-12 P=8e-6 -XM4_35 net31 net1 vdd well_1825 sg13_lv_pmos w=1u l=1u m=1 -XT1826 vdd well_1826 ntap1 A=4e-12 P=8e-6 -XM4_36 net31 net1 vdd well_1826 sg13_lv_pmos w=1u l=1u m=1 -XT1827 vdd well_1827 ntap1 A=4e-12 P=8e-6 -XM4_37 net31 net1 vdd well_1827 sg13_lv_pmos w=1u l=1u m=1 -XT1828 vdd well_1828 ntap1 A=4e-12 P=8e-6 -XM4_38 net31 net1 vdd well_1828 sg13_lv_pmos w=1u l=1u m=1 -XT1829 vdd well_1829 ntap1 A=4e-12 P=8e-6 -XM4_39 net31 net1 vdd well_1829 sg13_lv_pmos w=1u l=1u m=1 -XT1830 vdd well_1830 ntap1 A=4e-12 P=8e-6 -XM4_40 net31 net1 vdd well_1830 sg13_lv_pmos w=1u l=1u m=1 -XT1831 vdd well_1831 ntap1 A=4e-12 P=8e-6 -XM4_41 net31 net1 vdd well_1831 sg13_lv_pmos w=1u l=1u m=1 -XT1832 vdd well_1832 ntap1 A=4e-12 P=8e-6 -XM4_42 net31 net1 vdd well_1832 sg13_lv_pmos w=1u l=1u m=1 -XT1833 vdd well_1833 ntap1 A=4e-12 P=8e-6 -XM4_43 net31 net1 vdd well_1833 sg13_lv_pmos w=1u l=1u m=1 -XT1834 vdd well_1834 ntap1 A=4e-12 P=8e-6 -XM4_44 net31 net1 vdd well_1834 sg13_lv_pmos w=1u l=1u m=1 -XT1835 vdd well_1835 ntap1 A=4e-12 P=8e-6 -XM4_45 net31 net1 vdd well_1835 sg13_lv_pmos w=1u l=1u m=1 -XT1836 vdd well_1836 ntap1 A=4e-12 P=8e-6 -XM4_46 net31 net1 vdd well_1836 sg13_lv_pmos w=1u l=1u m=1 -XT1837 vdd well_1837 ntap1 A=4e-12 P=8e-6 -XM4_47 net31 net1 vdd well_1837 sg13_lv_pmos w=1u l=1u m=1 -XT1838 vdd well_1838 ntap1 A=4e-12 P=8e-6 -XM4_48 net31 net1 vdd well_1838 sg13_lv_pmos w=1u l=1u m=1 -XT1839 vdd well_1839 ntap1 A=4e-12 P=8e-6 -XM4_49 net31 net1 vdd well_1839 sg13_lv_pmos w=1u l=1u m=1 -XT1840 vdd well_1840 ntap1 A=4e-12 P=8e-6 -XM4_50 net31 net1 vdd well_1840 sg13_lv_pmos w=1u l=1u m=1 -XT1841 vdd well_1841 ntap1 A=4e-12 P=8e-6 -XM4_51 net31 net1 vdd well_1841 sg13_lv_pmos w=1u l=1u m=1 -XT1842 vdd well_1842 ntap1 A=4e-12 P=8e-6 -XM4_52 net31 net1 vdd well_1842 sg13_lv_pmos w=1u l=1u m=1 -XT1843 vdd well_1843 ntap1 A=4e-12 P=8e-6 -XM4_53 net31 net1 vdd well_1843 sg13_lv_pmos w=1u l=1u m=1 -XT1844 vdd well_1844 ntap1 A=4e-12 P=8e-6 -XM4_54 net31 net1 vdd well_1844 sg13_lv_pmos w=1u l=1u m=1 -XT1845 vdd well_1845 ntap1 A=4e-12 P=8e-6 -XM4_55 net31 net1 vdd well_1845 sg13_lv_pmos w=1u l=1u m=1 -XT1846 vdd well_1846 ntap1 A=4e-12 P=8e-6 -XM4_56 net31 net1 vdd well_1846 sg13_lv_pmos w=1u l=1u m=1 -XT1847 vdd well_1847 ntap1 A=4e-12 P=8e-6 -XM4_57 net31 net1 vdd well_1847 sg13_lv_pmos w=1u l=1u m=1 -XT1848 vdd well_1848 ntap1 A=4e-12 P=8e-6 -XM4_58 net31 net1 vdd well_1848 sg13_lv_pmos w=1u l=1u m=1 -XT1849 vdd well_1849 ntap1 A=4e-12 P=8e-6 -XM4_59 net31 net1 vdd well_1849 sg13_lv_pmos w=1u l=1u m=1 -XT1850 vdd well_1850 ntap1 A=4e-12 P=8e-6 -XM4_60 net31 net1 vdd well_1850 sg13_lv_pmos w=1u l=1u m=1 -XT1851 vdd well_1851 ntap1 A=4e-12 P=8e-6 -XM4_61 net31 net1 vdd well_1851 sg13_lv_pmos w=1u l=1u m=1 -XT1852 vdd well_1852 ntap1 A=4e-12 P=8e-6 -XM4_62 net31 net1 vdd well_1852 sg13_lv_pmos w=1u l=1u m=1 -XT1853 vdd well_1853 ntap1 A=4e-12 P=8e-6 -XM4_63 net31 net1 vdd well_1853 sg13_lv_pmos w=1u l=1u m=1 -XT1854 vdd well_1854 ntap1 A=4e-12 P=8e-6 -XM4_64 net31 net1 vdd well_1854 sg13_lv_pmos w=1u l=1u m=1 -XT1855 vdd well_1855 ntap1 A=4e-12 P=8e-6 -XM4_65 net31 net1 vdd well_1855 sg13_lv_pmos w=1u l=1u m=1 -XT1856 vdd well_1856 ntap1 A=4e-12 P=8e-6 -XM4_66 net31 net1 vdd well_1856 sg13_lv_pmos w=1u l=1u m=1 -XT1857 vdd well_1857 ntap1 A=4e-12 P=8e-6 -XM4_67 net31 net1 vdd well_1857 sg13_lv_pmos w=1u l=1u m=1 -XT1858 vdd well_1858 ntap1 A=4e-12 P=8e-6 -XM4_68 net31 net1 vdd well_1858 sg13_lv_pmos w=1u l=1u m=1 -XT1859 vdd well_1859 ntap1 A=4e-12 P=8e-6 -XM4_69 net31 net1 vdd well_1859 sg13_lv_pmos w=1u l=1u m=1 -XT1860 vdd well_1860 ntap1 A=4e-12 P=8e-6 -XM4_70 net31 net1 vdd well_1860 sg13_lv_pmos w=1u l=1u m=1 -XT1861 vdd well_1861 ntap1 A=4e-12 P=8e-6 -XM4_71 net31 net1 vdd well_1861 sg13_lv_pmos w=1u l=1u m=1 -XT1862 vdd well_1862 ntap1 A=4e-12 P=8e-6 -XM4_72 net31 net1 vdd well_1862 sg13_lv_pmos w=1u l=1u m=1 -XT1863 vdd well_1863 ntap1 A=4e-12 P=8e-6 -XM4_73 net31 net1 vdd well_1863 sg13_lv_pmos w=1u l=1u m=1 -XT1864 vdd well_1864 ntap1 A=4e-12 P=8e-6 -XM4_74 net31 net1 vdd well_1864 sg13_lv_pmos w=1u l=1u m=1 -XT1865 vdd well_1865 ntap1 A=4e-12 P=8e-6 -XM4_75 net31 net1 vdd well_1865 sg13_lv_pmos w=1u l=1u m=1 -XT1866 vdd well_1866 ntap1 A=4e-12 P=8e-6 -XM4_76 net31 net1 vdd well_1866 sg13_lv_pmos w=1u l=1u m=1 -XT1867 vdd well_1867 ntap1 A=4e-12 P=8e-6 -XM4_77 net31 net1 vdd well_1867 sg13_lv_pmos w=1u l=1u m=1 -XT1868 vdd well_1868 ntap1 A=4e-12 P=8e-6 -XM4_78 net31 net1 vdd well_1868 sg13_lv_pmos w=1u l=1u m=1 -XT1869 vdd well_1869 ntap1 A=4e-12 P=8e-6 -XM4_79 net31 net1 vdd well_1869 sg13_lv_pmos w=1u l=1u m=1 -XT1870 vdd well_1870 ntap1 A=4e-12 P=8e-6 -XM4_80 net31 net1 vdd well_1870 sg13_lv_pmos w=1u l=1u m=1 -XT1871 vdd well_1871 ntap1 A=4e-12 P=8e-6 -XM4_81 net31 net1 vdd well_1871 sg13_lv_pmos w=1u l=1u m=1 -XT1872 vdd well_1872 ntap1 A=4e-12 P=8e-6 -XM4_82 net31 net1 vdd well_1872 sg13_lv_pmos w=1u l=1u m=1 -XT1873 vdd well_1873 ntap1 A=4e-12 P=8e-6 -XM4_83 net31 net1 vdd well_1873 sg13_lv_pmos w=1u l=1u m=1 -XT1874 vdd well_1874 ntap1 A=4e-12 P=8e-6 -XM4_84 net31 net1 vdd well_1874 sg13_lv_pmos w=1u l=1u m=1 -XT1875 vdd well_1875 ntap1 A=4e-12 P=8e-6 -XM4_85 net31 net1 vdd well_1875 sg13_lv_pmos w=1u l=1u m=1 -XT1876 vdd well_1876 ntap1 A=4e-12 P=8e-6 -XM4_86 net31 net1 vdd well_1876 sg13_lv_pmos w=1u l=1u m=1 -XT1877 vdd well_1877 ntap1 A=4e-12 P=8e-6 -XM4_87 net31 net1 vdd well_1877 sg13_lv_pmos w=1u l=1u m=1 -XT1878 vdd well_1878 ntap1 A=4e-12 P=8e-6 -XM4_88 net31 net1 vdd well_1878 sg13_lv_pmos w=1u l=1u m=1 -XT1879 vdd well_1879 ntap1 A=4e-12 P=8e-6 -XM4_89 net31 net1 vdd well_1879 sg13_lv_pmos w=1u l=1u m=1 -XT1880 vdd well_1880 ntap1 A=4e-12 P=8e-6 -XM4_90 net31 net1 vdd well_1880 sg13_lv_pmos w=1u l=1u m=1 -XT1881 vdd well_1881 ntap1 A=4e-12 P=8e-6 -XM4_91 net31 net1 vdd well_1881 sg13_lv_pmos w=1u l=1u m=1 -XT1882 vdd well_1882 ntap1 A=4e-12 P=8e-6 -XM4_92 net31 net1 vdd well_1882 sg13_lv_pmos w=1u l=1u m=1 -XT1883 vdd well_1883 ntap1 A=4e-12 P=8e-6 -XM4_93 net31 net1 vdd well_1883 sg13_lv_pmos w=1u l=1u m=1 -XT1884 vdd well_1884 ntap1 A=4e-12 P=8e-6 -XM4_94 net31 net1 vdd well_1884 sg13_lv_pmos w=1u l=1u m=1 -XT1885 vdd well_1885 ntap1 A=4e-12 P=8e-6 -XM4_95 net31 net1 vdd well_1885 sg13_lv_pmos w=1u l=1u m=1 -XT1886 vdd well_1886 ntap1 A=4e-12 P=8e-6 -XM4_96 net31 net1 vdd well_1886 sg13_lv_pmos w=1u l=1u m=1 -XT1887 vdd well_1887 ntap1 A=4e-12 P=8e-6 -XM4_97 net31 net1 vdd well_1887 sg13_lv_pmos w=1u l=1u m=1 -XT1888 vdd well_1888 ntap1 A=4e-12 P=8e-6 -XM4_98 net31 net1 vdd well_1888 sg13_lv_pmos w=1u l=1u m=1 -XT1889 vdd well_1889 ntap1 A=4e-12 P=8e-6 -XM4_99 net31 net1 vdd well_1889 sg13_lv_pmos w=1u l=1u m=1 -XT1890 vdd well_1890 ntap1 A=4e-12 P=8e-6 -XM4_100 net31 net1 vdd well_1890 sg13_lv_pmos w=1u l=1u m=1 -XT1891 vdd well_1891 ntap1 A=4e-12 P=8e-6 -XM4_101 net31 net1 vdd well_1891 sg13_lv_pmos w=1u l=1u m=1 -XT1892 vdd well_1892 ntap1 A=4e-12 P=8e-6 -XM4_102 net31 net1 vdd well_1892 sg13_lv_pmos w=1u l=1u m=1 -XT1893 vdd well_1893 ntap1 A=4e-12 P=8e-6 -XM4_103 net31 net1 vdd well_1893 sg13_lv_pmos w=1u l=1u m=1 -XT1894 vdd well_1894 ntap1 A=4e-12 P=8e-6 -XM4_104 net31 net1 vdd well_1894 sg13_lv_pmos w=1u l=1u m=1 -XT1895 vdd well_1895 ntap1 A=4e-12 P=8e-6 -XM4_105 net31 net1 vdd well_1895 sg13_lv_pmos w=1u l=1u m=1 -XT1896 vdd well_1896 ntap1 A=4e-12 P=8e-6 -XM4_106 net31 net1 vdd well_1896 sg13_lv_pmos w=1u l=1u m=1 -XT1897 vdd well_1897 ntap1 A=4e-12 P=8e-6 -XM4_107 net31 net1 vdd well_1897 sg13_lv_pmos w=1u l=1u m=1 -XT1898 vdd well_1898 ntap1 A=4e-12 P=8e-6 -XM4_108 net31 net1 vdd well_1898 sg13_lv_pmos w=1u l=1u m=1 -XT1899 vdd well_1899 ntap1 A=4e-12 P=8e-6 -XM4_109 net31 net1 vdd well_1899 sg13_lv_pmos w=1u l=1u m=1 -XT1900 vdd well_1900 ntap1 A=4e-12 P=8e-6 -XM4_110 net31 net1 vdd well_1900 sg13_lv_pmos w=1u l=1u m=1 -XT1901 vdd well_1901 ntap1 A=4e-12 P=8e-6 -XM4_111 net31 net1 vdd well_1901 sg13_lv_pmos w=1u l=1u m=1 -XT1902 vdd well_1902 ntap1 A=4e-12 P=8e-6 -XM4_112 net31 net1 vdd well_1902 sg13_lv_pmos w=1u l=1u m=1 -XT1903 vdd well_1903 ntap1 A=4e-12 P=8e-6 -XM4_113 net31 net1 vdd well_1903 sg13_lv_pmos w=1u l=1u m=1 -XT1904 vdd well_1904 ntap1 A=4e-12 P=8e-6 -XM4_114 net31 net1 vdd well_1904 sg13_lv_pmos w=1u l=1u m=1 -XT1905 vdd well_1905 ntap1 A=4e-12 P=8e-6 -XM4_115 net31 net1 vdd well_1905 sg13_lv_pmos w=1u l=1u m=1 -XT1906 vdd well_1906 ntap1 A=4e-12 P=8e-6 -XM4_116 net31 net1 vdd well_1906 sg13_lv_pmos w=1u l=1u m=1 -XT1907 vdd well_1907 ntap1 A=4e-12 P=8e-6 -XM4_117 net31 net1 vdd well_1907 sg13_lv_pmos w=1u l=1u m=1 -XT1908 vdd well_1908 ntap1 A=4e-12 P=8e-6 -XM4_118 net31 net1 vdd well_1908 sg13_lv_pmos w=1u l=1u m=1 -XT1909 vdd well_1909 ntap1 A=4e-12 P=8e-6 -XM4_119 net31 net1 vdd well_1909 sg13_lv_pmos w=1u l=1u m=1 -XT1910 vdd well_1910 ntap1 A=4e-12 P=8e-6 -XM4_120 net31 net1 vdd well_1910 sg13_lv_pmos w=1u l=1u m=1 -XT1911 vdd well_1911 ntap1 A=4e-12 P=8e-6 -XM4_121 net31 net1 vdd well_1911 sg13_lv_pmos w=1u l=1u m=1 -XT1912 vdd well_1912 ntap1 A=4e-12 P=8e-6 -XM4_122 net31 net1 vdd well_1912 sg13_lv_pmos w=1u l=1u m=1 -XT1913 vdd well_1913 ntap1 A=4e-12 P=8e-6 -XM4_123 net31 net1 vdd well_1913 sg13_lv_pmos w=1u l=1u m=1 -XT1914 vdd well_1914 ntap1 A=4e-12 P=8e-6 -XM4_124 net31 net1 vdd well_1914 sg13_lv_pmos w=1u l=1u m=1 -XT1915 vdd well_1915 ntap1 A=4e-12 P=8e-6 -XM4_125 net31 net1 vdd well_1915 sg13_lv_pmos w=1u l=1u m=1 -XT1916 vdd well_1916 ntap1 A=4e-12 P=8e-6 -XM4_126 net31 net1 vdd well_1916 sg13_lv_pmos w=1u l=1u m=1 -XT1917 vdd well_1917 ntap1 A=4e-12 P=8e-6 -XM4_127 net31 net1 vdd well_1917 sg13_lv_pmos w=1u l=1u m=1 -XT1918 vdd well_1918 ntap1 A=4e-12 P=8e-6 -XM4_128 net31 net1 vdd well_1918 sg13_lv_pmos w=1u l=1u m=1 -XT1919 vdd well_1919 ntap1 A=4e-12 P=8e-6 -XM4_129 net31 net1 vdd well_1919 sg13_lv_pmos w=1u l=1u m=1 -XT1920 vdd well_1920 ntap1 A=4e-12 P=8e-6 -XM4_130 net31 net1 vdd well_1920 sg13_lv_pmos w=1u l=1u m=1 -XT1921 vdd well_1921 ntap1 A=4e-12 P=8e-6 -XM4_131 net31 net1 vdd well_1921 sg13_lv_pmos w=1u l=1u m=1 -XT1922 vdd well_1922 ntap1 A=4e-12 P=8e-6 -XM4_132 net31 net1 vdd well_1922 sg13_lv_pmos w=1u l=1u m=1 -XT1923 vdd well_1923 ntap1 A=4e-12 P=8e-6 -XM4_133 net31 net1 vdd well_1923 sg13_lv_pmos w=1u l=1u m=1 -XT1924 vdd well_1924 ntap1 A=4e-12 P=8e-6 -XM4_134 net31 net1 vdd well_1924 sg13_lv_pmos w=1u l=1u m=1 -XT1925 vdd well_1925 ntap1 A=4e-12 P=8e-6 -XM4_135 net31 net1 vdd well_1925 sg13_lv_pmos w=1u l=1u m=1 -XT1926 vdd well_1926 ntap1 A=4e-12 P=8e-6 -XM4_136 net31 net1 vdd well_1926 sg13_lv_pmos w=1u l=1u m=1 -XT1927 vdd well_1927 ntap1 A=4e-12 P=8e-6 -XM4_137 net31 net1 vdd well_1927 sg13_lv_pmos w=1u l=1u m=1 -XT1928 vdd well_1928 ntap1 A=4e-12 P=8e-6 -XM4_138 net31 net1 vdd well_1928 sg13_lv_pmos w=1u l=1u m=1 -XT1929 vdd well_1929 ntap1 A=4e-12 P=8e-6 -XM4_139 net31 net1 vdd well_1929 sg13_lv_pmos w=1u l=1u m=1 -XT1930 vdd well_1930 ntap1 A=4e-12 P=8e-6 -XM4_140 net31 net1 vdd well_1930 sg13_lv_pmos w=1u l=1u m=1 -XT1931 vdd well_1931 ntap1 A=4e-12 P=8e-6 -XM4_141 net31 net1 vdd well_1931 sg13_lv_pmos w=1u l=1u m=1 -XT1932 vdd well_1932 ntap1 A=4e-12 P=8e-6 -XM4_142 net31 net1 vdd well_1932 sg13_lv_pmos w=1u l=1u m=1 -XT1933 vdd well_1933 ntap1 A=4e-12 P=8e-6 -XM4_143 net31 net1 vdd well_1933 sg13_lv_pmos w=1u l=1u m=1 -XT1934 vdd well_1934 ntap1 A=4e-12 P=8e-6 -XM4_144 net31 net1 vdd well_1934 sg13_lv_pmos w=1u l=1u m=1 -XT1935 vdd well_1935 ntap1 A=4e-12 P=8e-6 -XM4_145 net31 net1 vdd well_1935 sg13_lv_pmos w=1u l=1u m=1 -XT1936 vdd well_1936 ntap1 A=4e-12 P=8e-6 -XM4_146 net31 net1 vdd well_1936 sg13_lv_pmos w=1u l=1u m=1 -XT1937 vdd well_1937 ntap1 A=4e-12 P=8e-6 -XM4_147 net31 net1 vdd well_1937 sg13_lv_pmos w=1u l=1u m=1 -XT1938 vdd well_1938 ntap1 A=4e-12 P=8e-6 -XM4_148 net31 net1 vdd well_1938 sg13_lv_pmos w=1u l=1u m=1 -XT1939 vdd well_1939 ntap1 A=4e-12 P=8e-6 -XM4_149 net31 net1 vdd well_1939 sg13_lv_pmos w=1u l=1u m=1 -XT1940 vdd well_1940 ntap1 A=4e-12 P=8e-6 -XM4_150 net31 net1 vdd well_1940 sg13_lv_pmos w=1u l=1u m=1 -XT1941 vdd well_1941 ntap1 A=4e-12 P=8e-6 -XM4_151 net31 net1 vdd well_1941 sg13_lv_pmos w=1u l=1u m=1 -XT1942 vdd well_1942 ntap1 A=4e-12 P=8e-6 -XM4_152 net31 net1 vdd well_1942 sg13_lv_pmos w=1u l=1u m=1 -XT1943 vdd well_1943 ntap1 A=4e-12 P=8e-6 -XM4_153 net31 net1 vdd well_1943 sg13_lv_pmos w=1u l=1u m=1 -XT1944 vdd well_1944 ntap1 A=4e-12 P=8e-6 -XM4_154 net31 net1 vdd well_1944 sg13_lv_pmos w=1u l=1u m=1 -XT1945 vdd well_1945 ntap1 A=4e-12 P=8e-6 -XM4_155 net31 net1 vdd well_1945 sg13_lv_pmos w=1u l=1u m=1 -XT1946 vdd well_1946 ntap1 A=4e-12 P=8e-6 -XM4_156 net31 net1 vdd well_1946 sg13_lv_pmos w=1u l=1u m=1 -XT1947 vdd well_1947 ntap1 A=4e-12 P=8e-6 -XM4_157 net31 net1 vdd well_1947 sg13_lv_pmos w=1u l=1u m=1 -XT1948 vdd well_1948 ntap1 A=4e-12 P=8e-6 -XM4_158 net31 net1 vdd well_1948 sg13_lv_pmos w=1u l=1u m=1 -XT1949 vdd well_1949 ntap1 A=4e-12 P=8e-6 -XM4_159 net31 net1 vdd well_1949 sg13_lv_pmos w=1u l=1u m=1 -XT1950 vdd well_1950 ntap1 A=4e-12 P=8e-6 -XM4_160 net31 net1 vdd well_1950 sg13_lv_pmos w=1u l=1u m=1 -XT1951 vdd well_1951 ntap1 A=4e-12 P=8e-6 -XM4_161 net31 net1 vdd well_1951 sg13_lv_pmos w=1u l=1u m=1 -XT1952 vdd well_1952 ntap1 A=4e-12 P=8e-6 -XM4_162 net31 net1 vdd well_1952 sg13_lv_pmos w=1u l=1u m=1 -XT1953 vdd well_1953 ntap1 A=4e-12 P=8e-6 -XM4_163 net31 net1 vdd well_1953 sg13_lv_pmos w=1u l=1u m=1 -XT1954 vdd well_1954 ntap1 A=4e-12 P=8e-6 -XM4_164 net31 net1 vdd well_1954 sg13_lv_pmos w=1u l=1u m=1 -XT1955 vdd well_1955 ntap1 A=4e-12 P=8e-6 -XM4_165 net31 net1 vdd well_1955 sg13_lv_pmos w=1u l=1u m=1 -XT1956 vdd well_1956 ntap1 A=4e-12 P=8e-6 -XM4_166 net31 net1 vdd well_1956 sg13_lv_pmos w=1u l=1u m=1 -XT1957 vdd well_1957 ntap1 A=4e-12 P=8e-6 -XM4_167 net31 net1 vdd well_1957 sg13_lv_pmos w=1u l=1u m=1 -XT1958 vdd well_1958 ntap1 A=4e-12 P=8e-6 -XM4_168 net31 net1 vdd well_1958 sg13_lv_pmos w=1u l=1u m=1 -XT1959 vdd well_1959 ntap1 A=4e-12 P=8e-6 -XM4_169 net31 net1 vdd well_1959 sg13_lv_pmos w=1u l=1u m=1 -XT1960 vdd well_1960 ntap1 A=4e-12 P=8e-6 -XM4_170 net31 net1 vdd well_1960 sg13_lv_pmos w=1u l=1u m=1 -XT1961 vdd well_1961 ntap1 A=4e-12 P=8e-6 -XM4_171 net31 net1 vdd well_1961 sg13_lv_pmos w=1u l=1u m=1 -XT1962 vdd well_1962 ntap1 A=4e-12 P=8e-6 -XM4_172 net31 net1 vdd well_1962 sg13_lv_pmos w=1u l=1u m=1 -XT1963 vdd well_1963 ntap1 A=4e-12 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m=1 -XT1973 vdd well_1973 ntap1 A=4e-12 P=8e-6 -XM4_183 net31 net1 vdd well_1973 sg13_lv_pmos w=1u l=1u m=1 -XT1974 vdd well_1974 ntap1 A=4e-12 P=8e-6 -XM4_184 net31 net1 vdd well_1974 sg13_lv_pmos w=1u l=1u m=1 -XT1975 vdd well_1975 ntap1 A=4e-12 P=8e-6 -XM4_185 net31 net1 vdd well_1975 sg13_lv_pmos w=1u l=1u m=1 -XT1976 vdd well_1976 ntap1 A=4e-12 P=8e-6 -XM4_186 net31 net1 vdd well_1976 sg13_lv_pmos w=1u l=1u m=1 -XT1977 vdd well_1977 ntap1 A=4e-12 P=8e-6 -XM4_187 net31 net1 vdd well_1977 sg13_lv_pmos w=1u l=1u m=1 -XT1978 vdd well_1978 ntap1 A=4e-12 P=8e-6 -XM4_188 net31 net1 vdd well_1978 sg13_lv_pmos w=1u l=1u m=1 -XT1979 vdd well_1979 ntap1 A=4e-12 P=8e-6 -XM4_189 net31 net1 vdd well_1979 sg13_lv_pmos w=1u l=1u m=1 -XT1980 vdd well_1980 ntap1 A=4e-12 P=8e-6 -XM4_190 net31 net1 vdd well_1980 sg13_lv_pmos w=1u l=1u m=1 -XT1981 vdd well_1981 ntap1 A=4e-12 P=8e-6 -XM4_191 net31 net1 vdd well_1981 sg13_lv_pmos w=1u l=1u m=1 -XT1982 vdd well_1982 ntap1 A=4e-12 P=8e-6 -XM4_192 net31 net1 vdd well_1982 sg13_lv_pmos w=1u l=1u m=1 -XT1983 vdd well_1983 ntap1 A=4e-12 P=8e-6 -XM4_193 net31 net1 vdd well_1983 sg13_lv_pmos w=1u l=1u m=1 -XT1984 vdd well_1984 ntap1 A=4e-12 P=8e-6 -XM4_194 net31 net1 vdd well_1984 sg13_lv_pmos w=1u l=1u m=1 -XT1985 vdd well_1985 ntap1 A=4e-12 P=8e-6 -XM4_195 net31 net1 vdd well_1985 sg13_lv_pmos w=1u l=1u m=1 -XT1986 vdd well_1986 ntap1 A=4e-12 P=8e-6 -XM4_196 net31 net1 vdd well_1986 sg13_lv_pmos w=1u l=1u m=1 -XT1987 vdd well_1987 ntap1 A=4e-12 P=8e-6 -XM4_197 net31 net1 vdd well_1987 sg13_lv_pmos w=1u l=1u m=1 -XT1988 vdd well_1988 ntap1 A=4e-12 P=8e-6 -XM4_198 net31 net1 vdd well_1988 sg13_lv_pmos w=1u l=1u m=1 -XT1989 vdd well_1989 ntap1 A=4e-12 P=8e-6 -XM4_199 net31 net1 vdd well_1989 sg13_lv_pmos w=1u l=1u m=1 -XT1990 vdd well_1990 ntap1 A=4e-12 P=8e-6 -XM4_200 net31 net1 vdd well_1990 sg13_lv_pmos w=1u l=1u m=1 -XT1991 vdd well_1991 ntap1 A=4e-12 P=8e-6 -XM4_201 net31 net1 vdd well_1991 sg13_lv_pmos w=1u l=1u m=1 -XT1992 vdd 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sg13_lv_pmos w=1u l=1u m=1 -XT2002 vdd well_2002 ntap1 A=4e-12 P=8e-6 -XM4_212 net31 net1 vdd well_2002 sg13_lv_pmos w=1u l=1u m=1 -XT2003 vdd well_2003 ntap1 A=4e-12 P=8e-6 -XM4_213 net31 net1 vdd well_2003 sg13_lv_pmos w=1u l=1u m=1 -XT2004 vdd well_2004 ntap1 A=4e-12 P=8e-6 -XM4_214 net31 net1 vdd well_2004 sg13_lv_pmos w=1u l=1u m=1 -XT2005 vdd well_2005 ntap1 A=4e-12 P=8e-6 -XM4_215 net31 net1 vdd well_2005 sg13_lv_pmos w=1u l=1u m=1 -XT2006 vdd well_2006 ntap1 A=4e-12 P=8e-6 -XM4_216 net31 net1 vdd well_2006 sg13_lv_pmos w=1u l=1u m=1 -XT2007 vdd well_2007 ntap1 A=4e-12 P=8e-6 -XM4_217 net31 net1 vdd well_2007 sg13_lv_pmos w=1u l=1u m=1 -XT2008 vdd well_2008 ntap1 A=4e-12 P=8e-6 -XM4_218 net31 net1 vdd well_2008 sg13_lv_pmos w=1u l=1u m=1 -XT2009 vdd well_2009 ntap1 A=4e-12 P=8e-6 -XM4_219 net31 net1 vdd well_2009 sg13_lv_pmos w=1u l=1u m=1 -XT2010 vdd well_2010 ntap1 A=4e-12 P=8e-6 -XM4_220 net31 net1 vdd well_2010 sg13_lv_pmos w=1u l=1u m=1 -XT2011 vdd well_2011 ntap1 A=4e-12 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m=1 -XT2021 vdd well_2021 ntap1 A=4e-12 P=8e-6 -XM4_231 net31 net1 vdd well_2021 sg13_lv_pmos w=1u l=1u m=1 -XT2022 vdd well_2022 ntap1 A=4e-12 P=8e-6 -XM4_232 net31 net1 vdd well_2022 sg13_lv_pmos w=1u l=1u m=1 -XT2023 vdd well_2023 ntap1 A=4e-12 P=8e-6 -XM4_233 net31 net1 vdd well_2023 sg13_lv_pmos w=1u l=1u m=1 -XT2024 vdd well_2024 ntap1 A=4e-12 P=8e-6 -XM4_234 net31 net1 vdd well_2024 sg13_lv_pmos w=1u l=1u m=1 -XT2025 vdd well_2025 ntap1 A=4e-12 P=8e-6 -XM4_235 net31 net1 vdd well_2025 sg13_lv_pmos w=1u l=1u m=1 -XT2026 vdd well_2026 ntap1 A=4e-12 P=8e-6 -XM4_236 net31 net1 vdd well_2026 sg13_lv_pmos w=1u l=1u m=1 -XT2027 vdd well_2027 ntap1 A=4e-12 P=8e-6 -XM4_237 net31 net1 vdd well_2027 sg13_lv_pmos w=1u l=1u m=1 -XT2028 vdd well_2028 ntap1 A=4e-12 P=8e-6 -XM4_238 net31 net1 vdd well_2028 sg13_lv_pmos w=1u l=1u m=1 -XT2029 vdd well_2029 ntap1 A=4e-12 P=8e-6 -XM4_239 net31 net1 vdd well_2029 sg13_lv_pmos w=1u l=1u m=1 -XT2030 vdd well_2030 ntap1 A=4e-12 P=8e-6 -XM4_240 net31 net1 vdd well_2030 sg13_lv_pmos w=1u l=1u m=1 -XT2031 vdd well_2031 ntap1 A=4e-12 P=8e-6 -XM4_241 net31 net1 vdd well_2031 sg13_lv_pmos w=1u l=1u m=1 -XT2032 vdd well_2032 ntap1 A=4e-12 P=8e-6 -XM4_242 net31 net1 vdd well_2032 sg13_lv_pmos w=1u l=1u m=1 -XT2033 vdd well_2033 ntap1 A=4e-12 P=8e-6 -XM4_243 net31 net1 vdd well_2033 sg13_lv_pmos w=1u l=1u m=1 -XT2034 vdd well_2034 ntap1 A=4e-12 P=8e-6 -XM4_244 net31 net1 vdd well_2034 sg13_lv_pmos w=1u l=1u m=1 -XT2035 vdd well_2035 ntap1 A=4e-12 P=8e-6 -XM4_245 net31 net1 vdd well_2035 sg13_lv_pmos w=1u l=1u m=1 -XT2036 vdd well_2036 ntap1 A=4e-12 P=8e-6 -XM4_246 net31 net1 vdd well_2036 sg13_lv_pmos w=1u l=1u m=1 -XT2037 vdd well_2037 ntap1 A=4e-12 P=8e-6 -XM4_247 net31 net1 vdd well_2037 sg13_lv_pmos w=1u l=1u m=1 -XT2038 vdd well_2038 ntap1 A=4e-12 P=8e-6 -XM4_248 net31 net1 vdd well_2038 sg13_lv_pmos w=1u l=1u m=1 -XT2039 vdd well_2039 ntap1 A=4e-12 P=8e-6 -XM4_249 net31 net1 vdd well_2039 sg13_lv_pmos w=1u l=1u m=1 -XT2040 vdd well_2040 ntap1 A=4e-12 P=8e-6 -XM4_250 net31 net1 vdd well_2040 sg13_lv_pmos w=1u l=1u m=1 -XT2041 vdd well_2041 ntap1 A=4e-12 P=8e-6 -XM4_251 net31 net1 vdd well_2041 sg13_lv_pmos w=1u l=1u m=1 -XT2042 vdd well_2042 ntap1 A=4e-12 P=8e-6 -XM4_252 net31 net1 vdd well_2042 sg13_lv_pmos w=1u l=1u m=1 -XT2043 vdd well_2043 ntap1 A=4e-12 P=8e-6 -XM4_253 net31 net1 vdd well_2043 sg13_lv_pmos w=1u l=1u m=1 -XT2044 vdd well_2044 ntap1 A=4e-12 P=8e-6 -XM4_254 net31 net1 vdd well_2044 sg13_lv_pmos w=1u l=1u m=1 -XT2045 vdd well_2045 ntap1 A=4e-12 P=8e-6 -XM4_255 net31 net1 vdd well_2045 sg13_lv_pmos w=1u l=1u m=1 -XT2046 vdd well_2046 ntap1 A=4e-12 P=8e-6 -XM4_256 net31 net1 vdd well_2046 sg13_lv_pmos w=1u l=1u m=1 -XT2047 vdd well_2047 ntap1 A=4e-12 P=8e-6 -XM4_257 net31 net1 vdd well_2047 sg13_lv_pmos w=1u l=1u m=1 -XT2048 vdd well_2048 ntap1 A=4e-12 P=8e-6 -XM4_258 net31 net1 vdd well_2048 sg13_lv_pmos w=1u l=1u m=1 -XT2049 vdd well_2049 ntap1 A=4e-12 P=8e-6 -XM4_259 net31 net1 vdd well_2049 sg13_lv_pmos w=1u l=1u m=1 -XT2050 vdd well_2050 ntap1 A=4e-12 P=8e-6 -XM4_260 net31 net1 vdd well_2050 sg13_lv_pmos w=1u l=1u m=1 -XT2051 vdd well_2051 ntap1 A=4e-12 P=8e-6 -XM4_261 net31 net1 vdd well_2051 sg13_lv_pmos w=1u l=1u m=1 -XT2052 vdd well_2052 ntap1 A=4e-12 P=8e-6 -XM4_262 net31 net1 vdd well_2052 sg13_lv_pmos w=1u l=1u m=1 -XT2053 vdd well_2053 ntap1 A=4e-12 P=8e-6 -XM4_263 net31 net1 vdd well_2053 sg13_lv_pmos w=1u l=1u m=1 -XT2054 vdd well_2054 ntap1 A=4e-12 P=8e-6 -XM4_264 net31 net1 vdd well_2054 sg13_lv_pmos w=1u l=1u m=1 -XT2055 vdd well_2055 ntap1 A=4e-12 P=8e-6 -XM4_265 net31 net1 vdd well_2055 sg13_lv_pmos w=1u l=1u m=1 -XT2056 vdd well_2056 ntap1 A=4e-12 P=8e-6 -XM4_266 net31 net1 vdd well_2056 sg13_lv_pmos w=1u l=1u m=1 -XT2057 vdd well_2057 ntap1 A=4e-12 P=8e-6 -XM4_267 net31 net1 vdd well_2057 sg13_lv_pmos w=1u l=1u m=1 -XT2058 vdd well_2058 ntap1 A=4e-12 P=8e-6 -XM4_268 net31 net1 vdd well_2058 sg13_lv_pmos w=1u l=1u m=1 -XT2059 vdd well_2059 ntap1 A=4e-12 P=8e-6 -XM4_269 net31 net1 vdd well_2059 sg13_lv_pmos w=1u l=1u m=1 -XT2060 vdd well_2060 ntap1 A=4e-12 P=8e-6 -XM4_270 net31 net1 vdd well_2060 sg13_lv_pmos w=1u l=1u m=1 -XT2061 vdd well_2061 ntap1 A=4e-12 P=8e-6 -XM4_271 net31 net1 vdd well_2061 sg13_lv_pmos w=1u l=1u m=1 -XT2062 vdd well_2062 ntap1 A=4e-12 P=8e-6 -XM4_272 net31 net1 vdd well_2062 sg13_lv_pmos w=1u l=1u m=1 -XT2063 vdd well_2063 ntap1 A=4e-12 P=8e-6 -XM4_273 net31 net1 vdd well_2063 sg13_lv_pmos w=1u l=1u m=1 -XT2064 vdd well_2064 ntap1 A=4e-12 P=8e-6 -XM4_274 net31 net1 vdd well_2064 sg13_lv_pmos w=1u l=1u m=1 -XT2065 vdd well_2065 ntap1 A=4e-12 P=8e-6 -XM4_275 net31 net1 vdd well_2065 sg13_lv_pmos w=1u l=1u m=1 -XT2066 vdd well_2066 ntap1 A=4e-12 P=8e-6 -XM4_276 net31 net1 vdd well_2066 sg13_lv_pmos w=1u l=1u m=1 -XT2067 vdd well_2067 ntap1 A=4e-12 P=8e-6 -XM4_277 net31 net1 vdd well_2067 sg13_lv_pmos w=1u l=1u m=1 -XT2068 vdd well_2068 ntap1 A=4e-12 P=8e-6 -XM4_278 net31 net1 vdd well_2068 sg13_lv_pmos w=1u l=1u m=1 -XT2069 vdd well_2069 ntap1 A=4e-12 P=8e-6 -XM4_279 net31 net1 vdd well_2069 sg13_lv_pmos w=1u l=1u m=1 -XT2070 vdd well_2070 ntap1 A=4e-12 P=8e-6 -XM4_280 net31 net1 vdd well_2070 sg13_lv_pmos w=1u l=1u m=1 -XT2071 vdd well_2071 ntap1 A=4e-12 P=8e-6 -XM4_281 net31 net1 vdd well_2071 sg13_lv_pmos w=1u l=1u m=1 -XT2072 vdd well_2072 ntap1 A=4e-12 P=8e-6 -XM4_282 net31 net1 vdd well_2072 sg13_lv_pmos w=1u l=1u m=1 -XT2073 vdd well_2073 ntap1 A=4e-12 P=8e-6 -XM4_283 net31 net1 vdd well_2073 sg13_lv_pmos w=1u l=1u m=1 -XT2074 vdd well_2074 ntap1 A=4e-12 P=8e-6 -XM5_0 voutn voutn vdd well_2074 sg13_lv_pmos w=1u l=1u m=1 -XT2075 vdd well_2075 ntap1 A=4e-12 P=8e-6 -XM5_1 voutn voutn vdd well_2075 sg13_lv_pmos w=1u l=1u m=1 -XT2076 vdd well_2076 ntap1 A=4e-12 P=8e-6 -XM5_2 voutn voutn vdd well_2076 sg13_lv_pmos w=1u l=1u m=1 -XT2077 vdd well_2077 ntap1 A=4e-12 P=8e-6 -XM5_3 voutn voutn vdd well_2077 sg13_lv_pmos w=1u l=1u m=1 -XT2078 vdd well_2078 ntap1 A=4e-12 P=8e-6 -XM5_4 voutn voutn vdd well_2078 sg13_lv_pmos w=1u l=1u m=1 -XT2079 vdd well_2079 ntap1 A=4e-12 P=8e-6 -XM5_5 voutn voutn vdd well_2079 sg13_lv_pmos w=1u l=1u m=1 -XT2080 vdd well_2080 ntap1 A=4e-12 P=8e-6 -XM5_6 voutn voutn vdd well_2080 sg13_lv_pmos w=1u l=1u m=1 -XT2081 vdd well_2081 ntap1 A=4e-12 P=8e-6 -XM5_7 voutn voutn vdd well_2081 sg13_lv_pmos w=1u l=1u m=1 -XT2082 vdd well_2082 ntap1 A=4e-12 P=8e-6 -XM5_8 voutn voutn vdd well_2082 sg13_lv_pmos w=1u l=1u m=1 -XT2083 vdd well_2083 ntap1 A=4e-12 P=8e-6 -XM5_9 voutn voutn vdd well_2083 sg13_lv_pmos w=1u l=1u m=1 -XT2084 vdd well_2084 ntap1 A=4e-12 P=8e-6 -XM5_10 voutn voutn vdd well_2084 sg13_lv_pmos w=1u l=1u m=1 -XT2085 vdd well_2085 ntap1 A=4e-12 P=8e-6 -XM5_11 voutn voutn vdd well_2085 sg13_lv_pmos w=1u l=1u m=1 -XT2086 vdd well_2086 ntap1 A=4e-12 P=8e-6 -XM5_12 voutn voutn vdd well_2086 sg13_lv_pmos w=1u l=1u m=1 -XT2087 vdd well_2087 ntap1 A=4e-12 P=8e-6 -XM5_13 voutn voutn vdd well_2087 sg13_lv_pmos w=1u l=1u m=1 -XT2088 vdd well_2088 ntap1 A=4e-12 P=8e-6 -XM5_14 voutn voutn vdd well_2088 sg13_lv_pmos w=1u l=1u m=1 -XT2089 vdd well_2089 ntap1 A=4e-12 P=8e-6 -XM5_15 voutn voutn vdd well_2089 sg13_lv_pmos w=1u l=1u m=1 -XT2090 vdd well_2090 ntap1 A=4e-12 P=8e-6 -XM5_16 voutn voutn vdd well_2090 sg13_lv_pmos w=1u l=1u m=1 -XT2091 vdd well_2091 ntap1 A=4e-12 P=8e-6 -XM5_17 voutn voutn vdd well_2091 sg13_lv_pmos w=1u l=1u m=1 -XT2092 vdd well_2092 ntap1 A=4e-12 P=8e-6 -XM5_18 voutn voutn vdd well_2092 sg13_lv_pmos w=1u l=1u m=1 -XT2093 vdd well_2093 ntap1 A=4e-12 P=8e-6 -XM5_19 voutn voutn vdd well_2093 sg13_lv_pmos w=1u l=1u m=1 -XT2094 vdd well_2094 ntap1 A=4e-12 P=8e-6 -XM5_20 voutn voutn vdd well_2094 sg13_lv_pmos w=1u l=1u m=1 -XT2095 vdd well_2095 ntap1 A=4e-12 P=8e-6 -XM5_21 voutn voutn vdd well_2095 sg13_lv_pmos w=1u l=1u m=1 -XT2096 vdd well_2096 ntap1 A=4e-12 P=8e-6 -XM5_22 voutn voutn vdd well_2096 sg13_lv_pmos w=1u l=1u m=1 -XT2097 vdd well_2097 ntap1 A=4e-12 P=8e-6 -XM5_23 voutn voutn vdd well_2097 sg13_lv_pmos w=1u l=1u m=1 -XT2098 vdd well_2098 ntap1 A=4e-12 P=8e-6 -XM5_24 voutn voutn vdd well_2098 sg13_lv_pmos w=1u l=1u m=1 -XT2099 vdd well_2099 ntap1 A=4e-12 P=8e-6 -XM5_25 voutn voutn vdd well_2099 sg13_lv_pmos w=1u l=1u m=1 -XT2100 vdd well_2100 ntap1 A=4e-12 P=8e-6 -XM5_26 voutn voutn vdd well_2100 sg13_lv_pmos w=1u l=1u m=1 -XT2101 vdd well_2101 ntap1 A=4e-12 P=8e-6 -XM5_27 voutn voutn vdd well_2101 sg13_lv_pmos w=1u l=1u m=1 -XT2102 vdd well_2102 ntap1 A=4e-12 P=8e-6 -XM5_28 voutn voutn vdd well_2102 sg13_lv_pmos w=1u l=1u m=1 -XT2103 vdd well_2103 ntap1 A=4e-12 P=8e-6 -XM5_29 voutn voutn vdd well_2103 sg13_lv_pmos w=1u l=1u m=1 -XT2104 vdd well_2104 ntap1 A=4e-12 P=8e-6 -XM5_30 voutn voutn vdd well_2104 sg13_lv_pmos w=1u l=1u m=1 -XT2105 vdd well_2105 ntap1 A=4e-12 P=8e-6 -XM5_31 voutn voutn vdd well_2105 sg13_lv_pmos w=1u l=1u m=1 -XT2106 vdd well_2106 ntap1 A=4e-12 P=8e-6 -XM5_32 voutn voutn vdd well_2106 sg13_lv_pmos w=1u l=1u m=1 -XT2107 vdd well_2107 ntap1 A=4e-12 P=8e-6 -XM5_33 voutn voutn vdd well_2107 sg13_lv_pmos w=1u l=1u m=1 -XT2108 vdd well_2108 ntap1 A=4e-12 P=8e-6 -XM5_34 voutn voutn vdd well_2108 sg13_lv_pmos w=1u l=1u m=1 -XT2109 vdd well_2109 ntap1 A=4e-12 P=8e-6 -XM5_35 voutn voutn vdd well_2109 sg13_lv_pmos w=1u l=1u m=1 -XT2110 vdd well_2110 ntap1 A=4e-12 P=8e-6 -XM5_36 voutn voutn vdd well_2110 sg13_lv_pmos w=1u l=1u m=1 -XT2111 vdd well_2111 ntap1 A=4e-12 P=8e-6 -XM5_37 voutn voutn vdd well_2111 sg13_lv_pmos w=1u l=1u m=1 -XT2112 vdd well_2112 ntap1 A=4e-12 P=8e-6 -XM5_38 voutn voutn vdd well_2112 sg13_lv_pmos w=1u l=1u m=1 -XT2113 vdd well_2113 ntap1 A=4e-12 P=8e-6 -XM5_39 voutn voutn vdd well_2113 sg13_lv_pmos w=1u l=1u m=1 -XT2114 vdd well_2114 ntap1 A=4e-12 P=8e-6 -XM5_40 voutn voutn vdd well_2114 sg13_lv_pmos w=1u l=1u m=1 -XT2115 vdd well_2115 ntap1 A=4e-12 P=8e-6 -XM5_41 voutn voutn vdd well_2115 sg13_lv_pmos w=1u l=1u m=1 -XT2116 vdd well_2116 ntap1 A=4e-12 P=8e-6 -XM5_42 voutn voutn vdd well_2116 sg13_lv_pmos w=1u l=1u m=1 -XT2117 vdd well_2117 ntap1 A=4e-12 P=8e-6 -XM5_43 voutn voutn vdd well_2117 sg13_lv_pmos w=1u l=1u m=1 -XT2118 vdd well_2118 ntap1 A=4e-12 P=8e-6 -XM5_44 voutn voutn vdd well_2118 sg13_lv_pmos w=1u l=1u m=1 -XT2119 vdd well_2119 ntap1 A=4e-12 P=8e-6 -XM5_45 voutn voutn vdd well_2119 sg13_lv_pmos w=1u l=1u m=1 -XT2120 vdd well_2120 ntap1 A=4e-12 P=8e-6 -XM5_46 voutn voutn vdd well_2120 sg13_lv_pmos w=1u l=1u m=1 -XT2121 vdd well_2121 ntap1 A=4e-12 P=8e-6 -XM5_47 voutn voutn vdd well_2121 sg13_lv_pmos w=1u l=1u m=1 -XT2122 vdd well_2122 ntap1 A=4e-12 P=8e-6 -XM5_48 voutn voutn vdd well_2122 sg13_lv_pmos w=1u l=1u m=1 -XT2123 vdd well_2123 ntap1 A=4e-12 P=8e-6 -XM5_49 voutn voutn vdd well_2123 sg13_lv_pmos w=1u l=1u m=1 -XT2124 vdd well_2124 ntap1 A=4e-12 P=8e-6 -XM5_50 voutn voutn vdd well_2124 sg13_lv_pmos w=1u l=1u m=1 -XT2125 vdd well_2125 ntap1 A=4e-12 P=8e-6 -XM5_51 voutn voutn vdd well_2125 sg13_lv_pmos w=1u l=1u m=1 -XT2126 vdd well_2126 ntap1 A=4e-12 P=8e-6 -XM5_52 voutn voutn vdd well_2126 sg13_lv_pmos w=1u l=1u m=1 -XT2127 vdd well_2127 ntap1 A=4e-12 P=8e-6 -XM5_53 voutn voutn vdd well_2127 sg13_lv_pmos w=1u l=1u m=1 -XT2128 vdd well_2128 ntap1 A=4e-12 P=8e-6 -XM5_54 voutn voutn vdd well_2128 sg13_lv_pmos w=1u l=1u m=1 -XT2129 vdd well_2129 ntap1 A=4e-12 P=8e-6 -XM5_55 voutn voutn vdd well_2129 sg13_lv_pmos w=1u l=1u m=1 -XT2130 vdd well_2130 ntap1 A=4e-12 P=8e-6 -XM5_56 voutn voutn vdd well_2130 sg13_lv_pmos w=1u l=1u m=1 -XT2131 vdd well_2131 ntap1 A=4e-12 P=8e-6 -XM5_57 voutn voutn vdd well_2131 sg13_lv_pmos w=1u l=1u m=1 -XT2132 vdd well_2132 ntap1 A=4e-12 P=8e-6 -XM5_58 voutn voutn vdd well_2132 sg13_lv_pmos w=1u l=1u m=1 -XT2133 vdd well_2133 ntap1 A=4e-12 P=8e-6 -XM5_59 voutn voutn vdd well_2133 sg13_lv_pmos w=1u l=1u m=1 -XT2134 vdd well_2134 ntap1 A=4e-12 P=8e-6 -XM5_60 voutn voutn vdd well_2134 sg13_lv_pmos w=1u l=1u m=1 -XT2135 vdd well_2135 ntap1 A=4e-12 P=8e-6 -XM5_61 voutn voutn vdd well_2135 sg13_lv_pmos w=1u l=1u m=1 -XT2136 vdd well_2136 ntap1 A=4e-12 P=8e-6 -XM5_62 voutn voutn vdd well_2136 sg13_lv_pmos w=1u l=1u m=1 -XT2137 vdd well_2137 ntap1 A=4e-12 P=8e-6 -XM5_63 voutn voutn vdd well_2137 sg13_lv_pmos w=1u l=1u m=1 -XT2138 vdd well_2138 ntap1 A=4e-12 P=8e-6 -XM5_64 voutn voutn vdd well_2138 sg13_lv_pmos w=1u l=1u m=1 -XT2139 vdd well_2139 ntap1 A=4e-12 P=8e-6 -XM5_65 voutn voutn vdd well_2139 sg13_lv_pmos w=1u l=1u m=1 -XT2140 vdd well_2140 ntap1 A=4e-12 P=8e-6 -XM5_66 voutn voutn vdd well_2140 sg13_lv_pmos w=1u l=1u m=1 -XT2141 vdd well_2141 ntap1 A=4e-12 P=8e-6 -XM5_67 voutn voutn vdd well_2141 sg13_lv_pmos w=1u l=1u m=1 -XT2142 vdd well_2142 ntap1 A=4e-12 P=8e-6 -XM5_68 voutn voutn vdd well_2142 sg13_lv_pmos w=1u l=1u m=1 -XT2143 vdd well_2143 ntap1 A=4e-12 P=8e-6 -XM5_69 voutn voutn vdd well_2143 sg13_lv_pmos w=1u l=1u m=1 -XT2144 vdd well_2144 ntap1 A=4e-12 P=8e-6 -XM5_70 voutn voutn vdd well_2144 sg13_lv_pmos w=1u l=1u m=1 -XT2145 vdd well_2145 ntap1 A=4e-12 P=8e-6 -XM6_0 net050 voutn vdd well_2145 sg13_lv_pmos w=1u l=1u m=1 -XT2146 vdd well_2146 ntap1 A=4e-12 P=8e-6 -XM6_1 net050 voutn vdd well_2146 sg13_lv_pmos w=1u l=1u m=1 -XT2147 vdd well_2147 ntap1 A=4e-12 P=8e-6 -XM6_2 net050 voutn vdd well_2147 sg13_lv_pmos w=1u l=1u m=1 -XT2148 vdd well_2148 ntap1 A=4e-12 P=8e-6 -XM6_3 net050 voutn vdd well_2148 sg13_lv_pmos w=1u l=1u m=1 -XT2149 vdd well_2149 ntap1 A=4e-12 P=8e-6 -XM6_4 net050 voutn vdd well_2149 sg13_lv_pmos w=1u l=1u m=1 -XT2150 vdd well_2150 ntap1 A=4e-12 P=8e-6 -XM6_5 net050 voutn vdd well_2150 sg13_lv_pmos w=1u l=1u m=1 -XT2151 vdd well_2151 ntap1 A=4e-12 P=8e-6 -XM6_6 net050 voutn vdd well_2151 sg13_lv_pmos w=1u l=1u m=1 -XT2152 vdd well_2152 ntap1 A=4e-12 P=8e-6 -XM6_7 net050 voutn vdd well_2152 sg13_lv_pmos w=1u l=1u m=1 -XT2153 vdd well_2153 ntap1 A=4e-12 P=8e-6 -XM6_8 net050 voutn vdd well_2153 sg13_lv_pmos w=1u l=1u m=1 -XT2154 vdd well_2154 ntap1 A=4e-12 P=8e-6 -XM6_9 net050 voutn vdd well_2154 sg13_lv_pmos w=1u l=1u m=1 -XT2155 vdd well_2155 ntap1 A=4e-12 P=8e-6 -XM6_10 net050 voutn vdd well_2155 sg13_lv_pmos w=1u l=1u m=1 -XT2156 vdd well_2156 ntap1 A=4e-12 P=8e-6 -XM6_11 net050 voutn vdd well_2156 sg13_lv_pmos w=1u l=1u m=1 -XT2157 vdd well_2157 ntap1 A=4e-12 P=8e-6 -XM6_12 net050 voutn vdd well_2157 sg13_lv_pmos w=1u l=1u m=1 -XT2158 vdd well_2158 ntap1 A=4e-12 P=8e-6 -XM6_13 net050 voutn vdd well_2158 sg13_lv_pmos w=1u l=1u m=1 -XT2159 vdd well_2159 ntap1 A=4e-12 P=8e-6 -XM6_14 net050 voutn vdd well_2159 sg13_lv_pmos w=1u l=1u m=1 -XT2160 vdd well_2160 ntap1 A=4e-12 P=8e-6 -XM6_15 net050 voutn vdd well_2160 sg13_lv_pmos w=1u l=1u m=1 -XT2161 vdd well_2161 ntap1 A=4e-12 P=8e-6 -XM6_16 net050 voutn vdd well_2161 sg13_lv_pmos w=1u l=1u m=1 -XT2162 vdd well_2162 ntap1 A=4e-12 P=8e-6 -XM6_17 net050 voutn vdd well_2162 sg13_lv_pmos w=1u l=1u m=1 -XT2163 vdd well_2163 ntap1 A=4e-12 P=8e-6 -XM6_18 net050 voutn vdd well_2163 sg13_lv_pmos w=1u l=1u m=1 -XT2164 vdd well_2164 ntap1 A=4e-12 P=8e-6 -XM6_19 net050 voutn vdd well_2164 sg13_lv_pmos w=1u l=1u m=1 -XT2165 vdd well_2165 ntap1 A=4e-12 P=8e-6 -XM6_20 net050 voutn vdd well_2165 sg13_lv_pmos w=1u l=1u m=1 -XT2166 vdd well_2166 ntap1 A=4e-12 P=8e-6 -XM6_21 net050 voutn vdd well_2166 sg13_lv_pmos w=1u l=1u m=1 -XT2167 vdd well_2167 ntap1 A=4e-12 P=8e-6 -XM6_22 net050 voutn vdd well_2167 sg13_lv_pmos w=1u l=1u m=1 -XT2168 vdd well_2168 ntap1 A=4e-12 P=8e-6 -XM6_23 net050 voutn vdd well_2168 sg13_lv_pmos w=1u l=1u m=1 -XT2169 vdd well_2169 ntap1 A=4e-12 P=8e-6 -XM6_24 net050 voutn vdd well_2169 sg13_lv_pmos w=1u l=1u m=1 -XT2170 vdd well_2170 ntap1 A=4e-12 P=8e-6 -XM6_25 net050 voutn vdd well_2170 sg13_lv_pmos w=1u l=1u m=1 -XT2171 vdd well_2171 ntap1 A=4e-12 P=8e-6 -XM6_26 net050 voutn vdd well_2171 sg13_lv_pmos w=1u l=1u m=1 -XT2172 vdd well_2172 ntap1 A=4e-12 P=8e-6 -XM6_27 net050 voutn vdd well_2172 sg13_lv_pmos w=1u l=1u m=1 -XT2173 vdd well_2173 ntap1 A=4e-12 P=8e-6 -XM6_28 net050 voutn vdd well_2173 sg13_lv_pmos w=1u l=1u m=1 -XT2174 vdd well_2174 ntap1 A=4e-12 P=8e-6 -XM6_29 net050 voutn vdd well_2174 sg13_lv_pmos w=1u l=1u m=1 -XT2175 vdd well_2175 ntap1 A=4e-12 P=8e-6 -XM6_30 net050 voutn vdd well_2175 sg13_lv_pmos w=1u l=1u m=1 -XT2176 vdd well_2176 ntap1 A=4e-12 P=8e-6 -XM6_31 net050 voutn vdd well_2176 sg13_lv_pmos w=1u l=1u m=1 -XT2177 vdd well_2177 ntap1 A=4e-12 P=8e-6 -XM6_32 net050 voutn vdd well_2177 sg13_lv_pmos w=1u l=1u m=1 -XT2178 vdd well_2178 ntap1 A=4e-12 P=8e-6 -XM6_33 net050 voutn vdd well_2178 sg13_lv_pmos w=1u l=1u m=1 -XT2179 vdd well_2179 ntap1 A=4e-12 P=8e-6 -XM6_34 net050 voutn vdd well_2179 sg13_lv_pmos w=1u l=1u m=1 -XT2180 vdd well_2180 ntap1 A=4e-12 P=8e-6 -XM6_35 net050 voutn vdd well_2180 sg13_lv_pmos w=1u l=1u m=1 -XT2181 vdd well_2181 ntap1 A=4e-12 P=8e-6 -XM6_36 net050 voutn vdd well_2181 sg13_lv_pmos w=1u l=1u m=1 -XT2182 vdd well_2182 ntap1 A=4e-12 P=8e-6 -XM6_37 net050 voutn vdd well_2182 sg13_lv_pmos w=1u l=1u m=1 -XT2183 vdd well_2183 ntap1 A=4e-12 P=8e-6 -XM6_38 net050 voutn vdd well_2183 sg13_lv_pmos w=1u l=1u m=1 -XT2184 vdd well_2184 ntap1 A=4e-12 P=8e-6 -XM6_39 net050 voutn vdd well_2184 sg13_lv_pmos w=1u l=1u m=1 -XT2185 vdd well_2185 ntap1 A=4e-12 P=8e-6 -XM6_40 net050 voutn vdd well_2185 sg13_lv_pmos w=1u l=1u m=1 -XT2186 vdd well_2186 ntap1 A=4e-12 P=8e-6 -XM6_41 net050 voutn vdd well_2186 sg13_lv_pmos w=1u l=1u m=1 -XT2187 vdd well_2187 ntap1 A=4e-12 P=8e-6 -XM6_42 net050 voutn vdd well_2187 sg13_lv_pmos w=1u l=1u m=1 -XT2188 vdd well_2188 ntap1 A=4e-12 P=8e-6 -XM6_43 net050 voutn vdd well_2188 sg13_lv_pmos w=1u l=1u m=1 -XT2189 vdd well_2189 ntap1 A=4e-12 P=8e-6 -XM6_44 net050 voutn vdd well_2189 sg13_lv_pmos w=1u l=1u m=1 -XT2190 vdd well_2190 ntap1 A=4e-12 P=8e-6 -XM6_45 net050 voutn vdd well_2190 sg13_lv_pmos w=1u l=1u m=1 -XT2191 vdd well_2191 ntap1 A=4e-12 P=8e-6 -XM6_46 net050 voutn vdd well_2191 sg13_lv_pmos w=1u l=1u m=1 -XT2192 vdd well_2192 ntap1 A=4e-12 P=8e-6 -XM6_47 net050 voutn vdd well_2192 sg13_lv_pmos w=1u l=1u m=1 -XT2193 vdd well_2193 ntap1 A=4e-12 P=8e-6 -XM6_48 net050 voutn vdd well_2193 sg13_lv_pmos w=1u l=1u m=1 -XT2194 vdd well_2194 ntap1 A=4e-12 P=8e-6 -XM6_49 net050 voutn vdd well_2194 sg13_lv_pmos w=1u l=1u m=1 -XT2195 vdd well_2195 ntap1 A=4e-12 P=8e-6 -XM6_50 net050 voutn vdd well_2195 sg13_lv_pmos w=1u l=1u m=1 -XT2196 vdd well_2196 ntap1 A=4e-12 P=8e-6 -XM6_51 net050 voutn vdd well_2196 sg13_lv_pmos w=1u l=1u m=1 -XT2197 vdd well_2197 ntap1 A=4e-12 P=8e-6 -XM6_52 net050 voutn vdd well_2197 sg13_lv_pmos w=1u l=1u m=1 -XT2198 vdd well_2198 ntap1 A=4e-12 P=8e-6 -XM6_53 net050 voutn vdd well_2198 sg13_lv_pmos w=1u l=1u m=1 -XT2199 vdd well_2199 ntap1 A=4e-12 P=8e-6 -XM6_54 net050 voutn vdd well_2199 sg13_lv_pmos w=1u l=1u m=1 -XT2200 vdd well_2200 ntap1 A=4e-12 P=8e-6 -XM6_55 net050 voutn vdd well_2200 sg13_lv_pmos w=1u l=1u m=1 -XT2201 vdd well_2201 ntap1 A=4e-12 P=8e-6 -XM6_56 net050 voutn vdd well_2201 sg13_lv_pmos w=1u l=1u m=1 -XT2202 vdd well_2202 ntap1 A=4e-12 P=8e-6 -XM6_57 net050 voutn vdd well_2202 sg13_lv_pmos w=1u l=1u m=1 -XT2203 vdd well_2203 ntap1 A=4e-12 P=8e-6 -XM6_58 net050 voutn vdd well_2203 sg13_lv_pmos w=1u l=1u m=1 -XT2204 vdd well_2204 ntap1 A=4e-12 P=8e-6 -XM6_59 net050 voutn vdd well_2204 sg13_lv_pmos w=1u l=1u m=1 -XT2205 vdd well_2205 ntap1 A=4e-12 P=8e-6 -XM6_60 net050 voutn vdd well_2205 sg13_lv_pmos w=1u l=1u m=1 -XT2206 vdd well_2206 ntap1 A=4e-12 P=8e-6 -XM6_61 net050 voutn vdd well_2206 sg13_lv_pmos w=1u l=1u m=1 -XT2207 vdd well_2207 ntap1 A=4e-12 P=8e-6 -XM6_62 net050 voutn vdd well_2207 sg13_lv_pmos w=1u l=1u m=1 -XT2208 vdd well_2208 ntap1 A=4e-12 P=8e-6 -XM6_63 net050 voutn vdd well_2208 sg13_lv_pmos w=1u l=1u m=1 -XT2209 vdd well_2209 ntap1 A=4e-12 P=8e-6 -XM6_64 net050 voutn vdd well_2209 sg13_lv_pmos w=1u l=1u m=1 -XT2210 vdd well_2210 ntap1 A=4e-12 P=8e-6 -XM6_65 net050 voutn vdd well_2210 sg13_lv_pmos w=1u l=1u m=1 -XT2211 vdd well_2211 ntap1 A=4e-12 P=8e-6 -XM6_66 net050 voutn vdd well_2211 sg13_lv_pmos w=1u l=1u m=1 -XT2212 vdd well_2212 ntap1 A=4e-12 P=8e-6 -XM6_67 net050 voutn vdd well_2212 sg13_lv_pmos w=1u l=1u m=1 -XT2213 vdd well_2213 ntap1 A=4e-12 P=8e-6 -XM6_68 net050 voutn vdd well_2213 sg13_lv_pmos w=1u l=1u m=1 -XT2214 vdd well_2214 ntap1 A=4e-12 P=8e-6 -XM6_69 net050 voutn vdd well_2214 sg13_lv_pmos w=1u l=1u m=1 -XT2215 vdd well_2215 ntap1 A=4e-12 P=8e-6 -XM6_70 net050 voutn vdd well_2215 sg13_lv_pmos w=1u l=1u m=1 -XT2216 vdd well_2216 ntap1 A=4e-12 P=8e-6 -XM7_0 net049 net1 vdd well_2216 sg13_lv_pmos w=1u l=1u m=1 -XT2217 vdd well_2217 ntap1 A=4e-12 P=8e-6 -XM7_1 net049 net1 vdd well_2217 sg13_lv_pmos w=1u l=1u m=1 -XT2218 vdd well_2218 ntap1 A=4e-12 P=8e-6 -XM7_2 net049 net1 vdd well_2218 sg13_lv_pmos w=1u l=1u m=1 -XT2219 vdd well_2219 ntap1 A=4e-12 P=8e-6 -XM7_3 net049 net1 vdd well_2219 sg13_lv_pmos w=1u l=1u m=1 -XT2220 vdd well_2220 ntap1 A=4e-12 P=8e-6 -XM7_4 net049 net1 vdd well_2220 sg13_lv_pmos w=1u l=1u m=1 -XT2221 vdd well_2221 ntap1 A=4e-12 P=8e-6 -XM7_5 net049 net1 vdd well_2221 sg13_lv_pmos w=1u l=1u m=1 -XT2222 vdd well_2222 ntap1 A=4e-12 P=8e-6 -XM7_6 net049 net1 vdd well_2222 sg13_lv_pmos w=1u l=1u m=1 -XT2223 vdd well_2223 ntap1 A=4e-12 P=8e-6 -XM7_7 net049 net1 vdd well_2223 sg13_lv_pmos w=1u l=1u m=1 -XT2224 vdd well_2224 ntap1 A=4e-12 P=8e-6 -XM7_8 net049 net1 vdd well_2224 sg13_lv_pmos w=1u l=1u m=1 -XT2225 vdd well_2225 ntap1 A=4e-12 P=8e-6 -XM7_9 net049 net1 vdd well_2225 sg13_lv_pmos w=1u l=1u m=1 -XT2226 vdd well_2226 ntap1 A=4e-12 P=8e-6 -XM7_10 net049 net1 vdd well_2226 sg13_lv_pmos w=1u l=1u m=1 -XT2227 vdd well_2227 ntap1 A=4e-12 P=8e-6 -XM7_11 net049 net1 vdd well_2227 sg13_lv_pmos w=1u l=1u m=1 -XT2228 vdd well_2228 ntap1 A=4e-12 P=8e-6 -XM7_12 net049 net1 vdd well_2228 sg13_lv_pmos w=1u l=1u m=1 -XT2229 vdd well_2229 ntap1 A=4e-12 P=8e-6 -XM7_13 net049 net1 vdd well_2229 sg13_lv_pmos w=1u l=1u m=1 -XT2230 vdd well_2230 ntap1 A=4e-12 P=8e-6 -XM7_14 net049 net1 vdd well_2230 sg13_lv_pmos w=1u l=1u m=1 -XT2231 vdd well_2231 ntap1 A=4e-12 P=8e-6 -XM7_15 net049 net1 vdd well_2231 sg13_lv_pmos w=1u l=1u m=1 -XT2232 vdd well_2232 ntap1 A=4e-12 P=8e-6 -XM7_16 net049 net1 vdd well_2232 sg13_lv_pmos w=1u l=1u m=1 -XT2233 vdd well_2233 ntap1 A=4e-12 P=8e-6 -XM7_17 net049 net1 vdd well_2233 sg13_lv_pmos w=1u l=1u m=1 -XT2234 vdd well_2234 ntap1 A=4e-12 P=8e-6 -XM7_18 net049 net1 vdd well_2234 sg13_lv_pmos w=1u l=1u m=1 -XT2235 vdd well_2235 ntap1 A=4e-12 P=8e-6 -XM7_19 net049 net1 vdd well_2235 sg13_lv_pmos w=1u l=1u m=1 -XT2236 vdd well_2236 ntap1 A=4e-12 P=8e-6 -XM7_20 net049 net1 vdd well_2236 sg13_lv_pmos w=1u l=1u m=1 -XT2237 vdd well_2237 ntap1 A=4e-12 P=8e-6 -XM7_21 net049 net1 vdd well_2237 sg13_lv_pmos w=1u l=1u m=1 -XT2238 vdd well_2238 ntap1 A=4e-12 P=8e-6 -XM7_22 net049 net1 vdd well_2238 sg13_lv_pmos w=1u l=1u m=1 -XT2239 vdd well_2239 ntap1 A=4e-12 P=8e-6 -XM7_23 net049 net1 vdd well_2239 sg13_lv_pmos w=1u l=1u m=1 -XT2240 vdd well_2240 ntap1 A=4e-12 P=8e-6 -XM7_24 net049 net1 vdd well_2240 sg13_lv_pmos w=1u l=1u m=1 -XT2241 vdd well_2241 ntap1 A=4e-12 P=8e-6 -XM7_25 net049 net1 vdd well_2241 sg13_lv_pmos w=1u l=1u m=1 -XT2242 vdd well_2242 ntap1 A=4e-12 P=8e-6 -XM7_26 net049 net1 vdd well_2242 sg13_lv_pmos w=1u l=1u m=1 -XT2243 vdd well_2243 ntap1 A=4e-12 P=8e-6 -XM7_27 net049 net1 vdd well_2243 sg13_lv_pmos w=1u l=1u m=1 -XT2244 vdd well_2244 ntap1 A=4e-12 P=8e-6 -XM7_28 net049 net1 vdd well_2244 sg13_lv_pmos w=1u l=1u m=1 -XT2245 vdd well_2245 ntap1 A=4e-12 P=8e-6 -XM7_29 net049 net1 vdd well_2245 sg13_lv_pmos w=1u l=1u m=1 -XT2246 vdd well_2246 ntap1 A=4e-12 P=8e-6 -XM7_30 net049 net1 vdd well_2246 sg13_lv_pmos w=1u l=1u m=1 -XT2247 vdd well_2247 ntap1 A=4e-12 P=8e-6 -XM7_31 net049 net1 vdd well_2247 sg13_lv_pmos w=1u l=1u m=1 -XT2248 vdd well_2248 ntap1 A=4e-12 P=8e-6 -XM7_32 net049 net1 vdd well_2248 sg13_lv_pmos w=1u l=1u m=1 -XT2249 vdd well_2249 ntap1 A=4e-12 P=8e-6 -XM7_33 net049 net1 vdd well_2249 sg13_lv_pmos w=1u l=1u m=1 -XT2250 vdd well_2250 ntap1 A=4e-12 P=8e-6 -XM7_34 net049 net1 vdd well_2250 sg13_lv_pmos w=1u l=1u m=1 -XT2251 vdd well_2251 ntap1 A=4e-12 P=8e-6 -XM7_35 net049 net1 vdd well_2251 sg13_lv_pmos w=1u l=1u m=1 -XT2252 vdd well_2252 ntap1 A=4e-12 P=8e-6 -XM7_36 net049 net1 vdd well_2252 sg13_lv_pmos w=1u l=1u m=1 -XT2253 vdd well_2253 ntap1 A=4e-12 P=8e-6 -XM7_37 net049 net1 vdd well_2253 sg13_lv_pmos w=1u l=1u m=1 -XT2254 vdd well_2254 ntap1 A=4e-12 P=8e-6 -XM7_38 net049 net1 vdd well_2254 sg13_lv_pmos w=1u l=1u m=1 -XT2255 vdd well_2255 ntap1 A=4e-12 P=8e-6 -XM7_39 net049 net1 vdd well_2255 sg13_lv_pmos w=1u l=1u m=1 -XT2256 vdd well_2256 ntap1 A=4e-12 P=8e-6 -XM7_40 net049 net1 vdd well_2256 sg13_lv_pmos w=1u l=1u m=1 -XT2257 vdd well_2257 ntap1 A=4e-12 P=8e-6 -XM7_41 net049 net1 vdd well_2257 sg13_lv_pmos w=1u l=1u m=1 -XT2258 vdd well_2258 ntap1 A=4e-12 P=8e-6 -XM7_42 net049 net1 vdd well_2258 sg13_lv_pmos w=1u l=1u m=1 -XT2259 vdd well_2259 ntap1 A=4e-12 P=8e-6 -XM7_43 net049 net1 vdd well_2259 sg13_lv_pmos w=1u l=1u m=1 -XT2260 vdd well_2260 ntap1 A=4e-12 P=8e-6 -XM7_44 net049 net1 vdd well_2260 sg13_lv_pmos w=1u l=1u m=1 -XT2261 vdd well_2261 ntap1 A=4e-12 P=8e-6 -XM7_45 net049 net1 vdd well_2261 sg13_lv_pmos w=1u l=1u m=1 -XT2262 vdd well_2262 ntap1 A=4e-12 P=8e-6 -XM7_46 net049 net1 vdd well_2262 sg13_lv_pmos w=1u l=1u m=1 -XT2263 vdd well_2263 ntap1 A=4e-12 P=8e-6 -XM7_47 net049 net1 vdd well_2263 sg13_lv_pmos w=1u l=1u m=1 -XT2264 vdd well_2264 ntap1 A=4e-12 P=8e-6 -XM7_48 net049 net1 vdd well_2264 sg13_lv_pmos w=1u l=1u m=1 -XT2265 vdd well_2265 ntap1 A=4e-12 P=8e-6 -XM7_49 net049 net1 vdd well_2265 sg13_lv_pmos w=1u l=1u m=1 -XT2266 vdd well_2266 ntap1 A=4e-12 P=8e-6 -XM7_50 net049 net1 vdd well_2266 sg13_lv_pmos w=1u l=1u m=1 -XT2267 vdd well_2267 ntap1 A=4e-12 P=8e-6 -XM7_51 net049 net1 vdd well_2267 sg13_lv_pmos w=1u l=1u m=1 -XT2268 vdd well_2268 ntap1 A=4e-12 P=8e-6 -XM7_52 net049 net1 vdd well_2268 sg13_lv_pmos w=1u l=1u m=1 -XT2269 vdd well_2269 ntap1 A=4e-12 P=8e-6 -XM7_53 net049 net1 vdd well_2269 sg13_lv_pmos w=1u l=1u m=1 -XT2270 vdd well_2270 ntap1 A=4e-12 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net31 well_2346 ntap1 A=4e-12 P=8e-6 -XM8_59 dm_2 vinn net31 well_2346 sg13_lv_pmos w=1u l=1u m=1 -XT2347 net31 well_2347 ntap1 A=4e-12 P=8e-6 -XM8_60 dm_2 vinn net31 well_2347 sg13_lv_pmos w=1u l=1u m=1 -XT2348 net31 well_2348 ntap1 A=4e-12 P=8e-6 -XM8_61 dm_2 vinn net31 well_2348 sg13_lv_pmos w=1u l=1u m=1 -XT2349 net31 well_2349 ntap1 A=4e-12 P=8e-6 -XM8_62 dm_2 vinn net31 well_2349 sg13_lv_pmos w=1u l=1u m=1 -XT2350 net31 well_2350 ntap1 A=4e-12 P=8e-6 -XM8_63 dm_2 vinn net31 well_2350 sg13_lv_pmos w=1u l=1u m=1 -XT2351 net31 well_2351 ntap1 A=4e-12 P=8e-6 -XM8_64 dm_2 vinn net31 well_2351 sg13_lv_pmos w=1u l=1u m=1 -XT2352 net31 well_2352 ntap1 A=4e-12 P=8e-6 -XM8_65 dm_2 vinn net31 well_2352 sg13_lv_pmos w=1u l=1u m=1 -XT2353 net31 well_2353 ntap1 A=4e-12 P=8e-6 -XM8_66 dm_2 vinn net31 well_2353 sg13_lv_pmos w=1u l=1u m=1 -XT2354 net31 well_2354 ntap1 A=4e-12 P=8e-6 -XM8_67 dm_2 vinn net31 well_2354 sg13_lv_pmos w=1u l=1u m=1 -XT2355 net31 well_2355 ntap1 A=4e-12 P=8e-6 -XM8_68 dm_2 vinn net31 well_2355 sg13_lv_pmos w=1u l=1u m=1 -XT2356 net31 well_2356 ntap1 A=4e-12 P=8e-6 -XM8_69 dm_2 vinn net31 well_2356 sg13_lv_pmos w=1u l=1u m=1 -XT2357 net31 well_2357 ntap1 A=4e-12 P=8e-6 -XM8_70 dm_2 vinn net31 well_2357 sg13_lv_pmos w=1u l=1u m=1 -XT2358 net31 well_2358 ntap1 A=4e-12 P=8e-6 -XM8_71 dm_2 vinn net31 well_2358 sg13_lv_pmos w=1u l=1u m=1 -XT2359 net31 well_2359 ntap1 A=4e-12 P=8e-6 -XM8_72 dm_2 vinn net31 well_2359 sg13_lv_pmos w=1u l=1u m=1 -XT2360 net31 well_2360 ntap1 A=4e-12 P=8e-6 -XM8_73 dm_2 vinn net31 well_2360 sg13_lv_pmos w=1u l=1u m=1 -XT2361 net31 well_2361 ntap1 A=4e-12 P=8e-6 -XM8_74 dm_2 vinn net31 well_2361 sg13_lv_pmos w=1u l=1u m=1 -XT2362 net31 well_2362 ntap1 A=4e-12 P=8e-6 -XM8_75 dm_2 vinn net31 well_2362 sg13_lv_pmos w=1u l=1u m=1 -XT2363 net31 well_2363 ntap1 A=4e-12 P=8e-6 -XM8_76 dm_2 vinn net31 well_2363 sg13_lv_pmos w=1u l=1u m=1 -XT2364 net31 well_2364 ntap1 A=4e-12 P=8e-6 -XM8_77 dm_2 vinn net31 well_2364 sg13_lv_pmos w=1u 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l=1u m=1 -XT2578 net31 well_2578 ntap1 A=4e-12 P=8e-6 -XM9_143 net063 vinp net31 well_2578 sg13_lv_pmos w=1u l=1u m=1 -XT2579 net31 well_2579 ntap1 A=4e-12 P=8e-6 -XM9_144 net063 vinp net31 well_2579 sg13_lv_pmos w=1u l=1u m=1 -XT2580 net31 well_2580 ntap1 A=4e-12 P=8e-6 -XM9_145 net063 vinp net31 well_2580 sg13_lv_pmos w=1u l=1u m=1 -XT2581 net31 well_2581 ntap1 A=4e-12 P=8e-6 -XM9_146 net063 vinp net31 well_2581 sg13_lv_pmos w=1u l=1u m=1 -XT2582 net31 well_2582 ntap1 A=4e-12 P=8e-6 -XM9_147 net063 vinp net31 well_2582 sg13_lv_pmos w=1u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 -XC0_0 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_1 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_2 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_3 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_4 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_5 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_6 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_7 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_8 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_9 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_10 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_11 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_12 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_13 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_14 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC0_15 net050 vout cap_cmim w=51.18u l=51.18u m=1 -XC1_0 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -XC1_1 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -XC1_2 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -XC1_3 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -XC1_4 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -XC1_5 net050 net049 cap_cmim w=48.74u l=48.74u m=1 -XC1_6 net050 net049 cap_cmim w=48.74u l=48.74u m=1 +XC0 net050 vout cap_cmim w=51.18u l=51.18u m=16 +XC1 net050 net049 cap_cmim w=48.74u l=48.74u m=7 +XM0 net1 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +XM1 vb4 net1 vdd vdd sg13_lv_pmos w=1u l=1u m=71 +XM10 net043 net050 vdd vdd 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R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Repeated device arrays are split into contiguous source-order ranges sized for responsive Analog Canvas editing; every source device and literal parameter remains represented.","No interactive editor walkthrough is claimed."],"known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_014_ramos_pfc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/design/amp_014_ramos_pfc.icproj.json"}}Main-sheet overview; 58 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_014_ramos_pfcvoutnet050vddnet1vb4vinndm_2net31vddnet1vb3vsssubvssvb4subnet54vddnet1vddnet1net31vddnet1net049vssvb4subnet063subvb3voutndm_2vddvoutnet050vddnet043net050vddnet1dm_1vssvb4subnet56subvb3dm_1net56vddnet050voutnvb4subvb3net54vssvoutsubnet049vssvb4subdm_2vinpnet063net31vddvoutnnet050net049net050subvb3net063vsssubvb3vssvssnet1vddvinnvinpvoutvssamp_014_ramos_pfcBIAS AND REFERENCEINPUT PAIR AND CASCODED GAINOUTPUT AND COMPENSATIONMM21w=1u l=1uMM22w=1u l=1uXMM0_bank1XMM1_bank2XMM10_bank3XMM11_bank4XMM12_bank5XMM13_bank6XMM14_bank7XMM15_bank8XMM16_bank9XMM17_bank10XMM18_bank11XMM19_bank12XMM2_bank13XMM20_bank14XMM23_bank15XMM3_bank16XMM4_bank17XMM5_bank18XMM6_bank19XMM7_bank20XMM8_bank21XMM9_bank22XXRT623_bank23XXC0_bank24XXC1_bank25 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md index 83d301dc369f5842278797958d6d742945d1cd38..52672283ac9e045d1319cefa7297f50d5d885d64 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md @@ -3,13 +3,13 @@ ## Objective Implement `amp_014_ramos_pfc` with the supplied fixed topology and dimensions. The PMOS input pair drives the cascoded NMOS branches at dm_2/net063; the voutn mirror produces net050. XM10 and the XM21/XM22 mirror drive net049, while XM11/XM23 drive the single-ended output. Both compensation paths remain: 63 pF from net050 to vout and 25 pF from net050 to net049. The vb3/vb4 bias network is retained. -Do not replace the circuit, delete compensation, or add a servo. The physical core -contains 2583 MOS after expanding explicit upstream multiplicities. Each PMOS -input body remains tied to its own tail node through its physical well contact. +Do not replace the circuit, delete compensation, or add a servo. The circuit contains 24 logical MOS groups with the upstream W, L, multiplicity +and four-terminal connections. PMOS groups XM8 and XM9 both have source and body +on net31; other PMOS bodies connect to vdd, and NMOS bodies connect to vss. ## Inputs and Interface -`materials/circuit.cdl` is the authoritative physical circuit, `materials/circuit.spice` its simulation representation, `materials/testbench.spice` defines closed-loop observations, and `materials/ac.spice` defines balanced differential AC excitation. Ordered ports are `vss vdd vinn vinp vout net1`: ground, supply, negative/positive inputs, single-ended output and an external bias-current pull-down. Bias, input drive, feedback connections and loads are external test fixtures. Contacts and internal R/C must be physically implemented. +`materials/circuit.cdl` is the authoritative logical circuit with native PDK model bindings, `materials/circuit.spice` its simulation representation, `materials/testbench.spice` defines closed-loop observations, and `materials/ac.spice` defines balanced differential AC excitation. Ordered ports are `vss vdd vinn vinp vout net1`: ground, supply, negative/positive inputs, single-ended output and an external bias-current pull-down. Bias, input drive, feedback connections and loads are external test fixtures. Implement the compensation capacitors and physical body contacts. Body contacts are layout connectivity and are not additional logical circuit devices. ## Operating Conditions @@ -28,10 +28,16 @@ AC sweeps 200 points per decade from 1 Hz to 1 GHz. The differential-mode deck r Supply a GDS <=64 MiB with top cell `amp_014_ramos_pfc`, within 20000 by 2000 um (the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS and functional-area measurement must pass; no marker waivers apply. Preserve -MOS dimensions, multiplicities, body connections, all physical R/C and tap geometry. +MOS models, gate lengths, parallel-equivalent widths (W*m), logical body connections +and the two native compensation-capacitor bindings. Electrically equivalent unit +arrays, multiple gate fingers and shared diffusion are allowed when native LVS +verifies them. Sharing a well is allowed only for bodies on the same logical net. +Physically connect each well/substrate region to its declared body net through +DRC-compliant contacts; contact count, placement and geometry are layout choices. +No particular reference-array partition or isolated well per unit is required. Functional layers in the published task include active, implant, wells, gates, contacts, passive plates, vias and routing; annotation/text-only layers are excluded. -IHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job. +IHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. The two native MIM bindings use 51.18 um square plates with m=16 and 48.74 um square plates with m=7, giving nominal 62.9964384 pF and 24.9982586 pF at the stated typical model. LVS connects actual tap regions to their wells/substrate before comparing the four-terminal logical MOS; it does not compare a prescribed tap inventory. Source simulation uses the same logical body boundary and native MIM models as candidate extraction. Magic extracts the candidate devices, junction geometry and distributed interconnect RC. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job. ## Electrical Requirements and Scoring @@ -70,9 +76,9 @@ Error metrics use saturating normalization `2*(b+s)/(b+x+2*s)`, with the quality The area quality target is **70000 um2**. It is an integration budget, not a hard limit or a proven process minimum. -The 23 fixed MIM plates occupy 58539.3916 um2. A 70000 um2 integration budget allocates about 84% to those plates, leaving 11460.6084 um2 for enclosures, the expanded MOS array, taps and interconnect; it is not a minimum-area theorem. Area carries 35%, 100 ppm step-referred late accuracy 15%, the worst bilateral normalized response integral 20%, 10 kHz gain 15%, DC gain 10% and mean power 5%. The response integral removes each final plateau offset, so dynamic response and static accuracy are distinct. Repeated return offset, ripple and operating-point summaries remain diagnostic. +The 23 fixed MIM plates occupy 58539.3916 um2. A 70000 um2 integration budget allocates about 84% to those plates, leaving 11460.6084 um2 for enclosures, MOS devices, body contacts and interconnect; it is not a minimum-area theorem. Area carries 35%, 100 ppm step-referred late accuracy 15%, the worst bilateral normalized response integral 20%, 10 kHz gain 15%, DC gain 10% and mean power 5%. The response integral removes each final plateau offset, so dynamic response and static accuracy are distinct. Repeated return offset, ripple and operating-point summaries remain diagnostic. -`response_time_s` takes the worse normalized absolute-error integral: integrate `abs(v(vout)-high_v)/0.1` over 20.1–100 us, or `abs(v(vout)-low_v)/0.1` over 100.2–180 us. The existing high/return means supply the final plateau values. The 75 ns budget leaves about 5.6 ns above the worst 69.4 ns source result under the declared 100 mV step and 10 pF load. Removing each plateau offset isolates dynamic response from the separately scored static error. This finite-window integral is in seconds; it is not a threshold-crossing settling time and does not establish periodic steady state. +`response_time_s` takes the worse normalized absolute-error integral: integrate `abs(v(vout)-high_v)/0.1` over 20.1–100 us, or `abs(v(vout)-low_v)/0.1` over 100.2–180 us. The existing high/return means supply the final plateau values. The 75 ns response-integral budget is a layout-delay quality target under the declared 100 mV step and 10 pF load; it is not an acceptance threshold. Removing each plateau offset isolates dynamic response from the separately scored static error. This finite-window integral is in seconds; it is not a threshold-crossing settling time and does not establish periodic steady state. | Metric | Quality anchor | Unit | Scale | Weight | | --- | --- | --- | --- | ---: | diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml index aaff0ceff92878741b0c67708e86d37ef6a18249..dd6beaa14063fcb0b6c3d552dab55dc4e4f4a107 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml @@ -4,13 +4,6 @@ title = "Input-Driven Active-Feedforward OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "bb343709aa6ab5c7cda37c3efcd080d68b24632f84a862c65648d15b86a874d0" - [[assets]] path = "reference/amp_015_sau_cfcc.gds" role = "physical-witness" @@ -28,13 +21,13 @@ environment = "ihp-sg13g2-amp_015_sau_cfcc-nominal-rc" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "35ad982ea87b187ae88e8310c0f63d24de73d476e45b0746f9ab5fad044676ad" +sha256 = "f693e31d5ea9e39cddaae0906e2b171551d966962730c4f7037df8933790a2a8" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_015_sau_cfcc" -sha256 = "9934cbb25b0b85a604e0e3a453094d54a55c9ea1edfc8d66e6eb3b4fce0a0190" +sha256 = "97d4a622ebdbebdeed5e1050e29ca4c1ab7496c39596180bec3270f7efc79901" [task.inputs.performance] path = "materials/testbench.spice" @@ -44,7 +37,7 @@ sha256 = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +sha256 = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.constraints] quality = [ @@ -1163,10 +1156,10 @@ upper = 1.2 rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective." [task.evaluation.pre_layout] -source_report_sha256 = "96c7a4d18298005bc04d451cb411d041ef1352615d8d082ec81a99075cc1df0f" +source_report_sha256 = "adac7126a0f42810a74ed5090cdc5fea3616f746606a1ce64bd0a9df0e7bc27d" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1213,86 +1206,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" -dut = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +dut = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 0.7271532841715 +value = 0.730458062748 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dc_gain_db] -value = 93.74538 +value = 94.75017 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_phase_margin_deg] -value = 97.82809 +value = 97.94419 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_unity_hz] -value = 203539.7 +value = 221563.2 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.hf_gain_db] -value = -69.26125 +value = -78.3033 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 2.329226e-05 +value = 2.546493e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_return_distance] -value = 0.6659419638617 +value = 0.6711007967414 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_error_v] -value = 0.001727593090003 +value = 0.001479806692025 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.50172759309 +value = 0.501479806692 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.peak_v] -value = 0.7017558 +value = 0.7015028 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin_deg] -value = 97.82809 +value = 97.94419 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 2.284224693255e-05 +value = 2.502711500602e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_down_v] -value = 0.001738971 +value = 0.001484267 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_up_v] -value = 0.001755749 +value = 0.001502772 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_phase_excursion_deg] -value = 89.44570594302 +value = 89.47642011811 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_gain] -value = 1.0001405 +value = 1.000115 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.trough_v] -value = 0.5017276 +value = 0.5014798 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] -value = 203539.7 +value = 221563.2 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "adb29d32bc546663ebbb35f74b9fba68af72f39ce03cb913965b7f8baf4a8d86" -ac = "ec2377acb28291e821ae550596bc474a7f05976f0be0b468c92f4d44690795a1" -transient = "cff2a8709cf28035a5d3b7cd3578d8f9e48172e6aed68bab3ab8bba9742cf8e7" -voltage = "0ba609610d9cdeb8bae45bf08201f187b9b7aa6892b8868ee8ce4d84bdef80ed" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1338,86 +1325,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" -dut = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +dut = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] -value = 0.7271532841715 +value = 0.730458062748 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_gain_db] -value = 93.74538 +value = 94.75017 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_phase_margin_deg] -value = 97.61539 +value = 97.7433 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_unity_hz] -value = 203601.3 +value = 221625.8 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.hf_gain_db] -value = -70.0262 +value = -79.06696 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] -value = 2.333544e-05 +value = 2.550746e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_return_distance] -value = 0.6762456710346 +value = 0.6811792580009 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_error_v] -value = 0.001727593090003 +value = 0.001479806692025 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] -value = 0.50172759309 +value = 0.501479806692 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.peak_v] -value = 0.7023162 +value = 0.7015028 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin_deg] -value = 97.61539 +value = 97.7433 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 2.284224693255e-05 +value = 2.502711500602e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_down_v] -value = 0.001738796 +value = 0.001484192 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_up_v] -value = 0.00175575 +value = 0.001502772 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.return_phase_excursion_deg] -value = 89.44657554678 +value = 89.47719356039 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_gain] -value = 1.0001405 +value = 1.000115 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.trough_v] -value = 0.5017276 +value = 0.5014798 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] -value = 203601.3 +value = 221625.8 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "adb29d32bc546663ebbb35f74b9fba68af72f39ce03cb913965b7f8baf4a8d86" -ac = "6e34f4047f820532ffa5e63a88fe9adaa97584d097faf04c3a9e6e0ab8162d32" -transient = "dff76a40135e17cf7ad981360fa7b0261a1c158e1b131e4f4a890b9f9b18754b" -voltage = "265369f0b5289be145d60904168c1751226a634f88eb9a3a83725ff2353ddbad" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1463,86 +1444,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" -dut = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +dut = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] -value = 0.7271532841715 +value = 0.730458062748 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_gain_db] -value = 93.74538 +value = 94.75017 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_phase_margin_deg] -value = 97.40235 +value = 97.54211 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_unity_hz] -value = 203659.9 +value = 221685.3 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.hf_gain_db] -value = -70.72921 +value = -79.76887 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] -value = 2.337913e-05 +value = 2.555054e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_return_distance] -value = 0.6854072999508 +value = 0.6901326958723 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_error_v] -value = 0.001727593090003 +value = 0.001479806692025 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] -value = 0.50172759309 +value = 0.501479806692 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.peak_v] -value = 0.704205 +value = 0.7020675 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_margin_deg] -value = 97.40235 +value = 97.54211 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 2.284224693255e-05 +value = 2.502711500602e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_down_v] -value = 0.001738622 +value = 0.001484118 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_up_v] -value = 0.001755751 +value = 0.001502773 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.return_phase_excursion_deg] -value = 89.44744606828 +value = 89.477966947 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_gain] -value = 1.000141 +value = 1.000115 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.trough_v] -value = 0.5017276 +value = 0.5014798 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.unity_hz] -value = 203659.9 +value = 221685.3 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "adb29d32bc546663ebbb35f74b9fba68af72f39ce03cb913965b7f8baf4a8d86" -ac = "9e7cb4bed88281cdada7371ec49f29586cf69c037dd5b501bf693d6403aba9b2" -transient = "d4d8dc735d7a31f07a77ab03d45f78ec91435517f75c0de36e163fb4bf142b17" -voltage = "3b3f6265237f7acf9b0caa7e5cec826b40fd278c7e67087ca19f0339136dbc9b" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -1588,86 +1563,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" -dut = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +dut = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.bias_v] -value = 0.7271535046861 +value = 0.7304582741723 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dc_gain_db] -value = 95.57222 +value = 96.55415 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_phase_margin_deg] -value = 97.81095 +value = 97.93207 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_unity_hz] -value = 201599.6 +value = 219565.3 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.hf_gain_db] -value = -69.73849 +value = -79.16884 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.mean_power_w] -value = 2.329226e-05 +value = 2.546493e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_return_distance] -value = 0.6735552829949 +value = 0.6783262531751 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_error_v] -value = 0.001755749884198 +value = 0.001502771819659 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] -value = 0.7017557498842 +value = 0.7015027718197 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.peak_v] -value = 0.7017558 +value = 0.7015028 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.phase_margin_deg] -value = 97.81095 +value = 97.93207 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 2.292439727606e-05 +value = 2.512373530261e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_down_v] -value = 0.001738971 +value = 0.001484267 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_up_v] -value = 0.001755749 +value = 0.001502772 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.return_phase_excursion_deg] -value = 89.50108092055 +value = 89.52808187816 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_gain] -value = 1.0001405 +value = 1.000115 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.trough_v] -value = 0.5017276 +value = 0.5014798 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.unity_hz] -value = 201599.6 +value = 219565.3 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "83aa096f666f4cc5b0abc2a9338527507d1d2fc60e67c9d5f6164f86d4eac43f" -ac = "89e5666bdd47bb912099adf36c4439c2b9bbadb1202c6196b733affe5f69a186" -transient = "cff2a8709cf28035a5d3b7cd3578d8f9e48172e6aed68bab3ab8bba9742cf8e7" -voltage = "98ad07f88ad5b69b1e1f20f3c02cd7b9010f23d7ecc2fe85a28423ea5342580a" - [task.evaluation.pre_layout.jobs.source_condition_4] operation = "circuit.simulate" @@ -1713,86 +1682,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] deck = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" -dut = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +dut = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.bias_v] -value = 0.7271535046861 +value = 0.7304582741723 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.dc_gain_db] -value = 95.57222 +value = 96.55415 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_phase_margin_deg] -value = 97.60166 +value = 97.73427 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.final_unity_hz] -value = 201657.2 +value = 219623.9 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.hf_gain_db] -value = -70.50338 +value = -79.93243 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.mean_power_w] -value = 2.333544e-05 +value = 2.550746e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.minimum_return_distance] -value = 0.6837858653393 +value = 0.6883393767596 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_error_v] -value = 0.001755749884198 +value = 0.001502771819659 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] -value = 0.7017557498842 +value = 0.7015027718197 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.peak_v] -value = 0.7023162 +value = 0.7015028 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.phase_margin_deg] -value = 97.60166 +value = 97.73427 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] -value = 2.292439727606e-05 +value = 2.512373530261e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_down_v] -value = 0.001738796 +value = 0.001484192 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.recovery_up_v] -value = 0.00175575 +value = 0.001502772 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.return_phase_excursion_deg] -value = 89.50185178109 +value = 89.52876720064 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.step_gain] -value = 1.0001405 +value = 1.000115 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.trough_v] -value = 0.5017276 +value = 0.5014798 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.unity_hz] -value = 201657.2 +value = 219623.9 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_4.output_sha256] -op = "83aa096f666f4cc5b0abc2a9338527507d1d2fc60e67c9d5f6164f86d4eac43f" -ac = "55c1af34d9eb72d613e184cfea429118305dd610d9c3f7b52b1fa4083a57a754" -transient = "dff76a40135e17cf7ad981360fa7b0261a1c158e1b131e4f4a890b9f9b18754b" -voltage = "e867bab8260a69dab2403cfcea4352c17075878370960f338e1279fcafb6380b" - [task.evaluation.pre_layout.jobs.source_condition_5] operation = "circuit.simulate" @@ -1838,86 +1801,80 @@ voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] deck = "1800a671db4d09db7b3fbfd0da2ac9842fdf2ac9316684556bd78377dd0fd69a" -dut = "69c93dd5282db5c6076c00154f7115c9d8b6ec4f6cca9d475921682c88d93269" +dut = "2e781482f91c6295ecac0743dbca6070dcf2b8126e7344bf99c9f7e6c2d00259" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.bias_v] -value = 0.7271535046861 +value = 0.7304582741723 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.dc_gain_db] -value = 95.57222 +value = 96.55415 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_phase_margin_deg] -value = 97.39206 +value = 97.53618 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.final_unity_hz] -value = 201711.9 +value = 219679.8 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.hf_gain_db] -value = -71.20634 +value = -80.63429 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.mean_power_w] -value = 2.337913e-05 +value = 2.555054e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.minimum_return_distance] -value = 0.6926626696473 +value = 0.697017222412 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_error_v] -value = 0.001755749884198 +value = 0.001502771819659 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_v] -value = 0.7017557498842 +value = 0.7015027718197 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.peak_v] -value = 0.704205 +value = 0.7020675 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.phase_margin_deg] -value = 97.39206 +value = 97.53618 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.power_w] -value = 2.292439727606e-05 +value = 2.512373530261e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.recovery_down_v] -value = 0.001738622 +value = 0.001484118 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.recovery_up_v] -value = 0.001755751 +value = 0.001502773 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.return_phase_excursion_deg] -value = 89.50262257445 +value = 89.52945728477 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.step_gain] -value = 1.000141 +value = 1.000115 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.trough_v] -value = 0.5017276 +value = 0.5014798 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.unity_hz] -value = 201711.9 +value = 219679.8 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_5.output_sha256] -op = "83aa096f666f4cc5b0abc2a9338527507d1d2fc60e67c9d5f6164f86d4eac43f" -ac = "77b3557ece5cc4b432cf75992cb755951a917f868b1c50fed1292ad427524d6d" -transient = "d4d8dc735d7a31f07a77ab03d45f78ec91435517f75c0de36e163fb4bf142b17" -voltage = "dba9e9d46c743211a0e7bbc0db0c7f64d7438e3beba7f807eb8bdc714be0957e" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1957,7 +1914,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/input-pair-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl index 6fa428fa377f38fd46719dbe4c6cbb65e77ffc71..d78cb0b047da4cdf71604043d97f8eed8ecbca97 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl @@ -1,172 +1,31 @@ -* Derived from analog-db amp_015_sau_cfcc, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified: 10 nm MOS grid, equivalent parallel regrouping, explicit physical MIM/taps; -* disclosed bias and added physical compensation calibration. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_015_sau_cfcc vss vdd vinn vinp vout net013 -MM12 vb4 vb3 net54 sub sg13_lv_nmos w=5.14u l=3.99u m=16 -MM13 dm_1 vb3 net56 sub sg13_lv_nmos w=5.14u l=3.99u m=16 -MM14 vb3 vb3 vss sub sg13_lv_nmos w=5.14u l=3.99u m=4 -MM15 voutn vb3 dm_2 sub sg13_lv_nmos w=6.74u l=3.98u m=8 -MM16 net050 vb3 net063 sub sg13_lv_nmos w=6.74u l=3.98u m=8 -MM17 net54 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=16 -MM18 net56 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=16 -MM19 dm_2 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=32 -MM20 net063 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=32 -MM21 net043 net043 vss sub sg13_lv_nmos w=6.87u l=0.64u m=8 -MM22 net049 net043 vss sub sg13_lv_nmos w=6.87u l=0.64u m=24 -MM23 vout net049 vss sub sg13_lv_nmos w=7.31u l=0.81u m=4 -MM8 dm_2 vinn net31 well_net31 sg13_lv_pmos w=7.33u l=0.46u m=4 -MM9 net063 vinp net31 well_net31 sg13_lv_pmos w=7.33u l=0.46u m=4 -RRtap_net31_0 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_1 net31 well_net31 ntap1 A=4e-12 P=8e-6 -RRtap_net31_2 net31 well_net31 ntap1 A=4e-12 P=8e-6 -MM0 net013 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -MM1 vb4 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -MM10 net043 net050 vdd well_vdd sg13_lv_pmos w=6.38u l=1.97u m=8 -MM11 vout net050 vdd well_vdd sg13_lv_pmos w=9.59u l=1.2u m=8 -MM2 dm_1 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -MM3 vb3 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -MM4 net31 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=4 -MM5 voutn voutn vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -MM6 net050 voutn vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -MM7 net049 voutn vdd well_vdd sg13_lv_pmos w=5.52u l=1.09u m=1 -RRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRptap_0 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_1 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_2 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_3 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_4 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_5 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_6 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_7 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_8 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_9 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_10 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_11 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_12 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_13 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_14 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_15 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_16 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_17 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_18 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_19 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_20 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_21 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_22 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_23 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_24 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_25 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_26 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_27 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_28 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_29 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_30 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_31 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_32 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_33 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_34 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_35 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_36 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_37 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_38 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_39 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_40 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_41 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_42 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_43 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_44 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_45 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_46 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_47 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_48 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_49 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_50 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_51 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_52 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_53 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_54 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_55 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_56 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_57 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_58 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_59 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_60 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_61 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_62 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_63 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_64 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_65 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_66 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_67 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_68 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_69 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_70 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_71 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_72 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_73 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_74 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_75 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_76 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_77 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_78 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_79 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_80 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_81 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_82 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_83 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_84 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_85 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_86 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_87 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_88 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_89 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_90 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_91 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_92 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_93 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_94 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_95 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_96 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_97 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_98 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_99 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_100 vss sub ptap1 A=4e-12 P=8e-6 -CC0_0 net063 vout cap_cmim w=51.3u l=51.3u m=1 -CCLOCAL_0 net050 vout cap_cmim w=51.64u l=51.64u m=1 -CCLOCAL_1 net050 vout cap_cmim w=51.64u l=51.64u m=1 -CCLOCAL_2 net050 vout cap_cmim w=51.64u l=51.64u m=1 -CCLOCAL_3 net050 vout cap_cmim w=51.64u l=51.64u m=1 -CCOUT_0 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_1 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_2 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_3 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_4 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_5 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_6 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_7 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_8 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_9 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_10 vout vss cap_cmim w=51.64u l=51.64u m=1 -CCOUT_11 vout vss cap_cmim w=51.64u l=51.64u m=1 +MM0 net013 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +MM1 vb4 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +MM10 net043 net050 vdd vdd sg13_lv_pmos w=6.38u l=1.97u m=8 +MM11 vout net050 vdd vdd sg13_lv_pmos w=9.59u l=1.2u m=8 +MM12 vb4 vb3 net54 vss sg13_lv_nmos w=2.57u l=3.99u m=32 +MM13 dm_1 vb3 net56 vss sg13_lv_nmos w=2.57u l=3.99u m=32 +MM14 vb3 vb3 vss vss sg13_lv_nmos w=2.57u l=3.99u m=8 +MM15 voutn vb3 dm_2 vss sg13_lv_nmos w=6.74u l=3.98u m=8 +MM16 net050 vb3 net063 vss sg13_lv_nmos w=6.74u l=3.98u m=8 +MM17 net54 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=32 +MM18 net56 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=32 +MM19 dm_2 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=64 +MM2 dm_1 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +MM20 net063 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=64 +MM21 net043 net043 vss vss sg13_lv_nmos w=6.87u l=0.64u m=8 +MM22 net049 net043 vss vss sg13_lv_nmos w=6.87u l=0.64u m=24 +MM23 vout net049 vss vss sg13_lv_nmos w=7.31u l=0.81u m=4 +MM3 vb3 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +MM4 net31 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=8 +MM5 voutn voutn vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +MM6 net050 voutn vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +MM7 net049 voutn vdd vdd sg13_lv_pmos w=1.38u l=1.09u m=4 +MM8 dm_2 vinn net31 net31 sg13_lv_pmos w=7.33u l=0.46u m=4 +MM9 net063 vinp net31 net31 sg13_lv_pmos w=7.33u l=0.46u m=4 +C0_0 net063 vout cap_cmim w=51.3u l=51.3u m=1 +CLOCAL_0 net050 vout cap_cmim w=51.64u l=51.64u m=4 +COUT_0 vout vss cap_cmim w=51.64u l=51.64u m=12 .ends amp_015_sau_cfcc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.spice index 3d28031071f57c197625cb0b8c810edbfc569307..e3151cb0a24cab723485a99943baf16e488513dd 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.spice @@ -1,172 +1,31 @@ -* Derived from analog-db amp_015_sau_cfcc, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified: 10 nm MOS grid, equivalent parallel regrouping, explicit physical MIM/taps; -* disclosed bias and added physical compensation calibration. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_015_sau_cfcc vss vdd vinn vinp vout net013 -XM12 vb4 vb3 net54 sub sg13_lv_nmos w=5.14u l=3.99u m=16 -XM13 dm_1 vb3 net56 sub sg13_lv_nmos w=5.14u l=3.99u m=16 -XM14 vb3 vb3 vss sub sg13_lv_nmos w=5.14u l=3.99u m=4 -XM15 voutn vb3 dm_2 sub sg13_lv_nmos w=6.74u l=3.98u m=8 -XM16 net050 vb3 net063 sub sg13_lv_nmos w=6.74u l=3.98u m=8 -XM17 net54 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=16 -XM18 net56 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=16 -XM19 dm_2 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=32 -XM20 net063 vb4 vss sub sg13_lv_nmos w=5.14u l=3.99u m=32 -XM21 net043 net043 vss sub sg13_lv_nmos w=6.87u l=0.64u m=8 -XM22 net049 net043 vss sub sg13_lv_nmos w=6.87u l=0.64u m=24 -XM23 vout net049 vss sub sg13_lv_nmos w=7.31u l=0.81u m=4 -XM8 dm_2 vinn net31 well_net31 sg13_lv_pmos w=7.33u l=0.46u m=4 -XM9 net063 vinp net31 well_net31 sg13_lv_pmos w=7.33u l=0.46u m=4 -XRtap_net31_0 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_1 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XRtap_net31_2 net31 well_net31 ntap1 A=4e-12 P=8e-6 -XM0 net013 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -XM1 vb4 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -XM10 net043 net050 vdd well_vdd sg13_lv_pmos w=6.38u l=1.97u m=8 -XM11 vout net050 vdd well_vdd sg13_lv_pmos w=9.59u l=1.2u m=8 -XM2 dm_1 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -XM3 vb3 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -XM4 net31 net013 vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=4 -XM5 voutn voutn vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -XM6 net050 voutn vdd well_vdd sg13_lv_pmos w=6.22u l=8.33u m=2 -XM7 net049 voutn vdd well_vdd sg13_lv_pmos w=5.52u l=1.09u m=1 -XRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRptap_0 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_1 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_2 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_3 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_4 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_5 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_6 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_7 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_8 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_9 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_10 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_11 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_12 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_13 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_14 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_15 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_16 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_17 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_18 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_19 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_20 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_21 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_22 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_23 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_24 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_25 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_26 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_27 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_28 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_29 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_30 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_31 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_32 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_33 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_34 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_35 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_36 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_37 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_38 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_39 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_40 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_41 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_42 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_43 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_44 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_45 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_46 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_47 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_48 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_49 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_50 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_51 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_52 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_53 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_54 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_55 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_56 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_57 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_58 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_59 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_60 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_61 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_62 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_63 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_64 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_65 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_66 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_67 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_68 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_69 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_70 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_71 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_72 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_73 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_74 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_75 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_76 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_77 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_78 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_79 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_80 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_81 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_82 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_83 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_84 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_85 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_86 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_87 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_88 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_89 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_90 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_91 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_92 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_93 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_94 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_95 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_96 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_97 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_98 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_99 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_100 vss sub ptap1 A=4e-12 P=8e-6 +XM0 net013 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +XM1 vb4 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +XM10 net043 net050 vdd vdd sg13_lv_pmos w=6.38u l=1.97u m=8 +XM11 vout net050 vdd vdd sg13_lv_pmos w=9.59u l=1.2u m=8 +XM12 vb4 vb3 net54 vss sg13_lv_nmos w=2.57u l=3.99u m=32 +XM13 dm_1 vb3 net56 vss sg13_lv_nmos w=2.57u l=3.99u m=32 +XM14 vb3 vb3 vss vss sg13_lv_nmos w=2.57u l=3.99u m=8 +XM15 voutn vb3 dm_2 vss sg13_lv_nmos w=6.74u l=3.98u m=8 +XM16 net050 vb3 net063 vss sg13_lv_nmos w=6.74u l=3.98u m=8 +XM17 net54 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=32 +XM18 net56 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=32 +XM19 dm_2 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=64 +XM2 dm_1 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +XM20 net063 vb4 vss vss sg13_lv_nmos w=2.57u l=3.99u m=64 +XM21 net043 net043 vss vss sg13_lv_nmos w=6.87u l=0.64u m=8 +XM22 net049 net043 vss vss sg13_lv_nmos w=6.87u l=0.64u m=24 +XM23 vout net049 vss vss sg13_lv_nmos w=7.31u l=0.81u m=4 +XM3 vb3 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +XM4 net31 net013 vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=8 +XM5 voutn voutn vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +XM6 net050 voutn vdd vdd sg13_lv_pmos w=3.11u l=8.33u m=4 +XM7 net049 voutn vdd vdd sg13_lv_pmos w=1.38u l=1.09u m=4 +XM8 dm_2 vinn net31 net31 sg13_lv_pmos w=7.33u l=0.46u m=4 +XM9 net063 vinp net31 net31 sg13_lv_pmos w=7.33u l=0.46u m=4 XC0_0 net063 vout cap_cmim w=51.3u l=51.3u m=1 -XCLOCAL_0 net050 vout cap_cmim w=51.64u l=51.64u m=1 -XCLOCAL_1 net050 vout cap_cmim w=51.64u l=51.64u m=1 -XCLOCAL_2 net050 vout cap_cmim w=51.64u l=51.64u m=1 -XCLOCAL_3 net050 vout cap_cmim w=51.64u l=51.64u m=1 -XCOUT_0 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_1 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_2 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_3 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_4 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_5 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_6 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_7 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_8 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_9 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_10 vout vss cap_cmim w=51.64u l=51.64u m=1 -XCOUT_11 vout vss cap_cmim w=51.64u l=51.64u m=1 +XCLOCAL_0 net050 vout cap_cmim w=51.64u l=51.64u m=4 +XCOUT_0 vout vss cap_cmim w=51.64u l=51.64u m=12 .ends amp_015_sau_cfcc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/schematic.svg deleted file mode 100644 index f1249696838ac0b63e32c8ccfefb735bf0a4970c..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_015_sau_cfcc{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_015_sau_cfcc","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_015_sau_cfcc","Bank1_18x_ntap1","Bank2_101x_ptap1","Bank3_12x_cap_cmim"],"banks":[{"name":"Bank1_18x_ntap1","count":18,"model":"ntap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank2_101x_ptap1","count":101,"model":"ptap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank3_12x_cap_cmim","count":12,"model":"cap_cmim","params":{"w":"51.64u","l":"51.64u","m":"1"}}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/design/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_015_sau_cfcc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/design/amp_015_sau_cfcc.icproj.json"}}Main-sheet overview; 3 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_015_sau_cfccvddwell_vddvsssubvoutvssvinnvinpvddnet050net31vb3vb4vssdm_2net063voutnvoutnnet050voutvddnet049vssnet043dm_1net54net56vssvddvb4net013vb3net31net013vddnet063net050voutvddwell_vddsubvoutvssvssnet31well_net31vssvddvinnvinpvoutnet013amp_015_sau_cfccihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresDifferential input and folded branchesMM56.22/8.33 ×2MM66.22/8.33 ×2MM87.33/0.46 ×4MM97.33/0.46 ×4MM156.74/3.98 ×8MM166.74/3.98 ×8MM195.14/3.99 ×32MM205.14/3.99 ×32MM5, MM6: B → well_vddMM8, MM9: B → well_net31N bulk → subIntermediate gainMM106.38/1.97 ×8MM75.52/1.09MM119.59/1.2 ×8MM216.87/0.64 ×8MM226.87/0.64 ×24MM237.31/0.81 ×4P bulk → well_vddN bulk → subTail-current bias networkMM06.22/8.33 ×2MM16.22/8.33 ×2MM26.22/8.33 ×2MM36.22/8.33 ×2MM125.14/3.99 ×16MM135.14/3.99 ×16MM145.14/3.99 ×4MM175.14/3.99 ×16MM185.14/3.99 ×16P bulk → well_vddN bulk → subBias referenceMM46.22/8.33 ×4P bulk → well_vddCompensation capacitorsCC0_051.3/51.3CCLOCAL_051.6/51.6CCLOCAL_151.6/51.6CCLOCAL_251.6/51.6CCLOCAL_351.6/51.6Bulk ties and device banksRRtap_net31_0A=4 µm²RRtap_net31_1A=4 µm²RRtap_net31_2A=4 µm²XBANK1Bank1_18x_ntap1XBANK2Bank2_101x_ptap1XBANK3Bank3_12x_cap_cmimModels: sg13_lv_nmos · sg13_lv_pmos · ntap1 · cap_cmim - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md index 7a38dcbfed5734aebffdc52935115a660c7abb81..10bf8ee29347ac28241489d0e622bdc5b2e67a0b 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md @@ -12,17 +12,17 @@ and both explicitly added physical capacitor arrays. ## Inputs and Interface - `materials/circuit.cdl`: authoritative native physical connectivity. -- `materials/circuit.spice`: equivalent simulation connectivity including finite body contacts. +- `materials/circuit.spice`: equivalent simulation connectivity with logical body nets. - `materials/testbench.spice`: DC, bilateral-loop and sustained-step measurements. Ordered ports: `vss vdd vinn vinp vout net013`. VSS/VDD are return/supply; VINN/VINP are inverting/noninverting inputs; VOUT is output; `net013` connects to the external bias sink. Input PMOS bodies use the separate `net31` source-tied well; other PMOS use VDD and NMOS use the VSS substrate. -Preserve all 24 MOS groups, 225 physical fingers, +Preserve all 24 MOS groups, W/L/m, every body connection and all physical passive devices. -MOS dimensions are rounded to the 10 nm physical grid. Parallel regrouping within each original group preserves rounded total W and L, with each finger at most 10 um wide; individual widths/multiplicities and diffusion perimeters change accordingly. Distributed 2 × 2 um body contacts have spacing at most 20 um. All internal capacitors use `cap_cmim`: +MOS dimensions retain the declared grid adaptation. All internal capacitors use `cap_cmim`: - `c0`: `net063` (top) to `vout` (bottom), 1 parallel 51.3 × 51.3 um MIM units. - `clocal`: `net050` (top) to `vout` (bottom), 4 parallel 51.64 × 51.64 um MIM units. @@ -59,9 +59,8 @@ Post-layout simulation uses the submitted GDS's complete Magic RC, with physical MIM devices and interconnect resistances/capacitances. Half-grid import is explicit. Magic retains only Metal3 interface labels in its isolated extraction copy to avoid repeated internal well-name aliases, while native LVS -checks the original GDS and its explicit tap devices. No resistance/capacitance threshold omits small parasitics. -Magic idealizes well/substrate taps, whereas source simulation uses finite -physical tap models. Distributed substrate resistance/noise and fabrication +checks the original GDS and its actual body-contact connectivity. No resistance/capacitance threshold omits small parasitics. +Source simulation and extraction use the same logical body-net boundary. Distributed substrate resistance/noise and fabrication signoff remain unqualified. The long independent witness is a feasibility layout, not an area optimum. @@ -102,7 +101,7 @@ The measurements below use the supplied SPICE node and source names. `v(n)` is a | `peak_v` | TRAN: Maximum of `v(vout) from=2u to=20u`. | V | target / target | 0 … 1.2 | 1.2 | response | | `trough_v` | TRAN: Minimum of `v(vout) from=20.04u to=40u`. | V | target / target | 0 … 1.2 | 1.2 | response | -Area reference: **84393.45 um2**. The expanded circuit has 364 device instances, a sum of device/contact envelopes 55883.1016 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. +Area reference: **84393.45 um2**. The reference engineering estimate used 364 device instances, a sum of device/contact envelopes 55883.1016 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. Reference MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. The capability coefficient is **8**, independent of this task's reference-normalized score. @@ -137,3 +136,5 @@ Multiple-crossing feedback amplifier: loaded recovery 28.6%, loop stability 24.5 Solve budget: **3 hours**. Discover inputs, resources and feedback through `/protocol/task.json`, `/protocol/resources.json`, `/protocol/harness.json`. Use supplied IHP primitives and KLayout, Magic and ngspice; explicitly submit after writing `/workspace/output/final.gds`. Host configuration, source records and reference solutions are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml index c7805bfdd8196b245d2127d8d48561c8b2ff2751..a8dd75e3f6794d5fc716c2280e229fc9a536b6dc 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml @@ -4,13 +4,6 @@ title = "Song DACFC Three-Stage Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "e1b77c7dea64e2d216a8a67e5addacf0e06a7ecddadb3093c237ba0b0a128186" - [[assets]] path = "reference/amp_016_song_dacfc.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "612d0d659b07cc0eda83b7292882651ac30901421033d4ecae9b5b598ae212c5" +sha256 = "1cdb4772acf4253eb495d7fba18370d6cfe009b26763c7795976d918dc45a7e8" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_016_song_dacfc" -sha256 = "cc7cee55037a3aa08fbbc4323632ff893f435beea53209e451e1e948293363a4" +sha256 = "5658b9596b3ed2b28c97f87fc0b7df00533cd950b6a70a61b6d64a8d4f4701e3" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "d848e329f6fdc8d2bb8d22c278be92a5de29647ba28d3ebbc7a4f23ba8353b3a" +sha256 = "9f0e9f4dc6c61bac1265af4dd7080136da53b15901da907b5c80bbe1a66f8810" [task.inputs.performance] path = "materials/testbench.spice" @@ -686,10 +679,10 @@ upper = 1e-06 rationale = "The ideal external feedback/injection fixture must preserve its stated common mode and DC feedback; 1 uV is the numerical consistency allowance for this measurement fixture." [task.evaluation.pre_layout] -source_report_sha256 = "f0a689c482194a284f6904b74db7a72eb8cd8a35ddb9cf6634940bff9ec48e25" +source_report_sha256 = "085108a4c505dd48ab1b0bbbbd7b3a2f5a5bed0af48e33d2346503260455f68f" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5d384a76e9c131bac2ca2ea8519a17d0769e9ef6e93bd9cad97f6294738568db\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -729,65 +722,60 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "38aa2c96d47fdfb664ed7c4bba002d9803750c3f39fe757233717875690726b4" -dut = "d848e329f6fdc8d2bb8d22c278be92a5de29647ba28d3ebbc7a4f23ba8353b3a" +dut = "9f0e9f4dc6c61bac1265af4dd7080136da53b15901da907b5c80bbe1a66f8810" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 1.094388433264965 +value = 1.09438836490189 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = 0.001331662 +value = 0.00133088 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] -value = 0.415924 +value = 0.4159528 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] -value = 0.04387765 +value = 0.04415878 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] -value = 0.3182086 +value = 0.3180102 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0002266865 +value = 0.0002269607 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] -value = 0.4912286 +value = 0.4915589 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] -value = 0.2573824 +value = 0.2569881 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.3214231648017872 +value = 0.3214228156357129 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0001971055167180119 +value = 0.0001971054952361139 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 0.0334657 +value = 0.0336415 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] -value = 0.109958 +value = 0.1108187 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 0.1522979 +value = 0.1533037 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "35797c341e43645e74ed67110b09e4322d70401bcf201b0a3bd1e972782d8d4c" -ac = "e419e21fc1cd797b860c2c014ef1ce37283efc4a8903ffa68edd4f76dc3feafd" -transient = "46596243de275ebeed798bb765eeb137217b2822b20a8ebf994c98f8941b4fae" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -814,28 +802,24 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "bd58d5fef7c72e008a56888d98175601bb2c59bd439ee7a7c4281d03d718f1cf" -dut = "d848e329f6fdc8d2bb8d22c278be92a5de29647ba28d3ebbc7a4f23ba8353b3a" +dut = "9f0e9f4dc6c61bac1265af4dd7080136da53b15901da907b5c80bbe1a66f8810" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] -value = 3.772583379143681e-11 +value = 3.772661258926385e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] -value = 45.1236 +value = 45.12359 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] -value = 69.4786 +value = 69.47878 unit = "dB" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "27b3b376231732b71a5d8b39ee5a5febb215139e1fad4973363920638a6e6f89" -ac = "5fc56cfcf1f0ec53b4382de4a75fa52b6df57d4dbb6754660016f60eb7c23ac5" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -875,7 +859,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl index 3b81e9e2c6063d70f40b880191ee9d65cee16a3a..05828130b22b7523e66837b705f54759958c1ab7 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl @@ -1,951 +1,43 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_016_song_dacfc vss vdd vinn vinp vout net013 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM0_0 net013 net013 vdd well_0 sg13_lv_pmos w=1u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM0_1 net013 net013 vdd well_1 sg13_lv_pmos w=1u l=1u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM0_2 net013 net013 vdd well_2 sg13_lv_pmos w=1u l=1u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM0_3 net013 net013 vdd well_3 sg13_lv_pmos w=1u l=1u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM0_4 net013 net013 vdd well_4 sg13_lv_pmos w=1u l=1u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM0_5 net013 net013 vdd well_5 sg13_lv_pmos w=1u l=1u m=1 -RT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -MM0_6 net013 net013 vdd well_6 sg13_lv_pmos w=1u l=1u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM0_7 net013 net013 vdd well_7 sg13_lv_pmos w=1u l=1u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM0_8 net013 net013 vdd well_8 sg13_lv_pmos w=1u l=1u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM0_9 net013 net013 vdd well_9 sg13_lv_pmos w=1u l=1u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM0_10 net013 net013 vdd well_10 sg13_lv_pmos w=1u l=1u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM0_11 net013 net013 vdd well_11 sg13_lv_pmos w=1u l=1u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM0_12 net013 net013 vdd well_12 sg13_lv_pmos w=1u l=1u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM0_13 net013 net013 vdd well_13 sg13_lv_pmos w=1u l=1u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM0_14 net013 net013 vdd well_14 sg13_lv_pmos w=1u l=1u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM0_15 net013 net013 vdd well_15 sg13_lv_pmos w=1u l=1u m=1 -RT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -MM1_0 vb4 net013 vdd well_16 sg13_lv_pmos w=1u l=1u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM1_1 vb4 net013 vdd well_17 sg13_lv_pmos w=1u l=1u m=1 -RT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -MM1_2 vb4 net013 vdd well_18 sg13_lv_pmos w=1u l=1u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM1_3 vb4 net013 vdd well_19 sg13_lv_pmos w=1u l=1u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM1_4 vb4 net013 vdd well_20 sg13_lv_pmos w=1u l=1u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM1_5 vb4 net013 vdd well_21 sg13_lv_pmos w=1u l=1u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM1_6 vb4 net013 vdd well_22 sg13_lv_pmos w=1u l=1u m=1 -RT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -MM1_7 vb4 net013 vdd well_23 sg13_lv_pmos w=1u l=1u m=1 -RT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -MM1_8 vb4 net013 vdd well_24 sg13_lv_pmos w=1u l=1u m=1 -RT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -MM1_9 vb4 net013 vdd well_25 sg13_lv_pmos w=1u l=1u m=1 -RT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -MM1_10 vb4 net013 vdd well_26 sg13_lv_pmos w=1u l=1u m=1 -RT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -MM1_11 vb4 net013 vdd well_27 sg13_lv_pmos w=1u l=1u m=1 -RT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -MM1_12 vb4 net013 vdd well_28 sg13_lv_pmos w=1u l=1u m=1 -RT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -MM1_13 vb4 net013 vdd well_29 sg13_lv_pmos w=1u l=1u m=1 -RT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -MM1_14 vb4 net013 vdd well_30 sg13_lv_pmos w=1u l=1u m=1 -RT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -MM1_15 vb4 net013 vdd well_31 sg13_lv_pmos w=1u l=1u m=1 -RT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -MM10_0 net043 net4 vdd well_32 sg13_lv_pmos w=1u l=1u m=1 -RT33 vdd well_33 ntap1 A=4e-12 P=8e-6 -MM10_1 net043 net4 vdd well_33 sg13_lv_pmos w=1u l=1u m=1 -RT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -MM10_2 net043 net4 vdd well_34 sg13_lv_pmos w=1u l=1u m=1 -RT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -MM10_3 net043 net4 vdd well_35 sg13_lv_pmos w=1u l=1u m=1 -RT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -MM11_0 vout net4 vdd well_36 sg13_lv_pmos w=1u l=1u m=1 -RT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -MM11_1 vout net4 vdd well_37 sg13_lv_pmos w=1u l=1u m=1 -RT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -MM11_2 vout net4 vdd well_38 sg13_lv_pmos w=1u l=1u m=1 -RT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -MM11_3 vout net4 vdd well_39 sg13_lv_pmos w=1u l=1u m=1 -RT40 vss sub ptap1 A=4e-12 P=8e-6 -MM12_0 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT41 vss sub ptap1 A=4e-12 P=8e-6 -MM12_1 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT42 vss sub ptap1 A=4e-12 P=8e-6 -MM12_2 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT43 vss sub ptap1 A=4e-12 P=8e-6 -MM12_3 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT44 vss sub ptap1 A=4e-12 P=8e-6 -MM12_4 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT45 vss sub ptap1 A=4e-12 P=8e-6 -MM12_5 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT46 vss sub ptap1 A=4e-12 P=8e-6 -MM12_6 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT47 vss sub ptap1 A=4e-12 P=8e-6 -MM12_7 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT48 vss sub ptap1 A=4e-12 P=8e-6 -MM12_8 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT49 vss sub ptap1 A=4e-12 P=8e-6 -MM12_9 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT50 vss sub ptap1 A=4e-12 P=8e-6 -MM12_10 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT51 vss sub ptap1 A=4e-12 P=8e-6 -MM12_11 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT52 vss sub ptap1 A=4e-12 P=8e-6 -MM12_12 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT53 vss sub ptap1 A=4e-12 P=8e-6 -MM12_13 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT54 vss sub ptap1 A=4e-12 P=8e-6 -MM12_14 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT55 vss sub ptap1 A=4e-12 P=8e-6 -MM12_15 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -RT56 vss sub ptap1 A=4e-12 P=8e-6 -MM13_0 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT57 vss sub ptap1 A=4e-12 P=8e-6 -MM13_1 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT58 vss sub ptap1 A=4e-12 P=8e-6 -MM13_2 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT59 vss sub ptap1 A=4e-12 P=8e-6 -MM13_3 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT60 vss sub ptap1 A=4e-12 P=8e-6 -MM13_4 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT61 vss sub ptap1 A=4e-12 P=8e-6 -MM13_5 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT62 vss sub ptap1 A=4e-12 P=8e-6 -MM13_6 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT63 vss sub ptap1 A=4e-12 P=8e-6 -MM13_7 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT64 vss sub ptap1 A=4e-12 P=8e-6 -MM13_8 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT65 vss sub ptap1 A=4e-12 P=8e-6 -MM13_9 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT66 vss sub ptap1 A=4e-12 P=8e-6 -MM13_10 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT67 vss sub ptap1 A=4e-12 P=8e-6 -MM13_11 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT68 vss sub ptap1 A=4e-12 P=8e-6 -MM13_12 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT69 vss sub ptap1 A=4e-12 P=8e-6 -MM13_13 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT70 vss sub ptap1 A=4e-12 P=8e-6 -MM13_14 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT71 vss sub ptap1 A=4e-12 P=8e-6 -MM13_15 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -RT72 vss sub ptap1 A=4e-12 P=8e-6 -MM14_0 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT73 vss sub ptap1 A=4e-12 P=8e-6 -MM14_1 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT74 vss sub ptap1 A=4e-12 P=8e-6 -MM14_2 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT75 vss sub ptap1 A=4e-12 P=8e-6 -MM14_3 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT76 vss sub ptap1 A=4e-12 P=8e-6 -MM15_0 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT77 vss sub ptap1 A=4e-12 P=8e-6 -MM15_1 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT78 vss sub ptap1 A=4e-12 P=8e-6 -MM15_2 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT79 vss sub ptap1 A=4e-12 P=8e-6 -MM15_3 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT80 vss sub ptap1 A=4e-12 P=8e-6 -MM15_4 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT81 vss sub ptap1 A=4e-12 P=8e-6 -MM15_5 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT82 vss sub ptap1 A=4e-12 P=8e-6 -MM15_6 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT83 vss sub ptap1 A=4e-12 P=8e-6 -MM15_7 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT84 vss sub ptap1 A=4e-12 P=8e-6 -MM15_8 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT85 vss sub ptap1 A=4e-12 P=8e-6 -MM15_9 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT86 vss sub ptap1 A=4e-12 P=8e-6 -MM15_10 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT87 vss sub ptap1 A=4e-12 P=8e-6 -MM15_11 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT88 vss sub ptap1 A=4e-12 P=8e-6 -MM15_12 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT89 vss sub ptap1 A=4e-12 P=8e-6 -MM15_13 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT90 vss sub ptap1 A=4e-12 P=8e-6 -MM15_14 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT91 vss sub ptap1 A=4e-12 P=8e-6 -MM15_15 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -RT92 vss sub ptap1 A=4e-12 P=8e-6 -MM16_0 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT93 vss sub ptap1 A=4e-12 P=8e-6 -MM16_1 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT94 vss sub ptap1 A=4e-12 P=8e-6 -MM16_2 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT95 vss sub ptap1 A=4e-12 P=8e-6 -MM16_3 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT96 vss sub ptap1 A=4e-12 P=8e-6 -MM16_4 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT97 vss sub ptap1 A=4e-12 P=8e-6 -MM16_5 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT98 vss sub ptap1 A=4e-12 P=8e-6 -MM16_6 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT99 vss sub ptap1 A=4e-12 P=8e-6 -MM16_7 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT100 vss sub ptap1 A=4e-12 P=8e-6 -MM16_8 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT101 vss sub ptap1 A=4e-12 P=8e-6 -MM16_9 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT102 vss sub ptap1 A=4e-12 P=8e-6 -MM16_10 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT103 vss sub ptap1 A=4e-12 P=8e-6 -MM16_11 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT104 vss sub ptap1 A=4e-12 P=8e-6 -MM16_12 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT105 vss sub ptap1 A=4e-12 P=8e-6 -MM16_13 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT106 vss sub ptap1 A=4e-12 P=8e-6 -MM16_14 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT107 vss sub ptap1 A=4e-12 P=8e-6 -MM16_15 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -RT108 vss sub ptap1 A=4e-12 P=8e-6 -MM17_0 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT109 vss sub ptap1 A=4e-12 P=8e-6 -MM17_1 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT110 vss sub ptap1 A=4e-12 P=8e-6 -MM17_2 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT111 vss sub ptap1 A=4e-12 P=8e-6 -MM17_3 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT112 vss sub ptap1 A=4e-12 P=8e-6 -MM17_4 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT113 vss sub ptap1 A=4e-12 P=8e-6 -MM17_5 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT114 vss sub ptap1 A=4e-12 P=8e-6 -MM17_6 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT115 vss sub ptap1 A=4e-12 P=8e-6 -MM17_7 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT116 vss sub ptap1 A=4e-12 P=8e-6 -MM17_8 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT117 vss sub ptap1 A=4e-12 P=8e-6 -MM17_9 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT118 vss sub ptap1 A=4e-12 P=8e-6 -MM17_10 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT119 vss sub ptap1 A=4e-12 P=8e-6 -MM17_11 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT120 vss sub ptap1 A=4e-12 P=8e-6 -MM17_12 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT121 vss sub ptap1 A=4e-12 P=8e-6 -MM17_13 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT122 vss sub ptap1 A=4e-12 P=8e-6 -MM17_14 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT123 vss sub ptap1 A=4e-12 P=8e-6 -MM17_15 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT124 vss sub ptap1 A=4e-12 P=8e-6 -MM18_0 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT125 vss sub ptap1 A=4e-12 P=8e-6 -MM18_1 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT126 vss sub ptap1 A=4e-12 P=8e-6 -MM18_2 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT127 vss sub ptap1 A=4e-12 P=8e-6 -MM18_3 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT128 vss sub ptap1 A=4e-12 P=8e-6 -MM18_4 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT129 vss sub ptap1 A=4e-12 P=8e-6 -MM18_5 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT130 vss sub ptap1 A=4e-12 P=8e-6 -MM18_6 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT131 vss sub ptap1 A=4e-12 P=8e-6 -MM18_7 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT132 vss sub ptap1 A=4e-12 P=8e-6 -MM18_8 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT133 vss sub ptap1 A=4e-12 P=8e-6 -MM18_9 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT134 vss sub ptap1 A=4e-12 P=8e-6 -MM18_10 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT135 vss sub ptap1 A=4e-12 P=8e-6 -MM18_11 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT136 vss sub ptap1 A=4e-12 P=8e-6 -MM18_12 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT137 vss sub ptap1 A=4e-12 P=8e-6 -MM18_13 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT138 vss sub ptap1 A=4e-12 P=8e-6 -MM18_14 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT139 vss sub ptap1 A=4e-12 P=8e-6 -MM18_15 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT140 vss sub ptap1 A=4e-12 P=8e-6 -MM19_0 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT141 vss sub ptap1 A=4e-12 P=8e-6 -MM19_1 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT142 vss sub ptap1 A=4e-12 P=8e-6 -MM19_2 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT143 vss sub ptap1 A=4e-12 P=8e-6 -MM19_3 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT144 vss sub ptap1 A=4e-12 P=8e-6 -MM19_4 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT145 vss sub ptap1 A=4e-12 P=8e-6 -MM19_5 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT146 vss sub ptap1 A=4e-12 P=8e-6 -MM19_6 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT147 vss sub ptap1 A=4e-12 P=8e-6 -MM19_7 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT148 vss sub ptap1 A=4e-12 P=8e-6 -MM19_8 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT149 vss sub ptap1 A=4e-12 P=8e-6 -MM19_9 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT150 vss sub ptap1 A=4e-12 P=8e-6 -MM19_10 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT151 vss sub ptap1 A=4e-12 P=8e-6 -MM19_11 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT152 vss sub ptap1 A=4e-12 P=8e-6 -MM19_12 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT153 vss sub ptap1 A=4e-12 P=8e-6 -MM19_13 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT154 vss sub ptap1 A=4e-12 P=8e-6 -MM19_14 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT155 vss sub ptap1 A=4e-12 P=8e-6 -MM19_15 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT156 vss sub ptap1 A=4e-12 P=8e-6 -MM19_16 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT157 vss sub ptap1 A=4e-12 P=8e-6 -MM19_17 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT158 vss sub ptap1 A=4e-12 P=8e-6 -MM19_18 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT159 vss sub ptap1 A=4e-12 P=8e-6 -MM19_19 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT160 vss sub ptap1 A=4e-12 P=8e-6 -MM19_20 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT161 vss sub ptap1 A=4e-12 P=8e-6 -MM19_21 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT162 vss sub ptap1 A=4e-12 P=8e-6 -MM19_22 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT163 vss sub ptap1 A=4e-12 P=8e-6 -MM19_23 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT164 vss sub ptap1 A=4e-12 P=8e-6 -MM19_24 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT165 vss sub ptap1 A=4e-12 P=8e-6 -MM19_25 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT166 vss sub ptap1 A=4e-12 P=8e-6 -MM19_26 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT167 vss sub ptap1 A=4e-12 P=8e-6 -MM19_27 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT168 vss sub ptap1 A=4e-12 P=8e-6 -MM19_28 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT169 vss sub ptap1 A=4e-12 P=8e-6 -MM19_29 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT170 vss sub ptap1 A=4e-12 P=8e-6 -MM19_30 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT171 vss sub ptap1 A=4e-12 P=8e-6 -MM19_31 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT172 vdd well_172 ntap1 A=4e-12 P=8e-6 -MM2_0 dm_1 dm_1 vdd well_172 sg13_lv_pmos w=1u l=1u m=1 -RT173 vdd well_173 ntap1 A=4e-12 P=8e-6 -MM2_1 dm_1 dm_1 vdd well_173 sg13_lv_pmos w=1u l=1u m=1 -RT174 vdd well_174 ntap1 A=4e-12 P=8e-6 -MM2_2 dm_1 dm_1 vdd well_174 sg13_lv_pmos w=1u l=1u m=1 -RT175 vdd well_175 ntap1 A=4e-12 P=8e-6 -MM2_3 dm_1 dm_1 vdd well_175 sg13_lv_pmos w=1u l=1u m=1 -RT176 vss sub ptap1 A=4e-12 P=8e-6 -MM20_0 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT177 vss sub ptap1 A=4e-12 P=8e-6 -MM20_1 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT178 vss sub ptap1 A=4e-12 P=8e-6 -MM20_2 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT179 vss sub ptap1 A=4e-12 P=8e-6 -MM20_3 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT180 vss sub ptap1 A=4e-12 P=8e-6 -MM20_4 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT181 vss sub ptap1 A=4e-12 P=8e-6 -MM20_5 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT182 vss sub ptap1 A=4e-12 P=8e-6 -MM20_6 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT183 vss sub ptap1 A=4e-12 P=8e-6 -MM20_7 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT184 vss sub ptap1 A=4e-12 P=8e-6 -MM20_8 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT185 vss sub ptap1 A=4e-12 P=8e-6 -MM20_9 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT186 vss sub ptap1 A=4e-12 P=8e-6 -MM20_10 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT187 vss sub ptap1 A=4e-12 P=8e-6 -MM20_11 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT188 vss sub ptap1 A=4e-12 P=8e-6 -MM20_12 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT189 vss sub ptap1 A=4e-12 P=8e-6 -MM20_13 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT190 vss sub ptap1 A=4e-12 P=8e-6 -MM20_14 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT191 vss sub ptap1 A=4e-12 P=8e-6 -MM20_15 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT192 vss sub ptap1 A=4e-12 P=8e-6 -MM20_16 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT193 vss sub ptap1 A=4e-12 P=8e-6 -MM20_17 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT194 vss sub ptap1 A=4e-12 P=8e-6 -MM20_18 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT195 vss sub ptap1 A=4e-12 P=8e-6 -MM20_19 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT196 vss sub ptap1 A=4e-12 P=8e-6 -MM20_20 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT197 vss sub ptap1 A=4e-12 P=8e-6 -MM20_21 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT198 vss sub ptap1 A=4e-12 P=8e-6 -MM20_22 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT199 vss sub ptap1 A=4e-12 P=8e-6 -MM20_23 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT200 vss sub ptap1 A=4e-12 P=8e-6 -MM20_24 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT201 vss sub ptap1 A=4e-12 P=8e-6 -MM20_25 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT202 vss sub ptap1 A=4e-12 P=8e-6 -MM20_26 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT203 vss sub ptap1 A=4e-12 P=8e-6 -MM20_27 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT204 vss sub ptap1 A=4e-12 P=8e-6 -MM20_28 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT205 vss sub ptap1 A=4e-12 P=8e-6 -MM20_29 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT206 vss sub ptap1 A=4e-12 P=8e-6 -MM20_30 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT207 vss sub ptap1 A=4e-12 P=8e-6 -MM20_31 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT208 vss sub ptap1 A=4e-12 P=8e-6 -MM21_0 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT209 vss sub ptap1 A=4e-12 P=8e-6 -MM21_1 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT210 vss sub ptap1 A=4e-12 P=8e-6 -MM21_2 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT211 vss sub ptap1 A=4e-12 P=8e-6 -MM21_3 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT212 vss sub ptap1 A=4e-12 P=8e-6 -MM22_0 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT213 vss sub ptap1 A=4e-12 P=8e-6 -MM22_1 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT214 vss sub ptap1 A=4e-12 P=8e-6 -MM22_2 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT215 vss sub ptap1 A=4e-12 P=8e-6 -MM22_3 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT216 vss sub ptap1 A=4e-12 P=8e-6 -MM23_0 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT217 vss sub ptap1 A=4e-12 P=8e-6 -MM23_1 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT218 vss sub ptap1 A=4e-12 P=8e-6 -MM23_2 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT219 vss sub ptap1 A=4e-12 P=8e-6 -MM23_3 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT220 vdd well_220 ntap1 A=4e-12 P=8e-6 -MM3_0 vb3 net013 vdd well_220 sg13_lv_pmos w=1u l=1u m=1 -RT221 vdd well_221 ntap1 A=4e-12 P=8e-6 -MM3_1 vb3 net013 vdd well_221 sg13_lv_pmos w=1u l=1u m=1 -RT222 vdd well_222 ntap1 A=4e-12 P=8e-6 -MM3_2 vb3 net013 vdd well_222 sg13_lv_pmos w=1u l=1u m=1 -RT223 vdd well_223 ntap1 A=4e-12 P=8e-6 -MM3_3 vb3 net013 vdd well_223 sg13_lv_pmos w=1u l=1u m=1 -RT224 vdd well_224 ntap1 A=4e-12 P=8e-6 -MM3_4 vb3 net013 vdd well_224 sg13_lv_pmos w=1u l=1u m=1 -RT225 vdd well_225 ntap1 A=4e-12 P=8e-6 -MM3_5 vb3 net013 vdd well_225 sg13_lv_pmos w=1u l=1u m=1 -RT226 vdd well_226 ntap1 A=4e-12 P=8e-6 -MM3_6 vb3 net013 vdd well_226 sg13_lv_pmos w=1u l=1u m=1 -RT227 vdd well_227 ntap1 A=4e-12 P=8e-6 -MM3_7 vb3 net013 vdd well_227 sg13_lv_pmos w=1u l=1u m=1 -RT228 vdd well_228 ntap1 A=4e-12 P=8e-6 -MM3_8 vb3 net013 vdd well_228 sg13_lv_pmos w=1u l=1u m=1 -RT229 vdd well_229 ntap1 A=4e-12 P=8e-6 -MM3_9 vb3 net013 vdd well_229 sg13_lv_pmos w=1u l=1u m=1 -RT230 vdd well_230 ntap1 A=4e-12 P=8e-6 -MM3_10 vb3 net013 vdd well_230 sg13_lv_pmos w=1u l=1u m=1 -RT231 vdd well_231 ntap1 A=4e-12 P=8e-6 -MM3_11 vb3 net013 vdd well_231 sg13_lv_pmos w=1u l=1u m=1 -RT232 vdd well_232 ntap1 A=4e-12 P=8e-6 -MM3_12 vb3 net013 vdd well_232 sg13_lv_pmos w=1u l=1u m=1 -RT233 vdd well_233 ntap1 A=4e-12 P=8e-6 -MM3_13 vb3 net013 vdd well_233 sg13_lv_pmos w=1u l=1u m=1 -RT234 vdd well_234 ntap1 A=4e-12 P=8e-6 -MM3_14 vb3 net013 vdd well_234 sg13_lv_pmos w=1u l=1u m=1 -RT235 vdd well_235 ntap1 A=4e-12 P=8e-6 -MM3_15 vb3 net013 vdd well_235 sg13_lv_pmos w=1u l=1u m=1 -RT236 vdd well_236 ntap1 A=4e-12 P=8e-6 -MM4_0 net31 net013 vdd well_236 sg13_lv_pmos w=1u l=1u m=1 -RT237 vdd well_237 ntap1 A=4e-12 P=8e-6 -MM4_1 net31 net013 vdd well_237 sg13_lv_pmos w=1u l=1u m=1 -RT238 vdd well_238 ntap1 A=4e-12 P=8e-6 -MM4_2 net31 net013 vdd well_238 sg13_lv_pmos w=1u l=1u m=1 -RT239 vdd well_239 ntap1 A=4e-12 P=8e-6 -MM4_3 net31 net013 vdd well_239 sg13_lv_pmos w=1u l=1u m=1 -RT240 vdd well_240 ntap1 A=4e-12 P=8e-6 -MM4_4 net31 net013 vdd well_240 sg13_lv_pmos w=1u l=1u m=1 -RT241 vdd well_241 ntap1 A=4e-12 P=8e-6 -MM4_5 net31 net013 vdd well_241 sg13_lv_pmos w=1u l=1u m=1 -RT242 vdd well_242 ntap1 A=4e-12 P=8e-6 -MM4_6 net31 net013 vdd well_242 sg13_lv_pmos w=1u l=1u m=1 -RT243 vdd well_243 ntap1 A=4e-12 P=8e-6 -MM4_7 net31 net013 vdd well_243 sg13_lv_pmos w=1u l=1u m=1 -RT244 vdd well_244 ntap1 A=4e-12 P=8e-6 -MM5_0 net5 voutn vdd well_244 sg13_lv_pmos w=1u l=1u m=1 -RT245 vdd well_245 ntap1 A=4e-12 P=8e-6 -MM5_1 net5 voutn vdd well_245 sg13_lv_pmos w=1u l=1u m=1 -RT246 vdd well_246 ntap1 A=4e-12 P=8e-6 -MM5_2 net5 voutn vdd well_246 sg13_lv_pmos w=1u l=1u m=1 -RT247 vdd well_247 ntap1 A=4e-12 P=8e-6 -MM5_3 net5 voutn vdd well_247 sg13_lv_pmos w=1u l=1u m=1 -RT248 net1 well_248 ntap1 A=4e-12 P=8e-6 -MM57_0 net043 vinn net1 well_248 sg13_lv_pmos w=1u l=1u m=1 -RT249 net1 well_249 ntap1 A=4e-12 P=8e-6 -MM57_1 net043 vinn net1 well_249 sg13_lv_pmos w=1u l=1u m=1 -RT250 net1 well_250 ntap1 A=4e-12 P=8e-6 -MM57_2 net043 vinn net1 well_250 sg13_lv_pmos w=1u l=1u m=1 -RT251 net1 well_251 ntap1 A=4e-12 P=8e-6 -MM57_3 net043 vinn net1 well_251 sg13_lv_pmos w=1u l=1u m=1 -RT252 net1 well_252 ntap1 A=4e-12 P=8e-6 -MM58_0 net049 vinp net1 well_252 sg13_lv_pmos w=1u l=1u m=1 -RT253 net1 well_253 ntap1 A=4e-12 P=8e-6 -MM58_1 net049 vinp net1 well_253 sg13_lv_pmos w=1u l=1u m=1 -RT254 net1 well_254 ntap1 A=4e-12 P=8e-6 -MM58_2 net049 vinp net1 well_254 sg13_lv_pmos w=1u l=1u m=1 -RT255 net1 well_255 ntap1 A=4e-12 P=8e-6 -MM58_3 net049 vinp net1 well_255 sg13_lv_pmos w=1u l=1u m=1 -RT256 vdd well_256 ntap1 A=4e-12 P=8e-6 -MM59_0 net1 net013 vdd well_256 sg13_lv_pmos w=1u l=1u m=1 -RT257 vdd well_257 ntap1 A=4e-12 P=8e-6 -MM59_1 net1 net013 vdd well_257 sg13_lv_pmos w=1u l=1u m=1 -RT258 vdd well_258 ntap1 A=4e-12 P=8e-6 -MM59_2 net1 net013 vdd well_258 sg13_lv_pmos w=1u l=1u m=1 -RT259 vdd well_259 ntap1 A=4e-12 P=8e-6 -MM59_3 net1 net013 vdd well_259 sg13_lv_pmos w=1u l=1u m=1 -RT260 vdd well_260 ntap1 A=4e-12 P=8e-6 -MM59_4 net1 net013 vdd well_260 sg13_lv_pmos w=1u l=1u m=1 -RT261 vdd well_261 ntap1 A=4e-12 P=8e-6 -MM59_5 net1 net013 vdd well_261 sg13_lv_pmos w=1u l=1u m=1 -RT262 vdd well_262 ntap1 A=4e-12 P=8e-6 -MM59_6 net1 net013 vdd well_262 sg13_lv_pmos w=1u l=1u m=1 -RT263 vdd well_263 ntap1 A=4e-12 P=8e-6 -MM59_7 net1 net013 vdd well_263 sg13_lv_pmos w=1u l=1u m=1 -RT264 vdd well_264 ntap1 A=4e-12 P=8e-6 -MM6_0 net050 voutn vdd well_264 sg13_lv_pmos w=1u l=1u m=1 -RT265 vdd well_265 ntap1 A=4e-12 P=8e-6 -MM6_1 net050 voutn vdd well_265 sg13_lv_pmos w=1u l=1u m=1 -RT266 vdd well_266 ntap1 A=4e-12 P=8e-6 -MM6_2 net050 voutn vdd well_266 sg13_lv_pmos w=1u l=1u m=1 -RT267 vdd well_267 ntap1 A=4e-12 P=8e-6 -MM6_3 net050 voutn vdd well_267 sg13_lv_pmos w=1u l=1u m=1 -RT268 vdd well_268 ntap1 A=4e-12 P=8e-6 -MM60_0 voutn dm_1 net5 well_268 sg13_lv_pmos w=1u l=1u m=1 -RT269 vdd well_269 ntap1 A=4e-12 P=8e-6 -MM60_1 voutn dm_1 net5 well_269 sg13_lv_pmos w=1u l=1u m=1 -RT270 vdd well_270 ntap1 A=4e-12 P=8e-6 -MM60_2 voutn dm_1 net5 well_270 sg13_lv_pmos w=1u l=1u m=1 -RT271 vdd well_271 ntap1 A=4e-12 P=8e-6 -MM60_3 voutn dm_1 net5 well_271 sg13_lv_pmos w=1u l=1u m=1 -RT272 vdd well_272 ntap1 A=4e-12 P=8e-6 -MM60_4 voutn dm_1 net5 well_272 sg13_lv_pmos w=1u l=1u m=1 -RT273 vdd well_273 ntap1 A=4e-12 P=8e-6 -MM60_5 voutn dm_1 net5 well_273 sg13_lv_pmos w=1u l=1u m=1 -RT274 vdd well_274 ntap1 A=4e-12 P=8e-6 -MM60_6 voutn dm_1 net5 well_274 sg13_lv_pmos w=1u l=1u m=1 -RT275 vdd well_275 ntap1 A=4e-12 P=8e-6 -MM60_7 voutn dm_1 net5 well_275 sg13_lv_pmos w=1u l=1u m=1 -RT276 vdd well_276 ntap1 A=4e-12 P=8e-6 -MM60_8 voutn dm_1 net5 well_276 sg13_lv_pmos w=1u l=1u m=1 -RT277 vdd well_277 ntap1 A=4e-12 P=8e-6 -MM60_9 voutn dm_1 net5 well_277 sg13_lv_pmos w=1u l=1u m=1 -RT278 vdd well_278 ntap1 A=4e-12 P=8e-6 -MM60_10 voutn dm_1 net5 well_278 sg13_lv_pmos w=1u l=1u m=1 -RT279 vdd well_279 ntap1 A=4e-12 P=8e-6 -MM60_11 voutn dm_1 net5 well_279 sg13_lv_pmos w=1u l=1u m=1 -RT280 vdd well_280 ntap1 A=4e-12 P=8e-6 -MM60_12 voutn dm_1 net5 well_280 sg13_lv_pmos w=1u l=1u m=1 -RT281 vdd well_281 ntap1 A=4e-12 P=8e-6 -MM60_13 voutn dm_1 net5 well_281 sg13_lv_pmos w=1u l=1u m=1 -RT282 vdd well_282 ntap1 A=4e-12 P=8e-6 -MM60_14 voutn dm_1 net5 well_282 sg13_lv_pmos w=1u l=1u m=1 -RT283 vdd well_283 ntap1 A=4e-12 P=8e-6 -MM60_15 voutn dm_1 net5 well_283 sg13_lv_pmos w=1u l=1u m=1 -RT284 vdd well_284 ntap1 A=4e-12 P=8e-6 -MM61_0 net4 dm_1 net050 well_284 sg13_lv_pmos w=1u l=1u m=1 -RT285 vdd well_285 ntap1 A=4e-12 P=8e-6 -MM61_1 net4 dm_1 net050 well_285 sg13_lv_pmos w=1u l=1u m=1 -RT286 vdd well_286 ntap1 A=4e-12 P=8e-6 -MM61_2 net4 dm_1 net050 well_286 sg13_lv_pmos w=1u l=1u m=1 -RT287 vdd well_287 ntap1 A=4e-12 P=8e-6 -MM61_3 net4 dm_1 net050 well_287 sg13_lv_pmos w=1u l=1u m=1 -RT288 vdd well_288 ntap1 A=4e-12 P=8e-6 -MM61_4 net4 dm_1 net050 well_288 sg13_lv_pmos w=1u l=1u m=1 -RT289 vdd well_289 ntap1 A=4e-12 P=8e-6 -MM61_5 net4 dm_1 net050 well_289 sg13_lv_pmos w=1u l=1u m=1 -RT290 vdd well_290 ntap1 A=4e-12 P=8e-6 -MM61_6 net4 dm_1 net050 well_290 sg13_lv_pmos w=1u l=1u m=1 -RT291 vdd well_291 ntap1 A=4e-12 P=8e-6 -MM61_7 net4 dm_1 net050 well_291 sg13_lv_pmos w=1u l=1u m=1 -RT292 vdd well_292 ntap1 A=4e-12 P=8e-6 -MM61_8 net4 dm_1 net050 well_292 sg13_lv_pmos w=1u l=1u m=1 -RT293 vdd well_293 ntap1 A=4e-12 P=8e-6 -MM61_9 net4 dm_1 net050 well_293 sg13_lv_pmos w=1u l=1u m=1 -RT294 vdd well_294 ntap1 A=4e-12 P=8e-6 -MM61_10 net4 dm_1 net050 well_294 sg13_lv_pmos w=1u l=1u m=1 -RT295 vdd well_295 ntap1 A=4e-12 P=8e-6 -MM61_11 net4 dm_1 net050 well_295 sg13_lv_pmos w=1u l=1u m=1 -RT296 vdd well_296 ntap1 A=4e-12 P=8e-6 -MM61_12 net4 dm_1 net050 well_296 sg13_lv_pmos w=1u l=1u m=1 -RT297 vdd well_297 ntap1 A=4e-12 P=8e-6 -MM61_13 net4 dm_1 net050 well_297 sg13_lv_pmos w=1u l=1u m=1 -RT298 vdd well_298 ntap1 A=4e-12 P=8e-6 -MM61_14 net4 dm_1 net050 well_298 sg13_lv_pmos w=1u l=1u m=1 -RT299 vdd well_299 ntap1 A=4e-12 P=8e-6 -MM61_15 net4 dm_1 net050 well_299 sg13_lv_pmos w=1u l=1u m=1 -RT300 vdd well_300 ntap1 A=4e-12 P=8e-6 -MM62_0 voutn dm_1 net3 well_300 sg13_lv_pmos w=1u l=1u m=1 -RT301 vdd well_301 ntap1 A=4e-12 P=8e-6 -MM62_1 voutn dm_1 net3 well_301 sg13_lv_pmos w=1u l=1u m=1 -RT302 vdd well_302 ntap1 A=4e-12 P=8e-6 -MM62_2 voutn dm_1 net3 well_302 sg13_lv_pmos w=1u l=1u m=1 -RT303 vdd well_303 ntap1 A=4e-12 P=8e-6 -MM62_3 voutn dm_1 net3 well_303 sg13_lv_pmos w=1u l=1u m=1 -RT304 vdd well_304 ntap1 A=4e-12 P=8e-6 -MM62_4 voutn dm_1 net3 well_304 sg13_lv_pmos w=1u l=1u m=1 -RT305 vdd well_305 ntap1 A=4e-12 P=8e-6 -MM62_5 voutn dm_1 net3 well_305 sg13_lv_pmos w=1u l=1u m=1 -RT306 vdd well_306 ntap1 A=4e-12 P=8e-6 -MM62_6 voutn dm_1 net3 well_306 sg13_lv_pmos w=1u l=1u m=1 -RT307 vdd well_307 ntap1 A=4e-12 P=8e-6 -MM62_7 voutn dm_1 net3 well_307 sg13_lv_pmos w=1u l=1u m=1 -RT308 vdd well_308 ntap1 A=4e-12 P=8e-6 -MM62_8 voutn dm_1 net3 well_308 sg13_lv_pmos w=1u l=1u m=1 -RT309 vdd well_309 ntap1 A=4e-12 P=8e-6 -MM62_9 voutn dm_1 net3 well_309 sg13_lv_pmos w=1u l=1u m=1 -RT310 vdd well_310 ntap1 A=4e-12 P=8e-6 -MM62_10 voutn dm_1 net3 well_310 sg13_lv_pmos w=1u l=1u m=1 -RT311 vdd well_311 ntap1 A=4e-12 P=8e-6 -MM62_11 voutn dm_1 net3 well_311 sg13_lv_pmos w=1u l=1u m=1 -RT312 vdd well_312 ntap1 A=4e-12 P=8e-6 -MM62_12 voutn dm_1 net3 well_312 sg13_lv_pmos w=1u l=1u m=1 -RT313 vdd well_313 ntap1 A=4e-12 P=8e-6 -MM62_13 voutn dm_1 net3 well_313 sg13_lv_pmos w=1u l=1u m=1 -RT314 vdd well_314 ntap1 A=4e-12 P=8e-6 -MM62_14 voutn dm_1 net3 well_314 sg13_lv_pmos w=1u l=1u m=1 -RT315 vdd well_315 ntap1 A=4e-12 P=8e-6 -MM62_15 voutn dm_1 net3 well_315 sg13_lv_pmos w=1u l=1u m=1 -RT316 vdd well_316 ntap1 A=4e-12 P=8e-6 -MM63_0 net70 dm_1 net2 well_316 sg13_lv_pmos w=1u l=1u m=1 -RT317 vdd well_317 ntap1 A=4e-12 P=8e-6 -MM63_1 net70 dm_1 net2 well_317 sg13_lv_pmos w=1u l=1u m=1 -RT318 vdd well_318 ntap1 A=4e-12 P=8e-6 -MM63_2 net70 dm_1 net2 well_318 sg13_lv_pmos w=1u l=1u m=1 -RT319 vdd well_319 ntap1 A=4e-12 P=8e-6 -MM63_3 net70 dm_1 net2 well_319 sg13_lv_pmos w=1u l=1u m=1 -RT320 vdd well_320 ntap1 A=4e-12 P=8e-6 -MM63_4 net70 dm_1 net2 well_320 sg13_lv_pmos w=1u l=1u m=1 -RT321 vdd well_321 ntap1 A=4e-12 P=8e-6 -MM63_5 net70 dm_1 net2 well_321 sg13_lv_pmos w=1u l=1u m=1 -RT322 vdd well_322 ntap1 A=4e-12 P=8e-6 -MM63_6 net70 dm_1 net2 well_322 sg13_lv_pmos w=1u l=1u m=1 -RT323 vdd well_323 ntap1 A=4e-12 P=8e-6 -MM63_7 net70 dm_1 net2 well_323 sg13_lv_pmos w=1u l=1u m=1 -RT324 vdd well_324 ntap1 A=4e-12 P=8e-6 -MM63_8 net70 dm_1 net2 well_324 sg13_lv_pmos w=1u l=1u m=1 -RT325 vdd well_325 ntap1 A=4e-12 P=8e-6 -MM63_9 net70 dm_1 net2 well_325 sg13_lv_pmos w=1u l=1u m=1 -RT326 vdd well_326 ntap1 A=4e-12 P=8e-6 -MM63_10 net70 dm_1 net2 well_326 sg13_lv_pmos w=1u l=1u m=1 -RT327 vdd well_327 ntap1 A=4e-12 P=8e-6 -MM63_11 net70 dm_1 net2 well_327 sg13_lv_pmos w=1u l=1u m=1 -RT328 vdd well_328 ntap1 A=4e-12 P=8e-6 -MM63_12 net70 dm_1 net2 well_328 sg13_lv_pmos w=1u l=1u m=1 -RT329 vdd well_329 ntap1 A=4e-12 P=8e-6 -MM63_13 net70 dm_1 net2 well_329 sg13_lv_pmos w=1u l=1u m=1 -RT330 vdd well_330 ntap1 A=4e-12 P=8e-6 -MM63_14 net70 dm_1 net2 well_330 sg13_lv_pmos w=1u l=1u m=1 -RT331 vdd well_331 ntap1 A=4e-12 P=8e-6 -MM63_15 net70 dm_1 net2 well_331 sg13_lv_pmos w=1u l=1u m=1 -RT332 vss sub ptap1 A=4e-12 P=8e-6 -MM64_0 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT333 vss sub ptap1 A=4e-12 P=8e-6 -MM64_1 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT334 vss sub ptap1 A=4e-12 P=8e-6 -MM64_2 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT335 vss sub ptap1 A=4e-12 P=8e-6 -MM64_3 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT336 vss sub ptap1 A=4e-12 P=8e-6 -MM64_4 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT337 vss sub ptap1 A=4e-12 P=8e-6 -MM64_5 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT338 vss sub ptap1 A=4e-12 P=8e-6 -MM64_6 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT339 vss sub ptap1 A=4e-12 P=8e-6 -MM64_7 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT340 vss sub ptap1 A=4e-12 P=8e-6 -MM64_8 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT341 vss sub ptap1 A=4e-12 P=8e-6 -MM64_9 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT342 vss sub ptap1 A=4e-12 P=8e-6 -MM64_10 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT343 vss sub ptap1 A=4e-12 P=8e-6 -MM64_11 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT344 vss sub ptap1 A=4e-12 P=8e-6 -MM64_12 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT345 vss sub ptap1 A=4e-12 P=8e-6 -MM64_13 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT346 vss sub ptap1 A=4e-12 P=8e-6 -MM64_14 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT347 vss sub ptap1 A=4e-12 P=8e-6 -MM64_15 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT348 vss sub ptap1 A=4e-12 P=8e-6 -MM64_16 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT349 vss sub ptap1 A=4e-12 P=8e-6 -MM64_17 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT350 vss sub ptap1 A=4e-12 P=8e-6 -MM64_18 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT351 vss sub ptap1 A=4e-12 P=8e-6 -MM64_19 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT352 vss sub ptap1 A=4e-12 P=8e-6 -MM64_20 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT353 vss sub ptap1 A=4e-12 P=8e-6 -MM64_21 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT354 vss sub ptap1 A=4e-12 P=8e-6 -MM64_22 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT355 vss sub ptap1 A=4e-12 P=8e-6 -MM64_23 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT356 vss sub ptap1 A=4e-12 P=8e-6 -MM64_24 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT357 vss sub ptap1 A=4e-12 P=8e-6 -MM64_25 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT358 vss sub ptap1 A=4e-12 P=8e-6 -MM64_26 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT359 vss sub ptap1 A=4e-12 P=8e-6 -MM64_27 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT360 vss sub ptap1 A=4e-12 P=8e-6 -MM64_28 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT361 vss sub ptap1 A=4e-12 P=8e-6 -MM64_29 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT362 vss sub ptap1 A=4e-12 P=8e-6 -MM64_30 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT363 vss sub ptap1 A=4e-12 P=8e-6 -MM64_31 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT364 vss sub ptap1 A=4e-12 P=8e-6 -MM65_0 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT365 vss sub ptap1 A=4e-12 P=8e-6 -MM65_1 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT366 vss sub ptap1 A=4e-12 P=8e-6 -MM65_2 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT367 vss sub ptap1 A=4e-12 P=8e-6 -MM65_3 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT368 vss sub ptap1 A=4e-12 P=8e-6 -MM65_4 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT369 vss sub ptap1 A=4e-12 P=8e-6 -MM65_5 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT370 vss sub ptap1 A=4e-12 P=8e-6 -MM65_6 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT371 vss sub ptap1 A=4e-12 P=8e-6 -MM65_7 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT372 vss sub ptap1 A=4e-12 P=8e-6 -MM65_8 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT373 vss sub ptap1 A=4e-12 P=8e-6 -MM65_9 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT374 vss sub ptap1 A=4e-12 P=8e-6 -MM65_10 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT375 vss sub ptap1 A=4e-12 P=8e-6 -MM65_11 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT376 vss sub ptap1 A=4e-12 P=8e-6 -MM65_12 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT377 vss sub ptap1 A=4e-12 P=8e-6 -MM65_13 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT378 vss sub ptap1 A=4e-12 P=8e-6 -MM65_14 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT379 vss sub ptap1 A=4e-12 P=8e-6 -MM65_15 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT380 vss sub ptap1 A=4e-12 P=8e-6 -MM65_16 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT381 vss sub ptap1 A=4e-12 P=8e-6 -MM65_17 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT382 vss sub ptap1 A=4e-12 P=8e-6 -MM65_18 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT383 vss sub ptap1 A=4e-12 P=8e-6 -MM65_19 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT384 vss sub ptap1 A=4e-12 P=8e-6 -MM65_20 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT385 vss sub ptap1 A=4e-12 P=8e-6 -MM65_21 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT386 vss sub ptap1 A=4e-12 P=8e-6 -MM65_22 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT387 vss sub ptap1 A=4e-12 P=8e-6 -MM65_23 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT388 vss sub ptap1 A=4e-12 P=8e-6 -MM65_24 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT389 vss sub ptap1 A=4e-12 P=8e-6 -MM65_25 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT390 vss sub ptap1 A=4e-12 P=8e-6 -MM65_26 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT391 vss sub ptap1 A=4e-12 P=8e-6 -MM65_27 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT392 vss sub ptap1 A=4e-12 P=8e-6 -MM65_28 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT393 vss sub ptap1 A=4e-12 P=8e-6 -MM65_29 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT394 vss sub ptap1 A=4e-12 P=8e-6 -MM65_30 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT395 vss sub ptap1 A=4e-12 P=8e-6 -MM65_31 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -RT396 vdd well_396 ntap1 A=4e-12 P=8e-6 -MM68_0 net2 net70 vdd well_396 sg13_lv_pmos w=1u l=1u m=1 -RT397 vdd well_397 ntap1 A=4e-12 P=8e-6 -MM68_1 net2 net70 vdd well_397 sg13_lv_pmos w=1u l=1u m=1 -RT398 vdd well_398 ntap1 A=4e-12 P=8e-6 -MM68_2 net2 net70 vdd well_398 sg13_lv_pmos w=1u l=1u m=1 -RT399 vdd well_399 ntap1 A=4e-12 P=8e-6 -MM68_3 net2 net70 vdd well_399 sg13_lv_pmos w=1u l=1u m=1 -RT400 vdd well_400 ntap1 A=4e-12 P=8e-6 -MM68_4 net2 net70 vdd well_400 sg13_lv_pmos w=1u l=1u m=1 -RT401 vdd well_401 ntap1 A=4e-12 P=8e-6 -MM68_5 net2 net70 vdd well_401 sg13_lv_pmos w=1u l=1u m=1 -RT402 vdd well_402 ntap1 A=4e-12 P=8e-6 -MM68_6 net2 net70 vdd well_402 sg13_lv_pmos w=1u l=1u m=1 -RT403 vdd well_403 ntap1 A=4e-12 P=8e-6 -MM68_7 net2 net70 vdd well_403 sg13_lv_pmos w=1u l=1u m=1 -RT404 vdd well_404 ntap1 A=4e-12 P=8e-6 -MM68_8 net2 net70 vdd well_404 sg13_lv_pmos w=1u l=1u m=1 -RT405 vdd well_405 ntap1 A=4e-12 P=8e-6 -MM68_9 net2 net70 vdd well_405 sg13_lv_pmos w=1u l=1u m=1 -RT406 vdd well_406 ntap1 A=4e-12 P=8e-6 -MM68_10 net2 net70 vdd well_406 sg13_lv_pmos w=1u l=1u m=1 -RT407 vdd well_407 ntap1 A=4e-12 P=8e-6 -MM68_11 net2 net70 vdd well_407 sg13_lv_pmos w=1u l=1u m=1 -RT408 vdd well_408 ntap1 A=4e-12 P=8e-6 -MM68_12 net2 net70 vdd well_408 sg13_lv_pmos w=1u l=1u m=1 -RT409 vdd well_409 ntap1 A=4e-12 P=8e-6 -MM68_13 net2 net70 vdd well_409 sg13_lv_pmos w=1u l=1u m=1 -RT410 vdd well_410 ntap1 A=4e-12 P=8e-6 -MM68_14 net2 net70 vdd well_410 sg13_lv_pmos w=1u l=1u m=1 -RT411 vdd well_411 ntap1 A=4e-12 P=8e-6 -MM68_15 net2 net70 vdd well_411 sg13_lv_pmos w=1u l=1u m=1 -RT412 vdd well_412 ntap1 A=4e-12 P=8e-6 -MM69_0 net3 net70 vdd well_412 sg13_lv_pmos w=1u l=1u m=1 -RT413 vdd well_413 ntap1 A=4e-12 P=8e-6 -MM69_1 net3 net70 vdd well_413 sg13_lv_pmos w=1u l=1u m=1 -RT414 vdd well_414 ntap1 A=4e-12 P=8e-6 -MM69_2 net3 net70 vdd well_414 sg13_lv_pmos w=1u l=1u m=1 -RT415 vdd well_415 ntap1 A=4e-12 P=8e-6 -MM69_3 net3 net70 vdd well_415 sg13_lv_pmos w=1u l=1u m=1 -RT416 vdd well_416 ntap1 A=4e-12 P=8e-6 -MM69_4 net3 net70 vdd well_416 sg13_lv_pmos w=1u l=1u m=1 -RT417 vdd well_417 ntap1 A=4e-12 P=8e-6 -MM69_5 net3 net70 vdd well_417 sg13_lv_pmos w=1u l=1u m=1 -RT418 vdd well_418 ntap1 A=4e-12 P=8e-6 -MM69_6 net3 net70 vdd well_418 sg13_lv_pmos w=1u l=1u m=1 -RT419 vdd well_419 ntap1 A=4e-12 P=8e-6 -MM69_7 net3 net70 vdd well_419 sg13_lv_pmos w=1u l=1u m=1 -RT420 vdd well_420 ntap1 A=4e-12 P=8e-6 -MM69_8 net3 net70 vdd well_420 sg13_lv_pmos w=1u l=1u m=1 -RT421 vdd well_421 ntap1 A=4e-12 P=8e-6 -MM69_9 net3 net70 vdd well_421 sg13_lv_pmos w=1u l=1u m=1 -RT422 vdd well_422 ntap1 A=4e-12 P=8e-6 -MM69_10 net3 net70 vdd well_422 sg13_lv_pmos w=1u l=1u m=1 -RT423 vdd well_423 ntap1 A=4e-12 P=8e-6 -MM69_11 net3 net70 vdd well_423 sg13_lv_pmos w=1u l=1u m=1 -RT424 vdd well_424 ntap1 A=4e-12 P=8e-6 -MM69_12 net3 net70 vdd well_424 sg13_lv_pmos w=1u l=1u m=1 -RT425 vdd well_425 ntap1 A=4e-12 P=8e-6 -MM69_13 net3 net70 vdd well_425 sg13_lv_pmos w=1u l=1u m=1 -RT426 vdd well_426 ntap1 A=4e-12 P=8e-6 -MM69_14 net3 net70 vdd well_426 sg13_lv_pmos w=1u l=1u m=1 -RT427 vdd well_427 ntap1 A=4e-12 P=8e-6 -MM69_15 net3 net70 vdd well_427 sg13_lv_pmos w=1u l=1u m=1 -RT428 vdd well_428 ntap1 A=4e-12 P=8e-6 -MM7_0 net049 voutn vdd well_428 sg13_lv_pmos w=1u l=1u m=1 -RT429 vdd well_429 ntap1 A=4e-12 P=8e-6 -MM7_1 net049 voutn vdd well_429 sg13_lv_pmos w=1u l=1u m=1 -RT430 vdd well_430 ntap1 A=4e-12 P=8e-6 -MM7_2 net049 voutn vdd well_430 sg13_lv_pmos w=1u l=1u m=1 -RT431 vdd well_431 ntap1 A=4e-12 P=8e-6 -MM7_3 net049 voutn vdd well_431 sg13_lv_pmos w=1u l=1u m=1 -RT432 vss sub ptap1 A=4e-12 P=8e-6 -MM70_0 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT433 vss sub ptap1 A=4e-12 P=8e-6 -MM70_1 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT434 vss sub ptap1 A=4e-12 P=8e-6 -MM70_2 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT435 vss sub ptap1 A=4e-12 P=8e-6 -MM70_3 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT436 vss sub ptap1 A=4e-12 P=8e-6 -MM70_4 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT437 vss sub ptap1 A=4e-12 P=8e-6 -MM70_5 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT438 vss sub ptap1 A=4e-12 P=8e-6 -MM70_6 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT439 vss sub ptap1 A=4e-12 P=8e-6 -MM70_7 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT440 vss sub ptap1 A=4e-12 P=8e-6 -MM70_8 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT441 vss sub ptap1 A=4e-12 P=8e-6 -MM70_9 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT442 vss sub ptap1 A=4e-12 P=8e-6 -MM70_10 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT443 vss sub ptap1 A=4e-12 P=8e-6 -MM70_11 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT444 vss sub ptap1 A=4e-12 P=8e-6 -MM70_12 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT445 vss sub ptap1 A=4e-12 P=8e-6 -MM70_13 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT446 vss sub ptap1 A=4e-12 P=8e-6 -MM70_14 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT447 vss sub ptap1 A=4e-12 P=8e-6 -MM70_15 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -RT448 vss sub ptap1 A=4e-12 P=8e-6 -MM71_0 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT449 vss sub ptap1 A=4e-12 P=8e-6 -MM71_1 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT450 vss sub ptap1 A=4e-12 P=8e-6 -MM71_2 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT451 vss sub ptap1 A=4e-12 P=8e-6 -MM71_3 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT452 vss sub ptap1 A=4e-12 P=8e-6 -MM71_4 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT453 vss sub ptap1 A=4e-12 P=8e-6 -MM71_5 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT454 vss sub ptap1 A=4e-12 P=8e-6 -MM71_6 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT455 vss sub ptap1 A=4e-12 P=8e-6 -MM71_7 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT456 vss sub ptap1 A=4e-12 P=8e-6 -MM71_8 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT457 vss sub ptap1 A=4e-12 P=8e-6 -MM71_9 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT458 vss sub ptap1 A=4e-12 P=8e-6 -MM71_10 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT459 vss sub ptap1 A=4e-12 P=8e-6 -MM71_11 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT460 vss sub ptap1 A=4e-12 P=8e-6 -MM71_12 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT461 vss sub ptap1 A=4e-12 P=8e-6 -MM71_13 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT462 vss sub ptap1 A=4e-12 P=8e-6 -MM71_14 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT463 vss sub ptap1 A=4e-12 P=8e-6 -MM71_15 voutn vb3 net85 sub sg13_lv_nmos w=1u l=1u m=1 -RT464 net31 well_464 ntap1 A=4e-12 P=8e-6 -MM8_0 dm_2 vinn net31 well_464 sg13_lv_pmos w=1u l=1u m=1 -RT465 net31 well_465 ntap1 A=4e-12 P=8e-6 -MM8_1 dm_2 vinn net31 well_465 sg13_lv_pmos w=1u l=1u m=1 -RT466 net31 well_466 ntap1 A=4e-12 P=8e-6 -MM8_2 dm_2 vinn net31 well_466 sg13_lv_pmos w=1u l=1u m=1 -RT467 net31 well_467 ntap1 A=4e-12 P=8e-6 -MM8_3 dm_2 vinn net31 well_467 sg13_lv_pmos w=1u l=1u m=1 -RT468 net31 well_468 ntap1 A=4e-12 P=8e-6 -MM9_0 net063 vinp net31 well_468 sg13_lv_pmos w=1u l=1u m=1 -RT469 net31 well_469 ntap1 A=4e-12 P=8e-6 -MM9_1 net063 vinp net31 well_469 sg13_lv_pmos w=1u l=1u m=1 -RT470 net31 well_470 ntap1 A=4e-12 P=8e-6 -MM9_2 net063 vinp net31 well_470 sg13_lv_pmos w=1u l=1u m=1 -RT471 net31 well_471 ntap1 A=4e-12 P=8e-6 -MM9_3 net063 vinp net31 well_471 sg13_lv_pmos w=1u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM0 net013 net013 vdd vdd sg13_lv_pmos w=1u l=1u m=16 +MM1 vb4 net013 vdd vdd sg13_lv_pmos w=1u l=1u m=16 +MM10 net043 net4 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM11 vout net4 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM12 vb4 vb3 net54 vss sg13_lv_nmos w=1u l=1u m=16 +MM13 dm_1 vb3 net56 vss sg13_lv_nmos w=1u l=1u m=16 +MM14 vb3 vb3 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM15 voutn vb3 dm_2 vss sg13_lv_nmos w=1u l=1u m=16 +MM16 net4 vb3 net063 vss sg13_lv_nmos w=1u l=1u m=16 +MM17 net54 vb4 vss vss sg13_lv_nmos w=1u l=1u m=16 +MM18 net56 vb4 vss vss sg13_lv_nmos w=1u l=1u m=16 +MM19 dm_2 vb4 vss vss sg13_lv_nmos w=1u l=1u m=32 +MM2 dm_1 dm_1 vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM20 net063 vb4 vss vss sg13_lv_nmos w=1u l=1u m=32 +MM21 net043 net043 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM22 net049 net043 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM23 vout net049 vss vss sg13_lv_nmos w=1u l=1u m=4 +MM3 vb3 net013 vdd vdd sg13_lv_pmos w=1u l=1u m=16 +MM4 net31 net013 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +MM5 net5 voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM57 net043 vinn net1 net1 sg13_lv_pmos w=1u l=1u m=4 +MM58 net049 vinp net1 net1 sg13_lv_pmos w=1u l=1u m=4 +MM59 net1 net013 vdd vdd sg13_lv_pmos w=1u l=1u m=8 +MM6 net050 voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM60 voutn dm_1 net5 vdd sg13_lv_pmos w=1u l=1u m=16 +MM61 net4 dm_1 net050 vdd sg13_lv_pmos w=1u l=1u m=16 +MM62 voutn dm_1 net3 vdd sg13_lv_pmos w=1u l=1u m=16 +MM63 net70 dm_1 net2 vdd sg13_lv_pmos w=1u l=1u m=16 +MM64 net85 vb4 vss vss sg13_lv_nmos w=1u l=1u m=32 +MM65 net69 vb4 vss vss sg13_lv_nmos w=1u l=1u m=32 +MM68 net2 net70 vdd vdd sg13_lv_pmos w=1u l=1u m=16 +MM69 net3 net70 vdd vdd sg13_lv_pmos w=1u l=1u m=16 +MM7 net049 voutn vdd vdd sg13_lv_pmos w=1u l=1u m=4 +MM70 net70 vb3 net69 vss sg13_lv_nmos w=1u l=1u m=16 +MM71 voutn vb3 net85 vss sg13_lv_nmos w=1u l=1u m=16 +MM8 dm_2 vinn net31 net31 sg13_lv_pmos w=1u l=1u m=4 +MM9 net063 vinp net31 net31 sg13_lv_pmos w=1u l=1u m=4 C0_0 vout net70 cap_cmim w=31.57u l=31.57u m=1 C2_0 net4 vss cap_cmim w=21.55u l=21.55u m=1 .ends amp_016_song_dacfc diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.spice index 7798b9eca083e086979ec27354c6e8daa8f378c3..1e8ceeb2c8dd00b152dea9cbc162b9eac3cafdec 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.spice @@ -1,951 +1,43 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_016_song_dacfc vss vdd vinn vinp vout net013 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM0_0 net013 net013 vdd well_0 sg13_lv_pmos w=1u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM0_1 net013 net013 vdd well_1 sg13_lv_pmos w=1u l=1u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM0_2 net013 net013 vdd well_2 sg13_lv_pmos w=1u l=1u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM0_3 net013 net013 vdd well_3 sg13_lv_pmos w=1u l=1u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM0_4 net013 net013 vdd well_4 sg13_lv_pmos w=1u l=1u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM0_5 net013 net013 vdd well_5 sg13_lv_pmos w=1u l=1u m=1 -XT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -XM0_6 net013 net013 vdd well_6 sg13_lv_pmos w=1u l=1u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM0_7 net013 net013 vdd well_7 sg13_lv_pmos w=1u l=1u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM0_8 net013 net013 vdd well_8 sg13_lv_pmos w=1u l=1u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM0_9 net013 net013 vdd well_9 sg13_lv_pmos w=1u l=1u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM0_10 net013 net013 vdd well_10 sg13_lv_pmos w=1u l=1u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM0_11 net013 net013 vdd well_11 sg13_lv_pmos w=1u l=1u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM0_12 net013 net013 vdd well_12 sg13_lv_pmos w=1u l=1u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM0_13 net013 net013 vdd well_13 sg13_lv_pmos w=1u l=1u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM0_14 net013 net013 vdd well_14 sg13_lv_pmos w=1u l=1u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM0_15 net013 net013 vdd well_15 sg13_lv_pmos w=1u l=1u m=1 -XT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -XM1_0 vb4 net013 vdd well_16 sg13_lv_pmos w=1u l=1u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM1_1 vb4 net013 vdd well_17 sg13_lv_pmos w=1u l=1u m=1 -XT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -XM1_2 vb4 net013 vdd well_18 sg13_lv_pmos w=1u l=1u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM1_3 vb4 net013 vdd well_19 sg13_lv_pmos w=1u l=1u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM1_4 vb4 net013 vdd well_20 sg13_lv_pmos w=1u l=1u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM1_5 vb4 net013 vdd well_21 sg13_lv_pmos w=1u l=1u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM1_6 vb4 net013 vdd well_22 sg13_lv_pmos w=1u l=1u m=1 -XT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -XM1_7 vb4 net013 vdd well_23 sg13_lv_pmos w=1u l=1u m=1 -XT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -XM1_8 vb4 net013 vdd well_24 sg13_lv_pmos w=1u l=1u m=1 -XT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -XM1_9 vb4 net013 vdd well_25 sg13_lv_pmos w=1u l=1u m=1 -XT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -XM1_10 vb4 net013 vdd well_26 sg13_lv_pmos w=1u l=1u m=1 -XT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -XM1_11 vb4 net013 vdd well_27 sg13_lv_pmos w=1u l=1u m=1 -XT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -XM1_12 vb4 net013 vdd well_28 sg13_lv_pmos w=1u l=1u m=1 -XT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -XM1_13 vb4 net013 vdd well_29 sg13_lv_pmos w=1u l=1u m=1 -XT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -XM1_14 vb4 net013 vdd well_30 sg13_lv_pmos w=1u l=1u m=1 -XT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -XM1_15 vb4 net013 vdd well_31 sg13_lv_pmos w=1u l=1u m=1 -XT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -XM10_0 net043 net4 vdd well_32 sg13_lv_pmos w=1u l=1u m=1 -XT33 vdd well_33 ntap1 A=4e-12 P=8e-6 -XM10_1 net043 net4 vdd well_33 sg13_lv_pmos w=1u l=1u m=1 -XT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -XM10_2 net043 net4 vdd well_34 sg13_lv_pmos w=1u l=1u m=1 -XT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -XM10_3 net043 net4 vdd well_35 sg13_lv_pmos w=1u l=1u m=1 -XT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -XM11_0 vout net4 vdd well_36 sg13_lv_pmos w=1u l=1u m=1 -XT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -XM11_1 vout net4 vdd well_37 sg13_lv_pmos w=1u l=1u m=1 -XT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -XM11_2 vout net4 vdd well_38 sg13_lv_pmos w=1u l=1u m=1 -XT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -XM11_3 vout net4 vdd well_39 sg13_lv_pmos w=1u l=1u m=1 -XT40 vss sub ptap1 A=4e-12 P=8e-6 -XM12_0 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT41 vss sub ptap1 A=4e-12 P=8e-6 -XM12_1 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT42 vss sub ptap1 A=4e-12 P=8e-6 -XM12_2 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT43 vss sub ptap1 A=4e-12 P=8e-6 -XM12_3 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT44 vss sub ptap1 A=4e-12 P=8e-6 -XM12_4 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT45 vss sub ptap1 A=4e-12 P=8e-6 -XM12_5 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT46 vss sub ptap1 A=4e-12 P=8e-6 -XM12_6 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT47 vss sub ptap1 A=4e-12 P=8e-6 -XM12_7 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT48 vss sub ptap1 A=4e-12 P=8e-6 -XM12_8 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT49 vss sub ptap1 A=4e-12 P=8e-6 -XM12_9 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT50 vss sub ptap1 A=4e-12 P=8e-6 -XM12_10 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT51 vss sub ptap1 A=4e-12 P=8e-6 -XM12_11 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT52 vss sub ptap1 A=4e-12 P=8e-6 -XM12_12 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT53 vss sub ptap1 A=4e-12 P=8e-6 -XM12_13 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT54 vss sub ptap1 A=4e-12 P=8e-6 -XM12_14 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT55 vss sub ptap1 A=4e-12 P=8e-6 -XM12_15 vb4 vb3 net54 sub sg13_lv_nmos w=1u l=1u m=1 -XT56 vss sub ptap1 A=4e-12 P=8e-6 -XM13_0 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT57 vss sub ptap1 A=4e-12 P=8e-6 -XM13_1 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT58 vss sub ptap1 A=4e-12 P=8e-6 -XM13_2 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT59 vss sub ptap1 A=4e-12 P=8e-6 -XM13_3 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT60 vss sub ptap1 A=4e-12 P=8e-6 -XM13_4 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT61 vss sub ptap1 A=4e-12 P=8e-6 -XM13_5 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT62 vss sub ptap1 A=4e-12 P=8e-6 -XM13_6 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT63 vss sub ptap1 A=4e-12 P=8e-6 -XM13_7 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT64 vss sub ptap1 A=4e-12 P=8e-6 -XM13_8 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT65 vss sub ptap1 A=4e-12 P=8e-6 -XM13_9 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT66 vss sub ptap1 A=4e-12 P=8e-6 -XM13_10 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT67 vss sub ptap1 A=4e-12 P=8e-6 -XM13_11 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT68 vss sub ptap1 A=4e-12 P=8e-6 -XM13_12 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT69 vss sub ptap1 A=4e-12 P=8e-6 -XM13_13 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT70 vss sub ptap1 A=4e-12 P=8e-6 -XM13_14 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT71 vss sub ptap1 A=4e-12 P=8e-6 -XM13_15 dm_1 vb3 net56 sub sg13_lv_nmos w=1u l=1u m=1 -XT72 vss sub ptap1 A=4e-12 P=8e-6 -XM14_0 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT73 vss sub ptap1 A=4e-12 P=8e-6 -XM14_1 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT74 vss sub ptap1 A=4e-12 P=8e-6 -XM14_2 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT75 vss sub ptap1 A=4e-12 P=8e-6 -XM14_3 vb3 vb3 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT76 vss sub ptap1 A=4e-12 P=8e-6 -XM15_0 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT77 vss sub ptap1 A=4e-12 P=8e-6 -XM15_1 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT78 vss sub ptap1 A=4e-12 P=8e-6 -XM15_2 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT79 vss sub ptap1 A=4e-12 P=8e-6 -XM15_3 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT80 vss sub ptap1 A=4e-12 P=8e-6 -XM15_4 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT81 vss sub ptap1 A=4e-12 P=8e-6 -XM15_5 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT82 vss sub ptap1 A=4e-12 P=8e-6 -XM15_6 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT83 vss sub ptap1 A=4e-12 P=8e-6 -XM15_7 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT84 vss sub ptap1 A=4e-12 P=8e-6 -XM15_8 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT85 vss sub ptap1 A=4e-12 P=8e-6 -XM15_9 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT86 vss sub ptap1 A=4e-12 P=8e-6 -XM15_10 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT87 vss sub ptap1 A=4e-12 P=8e-6 -XM15_11 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT88 vss sub ptap1 A=4e-12 P=8e-6 -XM15_12 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT89 vss sub ptap1 A=4e-12 P=8e-6 -XM15_13 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT90 vss sub ptap1 A=4e-12 P=8e-6 -XM15_14 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT91 vss sub ptap1 A=4e-12 P=8e-6 -XM15_15 voutn vb3 dm_2 sub sg13_lv_nmos w=1u l=1u m=1 -XT92 vss sub ptap1 A=4e-12 P=8e-6 -XM16_0 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT93 vss sub ptap1 A=4e-12 P=8e-6 -XM16_1 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT94 vss sub ptap1 A=4e-12 P=8e-6 -XM16_2 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT95 vss sub ptap1 A=4e-12 P=8e-6 -XM16_3 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT96 vss sub ptap1 A=4e-12 P=8e-6 -XM16_4 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT97 vss sub ptap1 A=4e-12 P=8e-6 -XM16_5 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT98 vss sub ptap1 A=4e-12 P=8e-6 -XM16_6 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT99 vss sub ptap1 A=4e-12 P=8e-6 -XM16_7 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT100 vss sub ptap1 A=4e-12 P=8e-6 -XM16_8 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT101 vss sub ptap1 A=4e-12 P=8e-6 -XM16_9 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT102 vss sub ptap1 A=4e-12 P=8e-6 -XM16_10 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT103 vss sub ptap1 A=4e-12 P=8e-6 -XM16_11 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT104 vss sub ptap1 A=4e-12 P=8e-6 -XM16_12 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT105 vss sub ptap1 A=4e-12 P=8e-6 -XM16_13 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT106 vss sub ptap1 A=4e-12 P=8e-6 -XM16_14 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT107 vss sub ptap1 A=4e-12 P=8e-6 -XM16_15 net4 vb3 net063 sub sg13_lv_nmos w=1u l=1u m=1 -XT108 vss sub ptap1 A=4e-12 P=8e-6 -XM17_0 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT109 vss sub ptap1 A=4e-12 P=8e-6 -XM17_1 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT110 vss sub ptap1 A=4e-12 P=8e-6 -XM17_2 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT111 vss sub ptap1 A=4e-12 P=8e-6 -XM17_3 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT112 vss sub ptap1 A=4e-12 P=8e-6 -XM17_4 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT113 vss sub ptap1 A=4e-12 P=8e-6 -XM17_5 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT114 vss sub ptap1 A=4e-12 P=8e-6 -XM17_6 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT115 vss sub ptap1 A=4e-12 P=8e-6 -XM17_7 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT116 vss sub ptap1 A=4e-12 P=8e-6 -XM17_8 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT117 vss sub ptap1 A=4e-12 P=8e-6 -XM17_9 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT118 vss sub ptap1 A=4e-12 P=8e-6 -XM17_10 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT119 vss sub ptap1 A=4e-12 P=8e-6 -XM17_11 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT120 vss sub ptap1 A=4e-12 P=8e-6 -XM17_12 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT121 vss sub ptap1 A=4e-12 P=8e-6 -XM17_13 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT122 vss sub ptap1 A=4e-12 P=8e-6 -XM17_14 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT123 vss sub ptap1 A=4e-12 P=8e-6 -XM17_15 net54 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT124 vss sub ptap1 A=4e-12 P=8e-6 -XM18_0 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT125 vss sub ptap1 A=4e-12 P=8e-6 -XM18_1 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT126 vss sub ptap1 A=4e-12 P=8e-6 -XM18_2 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT127 vss sub ptap1 A=4e-12 P=8e-6 -XM18_3 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT128 vss sub ptap1 A=4e-12 P=8e-6 -XM18_4 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT129 vss sub ptap1 A=4e-12 P=8e-6 -XM18_5 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT130 vss sub ptap1 A=4e-12 P=8e-6 -XM18_6 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT131 vss sub ptap1 A=4e-12 P=8e-6 -XM18_7 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT132 vss sub ptap1 A=4e-12 P=8e-6 -XM18_8 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT133 vss sub ptap1 A=4e-12 P=8e-6 -XM18_9 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT134 vss sub ptap1 A=4e-12 P=8e-6 -XM18_10 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT135 vss sub ptap1 A=4e-12 P=8e-6 -XM18_11 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT136 vss sub ptap1 A=4e-12 P=8e-6 -XM18_12 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT137 vss sub ptap1 A=4e-12 P=8e-6 -XM18_13 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT138 vss sub ptap1 A=4e-12 P=8e-6 -XM18_14 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT139 vss sub ptap1 A=4e-12 P=8e-6 -XM18_15 net56 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT140 vss sub ptap1 A=4e-12 P=8e-6 -XM19_0 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT141 vss sub ptap1 A=4e-12 P=8e-6 -XM19_1 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT142 vss sub ptap1 A=4e-12 P=8e-6 -XM19_2 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT143 vss sub ptap1 A=4e-12 P=8e-6 -XM19_3 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT144 vss sub ptap1 A=4e-12 P=8e-6 -XM19_4 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT145 vss sub ptap1 A=4e-12 P=8e-6 -XM19_5 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT146 vss sub ptap1 A=4e-12 P=8e-6 -XM19_6 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT147 vss sub ptap1 A=4e-12 P=8e-6 -XM19_7 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT148 vss sub ptap1 A=4e-12 P=8e-6 -XM19_8 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT149 vss sub ptap1 A=4e-12 P=8e-6 -XM19_9 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT150 vss sub ptap1 A=4e-12 P=8e-6 -XM19_10 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT151 vss sub ptap1 A=4e-12 P=8e-6 -XM19_11 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT152 vss sub ptap1 A=4e-12 P=8e-6 -XM19_12 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT153 vss sub ptap1 A=4e-12 P=8e-6 -XM19_13 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT154 vss sub ptap1 A=4e-12 P=8e-6 -XM19_14 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT155 vss sub ptap1 A=4e-12 P=8e-6 -XM19_15 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT156 vss sub ptap1 A=4e-12 P=8e-6 -XM19_16 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT157 vss sub ptap1 A=4e-12 P=8e-6 -XM19_17 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT158 vss sub ptap1 A=4e-12 P=8e-6 -XM19_18 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT159 vss sub ptap1 A=4e-12 P=8e-6 -XM19_19 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT160 vss sub ptap1 A=4e-12 P=8e-6 -XM19_20 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT161 vss sub ptap1 A=4e-12 P=8e-6 -XM19_21 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT162 vss sub ptap1 A=4e-12 P=8e-6 -XM19_22 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT163 vss sub ptap1 A=4e-12 P=8e-6 -XM19_23 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT164 vss sub ptap1 A=4e-12 P=8e-6 -XM19_24 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT165 vss sub ptap1 A=4e-12 P=8e-6 -XM19_25 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT166 vss sub ptap1 A=4e-12 P=8e-6 -XM19_26 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT167 vss sub ptap1 A=4e-12 P=8e-6 -XM19_27 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT168 vss sub ptap1 A=4e-12 P=8e-6 -XM19_28 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT169 vss sub ptap1 A=4e-12 P=8e-6 -XM19_29 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT170 vss sub ptap1 A=4e-12 P=8e-6 -XM19_30 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT171 vss sub ptap1 A=4e-12 P=8e-6 -XM19_31 dm_2 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT172 vdd well_172 ntap1 A=4e-12 P=8e-6 -XM2_0 dm_1 dm_1 vdd well_172 sg13_lv_pmos w=1u l=1u m=1 -XT173 vdd well_173 ntap1 A=4e-12 P=8e-6 -XM2_1 dm_1 dm_1 vdd well_173 sg13_lv_pmos w=1u l=1u m=1 -XT174 vdd well_174 ntap1 A=4e-12 P=8e-6 -XM2_2 dm_1 dm_1 vdd well_174 sg13_lv_pmos w=1u l=1u m=1 -XT175 vdd well_175 ntap1 A=4e-12 P=8e-6 -XM2_3 dm_1 dm_1 vdd well_175 sg13_lv_pmos w=1u l=1u m=1 -XT176 vss sub ptap1 A=4e-12 P=8e-6 -XM20_0 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT177 vss sub ptap1 A=4e-12 P=8e-6 -XM20_1 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT178 vss sub ptap1 A=4e-12 P=8e-6 -XM20_2 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT179 vss sub ptap1 A=4e-12 P=8e-6 -XM20_3 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT180 vss sub ptap1 A=4e-12 P=8e-6 -XM20_4 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT181 vss sub ptap1 A=4e-12 P=8e-6 -XM20_5 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT182 vss sub ptap1 A=4e-12 P=8e-6 -XM20_6 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT183 vss sub ptap1 A=4e-12 P=8e-6 -XM20_7 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT184 vss sub ptap1 A=4e-12 P=8e-6 -XM20_8 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT185 vss sub ptap1 A=4e-12 P=8e-6 -XM20_9 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT186 vss sub ptap1 A=4e-12 P=8e-6 -XM20_10 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT187 vss sub ptap1 A=4e-12 P=8e-6 -XM20_11 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT188 vss sub ptap1 A=4e-12 P=8e-6 -XM20_12 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT189 vss sub ptap1 A=4e-12 P=8e-6 -XM20_13 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT190 vss sub ptap1 A=4e-12 P=8e-6 -XM20_14 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT191 vss sub ptap1 A=4e-12 P=8e-6 -XM20_15 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT192 vss sub ptap1 A=4e-12 P=8e-6 -XM20_16 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT193 vss sub ptap1 A=4e-12 P=8e-6 -XM20_17 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT194 vss sub ptap1 A=4e-12 P=8e-6 -XM20_18 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT195 vss sub ptap1 A=4e-12 P=8e-6 -XM20_19 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT196 vss sub ptap1 A=4e-12 P=8e-6 -XM20_20 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT197 vss sub ptap1 A=4e-12 P=8e-6 -XM20_21 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT198 vss sub ptap1 A=4e-12 P=8e-6 -XM20_22 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT199 vss sub ptap1 A=4e-12 P=8e-6 -XM20_23 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT200 vss sub ptap1 A=4e-12 P=8e-6 -XM20_24 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT201 vss sub ptap1 A=4e-12 P=8e-6 -XM20_25 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT202 vss sub ptap1 A=4e-12 P=8e-6 -XM20_26 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT203 vss sub ptap1 A=4e-12 P=8e-6 -XM20_27 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT204 vss sub ptap1 A=4e-12 P=8e-6 -XM20_28 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT205 vss sub ptap1 A=4e-12 P=8e-6 -XM20_29 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT206 vss sub ptap1 A=4e-12 P=8e-6 -XM20_30 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT207 vss sub ptap1 A=4e-12 P=8e-6 -XM20_31 net063 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT208 vss sub ptap1 A=4e-12 P=8e-6 -XM21_0 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT209 vss sub ptap1 A=4e-12 P=8e-6 -XM21_1 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT210 vss sub ptap1 A=4e-12 P=8e-6 -XM21_2 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT211 vss sub ptap1 A=4e-12 P=8e-6 -XM21_3 net043 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT212 vss sub ptap1 A=4e-12 P=8e-6 -XM22_0 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT213 vss sub ptap1 A=4e-12 P=8e-6 -XM22_1 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT214 vss sub ptap1 A=4e-12 P=8e-6 -XM22_2 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT215 vss sub ptap1 A=4e-12 P=8e-6 -XM22_3 net049 net043 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT216 vss sub ptap1 A=4e-12 P=8e-6 -XM23_0 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT217 vss sub ptap1 A=4e-12 P=8e-6 -XM23_1 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT218 vss sub ptap1 A=4e-12 P=8e-6 -XM23_2 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT219 vss sub ptap1 A=4e-12 P=8e-6 -XM23_3 vout net049 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT220 vdd well_220 ntap1 A=4e-12 P=8e-6 -XM3_0 vb3 net013 vdd well_220 sg13_lv_pmos w=1u l=1u m=1 -XT221 vdd well_221 ntap1 A=4e-12 P=8e-6 -XM3_1 vb3 net013 vdd well_221 sg13_lv_pmos w=1u l=1u m=1 -XT222 vdd well_222 ntap1 A=4e-12 P=8e-6 -XM3_2 vb3 net013 vdd well_222 sg13_lv_pmos w=1u l=1u m=1 -XT223 vdd well_223 ntap1 A=4e-12 P=8e-6 -XM3_3 vb3 net013 vdd well_223 sg13_lv_pmos w=1u l=1u m=1 -XT224 vdd well_224 ntap1 A=4e-12 P=8e-6 -XM3_4 vb3 net013 vdd well_224 sg13_lv_pmos w=1u l=1u m=1 -XT225 vdd well_225 ntap1 A=4e-12 P=8e-6 -XM3_5 vb3 net013 vdd well_225 sg13_lv_pmos w=1u l=1u m=1 -XT226 vdd well_226 ntap1 A=4e-12 P=8e-6 -XM3_6 vb3 net013 vdd well_226 sg13_lv_pmos w=1u l=1u m=1 -XT227 vdd well_227 ntap1 A=4e-12 P=8e-6 -XM3_7 vb3 net013 vdd well_227 sg13_lv_pmos w=1u l=1u m=1 -XT228 vdd well_228 ntap1 A=4e-12 P=8e-6 -XM3_8 vb3 net013 vdd well_228 sg13_lv_pmos w=1u l=1u m=1 -XT229 vdd well_229 ntap1 A=4e-12 P=8e-6 -XM3_9 vb3 net013 vdd well_229 sg13_lv_pmos w=1u l=1u m=1 -XT230 vdd well_230 ntap1 A=4e-12 P=8e-6 -XM3_10 vb3 net013 vdd well_230 sg13_lv_pmos w=1u l=1u m=1 -XT231 vdd well_231 ntap1 A=4e-12 P=8e-6 -XM3_11 vb3 net013 vdd well_231 sg13_lv_pmos w=1u l=1u m=1 -XT232 vdd well_232 ntap1 A=4e-12 P=8e-6 -XM3_12 vb3 net013 vdd well_232 sg13_lv_pmos w=1u l=1u m=1 -XT233 vdd well_233 ntap1 A=4e-12 P=8e-6 -XM3_13 vb3 net013 vdd well_233 sg13_lv_pmos w=1u l=1u m=1 -XT234 vdd well_234 ntap1 A=4e-12 P=8e-6 -XM3_14 vb3 net013 vdd well_234 sg13_lv_pmos w=1u l=1u m=1 -XT235 vdd well_235 ntap1 A=4e-12 P=8e-6 -XM3_15 vb3 net013 vdd well_235 sg13_lv_pmos w=1u l=1u m=1 -XT236 vdd well_236 ntap1 A=4e-12 P=8e-6 -XM4_0 net31 net013 vdd well_236 sg13_lv_pmos w=1u l=1u m=1 -XT237 vdd well_237 ntap1 A=4e-12 P=8e-6 -XM4_1 net31 net013 vdd well_237 sg13_lv_pmos w=1u l=1u m=1 -XT238 vdd well_238 ntap1 A=4e-12 P=8e-6 -XM4_2 net31 net013 vdd well_238 sg13_lv_pmos w=1u l=1u m=1 -XT239 vdd well_239 ntap1 A=4e-12 P=8e-6 -XM4_3 net31 net013 vdd well_239 sg13_lv_pmos w=1u l=1u m=1 -XT240 vdd well_240 ntap1 A=4e-12 P=8e-6 -XM4_4 net31 net013 vdd well_240 sg13_lv_pmos w=1u l=1u m=1 -XT241 vdd well_241 ntap1 A=4e-12 P=8e-6 -XM4_5 net31 net013 vdd well_241 sg13_lv_pmos w=1u l=1u m=1 -XT242 vdd well_242 ntap1 A=4e-12 P=8e-6 -XM4_6 net31 net013 vdd well_242 sg13_lv_pmos w=1u l=1u m=1 -XT243 vdd well_243 ntap1 A=4e-12 P=8e-6 -XM4_7 net31 net013 vdd well_243 sg13_lv_pmos w=1u l=1u m=1 -XT244 vdd well_244 ntap1 A=4e-12 P=8e-6 -XM5_0 net5 voutn vdd well_244 sg13_lv_pmos w=1u l=1u m=1 -XT245 vdd well_245 ntap1 A=4e-12 P=8e-6 -XM5_1 net5 voutn vdd well_245 sg13_lv_pmos w=1u l=1u m=1 -XT246 vdd well_246 ntap1 A=4e-12 P=8e-6 -XM5_2 net5 voutn vdd well_246 sg13_lv_pmos w=1u l=1u m=1 -XT247 vdd well_247 ntap1 A=4e-12 P=8e-6 -XM5_3 net5 voutn vdd well_247 sg13_lv_pmos w=1u l=1u m=1 -XT248 net1 well_248 ntap1 A=4e-12 P=8e-6 -XM57_0 net043 vinn net1 well_248 sg13_lv_pmos w=1u l=1u m=1 -XT249 net1 well_249 ntap1 A=4e-12 P=8e-6 -XM57_1 net043 vinn net1 well_249 sg13_lv_pmos w=1u l=1u m=1 -XT250 net1 well_250 ntap1 A=4e-12 P=8e-6 -XM57_2 net043 vinn net1 well_250 sg13_lv_pmos w=1u l=1u m=1 -XT251 net1 well_251 ntap1 A=4e-12 P=8e-6 -XM57_3 net043 vinn net1 well_251 sg13_lv_pmos w=1u l=1u m=1 -XT252 net1 well_252 ntap1 A=4e-12 P=8e-6 -XM58_0 net049 vinp net1 well_252 sg13_lv_pmos w=1u l=1u m=1 -XT253 net1 well_253 ntap1 A=4e-12 P=8e-6 -XM58_1 net049 vinp net1 well_253 sg13_lv_pmos w=1u l=1u m=1 -XT254 net1 well_254 ntap1 A=4e-12 P=8e-6 -XM58_2 net049 vinp net1 well_254 sg13_lv_pmos w=1u l=1u m=1 -XT255 net1 well_255 ntap1 A=4e-12 P=8e-6 -XM58_3 net049 vinp net1 well_255 sg13_lv_pmos w=1u l=1u m=1 -XT256 vdd well_256 ntap1 A=4e-12 P=8e-6 -XM59_0 net1 net013 vdd well_256 sg13_lv_pmos w=1u l=1u m=1 -XT257 vdd well_257 ntap1 A=4e-12 P=8e-6 -XM59_1 net1 net013 vdd well_257 sg13_lv_pmos w=1u l=1u m=1 -XT258 vdd well_258 ntap1 A=4e-12 P=8e-6 -XM59_2 net1 net013 vdd well_258 sg13_lv_pmos w=1u l=1u m=1 -XT259 vdd well_259 ntap1 A=4e-12 P=8e-6 -XM59_3 net1 net013 vdd well_259 sg13_lv_pmos w=1u l=1u m=1 -XT260 vdd well_260 ntap1 A=4e-12 P=8e-6 -XM59_4 net1 net013 vdd well_260 sg13_lv_pmos w=1u l=1u m=1 -XT261 vdd well_261 ntap1 A=4e-12 P=8e-6 -XM59_5 net1 net013 vdd well_261 sg13_lv_pmos w=1u l=1u m=1 -XT262 vdd well_262 ntap1 A=4e-12 P=8e-6 -XM59_6 net1 net013 vdd well_262 sg13_lv_pmos w=1u l=1u m=1 -XT263 vdd well_263 ntap1 A=4e-12 P=8e-6 -XM59_7 net1 net013 vdd well_263 sg13_lv_pmos w=1u l=1u m=1 -XT264 vdd well_264 ntap1 A=4e-12 P=8e-6 -XM6_0 net050 voutn vdd well_264 sg13_lv_pmos w=1u l=1u m=1 -XT265 vdd well_265 ntap1 A=4e-12 P=8e-6 -XM6_1 net050 voutn vdd well_265 sg13_lv_pmos w=1u l=1u m=1 -XT266 vdd well_266 ntap1 A=4e-12 P=8e-6 -XM6_2 net050 voutn vdd well_266 sg13_lv_pmos w=1u l=1u m=1 -XT267 vdd well_267 ntap1 A=4e-12 P=8e-6 -XM6_3 net050 voutn vdd well_267 sg13_lv_pmos w=1u l=1u m=1 -XT268 vdd well_268 ntap1 A=4e-12 P=8e-6 -XM60_0 voutn dm_1 net5 well_268 sg13_lv_pmos w=1u l=1u m=1 -XT269 vdd well_269 ntap1 A=4e-12 P=8e-6 -XM60_1 voutn dm_1 net5 well_269 sg13_lv_pmos w=1u l=1u m=1 -XT270 vdd well_270 ntap1 A=4e-12 P=8e-6 -XM60_2 voutn dm_1 net5 well_270 sg13_lv_pmos w=1u l=1u m=1 -XT271 vdd well_271 ntap1 A=4e-12 P=8e-6 -XM60_3 voutn dm_1 net5 well_271 sg13_lv_pmos w=1u l=1u m=1 -XT272 vdd well_272 ntap1 A=4e-12 P=8e-6 -XM60_4 voutn dm_1 net5 well_272 sg13_lv_pmos w=1u l=1u m=1 -XT273 vdd well_273 ntap1 A=4e-12 P=8e-6 -XM60_5 voutn dm_1 net5 well_273 sg13_lv_pmos w=1u l=1u m=1 -XT274 vdd well_274 ntap1 A=4e-12 P=8e-6 -XM60_6 voutn dm_1 net5 well_274 sg13_lv_pmos w=1u l=1u m=1 -XT275 vdd well_275 ntap1 A=4e-12 P=8e-6 -XM60_7 voutn dm_1 net5 well_275 sg13_lv_pmos w=1u l=1u m=1 -XT276 vdd well_276 ntap1 A=4e-12 P=8e-6 -XM60_8 voutn dm_1 net5 well_276 sg13_lv_pmos w=1u l=1u m=1 -XT277 vdd well_277 ntap1 A=4e-12 P=8e-6 -XM60_9 voutn dm_1 net5 well_277 sg13_lv_pmos w=1u l=1u m=1 -XT278 vdd well_278 ntap1 A=4e-12 P=8e-6 -XM60_10 voutn dm_1 net5 well_278 sg13_lv_pmos w=1u l=1u m=1 -XT279 vdd well_279 ntap1 A=4e-12 P=8e-6 -XM60_11 voutn dm_1 net5 well_279 sg13_lv_pmos w=1u l=1u m=1 -XT280 vdd well_280 ntap1 A=4e-12 P=8e-6 -XM60_12 voutn dm_1 net5 well_280 sg13_lv_pmos w=1u l=1u m=1 -XT281 vdd well_281 ntap1 A=4e-12 P=8e-6 -XM60_13 voutn dm_1 net5 well_281 sg13_lv_pmos w=1u l=1u m=1 -XT282 vdd well_282 ntap1 A=4e-12 P=8e-6 -XM60_14 voutn dm_1 net5 well_282 sg13_lv_pmos w=1u l=1u m=1 -XT283 vdd well_283 ntap1 A=4e-12 P=8e-6 -XM60_15 voutn dm_1 net5 well_283 sg13_lv_pmos w=1u l=1u m=1 -XT284 vdd well_284 ntap1 A=4e-12 P=8e-6 -XM61_0 net4 dm_1 net050 well_284 sg13_lv_pmos w=1u l=1u m=1 -XT285 vdd well_285 ntap1 A=4e-12 P=8e-6 -XM61_1 net4 dm_1 net050 well_285 sg13_lv_pmos w=1u l=1u m=1 -XT286 vdd well_286 ntap1 A=4e-12 P=8e-6 -XM61_2 net4 dm_1 net050 well_286 sg13_lv_pmos w=1u l=1u m=1 -XT287 vdd well_287 ntap1 A=4e-12 P=8e-6 -XM61_3 net4 dm_1 net050 well_287 sg13_lv_pmos w=1u l=1u m=1 -XT288 vdd well_288 ntap1 A=4e-12 P=8e-6 -XM61_4 net4 dm_1 net050 well_288 sg13_lv_pmos w=1u l=1u m=1 -XT289 vdd well_289 ntap1 A=4e-12 P=8e-6 -XM61_5 net4 dm_1 net050 well_289 sg13_lv_pmos w=1u l=1u m=1 -XT290 vdd well_290 ntap1 A=4e-12 P=8e-6 -XM61_6 net4 dm_1 net050 well_290 sg13_lv_pmos w=1u l=1u m=1 -XT291 vdd well_291 ntap1 A=4e-12 P=8e-6 -XM61_7 net4 dm_1 net050 well_291 sg13_lv_pmos w=1u l=1u m=1 -XT292 vdd well_292 ntap1 A=4e-12 P=8e-6 -XM61_8 net4 dm_1 net050 well_292 sg13_lv_pmos w=1u l=1u m=1 -XT293 vdd well_293 ntap1 A=4e-12 P=8e-6 -XM61_9 net4 dm_1 net050 well_293 sg13_lv_pmos w=1u l=1u m=1 -XT294 vdd well_294 ntap1 A=4e-12 P=8e-6 -XM61_10 net4 dm_1 net050 well_294 sg13_lv_pmos w=1u l=1u m=1 -XT295 vdd well_295 ntap1 A=4e-12 P=8e-6 -XM61_11 net4 dm_1 net050 well_295 sg13_lv_pmos w=1u l=1u m=1 -XT296 vdd well_296 ntap1 A=4e-12 P=8e-6 -XM61_12 net4 dm_1 net050 well_296 sg13_lv_pmos w=1u l=1u m=1 -XT297 vdd well_297 ntap1 A=4e-12 P=8e-6 -XM61_13 net4 dm_1 net050 well_297 sg13_lv_pmos w=1u l=1u m=1 -XT298 vdd well_298 ntap1 A=4e-12 P=8e-6 -XM61_14 net4 dm_1 net050 well_298 sg13_lv_pmos w=1u l=1u m=1 -XT299 vdd well_299 ntap1 A=4e-12 P=8e-6 -XM61_15 net4 dm_1 net050 well_299 sg13_lv_pmos w=1u l=1u m=1 -XT300 vdd well_300 ntap1 A=4e-12 P=8e-6 -XM62_0 voutn dm_1 net3 well_300 sg13_lv_pmos w=1u l=1u m=1 -XT301 vdd well_301 ntap1 A=4e-12 P=8e-6 -XM62_1 voutn dm_1 net3 well_301 sg13_lv_pmos w=1u l=1u m=1 -XT302 vdd well_302 ntap1 A=4e-12 P=8e-6 -XM62_2 voutn dm_1 net3 well_302 sg13_lv_pmos w=1u l=1u m=1 -XT303 vdd well_303 ntap1 A=4e-12 P=8e-6 -XM62_3 voutn dm_1 net3 well_303 sg13_lv_pmos w=1u l=1u m=1 -XT304 vdd well_304 ntap1 A=4e-12 P=8e-6 -XM62_4 voutn dm_1 net3 well_304 sg13_lv_pmos w=1u l=1u m=1 -XT305 vdd well_305 ntap1 A=4e-12 P=8e-6 -XM62_5 voutn dm_1 net3 well_305 sg13_lv_pmos w=1u l=1u m=1 -XT306 vdd well_306 ntap1 A=4e-12 P=8e-6 -XM62_6 voutn dm_1 net3 well_306 sg13_lv_pmos w=1u l=1u m=1 -XT307 vdd well_307 ntap1 A=4e-12 P=8e-6 -XM62_7 voutn dm_1 net3 well_307 sg13_lv_pmos w=1u l=1u m=1 -XT308 vdd well_308 ntap1 A=4e-12 P=8e-6 -XM62_8 voutn dm_1 net3 well_308 sg13_lv_pmos w=1u l=1u m=1 -XT309 vdd well_309 ntap1 A=4e-12 P=8e-6 -XM62_9 voutn dm_1 net3 well_309 sg13_lv_pmos w=1u l=1u m=1 -XT310 vdd well_310 ntap1 A=4e-12 P=8e-6 -XM62_10 voutn dm_1 net3 well_310 sg13_lv_pmos w=1u l=1u m=1 -XT311 vdd well_311 ntap1 A=4e-12 P=8e-6 -XM62_11 voutn dm_1 net3 well_311 sg13_lv_pmos w=1u l=1u m=1 -XT312 vdd well_312 ntap1 A=4e-12 P=8e-6 -XM62_12 voutn dm_1 net3 well_312 sg13_lv_pmos w=1u l=1u m=1 -XT313 vdd well_313 ntap1 A=4e-12 P=8e-6 -XM62_13 voutn dm_1 net3 well_313 sg13_lv_pmos w=1u l=1u m=1 -XT314 vdd well_314 ntap1 A=4e-12 P=8e-6 -XM62_14 voutn dm_1 net3 well_314 sg13_lv_pmos w=1u l=1u m=1 -XT315 vdd well_315 ntap1 A=4e-12 P=8e-6 -XM62_15 voutn dm_1 net3 well_315 sg13_lv_pmos w=1u l=1u m=1 -XT316 vdd well_316 ntap1 A=4e-12 P=8e-6 -XM63_0 net70 dm_1 net2 well_316 sg13_lv_pmos w=1u l=1u m=1 -XT317 vdd well_317 ntap1 A=4e-12 P=8e-6 -XM63_1 net70 dm_1 net2 well_317 sg13_lv_pmos w=1u l=1u m=1 -XT318 vdd well_318 ntap1 A=4e-12 P=8e-6 -XM63_2 net70 dm_1 net2 well_318 sg13_lv_pmos w=1u l=1u m=1 -XT319 vdd well_319 ntap1 A=4e-12 P=8e-6 -XM63_3 net70 dm_1 net2 well_319 sg13_lv_pmos w=1u l=1u m=1 -XT320 vdd well_320 ntap1 A=4e-12 P=8e-6 -XM63_4 net70 dm_1 net2 well_320 sg13_lv_pmos w=1u l=1u m=1 -XT321 vdd well_321 ntap1 A=4e-12 P=8e-6 -XM63_5 net70 dm_1 net2 well_321 sg13_lv_pmos w=1u l=1u m=1 -XT322 vdd well_322 ntap1 A=4e-12 P=8e-6 -XM63_6 net70 dm_1 net2 well_322 sg13_lv_pmos w=1u l=1u m=1 -XT323 vdd well_323 ntap1 A=4e-12 P=8e-6 -XM63_7 net70 dm_1 net2 well_323 sg13_lv_pmos w=1u l=1u m=1 -XT324 vdd well_324 ntap1 A=4e-12 P=8e-6 -XM63_8 net70 dm_1 net2 well_324 sg13_lv_pmos w=1u l=1u m=1 -XT325 vdd well_325 ntap1 A=4e-12 P=8e-6 -XM63_9 net70 dm_1 net2 well_325 sg13_lv_pmos w=1u l=1u m=1 -XT326 vdd well_326 ntap1 A=4e-12 P=8e-6 -XM63_10 net70 dm_1 net2 well_326 sg13_lv_pmos w=1u l=1u m=1 -XT327 vdd well_327 ntap1 A=4e-12 P=8e-6 -XM63_11 net70 dm_1 net2 well_327 sg13_lv_pmos w=1u l=1u m=1 -XT328 vdd well_328 ntap1 A=4e-12 P=8e-6 -XM63_12 net70 dm_1 net2 well_328 sg13_lv_pmos w=1u l=1u m=1 -XT329 vdd well_329 ntap1 A=4e-12 P=8e-6 -XM63_13 net70 dm_1 net2 well_329 sg13_lv_pmos w=1u l=1u m=1 -XT330 vdd well_330 ntap1 A=4e-12 P=8e-6 -XM63_14 net70 dm_1 net2 well_330 sg13_lv_pmos w=1u l=1u m=1 -XT331 vdd well_331 ntap1 A=4e-12 P=8e-6 -XM63_15 net70 dm_1 net2 well_331 sg13_lv_pmos w=1u l=1u m=1 -XT332 vss sub ptap1 A=4e-12 P=8e-6 -XM64_0 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT333 vss sub ptap1 A=4e-12 P=8e-6 -XM64_1 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT334 vss sub ptap1 A=4e-12 P=8e-6 -XM64_2 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT335 vss sub ptap1 A=4e-12 P=8e-6 -XM64_3 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT336 vss sub ptap1 A=4e-12 P=8e-6 -XM64_4 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT337 vss sub ptap1 A=4e-12 P=8e-6 -XM64_5 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT338 vss sub ptap1 A=4e-12 P=8e-6 -XM64_6 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT339 vss sub ptap1 A=4e-12 P=8e-6 -XM64_7 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT340 vss sub ptap1 A=4e-12 P=8e-6 -XM64_8 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT341 vss sub ptap1 A=4e-12 P=8e-6 -XM64_9 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT342 vss sub ptap1 A=4e-12 P=8e-6 -XM64_10 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT343 vss sub ptap1 A=4e-12 P=8e-6 -XM64_11 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT344 vss sub ptap1 A=4e-12 P=8e-6 -XM64_12 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT345 vss sub ptap1 A=4e-12 P=8e-6 -XM64_13 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT346 vss sub ptap1 A=4e-12 P=8e-6 -XM64_14 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT347 vss sub ptap1 A=4e-12 P=8e-6 -XM64_15 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT348 vss sub ptap1 A=4e-12 P=8e-6 -XM64_16 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT349 vss sub ptap1 A=4e-12 P=8e-6 -XM64_17 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT350 vss sub ptap1 A=4e-12 P=8e-6 -XM64_18 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT351 vss sub ptap1 A=4e-12 P=8e-6 -XM64_19 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT352 vss sub ptap1 A=4e-12 P=8e-6 -XM64_20 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT353 vss sub ptap1 A=4e-12 P=8e-6 -XM64_21 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT354 vss sub ptap1 A=4e-12 P=8e-6 -XM64_22 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT355 vss sub ptap1 A=4e-12 P=8e-6 -XM64_23 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT356 vss sub ptap1 A=4e-12 P=8e-6 -XM64_24 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT357 vss sub ptap1 A=4e-12 P=8e-6 -XM64_25 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT358 vss sub ptap1 A=4e-12 P=8e-6 -XM64_26 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT359 vss sub ptap1 A=4e-12 P=8e-6 -XM64_27 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT360 vss sub ptap1 A=4e-12 P=8e-6 -XM64_28 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT361 vss sub ptap1 A=4e-12 P=8e-6 -XM64_29 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT362 vss sub ptap1 A=4e-12 P=8e-6 -XM64_30 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT363 vss sub ptap1 A=4e-12 P=8e-6 -XM64_31 net85 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT364 vss sub ptap1 A=4e-12 P=8e-6 -XM65_0 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT365 vss sub ptap1 A=4e-12 P=8e-6 -XM65_1 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT366 vss sub ptap1 A=4e-12 P=8e-6 -XM65_2 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT367 vss sub ptap1 A=4e-12 P=8e-6 -XM65_3 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT368 vss sub ptap1 A=4e-12 P=8e-6 -XM65_4 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT369 vss sub ptap1 A=4e-12 P=8e-6 -XM65_5 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT370 vss sub ptap1 A=4e-12 P=8e-6 -XM65_6 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT371 vss sub ptap1 A=4e-12 P=8e-6 -XM65_7 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT372 vss sub ptap1 A=4e-12 P=8e-6 -XM65_8 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT373 vss sub ptap1 A=4e-12 P=8e-6 -XM65_9 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT374 vss sub ptap1 A=4e-12 P=8e-6 -XM65_10 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT375 vss sub ptap1 A=4e-12 P=8e-6 -XM65_11 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT376 vss sub ptap1 A=4e-12 P=8e-6 -XM65_12 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT377 vss sub ptap1 A=4e-12 P=8e-6 -XM65_13 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT378 vss sub ptap1 A=4e-12 P=8e-6 -XM65_14 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT379 vss sub ptap1 A=4e-12 P=8e-6 -XM65_15 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT380 vss sub ptap1 A=4e-12 P=8e-6 -XM65_16 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT381 vss sub ptap1 A=4e-12 P=8e-6 -XM65_17 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT382 vss sub ptap1 A=4e-12 P=8e-6 -XM65_18 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT383 vss sub ptap1 A=4e-12 P=8e-6 -XM65_19 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT384 vss sub ptap1 A=4e-12 P=8e-6 -XM65_20 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT385 vss sub ptap1 A=4e-12 P=8e-6 -XM65_21 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT386 vss sub ptap1 A=4e-12 P=8e-6 -XM65_22 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT387 vss sub ptap1 A=4e-12 P=8e-6 -XM65_23 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT388 vss sub ptap1 A=4e-12 P=8e-6 -XM65_24 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT389 vss sub ptap1 A=4e-12 P=8e-6 -XM65_25 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT390 vss sub ptap1 A=4e-12 P=8e-6 -XM65_26 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT391 vss sub ptap1 A=4e-12 P=8e-6 -XM65_27 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT392 vss sub ptap1 A=4e-12 P=8e-6 -XM65_28 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT393 vss sub ptap1 A=4e-12 P=8e-6 -XM65_29 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT394 vss sub ptap1 A=4e-12 P=8e-6 -XM65_30 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT395 vss sub ptap1 A=4e-12 P=8e-6 -XM65_31 net69 vb4 vss sub sg13_lv_nmos w=1u l=1u m=1 -XT396 vdd well_396 ntap1 A=4e-12 P=8e-6 -XM68_0 net2 net70 vdd well_396 sg13_lv_pmos w=1u l=1u m=1 -XT397 vdd well_397 ntap1 A=4e-12 P=8e-6 -XM68_1 net2 net70 vdd well_397 sg13_lv_pmos w=1u l=1u m=1 -XT398 vdd well_398 ntap1 A=4e-12 P=8e-6 -XM68_2 net2 net70 vdd well_398 sg13_lv_pmos w=1u l=1u m=1 -XT399 vdd well_399 ntap1 A=4e-12 P=8e-6 -XM68_3 net2 net70 vdd well_399 sg13_lv_pmos w=1u l=1u m=1 -XT400 vdd well_400 ntap1 A=4e-12 P=8e-6 -XM68_4 net2 net70 vdd well_400 sg13_lv_pmos w=1u l=1u m=1 -XT401 vdd well_401 ntap1 A=4e-12 P=8e-6 -XM68_5 net2 net70 vdd well_401 sg13_lv_pmos w=1u l=1u m=1 -XT402 vdd well_402 ntap1 A=4e-12 P=8e-6 -XM68_6 net2 net70 vdd well_402 sg13_lv_pmos w=1u l=1u m=1 -XT403 vdd well_403 ntap1 A=4e-12 P=8e-6 -XM68_7 net2 net70 vdd well_403 sg13_lv_pmos w=1u l=1u m=1 -XT404 vdd well_404 ntap1 A=4e-12 P=8e-6 -XM68_8 net2 net70 vdd well_404 sg13_lv_pmos w=1u l=1u m=1 -XT405 vdd well_405 ntap1 A=4e-12 P=8e-6 -XM68_9 net2 net70 vdd well_405 sg13_lv_pmos w=1u l=1u m=1 -XT406 vdd well_406 ntap1 A=4e-12 P=8e-6 -XM68_10 net2 net70 vdd well_406 sg13_lv_pmos w=1u l=1u m=1 -XT407 vdd well_407 ntap1 A=4e-12 P=8e-6 -XM68_11 net2 net70 vdd well_407 sg13_lv_pmos w=1u l=1u m=1 -XT408 vdd well_408 ntap1 A=4e-12 P=8e-6 -XM68_12 net2 net70 vdd well_408 sg13_lv_pmos w=1u l=1u m=1 -XT409 vdd well_409 ntap1 A=4e-12 P=8e-6 -XM68_13 net2 net70 vdd well_409 sg13_lv_pmos w=1u l=1u m=1 -XT410 vdd well_410 ntap1 A=4e-12 P=8e-6 -XM68_14 net2 net70 vdd well_410 sg13_lv_pmos w=1u l=1u m=1 -XT411 vdd well_411 ntap1 A=4e-12 P=8e-6 -XM68_15 net2 net70 vdd well_411 sg13_lv_pmos w=1u l=1u m=1 -XT412 vdd well_412 ntap1 A=4e-12 P=8e-6 -XM69_0 net3 net70 vdd well_412 sg13_lv_pmos w=1u l=1u m=1 -XT413 vdd well_413 ntap1 A=4e-12 P=8e-6 -XM69_1 net3 net70 vdd well_413 sg13_lv_pmos w=1u l=1u m=1 -XT414 vdd well_414 ntap1 A=4e-12 P=8e-6 -XM69_2 net3 net70 vdd well_414 sg13_lv_pmos w=1u l=1u m=1 -XT415 vdd well_415 ntap1 A=4e-12 P=8e-6 -XM69_3 net3 net70 vdd well_415 sg13_lv_pmos w=1u l=1u m=1 -XT416 vdd well_416 ntap1 A=4e-12 P=8e-6 -XM69_4 net3 net70 vdd well_416 sg13_lv_pmos w=1u l=1u m=1 -XT417 vdd well_417 ntap1 A=4e-12 P=8e-6 -XM69_5 net3 net70 vdd well_417 sg13_lv_pmos w=1u l=1u m=1 -XT418 vdd well_418 ntap1 A=4e-12 P=8e-6 -XM69_6 net3 net70 vdd well_418 sg13_lv_pmos w=1u l=1u m=1 -XT419 vdd well_419 ntap1 A=4e-12 P=8e-6 -XM69_7 net3 net70 vdd well_419 sg13_lv_pmos w=1u l=1u m=1 -XT420 vdd well_420 ntap1 A=4e-12 P=8e-6 -XM69_8 net3 net70 vdd well_420 sg13_lv_pmos w=1u l=1u m=1 -XT421 vdd well_421 ntap1 A=4e-12 P=8e-6 -XM69_9 net3 net70 vdd well_421 sg13_lv_pmos w=1u l=1u m=1 -XT422 vdd well_422 ntap1 A=4e-12 P=8e-6 -XM69_10 net3 net70 vdd well_422 sg13_lv_pmos w=1u l=1u m=1 -XT423 vdd well_423 ntap1 A=4e-12 P=8e-6 -XM69_11 net3 net70 vdd well_423 sg13_lv_pmos w=1u l=1u m=1 -XT424 vdd well_424 ntap1 A=4e-12 P=8e-6 -XM69_12 net3 net70 vdd well_424 sg13_lv_pmos w=1u l=1u m=1 -XT425 vdd well_425 ntap1 A=4e-12 P=8e-6 -XM69_13 net3 net70 vdd well_425 sg13_lv_pmos w=1u l=1u m=1 -XT426 vdd well_426 ntap1 A=4e-12 P=8e-6 -XM69_14 net3 net70 vdd well_426 sg13_lv_pmos w=1u l=1u m=1 -XT427 vdd well_427 ntap1 A=4e-12 P=8e-6 -XM69_15 net3 net70 vdd well_427 sg13_lv_pmos w=1u l=1u m=1 -XT428 vdd well_428 ntap1 A=4e-12 P=8e-6 -XM7_0 net049 voutn vdd well_428 sg13_lv_pmos w=1u l=1u m=1 -XT429 vdd well_429 ntap1 A=4e-12 P=8e-6 -XM7_1 net049 voutn vdd well_429 sg13_lv_pmos w=1u l=1u m=1 -XT430 vdd well_430 ntap1 A=4e-12 P=8e-6 -XM7_2 net049 voutn vdd well_430 sg13_lv_pmos w=1u l=1u m=1 -XT431 vdd well_431 ntap1 A=4e-12 P=8e-6 -XM7_3 net049 voutn vdd well_431 sg13_lv_pmos w=1u l=1u m=1 -XT432 vss sub ptap1 A=4e-12 P=8e-6 -XM70_0 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT433 vss sub ptap1 A=4e-12 P=8e-6 -XM70_1 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT434 vss sub ptap1 A=4e-12 P=8e-6 -XM70_2 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT435 vss sub ptap1 A=4e-12 P=8e-6 -XM70_3 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT436 vss sub ptap1 A=4e-12 P=8e-6 -XM70_4 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT437 vss sub ptap1 A=4e-12 P=8e-6 -XM70_5 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT438 vss sub ptap1 A=4e-12 P=8e-6 -XM70_6 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT439 vss sub ptap1 A=4e-12 P=8e-6 -XM70_7 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT440 vss sub ptap1 A=4e-12 P=8e-6 -XM70_8 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT441 vss sub ptap1 A=4e-12 P=8e-6 -XM70_9 net70 vb3 net69 sub sg13_lv_nmos w=1u l=1u m=1 -XT442 vss sub ptap1 A=4e-12 P=8e-6 -XM70_10 net70 vb3 net69 sub sg13_lv_nmos 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main sheet follows the circuit stages; repeated net names identify matching terminals within each sheet.","Physical R/C/Q use external model bindings with X-prefixed internal references; substrate terminals absent from artwork are printed explicitly and retained electrically. Exported decks are for connectivity inspection, not replacement simulation decks.","Repeated source devices remain individually represented. Large banks use contiguous source-order detail ranges only where needed for responsive editing."],"known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_016_song_dacfc"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/design/amp_016_song_dacfc.icproj.json"}}Main-sheet overview; 40 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_016_song_dacfcvdddm_1voutnnet5vddnet013vb4vinndm_2net31vddnet013vb3vddnet3net70vssvb4subnet54vddnet013vddnet013net31vinpnet049net1subvb3voutnnet85vssvb4subnet85vddvoutnnet049vssvb4subnet063subvb3voutndm_2vddvoutnet4vddnet043net4vdddm_1vddnet4dm_1net050vssvb4subnet56subvb3dm_1net56vddvoutnnet050vdddm_1voutnnet3vinnnet043net1vb4subvb3net54vddnet70net2vssvoutsubnet049vssvb4subdm_2vsssubvssnet043subvdddm_1net70net2vssvb4subnet69vinpnet063net31subvb3net70net69vssnet043subnet049vddvoutnnet5net4subvb3net063vddnet013net1vsssubvb3vddvinnvinpvoutvoutnet013net4vssvssnet70amp_016_song_dacfcC0_0cap_cmimw=31.57u l=31.57um=1C2_0cap_cmimw=21.55u l=21.55um=1XMM0_bank1XMM1_bank2XMM10_bank3XMM11_bank4XMM12_bank5XMM13_bank6XMM14_bank7XMM15_bank8XMM16_bank9XMM17_bank10XMM18_bank11XMM19_bank12XMM2_bank13XMM20_bank14XMM21_bank15XMM22_bank16XMM23_bank17XMM3_bank18XMM4_bank19XMM5_bank20XMM57_bank21XMM58_bank22XMM59_bank23XMM6_bank24XMM60_bank25XMM61_bank26XMM62_bank27XMM63_bank28XMM64_bank29XMM65_bank30XMM68_bank31XMM69_bank32XMM7_bank33XMM70_bank34XMM71_bank35XMM8_bank36XMM9_bank37XXRT40_bank38BIAS REFERENCES AND MIRRORSDIFFERENTIAL INPUT AND CASCODE CORESECOND GAIN STAGE AND AUXILIARY FEEDBACK - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md index f86e3fdf4fdb7fbe93d7aef51a002c84d0c8c035..6d0af2741d297f95d1d290215fed2cadc3e5be5f 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md @@ -4,7 +4,7 @@ Implement `amp_016_song_dacfc` with the supplied fixed topology and dimensions. The primary PMOS input pair feeds the cascoded voutn/net4 path. The separate XM57/XM58 input pair, biased by XM59, feeds net043/net049 directly; XM7 also feeds net049 from voutn. XM60/XM61 retain the main cascodes, while XM62/XM63, XM68/XM69 and XM64/XM65/XM70/XM71 retain the auxiliary net70 feedback network. XM11/XM23 drive vout. Both compensation capacitors remain: 1.5 pF from vout to net70 and 0.7 pF from net4 to vss. Do not replace the circuit, delete compensation, or add a servo. The physical core -contains 472 MOS after expanding explicit upstream multiplicities. Each PMOS +contains 37 logical MOS groups with upstream multiplicities. Each PMOS input body remains tied to its own tail node through its physical well contact. ## Inputs and Interface @@ -15,7 +15,7 @@ observations and `materials/ac.spice` defines balanced differential AC excitatio Ordered ports: `vss vdd vinn vinp vout net013`. `vss` is ground, `vdd` supply, `vinn/vinp` negative/positive input, `vout` the single-ended output, and `net013` the external bias-current sink. Bias, input drivers, feedback wiring and load are -external test apparatus; taps and all internal R/C are physical DUT elements. +external test apparatus; all internal R/C and actual body contacts are physical DUT elements. ## Operating Conditions @@ -35,10 +35,10 @@ AC sweeps 200 points per decade from 1 Hz to 1 GHz. The differential-mode deck r Supply a GDS <=64 MiB with top cell `amp_016_song_dacfc`, within 20000 by 2000 um (the task's artifact-size/outline bounds). Native DRC, strict named-interface LVS and functional-area measurement must pass; no marker waivers apply. Preserve -MOS dimensions, multiplicities, body connections, all physical R/C and tap geometry. +MOS dimensions, multiplicities, body connections, all physical R/C and logical body connectivity. Functional layers in the published task include active, implant, wells, gates, contacts, passive plates, vias and routing; annotation/text-only layers are excluded. -IHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation retains the explicit finite tap models. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job. +IHP native main and maximal DRC use the pinned PDK block profiles, with chip-level density and antenna disabled. Native MIM and high-poly primitives retain their compact models. Magic idealizes well/substrate taps; source simulation uses the declared logical body connections. This is not distributed substrate or RF/EM extraction. Candidate-derived Magic distributed RC feeds every post-layout job. ## Electrical Requirements and Scoring @@ -108,3 +108,5 @@ Finite-window amplifier response: tracking error 36%, ripple 22.5%, AC transfer Solve budget: **8 hours**. Use reviewed IHP SG13G2 resources and the ngspice 45 environment; see `/protocol/task.json` for frozen requirements and resource bindings. Explicitly submit `/workspace/output/final.gds` through the session tool; writing a file alone is insufficient. Evaluation checks files, native DRC/LVS, geometry, candidate RC, independent source simulation and post-layout simulation; source baselines, reference solutions and the author repository are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml index dd540a0815a8cfd6d8a2dd771e2c5f06f75a5170..f60fa4957ffec4c51ef6045dc67ddb702b394274 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml @@ -4,13 +4,6 @@ title = "Yan AZ Three-Stage Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "879c0c7b889decb6877118adbfc110dc50560c73ebb078c3aa6442e186efb93c" - [[assets]] path = "reference/amp_021_yan_az.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "e2b9c7534d6866f1cb3ad9924b7f4ff029fa9fcce9d0dc1a122487d0cba6e12b" +sha256 = "39bedd38c8d355124524e9809a1cb7ba4454254d138fc8afb36adc59bfe66dd7" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_021_yan_az" -sha256 = "490cbd376da9905b4a78527ec19101306e5a21c01822906a68d15a5cc974394c" +sha256 = "bdff9e4ee79809ab2499f77c52d9269d6728db8319af616d650ed4a3163f4696" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "dedb17b896280fa498e06aac8c840f7edec8c7f57a116108292a2bc5dab79ad2" +sha256 = "1fad82ccf87c21e498498a1535463416537fef228d0d39c865154203e745a0a1" [task.inputs.performance] path = "materials/testbench.spice" @@ -686,10 +679,10 @@ upper = 1e-06 rationale = "The ideal external feedback/injection fixture must preserve its stated common mode and DC feedback; 1 uV is the numerical consistency allowance for this measurement fixture." [task.evaluation.pre_layout] -source_report_sha256 = "deee25ba38af202141f6f9534280de7e21e2842d3c96a305bafd921342e7d4bb" +source_report_sha256 = "a13cbf7f7e8dd695c08a3b14fd8395159d6d304cc737fa69154e41aa094d7ca1" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -729,65 +722,60 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "9f75639b2743d2baa4082fed0b37af7d0fdfacc129c3d0b35cbd5dabf0f11a49" -dut = "dedb17b896280fa498e06aac8c840f7edec8c7f57a116108292a2bc5dab79ad2" +dut = "1fad82ccf87c21e498498a1535463416537fef228d0d39c865154203e745a0a1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 0.5139155539048934 +value = 0.5139159111504148 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = -0.04960392 +value = -0.04960408 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] -value = 0.4152886011471798 +value = 0.4133607780469337 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] -value = 0.2624499466655936 +value = 0.2615398327656031 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] -value = 0.2664402564287866 +value = 0.2656661912598312 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0001372918891475513 +value = 0.0001355444500917159 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] -value = 0.8532488151089851 +value = 0.8449964216158707 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] -value = 0.01787331297936472 +value = 0.01787071247760627 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.3070477297792138 +value = 0.3070477317907878 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 9.301193268110297e-05 +value = 9.301159864017528e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 0.1945447624583013 +value = 0.1953716360176374 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] -value = 0.6096700791259034 +value = 0.6096703098932652 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 0.8149665376305155 +value = 0.8142197102524538 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "868b18fb8fe932f67c57e30199b7d1b11e0b77ff7731061b85d89d651a7672f5" -ac = "75b265dea79b6392d0f4f41aa90329f636b986808ff8a5565436f7de206823a9" -transient = "b706733c2c073ec1634039dc9156d036f81225c1ec0df8b2f37ae61db100ae9b" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -814,28 +802,24 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "4532059d5ba64de59640959b7bc575b54e05a5a3a4b004693d7473d009703754" -dut = "dedb17b896280fa498e06aac8c840f7edec8c7f57a116108292a2bc5dab79ad2" +dut = "1fad82ccf87c21e498498a1535463416537fef228d0d39c865154203e745a0a1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] -value = 4.259671464197998e-08 +value = 4.298554161397722e-08 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] -value = 56.77529 +value = 56.77532 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] -value = 130.613 +value = 130.6145 unit = "dB" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "67ba2f596be2b39a5c15a2d2f69cc9472920911add71970d90d66c3a21b2febe" -ac = "4e5319510a5ff80b8b995f411465f10bc2bd41893bc5d836a90848111752c1cc" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -875,7 +859,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl index 074edf867c343ca6babe1c7a11edd5bc2d3dfcef..ed71a3845dfdd76de616e9f36b655496cc673457 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl @@ -1,219 +1,37 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_021_yan_az vss vdd vinn vinp vout vb1 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM0_0 vb1 vb1 vdd well_0 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM0_1 vb1 vb1 vdd well_1 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM0_2 vb1 vb1 vdd well_2 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM0_3 vb1 vb1 vdd well_3 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM1_0 vb4 vb1 vdd well_4 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM1_1 vb4 vb1 vdd well_5 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -MM1_2 vb4 vb1 vdd well_6 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM1_3 vb4 vb1 vdd well_7 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT8 net019 well_8 ntap1 A=4e-12 P=8e-6 -MM10_0 net063 vinp net019 well_8 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT9 net019 well_9 ntap1 A=4e-12 P=8e-6 -MM10_1 net063 vinp net019 well_9 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT10 net019 well_10 ntap1 A=4e-12 P=8e-6 -MM10_2 net063 vinp net019 well_10 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT11 net019 well_11 ntap1 A=4e-12 P=8e-6 -MM10_3 net063 vinp net019 well_11 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM11_0 net094 net050 vdd well_12 sg13_lv_pmos w=8.95u l=3.41u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM11_1 net094 net050 vdd well_13 sg13_lv_pmos w=8.95u l=3.41u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM11_2 net094 net050 vdd well_14 sg13_lv_pmos w=8.95u l=3.41u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM11_3 net094 net050 vdd well_15 sg13_lv_pmos w=8.95u l=3.41u m=1 -RT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -MM13_0 vout net050 vdd well_16 sg13_lv_pmos w=5.99u l=2.04u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM13_1 vout net050 vdd well_17 sg13_lv_pmos w=5.99u l=2.04u m=1 -RT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -MM13_2 vout net050 vdd well_18 sg13_lv_pmos w=5.99u l=2.04u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM13_3 vout net050 vdd well_19 sg13_lv_pmos w=5.99u l=2.04u m=1 -RT20 vss sub ptap1 A=4e-12 P=8e-6 -MM14_0 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT21 vss sub ptap1 A=4e-12 P=8e-6 -MM14_1 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT22 vss sub ptap1 A=4e-12 P=8e-6 -MM14_2 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT23 vss sub ptap1 A=4e-12 P=8e-6 -MM14_3 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT24 vss sub ptap1 A=4e-12 P=8e-6 -MM15_0 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT25 vss sub ptap1 A=4e-12 P=8e-6 -MM15_1 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT26 vss sub ptap1 A=4e-12 P=8e-6 -MM15_2 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT27 vss sub ptap1 A=4e-12 P=8e-6 -MM15_3 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -RT28 vss sub ptap1 A=4e-12 P=8e-6 -MM16_0 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT29 vss sub ptap1 A=4e-12 P=8e-6 -MM16_1 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT30 vss sub ptap1 A=4e-12 P=8e-6 -MM16_2 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT31 vss sub ptap1 A=4e-12 P=8e-6 -MM16_3 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT32 vss sub ptap1 A=4e-12 P=8e-6 -MM17_0 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT33 vss sub ptap1 A=4e-12 P=8e-6 -MM17_1 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT34 vss sub ptap1 A=4e-12 P=8e-6 -MM17_2 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT35 vss sub ptap1 A=4e-12 P=8e-6 -MM17_3 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -RT36 vss sub ptap1 A=4e-12 P=8e-6 -MM18_0 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -RT37 vss sub ptap1 A=4e-12 P=8e-6 -MM18_1 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -RT38 vss sub ptap1 A=4e-12 P=8e-6 -MM18_2 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -RT39 vss sub ptap1 A=4e-12 P=8e-6 -MM18_3 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -RT40 vss sub ptap1 A=4e-12 P=8e-6 -MM19_0 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT41 vss sub ptap1 A=4e-12 P=8e-6 -MM19_1 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT42 vss sub ptap1 A=4e-12 P=8e-6 -MM19_2 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT43 vss sub ptap1 A=4e-12 P=8e-6 -MM19_3 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -MM2_0 net019 vb1 vdd well_44 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -MM2_1 net019 vb1 vdd well_45 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -MM2_2 net019 vb1 vdd well_46 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -MM2_3 net019 vb1 vdd well_47 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -MM2_4 net019 vb1 vdd well_48 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -MM2_5 net019 vb1 vdd well_49 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -MM2_6 net019 vb1 vdd well_50 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -MM2_7 net019 vb1 vdd well_51 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT52 vss sub ptap1 A=4e-12 P=8e-6 -MM20_0 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT53 vss sub ptap1 A=4e-12 P=8e-6 -MM20_1 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT54 vss sub ptap1 A=4e-12 P=8e-6 -MM20_2 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT55 vss sub ptap1 A=4e-12 P=8e-6 -MM20_3 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT56 vss sub ptap1 A=4e-12 P=8e-6 -MM21_0 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT57 vss sub ptap1 A=4e-12 P=8e-6 -MM21_1 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT58 vss sub ptap1 A=4e-12 P=8e-6 -MM21_2 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT59 vss sub ptap1 A=4e-12 P=8e-6 -MM21_3 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -RT60 vss sub ptap1 A=4e-12 P=8e-6 -MM22_0 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -RT61 vss sub ptap1 A=4e-12 P=8e-6 -MM22_1 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -RT62 vss sub ptap1 A=4e-12 P=8e-6 -MM22_2 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -RT63 vss sub ptap1 A=4e-12 P=8e-6 -MM22_3 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -RT64 vss sub ptap1 A=4e-12 P=8e-6 -MM23_0 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -RT65 vss sub ptap1 A=4e-12 P=8e-6 -MM23_1 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -RT66 vss sub ptap1 A=4e-12 P=8e-6 -MM23_2 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -RT67 vss sub ptap1 A=4e-12 P=8e-6 -MM23_3 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -RT68 vdd well_68 ntap1 A=4e-12 P=8e-6 -MM3_0 net078 vb1 vdd well_68 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT69 vdd well_69 ntap1 A=4e-12 P=8e-6 -MM3_1 net078 vb1 vdd well_69 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT70 vdd well_70 ntap1 A=4e-12 P=8e-6 -MM3_2 net078 vb1 vdd well_70 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT71 vdd well_71 ntap1 A=4e-12 P=8e-6 -MM3_3 net078 vb1 vdd well_71 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT72 vdd well_72 ntap1 A=4e-12 P=8e-6 -MM3_4 net078 vb1 vdd well_72 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT73 vdd well_73 ntap1 A=4e-12 P=8e-6 -MM3_5 net078 vb1 vdd well_73 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT74 vdd well_74 ntap1 A=4e-12 P=8e-6 -MM3_6 net078 vb1 vdd well_74 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT75 vdd well_75 ntap1 A=4e-12 P=8e-6 -MM3_7 net078 vb1 vdd well_75 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT76 vdd well_76 ntap1 A=4e-12 P=8e-6 -MM3_8 net078 vb1 vdd well_76 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT77 vdd well_77 ntap1 A=4e-12 P=8e-6 -MM3_9 net078 vb1 vdd well_77 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT78 vdd well_78 ntap1 A=4e-12 P=8e-6 -MM3_10 net078 vb1 vdd well_78 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT79 vdd well_79 ntap1 A=4e-12 P=8e-6 -MM3_11 net078 vb1 vdd well_79 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT80 vdd well_80 ntap1 A=4e-12 P=8e-6 -MM3_12 net078 vb1 vdd well_80 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT81 vdd well_81 ntap1 A=4e-12 P=8e-6 -MM3_13 net078 vb1 vdd well_81 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT82 vdd well_82 ntap1 A=4e-12 P=8e-6 -MM3_14 net078 vb1 vdd well_82 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT83 vdd well_83 ntap1 A=4e-12 P=8e-6 -MM3_15 net078 vb1 vdd well_83 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT84 vdd well_84 ntap1 A=4e-12 P=8e-6 -MM4_0 voutn voutn vdd well_84 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT85 vdd well_85 ntap1 A=4e-12 P=8e-6 -MM4_1 voutn voutn vdd well_85 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT86 vdd well_86 ntap1 A=4e-12 P=8e-6 -MM4_2 voutn voutn vdd well_86 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT87 vdd well_87 ntap1 A=4e-12 P=8e-6 -MM4_3 voutn voutn vdd well_87 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT88 vdd well_88 ntap1 A=4e-12 P=8e-6 -MM5_0 net050 voutn vdd well_88 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT89 vdd well_89 ntap1 A=4e-12 P=8e-6 -MM5_1 net050 voutn vdd well_89 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT90 vdd well_90 ntap1 A=4e-12 P=8e-6 -MM5_2 net050 voutn vdd well_90 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT91 vdd well_91 ntap1 A=4e-12 P=8e-6 -MM5_3 net050 voutn vdd well_91 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT92 vdd well_92 ntap1 A=4e-12 P=8e-6 -MM67_0 net057 voutn vdd well_92 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT93 vdd well_93 ntap1 A=4e-12 P=8e-6 -MM67_1 net057 voutn vdd well_93 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT94 vdd well_94 ntap1 A=4e-12 P=8e-6 -MM67_2 net057 voutn vdd well_94 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT95 vdd well_95 ntap1 A=4e-12 P=8e-6 -MM67_3 net057 voutn vdd well_95 sg13_lv_pmos w=0.54u l=3.85u m=1 -RT96 net019 well_96 ntap1 A=4e-12 P=8e-6 -MM9_0 dm_2 vinn net019 well_96 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT97 net019 well_97 ntap1 A=4e-12 P=8e-6 -MM9_1 dm_2 vinn net019 well_97 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT98 net019 well_98 ntap1 A=4e-12 P=8e-6 -MM9_2 dm_2 vinn net019 well_98 sg13_lv_pmos w=2.59u l=0.37u m=1 -RT99 net019 well_99 ntap1 A=4e-12 P=8e-6 -MM9_3 dm_2 vinn net019 well_99 sg13_lv_pmos w=2.59u l=0.37u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 -C0_0 net063 vout cap_cmim w=36.86u l=36.86u m=1 -C0_1 net063 vout cap_cmim w=36.86u l=36.86u m=1 -C1_0 net051 vss cap_cmim w=46.99u l=46.99u m=1 -C1_1 net051 vss cap_cmim w=46.99u l=46.99u m=1 -RR0_0 net078 R0_s1 sub rhigh w=.5u l=61.2u m=1 b=0 -RR0_1 R0_s1 net077 sub rhigh w=.5u l=61.2u m=1 b=0 -RR1_0 net078 net082 sub rhigh w=.5u l=19.43u m=1 b=0 -RR2_0 net094 R2_s1 sub rhigh w=.5u l=79.64u m=1 b=0 -RR2_1 R2_s1 R2_s2 sub rhigh w=.5u l=79.64u m=1 b=0 -RR2_2 R2_s2 R2_s3 sub rhigh w=.5u l=79.64u m=1 b=0 -RR2_3 R2_s3 R2_s4 sub rhigh w=.5u l=79.64u m=1 b=0 -RR2_4 R2_s4 R2_s5 sub rhigh w=.5u l=79.64u m=1 b=0 -RR2_5 R2_s5 R2_s6 sub rhigh w=.5u l=79.64u m=1 b=0 -RR2_6 R2_s6 net051 sub rhigh w=.5u l=79.64u m=1 b=0 +MM0 vb1 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +MM1 vb4 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +MM10 net063 vinp net019 net019 sg13_lv_pmos w=2.59u l=0.37u m=4 +MM11 net094 net050 vdd vdd sg13_lv_pmos w=8.95u l=3.41u m=4 +MM13 vout net050 vdd vdd sg13_lv_pmos w=5.99u l=2.04u m=4 +MM14 voutn net077 dm_2 vss sg13_lv_nmos w=9.12u l=7.48u m=4 +MM15 net050 net082 net063 vss sg13_lv_nmos w=9.12u l=7.48u m=4 +MM16 net077 dm_2 vss vss sg13_lv_nmos w=2.64u l=5.64u m=4 +MM17 net082 net063 vss vss sg13_lv_nmos w=2.64u l=5.64u m=4 +MM18 vout net057 vss vss sg13_lv_nmos w=0.41u l=3u m=4 +MM19 vb4 vb4 vss vss sg13_lv_nmos w=2.01u l=1.26u m=4 +MM2 net019 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=8 +MM20 dm_2 vb4 vss vss sg13_lv_nmos w=2.01u l=1.26u m=4 +MM21 net063 vb4 vss vss sg13_lv_nmos w=2.01u l=1.26u m=4 +MM22 net094 net051 vss vss sg13_lv_nmos w=6.13u l=2.09u m=4 +MM23 net057 net094 vss vss sg13_lv_nmos w=5.95u l=9.97u m=4 +MM3 net078 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=16 +MM4 voutn voutn vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +MM5 net050 voutn vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +MM67 net057 voutn vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +MM9 dm_2 vinn net019 net019 sg13_lv_pmos w=2.59u l=0.37u m=4 +C0_0 net063 vout cap_cmim w=36.86u l=36.86u m=2 +C1_0 net051 vss cap_cmim w=46.99u l=46.99u m=2 +RR0_0 net078 R0_s1 vss rhigh w=.5u l=61.2u m=1 b=0 +RR0_1 R0_s1 net077 vss rhigh w=.5u l=61.2u m=1 b=0 +RR1_0 net078 net082 vss rhigh w=.5u l=19.43u m=1 b=0 +RR2_0 net094 R2_s1 vss rhigh w=.5u l=79.64u m=1 b=0 +RR2_1 R2_s1 R2_s2 vss rhigh w=.5u l=79.64u m=1 b=0 +RR2_2 R2_s2 R2_s3 vss rhigh w=.5u l=79.64u m=1 b=0 +RR2_3 R2_s3 R2_s4 vss rhigh w=.5u l=79.64u m=1 b=0 +RR2_4 R2_s4 R2_s5 vss rhigh w=.5u l=79.64u m=1 b=0 +RR2_5 R2_s5 R2_s6 vss rhigh w=.5u l=79.64u m=1 b=0 +RR2_6 R2_s6 net051 vss rhigh w=.5u l=79.64u m=1 b=0 .ends amp_021_yan_az diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.spice index 8fae5b7019421a153cbb1e62083e7b3a9d9d421d..e43d06f165333d83f1fde6e32e9dd902eabf913b 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.spice @@ -1,219 +1,37 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_021_yan_az vss vdd vinn vinp vout vb1 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM0_0 vb1 vb1 vdd well_0 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM0_1 vb1 vb1 vdd well_1 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM0_2 vb1 vb1 vdd well_2 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM0_3 vb1 vb1 vdd well_3 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM1_0 vb4 vb1 vdd well_4 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM1_1 vb4 vb1 vdd well_5 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -XM1_2 vb4 vb1 vdd well_6 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM1_3 vb4 vb1 vdd well_7 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT8 net019 well_8 ntap1 A=4e-12 P=8e-6 -XM10_0 net063 vinp net019 well_8 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT9 net019 well_9 ntap1 A=4e-12 P=8e-6 -XM10_1 net063 vinp net019 well_9 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT10 net019 well_10 ntap1 A=4e-12 P=8e-6 -XM10_2 net063 vinp net019 well_10 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT11 net019 well_11 ntap1 A=4e-12 P=8e-6 -XM10_3 net063 vinp net019 well_11 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM11_0 net094 net050 vdd well_12 sg13_lv_pmos w=8.95u l=3.41u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM11_1 net094 net050 vdd well_13 sg13_lv_pmos w=8.95u l=3.41u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM11_2 net094 net050 vdd well_14 sg13_lv_pmos w=8.95u l=3.41u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM11_3 net094 net050 vdd well_15 sg13_lv_pmos w=8.95u l=3.41u m=1 -XT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -XM13_0 vout net050 vdd well_16 sg13_lv_pmos w=5.99u l=2.04u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM13_1 vout net050 vdd well_17 sg13_lv_pmos w=5.99u l=2.04u m=1 -XT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -XM13_2 vout net050 vdd well_18 sg13_lv_pmos w=5.99u l=2.04u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM13_3 vout net050 vdd well_19 sg13_lv_pmos w=5.99u l=2.04u m=1 -XT20 vss sub ptap1 A=4e-12 P=8e-6 -XM14_0 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT21 vss sub ptap1 A=4e-12 P=8e-6 -XM14_1 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT22 vss sub ptap1 A=4e-12 P=8e-6 -XM14_2 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT23 vss sub ptap1 A=4e-12 P=8e-6 -XM14_3 voutn net077 dm_2 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT24 vss sub ptap1 A=4e-12 P=8e-6 -XM15_0 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT25 vss sub ptap1 A=4e-12 P=8e-6 -XM15_1 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT26 vss sub ptap1 A=4e-12 P=8e-6 -XM15_2 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT27 vss sub ptap1 A=4e-12 P=8e-6 -XM15_3 net050 net082 net063 sub sg13_lv_nmos w=9.12u l=7.48u m=1 -XT28 vss sub ptap1 A=4e-12 P=8e-6 -XM16_0 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT29 vss sub ptap1 A=4e-12 P=8e-6 -XM16_1 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT30 vss sub ptap1 A=4e-12 P=8e-6 -XM16_2 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT31 vss sub ptap1 A=4e-12 P=8e-6 -XM16_3 net077 dm_2 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT32 vss sub ptap1 A=4e-12 P=8e-6 -XM17_0 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT33 vss sub ptap1 A=4e-12 P=8e-6 -XM17_1 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT34 vss sub ptap1 A=4e-12 P=8e-6 -XM17_2 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT35 vss sub ptap1 A=4e-12 P=8e-6 -XM17_3 net082 net063 vss sub sg13_lv_nmos w=2.64u l=5.64u m=1 -XT36 vss sub ptap1 A=4e-12 P=8e-6 -XM18_0 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -XT37 vss sub ptap1 A=4e-12 P=8e-6 -XM18_1 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -XT38 vss sub ptap1 A=4e-12 P=8e-6 -XM18_2 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -XT39 vss sub ptap1 A=4e-12 P=8e-6 -XM18_3 vout net057 vss sub sg13_lv_nmos w=0.41u l=3u m=1 -XT40 vss sub ptap1 A=4e-12 P=8e-6 -XM19_0 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT41 vss sub ptap1 A=4e-12 P=8e-6 -XM19_1 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT42 vss sub ptap1 A=4e-12 P=8e-6 -XM19_2 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT43 vss sub ptap1 A=4e-12 P=8e-6 -XM19_3 vb4 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -XM2_0 net019 vb1 vdd well_44 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -XM2_1 net019 vb1 vdd well_45 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -XM2_2 net019 vb1 vdd well_46 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -XM2_3 net019 vb1 vdd well_47 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -XM2_4 net019 vb1 vdd well_48 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -XM2_5 net019 vb1 vdd well_49 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -XM2_6 net019 vb1 vdd well_50 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -XM2_7 net019 vb1 vdd well_51 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT52 vss sub ptap1 A=4e-12 P=8e-6 -XM20_0 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT53 vss sub ptap1 A=4e-12 P=8e-6 -XM20_1 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT54 vss sub ptap1 A=4e-12 P=8e-6 -XM20_2 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT55 vss sub ptap1 A=4e-12 P=8e-6 -XM20_3 dm_2 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT56 vss sub ptap1 A=4e-12 P=8e-6 -XM21_0 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT57 vss sub ptap1 A=4e-12 P=8e-6 -XM21_1 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT58 vss sub ptap1 A=4e-12 P=8e-6 -XM21_2 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT59 vss sub ptap1 A=4e-12 P=8e-6 -XM21_3 net063 vb4 vss sub sg13_lv_nmos w=2.01u l=1.26u m=1 -XT60 vss sub ptap1 A=4e-12 P=8e-6 -XM22_0 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -XT61 vss sub ptap1 A=4e-12 P=8e-6 -XM22_1 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -XT62 vss sub ptap1 A=4e-12 P=8e-6 -XM22_2 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -XT63 vss sub ptap1 A=4e-12 P=8e-6 -XM22_3 net094 net051 vss sub sg13_lv_nmos w=6.13u l=2.09u m=1 -XT64 vss sub ptap1 A=4e-12 P=8e-6 -XM23_0 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -XT65 vss sub ptap1 A=4e-12 P=8e-6 -XM23_1 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -XT66 vss sub ptap1 A=4e-12 P=8e-6 -XM23_2 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -XT67 vss sub ptap1 A=4e-12 P=8e-6 -XM23_3 net057 net094 vss sub sg13_lv_nmos w=5.95u l=9.97u m=1 -XT68 vdd well_68 ntap1 A=4e-12 P=8e-6 -XM3_0 net078 vb1 vdd well_68 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT69 vdd well_69 ntap1 A=4e-12 P=8e-6 -XM3_1 net078 vb1 vdd well_69 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT70 vdd well_70 ntap1 A=4e-12 P=8e-6 -XM3_2 net078 vb1 vdd well_70 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT71 vdd well_71 ntap1 A=4e-12 P=8e-6 -XM3_3 net078 vb1 vdd well_71 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT72 vdd well_72 ntap1 A=4e-12 P=8e-6 -XM3_4 net078 vb1 vdd well_72 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT73 vdd well_73 ntap1 A=4e-12 P=8e-6 -XM3_5 net078 vb1 vdd well_73 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT74 vdd well_74 ntap1 A=4e-12 P=8e-6 -XM3_6 net078 vb1 vdd well_74 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT75 vdd well_75 ntap1 A=4e-12 P=8e-6 -XM3_7 net078 vb1 vdd well_75 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT76 vdd well_76 ntap1 A=4e-12 P=8e-6 -XM3_8 net078 vb1 vdd well_76 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT77 vdd well_77 ntap1 A=4e-12 P=8e-6 -XM3_9 net078 vb1 vdd well_77 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT78 vdd well_78 ntap1 A=4e-12 P=8e-6 -XM3_10 net078 vb1 vdd well_78 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT79 vdd well_79 ntap1 A=4e-12 P=8e-6 -XM3_11 net078 vb1 vdd well_79 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT80 vdd well_80 ntap1 A=4e-12 P=8e-6 -XM3_12 net078 vb1 vdd well_80 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT81 vdd well_81 ntap1 A=4e-12 P=8e-6 -XM3_13 net078 vb1 vdd well_81 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT82 vdd well_82 ntap1 A=4e-12 P=8e-6 -XM3_14 net078 vb1 vdd well_82 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT83 vdd well_83 ntap1 A=4e-12 P=8e-6 -XM3_15 net078 vb1 vdd well_83 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT84 vdd well_84 ntap1 A=4e-12 P=8e-6 -XM4_0 voutn voutn vdd well_84 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT85 vdd well_85 ntap1 A=4e-12 P=8e-6 -XM4_1 voutn voutn vdd well_85 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT86 vdd well_86 ntap1 A=4e-12 P=8e-6 -XM4_2 voutn voutn vdd well_86 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT87 vdd well_87 ntap1 A=4e-12 P=8e-6 -XM4_3 voutn voutn vdd well_87 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT88 vdd well_88 ntap1 A=4e-12 P=8e-6 -XM5_0 net050 voutn vdd well_88 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT89 vdd well_89 ntap1 A=4e-12 P=8e-6 -XM5_1 net050 voutn vdd well_89 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT90 vdd well_90 ntap1 A=4e-12 P=8e-6 -XM5_2 net050 voutn vdd well_90 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT91 vdd well_91 ntap1 A=4e-12 P=8e-6 -XM5_3 net050 voutn vdd well_91 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT92 vdd well_92 ntap1 A=4e-12 P=8e-6 -XM67_0 net057 voutn vdd well_92 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT93 vdd well_93 ntap1 A=4e-12 P=8e-6 -XM67_1 net057 voutn vdd well_93 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT94 vdd well_94 ntap1 A=4e-12 P=8e-6 -XM67_2 net057 voutn vdd well_94 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT95 vdd well_95 ntap1 A=4e-12 P=8e-6 -XM67_3 net057 voutn vdd well_95 sg13_lv_pmos w=0.54u l=3.85u m=1 -XT96 net019 well_96 ntap1 A=4e-12 P=8e-6 -XM9_0 dm_2 vinn net019 well_96 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT97 net019 well_97 ntap1 A=4e-12 P=8e-6 -XM9_1 dm_2 vinn net019 well_97 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT98 net019 well_98 ntap1 A=4e-12 P=8e-6 -XM9_2 dm_2 vinn net019 well_98 sg13_lv_pmos w=2.59u l=0.37u m=1 -XT99 net019 well_99 ntap1 A=4e-12 P=8e-6 -XM9_3 dm_2 vinn net019 well_99 sg13_lv_pmos w=2.59u l=0.37u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 -XC0_0 net063 vout cap_cmim w=36.86u l=36.86u m=1 -XC0_1 net063 vout cap_cmim w=36.86u l=36.86u m=1 -XC1_0 net051 vss cap_cmim w=46.99u l=46.99u m=1 -XC1_1 net051 vss cap_cmim w=46.99u l=46.99u m=1 -XR0_0 net078 R0_s1 sub rhigh w=.5u l=61.2u m=1 b=0 -XR0_1 R0_s1 net077 sub rhigh w=.5u l=61.2u m=1 b=0 -XR1_0 net078 net082 sub rhigh w=.5u l=19.43u m=1 b=0 -XR2_0 net094 R2_s1 sub rhigh w=.5u l=79.64u m=1 b=0 -XR2_1 R2_s1 R2_s2 sub rhigh w=.5u l=79.64u m=1 b=0 -XR2_2 R2_s2 R2_s3 sub rhigh w=.5u l=79.64u m=1 b=0 -XR2_3 R2_s3 R2_s4 sub rhigh w=.5u l=79.64u m=1 b=0 -XR2_4 R2_s4 R2_s5 sub rhigh w=.5u l=79.64u m=1 b=0 -XR2_5 R2_s5 R2_s6 sub rhigh w=.5u l=79.64u m=1 b=0 -XR2_6 R2_s6 net051 sub rhigh w=.5u l=79.64u m=1 b=0 +XM0 vb1 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +XM1 vb4 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +XM10 net063 vinp net019 net019 sg13_lv_pmos w=2.59u l=0.37u m=4 +XM11 net094 net050 vdd vdd sg13_lv_pmos w=8.95u l=3.41u m=4 +XM13 vout net050 vdd vdd sg13_lv_pmos w=5.99u l=2.04u m=4 +XM14 voutn net077 dm_2 vss sg13_lv_nmos w=9.12u l=7.48u m=4 +XM15 net050 net082 net063 vss sg13_lv_nmos w=9.12u l=7.48u m=4 +XM16 net077 dm_2 vss vss sg13_lv_nmos w=2.64u l=5.64u m=4 +XM17 net082 net063 vss vss sg13_lv_nmos w=2.64u l=5.64u m=4 +XM18 vout net057 vss vss sg13_lv_nmos w=0.41u l=3u m=4 +XM19 vb4 vb4 vss vss sg13_lv_nmos w=2.01u l=1.26u m=4 +XM2 net019 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=8 +XM20 dm_2 vb4 vss vss sg13_lv_nmos w=2.01u l=1.26u m=4 +XM21 net063 vb4 vss vss sg13_lv_nmos w=2.01u l=1.26u m=4 +XM22 net094 net051 vss vss sg13_lv_nmos w=6.13u l=2.09u m=4 +XM23 net057 net094 vss vss sg13_lv_nmos w=5.95u l=9.97u m=4 +XM3 net078 vb1 vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=16 +XM4 voutn voutn vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +XM5 net050 voutn vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +XM67 net057 voutn vdd vdd sg13_lv_pmos w=0.54u l=3.85u m=4 +XM9 dm_2 vinn net019 net019 sg13_lv_pmos w=2.59u l=0.37u m=4 +XC0_0 net063 vout cap_cmim w=36.86u l=36.86u m=2 +XC1_0 net051 vss cap_cmim w=46.99u l=46.99u m=2 +XR0_0 net078 R0_s1 vss rhigh w=.5u l=61.2u m=1 b=0 +XR0_1 R0_s1 net077 vss rhigh w=.5u l=61.2u m=1 b=0 +XR1_0 net078 net082 vss rhigh w=.5u l=19.43u m=1 b=0 +XR2_0 net094 R2_s1 vss rhigh w=.5u l=79.64u m=1 b=0 +XR2_1 R2_s1 R2_s2 vss rhigh w=.5u l=79.64u m=1 b=0 +XR2_2 R2_s2 R2_s3 vss rhigh w=.5u l=79.64u m=1 b=0 +XR2_3 R2_s3 R2_s4 vss rhigh w=.5u l=79.64u m=1 b=0 +XR2_4 R2_s4 R2_s5 vss rhigh w=.5u l=79.64u m=1 b=0 +XR2_5 R2_s5 R2_s6 vss rhigh w=.5u l=79.64u m=1 b=0 +XR2_6 R2_s6 net051 vss rhigh w=.5u l=79.64u m=1 b=0 .ends amp_021_yan_az diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/schematic.svg deleted file mode 100644 index 5ae2ba89f21dcccc4cdf3d9e81c95ce0c5e52938..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_021_yan_az{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_021_yan_az","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_021_yan_az","MM0_bank1","MM1_bank2","MM10_bank3","MM11_bank4","MM13_bank5","MM14_bank6","MM15_bank7","MM16_bank8","MM17_bank9","MM18_bank10","MM19_bank11","MM2_bank12","MM20_bank13","MM21_bank14","MM22_bank15","MM23_bank16","MM3_bank17","MM4_bank18","MM5_bank19","MM67_bank20","MM9_bank21","XRT20_bank22","XRR2_bank23"],"banks":[{"name":"MM0_bank1","devices":8,"source_references":["RT0","MM0_0","RT1","MM0_1","RT2","MM0_2","RT3","MM0_3"]},{"name":"MM1_bank2","devices":8,"source_references":["RT4","MM1_0","RT5","MM1_1","RT6","MM1_2","RT7","MM1_3"]},{"name":"MM10_bank3","devices":8,"source_references":["RT8","MM10_0","RT9","MM10_1","RT10","MM10_2","RT11","MM10_3"]},{"name":"MM11_bank4","devices":8,"source_references":["RT12","MM11_0","RT13","MM11_1","RT14","MM11_2","RT15","MM11_3"]},{"name":"MM13_bank5","devices":8,"source_references":["RT16","MM13_0","RT17","MM13_1","RT18","MM13_2","RT19","MM13_3"]},{"name":"MM14_bank6","devices":4,"source_references":["MM14_0","MM14_1","MM14_2","MM14_3"]},{"name":"MM15_bank7","devices":4,"source_references":["MM15_0","MM15_1","MM15_2","MM15_3"]},{"name":"MM16_bank8","devices":4,"source_references":["MM16_0","MM16_1","MM16_2","MM16_3"]},{"name":"MM17_bank9","devices":4,"source_references":["MM17_0","MM17_1","MM17_2","MM17_3"]},{"name":"MM18_bank10","devices":4,"source_references":["MM18_0","MM18_1","MM18_2","MM18_3"]},{"name":"MM19_bank11","devices":4,"source_references":["MM19_0","MM19_1","MM19_2","MM19_3"]},{"name":"MM2_bank12","devices":16,"source_references":["RT44","MM2_0","RT45","MM2_1","RT46","MM2_2","RT47","MM2_3","RT48","MM2_4","RT49","MM2_5","RT50","MM2_6","RT51","MM2_7"]},{"name":"MM20_bank13","devices":4,"source_references":["MM20_0","MM20_1","MM20_2","MM20_3"]},{"name":"MM21_bank14","devices":4,"source_references":["MM21_0","MM21_1","MM21_2","MM21_3"]},{"name":"MM22_bank15","devices":4,"source_references":["MM22_0","MM22_1","MM22_2","MM22_3"]},{"name":"MM23_bank16","devices":4,"source_references":["MM23_0","MM23_1","MM23_2","MM23_3"]},{"name":"MM3_bank17","devices":32,"source_references":["RT68","MM3_0","RT69","MM3_1","RT70","MM3_2","RT71","MM3_3","RT72","MM3_4","RT73","MM3_5","RT74","MM3_6","RT75","MM3_7","RT76","MM3_8","RT77","MM3_9","RT78","MM3_10","RT79","MM3_11","RT80","MM3_12","RT81","MM3_13","RT82","MM3_14","RT83","MM3_15"]},{"name":"MM4_bank18","devices":8,"source_references":["RT84","MM4_0","RT85","MM4_1","RT86","MM4_2","RT87","MM4_3"]},{"name":"MM5_bank19","devices":8,"source_references":["RT88","MM5_0","RT89","MM5_1","RT90","MM5_2","RT91","MM5_3"]},{"name":"MM67_bank20","devices":8,"source_references":["RT92","MM67_0","RT93","MM67_1","RT94","MM67_2","RT95","MM67_3"]},{"name":"MM9_bank21","devices":8,"source_references":["RT96","MM9_0","RT97","MM9_1","RT98","MM9_2","RT99","MM9_3"]},{"name":"XRT20_bank22","devices":41,"source_references":["RT20","RT21","RT22","RT23","RT24","RT25","RT26","RT27","RT28","RT29","RT30","RT31","RT32","RT33","RT34","RT35","RT36","RT37","RT38","RT39","RT40","RT41","RT42","RT43","RT52","RT53","RT54","RT55","RT56","RT57","RT58","RT59","RT60","RT61","RT62","RT63","RT64","RT65","RT66","RT67","RTSUB"]},{"name":"XRR2_bank23","devices":7,"source_references":["RR2_0","RR2_1","RR2_2","RR2_3","RR2_4","RR2_5","RR2_6"]}],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_021_yan_az"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/design/amp_021_yan_az.icproj.json"}}Main-sheet overview; 23 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_021_yan_azvddvb1vb4net094subnet051vddvb1net078vddvb1vddvoutnvssvb4subdm_2net063net050subnet082vddnet094net050vinpnet019net063vddvb1net019vssnet063subnet082vssvoutsubnet057vddvoutnet050vssnet094subnet057vssvb4subvssvb4net063subvinnnet019dm_2vssnet094subnet051vddnet050voutnvsssubvsssubnet077dm_2vddvoutnnet057subvoutnnet077dm_2net063net094net094net063net078net078net050net050net057net057voutvddvinnvinpvoutvb1net063vssnet077net082net051net078R0_s1amp_021_yan_azC0_0cap_cmimw=36.86u l=36.86um=1C0_1cap_cmimw=36.86u l=36.86um=1C1_0cap_cmimw=46.99u l=46.99um=1C1_1cap_cmimw=46.99u l=46.99um=1RR0_0rhighw=.5u l=61.2uRR0_1RR1_0rhighw=.5u l=19.43uBIAS AND REFERENCEINPUT PAIR AND ACTIVE LOADOUTPUT AND COMPENSATIONXMM0_bank1XMM1_bank2XMM19_bank11XMM2_bank12XMM3_bank17XMM9_bank21XMM10_bank3XMM20_bank13XMM21_bank14XMM16_bank8XMM17_bank9XMM14_bank6XMM15_bank7XMM4_bank18XMM5_bank19XMM67_bank20XMM11_bank4XMM13_bank5XMM18_bank10XMM22_bank15XMM23_bank16XXRT20_bank22XXRR2_bank23 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md index 5e0ab0de41c278350c6908ed7a57e9b597ad304c..62ee373fc58c3aba0935921c4ee150b0a2f1af51 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md @@ -8,7 +8,7 @@ Implement `amp_021_yan_az` without changing the declared circuit. XM9/XM10 form `materials/circuit.cdl` is the authoritative physical circuit and `materials/circuit.spice` its equivalent simulation representation; `materials/testbench.spice` and `materials/ac.spice` define transient/closed-loop AC and balanced open-loop AC, respectively. This statement is the description input. Ordered interface is `vss vdd vinn vinp vout vb1`: `vss`/`vdd` are supply rails; all other signals, bias/reference and unloaded monitor ports retain netlist connections. Independent bias sources and loads remain outside the physical core. -W/L are rounded to 10 nm for centred contacts on the 5 nm grid. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. +W/L are rounded to 10 nm for centred contacts on the 5 nm grid. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source and extraction use logical body nets. Native LVS checks actual body-contact connectivity. Distributed substrate behavior is outside this model boundary. ## Operating Conditions @@ -89,3 +89,5 @@ Finite-window amplifier response: tracking error 36%, ripple 22.5%, AC transfer Solve budget: **8 hours**. Use the reviewed SG13G2 resources and ngspice 45 environment. Frozen inputs, requirements and tool bindings are in `/protocol/task.json`. Explicitly submit `/workspace/output/final.gds` through the session submission tool; file generation alone is not submission. Evaluation performs native checks, candidate RC extraction and independent paired source/post-layout simulation. Reference GDS, maintainer README and development sources are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml index 2d32e4d98d91db37dac21ac03d63ff1636bd7d37..64af6e23ba931c887dfe925c6b55bf697f5e6ae7 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml @@ -4,13 +4,6 @@ title = "Fer Two-Stage Miller Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "cf4e9870a1cc8dedb1ae661d3ef609bfd50b4ae17a62b9b92aed08ee4bebd12b" - [[assets]] path = "reference/amp_022_fer_two_stage.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "e14138167b8a248977bb8eecf3b3723f444aec1b6bf10372e80b6da8bfe7f2c9" +sha256 = "14b9e75b0f26e5a7c1799f7111752bcd07439df6c6e8d048e9be8a54ce33b0a4" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_022_fer_two_stage" -sha256 = "2376cfd1faf596940cbb75f9c842a71c603ab59107c0e88575b03a351e5550dc" +sha256 = "2a25c4caa82f7908ba955e77031391b2d2a98888c2a6f8e96643fc49802a0ab4" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "7faa764822a62fbfb24f91cf6b8ff300e9e0ac1c243e927713f8ff84bd9e17a9" +sha256 = "a43c293bbe4b69ebdd75a1fd656e3575ea1b88f7ab87640a79eb80bef12ca32b" [task.inputs.performance] path = "materials/testbench.spice" @@ -699,10 +692,10 @@ observations = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "a8ba629459cdd5996c2e8dc880b0392aa6d60c515a9dec11eb12fd627ee96421" +source_report_sha256 = "af1ca7c0fa3df8a3974daf59effcfd697476ec4e0bd59c6bd8b974f2a7655afa" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -743,69 +736,64 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "fa1586ca940d04a748a07be107907892cf57e1474aa8244a331cdd06da7708ea" -dut = "7faa764822a62fbfb24f91cf6b8ff300e9e0ac1c243e927713f8ff84bd9e17a9" +dut = "a43c293bbe4b69ebdd75a1fd656e3575ea1b88f7ab87640a79eb80bef12ca32b" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 0.3867579407410864 +value = 0.3867579407636933 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = -0.01778975 +value = -0.01778974 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] -value = 0.7988389269650475 +value = 0.798838928876953 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] -value = 1.958383542138842e-14 +value = 1.550273581382711e-15 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] -value = 0.001161073034947675 +value = 0.001161071123058072 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] -value = 0.5991740907845344 +value = 0.5991740925029558 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0003588599391214893 +value = 0.00035885990884722 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_max_v] -value = 0.80006486601298 +value = 0.8000643441053493 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_min_v] -value = 0.598200494414818 +value = 0.5982011498735788 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.5991740907847709 +value = 0.5991740925047854 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.000362342855808857 +value = 0.0003623428223256857 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 0.0008259092153180601 +value = 0.0008259074970558159 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_ripple_v] -value = 7.194334017412984e-11 +value = 2.019595601865376e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 2.14697148948062e-11 +value = 2.010946964503546e-11 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "ec8b41d41f48a532bb1eda312c723d4bad13b1282e05dc31e328bebc4ac1f6e9" -ac = "6873680836536aa4fdfdec0346bc6bb4ee133e04b6c734afadd98687bc2dc561" -transient = "4c074a2627dde98adb3f34603734d95a3651f2c38fb71d49bd90baa8ac480341" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -833,32 +821,28 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "dd9fa8ad91be9eefef87a58e0bd003930b65bd2ad3ebe04de8c2956a060bd633" -dut = "7faa764822a62fbfb24f91cf6b8ff300e9e0ac1c243e927713f8ff84bd9e17a9" +dut = "a43c293bbe4b69ebdd75a1fd656e3575ea1b88f7ab87640a79eb80bef12ca32b" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_feedback_error_v] value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] -value = 7.46190924089787e-12 +value = 7.461954258444414e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_10khz_db] -value = 51.36271 +value = 51.36272 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] -value = 51.50621 +value = 51.50622 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.kcl_a] -value = 1.094401804423162e-14 +value = 4.133927358415668e-15 unit = "A" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "738237c66cbd7a2bacb628cb41ba7c46fc08fe0d2ac00602e21fb9dbf31d9299" -ac = "bdcc6270e25b483560237d07022c0832ff77842b8cced25fa8ae8e67e9e03a93" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -898,7 +882,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl index 1d53e6156707a04f7c92d84504fb6fe0cac06739..44fb4c3e853d88395df071cf99a4231d0919c7e2 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl @@ -1,132 +1,15 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_022_fer_two_stage vdd vout vinp vinn ibias vss -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM0_0 a vinn c well_0 sg13_lv_pmos w=8u l=0.4u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM0_1 a vinn c well_1 sg13_lv_pmos w=8u l=0.4u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM0_2 a vinn c well_2 sg13_lv_pmos w=8u l=0.4u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM0_3 a vinn c well_3 sg13_lv_pmos w=8u l=0.4u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM0_4 a vinn c well_4 sg13_lv_pmos w=8u l=0.4u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM1_0 b vinp c well_5 sg13_lv_pmos w=8u l=0.4u m=1 -RT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -MM1_1 b vinp c well_6 sg13_lv_pmos w=8u l=0.4u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM1_2 b vinp c well_7 sg13_lv_pmos w=8u l=0.4u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM1_3 b vinp c well_8 sg13_lv_pmos w=8u l=0.4u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM1_4 b vinp c well_9 sg13_lv_pmos w=8u l=0.4u m=1 -RT10 vss sub ptap1 A=4e-12 P=8e-6 -MM2_0 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT11 vss sub ptap1 A=4e-12 P=8e-6 -MM2_1 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT12 vss sub ptap1 A=4e-12 P=8e-6 -MM2_2 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT13 vss sub ptap1 A=4e-12 P=8e-6 -MM2_3 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT14 vss sub ptap1 A=4e-12 P=8e-6 -MM2_4 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT15 vss sub ptap1 A=4e-12 P=8e-6 -MM2_5 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT16 vss sub ptap1 A=4e-12 P=8e-6 -MM2_6 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT17 vss sub ptap1 A=4e-12 P=8e-6 -MM2_7 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT18 vss sub ptap1 A=4e-12 P=8e-6 -MM2_8 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT19 vss sub ptap1 A=4e-12 P=8e-6 -MM2_9 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT20 vss sub ptap1 A=4e-12 P=8e-6 -MM2_10 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT21 vss sub ptap1 A=4e-12 P=8e-6 -MM2_11 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT22 vss sub ptap1 A=4e-12 P=8e-6 -MM2_12 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT23 vss sub ptap1 A=4e-12 P=8e-6 -MM2_13 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT24 vss sub ptap1 A=4e-12 P=8e-6 -MM2_14 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT25 vss sub ptap1 A=4e-12 P=8e-6 -MM2_15 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT26 vss sub ptap1 A=4e-12 P=8e-6 -MM2_16 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT27 vss sub ptap1 A=4e-12 P=8e-6 -MM2_17 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT28 vss sub ptap1 A=4e-12 P=8e-6 -MM2_18 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT29 vss sub ptap1 A=4e-12 P=8e-6 -MM2_19 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT30 vss sub ptap1 A=4e-12 P=8e-6 -MM2_20 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT31 vss sub ptap1 A=4e-12 P=8e-6 -MM2_21 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT32 vss sub ptap1 A=4e-12 P=8e-6 -MM2_22 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT33 vss sub ptap1 A=4e-12 P=8e-6 -MM2_23 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT34 vss sub ptap1 A=4e-12 P=8e-6 -MM3_0 a a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT35 vss sub ptap1 A=4e-12 P=8e-6 -MM3_1 a a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT36 vss sub ptap1 A=4e-12 P=8e-6 -MM4_0 b a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT37 vss sub ptap1 A=4e-12 P=8e-6 -MM4_1 b a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -RT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -MM5_0 c pbias vdd well_38 sg13_lv_pmos w=8u l=0.4u m=1 -RT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -MM5_1 c pbias vdd well_39 sg13_lv_pmos w=8u l=0.4u m=1 -RT40 vdd well_40 ntap1 A=4e-12 P=8e-6 -MM5_2 c pbias vdd well_40 sg13_lv_pmos w=8u l=0.4u m=1 -RT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -MM6_0 vout pbias vdd well_41 sg13_lv_pmos w=8u l=0.4u m=1 -RT42 vdd well_42 ntap1 A=4e-12 P=8e-6 -MM6_1 vout pbias vdd well_42 sg13_lv_pmos w=8u l=0.4u m=1 -RT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -MM6_2 vout pbias vdd well_43 sg13_lv_pmos w=8u l=0.4u m=1 -RT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -MM6_3 vout pbias vdd well_44 sg13_lv_pmos w=8u l=0.4u m=1 -RT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -MM6_4 vout pbias vdd well_45 sg13_lv_pmos w=8u l=0.4u m=1 -RT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -MM6_5 vout pbias vdd well_46 sg13_lv_pmos w=8u l=0.4u m=1 -RT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -MM6_6 vout pbias vdd well_47 sg13_lv_pmos w=8u l=0.4u m=1 -RT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -MM6_7 vout pbias vdd well_48 sg13_lv_pmos w=8u l=0.4u m=1 -RT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -MM6_8 vout pbias vdd well_49 sg13_lv_pmos w=8u l=0.4u m=1 -RT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -MM6_9 vout pbias vdd well_50 sg13_lv_pmos w=8u l=0.4u m=1 -RT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -MM6_10 vout pbias vdd well_51 sg13_lv_pmos w=8u l=0.4u m=1 -RT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -MM6_11 vout pbias vdd well_52 sg13_lv_pmos w=8u l=0.4u m=1 -RT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -MM6_12 vout pbias vdd well_53 sg13_lv_pmos w=8u l=0.4u m=1 -RT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -MM6_13 vout pbias vdd well_54 sg13_lv_pmos w=8u l=0.4u m=1 -RT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -MM6_14 vout pbias vdd well_55 sg13_lv_pmos w=8u l=0.4u m=1 -RT56 vdd well_56 ntap1 A=4e-12 P=8e-6 -MM6_15 vout pbias vdd well_56 sg13_lv_pmos w=8u l=0.4u m=1 -RT57 vdd well_57 ntap1 A=4e-12 P=8e-6 -MM6_16 vout pbias vdd well_57 sg13_lv_pmos w=8u l=0.4u m=1 -RT58 vdd well_58 ntap1 A=4e-12 P=8e-6 -MM7_0 pbias pbias vdd well_58 sg13_lv_pmos w=8u l=0.4u m=1 -RT59 vdd well_59 ntap1 A=4e-12 P=8e-6 -MM7_1 pbias pbias vdd well_59 sg13_lv_pmos w=8u l=0.4u m=1 -RT60 vdd well_60 ntap1 A=4e-12 P=8e-6 -MM7_2 pbias pbias vdd well_60 sg13_lv_pmos w=8u l=0.4u m=1 -RT61 vss sub ptap1 A=4e-12 P=8e-6 -MMBD ibias ibias vss sub sg13_lv_nmos w=4u l=0.4u m=1 -RT62 vss sub ptap1 A=4e-12 P=8e-6 -MMBS pbias ibias vss sub sg13_lv_nmos w=4u l=0.4u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM0 a vinn c vdd sg13_lv_pmos w=8u l=0.4u m=5 +MM1 b vinp c vdd sg13_lv_pmos w=8u l=0.4u m=5 +MM2 vout b vss vss sg13_lv_nmos w=6u l=0.4u m=24 +MM3 a a vss vss sg13_lv_nmos w=6u l=0.4u m=2 +MM4 b a vss vss sg13_lv_nmos w=6u l=0.4u m=2 +MM5 c pbias vdd vdd sg13_lv_pmos w=8u l=0.4u m=3 +MM6 vout pbias vdd vdd sg13_lv_pmos w=8u l=0.4u m=17 +MM7 pbias pbias vdd vdd sg13_lv_pmos w=8u l=0.4u m=3 +MMBD ibias ibias vss vss sg13_lv_nmos w=4u l=0.4u m=1 +MMBS pbias ibias vss vss sg13_lv_nmos w=4u l=0.4u m=1 CC_0 b vout cap_cmim w=36.46u l=36.46u m=1 .ends amp_022_fer_two_stage diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.spice index 1899d17b8d4cce2aa8ba90dbb296a3533cdedd59..8ee509d340f676807af63277caa8ef3c8ea4e61f 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.spice @@ -1,132 +1,15 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_022_fer_two_stage vdd vout vinp vinn ibias vss -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM0_0 a vinn c well_0 sg13_lv_pmos w=8u l=0.4u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM0_1 a vinn c well_1 sg13_lv_pmos w=8u l=0.4u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM0_2 a vinn c well_2 sg13_lv_pmos w=8u l=0.4u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM0_3 a vinn c well_3 sg13_lv_pmos w=8u l=0.4u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM0_4 a vinn c well_4 sg13_lv_pmos w=8u l=0.4u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM1_0 b vinp c well_5 sg13_lv_pmos w=8u l=0.4u m=1 -XT6 vdd well_6 ntap1 A=4e-12 P=8e-6 -XM1_1 b vinp c well_6 sg13_lv_pmos w=8u l=0.4u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM1_2 b vinp c well_7 sg13_lv_pmos w=8u l=0.4u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM1_3 b vinp c well_8 sg13_lv_pmos w=8u l=0.4u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM1_4 b vinp c well_9 sg13_lv_pmos w=8u l=0.4u m=1 -XT10 vss sub ptap1 A=4e-12 P=8e-6 -XM2_0 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT11 vss sub ptap1 A=4e-12 P=8e-6 -XM2_1 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT12 vss sub ptap1 A=4e-12 P=8e-6 -XM2_2 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT13 vss sub ptap1 A=4e-12 P=8e-6 -XM2_3 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT14 vss sub ptap1 A=4e-12 P=8e-6 -XM2_4 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT15 vss sub ptap1 A=4e-12 P=8e-6 -XM2_5 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT16 vss sub ptap1 A=4e-12 P=8e-6 -XM2_6 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT17 vss sub ptap1 A=4e-12 P=8e-6 -XM2_7 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT18 vss sub ptap1 A=4e-12 P=8e-6 -XM2_8 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT19 vss sub ptap1 A=4e-12 P=8e-6 -XM2_9 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT20 vss sub ptap1 A=4e-12 P=8e-6 -XM2_10 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT21 vss sub ptap1 A=4e-12 P=8e-6 -XM2_11 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT22 vss sub ptap1 A=4e-12 P=8e-6 -XM2_12 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT23 vss sub ptap1 A=4e-12 P=8e-6 -XM2_13 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT24 vss sub ptap1 A=4e-12 P=8e-6 -XM2_14 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT25 vss sub ptap1 A=4e-12 P=8e-6 -XM2_15 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT26 vss sub ptap1 A=4e-12 P=8e-6 -XM2_16 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT27 vss sub ptap1 A=4e-12 P=8e-6 -XM2_17 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT28 vss sub ptap1 A=4e-12 P=8e-6 -XM2_18 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT29 vss sub ptap1 A=4e-12 P=8e-6 -XM2_19 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT30 vss sub ptap1 A=4e-12 P=8e-6 -XM2_20 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT31 vss sub ptap1 A=4e-12 P=8e-6 -XM2_21 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT32 vss sub ptap1 A=4e-12 P=8e-6 -XM2_22 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT33 vss sub ptap1 A=4e-12 P=8e-6 -XM2_23 vout b vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT34 vss sub ptap1 A=4e-12 P=8e-6 -XM3_0 a a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT35 vss sub ptap1 A=4e-12 P=8e-6 -XM3_1 a a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT36 vss sub ptap1 A=4e-12 P=8e-6 -XM4_0 b a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT37 vss sub ptap1 A=4e-12 P=8e-6 -XM4_1 b a vss sub sg13_lv_nmos w=6u l=0.4u m=1 -XT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -XM5_0 c pbias vdd well_38 sg13_lv_pmos w=8u l=0.4u m=1 -XT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -XM5_1 c pbias vdd well_39 sg13_lv_pmos w=8u l=0.4u m=1 -XT40 vdd well_40 ntap1 A=4e-12 P=8e-6 -XM5_2 c pbias vdd well_40 sg13_lv_pmos w=8u l=0.4u m=1 -XT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -XM6_0 vout pbias vdd well_41 sg13_lv_pmos w=8u l=0.4u m=1 -XT42 vdd well_42 ntap1 A=4e-12 P=8e-6 -XM6_1 vout pbias vdd well_42 sg13_lv_pmos w=8u l=0.4u m=1 -XT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -XM6_2 vout pbias vdd well_43 sg13_lv_pmos w=8u l=0.4u m=1 -XT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -XM6_3 vout pbias vdd well_44 sg13_lv_pmos w=8u l=0.4u m=1 -XT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -XM6_4 vout pbias vdd well_45 sg13_lv_pmos w=8u l=0.4u m=1 -XT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -XM6_5 vout pbias vdd well_46 sg13_lv_pmos w=8u l=0.4u m=1 -XT47 vdd well_47 ntap1 A=4e-12 P=8e-6 -XM6_6 vout pbias vdd well_47 sg13_lv_pmos w=8u l=0.4u m=1 -XT48 vdd well_48 ntap1 A=4e-12 P=8e-6 -XM6_7 vout pbias vdd well_48 sg13_lv_pmos w=8u l=0.4u m=1 -XT49 vdd well_49 ntap1 A=4e-12 P=8e-6 -XM6_8 vout pbias vdd well_49 sg13_lv_pmos w=8u l=0.4u m=1 -XT50 vdd well_50 ntap1 A=4e-12 P=8e-6 -XM6_9 vout pbias vdd well_50 sg13_lv_pmos w=8u l=0.4u m=1 -XT51 vdd well_51 ntap1 A=4e-12 P=8e-6 -XM6_10 vout pbias vdd well_51 sg13_lv_pmos w=8u l=0.4u m=1 -XT52 vdd well_52 ntap1 A=4e-12 P=8e-6 -XM6_11 vout pbias vdd well_52 sg13_lv_pmos w=8u l=0.4u m=1 -XT53 vdd well_53 ntap1 A=4e-12 P=8e-6 -XM6_12 vout pbias vdd well_53 sg13_lv_pmos w=8u l=0.4u m=1 -XT54 vdd well_54 ntap1 A=4e-12 P=8e-6 -XM6_13 vout pbias vdd well_54 sg13_lv_pmos w=8u l=0.4u m=1 -XT55 vdd well_55 ntap1 A=4e-12 P=8e-6 -XM6_14 vout pbias vdd well_55 sg13_lv_pmos w=8u l=0.4u m=1 -XT56 vdd well_56 ntap1 A=4e-12 P=8e-6 -XM6_15 vout pbias vdd well_56 sg13_lv_pmos w=8u l=0.4u m=1 -XT57 vdd well_57 ntap1 A=4e-12 P=8e-6 -XM6_16 vout pbias vdd well_57 sg13_lv_pmos w=8u l=0.4u m=1 -XT58 vdd well_58 ntap1 A=4e-12 P=8e-6 -XM7_0 pbias pbias vdd well_58 sg13_lv_pmos w=8u l=0.4u m=1 -XT59 vdd well_59 ntap1 A=4e-12 P=8e-6 -XM7_1 pbias pbias vdd well_59 sg13_lv_pmos w=8u l=0.4u m=1 -XT60 vdd well_60 ntap1 A=4e-12 P=8e-6 -XM7_2 pbias pbias vdd well_60 sg13_lv_pmos w=8u l=0.4u m=1 -XT61 vss sub ptap1 A=4e-12 P=8e-6 -XMBD ibias ibias vss sub sg13_lv_nmos w=4u l=0.4u m=1 -XT62 vss sub ptap1 A=4e-12 P=8e-6 -XMBS pbias ibias vss sub sg13_lv_nmos w=4u l=0.4u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM0 a vinn c vdd sg13_lv_pmos w=8u l=0.4u m=5 +XM1 b vinp c vdd sg13_lv_pmos w=8u l=0.4u m=5 +XM2 vout b vss vss sg13_lv_nmos w=6u l=0.4u m=24 +XM3 a a vss vss sg13_lv_nmos w=6u l=0.4u m=2 +XM4 b a vss vss sg13_lv_nmos w=6u l=0.4u m=2 +XM5 c pbias vdd vdd sg13_lv_pmos w=8u l=0.4u m=3 +XM6 vout pbias vdd vdd sg13_lv_pmos w=8u l=0.4u m=17 +XM7 pbias pbias vdd vdd sg13_lv_pmos w=8u l=0.4u m=3 +XMBD ibias ibias vss vss sg13_lv_nmos w=4u l=0.4u m=1 +XMBS pbias ibias vss vss sg13_lv_nmos w=4u l=0.4u m=1 XCC_0 b vout cap_cmim w=36.46u l=36.46u m=1 .ends amp_022_fer_two_stage diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/schematic.svg deleted file mode 100644 index 5d2db7b8f94ed749026d2c7fde76fe30a4db48b2..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_022_fer_two_stage{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_022_fer_two_stage","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_022_fer_two_stage","MM0_bank1","MM1_bank2","MM2_bank3","MM6_bank4","XRT10_bank5"],"banks":[{"name":"MM0_bank1","devices":10,"source_references":["XRT0","MM0_0","XRT1","MM0_1","XRT2","MM0_2","XRT3","MM0_3","XRT4","MM0_4"]},{"name":"MM1_bank2","devices":10,"source_references":["XRT5","MM1_0","XRT6","MM1_1","XRT7","MM1_2","XRT8","MM1_3","XRT9","MM1_4"]},{"name":"MM2_bank3","devices":24,"source_references":["MM2_0","MM2_1","MM2_2","MM2_3","MM2_4","MM2_5","MM2_6","MM2_7","MM2_8","MM2_9","MM2_10","MM2_11","MM2_12","MM2_13","MM2_14","MM2_15","MM2_16","MM2_17","MM2_18","MM2_19","MM2_20","MM2_21","MM2_22","MM2_23"]},{"name":"MM6_bank4","devices":34,"source_references":["XRT41","MM6_0","XRT42","MM6_1","XRT43","MM6_2","XRT44","MM6_3","XRT45","MM6_4","XRT46","MM6_5","XRT47","MM6_6","XRT48","MM6_7","XRT49","MM6_8","XRT50","MM6_9","XRT51","MM6_10","XRT52","MM6_11","XRT53","MM6_12","XRT54","MM6_13","XRT55","MM6_14","XRT56","MM6_15","XRT57","MM6_16"]},{"name":"XRT10_bank5","devices":31,"source_references":["XRT10","XRT11","XRT12","XRT13","XRT14","XRT15","XRT16","XRT17","XRT18","XRT19","XRT20","XRT21","XRT22","XRT23","XRT24","XRT25","XRT26","XRT27","XRT28","XRT29","XRT30","XRT31","XRT32","XRT33","XRT34","XRT35","XRT36","XRT37","XRT61","XRT62","XRTSUB"]}],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_022_fer_two_stage"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/design/amp_022_fer_two_stage.icproj.json"}}Main-sheet overview; 5 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_022_fer_two_stagevsssubvddvinpcbvoutvssbsubvddvinnacvddvoutpbiascccsubsubsubsubsubsubsubsubvddwell_38cpbiasawell_39well_40well_58subwell_59well_60ibiasvoutvinnvinpbvssTwo-stage Miller OTAPMOS differential pair · NMOS mirror load · compensated common-source outputMM3_0MM3_1MM4_0MM4_1XRT38MM5_0XRT39MM5_1XRT40MM5_2XRT58MM7_0XRT59MM7_1XRT60MM7_2MMBDMMBSXCC_0XMM0_bank1XMM1_bank2XMM2_bank3XMM6_bank4XXRT10_bank5 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md index a612da092675724ae4d0bf7c5d8212cee478b851..d83faa443e09fa00e158fd25a5f164f0561c89dc 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md @@ -12,7 +12,7 @@ Implement `amp_022_fer_two_stage` as a GDS layout preserving the complete declar - `materials/ac.spice`: frequency observations. - `problem.md`: task description. -Ordered ports: `vdd vout vinp vinn ibias vss`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs. +Ordered ports: `vdd vout vinp vinn ibias vss`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. MOS groups retain their declared multiplicities; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs. ## Operating Conditions @@ -20,7 +20,7 @@ Ordered ports: `vdd vout vinp vinn ibias vss`. `vss` is ground, `vdd` the positi ## Physical Requirements -Use native IHP standalone-module DRC, named-port LVS and distributed Magic RC extraction. Source simulation retains finite native body-contact models; LVS checks physical contacts and bodies, while Magic idealizes well/substrate connections, omitting finite contact resistance and distributed substrate behavior. Functional area includes active/poly, passives and all metal/vias, excluding text and nonfunctional boundaries. No DRC waivers; topology, bodies and physical compensation are fixed, and equivalent geometry must preserve ports and device parameters. Maximum outline is 2000 × 1000 um, limiting module scope rather than electrical quality. +Use native IHP standalone-module DRC, named-port LVS and distributed Magic RC extraction. Source simulation uses the declared logical body connections. Functional area includes active/poly, passives and all metal/vias, excluding text and nonfunctional boundaries. No DRC waivers; topology, bodies and physical compensation are fixed, and equivalent geometry must preserve ports and device parameters. Maximum outline is 2000 × 1000 um, limiting module scope rather than electrical quality. ## Electrical Requirements and Scoring @@ -90,3 +90,5 @@ Solve budget: **8 hours**. Use the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `amp_022_fer_two_stage`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools. Both source and candidate extracted circuits require an absolute external DC current-conservation residual `kcl_a <= 1e-08 A`. Exceeding it terminates simulation with an evaluation error and an unknown score, rather than functional rejection. The residual is diagnostic and unscored. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml index c504b2d04a169be41fc7e994b3ac9f3a8dd1b2dc..1a89c794c4f97ff6a8fba9ecb36cb75fd70a4af1 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 19 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "81b2add1df46302fa2bb24bbcda161202e81a739f75d58ffea69791ed787594a" - [[assets]] path = "reference/amp_023_fer_fd2s.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/schematic.svg deleted file mode 100644 index 3fc392214171532f93815d777cc59f06d8bd9ad7..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_023_fer_fd2s{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_023_fer_fd2s","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_023_fer_fd2s","Bank1_8series_rhigh","Bank2_8series_rhigh"],"banks":[{"name":"Bank1_8series_rhigh","count":8,"model":"rhigh","kind":"series","members":["RRCA_0","RRCA_1","RRCA_2","RRCA_3","RRCA_4","RRCA_5","RRCA_6","RRCA_7"]},{"name":"Bank2_8series_rhigh","count":8,"model":"rhigh","kind":"series","members":["RRCB_0","RRCB_1","RRCB_2","RRCB_3","RRCB_4","RRCB_5","RRCB_6","RRCB_7"]}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":18},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_023_fer_fd2s"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/design/amp_023_fer_fd2s.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_023_fer_fd2svoutpvsensubvoutnvsensubfpfno1avcpo1bvcnx1ax1bvcmfbvsso1ao1bvoutpvbpvddvoutnvssvcmrvsenibiasvssvddvcmfbeataileadvcmfbvddvcpvcnvbpibiasvsso1ao1bvsenzazbvoutpvoutnvoutpvoutnvsensubsubvsssubvddwellvinpvinnibiasvssfpvbpvddfntailvinpvinnvoutpvoutnvddvssibiasvcmramp_023_fer_fd2sihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresFolded input stageMMSA6/0.4 ×2MMSB6/0.4 ×2MMI16/0.3 ×2MMI26/0.3 ×2MMT4/0.4 ×2P bulk → wellN bulk → subCascode branchesMMCA6/0.2MMCB6/0.2MMNA4/0.2MMNB4/0.2MMKA3/0.4MMKB3/0.4P bulk → wellN bulk → subDifferential output stageMMLA6/0.4 ×6MMLB6/0.4 ×6MM2A8/0.3 ×4MM2B8/0.3 ×4P bulk → wellN bulk → subCommon-mode error amplifierMMEPD3/0.4MMEPM3/0.4 ×2MMEA14/0.2MMEA24/0.2MMEAT4/0.4P bulk → wellN bulk → subBias generationMMPD16/0.4MMPD21.5/0.4MMPM16/0.4MMB14/0.4MMB24/0.4MMND10.75/0.4MMBD4/0.4MMNCD1.5/0.4P bulk → wellN bulk → subCompensation networkRRZA_01/0.96RRZB_01/0.96CCCA_025.9/25.9CCCB_025.9/25.9CCCA_125.9/25.9CCCB_125.9/25.9CCMA_09.95/9.95CCMB_09.95/9.95R substrate → subOutput common-mode sensingXBANK1Bank1_8series_rhighXBANK2Bank2_8series_rhighBulk ties and device banksRRptap1A=703 µm²RRntap1A=324 µm²Models: sg13_lv_nmos · sg13_lv_pmos · ptap1 · ntap1 · cap_cmim · rhigh - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml index 44e93508156ebe4758916d8d35d4e83856bdb4b1..e5d3ea4ec5ac4168b8e7b9e1de3daa5e2e379c5f 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml @@ -4,13 +4,6 @@ title = "Series-Nulling-Resistor Two-Stage OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "cae5c78098afdc05cfc96cdc3a0e820bf131a5c16b39a9f88f380f5a39d806c8" - [[assets]] path = "reference/amp_024_smcnr.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/materials/schematic.svg deleted file mode 100644 index 51ae503a92246cf9031ab67ae6a5aea67f7fefc8..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_024_smcnr{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_024_smcnr","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_024_smcnr"],"banks":[],"source_netlist":"design/circuit.cdl","svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_024_smcnr"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/design/amp_024_smcnr.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.amp_024_smcnroutnvddibiasvoutoutnrz1rz2rz3nzovsssubvddwelloutnvsstailpoutpvssvddvinnvinpvoutibiasamp_024_smcnrihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMM60.25/10 ×2MM07.5/8MM27.5/8MM11.5/10MM31.5/10P bulk → wellN bulk → subMM70.25/10MM50.25/10 ×10MM41.5/10 ×10P bulk → wellN bulk → subCC0_025.9/25.9CC0_125.9/25.9RRZ01/18RRZ11/18RRZ21/18RRZ31/18R substrate → subRRptap1A=850 µm²RRntap1A=472 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml index 0585ecb05efdf0fd15d8e5aa63dc4178d726c364..8f68fc5fbef5bd889d45cb9fbdef12dad7949a1e 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml @@ -4,13 +4,6 @@ title = "Fan Two-Stage OTA with Static Output Chopper" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "8ff76902dfaaed6f365d4336272e6f064b6bf58232b127b7080886bce21ce4cc" - [[assets]] path = "reference/amp_026_fan_chopper_ota.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "90ddb119bf484072a426a2635edb2cb0cd72828f0704e0b47861b7591a477845" +sha256 = "7108c9d1da647685b0464a5bd8eb47ca67ea8a69d758342b142525193f545a33" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_026_fan_chopper_ota" -sha256 = "232e765fe36c1fdd781bd26c556b0418f9bd53f3e39011fd244d67fd463e52c4" +sha256 = "e7f02597a0b80263ce7707ffcc520cd7cda3b89f5580fd1b7d5df215585b1158" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "1e37cd1ebd02de2445f3508e2a22652628babb729d747eebbcfbdd16817b8f4f" +sha256 = "3ad24015a858b686138732e0b7d6de9905a67ad66ae7658ed4691ea43cdc1f47" [task.inputs.performance] path = "materials/testbench.spice" @@ -737,10 +730,10 @@ observations = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "70a9d37d933deca9f9329dfed55ac2e19bce99012e861ed141b4bfd6e0ab7e4e" +source_report_sha256 = "c44dba90180b220410908f545c451632d90f5caa443e3fa810f9e85f37a556b0" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5d384a76e9c131bac2ca2ea8519a17d0769e9ef6e93bd9cad97f6294738568db\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -780,14 +773,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "b1d5cb0367382cf561131e06c2b217e9a91b32684bc9509bbd7a6ebb42b2c91e" -dut = "1e37cd1ebd02de2445f3508e2a22652628babb729d747eebbcfbdd16817b8f4f" +dut = "3ad24015a858b686138732e0b7d6de9905a67ad66ae7658ed4691ea43cdc1f47" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_before_v] -value = 0.5959001 +value = 0.5959 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_bias_v] -value = 0.5961939820830874 +value = 0.5961939876469189 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_kick_v] @@ -795,19 +788,19 @@ value = 0.007696899 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_max_v] -value = 0.603597 +value = 0.6035969 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_min_v] -value = 0.5955711 +value = 0.595571 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_recovery_v] -value = 0.001007352 +value = 0.001007441 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_bias_v] -value = 3.004263504635674e-13 +value = -2.29238850124602e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_100khz_db] @@ -819,22 +812,17 @@ value = 59.65068 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_100khz_deg] -value = -86.42558 +value = -86.42559 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0002689124640770754 +value = 0.000268912463946101 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_response_v] -value = 0.04994799000000024 +value = 0.04994799000016333 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "3db84de564702b44b52a43e16b1436136252f7272f88b02c1791d57232eeb372" -ac = "f2c1410d5ce25c78d0d39232cd8b6bd7b4d5981cd18bbeb35f816a8ae18b2d7a" -transient = "615714ecd58031e2e56e69f9c89d85ab4aeb067ec7609ca2cfd4f0c2f17d41d5" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -873,22 +861,22 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "b1d5cb0367382cf561131e06c2b217e9a91b32684bc9509bbd7a6ebb42b2c91e" -dut = "1e37cd1ebd02de2445f3508e2a22652628babb729d747eebbcfbdd16817b8f4f" +dut = "3ad24015a858b686138732e0b7d6de9905a67ad66ae7658ed4691ea43cdc1f47" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_before_v] value = 0.5959001 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_bias_v] -value = 0.5961939820830874 +value = 0.5961939876469189 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_kick_v] -value = 0.007696867 +value = 0.007696848 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_max_v] -value = 0.603597 +value = 0.6035969 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_min_v] @@ -896,11 +884,11 @@ value = 0.5955711 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_recovery_v] -value = 0.001007317 +value = 0.001007326 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_bias_v] -value = 3.004263504635674e-13 +value = -2.29238850124602e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_100khz_db] @@ -912,22 +900,17 @@ value = 59.65068 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_100khz_deg] -value = -86.42558 +value = -86.42559 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0002689124640770754 +value = 0.000268912463946101 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_response_v] -value = -0.0499479899999998 +value = -0.0499479899998367 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "3db84de564702b44b52a43e16b1436136252f7272f88b02c1791d57232eeb372" -ac = "f2c1410d5ce25c78d0d39232cd8b6bd7b4d5981cd18bbeb35f816a8ae18b2d7a" -transient = "3df137b3d5f6e6eede26ec7cae04e3f846f92094cf3a3201dfeadaae3eb01e28" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -966,34 +949,34 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "b1d5cb0367382cf561131e06c2b217e9a91b32684bc9509bbd7a6ebb42b2c91e" -dut = "1e37cd1ebd02de2445f3508e2a22652628babb729d747eebbcfbdd16817b8f4f" +dut = "3ad24015a858b686138732e0b7d6de9905a67ad66ae7658ed4691ea43cdc1f47" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_before_v] value = 0.5957633 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_bias_v] -value = 0.5961939820830874 +value = 0.5961939876469189 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_kick_v] -value = 0.007639619 +value = 0.007639673 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_max_v] -value = 0.6034029 +value = 0.603403 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_min_v] -value = 0.5949331 +value = 0.5949338 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_recovery_v] -value = 0.001119774 +value = 0.001119807 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dm_bias_v] -value = 3.004263504635674e-13 +value = -2.29238850124602e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_100khz_db] @@ -1005,22 +988,17 @@ value = 59.65068 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_100khz_deg] -value = -86.72871 +value = -86.72872 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 0.0002689124640770754 +value = 0.000268912463946101 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_response_v] -value = 0.04994799000000219 +value = 0.04994798999996786 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "3db84de564702b44b52a43e16b1436136252f7272f88b02c1791d57232eeb372" -ac = "d920bdd62b6e88311fed56d7a4709368e7ba954e53a80509be0d84152cc74c8c" -transient = "80a2901ab0e5c5df476bbb60442d13770ecdaa5fb9ed9e8844e544186be9eddf" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -1059,34 +1037,34 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "b1d5cb0367382cf561131e06c2b217e9a91b32684bc9509bbd7a6ebb42b2c91e" -dut = "1e37cd1ebd02de2445f3508e2a22652628babb729d747eebbcfbdd16817b8f4f" +dut = "3ad24015a858b686138732e0b7d6de9905a67ad66ae7658ed4691ea43cdc1f47" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_before_v] value = 0.5957633 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_bias_v] -value = 0.5961939820830874 +value = 0.5961939876469189 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_kick_v] -value = 0.007639669 +value = 0.007639593 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_max_v] -value = 0.603403 +value = 0.6034029 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_min_v] -value = 0.5949333 +value = 0.5949345 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_recovery_v] -value = 0.001119766 +value = 0.001119768 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dm_bias_v] -value = 3.004263504635674e-13 +value = -2.29238850124602e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain_100khz_db] @@ -1098,22 +1076,17 @@ value = 59.65068 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.phase_100khz_deg] -value = -86.72871 +value = -86.72872 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 0.0002689124640770754 +value = 0.000268912463946101 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_response_v] -value = -0.0499479899999978 +value = -0.0499479900000321 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "3db84de564702b44b52a43e16b1436136252f7272f88b02c1791d57232eeb372" -ac = "d920bdd62b6e88311fed56d7a4709368e7ba954e53a80509be0d84152cc74c8c" -transient = "2fb528752f2fffe23c8c2ea0ba9143cc5edeca031097c8eee082c52b7addbc86" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1153,7 +1126,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl index 07f3893e5a96ef54956bcf50b9552138ba5baca9..e71d9fc26709c5ec4fea8ec3e52df4cea47a46bb 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl @@ -1,55 +1,29 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_026_fan_chopper_ota vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM1 tail vb4 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM10 out1_n vb3 casc_src_n well_1 sg13_lv_pmos w=10u l=0.3u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM11 out1_p vb3 casc_src_p well_2 sg13_lv_pmos w=10u l=0.3u m=1 -RT3 vss sub ptap1 A=4e-12 P=8e-6 -MM12 out1_p vb2 fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -RT4 vss sub ptap1 A=4e-12 P=8e-6 -MM13 out1_n vb2 fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM14 voutp g2_p vss sub sg13_lv_nmos w=20u l=0.25u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM15 voutn g2_n vss sub sg13_lv_nmos w=20u l=0.25u m=1 -RT7 vss sub ptap1 A=4e-12 P=8e-6 -MM16 out1_n vdd g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM17 g2_n vss out1_n well_8 sg13_lv_pmos w=2u l=0.13u m=1 -RT9 vss sub ptap1 A=4e-12 P=8e-6 -MM18 out1_p vdd g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM19 g2_p vss out1_p well_10 sg13_lv_pmos w=2u l=0.13u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM2 fold_p vinp tail well_11 sg13_lv_pmos w=20u l=0.5u m=1 -RT12 vss sub ptap1 A=4e-12 P=8e-6 -MM20 out1_p vss g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM21 g2_n vdd out1_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -RT14 vss sub ptap1 A=4e-12 P=8e-6 -MM22 out1_n vss g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM23 g2_p vdd out1_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -RT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -MM3 fold_n vinn tail well_16 sg13_lv_pmos w=20u l=0.5u m=1 -RT17 vss sub ptap1 A=4e-12 P=8e-6 -MM4 fold_p vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -RT18 vss sub ptap1 A=4e-12 P=8e-6 -MM5 fold_n vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM6 casc_src_n vb4 vdd well_19 sg13_lv_pmos w=10u l=1u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM7 casc_src_p vb4 vdd well_20 sg13_lv_pmos w=10u l=1u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM8 voutp vb4 vdd well_21 sg13_lv_pmos w=20u l=1u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM9 voutn vb4 vdd well_22 sg13_lv_pmos w=20u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 -CM1_0 g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -CM1_1 g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -CM2_0 g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -CM2_1 g2_n voutn cap_cmim w=44.67u l=44.67u m=1 +MM1 tail vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM10 out1_n vb3 casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM11 out1_p vb3 casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM12 out1_p vb2 fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +MM13 out1_n vb2 fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +MM14 voutp g2_p vss vss sg13_lv_nmos w=20u l=0.25u m=1 +MM15 voutn g2_n vss vss sg13_lv_nmos w=20u l=0.25u m=1 +MM16 out1_n vdd g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM17 g2_n vss out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM18 out1_p vdd g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM19 g2_p vss out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM2 fold_p vinp tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM20 out1_p vss g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM21 g2_n vdd out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM22 out1_n vss g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM23 g2_p vdd out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM3 fold_n vinn tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM4 fold_p vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +MM5 fold_n vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +MM6 casc_src_n vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM7 casc_src_p vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM8 voutp vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM9 voutn vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +CM1_0 g2_p voutp cap_cmim w=44.67u l=44.67u m=2 +CM2_0 g2_n voutn cap_cmim w=44.67u l=44.67u m=2 .ends amp_026_fan_chopper_ota diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.spice index 934aff560a19de10bc9990564c567aa8d268e93d..772fb68016f7aed5af2cf3044b173d3116e0eea8 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.spice @@ -1,55 +1,29 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_026_fan_chopper_ota vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM1 tail vb4 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM10 out1_n vb3 casc_src_n well_1 sg13_lv_pmos w=10u l=0.3u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM11 out1_p vb3 casc_src_p well_2 sg13_lv_pmos w=10u l=0.3u m=1 -XT3 vss sub ptap1 A=4e-12 P=8e-6 -XM12 out1_p vb2 fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -XT4 vss sub ptap1 A=4e-12 P=8e-6 -XM13 out1_n vb2 fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM14 voutp g2_p vss sub sg13_lv_nmos w=20u l=0.25u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM15 voutn g2_n vss sub sg13_lv_nmos w=20u l=0.25u m=1 -XT7 vss sub ptap1 A=4e-12 P=8e-6 -XM16 out1_n vdd g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM17 g2_n vss out1_n well_8 sg13_lv_pmos w=2u l=0.13u m=1 -XT9 vss sub ptap1 A=4e-12 P=8e-6 -XM18 out1_p vdd g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM19 g2_p vss out1_p well_10 sg13_lv_pmos w=2u l=0.13u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM2 fold_p vinp tail well_11 sg13_lv_pmos w=20u l=0.5u m=1 -XT12 vss sub ptap1 A=4e-12 P=8e-6 -XM20 out1_p vss g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM21 g2_n vdd out1_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -XT14 vss sub ptap1 A=4e-12 P=8e-6 -XM22 out1_n vss g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM23 g2_p vdd out1_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -XT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -XM3 fold_n vinn tail well_16 sg13_lv_pmos w=20u l=0.5u m=1 -XT17 vss sub ptap1 A=4e-12 P=8e-6 -XM4 fold_p vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -XT18 vss sub ptap1 A=4e-12 P=8e-6 -XM5 fold_n vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM6 casc_src_n vb4 vdd well_19 sg13_lv_pmos w=10u l=1u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM7 casc_src_p vb4 vdd well_20 sg13_lv_pmos w=10u l=1u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM8 voutp vb4 vdd well_21 sg13_lv_pmos w=20u l=1u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM9 voutn vb4 vdd well_22 sg13_lv_pmos w=20u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 -XCM1_0 g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -XCM1_1 g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -XCM2_0 g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -XCM2_1 g2_n voutn cap_cmim w=44.67u l=44.67u m=1 +XM1 tail vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM10 out1_n vb3 casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM11 out1_p vb3 casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM12 out1_p vb2 fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +XM13 out1_n vb2 fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +XM14 voutp g2_p vss vss sg13_lv_nmos w=20u l=0.25u m=1 +XM15 voutn g2_n vss vss sg13_lv_nmos w=20u l=0.25u m=1 +XM16 out1_n vdd g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM17 g2_n vss out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM18 out1_p vdd g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM19 g2_p vss out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM2 fold_p vinp tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM20 out1_p vss g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM21 g2_n vdd out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM22 out1_n vss g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM23 g2_p vdd out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM3 fold_n vinn tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM4 fold_p vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +XM5 fold_n vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +XM6 casc_src_n vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM7 casc_src_p vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM8 voutp vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM9 voutn vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XCM1_0 g2_p voutp cap_cmim w=44.67u l=44.67u m=2 +XCM2_0 g2_n voutn cap_cmim w=44.67u l=44.67u m=2 .ends amp_026_fan_chopper_ota diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/schematic.svg deleted file mode 100644 index e4776b425a44197a1ab7075743081663ca1c3701..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_026_fan_chopper_ota{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_026_fan_chopper_ota","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_026_fan_chopper_ota","XRT3_bank1"],"banks":[{"name":"XRT3_bank1","devices":11,"source_references":["RT3","RT4","RT5","RT6","RT7","RT9","RT12","RT14","RT17","RT18","RTSUB"]}],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_026_fan_chopper_ota"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/design/amp_026_fan_chopper_ota.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_026_fan_chopper_otavsssubvinpvinntailfold_pfold_nvb2vb1vb4vb3vb4vddvddvddvb4vb4vb3vb3out1_nout1_pcasc_src_ncasc_src_pvb4vb3vb2vb1vb4vb4out1_pout1_nsubsubsubsubsubsubvsssubwell_0well_0vddwell_11well_11vddwell_16well_16vddwell_19well_19vddwell_20well_20vddwell_1well_1vddwell_2well_2vddwell_21well_21vddwell_22well_22vddwell_8well_8vddwell_10well_10vddwell_13well_13vddwell_15well_15vddvddvddvddvddout1_ng2_nvddsubvssout1_pg2_pvddsubvssout1_pg2_nvddsubvssout1_ng2_pvddsubvssvoutpvoutng2_pg2_pg2_ng2_nvddamp_026_fan_chopper_otaRT0A=4e-12 P=8e-6MM1w=20u l=1uRT1A=4e-12 P=8e-6MM10w=10u l=0.3uRT2A=4e-12 P=8e-6MM11w=10u l=0.3uMM12w=5u l=0.3uMM13w=5u l=0.3uMM14w=20u l=0.25uMM15w=20u l=0.25uMM16w=2u l=0.13uRT8A=4e-12 P=8e-6MM17w=2u l=0.13uMM18w=2u l=0.13uRT10A=4e-12 P=8e-6MM19w=2u l=0.13uRT11A=4e-12 P=8e-6MM2w=20u l=0.5uMM20w=2u l=0.13uRT13A=4e-12 P=8e-6MM21w=2u l=0.13uMM22w=2u l=0.13uRT15A=4e-12 P=8e-6MM23w=2u l=0.13uRT16A=4e-12 P=8e-6MM3w=20u l=0.5uMM4w=10u l=1uMM5w=10u l=1uRT19A=4e-12 P=8e-6MM6w=10u l=1uRT20A=4e-12 P=8e-6MM7w=10u l=1uRT21A=4e-12 P=8e-6MM8w=20u l=1uRT22A=4e-12 P=8e-6MM9w=20u l=1uCM1_0w=l=44.67uCM1_1w=l=44.67uCM2_0w=l=44.67uCM2_1w=l=44.67uXRT3_bank1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md index c973e07349435ed4ac6dd87681f7be0cc0fe30b3..edccaea2cb5573be03b042c96c5829dd933ae472 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md @@ -23,7 +23,7 @@ TT, 27 C, VDD=1.2 V, input common mode 0.6 V; vb1/vb2/vb3/vb4=0.3983759766/0.65/ Submit nonempty GDSII of at most 10485760 bytes. Pass native IHP DRC and strict named-interface LVS without waivers; preserve contact geometry and compact-device parameters. Functional devices, wells, contacts and routing layers define area, excluding annotations; bounds must fit within 5000 × 1000 um. -Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; source simulation retains finite contact models. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. +Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; Source simulation uses the declared logical body connections. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. The scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. @@ -31,7 +31,7 @@ The scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], All declared measurements must be finite and use the candidate extracted circuit. The deck observes gain/phase at 10 Hz/100 kHz, output bias, power, small differential steps and common-mode disturbance recovery. The step is response over 38–39 us minus baseline over 8–9 us; common-mode baseline is 58–59 us, peak 60–62 us and residual 98–99 us. Continuous quality is paired with independent source results under matching conditions. Nonnegative supply power and absolute error follow physical definitions, not upstream performance specifications. -Q is 14924.75 um2 divided by functional area. The anchor sums (W+2.4)(L+2.4) for each MOS and 3.2² um2 for each local tap and one global tap, adds four (44.67+2.4)² um2 MIM envelopes, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (50 mV scale), with common-mode kick/recovery retained as unscored diagnostics because this core has no common-mode regulator; bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 7 reflects multistage compensation and loaded differential response; common-mode drift and kick response remain observations, not proof of regulation. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system. +Q is 14924.75 um2 divided by functional area. The frozen anchor estimates (W+2.4)(L+2.4) per MOS unit and 3.2² um2 per reference local tap plus one global tap, adds four (44.67+2.4)² um2 MIM envelopes, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (50 mV scale), with common-mode kick/recovery retained as unscored diagnostics because this core has no common-mode regulator; bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 7 reflects multistage compensation and loaded differential response; common-mode drift and kick response remain observations, not proof of regulation. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system. Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result. @@ -83,3 +83,5 @@ Solve budget: **6 hours**. Use the reviewed IHP resources. Submit only the GDS with top cell amp_026_fan_chopper_ota. Evaluation runs native DRC/LVS, area, candidate-derived Magic RC extraction and ngspice post-layout observations. The source circuit is independently simulated for scoring. Discover the frozen task, resources and submission interface through `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`. Declared inputs are in `/task`. Write `/workspace/output/final.gds`, then run `python -I /protocol/submit.py` to submit explicitly; file generation alone is not submission. Feedback follows the capabilities provided by the current runtime protocol. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml index 6bfb4c68f5308d044c5f51bcdf14c972dfbc1b98..5a43874b8cee3154dbe9b82030e258fe09733820 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml @@ -4,13 +4,6 @@ title = "Fan Telescopic OTA with Transistor DDA-CMFB" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "7d5ee6b4a4575891cdb72e8667f027bbf472d42434600b419c3e9c686f4403f0" - [[assets]] path = "reference/amp_027_fan_rrl_ota.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "b441935176e7c5773342d5023b1db55f3f049fdd2169dccd52c5a6736bbe0c04" +sha256 = "6d38e295fcaff4886447d5ff1f548fb259175e59b4951410411509c7ad4cfce4" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_027_fan_rrl_ota" -sha256 = "afb6faf1d0f260f490f7bd748612c8d10ebbef233154362b853c867b9012b33e" +sha256 = "4bf3794124ddb9251f09ad02d608e6f4b15a5a4e57260a94676911b5904a9ddb" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "58a0cd7b6bcc782cc257925dd9cef3c9e6d0f4bcd810d33c529843ea0fa4a622" +sha256 = "246776344765a23cf7fd75de424a955089146fdc0569c26f63a85573c98eb2d0" [task.inputs.performance] path = "materials/testbench.spice" @@ -757,10 +750,10 @@ observations = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "8abe1520579486cd73add0e6b4ca1de773b92438d8e2a1387d64b9b94a5e0509" +source_report_sha256 = "875cdc466ada35dd8beda183268143ab75c19867d82c9225acc538cc25cfd84e" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5d384a76e9c131bac2ca2ea8519a17d0769e9ef6e93bd9cad97f6294738568db\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -800,14 +793,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "1942581a01fefbde8ea2c5f53eb7bb1184814f9f6e6aa85954cace0b2bc2181a" -dut = "58a0cd7b6bcc782cc257925dd9cef3c9e6d0f4bcd810d33c529843ea0fa4a622" +dut = "246776344765a23cf7fd75de424a955089146fdc0569c26f63a85573c98eb2d0" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_before_v] value = 0.4739868 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_bias_v] -value = 0.4739868306639629 +value = 0.4739868306821433 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_kick_v] @@ -823,15 +816,15 @@ value = 0.4739854 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_recovery_v] -value = 3.066743e-08 +value = 3.068407e-08 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_bias_v] -value = -1.2210255029288e-10 +value = -1.25405352768837e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_100khz_db] -value = 45.23201 +value = 45.23202 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_db] @@ -839,22 +832,17 @@ value = 46.60662 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_100khz_deg] -value = -31.40133 +value = -31.40125 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 7.707086122599944e-05 +value = 7.707086121310825e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.step_response_v] -value = 0.00427894007624212 +value = 0.0042789401341106 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "b44ee75f672a763d76513c1daa6bc3c98a8da3726e1bf95816f36732369fc1d6" -ac = "b060bf23b1cc59e184a10c00819be544010b4d24ebe2426e8f4ccd007109ac00" -transient = "e4522629f6fbafaa58d65a7d1df3768b2212e5a0fa0a1cfab63a13bb8d90298e" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -893,14 +881,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "1942581a01fefbde8ea2c5f53eb7bb1184814f9f6e6aa85954cace0b2bc2181a" -dut = "58a0cd7b6bcc782cc257925dd9cef3c9e6d0f4bcd810d33c529843ea0fa4a622" +dut = "246776344765a23cf7fd75de424a955089146fdc0569c26f63a85573c98eb2d0" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_before_v] value = 0.4739868 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_bias_v] -value = 0.4739868306639629 +value = 0.4739868306821433 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_kick_v] @@ -916,15 +904,15 @@ value = 0.4739854 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_recovery_v] -value = 3.066692e-08 +value = 3.068372e-08 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_bias_v] -value = -1.2210255029288e-10 +value = -1.25405352768837e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_100khz_db] -value = 45.23201 +value = 45.23202 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_db] @@ -932,22 +920,17 @@ value = 46.60662 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_100khz_deg] -value = -31.40133 +value = -31.40125 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 7.707086122599944e-05 +value = 7.707086121310825e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.step_response_v] -value = -0.00427893992375788 +value = -0.0042789398658894 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "b44ee75f672a763d76513c1daa6bc3c98a8da3726e1bf95816f36732369fc1d6" -ac = "b060bf23b1cc59e184a10c00819be544010b4d24ebe2426e8f4ccd007109ac00" -transient = "d4d6dc917f078483cb312b4072b9ac340a542465619da4ea5cf06c2b75c1657e" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -986,14 +969,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "1942581a01fefbde8ea2c5f53eb7bb1184814f9f6e6aa85954cace0b2bc2181a" -dut = "58a0cd7b6bcc782cc257925dd9cef3c9e6d0f4bcd810d33c529843ea0fa4a622" +dut = "246776344765a23cf7fd75de424a955089146fdc0569c26f63a85573c98eb2d0" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_before_v] value = 0.4739871 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_bias_v] -value = 0.4739868306639629 +value = 0.4739868306821433 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_kick_v] @@ -1009,11 +992,11 @@ value = 0.4739868 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.cm_recovery_v] -value = 2.692908e-07 +value = 2.692739e-07 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dm_bias_v] -value = -1.2210255029288e-10 +value = -1.25405352768837e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_100khz_db] @@ -1029,18 +1012,13 @@ value = -80.4361 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 7.707086122599944e-05 +value = 7.707086121310825e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_response_v] -value = 0.004070066131819199 +value = 0.0040700661264447 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "b44ee75f672a763d76513c1daa6bc3c98a8da3726e1bf95816f36732369fc1d6" -ac = "b8413cc57abf3d547471618767ea4b39124e94c6eed0cab30083c60f50691c15" -transient = "65776c23c24538c40de6c4bb83e1af0038e953c1d388ba57a49ac17fdbc2c641" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -1079,14 +1057,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "1942581a01fefbde8ea2c5f53eb7bb1184814f9f6e6aa85954cace0b2bc2181a" -dut = "58a0cd7b6bcc782cc257925dd9cef3c9e6d0f4bcd810d33c529843ea0fa4a622" +dut = "246776344765a23cf7fd75de424a955089146fdc0569c26f63a85573c98eb2d0" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_before_v] value = 0.4739871 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_bias_v] -value = 0.4739868306639629 +value = 0.4739868306821433 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_kick_v] @@ -1102,11 +1080,11 @@ value = 0.4739868 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.cm_recovery_v] -value = 2.692905e-07 +value = 2.692734e-07 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dm_bias_v] -value = -1.2210255029288e-10 +value = -1.25405352768837e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain_100khz_db] @@ -1122,18 +1100,13 @@ value = -80.4361 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 7.707086122599944e-05 +value = 7.707086121310825e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.step_response_v] -value = -0.0040700658681808 +value = -0.0040700658735553 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "b44ee75f672a763d76513c1daa6bc3c98a8da3726e1bf95816f36732369fc1d6" -ac = "b8413cc57abf3d547471618767ea4b39124e94c6eed0cab30083c60f50691c15" -transient = "4be96963da93a1b184bff87e499035f1e0f3df01728e120603b5660cfc9b3235" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1173,7 +1146,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl index a7208596c7073a640519df839db831b47282d858..26542f1da192df7b08c9e82cda437c168638ea33 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl @@ -1,37 +1,20 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_027_fan_rrl_ota vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4 -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM1 tail vb3 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM10 voutp vb1 d1p well_1 sg13_lv_pmos w=10u l=0.3u m=1 -RT2 vss sub ptap1 A=4e-12 P=8e-6 -MM11 voutn vb2 csrc_n sub sg13_lv_nmos w=5u l=0.3u m=1 -RT3 vss sub ptap1 A=4e-12 P=8e-6 -MM12 voutp vb2 csrc_p sub sg13_lv_nmos w=5u l=0.3u m=1 -RT4 vss sub ptap1 A=4e-12 P=8e-6 -MM13 csrc_n cm_bias vss sub sg13_lv_nmos w=6u l=1u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM14 csrc_p cm_bias vss sub sg13_lv_nmos w=6u l=1u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM15 cm_bias cm_bias vss sub sg13_lv_nmos w=2u l=1u m=1 -RT7 vss sub ptap1 A=4e-12 P=8e-6 -MM16 cm_sense cm_sense vss sub sg13_lv_nmos w=2u l=1u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM2 d1n vinp tail well_8 sg13_lv_pmos w=20u l=0.5u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM3 d1p vinn tail well_9 sg13_lv_pmos w=20u l=0.5u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM4 cm_tail vb3 vdd well_10 sg13_lv_pmos w=10u l=1u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM5 cm_sense voutn cm_tail well_11 sg13_lv_pmos w=4u l=0.5u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM6 cm_bias vb4 cm_tail well_12 sg13_lv_pmos w=4u l=0.5u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM7 cm_sense voutp cm_tail well_13 sg13_lv_pmos w=4u l=0.5u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM8 cm_bias vb4 cm_tail well_14 sg13_lv_pmos w=4u l=0.5u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM9 voutn vb1 d1n well_15 sg13_lv_pmos w=10u l=0.3u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM1 tail vb3 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM10 voutp vb1 d1p vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM11 voutn vb2 csrc_n vss sg13_lv_nmos w=5u l=0.3u m=1 +MM12 voutp vb2 csrc_p vss sg13_lv_nmos w=5u l=0.3u m=1 +MM13 csrc_n cm_bias vss vss sg13_lv_nmos w=6u l=1u m=1 +MM14 csrc_p cm_bias vss vss sg13_lv_nmos w=6u l=1u m=1 +MM15 cm_bias cm_bias vss vss sg13_lv_nmos w=2u l=1u m=1 +MM16 cm_sense cm_sense vss vss sg13_lv_nmos w=2u l=1u m=1 +MM2 d1n vinp tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM3 d1p vinn tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM4 cm_tail vb3 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM5 cm_sense voutn cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +MM6 cm_bias vb4 cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +MM7 cm_sense voutp cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +MM8 cm_bias vb4 cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +MM9 voutn vb1 d1n vdd sg13_lv_pmos w=10u l=0.3u m=1 .ends amp_027_fan_rrl_ota diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.spice index 2b6109119707278923999b2d6cb4d0eb715f51c2..a930ec2cefe84adad329f55a1e09eb66d501d3a6 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.spice @@ -1,37 +1,20 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_027_fan_rrl_ota vinp vinn voutp voutn vdd vss vb1 vb2 vb3 vb4 -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM1 tail vb3 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM10 voutp vb1 d1p well_1 sg13_lv_pmos w=10u l=0.3u m=1 -XT2 vss sub ptap1 A=4e-12 P=8e-6 -XM11 voutn vb2 csrc_n sub sg13_lv_nmos w=5u l=0.3u m=1 -XT3 vss sub ptap1 A=4e-12 P=8e-6 -XM12 voutp vb2 csrc_p sub sg13_lv_nmos w=5u l=0.3u m=1 -XT4 vss sub ptap1 A=4e-12 P=8e-6 -XM13 csrc_n cm_bias vss sub sg13_lv_nmos w=6u l=1u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM14 csrc_p cm_bias vss sub sg13_lv_nmos w=6u l=1u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM15 cm_bias cm_bias vss sub sg13_lv_nmos w=2u l=1u m=1 -XT7 vss sub ptap1 A=4e-12 P=8e-6 -XM16 cm_sense cm_sense vss sub sg13_lv_nmos w=2u l=1u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM2 d1n vinp tail well_8 sg13_lv_pmos w=20u l=0.5u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM3 d1p vinn tail well_9 sg13_lv_pmos w=20u l=0.5u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM4 cm_tail vb3 vdd well_10 sg13_lv_pmos w=10u l=1u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM5 cm_sense voutn cm_tail well_11 sg13_lv_pmos w=4u l=0.5u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM6 cm_bias vb4 cm_tail well_12 sg13_lv_pmos w=4u l=0.5u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM7 cm_sense voutp cm_tail well_13 sg13_lv_pmos w=4u l=0.5u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM8 cm_bias vb4 cm_tail well_14 sg13_lv_pmos w=4u l=0.5u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM9 voutn vb1 d1n well_15 sg13_lv_pmos w=10u l=0.3u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM1 tail vb3 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM10 voutp vb1 d1p vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM11 voutn vb2 csrc_n vss sg13_lv_nmos w=5u l=0.3u m=1 +XM12 voutp vb2 csrc_p vss sg13_lv_nmos w=5u l=0.3u m=1 +XM13 csrc_n cm_bias vss vss sg13_lv_nmos w=6u l=1u m=1 +XM14 csrc_p cm_bias vss vss sg13_lv_nmos w=6u l=1u m=1 +XM15 cm_bias cm_bias vss vss sg13_lv_nmos w=2u l=1u m=1 +XM16 cm_sense cm_sense vss vss sg13_lv_nmos w=2u l=1u m=1 +XM2 d1n vinp tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM3 d1p vinn tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM4 cm_tail vb3 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM5 cm_sense voutn cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +XM6 cm_bias vb4 cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +XM7 cm_sense voutp cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +XM8 cm_bias vb4 cm_tail vdd sg13_lv_pmos w=4u l=0.5u m=1 +XM9 voutn vb1 d1n vdd sg13_lv_pmos w=10u l=0.3u m=1 .ends amp_027_fan_rrl_ota diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/schematic.svg deleted file mode 100644 index e9f008bb4bd9928ed26aee2f2e14408261c96804..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_027_fan_rrl_ota{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_027_fan_rrl_ota","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_027_fan_rrl_ota","XRT2_bank1"],"banks":[{"name":"XRT2_bank1","devices":7,"source_references":["RT2","RT3","RT4","RT5","RT6","RT7","RTSUB"]}],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_027_fan_rrl_ota"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/design/amp_027_fan_rrl_ota.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_027_fan_rrl_otavsssubvb2csrc_pwell_0vsscm_biascm_biascm_biascm_sensevddvddwell_8vinpd1nvddwell_9vb3vinnvddwell_10vddvb3cm_tailvddwell_11tailvddwell_12vb4vddwell_13vddvddwell_14vb4vddwell_15well_1vb1voutpvb1d1pvddvoutnvb2subcsrc_nvoutnvoutpamp_027_fan_rrl_otaRT0ntap1A=4e-12 P=8e-6MM1sg13_lv_pmosw=20u l=1um=1RT1ntap1A=4e-12 P=8e-6MM10sg13_lv_pmosw=10u l=0.3um=1MM11sg13_lv_nmosw=5u l=0.3um=1MM12sg13_lv_nmosw=5u l=0.3um=1MM13sg13_lv_nmosw=6u l=1um=1MM14sg13_lv_nmosw=6u l=1um=1MM15sg13_lv_nmosw=2u l=1um=1MM16sg13_lv_nmosw=2u l=1um=1RT8ntap1A=4e-12 P=8e-6MM2sg13_lv_pmosw=20u l=0.5um=1RT9ntap1A=4e-12 P=8e-6MM3sg13_lv_pmosw=20u l=0.5um=1RT10ntap1A=4e-12 P=8e-6MM4sg13_lv_pmosw=10u l=1um=1RT11ntap1A=4e-12 P=8e-6MM5sg13_lv_pmosw=4u l=0.5um=1RT12ntap1A=4e-12 P=8e-6MM6sg13_lv_pmosw=4u l=0.5um=1RT13ntap1A=4e-12 P=8e-6MM7sg13_lv_pmosw=4u l=0.5um=1RT14ntap1A=4e-12 P=8e-6MM8sg13_lv_pmosw=4u l=0.5um=1RT15ntap1A=4e-12 P=8e-6MM9sg13_lv_pmosw=10u l=0.3um=1XXRT2_bank1XRT2_bank1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md index dcab930d9be1523e12ca9b3c75f968255bd61f7d..e50c690252a42d4daa708d28903bb0ad141639f1 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md @@ -23,7 +23,7 @@ TT, 27 C, VDD=1.2 V, input common mode 0.6 V; vb1/vb2/vb3/vb4=0.45/0.75/0.55/0.6 Submit nonempty GDSII of at most 10485760 bytes. Pass native IHP DRC and strict named-interface LVS without waivers; preserve contact geometry and compact-device parameters. Functional devices, wells, contacts and routing layers define area, excluding annotations; bounds must fit within 5000 × 1000 um. -Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; source simulation retains finite contact models. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. +Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; Source simulation uses the declared logical body connections. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. The scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. @@ -31,7 +31,7 @@ The scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], All declared measurements must be finite and use the candidate extracted circuit. The deck observes gain/phase at 10 Hz/100 kHz, output bias, power, small differential steps and common-mode disturbance recovery. The step is response over 38–39 us minus baseline over 8–9 us; common-mode baseline is 58–59 us, peak 60–62 us and residual 98–99 us. Continuous quality is paired with independent source results under matching conditions. Nonnegative supply power and absolute error follow physical definitions, not upstream performance specifications. -Q is 1035.78 um2 divided by functional area. The anchor sums (W+2.4)(L+2.4) for each MOS and 3.2² um2 for each local tap and one global tap, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (1 mV scale), and inverse absolute common-mode error (1 uV floor); bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 6 reflects the complete signal amplifier coupled to a transistor common-mode recovery loop. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system. +Q is 1035.78 um2 divided by functional area. The frozen anchor estimates (W+2.4)(L+2.4) per MOS unit and 3.2² um2 per reference local tap plus one global tap, then applies a 50% routing allowance. It is an engineering estimate, not a foundry minimum. Response metrics use source-paired dB gain, target phase (180 degree scale), target step (1 mV scale), and inverse absolute common-mode error (1 uV floor); bias uses a 1.2 V target scale; power uses an inverse ratio with 1 pW floor. Coefficient 6 reflects the complete signal amplifier coupled to a transistor common-mode recovery loop. Qualification does not require matching paper performance and does not cover PVT, noise, mismatch or an RRL system. Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result. @@ -87,3 +87,5 @@ Solve budget: **6 hours**. Use the reviewed IHP resources. Submit only the GDS with top cell amp_027_fan_rrl_ota. Evaluation runs native DRC/LVS, area, candidate-derived Magic RC extraction and ngspice post-layout observations. The source circuit is independently simulated for scoring. Discover the frozen task, resources and submission interface through `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`. Declared inputs are in `/task`. Write `/workspace/output/final.gds`, then run `python -I /protocol/submit.py` to submit explicitly; file generation alone is not submission. Feedback follows the capabilities provided by the current runtime protocol. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml index ca716356b344f8e68991d8e01aaca2f369cfad83..bdb8237955e725ba694c86624b120c5e28e33ecd 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml @@ -4,13 +4,6 @@ title = "Differential Two-Stage Miller Amplifier Without CMFB" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "42ec59386f3b24e7bf0f8bc92aa16ca1cb13e64dbd2e10737d91d113cb2c48a1" - [[assets]] path = "reference/amp_029_two_stage_miller_comp.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "29bc92aaa242d877a047a46ead56aaca9fa28fb4eca8363e7ed087bf923a3a8f" +sha256 = "d45d82891b16ec523b1aac4cab4633fea116db9910d121f05e1bf0113867d04f" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_029_two_stage_miller_comp" -sha256 = "7f89e7956013c5963092250563b16713f48f9a31dd350503d0e5fb7d7d408923" +sha256 = "c8709463f9bc4f0c0d858b246823449bf36470ad5e9fe9e067f3557936ef02cd" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "d7e4a50a7bad688a0431cc3610314166e7aace23f1bf9b7d822779a0fea9aea1" +sha256 = "dedb95f8c4d70f2c600d80e317b53865954206f4de82e363e261016445947fee" [task.inputs.performance] path = "materials/testbench.spice" @@ -618,10 +611,10 @@ observations = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "dae08be71190ec38e9bfd1dbe8a4088ede94a274c16cc92f784375c396ee6508" +source_report_sha256 = "caf0c4a3914688914ca4608bd2f29ff1d89e84e8e2e7a6f63b003399ebc74f61" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -655,14 +648,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "9830791d6e155fb24767e2be07ffd0e21eefd446a5145a4360cf0784d57d7c46" -dut = "d7e4a50a7bad688a0431cc3610314166e7aace23f1bf9b7d822779a0fea9aea1" +dut = "dedb95f8c4d70f2c600d80e317b53865954206f4de82e363e261016445947fee" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_max_v] -value = 0.5383859 +value = 0.538386 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_min_v] -value = 0.5383812 +value = 0.5383813 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.high_v] @@ -670,7 +663,7 @@ value = 0.009970116 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] -value = 8.315017511334455e-16 +value = 5.865262702603458e-16 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.late_error_v] @@ -678,33 +671,29 @@ value = 2.988441e-05 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.low_v] -value = -8.658507e-13 +value = -2.194012e-14 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.offset_v] -value = 2.315925229368077e-12 +value = 1.84297022087776e-13 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_cm_v] -value = 0.5383812217609086 +value = 0.5383813205289394 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0002154386891195785 +value = 0.0002154386932506705 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_error_v] -value = 9.457481e-13 +value = 5.105827e-13 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 1.22049e-11 +value = 8.853807e-12 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "0c96fedee8d9d8e927beb8641e3eba427a914789a01ef38ca0e029819fa366d0" -transient = "8212708c3db66380f8c95a7a948d43ccefeff0fad044d43589f765ebb63c3be6" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -733,7 +722,7 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "3f317035de9a6d81fd41593f17828a4c860e8cddfcd8f5b7d3ee78fa975494e9" -dut = "d7e4a50a7bad688a0431cc3610314166e7aace23f1bf9b7d822779a0fea9aea1" +dut = "dedb95f8c4d70f2c600d80e317b53865954206f4de82e363e261016445947fee" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.fixture_cm_max] value = 3.061616997868383e-17 @@ -748,25 +737,21 @@ value = 50.46528 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.kcl_a] -value = 9.412501160432907e-16 +value = 9.730714498057402e-16 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.offset_v] -value = -3.47988304838509e-11 +value = -7.39963645912667e-13 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_cm_v] -value = 0.5383812226821068 +value = 0.5383813155471775 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0002154386891591478 +value = 0.0002154386930418077 unit = "W" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "e705ecaa4295ad8c9666c328c5ba195345ecf7afdcc837d39eb5e37474ae5cba" -ac = "acc482d9e9783224d79f534619fe17743eca59a69e69c52d4aa791e82e1bb561" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -806,7 +791,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl index a49f817cf205b96cbfeb425ecab3d66ca9b8ef80..bad0880e3f408e0d624350b1681808af80ab6946 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl @@ -1,29 +1,18 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_029_two_stage_miller_comp vinp vinn voutp voutn vdd vss ref vbl -RT0 vss sub ptap1 A=4e-12 P=8e-6 -MM1 stg1p vinp tail sub sg13_lv_nmos w=10u l=0.5u m=1 -RT1 vss sub ptap1 A=4e-12 P=8e-6 -MM10 voutn ref vss sub sg13_lv_nmos w=6u l=1u m=1 -RT2 vss sub ptap1 A=4e-12 P=8e-6 -MM2 stg1n vinn tail sub sg13_lv_nmos w=10u l=0.5u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM3 stg1p vbl vdd well_3 sg13_lv_pmos w=10u l=1u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM4 stg1n vbl vdd well_4 sg13_lv_pmos w=10u l=1u m=1 -RT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -MM5 voutp stg1p vdd well_5 sg13_lv_pmos w=12u l=0.5u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM6 ref ref vss sub sg13_lv_nmos w=2u l=1u m=1 -RT7 vss sub ptap1 A=4e-12 P=8e-6 -MM7 voutp ref vss sub sg13_lv_nmos w=6u l=1u m=1 -RT8 vss sub ptap1 A=4e-12 P=8e-6 -MM8 tail ref vss sub sg13_lv_nmos w=2u l=1u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM9 voutn stg1n vdd well_9 sg13_lv_pmos w=12u l=0.5u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM1 stg1p vinp tail vss sg13_lv_nmos w=10u l=0.5u m=1 +MM10 voutn ref vss vss sg13_lv_nmos w=6u l=1u m=1 +MM2 stg1n vinn tail vss sg13_lv_nmos w=10u l=0.5u m=1 +MM3 stg1p vbl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM4 stg1n vbl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM5 voutp stg1p vdd vdd sg13_lv_pmos w=12u l=0.5u m=1 +MM6 ref ref vss vss sg13_lv_nmos w=2u l=1u m=1 +MM7 voutp ref vss vss sg13_lv_nmos w=6u l=1u m=1 +MM8 tail ref vss vss sg13_lv_nmos w=2u l=1u m=1 +MM9 voutn stg1n vdd vdd sg13_lv_pmos w=12u l=0.5u m=1 C1_0 mill_p voutp cap_cmim w=16.28u l=16.28u m=1 C2_0 mill_n voutn cap_cmim w=16.28u l=16.28u m=1 -RR1_0 stg1p mill_p sub rhigh w=.5u l=10.04u m=1 b=0 -RR2_0 stg1n mill_n sub rhigh w=.5u l=10.04u m=1 b=0 +RR1_0 stg1p mill_p vss rhigh w=.5u l=10.04u m=1 b=0 +RR2_0 stg1n mill_n vss rhigh w=.5u l=10.04u m=1 b=0 .ends amp_029_two_stage_miller_comp diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.spice index b3ec961c6700ed23eb401deeb8fb7a48ff08d4d9..65625b406da1fa7c8ad32ea1531bd89be829acd0 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.spice @@ -1,29 +1,18 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_029_two_stage_miller_comp vinp vinn voutp voutn vdd vss ref vbl -XT0 vss sub ptap1 A=4e-12 P=8e-6 -XM1 stg1p vinp tail sub sg13_lv_nmos w=10u l=0.5u m=1 -XT1 vss sub ptap1 A=4e-12 P=8e-6 -XM10 voutn ref vss sub sg13_lv_nmos w=6u l=1u m=1 -XT2 vss sub ptap1 A=4e-12 P=8e-6 -XM2 stg1n vinn tail sub sg13_lv_nmos w=10u l=0.5u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM3 stg1p vbl vdd well_3 sg13_lv_pmos w=10u l=1u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM4 stg1n vbl vdd well_4 sg13_lv_pmos w=10u l=1u m=1 -XT5 vdd well_5 ntap1 A=4e-12 P=8e-6 -XM5 voutp stg1p vdd well_5 sg13_lv_pmos w=12u l=0.5u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM6 ref ref vss sub sg13_lv_nmos w=2u l=1u m=1 -XT7 vss sub ptap1 A=4e-12 P=8e-6 -XM7 voutp ref vss sub sg13_lv_nmos w=6u l=1u m=1 -XT8 vss sub ptap1 A=4e-12 P=8e-6 -XM8 tail ref vss sub sg13_lv_nmos w=2u l=1u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM9 voutn stg1n vdd well_9 sg13_lv_pmos w=12u l=0.5u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM1 stg1p vinp tail vss sg13_lv_nmos w=10u l=0.5u m=1 +XM10 voutn ref vss vss sg13_lv_nmos w=6u l=1u m=1 +XM2 stg1n vinn tail vss sg13_lv_nmos w=10u l=0.5u m=1 +XM3 stg1p vbl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM4 stg1n vbl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM5 voutp stg1p vdd vdd sg13_lv_pmos w=12u l=0.5u m=1 +XM6 ref ref vss vss sg13_lv_nmos w=2u l=1u m=1 +XM7 voutp ref vss vss sg13_lv_nmos w=6u l=1u m=1 +XM8 tail ref vss vss sg13_lv_nmos w=2u l=1u m=1 +XM9 voutn stg1n vdd vdd sg13_lv_pmos w=12u l=0.5u m=1 XC1_0 mill_p voutp cap_cmim w=16.28u l=16.28u m=1 XC2_0 mill_n voutn cap_cmim w=16.28u l=16.28u m=1 -XR1_0 stg1p mill_p sub rhigh w=.5u l=10.04u m=1 b=0 -XR2_0 stg1n mill_n sub rhigh w=.5u l=10.04u m=1 b=0 +XR1_0 stg1p mill_p vss rhigh w=.5u l=10.04u m=1 b=0 +XR2_0 stg1n mill_n vss rhigh w=.5u l=10.04u m=1 b=0 .ends amp_029_two_stage_miller_comp diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/schematic.svg deleted file mode 100644 index 46a545f44e0a81265eed1e060806ca132099eb0d..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_029_two_stage_miller_comp{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_029_two_stage_miller_comp","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_029_two_stage_miller_comp","XRT0_bank1"],"banks":[{"name":"XRT0_bank1","devices":7,"source_references":["RT0","RT1","RT2","RT6","RT7","RT8","RTSUB"]}],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_029_two_stage_miller_comp"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/design/amp_029_two_stage_miller_comp.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_029_two_stage_miller_compvsssubwell_3vddwell_4vblsubwell_4vddwell_5well_5stg1pvsssubrefsubtailvssrefsubvddwell_9well_9mill_pmill_nvsssubvinpvinnvoutpvoutnvddvssrefvblrefsubsubstg1nvddwell_3amp_029_two_stage_miller_compMM1sg13_lv_nmosw=10u l=0.5um=1MM10sg13_lv_nmosw=6u l=1um=1MM2sg13_lv_nmosw=10u l=0.5um=1RT3ntap1A=4e-12 P=8e-6MM3sg13_lv_pmosw=10u l=1um=1RT4ntap1A=4e-12 P=8e-6MM4sg13_lv_pmosw=10u l=1um=1RT5ntap1A=4e-12 P=8e-6MM5sg13_lv_pmosw=12u l=0.5um=1MM6sg13_lv_nmosw=2u l=1um=1MM7sg13_lv_nmosw=6u l=1um=1MM8sg13_lv_nmosw=2u l=1um=1RT9ntap1A=4e-12 P=8e-6MM9sg13_lv_pmosw=12u l=0.5um=1C1_0cap_cmimw=16.28u l=16.28um=1C2_0cap_cmimw=16.28u l=16.28um=1RR1_0rhighw=.5u l=10.04um=1 b=0RR2_0rhighw=.5u l=10.04um=1 b=0XXRT0_bank1XRT0_bank1Substrate: B=sub - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md index 54eb749a5a2752b9b02b00dd51ca3773f0a9043c..6ef0043b859f3d6912c11999e1d08612eda5efc0 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md @@ -12,7 +12,7 @@ Implement `amp_029_two_stage_miller_comp` as a GDS layout preserving the complet - `materials/ac.spice`: frequency observations. - `problem.md`: task description. -Ordered ports: `vinp vinn voutp voutn vdd vss ref vbl`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. Device multipliers are explicitly expanded; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs. +Ordered ports: `vinp vinn voutp voutn vdd vss ref vbl`. `vss` is ground, `vdd` the positive rail; signal/output and bias/reference ports have the functions and directions specified below. Every named interface must be preserved. MOS groups retain their declared multiplicities; series/parallel passive realizations are already declared in the circuit. The reference layout and development source are not solver inputs. ## Operating Conditions @@ -20,7 +20,7 @@ Ordered ports: `vinp vinn voutp voutn vdd vss ref vbl`. `vss` is ground, `vdd` t ## Physical Requirements -Use native IHP standalone-module DRC, named-port LVS and distributed Magic RC extraction. Source simulation retains finite native body-contact models; LVS checks physical contacts and bodies, while Magic idealizes well/substrate connections, omitting finite contact resistance and distributed substrate behavior. Functional area includes active/poly, passives and all metal/vias, excluding text and nonfunctional boundaries. No DRC waivers; topology, bodies and physical compensation are fixed, and equivalent geometry must preserve ports and device parameters. Maximum outline is 2000 × 1000 um, limiting module scope rather than electrical quality. +Use native IHP standalone-module DRC, named-port LVS and distributed Magic RC extraction. Source simulation uses the declared logical body connections. Functional area includes active/poly, passives and all metal/vias, excluding text and nonfunctional boundaries. No DRC waivers; topology, bodies and physical compensation are fixed, and equivalent geometry must preserve ports and device parameters. Maximum outline is 2000 × 1000 um, limiting module scope rather than electrical quality. ## Electrical Requirements and Scoring @@ -84,3 +84,5 @@ Solve budget: **8 hours**. Use the runtime task/resource discovery interface for the frozen tool image, PDK and declared feedback operations. The evaluator checks the submitted GDS independently and extracts its parasitics. Submit `output/final.gds`, top cell `amp_029_two_stage_miller_comp`; do not submit a source netlist in place of a layout. Keep all named ports. The resource bundle contains the approved open PDK and native EDA tools. Both source and candidate extracted circuits require an absolute external DC current-conservation residual `kcl_a <= 1e-08 A`. Exceeding it terminates simulation with an evaluation error and an unknown score, rather than functional rejection. The residual is diagnostic and unscored. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml index 0b3a09d00fa9e765860f5b442302ff90d273ac67..5fd29c4f7a4785ddc69d4661c0ed4b14b14ec973 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml @@ -4,13 +4,6 @@ title = "Fan Output CMFB OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "03fac254ebcaec6a88a1aea3475c19610997f2842b13b00226c74661ddaf15fa" - [[assets]] path = "reference/amp_034_fan_chopper_cmfb.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "88b76a53ab8bf9e6cb9c2f44dec6fe5c57913fa68a418642724f9a0dfa69e004" +sha256 = "7dae7c766bf8119bf3e23cfff401b92042dc5f62c32191615f4d5879f8001935" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_034_fan_chopper_cmfb" -sha256 = "1898e7ade5f22a3a7785fcc52bb04bce6a9405a9b63a01f0b01da6ad316e00a3" +sha256 = "dcbb83aa8b8f5e038343c1bc8a52e4882169995747e809442136379ba0f33896" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "cda4a2fe217a444033868a7c36a0ab0e0644f2a18ebaabd963bce758fc0ccefb" +sha256 = "c85b096e1dc61f51e9458d8534ae95db7a144ca0ccea8018d37e42612ee4758f" [task.inputs.performance] path = "materials/testbench.spice" @@ -1187,10 +1180,10 @@ upper = 1e-06 rationale = "The external differential measurement loop must enforce its declared DC excitation within 1 uV; otherwise the observation uses an invalid fixture operating point." [task.evaluation.pre_layout] -source_report_sha256 = "39f60e11671104a77869414b7464bc89a055cb082b370cf910e8bee83d3eaeb1" +source_report_sha256 = "ed69654b6a7281f6e7e7a2975584bcc481790b715a154a7a1f7ed56a47817d24" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 1800.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 1800.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1251,133 +1244,128 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "53b7fd97e1fce73ec5827052a6a33416a10b9920d7046da23c5a45814ed67d4a" -dut = "cda4a2fe217a444033868a7c36a0ab0e0644f2a18ebaabd963bce758fc0ccefb" +dut = "c85b096e1dc61f51e9458d8534ae95db7a144ca0ccea8018d37e42612ee4758f" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] -value = -0.009874496 +value = -0.009874488 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_bias_v] -value = 0.5145191412199209 +value = 0.5145191341527368 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_input_cm_v] -value = 0.5145191413910424 +value = 0.5145191340944498 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_kick_v] -value = 2.581282965152809e-10 +value = 8.840261855880271e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_late_pp_v] -value = 2.783639985182162e-11 +value = 6.517342221457056e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_late_v] -value = 0.5145191413913373 +value = 0.5145191340931624 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_pre_kick_v] -value = 0.5145191413901259 +value = 0.514519134089349 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_quiet_pp_v] -value = 2.668398835226071e-11 +value = 5.809597247719012e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_quiet_v] -value = 0.5145191413919855 +value = 0.5145191340935519 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_recovery_error_v] -value = 3.925782407508563e-12 +value = 5.535332622808595e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_recovery_v] -value = 0.5145191413922028 +value = 0.514519134092804 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_ref_v] -value = 0.5145191413913728 +value = 0.5145191340919054 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_stage_ref_v] -value = 0.5145191413912287 +value = 0.5145191340926575 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_bias_v] -value = -2.93098878501041e-14 +value = -6.04338801224458e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_high_error_v] -value = 6.206424263409425e-15 +value = 3.15513892790117e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_return_error_v] -value = 4.251737850676298e-14 +value = 3.426438799357125e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0002723656021176976 +value = 0.0002723657168264794 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0002723656032978311 +value = 0.0002723657163815495 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_bias_v] -value = 0.3265125902632058 +value = 0.3265126446976954 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_input_cm_v] -value = 0.3265125897828277 +value = 0.3265126448785279 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_kick_v] -value = 1.506524349714766e-10 +value = 8.912115490034012e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_late_pp_v] -value = 1.922945136456633e-11 +value = 5.620409693207762e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_late_v] -value = 0.3265125897827136 +value = 0.3265126448783477 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_pre_kick_v] -value = 0.3265125897826363 +value = 0.3265126448755362 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_quiet_pp_v] -value = 1.870548160809449e-11 +value = 4.93209917351578e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_quiet_v] -value = 0.3265125897824681 +value = 0.3265126448770038 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_recovery_error_v] -value = 2.629791585899381e-12 +value = 3.461858924517499e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_recovery_v] -value = 0.3265125897825291 +value = 0.3265126448754256 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_ref_v] -value = 0.3265125897825922 +value = 0.3265126448765695 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_stage_ref_v] -value = 0.3265125897827368 +value = 0.3265126448759331 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "fda8f09af68e851c18465b4e2a29ecfb52ed073ca74551d05565852515c6246e" -ac = "b39af2545bf0c974bfb84422884575dca3ae4e321bd921638aa59d765b1b6c5b" -transient = "e1afd4bfabaf143d4785a880a0c32a2e09075e3c115d34d9dd14a1335dac065f" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1437,133 +1425,128 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "53b7fd97e1fce73ec5827052a6a33416a10b9920d7046da23c5a45814ed67d4a" -dut = "cda4a2fe217a444033868a7c36a0ab0e0644f2a18ebaabd963bce758fc0ccefb" +dut = "c85b096e1dc61f51e9458d8534ae95db7a144ca0ccea8018d37e42612ee4758f" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.closed_gain_10khz_db] -value = -0.009874496 +value = -0.009874488 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_bias_v] -value = 0.5145191412199209 +value = 0.5145191341527368 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_input_cm_v] -value = 0.5272836530470836 +value = 0.5272836524452108 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_kick_v] -value = 0.01439070334460935 +value = 0.01439094265062457 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_late_pp_v] -value = 2.420530442748259e-11 +value = 2.350941663564754e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_late_v] -value = 0.5145191409059839 +value = 0.514519133372046 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_pre_kick_v] -value = 0.5145191386521749 +value = 0.5145191313654978 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_quiet_pp_v] -value = 2.668398835226071e-11 +value = 5.809597247719012e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_quiet_v] -value = 0.5145191413919855 +value = 0.5145191340935519 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_recovery_error_v] -value = 3.491205786592767e-09 +value = 3.586909356756304e-09 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_recovery_v] -value = 0.514519142143372 +value = 0.5145191349524044 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_ref_v] -value = 0.539235380454869 +value = 0.5392353732919976 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_stage_ref_v] -value = 0.5145191408849435 +value = 0.5145191333577243 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_bias_v] -value = -2.93098878501041e-14 +value = -6.04338801224458e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_high_error_v] -value = 1.13643730197952e-05 +value = 1.136435922697761e-05 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_return_error_v] -value = 1.181886774455246e-13 +value = 1.244662131527355e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] -value = 0.000257795671053517 +value = 0.0002577957811847455 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0002723656032978311 +value = 0.0002723657163815495 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_bias_v] -value = 0.3265125902632058 +value = 0.3265126446976954 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_input_cm_v] -value = 0.2120932661019089 +value = 0.2120932708044927 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_kick_v] -value = 0.01603593834687328 +value = 0.01603668947492021 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_late_pp_v] -value = 1.985128728065888e-11 +value = 1.764899337786119e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_late_v] -value = 0.3265125897823087 +value = 0.3265126448624269 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_pre_kick_v] -value = 0.326512615876301 +value = 0.3265126708295557 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_quiet_pp_v] -value = 1.870548160809449e-11 +value = 4.93209917351578e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_quiet_v] -value = 0.3265125897824681 +value = 0.3265126448770038 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_recovery_error_v] -value = 3.62420842475402e-08 +value = 3.621710142538522e-08 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_recovery_v] -value = 0.3265125796342074 +value = 0.3265126346124517 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_ref_v] -value = 0.3265146461796988 +value = 0.3265147011836095 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_stage_ref_v] -value = 0.3265125897825504 +value = 0.3265126448631057 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "fda8f09af68e851c18465b4e2a29ecfb52ed073ca74551d05565852515c6246e" -ac = "b39af2545bf0c974bfb84422884575dca3ae4e321bd921638aa59d765b1b6c5b" -transient = "64a25853bf99c1e86e50f953be1d4256fc72b6d0dd9a1e35e85bfe20bf4aa2f2" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1595,10 +1578,10 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "1736398f413762ed95f591bc91ab8acc55c245376cc41aa840f9a0178510324f" -dut = "cda4a2fe217a444033868a7c36a0ab0e0644f2a18ebaabd963bce758fc0ccefb" +dut = "c85b096e1dc61f51e9458d8534ae95db7a144ca0ccea8018d37e42612ee4758f" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_feedback_error_v] -value = 0.0 +value = 1.110223024625157e-16 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.fixture_cm_max] @@ -1610,13 +1593,9 @@ value = 54.20632 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_db] -value = 58.87927 +value = 58.87928 unit = "dB" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "e012c48f45466ec38942ec0241b4c5c3d357f9cceca9fef03446618f10ef3b6d" -ac = "730519b8e53cba6299ed2d6a8366fc41228477dc0070940f10a78c5e98948113" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1656,7 +1635,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl index ce52afc9846a5a9cac1ab5790eea1fb7543b8a5d..bbe4bd23879b95148fe88357e382765c668e42fb 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl @@ -1,67 +1,36 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_034_fan_chopper_cmfb vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm core__out1_p core__out1_n vb4o -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM10_CORE core__out1_n core__vb3 core__casc_src_n well_0 sg13_lv_pmos w=10u l=0.3u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM11_CORE core__out1_p core__vb3 core__casc_src_p well_1 sg13_lv_pmos w=10u l=0.3u m=1 -RT2 vss sub ptap1 A=4e-12 P=8e-6 -MM12_CORE core__out1_p core__vb2 core__fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -RT3 vss sub ptap1 A=4e-12 P=8e-6 -MM13_CORE core__out1_n core__vb2 core__fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -RT4 vss sub ptap1 A=4e-12 P=8e-6 -MM14_CORE voutp core__g2_p vss sub sg13_lv_nmos w=20u l=0.25u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM15_CORE voutn core__g2_n vss sub sg13_lv_nmos w=20u l=0.25u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM16_CORE core__out1_n vdd core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM17_CORE core__g2_n vss core__out1_n well_7 sg13_lv_pmos w=2u l=0.13u m=1 -RT8 vss sub ptap1 A=4e-12 P=8e-6 -MM18_CORE core__out1_p vdd core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM19_CORE core__g2_p vss core__out1_p well_9 sg13_lv_pmos w=2u l=0.13u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM1_CMFB cmfb__ptail cmfb__bias vdd well_10 sg13_lv_pmos w=0.33u l=0.26u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM1_CORE core__tail core__vb4 vdd well_11 sg13_lv_pmos w=20u l=1u m=1 -RT12 vss sub ptap1 A=4e-12 P=8e-6 -MM20_CORE core__out1_p vss core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM21_CORE core__g2_n vdd core__out1_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -RT14 vss sub ptap1 A=4e-12 P=8e-6 -MM22_CORE core__out1_n vss core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM23_CORE core__g2_p vdd core__out1_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -RT16 vss sub ptap1 A=4e-12 P=8e-6 -MM2_CMFB vb4o cmfb__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM2_CORE core__fold_p vinp core__tail well_17 sg13_lv_pmos w=20u l=0.5u m=1 -RT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -MM3_CMFB cmfb__bias cmfb__bias vdd well_18 sg13_lv_pmos w=0.88u l=0.26u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM3_CORE core__fold_n vinn core__tail well_19 sg13_lv_pmos w=20u l=0.5u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM4_CMFB cmfb__mirr cmfb__cm_sense cmfb__ptail well_20 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT21 vss sub ptap1 A=4e-12 P=8e-6 -MM4_CORE core__fold_p core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM5_CMFB vb4o vref_cm cmfb__ptail well_22 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT23 vss sub ptap1 A=4e-12 P=8e-6 -MM5_CORE core__fold_n core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -RT24 vss sub ptap1 A=4e-12 P=8e-6 -MM6_CMFB cmfb__mirr cmfb__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -MM6_CORE core__casc_src_n core__vb4 vdd well_25 sg13_lv_pmos w=10u l=1u m=1 -RT26 vss sub ptap1 A=4e-12 P=8e-6 -MM7_CMFB cmfb__bias cmfb__bias vss sub sg13_lv_nmos w=0.3u l=0.22u m=1 -RT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -MM7_CORE core__casc_src_p core__vb4 vdd well_27 sg13_lv_pmos w=10u l=1u m=1 -RT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -MM8O voutp vb4o vdd well_28 sg13_lv_pmos w=20u l=1u m=1 -RT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -MM9O voutn vb4o vdd well_29 sg13_lv_pmos w=20u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM10_CORE core__out1_n core__vb3 core__casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM11_CORE core__out1_p core__vb3 core__casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM12_CORE core__out1_p core__vb2 core__fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +MM13_CORE core__out1_n core__vb2 core__fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +MM14_CORE voutp core__g2_p vss vss sg13_lv_nmos w=20u l=0.25u m=1 +MM15_CORE voutn core__g2_n vss vss sg13_lv_nmos w=20u l=0.25u m=1 +MM16_CORE core__out1_n vdd core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM17_CORE core__g2_n vss core__out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM18_CORE core__out1_p vdd core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM19_CORE core__g2_p vss core__out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM1_CMFB cmfb__ptail cmfb__bias vdd vdd sg13_lv_pmos w=0.33u l=0.26u m=1 +MM1_CORE core__tail core__vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM20_CORE core__out1_p vss core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM21_CORE core__g2_n vdd core__out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM22_CORE core__out1_n vss core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM23_CORE core__g2_p vdd core__out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM2_CMFB vb4o cmfb__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM2_CORE core__fold_p vinp core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM3_CMFB cmfb__bias cmfb__bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +MM3_CORE core__fold_n vinn core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM4_CMFB cmfb__mirr cmfb__cm_sense cmfb__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM4_CORE core__fold_p core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +MM5_CMFB vb4o vref_cm cmfb__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM5_CORE core__fold_n core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +MM6_CMFB cmfb__mirr cmfb__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM6_CORE core__casc_src_n core__vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM7_CMFB cmfb__bias cmfb__bias vss vss sg13_lv_nmos w=0.3u l=0.22u m=1 +MM7_CORE core__casc_src_p core__vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM8O voutp vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM9O voutn vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 CCM0_0 vb4o ccm_s1 cap_cmim w=2.11u l=2.11u m=1 CCM1_0 ccm_s1 ccm_s2 cap_cmim w=2.11u l=2.11u m=1 CCM2_0 ccm_s2 ccm_s3 cap_cmim w=2.11u l=2.11u m=1 @@ -69,16 +38,14 @@ CCM3_0 ccm_s3 ccm_s4 cap_cmim w=2.11u l=2.11u m=1 CCM4_0 ccm_s4 ccm_s5 cap_cmim w=2.11u l=2.11u m=1 CCM5_0 ccm_s5 ccm_s6 cap_cmim w=2.11u l=2.11u m=1 CCM6_0 ccm_s6 vss cap_cmim w=2.11u l=2.11u m=1 -CM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -CM1_CORE_1 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -CM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -CM2_CORE_1 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -RRMN_CMFB_0 voutn RMN_CMFB_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_1 RMN_CMFB_s1 RMN_CMFB_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_2 RMN_CMFB_s2 RMN_CMFB_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_3 RMN_CMFB_s3 cmfb__cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_0 cmfb__cm_sense RMP_CMFB_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_1 RMP_CMFB_s1 RMP_CMFB_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_2 RMP_CMFB_s2 RMP_CMFB_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_3 RMP_CMFB_s3 voutp sub rhigh w=.5u l=84.45u m=1 b=0 +CM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=2 +CM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=2 +RRMN_CMFB_0 voutn RMN_CMFB_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_1 RMN_CMFB_s1 RMN_CMFB_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_2 RMN_CMFB_s2 RMN_CMFB_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_3 RMN_CMFB_s3 cmfb__cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_0 cmfb__cm_sense RMP_CMFB_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_1 RMP_CMFB_s1 RMP_CMFB_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_2 RMP_CMFB_s2 RMP_CMFB_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_3 RMP_CMFB_s3 voutp vss rhigh w=.5u l=84.45u m=1 b=0 .ends amp_034_fan_chopper_cmfb diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.spice index 24eb61533fe762cc7e88bd2904d76d1bebb5a89d..2d857391ad8aed75d3bc8d86293616d38bf79e95 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.spice @@ -1,67 +1,36 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_034_fan_chopper_cmfb vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm core__out1_p core__out1_n vb4o -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM10_CORE core__out1_n core__vb3 core__casc_src_n well_0 sg13_lv_pmos w=10u l=0.3u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM11_CORE core__out1_p core__vb3 core__casc_src_p well_1 sg13_lv_pmos w=10u l=0.3u m=1 -XT2 vss sub ptap1 A=4e-12 P=8e-6 -XM12_CORE core__out1_p core__vb2 core__fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -XT3 vss sub ptap1 A=4e-12 P=8e-6 -XM13_CORE core__out1_n core__vb2 core__fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -XT4 vss sub ptap1 A=4e-12 P=8e-6 -XM14_CORE voutp core__g2_p vss sub sg13_lv_nmos w=20u l=0.25u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM15_CORE voutn core__g2_n vss sub sg13_lv_nmos w=20u l=0.25u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM16_CORE core__out1_n vdd core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM17_CORE core__g2_n vss core__out1_n well_7 sg13_lv_pmos w=2u l=0.13u m=1 -XT8 vss sub ptap1 A=4e-12 P=8e-6 -XM18_CORE core__out1_p vdd core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM19_CORE core__g2_p vss core__out1_p well_9 sg13_lv_pmos w=2u l=0.13u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM1_CMFB cmfb__ptail cmfb__bias vdd well_10 sg13_lv_pmos w=0.33u l=0.26u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM1_CORE core__tail core__vb4 vdd well_11 sg13_lv_pmos w=20u l=1u m=1 -XT12 vss sub ptap1 A=4e-12 P=8e-6 -XM20_CORE core__out1_p vss core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM21_CORE core__g2_n vdd core__out1_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -XT14 vss sub ptap1 A=4e-12 P=8e-6 -XM22_CORE core__out1_n vss core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM23_CORE core__g2_p vdd core__out1_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -XT16 vss sub ptap1 A=4e-12 P=8e-6 -XM2_CMFB vb4o cmfb__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM2_CORE core__fold_p vinp core__tail well_17 sg13_lv_pmos w=20u l=0.5u m=1 -XT18 vdd well_18 ntap1 A=4e-12 P=8e-6 -XM3_CMFB cmfb__bias cmfb__bias vdd well_18 sg13_lv_pmos w=0.88u l=0.26u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM3_CORE core__fold_n vinn core__tail well_19 sg13_lv_pmos w=20u l=0.5u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM4_CMFB cmfb__mirr cmfb__cm_sense cmfb__ptail well_20 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT21 vss sub ptap1 A=4e-12 P=8e-6 -XM4_CORE core__fold_p core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM5_CMFB vb4o vref_cm cmfb__ptail well_22 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT23 vss sub ptap1 A=4e-12 P=8e-6 -XM5_CORE core__fold_n core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -XT24 vss sub ptap1 A=4e-12 P=8e-6 -XM6_CMFB cmfb__mirr cmfb__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT25 vdd well_25 ntap1 A=4e-12 P=8e-6 -XM6_CORE core__casc_src_n core__vb4 vdd well_25 sg13_lv_pmos w=10u l=1u m=1 -XT26 vss sub ptap1 A=4e-12 P=8e-6 -XM7_CMFB cmfb__bias cmfb__bias vss sub sg13_lv_nmos w=0.3u l=0.22u m=1 -XT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -XM7_CORE core__casc_src_p core__vb4 vdd well_27 sg13_lv_pmos w=10u l=1u m=1 -XT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -XM8O voutp vb4o vdd well_28 sg13_lv_pmos w=20u l=1u m=1 -XT29 vdd well_29 ntap1 A=4e-12 P=8e-6 -XM9O voutn vb4o vdd well_29 sg13_lv_pmos w=20u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM10_CORE core__out1_n core__vb3 core__casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM11_CORE core__out1_p core__vb3 core__casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM12_CORE core__out1_p core__vb2 core__fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +XM13_CORE core__out1_n core__vb2 core__fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +XM14_CORE voutp core__g2_p vss vss sg13_lv_nmos w=20u l=0.25u m=1 +XM15_CORE voutn core__g2_n vss vss sg13_lv_nmos w=20u l=0.25u m=1 +XM16_CORE core__out1_n vdd core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM17_CORE core__g2_n vss core__out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM18_CORE core__out1_p vdd core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM19_CORE core__g2_p vss core__out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM1_CMFB cmfb__ptail cmfb__bias vdd vdd sg13_lv_pmos w=0.33u l=0.26u m=1 +XM1_CORE core__tail core__vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM20_CORE core__out1_p vss core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM21_CORE core__g2_n vdd core__out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM22_CORE core__out1_n vss core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM23_CORE core__g2_p vdd core__out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM2_CMFB vb4o cmfb__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM2_CORE core__fold_p vinp core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM3_CMFB cmfb__bias cmfb__bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +XM3_CORE core__fold_n vinn core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM4_CMFB cmfb__mirr cmfb__cm_sense cmfb__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM4_CORE core__fold_p core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +XM5_CMFB vb4o vref_cm cmfb__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM5_CORE core__fold_n core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +XM6_CMFB cmfb__mirr cmfb__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM6_CORE core__casc_src_n core__vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM7_CMFB cmfb__bias cmfb__bias vss vss sg13_lv_nmos w=0.3u l=0.22u m=1 +XM7_CORE core__casc_src_p core__vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM8O voutp vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM9O voutn vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 XCCM0_0 vb4o ccm_s1 cap_cmim w=2.11u l=2.11u m=1 XCCM1_0 ccm_s1 ccm_s2 cap_cmim w=2.11u l=2.11u m=1 XCCM2_0 ccm_s2 ccm_s3 cap_cmim w=2.11u l=2.11u m=1 @@ -69,16 +38,14 @@ XCCM3_0 ccm_s3 ccm_s4 cap_cmim w=2.11u l=2.11u m=1 XCCM4_0 ccm_s4 ccm_s5 cap_cmim w=2.11u l=2.11u m=1 XCCM5_0 ccm_s5 ccm_s6 cap_cmim w=2.11u l=2.11u m=1 XCCM6_0 ccm_s6 vss cap_cmim w=2.11u l=2.11u m=1 -XCM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -XCM1_CORE_1 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -XCM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -XCM2_CORE_1 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -XRMN_CMFB_0 voutn RMN_CMFB_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_1 RMN_CMFB_s1 RMN_CMFB_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_2 RMN_CMFB_s2 RMN_CMFB_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_3 RMN_CMFB_s3 cmfb__cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_0 cmfb__cm_sense RMP_CMFB_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_1 RMP_CMFB_s1 RMP_CMFB_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_2 RMP_CMFB_s2 RMP_CMFB_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_3 RMP_CMFB_s3 voutp sub rhigh w=.5u l=84.45u m=1 b=0 +XCM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=2 +XCM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=2 +XRMN_CMFB_0 voutn RMN_CMFB_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_1 RMN_CMFB_s1 RMN_CMFB_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_2 RMN_CMFB_s2 RMN_CMFB_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_3 RMN_CMFB_s3 cmfb__cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_0 cmfb__cm_sense RMP_CMFB_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_1 RMP_CMFB_s1 RMP_CMFB_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_2 RMP_CMFB_s2 RMP_CMFB_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_3 RMP_CMFB_s3 voutp vss rhigh w=.5u l=84.45u m=1 b=0 .ends amp_034_fan_chopper_cmfb diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/schematic.svg deleted file mode 100644 index d479dca748aec6515cbd2c26157bc69f101c3449..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_034_fan_chopper_cmfb{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_034_fan_chopper_cmfb","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["amp_034_fan_chopper_cmfb","XRT2_bank1","XRRMN_CMFB_bank2","XRRMP_CMFB_bank3"],"banks":[{"name":"XRT2_bank1","devices":14,"source_references":["RT2","RT3","RT4","RT5","RT6","RT8","RT12","RT14","RT16","RT21","RT23","RT24","RT26","RTSUB"]},{"name":"XRRMN_CMFB_bank2","devices":4,"source_references":["RRMN_CMFB_0","RRMN_CMFB_1","RRMN_CMFB_2","RRMN_CMFB_3"]},{"name":"XRRMP_CMFB_bank3","devices":4,"source_references":["RRMP_CMFB_0","RRMP_CMFB_1","RRMP_CMFB_2","RRMP_CMFB_3"]}],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["amp_034_fan_chopper_cmfb"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/design/amp_034_fan_chopper_cmfb.icproj.json"}}Main-sheet overview; 3 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_034_fan_chopper_cmfbvoutnsubcmfb__cm_sensevsssubvoutpsubcmfb__cm_senseccm_s4ccm_s5ccm_s5ccm_s6vssccm_s6voutpcore__g2_pvoutpcore__g2_pcore__vb2voutncore__g2_nvoutncore__g2_nvsssubvoutnsubcore__out1_ncmfb__cm_sensevoutpsubcmfb__cm_sensevinpvinnvoutpvoutnvddsubvsscore__vb1core__vb2core__vb3core__vb4vref_cmcore__out1_pcore__out1_nvb4ocore__fold_nwell_0voutpvsssubcore__g2_pvoutnvsssubcore__g2_nvddcore__out1_nsubcore__g2_nvddwell_7vsscore__vb3core__out1_ncore__g2_nwell_7vddcore__out1_psubcore__g2_pvddwell_9core__out1_nvsscore__out1_pcore__g2_pwell_9vddwell_10vddwell_10well_0cmfb__ptailcmfb__biasvddwell_11vddcore__vb4well_11core__tailcore__casc_src_nvsscore__out1_psubcore__g2_nvddwell_13vddcore__out1_pcore__g2_nwell_13vsscore__out1_nsubvddcore__g2_pvddwell_15vddcore__out1_ncore__g2_pwell_15vsswell_1vb4osubcmfb__mirrvddwell_17vinpcore__fold_pcore__tailwell_17vddwell_18vddcmfb__biascmfb__biaswell_18core__vb3vddwell_19vinncore__fold_ncore__tailwell_19vddwell_20core__out1_pcmfb__ptailcmfb__mirrwell_20cmfb__cm_sensevsscore__vb1subcore__fold_pwell_1vddwell_22vref_cmvb4ocmfb__ptailwell_22vsscore__vb1core__casc_src_psubcore__fold_nvsssubcmfb__mirrcmfb__mirrvddwell_25vddcore__vb4vddcore__casc_src_nwell_25vsssubcmfb__biascore__vb2cmfb__biasvddwell_27vddcore__vb4core__casc_src_pwell_27vddcore__out1_pwell_28voutpvddvb4owell_28vddwell_29voutnsubvddvb4owell_29vb4occm_s1ccm_s1ccm_s2ccm_s2core__fold_pccm_s3ccm_s3ccm_s4amp_034_fan_chopper_cmfbFOLDED INPUT AND CASCODE COREOUTPUT COMMON-MODE FEEDBACKLEVEL SHIFT AND OUTPUT DRIVERVOUTP / VOUTN OUTPUTCOMPENSATIONWELL AND SUBSTRATE CONTACTSMM10_COREMM11_COREMM12_COREMM13_COREMM14_COREMM15_COREMM16_COREMM17_COREMM18_COREMM19_COREMM1_CMFBMM1_COREMM20_COREMM21_COREMM22_COREMM23_COREMM2_CMFBMM2_COREMM3_CMFBMM3_COREMM4_CMFBMM4_COREMM5_CMFBMM5_COREMM6_CMFBMM6_COREMM7_CMFBMM7_COREMM8OMM9OXRRMN_CMFB_bank2XRRMP_CMFB_bank3XRT2_bank1CCM0CCM1CCM2CCM3CCM4CCM5CCM6CM1_CORE_0CM1_CORE_1CM2_CORE_0CM2_CORE_1RT0RT1RT7RT9RT10RT11RT13RT15RT17RT18RT19RT20RT22RT25RT27RT28RT29 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md index 1e5e183029ead6d52bb01a7733221dc0f23c140b..6363de6247f91513552b5f15b375cb6b680c0cf0 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md @@ -8,7 +8,7 @@ Implement `amp_034_fan_chopper_cmfb` without changing the declared circuit. The `materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 core__vb4 vref_cm core__out1_p core__out1_n vb4o`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core. -W/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. The subminimum 1 fF CCM is realized by seven series 7.016 fF MIM units (2.11 um sides), approximately 1.002 fF equivalent. Intermediate nodes and their physical parasitics are retained in both source and candidate models. The branch is never omitted. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. +W/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. The subminimum 1 fF CCM is realized by seven series 7.016 fF MIM units (2.11 um sides), approximately 1.002 fF equivalent. Intermediate nodes and their physical parasitics are retained in both source and candidate models. The branch is never omitted. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source and extraction use logical body nets. Native LVS checks actual body-contact connectivity. Distributed substrate behavior is outside this model boundary. ## Operating Conditions @@ -131,3 +131,5 @@ One/two-loop CMFB amplifier assemblies: output common-mode dynamics 33.8%; stage Solve budget: **8 hours**. Use the reviewed SG13G2 resources and ngspice 45 environment. Frozen inputs, requirements and tool bindings are in `/protocol/task.json`. Explicitly submit `/workspace/output/final.gds` through the session submission tool; file generation alone is not submission. Evaluation performs native checks, candidate RC extraction and independent paired source/post-layout simulation. Reference GDS, maintainer README and development sources are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml index 2a18131e99c302e151141453ab99b831013a5cfc..5e19faa93a8a6744e4025c5fe504f1b10ab2c011 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml @@ -4,13 +4,6 @@ title = "Fan Dual CMFB OTA" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "fd752c4bc9ff5e2c18a04121033f4a07fd3ccd09263b4d8123cd14c7ffa60217" - [[assets]] path = "reference/amp_035_fan_chopper_cmfb_dual.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "60ae5d997bd13333349d225d9acb5c7b9882c138357734c658a85773568e255c" +sha256 = "cc284e79a3b99861246aba04e0acba21fa18d9cc996f6d0345ffbe2c3598ac3d" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "amp_035_fan_chopper_cmfb_dual" -sha256 = "70db9a09e47cfaf6dc9aecb394d7300c2d6125f26d16252ff1ba67688085165c" +sha256 = "49c446a5ec68bdad0a70299c813709ca45fb59a4a99330d217c8d29e74a06af3" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "d1338e6ff0af234b256188279fd15f3a0bef1f9d34a0c06734199a9c60964b0c" +sha256 = "3881bd55697e62dc5d608ff25e2ba5c4421f85735d7f206d853ee1ecc7496a8d" [task.inputs.performance] path = "materials/testbench.spice" @@ -1188,10 +1181,10 @@ upper = 1e-06 rationale = "The external differential measurement loop must enforce its declared DC excitation within 1 uV; otherwise the observation uses an invalid fixture operating point." [task.evaluation.pre_layout] -source_report_sha256 = "e627faed6fa117e3d5b632f41329d8f5d470d1738589686c2e447669a81f9f13" +source_report_sha256 = "9804f6a15334f7f1f0426c9a18c27acdf332c9b0adff230eb699e1a19f0cbf84" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 1800.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 1800.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1252,133 +1245,128 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "d44740562add873b61fe5eaea67d3d9278e0e63b8cf1f35c61262200842d43b6" -dut = "d1338e6ff0af234b256188279fd15f3a0bef1f9d34a0c06734199a9c60964b0c" +dut = "3881bd55697e62dc5d608ff25e2ba5c4421f85735d7f206d853ee1ecc7496a8d" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.closed_gain_10khz_db] value = -0.008363524 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_bias_v] -value = 0.5124550434072465 +value = 0.5124550428535021 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_input_cm_v] -value = 0.5223745686028927 +value = 0.5123675422856172 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_kick_v] -value = 4.798649196282233e-06 +value = 5.674362524301353e-08 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_late_pp_v] -value = 0.002818616921816366 +value = 0.485332166759276 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_late_v] -value = 0.02422180974482191 +value = 0.1444214828060857 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_pre_kick_v] -value = 0.5124554955331873 +value = 0.5124550484304052 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_quiet_pp_v] -value = 4.771258055313865e-08 +value = 3.006725979304292e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_quiet_v] -value = 0.5124549597971081 +value = 0.5124550449379567 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_recovery_error_v] -value = 3.519040434407591e-05 +value = 5.520504985104497e-07 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_recovery_v] -value = 0.5124906859375302 +value = 0.512454496379898 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_ref_v] -value = 0.5120268894141123 +value = 0.5124615618785046 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_stage_ref_v] -value = 0.5666852139955194 +value = 0.5324462373446786 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_bias_v] -value = -4.26547686060985e-13 +value = -4.29412061464518e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_high_error_v] -value = 1.782649028390124e-13 +value = 5.99816085689303e-13 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_return_error_v] -value = 1.225932966257673e-13 +value = 7.810800201070227e-13 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0003949871582047419 +value = 0.0003949570349946296 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0003283154670056591 +value = 0.0003283154776579732 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_bias_v] -value = 0.3417966386454913 +value = 0.3417966422575449 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_input_cm_v] -value = 0.2581049351822609 +value = 0.3426048428857391 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_kick_v] -value = 3.240564107002865e-05 +value = 3.893327016614457e-07 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_late_pp_v] -value = 0.09479871160458342 +value = 0.7445176597467944 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_late_v] -value = 1.06484556310657 +value = 0.8075217302776377 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_pre_kick_v] -value = 0.3417923833962281 +value = 0.3417966242647419 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_quiet_pp_v] -value = 3.612232494232259e-07 +value = 1.578191466400369e-09 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_quiet_v] -value = 0.3417972242733103 +value = 0.3417966352392575 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_recovery_error_v] -value = 0.0002209070422553941 +value = 3.605773303733468e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_recovery_v] -value = 0.341571476353972 +value = 0.3418002300380638 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_ref_v] -value = 0.3444762082719498 +value = 0.3417539411463056 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.s1_stage_ref_v] -value = 0.001948147066014553 +value = 0.1608869885659387 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "fb7ee1224c3590a568d3b41a340794184256e70735bdaa46024ceaef319816a1" -ac = "ca914d115d5cce715e7ede73de6b76b604772872645d587e2559aabcaa28d386" -transient = "b14c55ec10e3cc3b09f61ef72e4b74af0f0a651aa9e9026c9e6fd9b756eb98bc" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1438,133 +1426,128 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "d44740562add873b61fe5eaea67d3d9278e0e63b8cf1f35c61262200842d43b6" -dut = "d1338e6ff0af234b256188279fd15f3a0bef1f9d34a0c06734199a9c60964b0c" +dut = "3881bd55697e62dc5d608ff25e2ba5c4421f85735d7f206d853ee1ecc7496a8d" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.closed_gain_10khz_db] value = -0.008363524 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_bias_v] -value = 0.5124550434072465 +value = 0.5124550428535021 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_input_cm_v] -value = 0.02984540185846699 +value = 0.02824686908208899 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_kick_v] -value = 0.01239092289404176 +value = 0.01239258538537114 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_late_pp_v] -value = 0.0002234986411182201 +value = 0.0002462867883746868 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_late_v] -value = 0.02282106359214712 +value = 0.02283353294941653 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_pre_kick_v] -value = 0.5124625481129548 +value = 0.5124620964219935 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_quiet_pp_v] -value = 4.771258055313865e-08 +value = 3.006725979304292e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_quiet_v] -value = 0.5124549597971081 +value = 0.5124550449379567 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_recovery_error_v] -value = 6.188717858143291e-05 +value = 3.934368148549977e-05 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_recovery_v] -value = 0.5125244352915471 +value = 0.5124887060959974 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_ref_v] -value = 0.5399578063961201 +value = 0.5403079630447306 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_stage_ref_v] -value = 0.5847758973349619 +value = 0.5857556682151915 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_bias_v] -value = -4.26547686060985e-13 +value = -4.29412061464518e-12 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_high_error_v] -value = 9.636491191785163e-06 +value = 9.636221609846729e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_return_error_v] -value = 2.664109428446812e-08 +value = 2.664137853435812e-08 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] -value = 0.0004800261426133078 +value = 0.0004806618901112183 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0003283154670056591 +value = 0.0003283154776579732 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_bias_v] -value = 0.3417966386454913 +value = 0.3417966422575449 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_input_cm_v] -value = 0.9118090511089213 +value = 0.9424599696240635 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_kick_v] -value = 0.01313044431709698 +value = 0.01315635399909892 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_late_pp_v] -value = 0.01042919562663625 +value = 0.01146254391486634 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_late_v] -value = 1.122327916929836 +value = 1.121746769578146 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_pre_kick_v] -value = 0.3417404592003688 +value = 0.3417447269628834 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_quiet_pp_v] -value = 3.612232494232259e-07 +value = 1.578191466400369e-09 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_quiet_v] -value = 0.3417972242733103 +value = 0.3417966352392575 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_recovery_error_v] -value = 0.0004713319322403166 +value = 0.0002978686321503909 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_recovery_v] -value = 0.3412691272681272 +value = 0.3414948497735911 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_ref_v] -value = 0.3226353653854883 +value = 0.3201468982816969 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.s1_stage_ref_v] -value = 0.02513125630632075 +value = 0.02636089729082803 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "fb7ee1224c3590a568d3b41a340794184256e70735bdaa46024ceaef319816a1" -ac = "ca914d115d5cce715e7ede73de6b76b604772872645d587e2559aabcaa28d386" -transient = "1df4de7b0f5aacae89c2f6a019c5f55eb9e04a7b878ee12ca66a26ff2bf66087" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1596,14 +1579,14 @@ ac = "ac.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "412511ca23585e19e5dd371b13aae4c24bc93bd6e468886ee2648bfc2c35ed81" -dut = "d1338e6ff0af234b256188279fd15f3a0bef1f9d34a0c06734199a9c60964b0c" +dut = "3881bd55697e62dc5d608ff25e2ba5c4421f85735d7f206d853ee1ecc7496a8d" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_feedback_error_v] -value = 1.110223024625157e-16 +value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.fixture_cm_max] -value = 1.00074151062168e-16 +value = 1.309227883336068e-16 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_10khz_db] @@ -1614,10 +1597,6 @@ unit = "dB" value = 60.34043 unit = "dB" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "c6d89b832a1be6cfbc7585bf17214bbed6a81de830c6d73282afdab7bdb4bc40" -ac = "6ab1f1e6f0e7f2e0d3ebcf8b9828a01cbcbe669e79745772154fc9a1e46e2f7d" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1657,7 +1636,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl index deba0489cae7a98200f71d4ea0a5bd0682406257..f77bc126dfa63a13db6f7ebd7a3c55f640e53e7d 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl @@ -1,516 +1,452 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_035_fan_chopper_cmfb_dual vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 vref_out vref_s1 stg1_p stg1_n vb4o vb4_ctl -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM10_CORE stg1_n core__vb3 core__casc_src_n well_0 sg13_lv_pmos w=10u l=0.3u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM11_CORE stg1_p core__vb3 core__casc_src_p well_1 sg13_lv_pmos w=10u l=0.3u m=1 -RT2 vss sub ptap1 A=4e-12 P=8e-6 -MM12_CORE stg1_p core__vb2 core__fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -RT3 vss sub ptap1 A=4e-12 P=8e-6 -MM13_CORE stg1_n core__vb2 core__fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -RT4 vss sub ptap1 A=4e-12 P=8e-6 -MM14_CORE voutp core__g2_p vss sub sg13_lv_nmos w=20u l=0.25u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM15_CORE voutn core__g2_n vss sub sg13_lv_nmos w=20u l=0.25u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM16_CORE stg1_n vdd core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -MM17_CORE core__g2_n vss stg1_n well_7 sg13_lv_pmos w=2u l=0.13u m=1 -RT8 vss sub ptap1 A=4e-12 P=8e-6 -MM18_CORE stg1_p vdd core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -MM19_CORE core__g2_p vss stg1_p well_9 sg13_lv_pmos w=2u l=0.13u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM1_CMFB_OUT cmfb_out__ptail cmfb_out__bias vdd well_10 sg13_lv_pmos w=0.33u l=0.26u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM1_CMFB_S1 cmfb_s1__ptail cmfb_s1__bias vdd well_11 sg13_lv_pmos w=0.33u l=0.26u m=1 -RT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -MM1_CORE core__tail vb4_ctl vdd well_12 sg13_lv_pmos w=20u l=1u m=1 -RT13 vss sub ptap1 A=4e-12 P=8e-6 -MM20_CORE stg1_p vss core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -MM21_CORE core__g2_n vdd stg1_p well_14 sg13_lv_pmos w=2u l=0.13u m=1 -RT15 vss sub ptap1 A=4e-12 P=8e-6 -MM22_CORE stg1_n vss core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -MM23_CORE core__g2_p vdd stg1_n well_16 sg13_lv_pmos w=2u l=0.13u m=1 -RT17 vss sub ptap1 A=4e-12 P=8e-6 -MM2_CMFB_OUT vb4o cmfb_out__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT18 vss sub ptap1 A=4e-12 P=8e-6 -MM2_CMFB_S1 vb4_ctl cmfb_s1__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM2_CORE core__fold_p vinp core__tail well_19 sg13_lv_pmos w=20u l=0.5u m=1 -RT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -MM3_CMFB_OUT cmfb_out__bias cmfb_out__bias vdd well_20 sg13_lv_pmos w=0.88u l=0.26u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM3_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vdd well_21 sg13_lv_pmos w=0.88u l=0.26u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM3_CORE core__fold_n vinn core__tail well_22 sg13_lv_pmos w=20u l=0.5u m=1 -RT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -MM4_CMFB_OUT cmfb_out__mirr cmfb_out__cm_sense cmfb_out__ptail well_23 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -MM4_CMFB_S1 cmfb_s1__mirr cmfb_s1__cm_sense cmfb_s1__ptail well_24 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT25 vss sub ptap1 A=4e-12 P=8e-6 -MM4_CORE core__fold_p core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -RT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -MM5_CMFB_OUT vb4o vref_out cmfb_out__ptail well_26 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -MM5_CMFB_S1 vb4_ctl vref_s1 cmfb_s1__ptail well_27 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT28 vss sub ptap1 A=4e-12 P=8e-6 -MM5_CORE core__fold_n core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -RT29 vss sub ptap1 A=4e-12 P=8e-6 -MM6_CMFB_OUT cmfb_out__mirr cmfb_out__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT30 vss sub ptap1 A=4e-12 P=8e-6 -MM6_CMFB_S1 cmfb_s1__mirr cmfb_s1__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -MM6_CORE core__casc_src_n vb4_ctl vdd well_31 sg13_lv_pmos w=10u l=1u m=1 -RT32 vss sub ptap1 A=4e-12 P=8e-6 -MM7_CMFB_OUT cmfb_out__bias cmfb_out__bias vss sub sg13_lv_nmos w=0.3u l=0.22u m=1 -RT33 vss sub ptap1 A=4e-12 P=8e-6 -MM7_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vss sub sg13_lv_nmos w=0.3u l=0.22u m=1 -RT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -MM7_CORE core__casc_src_p vb4_ctl vdd well_34 sg13_lv_pmos w=10u l=1u m=1 -RT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -MM8O voutp vb4o vdd well_35 sg13_lv_pmos w=20u l=1u m=1 -RT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -MM9O voutn vb4o vdd well_36 sg13_lv_pmos w=20u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 -CCM_S1_0 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_1 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_2 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_3 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_4 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_5 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_6 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_7 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_8 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_9 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_10 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_11 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_12 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_13 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_14 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_15 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_16 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_17 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_18 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_19 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_20 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_21 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_22 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_23 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CCM_S1_24 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -CM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -CM1_CORE_1 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -CM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -CM2_CORE_1 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -RRMN_CMFB_OUT_0 voutn RMN_CMFB_OUT_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_OUT_1 RMN_CMFB_OUT_s1 RMN_CMFB_OUT_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_OUT_2 RMN_CMFB_OUT_s2 RMN_CMFB_OUT_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_OUT_3 RMN_CMFB_OUT_s3 cmfb_out__cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_0 stg1_n RMN_CMFB_S1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_1 RMN_CMFB_S1_s1 RMN_CMFB_S1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_2 RMN_CMFB_S1_s2 RMN_CMFB_S1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_3 RMN_CMFB_S1_s3 RMN_CMFB_S1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_4 RMN_CMFB_S1_s4 RMN_CMFB_S1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_5 RMN_CMFB_S1_s5 RMN_CMFB_S1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_6 RMN_CMFB_S1_s6 RMN_CMFB_S1_s7 sub rhigh w=.5u l=84.45u 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w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_128 RMN_CMFB_S1_s128 RMN_CMFB_S1_s129 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_129 RMN_CMFB_S1_s129 RMN_CMFB_S1_s130 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_130 RMN_CMFB_S1_s130 RMN_CMFB_S1_s131 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_131 RMN_CMFB_S1_s131 RMN_CMFB_S1_s132 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_132 RMN_CMFB_S1_s132 RMN_CMFB_S1_s133 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_133 RMN_CMFB_S1_s133 RMN_CMFB_S1_s134 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_134 RMN_CMFB_S1_s134 RMN_CMFB_S1_s135 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_135 RMN_CMFB_S1_s135 RMN_CMFB_S1_s136 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_136 RMN_CMFB_S1_s136 RMN_CMFB_S1_s137 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_137 RMN_CMFB_S1_s137 RMN_CMFB_S1_s138 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_138 RMN_CMFB_S1_s138 RMN_CMFB_S1_s139 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_139 RMN_CMFB_S1_s139 RMN_CMFB_S1_s140 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_140 RMN_CMFB_S1_s140 RMN_CMFB_S1_s141 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_141 RMN_CMFB_S1_s141 RMN_CMFB_S1_s142 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_142 RMN_CMFB_S1_s142 RMN_CMFB_S1_s143 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_143 RMN_CMFB_S1_s143 RMN_CMFB_S1_s144 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_144 RMN_CMFB_S1_s144 RMN_CMFB_S1_s145 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_145 RMN_CMFB_S1_s145 RMN_CMFB_S1_s146 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_146 RMN_CMFB_S1_s146 RMN_CMFB_S1_s147 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_147 RMN_CMFB_S1_s147 RMN_CMFB_S1_s148 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_148 RMN_CMFB_S1_s148 RMN_CMFB_S1_s149 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_149 RMN_CMFB_S1_s149 RMN_CMFB_S1_s150 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_150 RMN_CMFB_S1_s150 RMN_CMFB_S1_s151 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_151 RMN_CMFB_S1_s151 RMN_CMFB_S1_s152 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_152 RMN_CMFB_S1_s152 RMN_CMFB_S1_s153 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_153 RMN_CMFB_S1_s153 RMN_CMFB_S1_s154 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_154 RMN_CMFB_S1_s154 RMN_CMFB_S1_s155 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_155 RMN_CMFB_S1_s155 RMN_CMFB_S1_s156 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_156 RMN_CMFB_S1_s156 RMN_CMFB_S1_s157 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_157 RMN_CMFB_S1_s157 RMN_CMFB_S1_s158 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_158 RMN_CMFB_S1_s158 RMN_CMFB_S1_s159 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_159 RMN_CMFB_S1_s159 RMN_CMFB_S1_s160 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_160 RMN_CMFB_S1_s160 RMN_CMFB_S1_s161 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_161 RMN_CMFB_S1_s161 RMN_CMFB_S1_s162 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_162 RMN_CMFB_S1_s162 RMN_CMFB_S1_s163 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_163 RMN_CMFB_S1_s163 RMN_CMFB_S1_s164 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_164 RMN_CMFB_S1_s164 RMN_CMFB_S1_s165 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_165 RMN_CMFB_S1_s165 RMN_CMFB_S1_s166 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_166 RMN_CMFB_S1_s166 RMN_CMFB_S1_s167 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_167 RMN_CMFB_S1_s167 RMN_CMFB_S1_s168 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_168 RMN_CMFB_S1_s168 RMN_CMFB_S1_s169 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_169 RMN_CMFB_S1_s169 RMN_CMFB_S1_s170 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_170 RMN_CMFB_S1_s170 RMN_CMFB_S1_s171 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_171 RMN_CMFB_S1_s171 RMN_CMFB_S1_s172 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_172 RMN_CMFB_S1_s172 RMN_CMFB_S1_s173 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_173 RMN_CMFB_S1_s173 RMN_CMFB_S1_s174 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_174 RMN_CMFB_S1_s174 RMN_CMFB_S1_s175 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_175 RMN_CMFB_S1_s175 RMN_CMFB_S1_s176 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_176 RMN_CMFB_S1_s176 RMN_CMFB_S1_s177 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_177 RMN_CMFB_S1_s177 RMN_CMFB_S1_s178 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_178 RMN_CMFB_S1_s178 RMN_CMFB_S1_s179 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_179 RMN_CMFB_S1_s179 RMN_CMFB_S1_s180 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_180 RMN_CMFB_S1_s180 RMN_CMFB_S1_s181 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_181 RMN_CMFB_S1_s181 RMN_CMFB_S1_s182 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_182 RMN_CMFB_S1_s182 RMN_CMFB_S1_s183 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_183 RMN_CMFB_S1_s183 RMN_CMFB_S1_s184 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_184 RMN_CMFB_S1_s184 RMN_CMFB_S1_s185 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_185 RMN_CMFB_S1_s185 RMN_CMFB_S1_s186 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_186 RMN_CMFB_S1_s186 RMN_CMFB_S1_s187 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_187 RMN_CMFB_S1_s187 RMN_CMFB_S1_s188 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_188 RMN_CMFB_S1_s188 RMN_CMFB_S1_s189 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_189 RMN_CMFB_S1_s189 RMN_CMFB_S1_s190 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_190 RMN_CMFB_S1_s190 RMN_CMFB_S1_s191 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_191 RMN_CMFB_S1_s191 RMN_CMFB_S1_s192 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_192 RMN_CMFB_S1_s192 RMN_CMFB_S1_s193 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_193 RMN_CMFB_S1_s193 RMN_CMFB_S1_s194 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_194 RMN_CMFB_S1_s194 RMN_CMFB_S1_s195 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_195 RMN_CMFB_S1_s195 RMN_CMFB_S1_s196 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_196 RMN_CMFB_S1_s196 RMN_CMFB_S1_s197 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_197 RMN_CMFB_S1_s197 RMN_CMFB_S1_s198 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_198 RMN_CMFB_S1_s198 RMN_CMFB_S1_s199 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_CMFB_S1_199 RMN_CMFB_S1_s199 cmfb_s1__cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_OUT_0 cmfb_out__cm_sense RMP_CMFB_OUT_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_OUT_1 RMP_CMFB_OUT_s1 RMP_CMFB_OUT_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_OUT_2 RMP_CMFB_OUT_s2 RMP_CMFB_OUT_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_OUT_3 RMP_CMFB_OUT_s3 voutp sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_0 cmfb_s1__cm_sense RMP_CMFB_S1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_1 RMP_CMFB_S1_s1 RMP_CMFB_S1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_2 RMP_CMFB_S1_s2 RMP_CMFB_S1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_3 RMP_CMFB_S1_s3 RMP_CMFB_S1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_4 RMP_CMFB_S1_s4 RMP_CMFB_S1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_5 RMP_CMFB_S1_s5 RMP_CMFB_S1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_6 RMP_CMFB_S1_s6 RMP_CMFB_S1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_7 RMP_CMFB_S1_s7 RMP_CMFB_S1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_8 RMP_CMFB_S1_s8 RMP_CMFB_S1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_9 RMP_CMFB_S1_s9 RMP_CMFB_S1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_10 RMP_CMFB_S1_s10 RMP_CMFB_S1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_11 RMP_CMFB_S1_s11 RMP_CMFB_S1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_12 RMP_CMFB_S1_s12 RMP_CMFB_S1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_13 RMP_CMFB_S1_s13 RMP_CMFB_S1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_14 RMP_CMFB_S1_s14 RMP_CMFB_S1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_15 RMP_CMFB_S1_s15 RMP_CMFB_S1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_16 RMP_CMFB_S1_s16 RMP_CMFB_S1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_17 RMP_CMFB_S1_s17 RMP_CMFB_S1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_18 RMP_CMFB_S1_s18 RMP_CMFB_S1_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_19 RMP_CMFB_S1_s19 RMP_CMFB_S1_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_20 RMP_CMFB_S1_s20 RMP_CMFB_S1_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_21 RMP_CMFB_S1_s21 RMP_CMFB_S1_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_22 RMP_CMFB_S1_s22 RMP_CMFB_S1_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_23 RMP_CMFB_S1_s23 RMP_CMFB_S1_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_24 RMP_CMFB_S1_s24 RMP_CMFB_S1_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_25 RMP_CMFB_S1_s25 RMP_CMFB_S1_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_26 RMP_CMFB_S1_s26 RMP_CMFB_S1_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_27 RMP_CMFB_S1_s27 RMP_CMFB_S1_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_28 RMP_CMFB_S1_s28 RMP_CMFB_S1_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_29 RMP_CMFB_S1_s29 RMP_CMFB_S1_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_30 RMP_CMFB_S1_s30 RMP_CMFB_S1_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_31 RMP_CMFB_S1_s31 RMP_CMFB_S1_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_32 RMP_CMFB_S1_s32 RMP_CMFB_S1_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_33 RMP_CMFB_S1_s33 RMP_CMFB_S1_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_34 RMP_CMFB_S1_s34 RMP_CMFB_S1_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_35 RMP_CMFB_S1_s35 RMP_CMFB_S1_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_36 RMP_CMFB_S1_s36 RMP_CMFB_S1_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_37 RMP_CMFB_S1_s37 RMP_CMFB_S1_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_38 RMP_CMFB_S1_s38 RMP_CMFB_S1_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_39 RMP_CMFB_S1_s39 RMP_CMFB_S1_s40 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_40 RMP_CMFB_S1_s40 RMP_CMFB_S1_s41 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_41 RMP_CMFB_S1_s41 RMP_CMFB_S1_s42 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_42 RMP_CMFB_S1_s42 RMP_CMFB_S1_s43 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_43 RMP_CMFB_S1_s43 RMP_CMFB_S1_s44 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_44 RMP_CMFB_S1_s44 RMP_CMFB_S1_s45 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_45 RMP_CMFB_S1_s45 RMP_CMFB_S1_s46 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_46 RMP_CMFB_S1_s46 RMP_CMFB_S1_s47 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_47 RMP_CMFB_S1_s47 RMP_CMFB_S1_s48 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_48 RMP_CMFB_S1_s48 RMP_CMFB_S1_s49 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_49 RMP_CMFB_S1_s49 RMP_CMFB_S1_s50 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_50 RMP_CMFB_S1_s50 RMP_CMFB_S1_s51 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_51 RMP_CMFB_S1_s51 RMP_CMFB_S1_s52 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_52 RMP_CMFB_S1_s52 RMP_CMFB_S1_s53 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_53 RMP_CMFB_S1_s53 RMP_CMFB_S1_s54 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_54 RMP_CMFB_S1_s54 RMP_CMFB_S1_s55 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_55 RMP_CMFB_S1_s55 RMP_CMFB_S1_s56 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_56 RMP_CMFB_S1_s56 RMP_CMFB_S1_s57 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_57 RMP_CMFB_S1_s57 RMP_CMFB_S1_s58 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_58 RMP_CMFB_S1_s58 RMP_CMFB_S1_s59 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_59 RMP_CMFB_S1_s59 RMP_CMFB_S1_s60 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_60 RMP_CMFB_S1_s60 RMP_CMFB_S1_s61 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_61 RMP_CMFB_S1_s61 RMP_CMFB_S1_s62 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_62 RMP_CMFB_S1_s62 RMP_CMFB_S1_s63 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_63 RMP_CMFB_S1_s63 RMP_CMFB_S1_s64 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_64 RMP_CMFB_S1_s64 RMP_CMFB_S1_s65 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_65 RMP_CMFB_S1_s65 RMP_CMFB_S1_s66 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_66 RMP_CMFB_S1_s66 RMP_CMFB_S1_s67 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_67 RMP_CMFB_S1_s67 RMP_CMFB_S1_s68 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_68 RMP_CMFB_S1_s68 RMP_CMFB_S1_s69 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_69 RMP_CMFB_S1_s69 RMP_CMFB_S1_s70 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_70 RMP_CMFB_S1_s70 RMP_CMFB_S1_s71 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_71 RMP_CMFB_S1_s71 RMP_CMFB_S1_s72 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_72 RMP_CMFB_S1_s72 RMP_CMFB_S1_s73 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_73 RMP_CMFB_S1_s73 RMP_CMFB_S1_s74 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_74 RMP_CMFB_S1_s74 RMP_CMFB_S1_s75 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_75 RMP_CMFB_S1_s75 RMP_CMFB_S1_s76 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_76 RMP_CMFB_S1_s76 RMP_CMFB_S1_s77 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_77 RMP_CMFB_S1_s77 RMP_CMFB_S1_s78 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_78 RMP_CMFB_S1_s78 RMP_CMFB_S1_s79 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_79 RMP_CMFB_S1_s79 RMP_CMFB_S1_s80 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_80 RMP_CMFB_S1_s80 RMP_CMFB_S1_s81 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_81 RMP_CMFB_S1_s81 RMP_CMFB_S1_s82 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_82 RMP_CMFB_S1_s82 RMP_CMFB_S1_s83 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_83 RMP_CMFB_S1_s83 RMP_CMFB_S1_s84 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_84 RMP_CMFB_S1_s84 RMP_CMFB_S1_s85 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_85 RMP_CMFB_S1_s85 RMP_CMFB_S1_s86 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_86 RMP_CMFB_S1_s86 RMP_CMFB_S1_s87 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_87 RMP_CMFB_S1_s87 RMP_CMFB_S1_s88 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_88 RMP_CMFB_S1_s88 RMP_CMFB_S1_s89 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_89 RMP_CMFB_S1_s89 RMP_CMFB_S1_s90 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_90 RMP_CMFB_S1_s90 RMP_CMFB_S1_s91 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_91 RMP_CMFB_S1_s91 RMP_CMFB_S1_s92 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_92 RMP_CMFB_S1_s92 RMP_CMFB_S1_s93 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_93 RMP_CMFB_S1_s93 RMP_CMFB_S1_s94 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_94 RMP_CMFB_S1_s94 RMP_CMFB_S1_s95 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_95 RMP_CMFB_S1_s95 RMP_CMFB_S1_s96 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_96 RMP_CMFB_S1_s96 RMP_CMFB_S1_s97 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_97 RMP_CMFB_S1_s97 RMP_CMFB_S1_s98 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_98 RMP_CMFB_S1_s98 RMP_CMFB_S1_s99 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_99 RMP_CMFB_S1_s99 RMP_CMFB_S1_s100 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_100 RMP_CMFB_S1_s100 RMP_CMFB_S1_s101 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_101 RMP_CMFB_S1_s101 RMP_CMFB_S1_s102 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_102 RMP_CMFB_S1_s102 RMP_CMFB_S1_s103 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_103 RMP_CMFB_S1_s103 RMP_CMFB_S1_s104 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_104 RMP_CMFB_S1_s104 RMP_CMFB_S1_s105 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_105 RMP_CMFB_S1_s105 RMP_CMFB_S1_s106 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_106 RMP_CMFB_S1_s106 RMP_CMFB_S1_s107 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_107 RMP_CMFB_S1_s107 RMP_CMFB_S1_s108 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_108 RMP_CMFB_S1_s108 RMP_CMFB_S1_s109 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_109 RMP_CMFB_S1_s109 RMP_CMFB_S1_s110 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_110 RMP_CMFB_S1_s110 RMP_CMFB_S1_s111 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_111 RMP_CMFB_S1_s111 RMP_CMFB_S1_s112 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_112 RMP_CMFB_S1_s112 RMP_CMFB_S1_s113 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_113 RMP_CMFB_S1_s113 RMP_CMFB_S1_s114 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_114 RMP_CMFB_S1_s114 RMP_CMFB_S1_s115 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_115 RMP_CMFB_S1_s115 RMP_CMFB_S1_s116 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_116 RMP_CMFB_S1_s116 RMP_CMFB_S1_s117 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_117 RMP_CMFB_S1_s117 RMP_CMFB_S1_s118 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_118 RMP_CMFB_S1_s118 RMP_CMFB_S1_s119 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_119 RMP_CMFB_S1_s119 RMP_CMFB_S1_s120 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_120 RMP_CMFB_S1_s120 RMP_CMFB_S1_s121 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_121 RMP_CMFB_S1_s121 RMP_CMFB_S1_s122 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_122 RMP_CMFB_S1_s122 RMP_CMFB_S1_s123 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_123 RMP_CMFB_S1_s123 RMP_CMFB_S1_s124 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_124 RMP_CMFB_S1_s124 RMP_CMFB_S1_s125 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_125 RMP_CMFB_S1_s125 RMP_CMFB_S1_s126 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_126 RMP_CMFB_S1_s126 RMP_CMFB_S1_s127 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_127 RMP_CMFB_S1_s127 RMP_CMFB_S1_s128 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_128 RMP_CMFB_S1_s128 RMP_CMFB_S1_s129 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_129 RMP_CMFB_S1_s129 RMP_CMFB_S1_s130 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_130 RMP_CMFB_S1_s130 RMP_CMFB_S1_s131 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_131 RMP_CMFB_S1_s131 RMP_CMFB_S1_s132 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_132 RMP_CMFB_S1_s132 RMP_CMFB_S1_s133 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_133 RMP_CMFB_S1_s133 RMP_CMFB_S1_s134 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_134 RMP_CMFB_S1_s134 RMP_CMFB_S1_s135 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_135 RMP_CMFB_S1_s135 RMP_CMFB_S1_s136 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_136 RMP_CMFB_S1_s136 RMP_CMFB_S1_s137 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_137 RMP_CMFB_S1_s137 RMP_CMFB_S1_s138 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_138 RMP_CMFB_S1_s138 RMP_CMFB_S1_s139 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_139 RMP_CMFB_S1_s139 RMP_CMFB_S1_s140 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_140 RMP_CMFB_S1_s140 RMP_CMFB_S1_s141 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_141 RMP_CMFB_S1_s141 RMP_CMFB_S1_s142 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_142 RMP_CMFB_S1_s142 RMP_CMFB_S1_s143 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_143 RMP_CMFB_S1_s143 RMP_CMFB_S1_s144 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_144 RMP_CMFB_S1_s144 RMP_CMFB_S1_s145 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_145 RMP_CMFB_S1_s145 RMP_CMFB_S1_s146 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_146 RMP_CMFB_S1_s146 RMP_CMFB_S1_s147 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_147 RMP_CMFB_S1_s147 RMP_CMFB_S1_s148 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_148 RMP_CMFB_S1_s148 RMP_CMFB_S1_s149 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_149 RMP_CMFB_S1_s149 RMP_CMFB_S1_s150 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_150 RMP_CMFB_S1_s150 RMP_CMFB_S1_s151 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_151 RMP_CMFB_S1_s151 RMP_CMFB_S1_s152 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_152 RMP_CMFB_S1_s152 RMP_CMFB_S1_s153 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_153 RMP_CMFB_S1_s153 RMP_CMFB_S1_s154 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_154 RMP_CMFB_S1_s154 RMP_CMFB_S1_s155 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_155 RMP_CMFB_S1_s155 RMP_CMFB_S1_s156 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_156 RMP_CMFB_S1_s156 RMP_CMFB_S1_s157 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_157 RMP_CMFB_S1_s157 RMP_CMFB_S1_s158 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_158 RMP_CMFB_S1_s158 RMP_CMFB_S1_s159 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_159 RMP_CMFB_S1_s159 RMP_CMFB_S1_s160 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_160 RMP_CMFB_S1_s160 RMP_CMFB_S1_s161 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_161 RMP_CMFB_S1_s161 RMP_CMFB_S1_s162 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_162 RMP_CMFB_S1_s162 RMP_CMFB_S1_s163 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_163 RMP_CMFB_S1_s163 RMP_CMFB_S1_s164 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_164 RMP_CMFB_S1_s164 RMP_CMFB_S1_s165 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_165 RMP_CMFB_S1_s165 RMP_CMFB_S1_s166 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_166 RMP_CMFB_S1_s166 RMP_CMFB_S1_s167 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_167 RMP_CMFB_S1_s167 RMP_CMFB_S1_s168 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_168 RMP_CMFB_S1_s168 RMP_CMFB_S1_s169 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_169 RMP_CMFB_S1_s169 RMP_CMFB_S1_s170 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_170 RMP_CMFB_S1_s170 RMP_CMFB_S1_s171 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_171 RMP_CMFB_S1_s171 RMP_CMFB_S1_s172 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_172 RMP_CMFB_S1_s172 RMP_CMFB_S1_s173 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_173 RMP_CMFB_S1_s173 RMP_CMFB_S1_s174 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_174 RMP_CMFB_S1_s174 RMP_CMFB_S1_s175 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_175 RMP_CMFB_S1_s175 RMP_CMFB_S1_s176 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_176 RMP_CMFB_S1_s176 RMP_CMFB_S1_s177 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_177 RMP_CMFB_S1_s177 RMP_CMFB_S1_s178 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_178 RMP_CMFB_S1_s178 RMP_CMFB_S1_s179 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_179 RMP_CMFB_S1_s179 RMP_CMFB_S1_s180 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_180 RMP_CMFB_S1_s180 RMP_CMFB_S1_s181 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_181 RMP_CMFB_S1_s181 RMP_CMFB_S1_s182 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_182 RMP_CMFB_S1_s182 RMP_CMFB_S1_s183 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_183 RMP_CMFB_S1_s183 RMP_CMFB_S1_s184 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_184 RMP_CMFB_S1_s184 RMP_CMFB_S1_s185 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_185 RMP_CMFB_S1_s185 RMP_CMFB_S1_s186 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_186 RMP_CMFB_S1_s186 RMP_CMFB_S1_s187 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_187 RMP_CMFB_S1_s187 RMP_CMFB_S1_s188 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_188 RMP_CMFB_S1_s188 RMP_CMFB_S1_s189 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_189 RMP_CMFB_S1_s189 RMP_CMFB_S1_s190 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_190 RMP_CMFB_S1_s190 RMP_CMFB_S1_s191 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_191 RMP_CMFB_S1_s191 RMP_CMFB_S1_s192 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_192 RMP_CMFB_S1_s192 RMP_CMFB_S1_s193 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_193 RMP_CMFB_S1_s193 RMP_CMFB_S1_s194 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_194 RMP_CMFB_S1_s194 RMP_CMFB_S1_s195 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_195 RMP_CMFB_S1_s195 RMP_CMFB_S1_s196 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_196 RMP_CMFB_S1_s196 RMP_CMFB_S1_s197 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_197 RMP_CMFB_S1_s197 RMP_CMFB_S1_s198 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_198 RMP_CMFB_S1_s198 RMP_CMFB_S1_s199 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_CMFB_S1_199 RMP_CMFB_S1_s199 stg1_p sub rhigh w=.5u l=84.45u m=1 b=0 +MM10_CORE stg1_n core__vb3 core__casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM11_CORE stg1_p core__vb3 core__casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM12_CORE stg1_p core__vb2 core__fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +MM13_CORE stg1_n core__vb2 core__fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +MM14_CORE voutp core__g2_p vss vss sg13_lv_nmos w=20u l=0.25u m=1 +MM15_CORE voutn core__g2_n vss vss sg13_lv_nmos w=20u l=0.25u m=1 +MM16_CORE stg1_n vdd core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM17_CORE core__g2_n vss stg1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM18_CORE stg1_p vdd core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM19_CORE core__g2_p vss stg1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM1_CMFB_OUT cmfb_out__ptail cmfb_out__bias vdd vdd sg13_lv_pmos w=0.33u l=0.26u m=1 +MM1_CMFB_S1 cmfb_s1__ptail cmfb_s1__bias vdd vdd sg13_lv_pmos w=0.33u l=0.26u m=1 +MM1_CORE core__tail vb4_ctl vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM20_CORE stg1_p vss core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM21_CORE core__g2_n vdd stg1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM22_CORE stg1_n vss core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM23_CORE core__g2_p vdd stg1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM2_CMFB_OUT vb4o cmfb_out__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM2_CMFB_S1 vb4_ctl cmfb_s1__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM2_CORE core__fold_p vinp core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM3_CMFB_OUT cmfb_out__bias cmfb_out__bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +MM3_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +MM3_CORE core__fold_n vinn core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM4_CMFB_OUT cmfb_out__mirr cmfb_out__cm_sense cmfb_out__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM4_CMFB_S1 cmfb_s1__mirr cmfb_s1__cm_sense cmfb_s1__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM4_CORE core__fold_p core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +MM5_CMFB_OUT vb4o vref_out cmfb_out__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM5_CMFB_S1 vb4_ctl vref_s1 cmfb_s1__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM5_CORE core__fold_n core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +MM6_CMFB_OUT cmfb_out__mirr cmfb_out__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM6_CMFB_S1 cmfb_s1__mirr cmfb_s1__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM6_CORE core__casc_src_n vb4_ctl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM7_CMFB_OUT cmfb_out__bias cmfb_out__bias vss vss sg13_lv_nmos w=0.3u l=0.22u m=1 +MM7_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vss vss sg13_lv_nmos w=0.3u l=0.22u m=1 +MM7_CORE core__casc_src_p vb4_ctl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM8O voutp vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM9O voutn vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 +CCM_S1_0 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=25 +CM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=2 +CM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=2 +RRMN_CMFB_OUT_0 voutn RMN_CMFB_OUT_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_OUT_1 RMN_CMFB_OUT_s1 RMN_CMFB_OUT_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_OUT_2 RMN_CMFB_OUT_s2 RMN_CMFB_OUT_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_OUT_3 RMN_CMFB_OUT_s3 cmfb_out__cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_0 stg1_n RMN_CMFB_S1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_1 RMN_CMFB_S1_s1 RMN_CMFB_S1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_2 RMN_CMFB_S1_s2 RMN_CMFB_S1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_3 RMN_CMFB_S1_s3 RMN_CMFB_S1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_4 RMN_CMFB_S1_s4 RMN_CMFB_S1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_5 RMN_CMFB_S1_s5 RMN_CMFB_S1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_6 RMN_CMFB_S1_s6 RMN_CMFB_S1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_7 RMN_CMFB_S1_s7 RMN_CMFB_S1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_8 RMN_CMFB_S1_s8 RMN_CMFB_S1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_9 RMN_CMFB_S1_s9 RMN_CMFB_S1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_10 RMN_CMFB_S1_s10 RMN_CMFB_S1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_11 RMN_CMFB_S1_s11 RMN_CMFB_S1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_12 RMN_CMFB_S1_s12 RMN_CMFB_S1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_13 RMN_CMFB_S1_s13 RMN_CMFB_S1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_14 RMN_CMFB_S1_s14 RMN_CMFB_S1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_15 RMN_CMFB_S1_s15 RMN_CMFB_S1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_16 RMN_CMFB_S1_s16 RMN_CMFB_S1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_17 RMN_CMFB_S1_s17 RMN_CMFB_S1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_18 RMN_CMFB_S1_s18 RMN_CMFB_S1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_19 RMN_CMFB_S1_s19 RMN_CMFB_S1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_20 RMN_CMFB_S1_s20 RMN_CMFB_S1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_21 RMN_CMFB_S1_s21 RMN_CMFB_S1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_22 RMN_CMFB_S1_s22 RMN_CMFB_S1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_23 RMN_CMFB_S1_s23 RMN_CMFB_S1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_24 RMN_CMFB_S1_s24 RMN_CMFB_S1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_25 RMN_CMFB_S1_s25 RMN_CMFB_S1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_26 RMN_CMFB_S1_s26 RMN_CMFB_S1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_27 RMN_CMFB_S1_s27 RMN_CMFB_S1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_28 RMN_CMFB_S1_s28 RMN_CMFB_S1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_29 RMN_CMFB_S1_s29 RMN_CMFB_S1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_30 RMN_CMFB_S1_s30 RMN_CMFB_S1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_31 RMN_CMFB_S1_s31 RMN_CMFB_S1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_32 RMN_CMFB_S1_s32 RMN_CMFB_S1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_33 RMN_CMFB_S1_s33 RMN_CMFB_S1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_34 RMN_CMFB_S1_s34 RMN_CMFB_S1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_35 RMN_CMFB_S1_s35 RMN_CMFB_S1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_36 RMN_CMFB_S1_s36 RMN_CMFB_S1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_37 RMN_CMFB_S1_s37 RMN_CMFB_S1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_38 RMN_CMFB_S1_s38 RMN_CMFB_S1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_39 RMN_CMFB_S1_s39 RMN_CMFB_S1_s40 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_40 RMN_CMFB_S1_s40 RMN_CMFB_S1_s41 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_41 RMN_CMFB_S1_s41 RMN_CMFB_S1_s42 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_42 RMN_CMFB_S1_s42 RMN_CMFB_S1_s43 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_43 RMN_CMFB_S1_s43 RMN_CMFB_S1_s44 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_44 RMN_CMFB_S1_s44 RMN_CMFB_S1_s45 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_45 RMN_CMFB_S1_s45 RMN_CMFB_S1_s46 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_46 RMN_CMFB_S1_s46 RMN_CMFB_S1_s47 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_47 RMN_CMFB_S1_s47 RMN_CMFB_S1_s48 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_48 RMN_CMFB_S1_s48 RMN_CMFB_S1_s49 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_49 RMN_CMFB_S1_s49 RMN_CMFB_S1_s50 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_50 RMN_CMFB_S1_s50 RMN_CMFB_S1_s51 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_51 RMN_CMFB_S1_s51 RMN_CMFB_S1_s52 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_52 RMN_CMFB_S1_s52 RMN_CMFB_S1_s53 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_53 RMN_CMFB_S1_s53 RMN_CMFB_S1_s54 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_54 RMN_CMFB_S1_s54 RMN_CMFB_S1_s55 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_55 RMN_CMFB_S1_s55 RMN_CMFB_S1_s56 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_56 RMN_CMFB_S1_s56 RMN_CMFB_S1_s57 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_57 RMN_CMFB_S1_s57 RMN_CMFB_S1_s58 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_58 RMN_CMFB_S1_s58 RMN_CMFB_S1_s59 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_59 RMN_CMFB_S1_s59 RMN_CMFB_S1_s60 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_60 RMN_CMFB_S1_s60 RMN_CMFB_S1_s61 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_61 RMN_CMFB_S1_s61 RMN_CMFB_S1_s62 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_62 RMN_CMFB_S1_s62 RMN_CMFB_S1_s63 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_63 RMN_CMFB_S1_s63 RMN_CMFB_S1_s64 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_64 RMN_CMFB_S1_s64 RMN_CMFB_S1_s65 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_65 RMN_CMFB_S1_s65 RMN_CMFB_S1_s66 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_66 RMN_CMFB_S1_s66 RMN_CMFB_S1_s67 vss rhigh w=.5u l=84.45u m=1 b=0 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RMN_CMFB_S1_s79 RMN_CMFB_S1_s80 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_80 RMN_CMFB_S1_s80 RMN_CMFB_S1_s81 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_81 RMN_CMFB_S1_s81 RMN_CMFB_S1_s82 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_82 RMN_CMFB_S1_s82 RMN_CMFB_S1_s83 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_83 RMN_CMFB_S1_s83 RMN_CMFB_S1_s84 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_84 RMN_CMFB_S1_s84 RMN_CMFB_S1_s85 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_85 RMN_CMFB_S1_s85 RMN_CMFB_S1_s86 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_86 RMN_CMFB_S1_s86 RMN_CMFB_S1_s87 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_87 RMN_CMFB_S1_s87 RMN_CMFB_S1_s88 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_88 RMN_CMFB_S1_s88 RMN_CMFB_S1_s89 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_89 RMN_CMFB_S1_s89 RMN_CMFB_S1_s90 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_90 RMN_CMFB_S1_s90 RMN_CMFB_S1_s91 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_91 RMN_CMFB_S1_s91 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RMN_CMFB_S1_s104 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_104 RMN_CMFB_S1_s104 RMN_CMFB_S1_s105 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_105 RMN_CMFB_S1_s105 RMN_CMFB_S1_s106 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_106 RMN_CMFB_S1_s106 RMN_CMFB_S1_s107 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_107 RMN_CMFB_S1_s107 RMN_CMFB_S1_s108 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_108 RMN_CMFB_S1_s108 RMN_CMFB_S1_s109 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_109 RMN_CMFB_S1_s109 RMN_CMFB_S1_s110 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_110 RMN_CMFB_S1_s110 RMN_CMFB_S1_s111 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_111 RMN_CMFB_S1_s111 RMN_CMFB_S1_s112 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_112 RMN_CMFB_S1_s112 RMN_CMFB_S1_s113 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_113 RMN_CMFB_S1_s113 RMN_CMFB_S1_s114 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_114 RMN_CMFB_S1_s114 RMN_CMFB_S1_s115 vss rhigh w=.5u l=84.45u m=1 b=0 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RMN_CMFB_S1_s139 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_139 RMN_CMFB_S1_s139 RMN_CMFB_S1_s140 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_140 RMN_CMFB_S1_s140 RMN_CMFB_S1_s141 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_141 RMN_CMFB_S1_s141 RMN_CMFB_S1_s142 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_142 RMN_CMFB_S1_s142 RMN_CMFB_S1_s143 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_143 RMN_CMFB_S1_s143 RMN_CMFB_S1_s144 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_144 RMN_CMFB_S1_s144 RMN_CMFB_S1_s145 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_145 RMN_CMFB_S1_s145 RMN_CMFB_S1_s146 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_146 RMN_CMFB_S1_s146 RMN_CMFB_S1_s147 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_147 RMN_CMFB_S1_s147 RMN_CMFB_S1_s148 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_148 RMN_CMFB_S1_s148 RMN_CMFB_S1_s149 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_149 RMN_CMFB_S1_s149 RMN_CMFB_S1_s150 vss rhigh w=.5u l=84.45u m=1 b=0 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RMN_CMFB_S1_s174 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_174 RMN_CMFB_S1_s174 RMN_CMFB_S1_s175 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_175 RMN_CMFB_S1_s175 RMN_CMFB_S1_s176 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_176 RMN_CMFB_S1_s176 RMN_CMFB_S1_s177 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_177 RMN_CMFB_S1_s177 RMN_CMFB_S1_s178 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_178 RMN_CMFB_S1_s178 RMN_CMFB_S1_s179 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_179 RMN_CMFB_S1_s179 RMN_CMFB_S1_s180 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_180 RMN_CMFB_S1_s180 RMN_CMFB_S1_s181 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_181 RMN_CMFB_S1_s181 RMN_CMFB_S1_s182 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_182 RMN_CMFB_S1_s182 RMN_CMFB_S1_s183 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_183 RMN_CMFB_S1_s183 RMN_CMFB_S1_s184 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_184 RMN_CMFB_S1_s184 RMN_CMFB_S1_s185 vss rhigh w=.5u l=84.45u m=1 b=0 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w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_197 RMN_CMFB_S1_s197 RMN_CMFB_S1_s198 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_198 RMN_CMFB_S1_s198 RMN_CMFB_S1_s199 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_CMFB_S1_199 RMN_CMFB_S1_s199 cmfb_s1__cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_OUT_0 cmfb_out__cm_sense RMP_CMFB_OUT_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_OUT_1 RMP_CMFB_OUT_s1 RMP_CMFB_OUT_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_OUT_2 RMP_CMFB_OUT_s2 RMP_CMFB_OUT_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_OUT_3 RMP_CMFB_OUT_s3 voutp vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_0 cmfb_s1__cm_sense RMP_CMFB_S1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_1 RMP_CMFB_S1_s1 RMP_CMFB_S1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_2 RMP_CMFB_S1_s2 RMP_CMFB_S1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_3 RMP_CMFB_S1_s3 RMP_CMFB_S1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_4 RMP_CMFB_S1_s4 RMP_CMFB_S1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_5 RMP_CMFB_S1_s5 RMP_CMFB_S1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_6 RMP_CMFB_S1_s6 RMP_CMFB_S1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_7 RMP_CMFB_S1_s7 RMP_CMFB_S1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_8 RMP_CMFB_S1_s8 RMP_CMFB_S1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_9 RMP_CMFB_S1_s9 RMP_CMFB_S1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_10 RMP_CMFB_S1_s10 RMP_CMFB_S1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_11 RMP_CMFB_S1_s11 RMP_CMFB_S1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_12 RMP_CMFB_S1_s12 RMP_CMFB_S1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_13 RMP_CMFB_S1_s13 RMP_CMFB_S1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_14 RMP_CMFB_S1_s14 RMP_CMFB_S1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_15 RMP_CMFB_S1_s15 RMP_CMFB_S1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_16 RMP_CMFB_S1_s16 RMP_CMFB_S1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_17 RMP_CMFB_S1_s17 RMP_CMFB_S1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_18 RMP_CMFB_S1_s18 RMP_CMFB_S1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_19 RMP_CMFB_S1_s19 RMP_CMFB_S1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_20 RMP_CMFB_S1_s20 RMP_CMFB_S1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_21 RMP_CMFB_S1_s21 RMP_CMFB_S1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_22 RMP_CMFB_S1_s22 RMP_CMFB_S1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_23 RMP_CMFB_S1_s23 RMP_CMFB_S1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_24 RMP_CMFB_S1_s24 RMP_CMFB_S1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_25 RMP_CMFB_S1_s25 RMP_CMFB_S1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_26 RMP_CMFB_S1_s26 RMP_CMFB_S1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_27 RMP_CMFB_S1_s27 RMP_CMFB_S1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_28 RMP_CMFB_S1_s28 RMP_CMFB_S1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_29 RMP_CMFB_S1_s29 RMP_CMFB_S1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_30 RMP_CMFB_S1_s30 RMP_CMFB_S1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_31 RMP_CMFB_S1_s31 RMP_CMFB_S1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_32 RMP_CMFB_S1_s32 RMP_CMFB_S1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_33 RMP_CMFB_S1_s33 RMP_CMFB_S1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_34 RMP_CMFB_S1_s34 RMP_CMFB_S1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_35 RMP_CMFB_S1_s35 RMP_CMFB_S1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_36 RMP_CMFB_S1_s36 RMP_CMFB_S1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_37 RMP_CMFB_S1_s37 RMP_CMFB_S1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_38 RMP_CMFB_S1_s38 RMP_CMFB_S1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_39 RMP_CMFB_S1_s39 RMP_CMFB_S1_s40 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_40 RMP_CMFB_S1_s40 RMP_CMFB_S1_s41 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_41 RMP_CMFB_S1_s41 RMP_CMFB_S1_s42 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_42 RMP_CMFB_S1_s42 RMP_CMFB_S1_s43 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_43 RMP_CMFB_S1_s43 RMP_CMFB_S1_s44 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_44 RMP_CMFB_S1_s44 RMP_CMFB_S1_s45 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_45 RMP_CMFB_S1_s45 RMP_CMFB_S1_s46 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_46 RMP_CMFB_S1_s46 RMP_CMFB_S1_s47 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_47 RMP_CMFB_S1_s47 RMP_CMFB_S1_s48 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_48 RMP_CMFB_S1_s48 RMP_CMFB_S1_s49 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_49 RMP_CMFB_S1_s49 RMP_CMFB_S1_s50 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_50 RMP_CMFB_S1_s50 RMP_CMFB_S1_s51 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_51 RMP_CMFB_S1_s51 RMP_CMFB_S1_s52 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_52 RMP_CMFB_S1_s52 RMP_CMFB_S1_s53 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_53 RMP_CMFB_S1_s53 RMP_CMFB_S1_s54 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_54 RMP_CMFB_S1_s54 RMP_CMFB_S1_s55 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_55 RMP_CMFB_S1_s55 RMP_CMFB_S1_s56 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_56 RMP_CMFB_S1_s56 RMP_CMFB_S1_s57 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_57 RMP_CMFB_S1_s57 RMP_CMFB_S1_s58 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_58 RMP_CMFB_S1_s58 RMP_CMFB_S1_s59 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_59 RMP_CMFB_S1_s59 RMP_CMFB_S1_s60 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_60 RMP_CMFB_S1_s60 RMP_CMFB_S1_s61 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_61 RMP_CMFB_S1_s61 RMP_CMFB_S1_s62 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_62 RMP_CMFB_S1_s62 RMP_CMFB_S1_s63 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_63 RMP_CMFB_S1_s63 RMP_CMFB_S1_s64 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_64 RMP_CMFB_S1_s64 RMP_CMFB_S1_s65 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_65 RMP_CMFB_S1_s65 RMP_CMFB_S1_s66 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_66 RMP_CMFB_S1_s66 RMP_CMFB_S1_s67 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_67 RMP_CMFB_S1_s67 RMP_CMFB_S1_s68 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_68 RMP_CMFB_S1_s68 RMP_CMFB_S1_s69 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_69 RMP_CMFB_S1_s69 RMP_CMFB_S1_s70 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_70 RMP_CMFB_S1_s70 RMP_CMFB_S1_s71 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_71 RMP_CMFB_S1_s71 RMP_CMFB_S1_s72 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_72 RMP_CMFB_S1_s72 RMP_CMFB_S1_s73 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_73 RMP_CMFB_S1_s73 RMP_CMFB_S1_s74 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_74 RMP_CMFB_S1_s74 RMP_CMFB_S1_s75 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_75 RMP_CMFB_S1_s75 RMP_CMFB_S1_s76 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_76 RMP_CMFB_S1_s76 RMP_CMFB_S1_s77 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_77 RMP_CMFB_S1_s77 RMP_CMFB_S1_s78 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_78 RMP_CMFB_S1_s78 RMP_CMFB_S1_s79 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_79 RMP_CMFB_S1_s79 RMP_CMFB_S1_s80 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_80 RMP_CMFB_S1_s80 RMP_CMFB_S1_s81 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_81 RMP_CMFB_S1_s81 RMP_CMFB_S1_s82 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_82 RMP_CMFB_S1_s82 RMP_CMFB_S1_s83 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_83 RMP_CMFB_S1_s83 RMP_CMFB_S1_s84 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_84 RMP_CMFB_S1_s84 RMP_CMFB_S1_s85 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_85 RMP_CMFB_S1_s85 RMP_CMFB_S1_s86 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_86 RMP_CMFB_S1_s86 RMP_CMFB_S1_s87 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_87 RMP_CMFB_S1_s87 RMP_CMFB_S1_s88 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_88 RMP_CMFB_S1_s88 RMP_CMFB_S1_s89 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_89 RMP_CMFB_S1_s89 RMP_CMFB_S1_s90 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_90 RMP_CMFB_S1_s90 RMP_CMFB_S1_s91 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_91 RMP_CMFB_S1_s91 RMP_CMFB_S1_s92 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_92 RMP_CMFB_S1_s92 RMP_CMFB_S1_s93 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_93 RMP_CMFB_S1_s93 RMP_CMFB_S1_s94 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_94 RMP_CMFB_S1_s94 RMP_CMFB_S1_s95 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_95 RMP_CMFB_S1_s95 RMP_CMFB_S1_s96 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_96 RMP_CMFB_S1_s96 RMP_CMFB_S1_s97 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_97 RMP_CMFB_S1_s97 RMP_CMFB_S1_s98 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_98 RMP_CMFB_S1_s98 RMP_CMFB_S1_s99 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_99 RMP_CMFB_S1_s99 RMP_CMFB_S1_s100 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_100 RMP_CMFB_S1_s100 RMP_CMFB_S1_s101 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_101 RMP_CMFB_S1_s101 RMP_CMFB_S1_s102 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_102 RMP_CMFB_S1_s102 RMP_CMFB_S1_s103 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_103 RMP_CMFB_S1_s103 RMP_CMFB_S1_s104 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_104 RMP_CMFB_S1_s104 RMP_CMFB_S1_s105 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_105 RMP_CMFB_S1_s105 RMP_CMFB_S1_s106 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_106 RMP_CMFB_S1_s106 RMP_CMFB_S1_s107 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_107 RMP_CMFB_S1_s107 RMP_CMFB_S1_s108 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_108 RMP_CMFB_S1_s108 RMP_CMFB_S1_s109 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_109 RMP_CMFB_S1_s109 RMP_CMFB_S1_s110 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_110 RMP_CMFB_S1_s110 RMP_CMFB_S1_s111 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_111 RMP_CMFB_S1_s111 RMP_CMFB_S1_s112 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_112 RMP_CMFB_S1_s112 RMP_CMFB_S1_s113 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_113 RMP_CMFB_S1_s113 RMP_CMFB_S1_s114 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_114 RMP_CMFB_S1_s114 RMP_CMFB_S1_s115 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_115 RMP_CMFB_S1_s115 RMP_CMFB_S1_s116 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_116 RMP_CMFB_S1_s116 RMP_CMFB_S1_s117 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_117 RMP_CMFB_S1_s117 RMP_CMFB_S1_s118 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_118 RMP_CMFB_S1_s118 RMP_CMFB_S1_s119 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_119 RMP_CMFB_S1_s119 RMP_CMFB_S1_s120 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_120 RMP_CMFB_S1_s120 RMP_CMFB_S1_s121 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_121 RMP_CMFB_S1_s121 RMP_CMFB_S1_s122 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_122 RMP_CMFB_S1_s122 RMP_CMFB_S1_s123 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_123 RMP_CMFB_S1_s123 RMP_CMFB_S1_s124 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_124 RMP_CMFB_S1_s124 RMP_CMFB_S1_s125 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_125 RMP_CMFB_S1_s125 RMP_CMFB_S1_s126 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_126 RMP_CMFB_S1_s126 RMP_CMFB_S1_s127 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_127 RMP_CMFB_S1_s127 RMP_CMFB_S1_s128 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_128 RMP_CMFB_S1_s128 RMP_CMFB_S1_s129 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_129 RMP_CMFB_S1_s129 RMP_CMFB_S1_s130 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_130 RMP_CMFB_S1_s130 RMP_CMFB_S1_s131 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_131 RMP_CMFB_S1_s131 RMP_CMFB_S1_s132 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_132 RMP_CMFB_S1_s132 RMP_CMFB_S1_s133 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_133 RMP_CMFB_S1_s133 RMP_CMFB_S1_s134 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_134 RMP_CMFB_S1_s134 RMP_CMFB_S1_s135 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_135 RMP_CMFB_S1_s135 RMP_CMFB_S1_s136 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_136 RMP_CMFB_S1_s136 RMP_CMFB_S1_s137 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_137 RMP_CMFB_S1_s137 RMP_CMFB_S1_s138 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_138 RMP_CMFB_S1_s138 RMP_CMFB_S1_s139 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_139 RMP_CMFB_S1_s139 RMP_CMFB_S1_s140 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_140 RMP_CMFB_S1_s140 RMP_CMFB_S1_s141 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_141 RMP_CMFB_S1_s141 RMP_CMFB_S1_s142 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_142 RMP_CMFB_S1_s142 RMP_CMFB_S1_s143 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_143 RMP_CMFB_S1_s143 RMP_CMFB_S1_s144 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_144 RMP_CMFB_S1_s144 RMP_CMFB_S1_s145 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_145 RMP_CMFB_S1_s145 RMP_CMFB_S1_s146 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_146 RMP_CMFB_S1_s146 RMP_CMFB_S1_s147 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_147 RMP_CMFB_S1_s147 RMP_CMFB_S1_s148 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_148 RMP_CMFB_S1_s148 RMP_CMFB_S1_s149 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_149 RMP_CMFB_S1_s149 RMP_CMFB_S1_s150 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_150 RMP_CMFB_S1_s150 RMP_CMFB_S1_s151 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_151 RMP_CMFB_S1_s151 RMP_CMFB_S1_s152 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_152 RMP_CMFB_S1_s152 RMP_CMFB_S1_s153 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_153 RMP_CMFB_S1_s153 RMP_CMFB_S1_s154 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_154 RMP_CMFB_S1_s154 RMP_CMFB_S1_s155 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_155 RMP_CMFB_S1_s155 RMP_CMFB_S1_s156 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_156 RMP_CMFB_S1_s156 RMP_CMFB_S1_s157 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_157 RMP_CMFB_S1_s157 RMP_CMFB_S1_s158 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_158 RMP_CMFB_S1_s158 RMP_CMFB_S1_s159 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_159 RMP_CMFB_S1_s159 RMP_CMFB_S1_s160 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_160 RMP_CMFB_S1_s160 RMP_CMFB_S1_s161 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_161 RMP_CMFB_S1_s161 RMP_CMFB_S1_s162 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_162 RMP_CMFB_S1_s162 RMP_CMFB_S1_s163 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_163 RMP_CMFB_S1_s163 RMP_CMFB_S1_s164 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_164 RMP_CMFB_S1_s164 RMP_CMFB_S1_s165 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_165 RMP_CMFB_S1_s165 RMP_CMFB_S1_s166 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_166 RMP_CMFB_S1_s166 RMP_CMFB_S1_s167 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_167 RMP_CMFB_S1_s167 RMP_CMFB_S1_s168 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_168 RMP_CMFB_S1_s168 RMP_CMFB_S1_s169 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_169 RMP_CMFB_S1_s169 RMP_CMFB_S1_s170 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_170 RMP_CMFB_S1_s170 RMP_CMFB_S1_s171 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_171 RMP_CMFB_S1_s171 RMP_CMFB_S1_s172 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_172 RMP_CMFB_S1_s172 RMP_CMFB_S1_s173 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_173 RMP_CMFB_S1_s173 RMP_CMFB_S1_s174 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_174 RMP_CMFB_S1_s174 RMP_CMFB_S1_s175 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_175 RMP_CMFB_S1_s175 RMP_CMFB_S1_s176 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_176 RMP_CMFB_S1_s176 RMP_CMFB_S1_s177 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_177 RMP_CMFB_S1_s177 RMP_CMFB_S1_s178 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_178 RMP_CMFB_S1_s178 RMP_CMFB_S1_s179 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_179 RMP_CMFB_S1_s179 RMP_CMFB_S1_s180 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_180 RMP_CMFB_S1_s180 RMP_CMFB_S1_s181 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_181 RMP_CMFB_S1_s181 RMP_CMFB_S1_s182 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_182 RMP_CMFB_S1_s182 RMP_CMFB_S1_s183 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_183 RMP_CMFB_S1_s183 RMP_CMFB_S1_s184 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_184 RMP_CMFB_S1_s184 RMP_CMFB_S1_s185 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_185 RMP_CMFB_S1_s185 RMP_CMFB_S1_s186 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_186 RMP_CMFB_S1_s186 RMP_CMFB_S1_s187 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_187 RMP_CMFB_S1_s187 RMP_CMFB_S1_s188 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_188 RMP_CMFB_S1_s188 RMP_CMFB_S1_s189 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_189 RMP_CMFB_S1_s189 RMP_CMFB_S1_s190 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_190 RMP_CMFB_S1_s190 RMP_CMFB_S1_s191 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_191 RMP_CMFB_S1_s191 RMP_CMFB_S1_s192 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_192 RMP_CMFB_S1_s192 RMP_CMFB_S1_s193 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_193 RMP_CMFB_S1_s193 RMP_CMFB_S1_s194 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_194 RMP_CMFB_S1_s194 RMP_CMFB_S1_s195 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_195 RMP_CMFB_S1_s195 RMP_CMFB_S1_s196 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_196 RMP_CMFB_S1_s196 RMP_CMFB_S1_s197 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_197 RMP_CMFB_S1_s197 RMP_CMFB_S1_s198 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_198 RMP_CMFB_S1_s198 RMP_CMFB_S1_s199 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_CMFB_S1_199 RMP_CMFB_S1_s199 stg1_p vss rhigh w=.5u l=84.45u m=1 b=0 .ends amp_035_fan_chopper_cmfb_dual diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.spice index 888c99b071c4e35330ee93149533f958306d8c8f..bd0899894acd61df3defa4d524709e9ff69a9d13 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.spice @@ -1,516 +1,452 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt amp_035_fan_chopper_cmfb_dual vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 vref_out vref_s1 stg1_p stg1_n vb4o vb4_ctl -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM10_CORE stg1_n core__vb3 core__casc_src_n well_0 sg13_lv_pmos w=10u l=0.3u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM11_CORE stg1_p core__vb3 core__casc_src_p well_1 sg13_lv_pmos w=10u l=0.3u m=1 -XT2 vss sub ptap1 A=4e-12 P=8e-6 -XM12_CORE stg1_p core__vb2 core__fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -XT3 vss sub ptap1 A=4e-12 P=8e-6 -XM13_CORE stg1_n core__vb2 core__fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -XT4 vss sub ptap1 A=4e-12 P=8e-6 -XM14_CORE voutp core__g2_p vss sub sg13_lv_nmos w=20u l=0.25u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM15_CORE voutn core__g2_n vss sub sg13_lv_nmos w=20u l=0.25u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM16_CORE stg1_n vdd core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT7 vdd well_7 ntap1 A=4e-12 P=8e-6 -XM17_CORE core__g2_n vss stg1_n well_7 sg13_lv_pmos w=2u l=0.13u m=1 -XT8 vss sub ptap1 A=4e-12 P=8e-6 -XM18_CORE stg1_p vdd core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT9 vdd well_9 ntap1 A=4e-12 P=8e-6 -XM19_CORE core__g2_p vss stg1_p well_9 sg13_lv_pmos w=2u l=0.13u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM1_CMFB_OUT cmfb_out__ptail cmfb_out__bias vdd well_10 sg13_lv_pmos w=0.33u l=0.26u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM1_CMFB_S1 cmfb_s1__ptail cmfb_s1__bias vdd well_11 sg13_lv_pmos w=0.33u l=0.26u m=1 -XT12 vdd well_12 ntap1 A=4e-12 P=8e-6 -XM1_CORE core__tail vb4_ctl vdd well_12 sg13_lv_pmos w=20u l=1u m=1 -XT13 vss sub ptap1 A=4e-12 P=8e-6 -XM20_CORE stg1_p vss core__g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT14 vdd well_14 ntap1 A=4e-12 P=8e-6 -XM21_CORE core__g2_n vdd stg1_p well_14 sg13_lv_pmos w=2u l=0.13u m=1 -XT15 vss sub ptap1 A=4e-12 P=8e-6 -XM22_CORE stg1_n vss core__g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT16 vdd well_16 ntap1 A=4e-12 P=8e-6 -XM23_CORE core__g2_p vdd stg1_n well_16 sg13_lv_pmos w=2u l=0.13u m=1 -XT17 vss sub ptap1 A=4e-12 P=8e-6 -XM2_CMFB_OUT vb4o cmfb_out__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT18 vss sub ptap1 A=4e-12 P=8e-6 -XM2_CMFB_S1 vb4_ctl cmfb_s1__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM2_CORE core__fold_p vinp core__tail well_19 sg13_lv_pmos w=20u l=0.5u m=1 -XT20 vdd well_20 ntap1 A=4e-12 P=8e-6 -XM3_CMFB_OUT cmfb_out__bias cmfb_out__bias vdd well_20 sg13_lv_pmos w=0.88u l=0.26u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM3_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vdd well_21 sg13_lv_pmos w=0.88u l=0.26u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM3_CORE core__fold_n vinn core__tail well_22 sg13_lv_pmos w=20u l=0.5u m=1 -XT23 vdd well_23 ntap1 A=4e-12 P=8e-6 -XM4_CMFB_OUT cmfb_out__mirr cmfb_out__cm_sense cmfb_out__ptail well_23 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -XM4_CMFB_S1 cmfb_s1__mirr cmfb_s1__cm_sense cmfb_s1__ptail well_24 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT25 vss sub ptap1 A=4e-12 P=8e-6 -XM4_CORE core__fold_p core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -XT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -XM5_CMFB_OUT vb4o vref_out cmfb_out__ptail well_26 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT27 vdd well_27 ntap1 A=4e-12 P=8e-6 -XM5_CMFB_S1 vb4_ctl vref_s1 cmfb_s1__ptail well_27 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT28 vss sub ptap1 A=4e-12 P=8e-6 -XM5_CORE core__fold_n core__vb1 vss sub sg13_lv_nmos w=10u l=1u m=1 -XT29 vss sub ptap1 A=4e-12 P=8e-6 -XM6_CMFB_OUT cmfb_out__mirr cmfb_out__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT30 vss sub ptap1 A=4e-12 P=8e-6 -XM6_CMFB_S1 cmfb_s1__mirr cmfb_s1__mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT31 vdd well_31 ntap1 A=4e-12 P=8e-6 -XM6_CORE core__casc_src_n vb4_ctl vdd well_31 sg13_lv_pmos w=10u l=1u m=1 -XT32 vss sub ptap1 A=4e-12 P=8e-6 -XM7_CMFB_OUT cmfb_out__bias cmfb_out__bias vss sub sg13_lv_nmos w=0.3u l=0.22u m=1 -XT33 vss sub ptap1 A=4e-12 P=8e-6 -XM7_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vss sub sg13_lv_nmos w=0.3u l=0.22u m=1 -XT34 vdd well_34 ntap1 A=4e-12 P=8e-6 -XM7_CORE core__casc_src_p vb4_ctl vdd well_34 sg13_lv_pmos w=10u l=1u m=1 -XT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -XM8O voutp vb4o vdd well_35 sg13_lv_pmos w=20u l=1u m=1 -XT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -XM9O voutn vb4o vdd well_36 sg13_lv_pmos w=20u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 -XCCM_S1_0 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_1 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_2 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_3 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_4 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_5 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_6 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_7 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_8 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_9 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_10 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_11 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_12 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_13 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_14 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_15 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_16 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_17 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_18 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_19 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_20 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_21 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_22 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_23 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCCM_S1_24 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=1 -XCM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -XCM1_CORE_1 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=1 -XCM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -XCM2_CORE_1 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=1 -XRMN_CMFB_OUT_0 voutn RMN_CMFB_OUT_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_OUT_1 RMN_CMFB_OUT_s1 RMN_CMFB_OUT_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_OUT_2 RMN_CMFB_OUT_s2 RMN_CMFB_OUT_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_OUT_3 RMN_CMFB_OUT_s3 cmfb_out__cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_0 stg1_n RMN_CMFB_S1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_1 RMN_CMFB_S1_s1 RMN_CMFB_S1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_2 RMN_CMFB_S1_s2 RMN_CMFB_S1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_3 RMN_CMFB_S1_s3 RMN_CMFB_S1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_4 RMN_CMFB_S1_s4 RMN_CMFB_S1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_5 RMN_CMFB_S1_s5 RMN_CMFB_S1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_6 RMN_CMFB_S1_s6 RMN_CMFB_S1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_7 RMN_CMFB_S1_s7 RMN_CMFB_S1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_8 RMN_CMFB_S1_s8 RMN_CMFB_S1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_9 RMN_CMFB_S1_s9 RMN_CMFB_S1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_10 RMN_CMFB_S1_s10 RMN_CMFB_S1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_11 RMN_CMFB_S1_s11 RMN_CMFB_S1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_12 RMN_CMFB_S1_s12 RMN_CMFB_S1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_13 RMN_CMFB_S1_s13 RMN_CMFB_S1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_14 RMN_CMFB_S1_s14 RMN_CMFB_S1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_15 RMN_CMFB_S1_s15 RMN_CMFB_S1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_16 RMN_CMFB_S1_s16 RMN_CMFB_S1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_17 RMN_CMFB_S1_s17 RMN_CMFB_S1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_18 RMN_CMFB_S1_s18 RMN_CMFB_S1_s19 sub rhigh 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RMN_CMFB_S1_s55 RMN_CMFB_S1_s56 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_56 RMN_CMFB_S1_s56 RMN_CMFB_S1_s57 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_57 RMN_CMFB_S1_s57 RMN_CMFB_S1_s58 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_58 RMN_CMFB_S1_s58 RMN_CMFB_S1_s59 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_59 RMN_CMFB_S1_s59 RMN_CMFB_S1_s60 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_60 RMN_CMFB_S1_s60 RMN_CMFB_S1_s61 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_61 RMN_CMFB_S1_s61 RMN_CMFB_S1_s62 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_62 RMN_CMFB_S1_s62 RMN_CMFB_S1_s63 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_63 RMN_CMFB_S1_s63 RMN_CMFB_S1_s64 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_64 RMN_CMFB_S1_s64 RMN_CMFB_S1_s65 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_65 RMN_CMFB_S1_s65 RMN_CMFB_S1_s66 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_66 RMN_CMFB_S1_s66 RMN_CMFB_S1_s67 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_67 RMN_CMFB_S1_s67 RMN_CMFB_S1_s68 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_68 RMN_CMFB_S1_s68 RMN_CMFB_S1_s69 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_69 RMN_CMFB_S1_s69 RMN_CMFB_S1_s70 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_70 RMN_CMFB_S1_s70 RMN_CMFB_S1_s71 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_71 RMN_CMFB_S1_s71 RMN_CMFB_S1_s72 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_72 RMN_CMFB_S1_s72 RMN_CMFB_S1_s73 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_73 RMN_CMFB_S1_s73 RMN_CMFB_S1_s74 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_74 RMN_CMFB_S1_s74 RMN_CMFB_S1_s75 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_75 RMN_CMFB_S1_s75 RMN_CMFB_S1_s76 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_76 RMN_CMFB_S1_s76 RMN_CMFB_S1_s77 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_77 RMN_CMFB_S1_s77 RMN_CMFB_S1_s78 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_78 RMN_CMFB_S1_s78 RMN_CMFB_S1_s79 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_CMFB_S1_79 RMN_CMFB_S1_s79 RMN_CMFB_S1_s80 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RMP_CMFB_S1_s5 RMP_CMFB_S1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_6 RMP_CMFB_S1_s6 RMP_CMFB_S1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_7 RMP_CMFB_S1_s7 RMP_CMFB_S1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_8 RMP_CMFB_S1_s8 RMP_CMFB_S1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_9 RMP_CMFB_S1_s9 RMP_CMFB_S1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_10 RMP_CMFB_S1_s10 RMP_CMFB_S1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_11 RMP_CMFB_S1_s11 RMP_CMFB_S1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_12 RMP_CMFB_S1_s12 RMP_CMFB_S1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_13 RMP_CMFB_S1_s13 RMP_CMFB_S1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_14 RMP_CMFB_S1_s14 RMP_CMFB_S1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_15 RMP_CMFB_S1_s15 RMP_CMFB_S1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_16 RMP_CMFB_S1_s16 RMP_CMFB_S1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_17 RMP_CMFB_S1_s17 RMP_CMFB_S1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_18 RMP_CMFB_S1_s18 RMP_CMFB_S1_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_19 RMP_CMFB_S1_s19 RMP_CMFB_S1_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_20 RMP_CMFB_S1_s20 RMP_CMFB_S1_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_21 RMP_CMFB_S1_s21 RMP_CMFB_S1_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_22 RMP_CMFB_S1_s22 RMP_CMFB_S1_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_23 RMP_CMFB_S1_s23 RMP_CMFB_S1_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_24 RMP_CMFB_S1_s24 RMP_CMFB_S1_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_25 RMP_CMFB_S1_s25 RMP_CMFB_S1_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_26 RMP_CMFB_S1_s26 RMP_CMFB_S1_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_27 RMP_CMFB_S1_s27 RMP_CMFB_S1_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_28 RMP_CMFB_S1_s28 RMP_CMFB_S1_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_29 RMP_CMFB_S1_s29 RMP_CMFB_S1_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_30 RMP_CMFB_S1_s30 RMP_CMFB_S1_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_31 RMP_CMFB_S1_s31 RMP_CMFB_S1_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_32 RMP_CMFB_S1_s32 RMP_CMFB_S1_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_33 RMP_CMFB_S1_s33 RMP_CMFB_S1_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_34 RMP_CMFB_S1_s34 RMP_CMFB_S1_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_35 RMP_CMFB_S1_s35 RMP_CMFB_S1_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_36 RMP_CMFB_S1_s36 RMP_CMFB_S1_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_37 RMP_CMFB_S1_s37 RMP_CMFB_S1_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_38 RMP_CMFB_S1_s38 RMP_CMFB_S1_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_39 RMP_CMFB_S1_s39 RMP_CMFB_S1_s40 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_40 RMP_CMFB_S1_s40 RMP_CMFB_S1_s41 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_41 RMP_CMFB_S1_s41 RMP_CMFB_S1_s42 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_42 RMP_CMFB_S1_s42 RMP_CMFB_S1_s43 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_43 RMP_CMFB_S1_s43 RMP_CMFB_S1_s44 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_44 RMP_CMFB_S1_s44 RMP_CMFB_S1_s45 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_45 RMP_CMFB_S1_s45 RMP_CMFB_S1_s46 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_46 RMP_CMFB_S1_s46 RMP_CMFB_S1_s47 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_47 RMP_CMFB_S1_s47 RMP_CMFB_S1_s48 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_48 RMP_CMFB_S1_s48 RMP_CMFB_S1_s49 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_49 RMP_CMFB_S1_s49 RMP_CMFB_S1_s50 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_50 RMP_CMFB_S1_s50 RMP_CMFB_S1_s51 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_51 RMP_CMFB_S1_s51 RMP_CMFB_S1_s52 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_52 RMP_CMFB_S1_s52 RMP_CMFB_S1_s53 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_53 RMP_CMFB_S1_s53 RMP_CMFB_S1_s54 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_54 RMP_CMFB_S1_s54 RMP_CMFB_S1_s55 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_55 RMP_CMFB_S1_s55 RMP_CMFB_S1_s56 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_56 RMP_CMFB_S1_s56 RMP_CMFB_S1_s57 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_57 RMP_CMFB_S1_s57 RMP_CMFB_S1_s58 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_58 RMP_CMFB_S1_s58 RMP_CMFB_S1_s59 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_59 RMP_CMFB_S1_s59 RMP_CMFB_S1_s60 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_60 RMP_CMFB_S1_s60 RMP_CMFB_S1_s61 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_61 RMP_CMFB_S1_s61 RMP_CMFB_S1_s62 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_62 RMP_CMFB_S1_s62 RMP_CMFB_S1_s63 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_63 RMP_CMFB_S1_s63 RMP_CMFB_S1_s64 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_64 RMP_CMFB_S1_s64 RMP_CMFB_S1_s65 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_65 RMP_CMFB_S1_s65 RMP_CMFB_S1_s66 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_66 RMP_CMFB_S1_s66 RMP_CMFB_S1_s67 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_67 RMP_CMFB_S1_s67 RMP_CMFB_S1_s68 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_68 RMP_CMFB_S1_s68 RMP_CMFB_S1_s69 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_69 RMP_CMFB_S1_s69 RMP_CMFB_S1_s70 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_70 RMP_CMFB_S1_s70 RMP_CMFB_S1_s71 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_71 RMP_CMFB_S1_s71 RMP_CMFB_S1_s72 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_72 RMP_CMFB_S1_s72 RMP_CMFB_S1_s73 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_73 RMP_CMFB_S1_s73 RMP_CMFB_S1_s74 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_74 RMP_CMFB_S1_s74 RMP_CMFB_S1_s75 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_75 RMP_CMFB_S1_s75 RMP_CMFB_S1_s76 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_76 RMP_CMFB_S1_s76 RMP_CMFB_S1_s77 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_77 RMP_CMFB_S1_s77 RMP_CMFB_S1_s78 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_78 RMP_CMFB_S1_s78 RMP_CMFB_S1_s79 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_79 RMP_CMFB_S1_s79 RMP_CMFB_S1_s80 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_80 RMP_CMFB_S1_s80 RMP_CMFB_S1_s81 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_81 RMP_CMFB_S1_s81 RMP_CMFB_S1_s82 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_82 RMP_CMFB_S1_s82 RMP_CMFB_S1_s83 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_83 RMP_CMFB_S1_s83 RMP_CMFB_S1_s84 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_84 RMP_CMFB_S1_s84 RMP_CMFB_S1_s85 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_85 RMP_CMFB_S1_s85 RMP_CMFB_S1_s86 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_86 RMP_CMFB_S1_s86 RMP_CMFB_S1_s87 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_87 RMP_CMFB_S1_s87 RMP_CMFB_S1_s88 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_88 RMP_CMFB_S1_s88 RMP_CMFB_S1_s89 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_89 RMP_CMFB_S1_s89 RMP_CMFB_S1_s90 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_90 RMP_CMFB_S1_s90 RMP_CMFB_S1_s91 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_91 RMP_CMFB_S1_s91 RMP_CMFB_S1_s92 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_92 RMP_CMFB_S1_s92 RMP_CMFB_S1_s93 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_93 RMP_CMFB_S1_s93 RMP_CMFB_S1_s94 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_94 RMP_CMFB_S1_s94 RMP_CMFB_S1_s95 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_95 RMP_CMFB_S1_s95 RMP_CMFB_S1_s96 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_96 RMP_CMFB_S1_s96 RMP_CMFB_S1_s97 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_97 RMP_CMFB_S1_s97 RMP_CMFB_S1_s98 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_98 RMP_CMFB_S1_s98 RMP_CMFB_S1_s99 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_99 RMP_CMFB_S1_s99 RMP_CMFB_S1_s100 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_100 RMP_CMFB_S1_s100 RMP_CMFB_S1_s101 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_101 RMP_CMFB_S1_s101 RMP_CMFB_S1_s102 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_102 RMP_CMFB_S1_s102 RMP_CMFB_S1_s103 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_103 RMP_CMFB_S1_s103 RMP_CMFB_S1_s104 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_104 RMP_CMFB_S1_s104 RMP_CMFB_S1_s105 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_105 RMP_CMFB_S1_s105 RMP_CMFB_S1_s106 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_106 RMP_CMFB_S1_s106 RMP_CMFB_S1_s107 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_107 RMP_CMFB_S1_s107 RMP_CMFB_S1_s108 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_108 RMP_CMFB_S1_s108 RMP_CMFB_S1_s109 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_109 RMP_CMFB_S1_s109 RMP_CMFB_S1_s110 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_110 RMP_CMFB_S1_s110 RMP_CMFB_S1_s111 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_111 RMP_CMFB_S1_s111 RMP_CMFB_S1_s112 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_112 RMP_CMFB_S1_s112 RMP_CMFB_S1_s113 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_113 RMP_CMFB_S1_s113 RMP_CMFB_S1_s114 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_114 RMP_CMFB_S1_s114 RMP_CMFB_S1_s115 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_115 RMP_CMFB_S1_s115 RMP_CMFB_S1_s116 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_116 RMP_CMFB_S1_s116 RMP_CMFB_S1_s117 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_117 RMP_CMFB_S1_s117 RMP_CMFB_S1_s118 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_118 RMP_CMFB_S1_s118 RMP_CMFB_S1_s119 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_119 RMP_CMFB_S1_s119 RMP_CMFB_S1_s120 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_120 RMP_CMFB_S1_s120 RMP_CMFB_S1_s121 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_121 RMP_CMFB_S1_s121 RMP_CMFB_S1_s122 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_122 RMP_CMFB_S1_s122 RMP_CMFB_S1_s123 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_123 RMP_CMFB_S1_s123 RMP_CMFB_S1_s124 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_124 RMP_CMFB_S1_s124 RMP_CMFB_S1_s125 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_125 RMP_CMFB_S1_s125 RMP_CMFB_S1_s126 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_126 RMP_CMFB_S1_s126 RMP_CMFB_S1_s127 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_127 RMP_CMFB_S1_s127 RMP_CMFB_S1_s128 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_128 RMP_CMFB_S1_s128 RMP_CMFB_S1_s129 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_129 RMP_CMFB_S1_s129 RMP_CMFB_S1_s130 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_130 RMP_CMFB_S1_s130 RMP_CMFB_S1_s131 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_131 RMP_CMFB_S1_s131 RMP_CMFB_S1_s132 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_132 RMP_CMFB_S1_s132 RMP_CMFB_S1_s133 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_133 RMP_CMFB_S1_s133 RMP_CMFB_S1_s134 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_134 RMP_CMFB_S1_s134 RMP_CMFB_S1_s135 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_135 RMP_CMFB_S1_s135 RMP_CMFB_S1_s136 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_136 RMP_CMFB_S1_s136 RMP_CMFB_S1_s137 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_137 RMP_CMFB_S1_s137 RMP_CMFB_S1_s138 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_138 RMP_CMFB_S1_s138 RMP_CMFB_S1_s139 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_139 RMP_CMFB_S1_s139 RMP_CMFB_S1_s140 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_140 RMP_CMFB_S1_s140 RMP_CMFB_S1_s141 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_141 RMP_CMFB_S1_s141 RMP_CMFB_S1_s142 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_142 RMP_CMFB_S1_s142 RMP_CMFB_S1_s143 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_143 RMP_CMFB_S1_s143 RMP_CMFB_S1_s144 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_144 RMP_CMFB_S1_s144 RMP_CMFB_S1_s145 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_145 RMP_CMFB_S1_s145 RMP_CMFB_S1_s146 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_146 RMP_CMFB_S1_s146 RMP_CMFB_S1_s147 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_147 RMP_CMFB_S1_s147 RMP_CMFB_S1_s148 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_148 RMP_CMFB_S1_s148 RMP_CMFB_S1_s149 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_149 RMP_CMFB_S1_s149 RMP_CMFB_S1_s150 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_150 RMP_CMFB_S1_s150 RMP_CMFB_S1_s151 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_151 RMP_CMFB_S1_s151 RMP_CMFB_S1_s152 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_152 RMP_CMFB_S1_s152 RMP_CMFB_S1_s153 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_153 RMP_CMFB_S1_s153 RMP_CMFB_S1_s154 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_154 RMP_CMFB_S1_s154 RMP_CMFB_S1_s155 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_155 RMP_CMFB_S1_s155 RMP_CMFB_S1_s156 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_156 RMP_CMFB_S1_s156 RMP_CMFB_S1_s157 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_157 RMP_CMFB_S1_s157 RMP_CMFB_S1_s158 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_158 RMP_CMFB_S1_s158 RMP_CMFB_S1_s159 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_159 RMP_CMFB_S1_s159 RMP_CMFB_S1_s160 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_160 RMP_CMFB_S1_s160 RMP_CMFB_S1_s161 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_161 RMP_CMFB_S1_s161 RMP_CMFB_S1_s162 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_162 RMP_CMFB_S1_s162 RMP_CMFB_S1_s163 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_163 RMP_CMFB_S1_s163 RMP_CMFB_S1_s164 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_164 RMP_CMFB_S1_s164 RMP_CMFB_S1_s165 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_165 RMP_CMFB_S1_s165 RMP_CMFB_S1_s166 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_166 RMP_CMFB_S1_s166 RMP_CMFB_S1_s167 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_167 RMP_CMFB_S1_s167 RMP_CMFB_S1_s168 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_168 RMP_CMFB_S1_s168 RMP_CMFB_S1_s169 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_169 RMP_CMFB_S1_s169 RMP_CMFB_S1_s170 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_170 RMP_CMFB_S1_s170 RMP_CMFB_S1_s171 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_171 RMP_CMFB_S1_s171 RMP_CMFB_S1_s172 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_172 RMP_CMFB_S1_s172 RMP_CMFB_S1_s173 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_173 RMP_CMFB_S1_s173 RMP_CMFB_S1_s174 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_174 RMP_CMFB_S1_s174 RMP_CMFB_S1_s175 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_175 RMP_CMFB_S1_s175 RMP_CMFB_S1_s176 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_176 RMP_CMFB_S1_s176 RMP_CMFB_S1_s177 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_177 RMP_CMFB_S1_s177 RMP_CMFB_S1_s178 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_178 RMP_CMFB_S1_s178 RMP_CMFB_S1_s179 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_179 RMP_CMFB_S1_s179 RMP_CMFB_S1_s180 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_180 RMP_CMFB_S1_s180 RMP_CMFB_S1_s181 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_181 RMP_CMFB_S1_s181 RMP_CMFB_S1_s182 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_182 RMP_CMFB_S1_s182 RMP_CMFB_S1_s183 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_183 RMP_CMFB_S1_s183 RMP_CMFB_S1_s184 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_184 RMP_CMFB_S1_s184 RMP_CMFB_S1_s185 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_185 RMP_CMFB_S1_s185 RMP_CMFB_S1_s186 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_186 RMP_CMFB_S1_s186 RMP_CMFB_S1_s187 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_187 RMP_CMFB_S1_s187 RMP_CMFB_S1_s188 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_188 RMP_CMFB_S1_s188 RMP_CMFB_S1_s189 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_189 RMP_CMFB_S1_s189 RMP_CMFB_S1_s190 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_190 RMP_CMFB_S1_s190 RMP_CMFB_S1_s191 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_191 RMP_CMFB_S1_s191 RMP_CMFB_S1_s192 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_192 RMP_CMFB_S1_s192 RMP_CMFB_S1_s193 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_193 RMP_CMFB_S1_s193 RMP_CMFB_S1_s194 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_194 RMP_CMFB_S1_s194 RMP_CMFB_S1_s195 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_195 RMP_CMFB_S1_s195 RMP_CMFB_S1_s196 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_196 RMP_CMFB_S1_s196 RMP_CMFB_S1_s197 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_197 RMP_CMFB_S1_s197 RMP_CMFB_S1_s198 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_198 RMP_CMFB_S1_s198 RMP_CMFB_S1_s199 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_CMFB_S1_199 RMP_CMFB_S1_s199 stg1_p sub rhigh w=.5u l=84.45u m=1 b=0 +XM10_CORE stg1_n core__vb3 core__casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM11_CORE stg1_p core__vb3 core__casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM12_CORE stg1_p core__vb2 core__fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +XM13_CORE stg1_n core__vb2 core__fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +XM14_CORE voutp core__g2_p vss vss sg13_lv_nmos w=20u l=0.25u m=1 +XM15_CORE voutn core__g2_n vss vss sg13_lv_nmos w=20u l=0.25u m=1 +XM16_CORE stg1_n vdd core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM17_CORE core__g2_n vss stg1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM18_CORE stg1_p vdd core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM19_CORE core__g2_p vss stg1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM1_CMFB_OUT cmfb_out__ptail cmfb_out__bias vdd vdd sg13_lv_pmos w=0.33u l=0.26u m=1 +XM1_CMFB_S1 cmfb_s1__ptail cmfb_s1__bias vdd vdd sg13_lv_pmos w=0.33u l=0.26u m=1 +XM1_CORE core__tail vb4_ctl vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM20_CORE stg1_p vss core__g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM21_CORE core__g2_n vdd stg1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM22_CORE stg1_n vss core__g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM23_CORE core__g2_p vdd stg1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM2_CMFB_OUT vb4o cmfb_out__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM2_CMFB_S1 vb4_ctl cmfb_s1__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM2_CORE core__fold_p vinp core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM3_CMFB_OUT cmfb_out__bias cmfb_out__bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +XM3_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +XM3_CORE core__fold_n vinn core__tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM4_CMFB_OUT cmfb_out__mirr cmfb_out__cm_sense cmfb_out__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM4_CMFB_S1 cmfb_s1__mirr cmfb_s1__cm_sense cmfb_s1__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM4_CORE core__fold_p core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +XM5_CMFB_OUT vb4o vref_out cmfb_out__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM5_CMFB_S1 vb4_ctl vref_s1 cmfb_s1__ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM5_CORE core__fold_n core__vb1 vss vss sg13_lv_nmos w=10u l=1u m=1 +XM6_CMFB_OUT cmfb_out__mirr cmfb_out__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM6_CMFB_S1 cmfb_s1__mirr cmfb_s1__mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM6_CORE core__casc_src_n vb4_ctl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM7_CMFB_OUT cmfb_out__bias cmfb_out__bias vss vss sg13_lv_nmos w=0.3u l=0.22u m=1 +XM7_CMFB_S1 cmfb_s1__bias cmfb_s1__bias vss vss sg13_lv_nmos w=0.3u l=0.22u m=1 +XM7_CORE core__casc_src_p vb4_ctl vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM8O voutp vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM9O voutn vb4o vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XCCM_S1_0 vb4_ctl vss cap_cmim w=51.59u l=51.59u m=25 +XCM1_CORE_0 core__g2_p voutp cap_cmim w=44.67u l=44.67u m=2 +XCM2_CORE_0 core__g2_n voutn cap_cmim w=44.67u l=44.67u m=2 +XRMN_CMFB_OUT_0 voutn RMN_CMFB_OUT_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_OUT_1 RMN_CMFB_OUT_s1 RMN_CMFB_OUT_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_OUT_2 RMN_CMFB_OUT_s2 RMN_CMFB_OUT_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_OUT_3 RMN_CMFB_OUT_s3 cmfb_out__cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_0 stg1_n RMN_CMFB_S1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_1 RMN_CMFB_S1_s1 RMN_CMFB_S1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_2 RMN_CMFB_S1_s2 RMN_CMFB_S1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_3 RMN_CMFB_S1_s3 RMN_CMFB_S1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_4 RMN_CMFB_S1_s4 RMN_CMFB_S1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_5 RMN_CMFB_S1_s5 RMN_CMFB_S1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_6 RMN_CMFB_S1_s6 RMN_CMFB_S1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_7 RMN_CMFB_S1_s7 RMN_CMFB_S1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_8 RMN_CMFB_S1_s8 RMN_CMFB_S1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_9 RMN_CMFB_S1_s9 RMN_CMFB_S1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_10 RMN_CMFB_S1_s10 RMN_CMFB_S1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_11 RMN_CMFB_S1_s11 RMN_CMFB_S1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_12 RMN_CMFB_S1_s12 RMN_CMFB_S1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_13 RMN_CMFB_S1_s13 RMN_CMFB_S1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_14 RMN_CMFB_S1_s14 RMN_CMFB_S1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_15 RMN_CMFB_S1_s15 RMN_CMFB_S1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_16 RMN_CMFB_S1_s16 RMN_CMFB_S1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_17 RMN_CMFB_S1_s17 RMN_CMFB_S1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_18 RMN_CMFB_S1_s18 RMN_CMFB_S1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_19 RMN_CMFB_S1_s19 RMN_CMFB_S1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_20 RMN_CMFB_S1_s20 RMN_CMFB_S1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_21 RMN_CMFB_S1_s21 RMN_CMFB_S1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_22 RMN_CMFB_S1_s22 RMN_CMFB_S1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_23 RMN_CMFB_S1_s23 RMN_CMFB_S1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_24 RMN_CMFB_S1_s24 RMN_CMFB_S1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_25 RMN_CMFB_S1_s25 RMN_CMFB_S1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_26 RMN_CMFB_S1_s26 RMN_CMFB_S1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_27 RMN_CMFB_S1_s27 RMN_CMFB_S1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_28 RMN_CMFB_S1_s28 RMN_CMFB_S1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_29 RMN_CMFB_S1_s29 RMN_CMFB_S1_s30 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w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_173 RMN_CMFB_S1_s173 RMN_CMFB_S1_s174 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_174 RMN_CMFB_S1_s174 RMN_CMFB_S1_s175 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_175 RMN_CMFB_S1_s175 RMN_CMFB_S1_s176 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_176 RMN_CMFB_S1_s176 RMN_CMFB_S1_s177 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_177 RMN_CMFB_S1_s177 RMN_CMFB_S1_s178 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_178 RMN_CMFB_S1_s178 RMN_CMFB_S1_s179 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_179 RMN_CMFB_S1_s179 RMN_CMFB_S1_s180 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_180 RMN_CMFB_S1_s180 RMN_CMFB_S1_s181 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_181 RMN_CMFB_S1_s181 RMN_CMFB_S1_s182 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_182 RMN_CMFB_S1_s182 RMN_CMFB_S1_s183 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_183 RMN_CMFB_S1_s183 RMN_CMFB_S1_s184 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_184 RMN_CMFB_S1_s184 RMN_CMFB_S1_s185 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_185 RMN_CMFB_S1_s185 RMN_CMFB_S1_s186 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_186 RMN_CMFB_S1_s186 RMN_CMFB_S1_s187 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_187 RMN_CMFB_S1_s187 RMN_CMFB_S1_s188 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_188 RMN_CMFB_S1_s188 RMN_CMFB_S1_s189 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_189 RMN_CMFB_S1_s189 RMN_CMFB_S1_s190 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_190 RMN_CMFB_S1_s190 RMN_CMFB_S1_s191 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_191 RMN_CMFB_S1_s191 RMN_CMFB_S1_s192 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_192 RMN_CMFB_S1_s192 RMN_CMFB_S1_s193 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_193 RMN_CMFB_S1_s193 RMN_CMFB_S1_s194 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_194 RMN_CMFB_S1_s194 RMN_CMFB_S1_s195 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_195 RMN_CMFB_S1_s195 RMN_CMFB_S1_s196 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_196 RMN_CMFB_S1_s196 RMN_CMFB_S1_s197 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_197 RMN_CMFB_S1_s197 RMN_CMFB_S1_s198 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_198 RMN_CMFB_S1_s198 RMN_CMFB_S1_s199 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_CMFB_S1_199 RMN_CMFB_S1_s199 cmfb_s1__cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_OUT_0 cmfb_out__cm_sense RMP_CMFB_OUT_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_OUT_1 RMP_CMFB_OUT_s1 RMP_CMFB_OUT_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_OUT_2 RMP_CMFB_OUT_s2 RMP_CMFB_OUT_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_OUT_3 RMP_CMFB_OUT_s3 voutp vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_0 cmfb_s1__cm_sense RMP_CMFB_S1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_1 RMP_CMFB_S1_s1 RMP_CMFB_S1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_2 RMP_CMFB_S1_s2 RMP_CMFB_S1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_3 RMP_CMFB_S1_s3 RMP_CMFB_S1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_4 RMP_CMFB_S1_s4 RMP_CMFB_S1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_5 RMP_CMFB_S1_s5 RMP_CMFB_S1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_6 RMP_CMFB_S1_s6 RMP_CMFB_S1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_7 RMP_CMFB_S1_s7 RMP_CMFB_S1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_8 RMP_CMFB_S1_s8 RMP_CMFB_S1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_9 RMP_CMFB_S1_s9 RMP_CMFB_S1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_10 RMP_CMFB_S1_s10 RMP_CMFB_S1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_11 RMP_CMFB_S1_s11 RMP_CMFB_S1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_12 RMP_CMFB_S1_s12 RMP_CMFB_S1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_13 RMP_CMFB_S1_s13 RMP_CMFB_S1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_14 RMP_CMFB_S1_s14 RMP_CMFB_S1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_15 RMP_CMFB_S1_s15 RMP_CMFB_S1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_16 RMP_CMFB_S1_s16 RMP_CMFB_S1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_17 RMP_CMFB_S1_s17 RMP_CMFB_S1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_18 RMP_CMFB_S1_s18 RMP_CMFB_S1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_19 RMP_CMFB_S1_s19 RMP_CMFB_S1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_20 RMP_CMFB_S1_s20 RMP_CMFB_S1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_21 RMP_CMFB_S1_s21 RMP_CMFB_S1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_22 RMP_CMFB_S1_s22 RMP_CMFB_S1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_23 RMP_CMFB_S1_s23 RMP_CMFB_S1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_24 RMP_CMFB_S1_s24 RMP_CMFB_S1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_25 RMP_CMFB_S1_s25 RMP_CMFB_S1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_26 RMP_CMFB_S1_s26 RMP_CMFB_S1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_27 RMP_CMFB_S1_s27 RMP_CMFB_S1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_28 RMP_CMFB_S1_s28 RMP_CMFB_S1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_29 RMP_CMFB_S1_s29 RMP_CMFB_S1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_30 RMP_CMFB_S1_s30 RMP_CMFB_S1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_31 RMP_CMFB_S1_s31 RMP_CMFB_S1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_32 RMP_CMFB_S1_s32 RMP_CMFB_S1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_33 RMP_CMFB_S1_s33 RMP_CMFB_S1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_34 RMP_CMFB_S1_s34 RMP_CMFB_S1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_35 RMP_CMFB_S1_s35 RMP_CMFB_S1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_36 RMP_CMFB_S1_s36 RMP_CMFB_S1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_37 RMP_CMFB_S1_s37 RMP_CMFB_S1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_38 RMP_CMFB_S1_s38 RMP_CMFB_S1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_39 RMP_CMFB_S1_s39 RMP_CMFB_S1_s40 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_40 RMP_CMFB_S1_s40 RMP_CMFB_S1_s41 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_41 RMP_CMFB_S1_s41 RMP_CMFB_S1_s42 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_42 RMP_CMFB_S1_s42 RMP_CMFB_S1_s43 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_43 RMP_CMFB_S1_s43 RMP_CMFB_S1_s44 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_44 RMP_CMFB_S1_s44 RMP_CMFB_S1_s45 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_45 RMP_CMFB_S1_s45 RMP_CMFB_S1_s46 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_46 RMP_CMFB_S1_s46 RMP_CMFB_S1_s47 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_47 RMP_CMFB_S1_s47 RMP_CMFB_S1_s48 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_48 RMP_CMFB_S1_s48 RMP_CMFB_S1_s49 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_49 RMP_CMFB_S1_s49 RMP_CMFB_S1_s50 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_50 RMP_CMFB_S1_s50 RMP_CMFB_S1_s51 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_51 RMP_CMFB_S1_s51 RMP_CMFB_S1_s52 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_52 RMP_CMFB_S1_s52 RMP_CMFB_S1_s53 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_53 RMP_CMFB_S1_s53 RMP_CMFB_S1_s54 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_54 RMP_CMFB_S1_s54 RMP_CMFB_S1_s55 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_55 RMP_CMFB_S1_s55 RMP_CMFB_S1_s56 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_56 RMP_CMFB_S1_s56 RMP_CMFB_S1_s57 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_57 RMP_CMFB_S1_s57 RMP_CMFB_S1_s58 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_58 RMP_CMFB_S1_s58 RMP_CMFB_S1_s59 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_59 RMP_CMFB_S1_s59 RMP_CMFB_S1_s60 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_60 RMP_CMFB_S1_s60 RMP_CMFB_S1_s61 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_61 RMP_CMFB_S1_s61 RMP_CMFB_S1_s62 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_62 RMP_CMFB_S1_s62 RMP_CMFB_S1_s63 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_63 RMP_CMFB_S1_s63 RMP_CMFB_S1_s64 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_64 RMP_CMFB_S1_s64 RMP_CMFB_S1_s65 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_65 RMP_CMFB_S1_s65 RMP_CMFB_S1_s66 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_66 RMP_CMFB_S1_s66 RMP_CMFB_S1_s67 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_67 RMP_CMFB_S1_s67 RMP_CMFB_S1_s68 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_68 RMP_CMFB_S1_s68 RMP_CMFB_S1_s69 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_69 RMP_CMFB_S1_s69 RMP_CMFB_S1_s70 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_70 RMP_CMFB_S1_s70 RMP_CMFB_S1_s71 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_71 RMP_CMFB_S1_s71 RMP_CMFB_S1_s72 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_72 RMP_CMFB_S1_s72 RMP_CMFB_S1_s73 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_73 RMP_CMFB_S1_s73 RMP_CMFB_S1_s74 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_74 RMP_CMFB_S1_s74 RMP_CMFB_S1_s75 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_75 RMP_CMFB_S1_s75 RMP_CMFB_S1_s76 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_76 RMP_CMFB_S1_s76 RMP_CMFB_S1_s77 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_77 RMP_CMFB_S1_s77 RMP_CMFB_S1_s78 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_78 RMP_CMFB_S1_s78 RMP_CMFB_S1_s79 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_79 RMP_CMFB_S1_s79 RMP_CMFB_S1_s80 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_80 RMP_CMFB_S1_s80 RMP_CMFB_S1_s81 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_81 RMP_CMFB_S1_s81 RMP_CMFB_S1_s82 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_82 RMP_CMFB_S1_s82 RMP_CMFB_S1_s83 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_83 RMP_CMFB_S1_s83 RMP_CMFB_S1_s84 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_84 RMP_CMFB_S1_s84 RMP_CMFB_S1_s85 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_85 RMP_CMFB_S1_s85 RMP_CMFB_S1_s86 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_86 RMP_CMFB_S1_s86 RMP_CMFB_S1_s87 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_87 RMP_CMFB_S1_s87 RMP_CMFB_S1_s88 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_88 RMP_CMFB_S1_s88 RMP_CMFB_S1_s89 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_89 RMP_CMFB_S1_s89 RMP_CMFB_S1_s90 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_90 RMP_CMFB_S1_s90 RMP_CMFB_S1_s91 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_91 RMP_CMFB_S1_s91 RMP_CMFB_S1_s92 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_92 RMP_CMFB_S1_s92 RMP_CMFB_S1_s93 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_93 RMP_CMFB_S1_s93 RMP_CMFB_S1_s94 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_94 RMP_CMFB_S1_s94 RMP_CMFB_S1_s95 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_95 RMP_CMFB_S1_s95 RMP_CMFB_S1_s96 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_96 RMP_CMFB_S1_s96 RMP_CMFB_S1_s97 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_97 RMP_CMFB_S1_s97 RMP_CMFB_S1_s98 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_98 RMP_CMFB_S1_s98 RMP_CMFB_S1_s99 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_99 RMP_CMFB_S1_s99 RMP_CMFB_S1_s100 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_100 RMP_CMFB_S1_s100 RMP_CMFB_S1_s101 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_101 RMP_CMFB_S1_s101 RMP_CMFB_S1_s102 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_102 RMP_CMFB_S1_s102 RMP_CMFB_S1_s103 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_103 RMP_CMFB_S1_s103 RMP_CMFB_S1_s104 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_104 RMP_CMFB_S1_s104 RMP_CMFB_S1_s105 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_105 RMP_CMFB_S1_s105 RMP_CMFB_S1_s106 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_106 RMP_CMFB_S1_s106 RMP_CMFB_S1_s107 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_107 RMP_CMFB_S1_s107 RMP_CMFB_S1_s108 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_108 RMP_CMFB_S1_s108 RMP_CMFB_S1_s109 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_109 RMP_CMFB_S1_s109 RMP_CMFB_S1_s110 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_110 RMP_CMFB_S1_s110 RMP_CMFB_S1_s111 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_111 RMP_CMFB_S1_s111 RMP_CMFB_S1_s112 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_112 RMP_CMFB_S1_s112 RMP_CMFB_S1_s113 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_113 RMP_CMFB_S1_s113 RMP_CMFB_S1_s114 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_114 RMP_CMFB_S1_s114 RMP_CMFB_S1_s115 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_115 RMP_CMFB_S1_s115 RMP_CMFB_S1_s116 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_116 RMP_CMFB_S1_s116 RMP_CMFB_S1_s117 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_117 RMP_CMFB_S1_s117 RMP_CMFB_S1_s118 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_118 RMP_CMFB_S1_s118 RMP_CMFB_S1_s119 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_119 RMP_CMFB_S1_s119 RMP_CMFB_S1_s120 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_120 RMP_CMFB_S1_s120 RMP_CMFB_S1_s121 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_121 RMP_CMFB_S1_s121 RMP_CMFB_S1_s122 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_122 RMP_CMFB_S1_s122 RMP_CMFB_S1_s123 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_123 RMP_CMFB_S1_s123 RMP_CMFB_S1_s124 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_124 RMP_CMFB_S1_s124 RMP_CMFB_S1_s125 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_125 RMP_CMFB_S1_s125 RMP_CMFB_S1_s126 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_126 RMP_CMFB_S1_s126 RMP_CMFB_S1_s127 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_127 RMP_CMFB_S1_s127 RMP_CMFB_S1_s128 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_128 RMP_CMFB_S1_s128 RMP_CMFB_S1_s129 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_129 RMP_CMFB_S1_s129 RMP_CMFB_S1_s130 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_130 RMP_CMFB_S1_s130 RMP_CMFB_S1_s131 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_131 RMP_CMFB_S1_s131 RMP_CMFB_S1_s132 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_132 RMP_CMFB_S1_s132 RMP_CMFB_S1_s133 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_133 RMP_CMFB_S1_s133 RMP_CMFB_S1_s134 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_134 RMP_CMFB_S1_s134 RMP_CMFB_S1_s135 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_135 RMP_CMFB_S1_s135 RMP_CMFB_S1_s136 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_136 RMP_CMFB_S1_s136 RMP_CMFB_S1_s137 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_137 RMP_CMFB_S1_s137 RMP_CMFB_S1_s138 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_138 RMP_CMFB_S1_s138 RMP_CMFB_S1_s139 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_139 RMP_CMFB_S1_s139 RMP_CMFB_S1_s140 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_140 RMP_CMFB_S1_s140 RMP_CMFB_S1_s141 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_141 RMP_CMFB_S1_s141 RMP_CMFB_S1_s142 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_142 RMP_CMFB_S1_s142 RMP_CMFB_S1_s143 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_143 RMP_CMFB_S1_s143 RMP_CMFB_S1_s144 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_144 RMP_CMFB_S1_s144 RMP_CMFB_S1_s145 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_145 RMP_CMFB_S1_s145 RMP_CMFB_S1_s146 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_146 RMP_CMFB_S1_s146 RMP_CMFB_S1_s147 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_147 RMP_CMFB_S1_s147 RMP_CMFB_S1_s148 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_148 RMP_CMFB_S1_s148 RMP_CMFB_S1_s149 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_149 RMP_CMFB_S1_s149 RMP_CMFB_S1_s150 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_150 RMP_CMFB_S1_s150 RMP_CMFB_S1_s151 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_151 RMP_CMFB_S1_s151 RMP_CMFB_S1_s152 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_152 RMP_CMFB_S1_s152 RMP_CMFB_S1_s153 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_153 RMP_CMFB_S1_s153 RMP_CMFB_S1_s154 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_154 RMP_CMFB_S1_s154 RMP_CMFB_S1_s155 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_155 RMP_CMFB_S1_s155 RMP_CMFB_S1_s156 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_156 RMP_CMFB_S1_s156 RMP_CMFB_S1_s157 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_157 RMP_CMFB_S1_s157 RMP_CMFB_S1_s158 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_158 RMP_CMFB_S1_s158 RMP_CMFB_S1_s159 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_159 RMP_CMFB_S1_s159 RMP_CMFB_S1_s160 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_160 RMP_CMFB_S1_s160 RMP_CMFB_S1_s161 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_161 RMP_CMFB_S1_s161 RMP_CMFB_S1_s162 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_162 RMP_CMFB_S1_s162 RMP_CMFB_S1_s163 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_163 RMP_CMFB_S1_s163 RMP_CMFB_S1_s164 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_164 RMP_CMFB_S1_s164 RMP_CMFB_S1_s165 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_165 RMP_CMFB_S1_s165 RMP_CMFB_S1_s166 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_166 RMP_CMFB_S1_s166 RMP_CMFB_S1_s167 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_167 RMP_CMFB_S1_s167 RMP_CMFB_S1_s168 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_168 RMP_CMFB_S1_s168 RMP_CMFB_S1_s169 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_169 RMP_CMFB_S1_s169 RMP_CMFB_S1_s170 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_170 RMP_CMFB_S1_s170 RMP_CMFB_S1_s171 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_171 RMP_CMFB_S1_s171 RMP_CMFB_S1_s172 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_172 RMP_CMFB_S1_s172 RMP_CMFB_S1_s173 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_173 RMP_CMFB_S1_s173 RMP_CMFB_S1_s174 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_174 RMP_CMFB_S1_s174 RMP_CMFB_S1_s175 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_175 RMP_CMFB_S1_s175 RMP_CMFB_S1_s176 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_176 RMP_CMFB_S1_s176 RMP_CMFB_S1_s177 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_177 RMP_CMFB_S1_s177 RMP_CMFB_S1_s178 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_178 RMP_CMFB_S1_s178 RMP_CMFB_S1_s179 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_179 RMP_CMFB_S1_s179 RMP_CMFB_S1_s180 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_180 RMP_CMFB_S1_s180 RMP_CMFB_S1_s181 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_181 RMP_CMFB_S1_s181 RMP_CMFB_S1_s182 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_182 RMP_CMFB_S1_s182 RMP_CMFB_S1_s183 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_183 RMP_CMFB_S1_s183 RMP_CMFB_S1_s184 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_184 RMP_CMFB_S1_s184 RMP_CMFB_S1_s185 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_185 RMP_CMFB_S1_s185 RMP_CMFB_S1_s186 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_186 RMP_CMFB_S1_s186 RMP_CMFB_S1_s187 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_187 RMP_CMFB_S1_s187 RMP_CMFB_S1_s188 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_188 RMP_CMFB_S1_s188 RMP_CMFB_S1_s189 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_189 RMP_CMFB_S1_s189 RMP_CMFB_S1_s190 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_190 RMP_CMFB_S1_s190 RMP_CMFB_S1_s191 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_191 RMP_CMFB_S1_s191 RMP_CMFB_S1_s192 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_192 RMP_CMFB_S1_s192 RMP_CMFB_S1_s193 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_193 RMP_CMFB_S1_s193 RMP_CMFB_S1_s194 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_194 RMP_CMFB_S1_s194 RMP_CMFB_S1_s195 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_195 RMP_CMFB_S1_s195 RMP_CMFB_S1_s196 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_196 RMP_CMFB_S1_s196 RMP_CMFB_S1_s197 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_197 RMP_CMFB_S1_s197 RMP_CMFB_S1_s198 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_198 RMP_CMFB_S1_s198 RMP_CMFB_S1_s199 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_CMFB_S1_199 RMP_CMFB_S1_s199 stg1_p vss rhigh w=.5u l=84.45u m=1 b=0 .ends amp_035_fan_chopper_cmfb_dual diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/schematic.svg deleted file mode 100644 index 3f62b565664034e34e10ad30df9511e17a1828a0..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -amp_035_fan_chopper_cmfb_dual{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.amp_035_fan_chopper_cmfb_dual","source_netlist":"design/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal 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overview; 8 child sheets are available in the editable .icproj.json project. Equal net labels connect.amp_035_fan_chopper_cmfb_dualstg1_nsubcmfb_s1__cm_sensevssvb4_ctlvoutpsubcmfb_out__cm_sensevoutnsubcmfb_out__cm_sensevsssubstg1_psubcmfb_s1__cm_sensewell_19well_20well_20well_21well_21well_22vddwell_22well_23well_23cmfb_out__cm_sensewell_24well_24cmfb_s1__cm_sensevddwell_26well_26well_27well_27well_31well_31well_34well_34well_35vddwell_35well_36well_36vddvddvddvddvddvddvddvddvddvddvddvddvinnvddvddvddvddvddvddvddvddvddvddvddvddvddvssvssvssvssvssvssvssvssvssvssvssvssvoutpvsscore__vb1core__vb1core__vb2core__vb2core__vb3voutpcore__vb3vref_outvref_outvref_s1vref_s1stg1_pvoutpstg1_nvb4ovb4ovb4ovb4ovb4ovb4_ctlvb4_ctlvb4_ctlvb4_ctlvb4_ctlwell_0well_0well_1well_1subsubsubsubsubsubsubsubsubvoutnsubsubsubsubsubsubsubvoutncore__g2_pcore__g2_pcore__g2_pcore__g2_nvoutncore__g2_ncore__g2_nwell_7well_7vinpwell_9well_9well_10well_10cmfb_out__ptailcmfb_out__ptailvddcmfb_out__ptailcmfb_out__biascmfb_out__biascmfb_out__biascmfb_out__biascmfb_out__biaswell_11well_11cmfb_s1__ptailcmfb_s1__ptailvddcmfb_s1__ptailcmfb_s1__biascmfb_s1__biascmfb_s1__biascmfb_s1__biascmfb_s1__biaswell_12well_12vddwell_14well_14well_16well_16cmfb_out__mirrcmfb_out__mirrcmfb_out__mirrcmfb_out__mirrcmfb_s1__mirrvddcmfb_s1__mirrcmfb_s1__mirrcmfb_s1__mirrwell_19amp_035_fan_chopper_cmfb_dualRT0ntap1A=4e-12 P=8e-6MM10_COREsg13_lv_pmosw=10u l=0.3um=1RT1ntap1A=4e-12 P=8e-6MM11_COREsg13_lv_pmosw=10u l=0.3um=1MM12_COREsg13_lv_nmosw=5u l=0.3um=1MM13_COREsg13_lv_nmosw=5u l=0.3um=1MM14_COREsg13_lv_nmosw=20u l=0.25um=1MM15_COREsg13_lv_nmosw=20u l=0.25um=1MM16_COREsg13_lv_nmosw=2u l=0.13um=1RT7ntap1A=4e-12 P=8e-6MM17_COREsg13_lv_pmosw=2u l=0.13um=1MM18_COREsg13_lv_nmosw=2u l=0.13um=1RT9ntap1A=4e-12 P=8e-6MM19_COREsg13_lv_pmosw=2u l=0.13um=1RT10ntap1A=4e-12 P=8e-6MM1_CMFB_OUTsg13_lv_pmosw=0.33u l=0.26um=1RT11ntap1A=4e-12 P=8e-6MM1_CMFB_S1sg13_lv_pmosw=0.33u l=0.26um=1RT12ntap1A=4e-12 P=8e-6MM1_COREsg13_lv_pmosw=20u l=1um=1MM20_COREsg13_lv_nmosw=2u l=0.13um=1RT14ntap1A=4e-12 P=8e-6MM21_COREsg13_lv_pmosw=2u l=0.13um=1MM22_COREsg13_lv_nmosw=2u l=0.13um=1RT16ntap1A=4e-12 P=8e-6MM23_COREsg13_lv_pmosw=2u l=0.13um=1MM2_CMFB_OUTsg13_lv_nmosw=2.32u l=1.31um=1MM2_CMFB_S1sg13_lv_nmosw=2.32u l=1.31um=1RT19ntap1A=4e-12 P=8e-6MM2_COREsg13_lv_pmosw=20u l=0.5um=1RT20ntap1A=4e-12 P=8e-6MM3_CMFB_OUTsg13_lv_pmosw=0.88u l=0.26um=1RT21ntap1A=4e-12 P=8e-6MM3_CMFB_S1sg13_lv_pmosw=0.88u l=0.26um=1RT22ntap1A=4e-12 P=8e-6MM3_COREsg13_lv_pmosw=20u l=0.5um=1RT23ntap1A=4e-12 P=8e-6MM4_CMFB_OUTsg13_lv_pmosw=1.42u l=0.27um=1RT24ntap1A=4e-12 P=8e-6MM4_CMFB_S1sg13_lv_pmosw=1.42u l=0.27um=1MM4_COREsg13_lv_nmosw=10u l=1um=1RT26ntap1A=4e-12 P=8e-6MM5_CMFB_OUTsg13_lv_pmosw=1.42u l=0.27um=1RT27ntap1A=4e-12 P=8e-6MM5_CMFB_S1sg13_lv_pmosw=1.42u l=0.27um=1MM5_COREsg13_lv_nmosw=10u l=1um=1MM6_CMFB_OUTsg13_lv_nmosw=2.32u l=1.31um=1MM6_CMFB_S1sg13_lv_nmosw=2.32u l=1.31um=1RT31ntap1A=4e-12 P=8e-6MM6_COREsg13_lv_pmosw=10u l=1um=1MM7_CMFB_OUTsg13_lv_nmosw=0.3u l=0.22um=1MM7_CMFB_S1sg13_lv_nmosw=0.3u l=0.22um=1RT34ntap1A=4e-12 P=8e-6MM7_COREsg13_lv_pmosw=10u l=1um=1RT35ntap1A=4e-12 P=8e-6MM8Osg13_lv_pmosw=20u l=1um=1RT36ntap1A=4e-12 P=8e-6MM9Osg13_lv_pmosw=20u l=1um=1CM1_CORE_0cap_cmimw=44.67u l=44.67um=1CM1_CORE_1cap_cmimw=44.67u l=44.67um=1CM2_CORE_0cap_cmimw=44.67u l=44.67um=1CM2_CORE_1cap_cmimw=44.67u l=44.67um=1XXRT2_bank1XRT2_bank1XXCCM_S1_bank2XCCM_S1_bank2XRRMN_CMFB_OUT_bank3XRRMN_CMFB_S1_bank4XRRMP_CMFB_OUT_bank5XRRMP_CMFB_S1_bank6CORE OTA AND OUTPUT CHOPPEROUTPUT COMMON-MODE FEEDBACKFIRST-STAGE COMMON-MODE FEEDBACKSTATIC OUTPUT CHOPPERDIFFERENTIAL OUTPUT AND MILLER COMPENSATIONWELL AND SUBSTRATE CONTACTS - diff --git a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md index 1d1486d9a7b2dd8aa6818a9a2e6357d45a44ea81..8ea7d3f3e4d1f608d3dfd32278bd7160acf4957d 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md @@ -8,7 +8,7 @@ Implement `amp_035_fan_chopper_cmfb_dual` without changing the declared circuit. `materials/circuit.cdl` is the physical authority; `materials/circuit.spice` is its equivalent simulator representation. `materials/testbench.spice` and `materials/ac.spice` define the transient/closed-AC and balanced open-AC observations. This problem is the description input. The ordered interface is `vinp vinn voutp voutn vdd vss core__vb1 core__vb2 core__vb3 vref_out vref_s1 stg1_p stg1_n vb4o vb4_ctl`. `vss`/`vdd` are rails, input/output names are signal terminals, and the bias/reference and unloaded monitor ports retain the connections named in the netlist. Independent bias sources and loads belong outside the physical core. -W/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source simulation retains finite native body-tap models. Native LVS checks physical taps and body connectivity; Magic extraction idealizes well/substrate ties and does not retain their finite resistance. Distributed substrate behavior is outside this model boundary. +W/L are rounded to 10 nm so centred contacts remain on the 5 nm manufacturing grid. The 0.293 um bias NMOS width is raised to 0.300 um to realize valid native active/contact geometry; no other sizing optimization is applied. Every resistor uses native rhigh segments of at most about 250 kOhm; every larger capacitor uses parallel native cap_cmim units of at most about 4 pF. Source and extraction use logical body nets. Native LVS checks actual body-contact connectivity. Distributed substrate behavior is outside this model boundary. ## Operating Conditions @@ -131,3 +131,5 @@ One/two-loop CMFB amplifier assemblies: output common-mode dynamics 27%; stage-1 Solve budget: **8 hours**. Use the reviewed SG13G2 resources and ngspice 45 environment. Frozen inputs, requirements and tool bindings are in `/protocol/task.json`. Explicitly submit `/workspace/output/final.gds` through the session submission tool; file generation alone is not submission. Evaluation performs native checks, candidate RC extraction and independent paired source/post-layout simulation. Reference GDS, maintainer README and development sources are not solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml b/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml index 56ef3ecc005fefd7b39bcbfa36ea536b75460729..70af065555b01a577b28e9ac2d56fd1d505d1531 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml @@ -4,13 +4,6 @@ title = "MIM-Compensated Local-Feedback Source Follower" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "121c4b7a69a5aa6704c6811c366d5f9c1f3d30c1f77d02a499e5d76491a73658" - [[assets]] path = "reference/buf_001_super_follower.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/schematic.svg deleted file mode 100644 index c556b9b27b110ff75283605343035ba54614fe2a..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -buf_001_super_follower{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.buf_001_super_follower","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["buf_001_super_follower"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["buf_001_super_follower"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/design/buf_001_super_follower.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.buf_001_super_followervddvsspdibiasnavssvsssubvddwellpdnavddvoutvinibiasvssbuf_001_super_followerihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresMMPB8/0.3 ×6MM18/0.3 ×4MM28/0.3 ×4P bulk → wellN bulk → subMMPD8/0.3MMNS4/0.3MMRN4/0.3P bulk → wellN bulk → subCCcomp12.8/12.8RRptap1A=216 µm²RRntap1A=86.2 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml index 341d7857fe59ddf75e21608ef20df24d923923f1..85a8c33e48998df79b35290506dd4220c761c4ff 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml @@ -4,13 +4,6 @@ title = "PMOS-Input Common-Mode Detector and Controller" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "7f684f8db009f30cd8fc2cae2fa21a851034083c48a4ce026b3d0a3b3f8722f8" - [[assets]] path = "reference/cmfb_002_5t_pmos_input.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "f577f3d43336aba3620626f8f8b70d366bcbdba620ec0528323262e8f13fd33c" +sha256 = "38b73479a4383f97b73ac06a3bd51ddce2b4cc2d32d14e32e435267ca4daaf45" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "cmfb_002_5t_pmos_input" -sha256 = "9d0cf10dd16c7a3e2e929dc7fe72dbfb0dd5f4d53f52574e92414e293c903d45" +sha256 = "e2c671312003fc7e6f8e86f593c3e04db6016f676dfa064a275c95fba54b641e" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +sha256 = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.inputs.performance] path = "materials/testbench.spice" @@ -867,10 +860,10 @@ upper = 0 rationale = "Increasing the reference must produce the declared nonpositive control-output response, opposite to the sensed-input response." [task.evaluation.pre_layout] -source_report_sha256 = "b7147afcc835b6bdd2bfc5d280a947c5251766902acfed5e446ecb7af99cb465" +source_report_sha256 = "38e0f50f2d1354ea560cceac5801c51fd47c02114a096a15111f6dcfd6836b13" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -915,14 +908,14 @@ ref_dc = "ref_dc.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "713b8af7eb91ced63acb01b10267bedc66c3f1d8f2827a3e98084948c18d948b" -dut = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +dut = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dc_cm_slope] -value = 16.48291794636148 +value = 16.48291818261605 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dc_ref_slope] -value = -16.4620085859726 +value = -16.4620084454246 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_100khz] @@ -934,15 +927,15 @@ value = 16.48404 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.346312502471509 +value = 0.3463125024735234 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 4.399139773700112e-05 +value = 4.399139773180449e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_v] -value = 9.761825e-11 +value = 8.004752e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.signed_gain] @@ -953,13 +946,6 @@ unit = "1" value = 0.01655849999999998 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "99d839ae57201ca22f2db9d672d0df2799a0396f7c6cf5dffeccf4db76a96f01" -ac = "095bfc09d6da36bf98f2ad8a6f25ca9efea0bc21b197fae183d46f12fbec29e9" -transient = "1cddcb2b8c7b836131251853d7f56e9852f7b9e3a5e75c64716a241f511634c1" -cm_dc = "68c649ba132fd2ff826f9419333dab5c66cc6d3b80698f3baf4a3795540e157b" -ref_dc = "c126a824a83f5fcf6fc1d22b46caac01b3bee8b397c6c9c30027e84a7a283a53" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1003,14 +989,14 @@ ref_dc = "ref_dc.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "713b8af7eb91ced63acb01b10267bedc66c3f1d8f2827a3e98084948c18d948b" -dut = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +dut = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_cm_slope] -value = 16.48291794636148 +value = 16.48291818261605 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_ref_slope] -value = -16.4620085859726 +value = -16.4620084454246 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_100khz] @@ -1022,15 +1008,15 @@ value = 16.4633 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] -value = 0.346312502471509 +value = 0.3463125024735234 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 4.399139773700112e-05 +value = 4.399139773180449e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.ripple_v] -value = 7.391404e-11 +value = 9.745688e-11 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.signed_gain] @@ -1041,13 +1027,6 @@ unit = "1" value = -0.0163921 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "99d839ae57201ca22f2db9d672d0df2799a0396f7c6cf5dffeccf4db76a96f01" -ac = "06d387917a51c4384e203875f4a11df9aaa80c7e0b5b518093fc8c05b32f97cb" -transient = "3611885182d95df41cada2ab78e5bc3cd76274f47b9da1a76cfc628df6842de1" -cm_dc = "68c649ba132fd2ff826f9419333dab5c66cc6d3b80698f3baf4a3795540e157b" -ref_dc = "c126a824a83f5fcf6fc1d22b46caac01b3bee8b397c6c9c30027e84a7a283a53" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1091,51 +1070,44 @@ ref_dc = "ref_dc.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "713b8af7eb91ced63acb01b10267bedc66c3f1d8f2827a3e98084948c18d948b" -dut = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +dut = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_cm_slope] -value = 16.48291794636148 +value = 16.48291818261605 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_ref_slope] -value = -16.4620085859726 +value = -16.4620084454246 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_100khz] -value = 2.313066e-24 +value = 2.288736e-13 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.gain_1khz] -value = 9.629784e-25 +value = 1.312004e-12 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] -value = 0.346312502471509 +value = 0.3463125024735234 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 4.399139773700112e-05 +value = 4.399139773180449e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.ripple_v] -value = 7.150525e-11 +value = 1.007243e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.signed_gain] -value = 1.416051e-34 +value = -1.277138e-12 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.step_response_v] value = -1.00000000002876e-07 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "99d839ae57201ca22f2db9d672d0df2799a0396f7c6cf5dffeccf4db76a96f01" -ac = "690379616be0a0f327f70b94b73b99d9cb6a4aea2d1fb1bde680d502472bc10f" -transient = "b8a0c1173c0270f0200b833fcf951b93f824eb74247e5ad066b829acb710c368" -cm_dc = "68c649ba132fd2ff826f9419333dab5c66cc6d3b80698f3baf4a3795540e157b" -ref_dc = "c126a824a83f5fcf6fc1d22b46caac01b3bee8b397c6c9c30027e84a7a283a53" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -1179,14 +1151,14 @@ ref_dc = "ref_dc.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "713b8af7eb91ced63acb01b10267bedc66c3f1d8f2827a3e98084948c18d948b" -dut = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +dut = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dc_cm_slope] -value = 17.49300763760875 +value = 17.49300733115433 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dc_ref_slope] -value = -17.5020435503379 +value = -17.5020436153925 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.gain_100khz] @@ -1198,15 +1170,15 @@ value = 17.49358 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] -value = 0.3483012660483951 +value = 0.3483012665695249 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 4.290349773321107e-05 +value = 4.290349772790711e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.ripple_v] -value = 1.874949e-10 +value = 2.259066e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.signed_gain] @@ -1217,13 +1189,6 @@ unit = "1" value = 0.01759659999999996 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "0253be93b0aecbe0f691a586879c6fe66a25ace1837bb8b84d0d31080d318cba" -ac = "5be71484d554a543953df878d957b24815a47e55d202e28508ec3b711737e16b" -transient = "5ef2fc31c81a36affe4ef596836caa4c12dcc92ed8d50906a1fc724575a4128b" -cm_dc = "9312b6e4e52c510d34bc9a20576204e2e805ce0e75faffa6c50387440805edd1" -ref_dc = "d215b9dbb9c3102ac9f98cf6b733f4fe89641f3d012e85af2e2dfeb027b1799e" - [task.evaluation.pre_layout.jobs.source_condition_4] operation = "circuit.simulate" @@ -1267,14 +1232,14 @@ ref_dc = "ref_dc.raw" [task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] deck = "713b8af7eb91ced63acb01b10267bedc66c3f1d8f2827a3e98084948c18d948b" -dut = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +dut = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.dc_cm_slope] -value = 17.49300763760875 +value = 17.49300733115433 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.dc_ref_slope] -value = -17.5020435503379 +value = -17.5020436153925 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.gain_100khz] @@ -1286,15 +1251,15 @@ value = 17.50274 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.output_v] -value = 0.3483012660483951 +value = 0.3483012665695249 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.power_w] -value = 4.290349773321107e-05 +value = 4.290349772790711e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.ripple_v] -value = 1.751256e-10 +value = 1.587761e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.signed_gain] @@ -1305,13 +1270,6 @@ unit = "1" value = -0.0174032 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_4.output_sha256] -op = "0253be93b0aecbe0f691a586879c6fe66a25ace1837bb8b84d0d31080d318cba" -ac = "511ed811b420ae412f780a60a9751a27407013367ea4ad183c3bf506e9d7c6ec" -transient = "9c746c68453cca78083a51d4055bfd314eff1238f88d564f8f9ad53b1a2b89ac" -cm_dc = "9312b6e4e52c510d34bc9a20576204e2e805ce0e75faffa6c50387440805edd1" -ref_dc = "d215b9dbb9c3102ac9f98cf6b733f4fe89641f3d012e85af2e2dfeb027b1799e" - [task.evaluation.pre_layout.jobs.source_condition_5] operation = "circuit.simulate" @@ -1355,51 +1313,44 @@ ref_dc = "ref_dc.raw" [task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] deck = "713b8af7eb91ced63acb01b10267bedc66c3f1d8f2827a3e98084948c18d948b" -dut = "c2f813d8f9a239ef66cb9342df6818496a08dcf86bce12ff210770ac2ac811ef" +dut = "d540d6438c1abb58618a36e9dd6422b6246afd7a74131ee5d0f6a07cae141cc0" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.dc_cm_slope] -value = 17.49300763760875 +value = 17.49300733115433 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.dc_ref_slope] -value = -17.5020435503379 +value = -17.5020436153925 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.gain_100khz] -value = 4.301414e-24 +value = 1.116949e-12 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.gain_1khz] -value = 3.312666e-12 +value = 7.02568e-13 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.output_v] -value = 0.3483012660483951 +value = 0.3483012665695249 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.power_w] -value = 4.290349773321107e-05 +value = 4.290349772790711e-05 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.ripple_v] -value = 1.594337e-10 +value = 1.548752e-10 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.signed_gain] -value = 2.789048e-34 +value = 1.055619e-12 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.step_response_v] value = -1.00000000002876e-07 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_5.output_sha256] -op = "0253be93b0aecbe0f691a586879c6fe66a25ace1837bb8b84d0d31080d318cba" -ac = "952c3cd4f1e78238c62cb582f792c8ff82d9ea29e36f6ada9f85c5bbd086d73e" -transient = "9070b081b97086fd7f82990bf12bb818b7e11e3450f1bff42d0eb0ffef0b4858" -cm_dc = "9312b6e4e52c510d34bc9a20576204e2e805ce0e75faffa6c50387440805edd1" -ref_dc = "d215b9dbb9c3102ac9f98cf6b733f4fe89641f3d012e85af2e2dfeb027b1799e" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1439,7 +1390,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl index 5688aaaf86bdd44038bae17d33dd61ef84fb7042..2b2df4abe6ca764448395b43c79d66ef5406b5f0 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl @@ -1,27 +1,19 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt cmfb_002_5t_pmos_input vinp vinn vcmfb vref vdd vss -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM1 ptail bias vdd well_0 sg13_lv_pmos w=0.33u l=0.27u m=1 -RT1 vss sub ptap1 A=4e-12 P=8e-6 -MM2 vcmfb mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM3 bias bias vdd well_2 sg13_lv_pmos w=0.88u l=0.26u m=1 -RT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -MM4 mirr cm_sense ptail well_3 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -MM5 vcmfb vref ptail well_4 sg13_lv_pmos w=1.42u l=0.27u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM6 mirr mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM7 bias bias vss sub sg13_lv_nmos w=0.29u l=0.22u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 -RRMN_0 vinn RMN_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_1 RMN_s1 RMN_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_2 RMN_s2 RMN_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMN_3 RMN_s3 cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_0 cm_sense RMP_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_1 RMP_s1 RMP_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_2 RMP_s2 RMP_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRMP_3 RMP_s3 vinp sub rhigh w=.5u l=84.45u m=1 b=0 +MM1 ptail bias vdd vdd sg13_lv_pmos w=0.33u l=0.27u m=1 +MM2 vcmfb mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM3 bias bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +MM4 mirr cm_sense ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM5 vcmfb vref ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +MM6 mirr mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +MM7 bias bias vss vss sg13_lv_nmos w=0.29u l=0.22u m=1 +RRMN_0 vinn RMN_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_1 RMN_s1 RMN_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_2 RMN_s2 RMN_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMN_3 RMN_s3 cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_0 cm_sense RMP_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_1 RMP_s1 RMP_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_2 RMP_s2 RMP_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRMP_3 RMP_s3 vinp vss rhigh w=.5u l=84.45u m=1 b=0 .ends cmfb_002_5t_pmos_input diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.spice index d1f8769b0475fc003ddbcbc06cb8bf536b1dc51a..175782d33d04db626c654346b5f91b052123b2df 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.spice @@ -1,27 +1,19 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt cmfb_002_5t_pmos_input vinp vinn vcmfb vref vdd vss -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM1 ptail bias vdd well_0 sg13_lv_pmos w=0.33u l=0.27u m=1 -XT1 vss sub ptap1 A=4e-12 P=8e-6 -XM2 vcmfb mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM3 bias bias vdd well_2 sg13_lv_pmos w=0.88u l=0.26u m=1 -XT3 vdd well_3 ntap1 A=4e-12 P=8e-6 -XM4 mirr cm_sense ptail well_3 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT4 vdd well_4 ntap1 A=4e-12 P=8e-6 -XM5 vcmfb vref ptail well_4 sg13_lv_pmos w=1.42u l=0.27u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM6 mirr mirr vss sub sg13_lv_nmos w=2.32u l=1.31u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM7 bias bias vss sub sg13_lv_nmos w=0.29u l=0.22u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 -XRMN_0 vinn RMN_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_1 RMN_s1 RMN_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_2 RMN_s2 RMN_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMN_3 RMN_s3 cm_sense sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_0 cm_sense RMP_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_1 RMP_s1 RMP_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_2 RMP_s2 RMP_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRMP_3 RMP_s3 vinp sub rhigh w=.5u l=84.45u m=1 b=0 +XM1 ptail bias vdd vdd sg13_lv_pmos w=0.33u l=0.27u m=1 +XM2 vcmfb mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM3 bias bias vdd vdd sg13_lv_pmos w=0.88u l=0.26u m=1 +XM4 mirr cm_sense ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM5 vcmfb vref ptail vdd sg13_lv_pmos w=1.42u l=0.27u m=1 +XM6 mirr mirr vss vss sg13_lv_nmos w=2.32u l=1.31u m=1 +XM7 bias bias vss vss sg13_lv_nmos w=0.29u l=0.22u m=1 +XRMN_0 vinn RMN_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_1 RMN_s1 RMN_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_2 RMN_s2 RMN_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMN_3 RMN_s3 cm_sense vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_0 cm_sense RMP_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_1 RMP_s1 RMP_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_2 RMP_s2 RMP_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRMP_3 RMP_s3 vinp vss rhigh w=.5u l=84.45u m=1 b=0 .ends cmfb_002_5t_pmos_input diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/schematic.svg deleted file mode 100644 index 9eb37c9e9051cd8f73a5ec5f3315203b81f8ceca..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -cmfb_002_5t_pmos_input{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.cmfb_002_5t_pmos_input","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["cmfb_002_5t_pmos_input","XRT1_bank1","XRRMN_bank2","XRRMP_bank3"],"banks":[{"name":"XRT1_bank1","devices":4,"source_references":["RT1","RT5","RT6","RTSUB"]},{"name":"XRRMN_bank2","devices":4,"source_references":["RRMN_0","RRMN_1","RRMN_2","RRMN_3"]},{"name":"XRRMP_bank3","devices":4,"source_references":["RRMP_0","RRMP_1","RRMP_2","RRMP_3"]}],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; the editable project retains the original terminals and model bindings. Exported decks are for connectivity inspection, not replacement simulation decks.","The sense-resistor ladders and physical contacts remain detailed child sheets in this same editable project; the main sheet shows the common-mode signal path."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":8},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cmfb_002_5t_pmos_input"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/design/cmfb_002_5t_pmos_input.icproj.json"}}Main-sheet overview; 3 child sheets are available in the editable .icproj.json project. Equal net labels connect.cmfb_002_5t_pmos_inputvinnsubcm_sensevsssubvinpsubcm_sensevddwell_3ptailmirrwell_0well_3cm_sensevddwell_4vcmfbvrefptailwell_4vsssubmirrmirrvssbiasbiasvddsubvsssubvinnsubcm_sensevinpsubcm_sensewell_0vinpvinnvcmfbvrefvddvssptailbiasvcmfbvsssubmirrvddwell_2vddvddbiasbiaswell_2cmfb_002_5t_pmos_inputSense ladderPMOS input pair and NMOS mirror loadBiasWell and substrate contactsMM3MM7MM1MM4MM5MM6MM2RRMN: vinn → cm_senseRRMP: cm_sense → vinpRT2RT0RT3RT4substrate taps - diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md index 55d83d592a9bc76967989504b592e1b7f84150f1..7ae8d2c99dfc5a45e00c547d22d228d520b7fed2 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md @@ -6,7 +6,7 @@ Implement `cmfb_002_5t_pmos_input` with the complete fixed topology and minimize ## Inputs and Interface -`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vinp vinn vcmfb vref vdd vss`. The resistor midpoint senses input common mode. Reference and input sources are external. This is a standalone detector/controller; it contains neither a controlled amplifier nor a complete common-mode feedback loop. Fixture dependent voltage sources only establish specified input voltages and are outside the DUT. +`materials/circuit.cdl` is the authoritative logical circuit netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `vinp vinn vcmfb vref vdd vss`. The resistor midpoint senses input common mode. Reference and input sources are external. This is a standalone detector/controller; it contains neither a controlled amplifier nor a complete common-mode feedback loop. Fixture dependent voltage sources only establish specified input voltages and are outside the DUT. ## Operating Conditions @@ -18,7 +18,7 @@ Source and candidate jobs use exactly the same test apparatus, parameters, nomin Submit a valid GDSII containing top cell `cmfb_002_5t_pmos_input`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor. -Post-layout simulation uses distributed wire RC from native candidate GDS and retains physical MOS, resistors and capacitors; LVS cannot replace PEX. Magic idealizes well/substrate contacts while source simulation retains finite native contact models; no distributed substrate resistance or noise accuracy is claimed. +Post-layout simulation uses distributed wire RC from native candidate GDS and retains physical MOS, resistors and capacitors; LVS cannot replace PEX. Source and Magic extraction use logical well/substrate body nets; no distributed substrate resistance or noise accuracy is claimed. ## Electrical Requirements and Scoring @@ -76,3 +76,5 @@ Common-mode sensing/controllers: signed transfer 45%; ripple 19.3%; output bias Solve budget: **8 hours**. Use the runtime task and reviewed PDK resources to complete the declared native checks, extraction and ngspice measurements. Write the required top cell to `output/final.gds`, then explicitly submit its path through the session interface; file generation alone is not submission. Reference GDS, qualification results and development sources are not standard solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml b/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml index a7037b87e1e5dd799554e2b8cf30695ad9c386a1..12ccd368ced776303f74c5296fb083417557adb5 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml @@ -4,13 +4,6 @@ title = "MIM Switched-Capacitor Common-Mode Sampler" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "33b4ef591e4b812c33447c6f198332cf8db2a3dd69ba2597809643709d612f6e" - [[assets]] path = "reference/cmfb_004_output_switched_cap.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/schematic.svg deleted file mode 100644 index 2ffdad6f657bebe75b9b758d6786e72bc9ec405a..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -cmfb_004_output_switched_cap{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.cmfb_004_output_switched_cap","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["cmfb_004_output_switched_cap"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["cmfb_004_output_switched_cap"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/design/cmfb_004_output_switched_cap.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.cmfb_004_output_switched_capvcmvinpvbiasvcmfbclk_phi_notclk_phisense_pctl_pvcmvinnvbiasvcmfbclk_phi_notclk_phisense_nctl_nvbiasvcmvsssubvddwellvinpvinnvcmfbvcmvbiasclk_phiclk_phi_notvddvsscmfb_004_output_switched_capPositive sampling branchMM20.15/0.13MM60.15/0.13MM10.15/0.13MM50.15/0.13CC2_025.9/25.9MM40.15/0.13MM80.15/0.13MM30.15/0.13MM70.15/0.13P bulk → wellN bulk → subNegative sampling branchMM100.15/0.13MM140.15/0.13MM90.15/0.13MM130.15/0.13CC4_025.9/25.9MM120.15/0.13MM160.15/0.13MM110.15/0.13MM150.15/0.13P bulk → wellN bulk → subReference capacitorsCC1_025.9/25.9CC3_025.9/25.9Substrate contactsRRptap1A=260 µm²RRntap1A=130 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml b/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml index 9687ca8a850de754fe2bf6c047ba95c14e0c42ff..1122209347612b754b6542d3945deb4a567bab13 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml @@ -8,13 +8,6 @@ core_order = 21 [origin] url = "https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/drv_001_pam4_sige_dac" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "436f1ec15be262427731227ccc98f1e2e20e5344a9c270202d5167ee0a5eec4c" - [[assets]] path = "materials/provenance.json" role = "source-material" diff --git a/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/schematic.svg deleted file mode 100644 index 9cc65e6d0a4320c6598c3a3e632b2dffbb4a2649..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -drv_001_pam4_sige_dac{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.drv_001_pam4_sige_dac","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["pam4drv_pam4_lay"],"banks":[],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":24},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["pam4drv_pam4_lay"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/design/drv_001_pam4_sige_dac.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.pam4drv_pam4_layoutpoutnvcascvcascvcmboutpoutnvcascvcascmsbpmsbnoutpoutnvcascvcmbvcmblsbplsbnmsbpmsbnoutpoutnvccvcascvcmbtmsb0tlsb0tmsb1subPAM4 current-steering driverThree cascode HBT cells share differential outputs; external tail sources set MSB/LSB currents.MSB steering cell 0npn13G2 · 70n/900n · Nx=3QQ3M0QQ4M0QQ1M0QQ2M0RRE1M0RRE2M0CCdegM04.5/0.774.5/0.773.21/3.21RRbmsbp0.5/2.14RRbmsbn0.5/2.14LSB steering cellnpn13G2 · 70n/900n · Nx=3QQ3L0QQ4L0QQ1L0QQ2L0RRE1L0RRE2L0CCdegL04.5/0.774.5/0.773.21/3.21RRblsbp0.5/2.14RRblsbn0.5/2.14MSB steering cell 1npn13G2 · 70n/900n · Nx=3QQ3M1QQ4M1QQ1M1QQ2M1RRE1M1RRE2M1CCdegM14.5/0.774.5/0.773.21/3.21Differential output loadsvcc pull-up; outp/outn are shared by all three steering cells.RRcp 1.4/8.71RRcn 1.4/8.71sub: hidden HBT S and resistor B terminals - diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml index 1b4042e42554aaacfec69921a75a65619d3ec9fc..b2f09be999729866d7996d6afc0bce46b727efaf 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml @@ -4,13 +4,6 @@ title = "Fan Clocked Capacitive Instrumentation Amplifier" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "7da1dda9bd90c197f234b71984e9c323f3bfecc9e48c814270b0987a1d1d824e" - [[assets]] path = "reference/ia_002_fan_chopper_simple.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-clocked-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "c9d9a3a76435976ea3c4f6776252493fd48fad6c95efd8b87743a33945f52037" +sha256 = "352015f3cd783ad27ede705bfd09e1c926e8bc91811f0b5a190f01fcdba6abe0" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "ia_002_fan_chopper_simple" -sha256 = "97f83b5e7f5fb018b9212759ab77f039f748e14d2ef15280b1e4fc7730ba8afb" +sha256 = "6849882e48941049efe869b0bb83e337b62e1f76d3d6d22a14038931fa7cdaa7" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "3a607e575115a85d667d2ed160e683938954ff4c8f4b6a3012dbdd0082a8f888" +sha256 = "ff13c9849022e5fe1e2c7516e757e74f06c8945954ad49fb784755ed01e5e640" [task.inputs.performance] path = "materials/testbench.spice" @@ -717,10 +710,10 @@ observations = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "bc4c5faa902750fd5d2fc7207357b87145e87dac97ca6a0710e13750b422ef0a" +source_report_sha256 = "ef4b24554c9f967519272a6770dad2217cdcc21f9d27715a553f5732793f4874" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 900.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 900.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -761,14 +754,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "7c7b3e282ada822a7d87552e96248624fd602187240ced57b548dd0ad272ef80" -dut = "3a607e575115a85d667d2ed160e683938954ff4c8f4b6a3012dbdd0082a8f888" +dut = "ff13c9849022e5fe1e2c7516e757e74f06c8945954ad49fb784755ed01e5e640" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.admittance_imag_s] -value = 3.193969771908487e-09 +value = 3.193853303058791e-09 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.admittance_real_s] -value = 7.78576740410132e-08 +value = 7.785898761456036e-08 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.boundary_error_s] @@ -776,43 +769,43 @@ value = 1.387778780781446e-17 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.clock_power_w] -value = 1.021779e-10 +value = 1.022113e-10 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_max_v] -value = 1.188307 +value = 1.188305 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_mean_v] -value = 0.558029 +value = 0.5580329 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_min_v] -value = 0.008013651 +value = 0.008013654 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_mean_v] -value = -7.533662e-06 +value = -7.535033e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.feedback_error_rms_v] -value = 0.000549125 +value = 0.000549094 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_vv] -value = 6.268803070543958 +value = 6.268810785437647 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.modulation_error_rms_v] -value = 0.000457135 +value = 0.000457134 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_deg] -value = -0.160814488645709 +value = -0.160790174694177 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0001587817 +value = 0.0001587816 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.residual_rms_v] @@ -820,20 +813,17 @@ value = 0.0345688 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_pp_v] -value = 0.4337837 +value = 0.4337882 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.window_change_v] -value = 0.0001819315772789762 +value = 0.0001819156019779765 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.zin_ohm] -value = 12833155.13880835 +value = 12832939.77815189 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -transient = "f8bbda59fe9fba44f71bb5764c150f97d1e880376d27d03320a66b32ab583c81" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -873,14 +863,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "7c7b3e282ada822a7d87552e96248624fd602187240ced57b548dd0ad272ef80" -dut = "3a607e575115a85d667d2ed160e683938954ff4c8f4b6a3012dbdd0082a8f888" +dut = "ff13c9849022e5fe1e2c7516e757e74f06c8945954ad49fb784755ed01e5e640" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.admittance_imag_s] -value = 4.446451517686729e-09 +value = 4.448126028221102e-09 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.admittance_real_s] -value = 7.765244033506784e-08 +value = 7.765354724179776e-08 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.boundary_error_s] @@ -888,7 +878,7 @@ value = 1.387778780781446e-17 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.clock_power_w] -value = 1.02114e-10 +value = 1.021537e-10 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_max_v] @@ -896,35 +886,35 @@ value = 1.188266 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_mean_v] -value = 0.5583273 +value = 0.5583314 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_min_v] -value = 0.008013652 +value = 0.008013653 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_mean_v] -value = 1.054001e-05 +value = 1.056022e-05 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.feedback_error_rms_v] -value = 0.000555456 +value = 0.000555659 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_vv] -value = 6.250555358922573 +value = 6.25056234227543 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.modulation_error_rms_v] -value = 0.000458237 +value = 0.000458315 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_deg] -value = -0.11283303558341 +value = -0.11284784943753 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0001587791 +value = 0.000158779 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.residual_rms_v] @@ -932,20 +922,17 @@ value = 0.034436 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.ripple_pp_v] -value = 0.3986781 +value = 0.3986699 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.window_change_v] -value = 0.0002019151791341725 +value = 0.0002019092125751551 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.zin_ohm] -value = 12856835.00380523 +value = 12856636.51010956 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -transient = "6b708e81d71055b8a4cf956707f91e12f9f2ce007577968e33b539aa3d720e02" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -985,7 +972,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/input-pair-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl index 9ba2e617022be0a3200df6bd86e4aab0abbc564b..f4540a8be80a461311acf914fef2882a228d854c 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl @@ -1,175 +1,129 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt ia_002_fan_chopper_simple vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM1 tail vb4 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM10 out1_n vb3 casc_src_n well_1 sg13_lv_pmos w=10u l=0.3u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM11 out1_p vb3 casc_src_p well_2 sg13_lv_pmos w=10u l=0.3u m=1 -RT3 vss sub ptap1 A=4e-12 P=8e-6 -MM12 out1_p vb2 fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -RT4 vss sub ptap1 A=4e-12 P=8e-6 -MM13 out1_n vb2 fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM14 voutp g2_p vss sub sg13_lv_nmos w=6u l=0.5u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM15 voutn g2_n vss sub sg13_lv_nmos w=6u l=0.5u m=1 -RT7 vss sub ptap1 A=4e-12 P=8e-6 -MM16 out1_n clk_chout g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM17 g2_n clk_chout_not out1_n well_8 sg13_lv_pmos w=2u l=0.13u m=1 -RT9 vss sub ptap1 A=4e-12 P=8e-6 -MM18 out1_p clk_chout g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM19 g2_p clk_chout_not out1_p well_10 sg13_lv_pmos w=2u l=0.13u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM2 fold_p vsum_p tail well_11 sg13_lv_pmos w=20u l=0.5u m=1 -RT12 vss sub ptap1 A=4e-12 P=8e-6 -MM20 fbch_p clk_chfb voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM21 voutp clk_chfb_not fbch_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -RT14 vss sub ptap1 A=4e-12 P=8e-6 -MM22 fbch_n clk_chfb voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM23 voutn clk_chfb_not fbch_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -RT16 vss sub ptap1 A=4e-12 P=8e-6 -MM24 vinn clk_chin inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM25 inch_n clk_chin_not vinn well_17 sg13_lv_pmos w=2u l=0.13u m=1 -RT18 vss sub ptap1 A=4e-12 P=8e-6 -MM26 vinp clk_chin inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM27 inch_p clk_chin_not vinp well_19 sg13_lv_pmos w=2u l=0.13u m=1 -RT20 vss sub ptap1 A=4e-12 P=8e-6 -MM28 out1_n clk_chout_not g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM29 g2_p clk_chout out1_n well_21 sg13_lv_pmos w=2u l=0.13u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM3 fold_n vsum_n tail well_22 sg13_lv_pmos w=20u l=0.5u m=1 -RT23 vss sub ptap1 A=4e-12 P=8e-6 -MM30 out1_p clk_chout_not g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -MM31 g2_n clk_chout out1_p well_24 sg13_lv_pmos w=2u l=0.13u m=1 -RT25 vss sub ptap1 A=4e-12 P=8e-6 -MM32 vinn clk_chin_not inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -MM33 inch_p clk_chin vinn well_26 sg13_lv_pmos w=2u l=0.13u m=1 -RT27 vss sub ptap1 A=4e-12 P=8e-6 -MM34 vinp clk_chin_not inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -MM35 inch_n clk_chin vinp well_28 sg13_lv_pmos w=2u l=0.13u m=1 -RT29 vss sub ptap1 A=4e-12 P=8e-6 -MM36 fbch_p clk_chfb_not voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -RT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -MM37 voutn clk_chfb fbch_p well_30 sg13_lv_pmos w=2u l=0.13u m=1 -RT31 vss sub ptap1 A=4e-12 P=8e-6 -MM38 fbch_n clk_chfb_not voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -RT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -MM39 voutp clk_chfb fbch_n well_32 sg13_lv_pmos w=2u l=0.13u m=1 -RT33 vss sub ptap1 A=4e-12 P=8e-6 -MM4 fold_p vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -RT34 vss sub ptap1 A=4e-12 P=8e-6 -MM5 fold_n vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -RT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -MM6 casc_src_n vb4 vdd well_35 sg13_lv_pmos w=10u l=1u m=1 -RT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -MM7 casc_src_p vb4 vdd well_36 sg13_lv_pmos w=10u l=1u m=1 -RT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -MM8 voutp vb4 vdd well_37 sg13_lv_pmos w=6.2u l=1u m=1 -RT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -MM9 voutn vb4 vdd well_38 sg13_lv_pmos w=6.2u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM1 tail vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM10 out1_n vb3 casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM11 out1_p vb3 casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM12 out1_p vb2 fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +MM13 out1_n vb2 fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +MM14 voutp g2_p vss vss sg13_lv_nmos w=6u l=0.5u m=1 +MM15 voutn g2_n vss vss sg13_lv_nmos w=6u l=0.5u m=1 +MM16 out1_n clk_chout g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM17 g2_n clk_chout_not out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM18 out1_p clk_chout g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM19 g2_p clk_chout_not out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM2 fold_p vsum_p tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM20 fbch_p clk_chfb voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +MM21 voutp clk_chfb_not fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM22 fbch_n clk_chfb voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +MM23 voutn clk_chfb_not fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM24 vinn clk_chin inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM25 inch_n clk_chin_not vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM26 vinp clk_chin inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM27 inch_p clk_chin_not vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM28 out1_n clk_chout_not g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM29 g2_p clk_chout out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM3 fold_n vsum_n tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM30 out1_p clk_chout_not g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM31 g2_n clk_chout out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM32 vinn clk_chin_not inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM33 inch_p clk_chin vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM34 vinp clk_chin_not inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM35 inch_n clk_chin vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM36 fbch_p clk_chfb_not voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +MM37 voutn clk_chfb fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM38 fbch_n clk_chfb_not voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +MM39 voutp clk_chfb fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM4 fold_p vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +MM5 fold_n vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +MM6 casc_src_n vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM7 casc_src_p vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM8 voutp vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 +MM9 voutn vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 CFB1_0 fbch_p vsum_n cap_cmim w=23.04u l=23.04u m=1 CFB2_0 fbch_n vsum_p cap_cmim w=23.04u l=23.04u m=1 -CIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN1_1 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN1_2 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN1_3 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -CIN2_1 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -CIN2_2 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -CIN2_3 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 +CIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=4 +CIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=4 CM1_0 g2_p voutp cap_cmim w=25.77u l=25.77u m=1 CM2_0 g2_n voutn cap_cmim w=25.77u l=25.77u m=1 -RRB1_0 vsum_n RB1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_1 RB1_s1 RB1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_2 RB1_s2 RB1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_3 RB1_s3 RB1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_4 RB1_s4 RB1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_5 RB1_s5 RB1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_6 RB1_s6 RB1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_7 RB1_s7 RB1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_8 RB1_s8 RB1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_9 RB1_s9 RB1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_10 RB1_s10 RB1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_11 RB1_s11 RB1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_12 RB1_s12 RB1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_13 RB1_s13 RB1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_14 RB1_s14 RB1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_15 RB1_s15 RB1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_16 RB1_s16 RB1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_17 RB1_s17 RB1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_18 RB1_s18 RB1_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_19 RB1_s19 RB1_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_20 RB1_s20 RB1_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_21 RB1_s21 RB1_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_22 RB1_s22 RB1_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_23 RB1_s23 RB1_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_24 RB1_s24 RB1_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_25 RB1_s25 RB1_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_26 RB1_s26 RB1_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_27 RB1_s27 RB1_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_28 RB1_s28 RB1_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_29 RB1_s29 RB1_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_30 RB1_s30 RB1_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_31 RB1_s31 RB1_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_32 RB1_s32 RB1_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_33 RB1_s33 RB1_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_34 RB1_s34 RB1_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_35 RB1_s35 RB1_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_36 RB1_s36 RB1_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_37 RB1_s37 RB1_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_38 RB1_s38 RB1_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_39 RB1_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_0 vsum_p RB2_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_1 RB2_s1 RB2_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_2 RB2_s2 RB2_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_3 RB2_s3 RB2_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_4 RB2_s4 RB2_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_5 RB2_s5 RB2_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_6 RB2_s6 RB2_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_7 RB2_s7 RB2_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_8 RB2_s8 RB2_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_9 RB2_s9 RB2_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_10 RB2_s10 RB2_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_11 RB2_s11 RB2_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_12 RB2_s12 RB2_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_13 RB2_s13 RB2_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_14 RB2_s14 RB2_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_15 RB2_s15 RB2_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_16 RB2_s16 RB2_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_17 RB2_s17 RB2_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_18 RB2_s18 RB2_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_19 RB2_s19 RB2_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_20 RB2_s20 RB2_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_21 RB2_s21 RB2_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_22 RB2_s22 RB2_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_23 RB2_s23 RB2_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_24 RB2_s24 RB2_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_25 RB2_s25 RB2_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_26 RB2_s26 RB2_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_27 RB2_s27 RB2_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_28 RB2_s28 RB2_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_29 RB2_s29 RB2_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_30 RB2_s30 RB2_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_31 RB2_s31 RB2_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_32 RB2_s32 RB2_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_33 RB2_s33 RB2_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_34 RB2_s34 RB2_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_35 RB2_s35 RB2_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_36 RB2_s36 RB2_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_37 RB2_s37 RB2_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_38 RB2_s38 RB2_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_39 RB2_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 +RRB1_0 vsum_n RB1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_1 RB1_s1 RB1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_2 RB1_s2 RB1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_3 RB1_s3 RB1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_4 RB1_s4 RB1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_5 RB1_s5 RB1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_6 RB1_s6 RB1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_7 RB1_s7 RB1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_8 RB1_s8 RB1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_9 RB1_s9 RB1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_10 RB1_s10 RB1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_11 RB1_s11 RB1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_12 RB1_s12 RB1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_13 RB1_s13 RB1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_14 RB1_s14 RB1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_15 RB1_s15 RB1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_16 RB1_s16 RB1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_17 RB1_s17 RB1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_18 RB1_s18 RB1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_19 RB1_s19 RB1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_20 RB1_s20 RB1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_21 RB1_s21 RB1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_22 RB1_s22 RB1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_23 RB1_s23 RB1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_24 RB1_s24 RB1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_25 RB1_s25 RB1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_26 RB1_s26 RB1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_27 RB1_s27 RB1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_28 RB1_s28 RB1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_29 RB1_s29 RB1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_30 RB1_s30 RB1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_31 RB1_s31 RB1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_32 RB1_s32 RB1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_33 RB1_s33 RB1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_34 RB1_s34 RB1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_35 RB1_s35 RB1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_36 RB1_s36 RB1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_37 RB1_s37 RB1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_38 RB1_s38 RB1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_39 RB1_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_0 vsum_p RB2_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_1 RB2_s1 RB2_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_2 RB2_s2 RB2_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_3 RB2_s3 RB2_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_4 RB2_s4 RB2_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_5 RB2_s5 RB2_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_6 RB2_s6 RB2_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_7 RB2_s7 RB2_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_8 RB2_s8 RB2_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_9 RB2_s9 RB2_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_10 RB2_s10 RB2_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_11 RB2_s11 RB2_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_12 RB2_s12 RB2_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_13 RB2_s13 RB2_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_14 RB2_s14 RB2_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_15 RB2_s15 RB2_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_16 RB2_s16 RB2_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_17 RB2_s17 RB2_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_18 RB2_s18 RB2_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_19 RB2_s19 RB2_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_20 RB2_s20 RB2_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_21 RB2_s21 RB2_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_22 RB2_s22 RB2_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_23 RB2_s23 RB2_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_24 RB2_s24 RB2_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_25 RB2_s25 RB2_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_26 RB2_s26 RB2_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_27 RB2_s27 RB2_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_28 RB2_s28 RB2_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_29 RB2_s29 RB2_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_30 RB2_s30 RB2_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_31 RB2_s31 RB2_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_32 RB2_s32 RB2_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_33 RB2_s33 RB2_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_34 RB2_s34 RB2_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_35 RB2_s35 RB2_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_36 RB2_s36 RB2_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_37 RB2_s37 RB2_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_38 RB2_s38 RB2_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_39 RB2_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 .ends ia_002_fan_chopper_simple diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.spice index e7329477597fdd08873ceff2a345442987d7a39a..8febd08adb48488577caf125775b06a11503f707 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.spice @@ -1,175 +1,129 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt ia_002_fan_chopper_simple vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM1 tail vb4 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM10 out1_n vb3 casc_src_n well_1 sg13_lv_pmos w=10u l=0.3u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM11 out1_p vb3 casc_src_p well_2 sg13_lv_pmos w=10u l=0.3u m=1 -XT3 vss sub ptap1 A=4e-12 P=8e-6 -XM12 out1_p vb2 fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -XT4 vss sub ptap1 A=4e-12 P=8e-6 -XM13 out1_n vb2 fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM14 voutp g2_p vss sub sg13_lv_nmos w=6u l=0.5u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM15 voutn g2_n vss sub sg13_lv_nmos w=6u l=0.5u m=1 -XT7 vss sub ptap1 A=4e-12 P=8e-6 -XM16 out1_n clk_chout g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM17 g2_n clk_chout_not out1_n well_8 sg13_lv_pmos w=2u l=0.13u m=1 -XT9 vss sub ptap1 A=4e-12 P=8e-6 -XM18 out1_p clk_chout g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM19 g2_p clk_chout_not out1_p well_10 sg13_lv_pmos w=2u l=0.13u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM2 fold_p vsum_p tail well_11 sg13_lv_pmos w=20u l=0.5u m=1 -XT12 vss sub ptap1 A=4e-12 P=8e-6 -XM20 fbch_p clk_chfb voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM21 voutp clk_chfb_not fbch_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -XT14 vss sub ptap1 A=4e-12 P=8e-6 -XM22 fbch_n clk_chfb voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM23 voutn clk_chfb_not fbch_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -XT16 vss sub ptap1 A=4e-12 P=8e-6 -XM24 vinn clk_chin inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM25 inch_n clk_chin_not vinn well_17 sg13_lv_pmos w=2u l=0.13u m=1 -XT18 vss sub ptap1 A=4e-12 P=8e-6 -XM26 vinp clk_chin inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM27 inch_p clk_chin_not vinp well_19 sg13_lv_pmos w=2u l=0.13u m=1 -XT20 vss sub ptap1 A=4e-12 P=8e-6 -XM28 out1_n clk_chout_not g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM29 g2_p clk_chout out1_n well_21 sg13_lv_pmos w=2u l=0.13u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM3 fold_n vsum_n tail well_22 sg13_lv_pmos w=20u l=0.5u m=1 -XT23 vss sub ptap1 A=4e-12 P=8e-6 -XM30 out1_p clk_chout_not g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -XM31 g2_n clk_chout out1_p well_24 sg13_lv_pmos w=2u l=0.13u m=1 -XT25 vss sub ptap1 A=4e-12 P=8e-6 -XM32 vinn clk_chin_not inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -XM33 inch_p clk_chin vinn well_26 sg13_lv_pmos w=2u l=0.13u m=1 -XT27 vss sub ptap1 A=4e-12 P=8e-6 -XM34 vinp clk_chin_not inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -XM35 inch_n clk_chin vinp well_28 sg13_lv_pmos w=2u l=0.13u m=1 -XT29 vss sub ptap1 A=4e-12 P=8e-6 -XM36 fbch_p clk_chfb_not voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -XT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -XM37 voutn clk_chfb fbch_p well_30 sg13_lv_pmos w=2u l=0.13u m=1 -XT31 vss sub ptap1 A=4e-12 P=8e-6 -XM38 fbch_n clk_chfb_not voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -XT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -XM39 voutp clk_chfb fbch_n well_32 sg13_lv_pmos w=2u l=0.13u m=1 -XT33 vss sub ptap1 A=4e-12 P=8e-6 -XM4 fold_p vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -XT34 vss sub ptap1 A=4e-12 P=8e-6 -XM5 fold_n vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -XT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -XM6 casc_src_n vb4 vdd well_35 sg13_lv_pmos w=10u l=1u m=1 -XT36 vdd well_36 ntap1 A=4e-12 P=8e-6 -XM7 casc_src_p vb4 vdd well_36 sg13_lv_pmos w=10u l=1u m=1 -XT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -XM8 voutp vb4 vdd well_37 sg13_lv_pmos w=6.2u l=1u m=1 -XT38 vdd well_38 ntap1 A=4e-12 P=8e-6 -XM9 voutn vb4 vdd well_38 sg13_lv_pmos w=6.2u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM1 tail vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM10 out1_n vb3 casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM11 out1_p vb3 casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM12 out1_p vb2 fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +XM13 out1_n vb2 fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +XM14 voutp g2_p vss vss sg13_lv_nmos w=6u l=0.5u m=1 +XM15 voutn g2_n vss vss sg13_lv_nmos w=6u l=0.5u m=1 +XM16 out1_n clk_chout g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM17 g2_n clk_chout_not out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM18 out1_p clk_chout g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM19 g2_p clk_chout_not out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM2 fold_p vsum_p tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM20 fbch_p clk_chfb voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +XM21 voutp clk_chfb_not fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM22 fbch_n clk_chfb voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +XM23 voutn clk_chfb_not fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM24 vinn clk_chin inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM25 inch_n clk_chin_not vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM26 vinp clk_chin inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM27 inch_p clk_chin_not vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM28 out1_n clk_chout_not g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM29 g2_p clk_chout out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM3 fold_n vsum_n tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM30 out1_p clk_chout_not g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM31 g2_n clk_chout out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM32 vinn clk_chin_not inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM33 inch_p clk_chin vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM34 vinp clk_chin_not inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM35 inch_n clk_chin vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM36 fbch_p clk_chfb_not voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +XM37 voutn clk_chfb fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM38 fbch_n clk_chfb_not voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +XM39 voutp clk_chfb fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM4 fold_p vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +XM5 fold_n vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +XM6 casc_src_n vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM7 casc_src_p vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM8 voutp vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 +XM9 voutn vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 XCFB1_0 fbch_p vsum_n cap_cmim w=23.04u l=23.04u m=1 XCFB2_0 fbch_n vsum_p cap_cmim w=23.04u l=23.04u m=1 -XCIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN1_1 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN1_2 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN1_3 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -XCIN2_1 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -XCIN2_2 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -XCIN2_3 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 +XCIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=4 +XCIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=4 XCM1_0 g2_p voutp cap_cmim w=25.77u l=25.77u m=1 XCM2_0 g2_n voutn cap_cmim w=25.77u l=25.77u m=1 -XRB1_0 vsum_n RB1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_1 RB1_s1 RB1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_2 RB1_s2 RB1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_3 RB1_s3 RB1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_4 RB1_s4 RB1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_5 RB1_s5 RB1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_6 RB1_s6 RB1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_7 RB1_s7 RB1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_8 RB1_s8 RB1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_9 RB1_s9 RB1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_10 RB1_s10 RB1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_11 RB1_s11 RB1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_12 RB1_s12 RB1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_13 RB1_s13 RB1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_14 RB1_s14 RB1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_15 RB1_s15 RB1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_16 RB1_s16 RB1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_17 RB1_s17 RB1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_18 RB1_s18 RB1_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_19 RB1_s19 RB1_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_20 RB1_s20 RB1_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_21 RB1_s21 RB1_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_22 RB1_s22 RB1_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_23 RB1_s23 RB1_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_24 RB1_s24 RB1_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_25 RB1_s25 RB1_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_26 RB1_s26 RB1_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_27 RB1_s27 RB1_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_28 RB1_s28 RB1_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_29 RB1_s29 RB1_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_30 RB1_s30 RB1_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_31 RB1_s31 RB1_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_32 RB1_s32 RB1_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_33 RB1_s33 RB1_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_34 RB1_s34 RB1_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_35 RB1_s35 RB1_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_36 RB1_s36 RB1_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_37 RB1_s37 RB1_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_38 RB1_s38 RB1_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_39 RB1_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_0 vsum_p RB2_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_1 RB2_s1 RB2_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_2 RB2_s2 RB2_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_3 RB2_s3 RB2_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_4 RB2_s4 RB2_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_5 RB2_s5 RB2_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_6 RB2_s6 RB2_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_7 RB2_s7 RB2_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_8 RB2_s8 RB2_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_9 RB2_s9 RB2_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_10 RB2_s10 RB2_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_11 RB2_s11 RB2_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_12 RB2_s12 RB2_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_13 RB2_s13 RB2_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_14 RB2_s14 RB2_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_15 RB2_s15 RB2_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_16 RB2_s16 RB2_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_17 RB2_s17 RB2_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_18 RB2_s18 RB2_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_19 RB2_s19 RB2_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_20 RB2_s20 RB2_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_21 RB2_s21 RB2_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_22 RB2_s22 RB2_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_23 RB2_s23 RB2_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_24 RB2_s24 RB2_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_25 RB2_s25 RB2_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_26 RB2_s26 RB2_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_27 RB2_s27 RB2_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_28 RB2_s28 RB2_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_29 RB2_s29 RB2_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_30 RB2_s30 RB2_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_31 RB2_s31 RB2_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_32 RB2_s32 RB2_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_33 RB2_s33 RB2_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_34 RB2_s34 RB2_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_35 RB2_s35 RB2_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_36 RB2_s36 RB2_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_37 RB2_s37 RB2_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_38 RB2_s38 RB2_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_39 RB2_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 +XRB1_0 vsum_n RB1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_1 RB1_s1 RB1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_2 RB1_s2 RB1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_3 RB1_s3 RB1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_4 RB1_s4 RB1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_5 RB1_s5 RB1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_6 RB1_s6 RB1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_7 RB1_s7 RB1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_8 RB1_s8 RB1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_9 RB1_s9 RB1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_10 RB1_s10 RB1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_11 RB1_s11 RB1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_12 RB1_s12 RB1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_13 RB1_s13 RB1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_14 RB1_s14 RB1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_15 RB1_s15 RB1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_16 RB1_s16 RB1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_17 RB1_s17 RB1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_18 RB1_s18 RB1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_19 RB1_s19 RB1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_20 RB1_s20 RB1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_21 RB1_s21 RB1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_22 RB1_s22 RB1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_23 RB1_s23 RB1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_24 RB1_s24 RB1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_25 RB1_s25 RB1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_26 RB1_s26 RB1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_27 RB1_s27 RB1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_28 RB1_s28 RB1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_29 RB1_s29 RB1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_30 RB1_s30 RB1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_31 RB1_s31 RB1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_32 RB1_s32 RB1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_33 RB1_s33 RB1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_34 RB1_s34 RB1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_35 RB1_s35 RB1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_36 RB1_s36 RB1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_37 RB1_s37 RB1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_38 RB1_s38 RB1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_39 RB1_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_0 vsum_p RB2_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_1 RB2_s1 RB2_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_2 RB2_s2 RB2_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_3 RB2_s3 RB2_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_4 RB2_s4 RB2_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_5 RB2_s5 RB2_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_6 RB2_s6 RB2_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_7 RB2_s7 RB2_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_8 RB2_s8 RB2_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_9 RB2_s9 RB2_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_10 RB2_s10 RB2_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_11 RB2_s11 RB2_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_12 RB2_s12 RB2_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_13 RB2_s13 RB2_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_14 RB2_s14 RB2_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_15 RB2_s15 RB2_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_16 RB2_s16 RB2_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_17 RB2_s17 RB2_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_18 RB2_s18 RB2_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_19 RB2_s19 RB2_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_20 RB2_s20 RB2_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_21 RB2_s21 RB2_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_22 RB2_s22 RB2_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_23 RB2_s23 RB2_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_24 RB2_s24 RB2_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_25 RB2_s25 RB2_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_26 RB2_s26 RB2_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_27 RB2_s27 RB2_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_28 RB2_s28 RB2_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_29 RB2_s29 RB2_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_30 RB2_s30 RB2_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_31 RB2_s31 RB2_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_32 RB2_s32 RB2_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_33 RB2_s33 RB2_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_34 RB2_s34 RB2_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_35 RB2_s35 RB2_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_36 RB2_s36 RB2_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_37 RB2_s37 RB2_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_38 RB2_s38 RB2_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_39 RB2_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 .ends ia_002_fan_chopper_simple diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/schematic.svg deleted file mode 100644 index eccea768403d5efaff8c276b85e49893f33538f5..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ia_002_fan_chopper_simple{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.ia_002_fan_chopper_simple","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["ia_002_fan_chopper_simple","XRT3_bank1","XCIN1_bank2","XCIN2_bank3","XRRB1_bank4","XRRB2_bank5"],"banks":[{"name":"XRT3_bank1","devices":19,"source_references":["RT3","RT4","RT5","RT6","RT7","RT9","RT12","RT14","RT16","RT18","RT20","RT23","RT25","RT27","RT29","RT31","RT33","RT34","RTSUB"]},{"name":"XCIN1_bank2","devices":4,"source_references":["CIN1_0","CIN1_1","CIN1_2","CIN1_3"]},{"name":"XCIN2_bank3","devices":4,"source_references":["CIN2_0","CIN2_1","CIN2_2","CIN2_3"]},{"name":"XRRB1_bank4","devices":40,"source_references":["RRB1_0","RRB1_1","RRB1_2","RRB1_3","RRB1_4","RRB1_5","RRB1_6","RRB1_7","RRB1_8","RRB1_9","RRB1_10","RRB1_11","RRB1_12","RRB1_13","RRB1_14","RRB1_15","RRB1_16","RRB1_17","RRB1_18","RRB1_19","RRB1_20","RRB1_21","RRB1_22","RRB1_23","RRB1_24","RRB1_25","RRB1_26","RRB1_27","RRB1_28","RRB1_29","RRB1_30","RRB1_31","RRB1_32","RRB1_33","RRB1_34","RRB1_35","RRB1_36","RRB1_37","RRB1_38","RRB1_39"]},{"name":"XRRB2_bank5","devices":40,"source_references":["RRB2_0","RRB2_1","RRB2_2","RRB2_3","RRB2_4","RRB2_5","RRB2_6","RRB2_7","RRB2_8","RRB2_9","RRB2_10","RRB2_11","RRB2_12","RRB2_13","RRB2_14","RRB2_15","RRB2_16","RRB2_17","RRB2_18","RRB2_19","RRB2_20","RRB2_21","RRB2_22","RRB2_23","RRB2_24","RRB2_25","RRB2_26","RRB2_27","RRB2_28","RRB2_29","RRB2_30","RRB2_31","RRB2_32","RRB2_33","RRB2_34","RRB2_35","RRB2_36","RRB2_37","RRB2_38","RRB2_39"]}],"limitations":["The editable project uses external model bindings for physical R/C/Q cards. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":80},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ia_002_fan_chopper_simple"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/design/ia_002_fan_chopper_simple.icproj.json"}}Main-sheet overview; 5 child sheets are available in the editable .icproj.json project. Equal net labels connect.ia_002_fan_chopper_simplevrefvsum_nsubvrefvsum_psubinch_pvsum_pvsssubinch_nvsum_nfbch_nwell_2well_32vddwell_35well_35vddwell_36well_36vddwell_37vddvb4well_37vddwell_38well_38fbch_pvsum_nfbch_nvsum_pvoutpout1_pg2_pvoutng2_nvsssubinch_nvsum_ninch_pwell_0subvsum_pvrefvsum_nsubvrefvsum_psubvrefvb1vb2vb3vb4inch_pinch_nvsum_pvsum_nout1_nvsssubout1_nvddwell_8well_8out1_psubvddwell_10well_0well_10vddwell_11vsum_pwell_11subvddwell_13voutpfbch_pwell_13vddvddwell_15voutnfbch_nwell_15well_1inch_nsubvddwell_17well_17vddwell_19inch_pwell_19out1_nwell_1vddwell_21well_21vddwell_22vsum_nwell_22out1_pvddwell_24well_24vddvddwell_26vddinch_pwell_26vddwell_28well_2inch_nwell_28vddwell_30voutnfbch_pwell_30vddwell_32voutpia_002_fan_chopper_simpleRT0ntap1A=4e-12 P=8e-6MM1sg13_lv_pmosw=20u l=1um=1RT1ntap1A=4e-12 P=8e-6MM10sg13_lv_pmosw=10u l=0.3um=1RT2ntap1A=4e-12 P=8e-6MM11sg13_lv_pmosw=10u l=0.3um=1MM12sg13_lv_nmosw=5u l=0.3um=1MM13sg13_lv_nmosw=5u l=0.3um=1MM14sg13_lv_nmosw=6u l=0.5um=1MM15sg13_lv_nmosw=6u l=0.5um=1MM16sg13_lv_nmosw=2u l=0.13um=1RT8ntap1A=4e-12 P=8e-6MM17sg13_lv_pmosw=2u l=0.13um=1MM18sg13_lv_nmosw=2u l=0.13um=1RT10ntap1A=4e-12 P=8e-6MM19sg13_lv_pmosw=2u l=0.13um=1RT11ntap1A=4e-12 P=8e-6MM2sg13_lv_pmosw=20u l=0.5um=1MM20sg13_lv_nmosw=2u l=0.13um=1RT13ntap1A=4e-12 P=8e-6MM21sg13_lv_pmosw=2u l=0.13um=1MM22sg13_lv_nmosw=2u l=0.13um=1RT15ntap1A=4e-12 P=8e-6MM23sg13_lv_pmosw=2u l=0.13um=1MM24sg13_lv_nmosw=2u l=0.13um=1RT17ntap1A=4e-12 P=8e-6MM25sg13_lv_pmosw=2u l=0.13um=1MM26sg13_lv_nmosw=2u l=0.13um=1RT19ntap1A=4e-12 P=8e-6MM27sg13_lv_pmosw=2u l=0.13um=1MM28sg13_lv_nmosw=2u l=0.13um=1RT21ntap1A=4e-12 P=8e-6MM29sg13_lv_pmosw=2u l=0.13um=1RT22ntap1A=4e-12 P=8e-6MM3sg13_lv_pmosw=20u l=0.5um=1MM30sg13_lv_nmosw=2u l=0.13um=1RT24ntap1A=4e-12 P=8e-6MM31sg13_lv_pmosw=2u l=0.13um=1MM32sg13_lv_nmosw=2u l=0.13um=1RT26ntap1A=4e-12 P=8e-6MM33sg13_lv_pmosw=2u l=0.13um=1MM34sg13_lv_nmosw=2u l=0.13um=1RT28ntap1A=4e-12 P=8e-6MM35sg13_lv_pmosw=2u l=0.13um=1MM36sg13_lv_nmosw=2u l=0.13um=1RT30ntap1A=4e-12 P=8e-6MM37sg13_lv_pmosw=2u l=0.13um=1MM38sg13_lv_nmosw=2u l=0.13um=1RT32ntap1A=4e-12 P=8e-6MM39sg13_lv_pmosw=2u l=0.13um=1MM4sg13_lv_nmosw=4.7u l=1um=1MM5sg13_lv_nmosw=4.7u l=1um=1RT35ntap1A=4e-12 P=8e-6MM6sg13_lv_pmosw=10u l=1um=1RT36ntap1A=4e-12 P=8e-6MM7sg13_lv_pmosw=10u l=1um=1RT37ntap1A=4e-12 P=8e-6MM8sg13_lv_pmosw=6.2u l=1um=1RT38ntap1A=4e-12 P=8e-6MM9sg13_lv_pmosw=6.2u l=1um=1CFB1_0cap_cmimw=23.04u l=23.04um=1CFB2_0cap_cmimw=23.04u l=23.04um=1CM1_0cap_cmimw=25.77u l=25.77um=1CM2_0cap_cmimw=25.77u l=25.77um=1XXRT3_bank1XRT3_bank1XXCIN1_bank2XCIN1_bank2XXCIN2_bank3XCIN2_bank3XXRRB1_bank4XRRB1_bank4XXRRB2_bank5XRRB2_bank5Input chopperFolded differential core and active loadsOutput chopper and gain stageFeedback chopperInput, feedback and output passivesWell and substrate contacts - diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md index 96f38be030e7989bb37fdfd6cb3487447e381605..416848fcabd32245d6b24871674cb2c74c4aee9d 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md @@ -23,7 +23,7 @@ TT, 27 C, VDD=1.2 V, input common mode and vref=0.6 V; vb1/vb2/vb3/vb4=0.5/0.75/ Submit nonempty GDSII of at most 10485760 bytes. Pass native IHP DRC and named-interface LVS without waivers. Functional bounds include devices, wells, contacts and all routing layers, excluding annotations, and are at most 5000 × 1000 um. Retain native physical contacts and all passive cells. -Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; source simulation retains finite contact models. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. +Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; Source simulation uses the declared logical body connections. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. The scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. @@ -93,3 +93,5 @@ Solve budget: **10 hours**. Submit GDS top cell ia_002_fan_chopper_simple. Evaluation runs native DRC/LVS, geometry, Magic candidate-derived RC extraction and ngspice transient measurement using reviewed resources. Reference materials and source checkouts are not solver inputs. Discover the frozen task, resources and submission interface through `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`. Declared inputs are in `/task`. Write `/workspace/output/final.gds`, then run `python -I /protocol/submit.py` to submit explicitly; file generation alone is not submission. Feedback follows the capabilities provided by the current runtime protocol. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml index 0060ef0c07b08ae2186801125294136a37ec678c..0d5fe7ccad4222f44e1203b052751a008923760e 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml @@ -4,13 +4,6 @@ title = "Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "f6bbcfe395fb6447182bfd4988b37da479c3fc6ef6809f0ec085e5c395267fe0" - [[assets]] path = "reference/ia_003_fan_chopper_pf.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-clocked-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "a0fc460b449dc67e10e1cb5bba5cd52ce3c8f829d7c28f83cdec25f90e6049d1" +sha256 = "c81d3494d68de2c7deb8a1e698e2ac9d20e47c2f0e92ab3862c7812e57c487e3" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "ia_003_fan_chopper_pf" -sha256 = "870cd5a0b88e0e29454c43f5d4c2e7c555b0ec9dd9f609f9c1e19f6b9258d71a" +sha256 = "2b15a77345aceac980332a2c9cab0e148238b01d04ddc633de4f178426b4e78c" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "6c5a19572e1c3fe59bcf248d6133d2f56b5357bf6bde73d64e4c6c3828791a89" +sha256 = "7e08f86e67a58d704856b173025db645022c117f187a6697ff3d082cc32e3db7" [task.inputs.performance] path = "materials/testbench.spice" @@ -734,10 +727,10 @@ observations = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "1b918f556d15a6b50336a1e759c9888a22d6abb8d1a88e050104c4251f6bb411" +source_report_sha256 = "ba710030f652fceece52dbc127f2437c94d62edb2821a441e360d78547a90ddc" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 900.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 4, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"2\", \"OMP_THREAD_LIMIT\": \"2\"}, \"threads\": 2, \"timeout_seconds\": 900.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -779,14 +772,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "778f3eddd82a0829495c94a56e4a0d48adca09b2e7969829f8033cbc91242d04" -dut = "6c5a19572e1c3fe59bcf248d6133d2f56b5357bf6bde73d64e4c6c3828791a89" +dut = "7e08f86e67a58d704856b173025db645022c117f187a6697ff3d082cc32e3db7" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.admittance_imag_s] -value = 4.463868436157989e-10 +value = 4.456557697746996e-10 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.admittance_real_s] -value = 4.412114780190523e-08 +value = 4.412326904002032e-08 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.boundary_error_s] @@ -794,7 +787,7 @@ value = 1.387778780781446e-17 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.clock_power_w] -value = 1.782276e-10 +value = 1.7809e-10 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_max_v] @@ -802,39 +795,39 @@ value = 1.1883 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_mean_v] -value = 0.5573066 +value = 0.5573113 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.cm_min_v] -value = 0.008014058 +value = 0.008014022 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dm_mean_v] -value = -4.187175e-05 +value = -4.18545e-05 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.feedback_error_rms_v] -value = 0.000459462 +value = 0.000459433 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.gain_vv] -value = 6.27386264741331 +value = 6.273871195380343 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.modulation_error_rms_v] -value = 0.000166605 +value = 0.000166609 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.pf_error_rms_v] -value = 0.000459615 +value = 0.000459586 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_deg] -value = -0.171030856820572 +value = -0.171017024199118 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0001587785 +value = 0.0001587784 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.residual_rms_v] @@ -842,20 +835,17 @@ value = 0.0343174 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ripple_pp_v] -value = 0.4458565 +value = 0.4458449 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.window_change_v] -value = 0.0003154849366289419 +value = 0.0003154416909298104 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.zin_ohm] -value = 22663708.30942519 +value = 22662622.652325 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -transient = "bc150f6c6a7146ac1d412aa2ad4dcd54f5fae5ac797a631a449866ea76861891" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -896,14 +886,14 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "778f3eddd82a0829495c94a56e4a0d48adca09b2e7969829f8033cbc91242d04" -dut = "6c5a19572e1c3fe59bcf248d6133d2f56b5357bf6bde73d64e4c6c3828791a89" +dut = "7e08f86e67a58d704856b173025db645022c117f187a6697ff3d082cc32e3db7" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.admittance_imag_s] -value = 9.075030827697052e-10 +value = 9.086988248636639e-10 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.admittance_real_s] -value = 4.420926951672147e-08 +value = 4.420978685760759e-08 unit = "S" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.boundary_error_s] @@ -911,7 +901,7 @@ value = 1.387778780781446e-17 unit = "s" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.clock_power_w] -value = 1.78367e-10 +value = 1.784118e-10 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_max_v] @@ -919,23 +909,23 @@ value = 1.188255 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_mean_v] -value = 0.5576291 +value = 0.5576335 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.cm_min_v] -value = 0.008014022 +value = 0.00801403 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dm_mean_v] -value = 2.833558e-05 +value = 2.82925e-05 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.feedback_error_rms_v] -value = 0.000446435 +value = 0.000446419 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.gain_vv] -value = 6.252277553404363 +value = 6.252282716569712 unit = "V/V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.modulation_error_rms_v] @@ -943,36 +933,33 @@ value = 0.000166859 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.pf_error_rms_v] -value = 0.000446596 +value = 0.000446579 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_deg] -value = -0.169375905901747 +value = -0.169408814724594 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0001587801 +value = 0.00015878 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.residual_rms_v] -value = 0.0342101 +value = 0.03421 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.ripple_pp_v] -value = 0.414272 +value = 0.4142689 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.window_change_v] -value = 0.0002166278821088033 +value = 0.0002165913468188981 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.zin_ohm] -value = 22614926.45353059 +value = 22614649.36755768 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -transient = "b7cc8a5bc3e9fd2e2f4359bd4f1260d2223bb1b998151b27322482c271e933f9" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1012,7 +999,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/input-pair-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl index f81a1359068986ab2f5f8b1f7ed3d773acd5a6fc..b64b4337b0e7520ea9e413bf48de3093b3ff79e8 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl @@ -1,193 +1,139 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt ia_003_fan_chopper_pf vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not clk_chpf clk_chpf_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n pfch_p pfch_n -RT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -MM1 tail vb4 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM10 out1_n vb3 casc_src_n well_1 sg13_lv_pmos w=10u l=0.3u m=1 -RT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -MM11 out1_p vb3 casc_src_p well_2 sg13_lv_pmos w=10u l=0.3u m=1 -RT3 vss sub ptap1 A=4e-12 P=8e-6 -MM12 out1_p vb2 fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -RT4 vss sub ptap1 A=4e-12 P=8e-6 -MM13 out1_n vb2 fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -RT5 vss sub ptap1 A=4e-12 P=8e-6 -MM14 voutp g2_p vss sub sg13_lv_nmos w=6u l=0.5u m=1 -RT6 vss sub ptap1 A=4e-12 P=8e-6 -MM15 voutn g2_n vss sub sg13_lv_nmos w=6u l=0.5u m=1 -RT7 vss sub ptap1 A=4e-12 P=8e-6 -MM16 out1_n clk_chout g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -MM17 g2_n clk_chout_not out1_n well_8 sg13_lv_pmos w=2u l=0.13u m=1 -RT9 vss sub ptap1 A=4e-12 P=8e-6 -MM18 out1_p clk_chout g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -MM19 g2_p clk_chout_not out1_p well_10 sg13_lv_pmos w=2u l=0.13u m=1 -RT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -MM2 fold_p vsum_p tail well_11 sg13_lv_pmos w=20u l=0.5u m=1 -RT12 vss sub ptap1 A=4e-12 P=8e-6 -MM20 fbch_p clk_chfb voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -RT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -MM21 voutp clk_chfb_not fbch_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -RT14 vss sub ptap1 A=4e-12 P=8e-6 -MM22 fbch_n clk_chfb voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -RT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -MM23 voutn clk_chfb_not fbch_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -RT16 vss sub ptap1 A=4e-12 P=8e-6 -MM24 vinn clk_chin inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -MM25 inch_n clk_chin_not vinn well_17 sg13_lv_pmos w=2u l=0.13u m=1 -RT18 vss sub ptap1 A=4e-12 P=8e-6 -MM26 vinp clk_chin inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -MM27 inch_p clk_chin_not vinp well_19 sg13_lv_pmos w=2u l=0.13u m=1 -RT20 vss sub ptap1 A=4e-12 P=8e-6 -MM28 pfch_p clk_chpf voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -RT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -MM29 voutp clk_chpf_not pfch_p well_21 sg13_lv_pmos w=2u l=0.13u m=1 -RT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -MM3 fold_n vsum_n tail well_22 sg13_lv_pmos w=20u l=0.5u m=1 -RT23 vss sub ptap1 A=4e-12 P=8e-6 -MM30 pfch_n clk_chpf voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -RT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -MM31 voutn clk_chpf_not pfch_n well_24 sg13_lv_pmos w=2u l=0.13u m=1 -RT25 vss sub ptap1 A=4e-12 P=8e-6 -MM32 out1_n clk_chout_not g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -MM33 g2_p clk_chout out1_n well_26 sg13_lv_pmos w=2u l=0.13u m=1 -RT27 vss sub ptap1 A=4e-12 P=8e-6 -MM34 out1_p clk_chout_not g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -MM35 g2_n clk_chout out1_p well_28 sg13_lv_pmos w=2u l=0.13u m=1 -RT29 vss sub ptap1 A=4e-12 P=8e-6 -MM36 vinn clk_chin_not inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -RT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -MM37 inch_p clk_chin vinn well_30 sg13_lv_pmos w=2u l=0.13u m=1 -RT31 vss sub ptap1 A=4e-12 P=8e-6 -MM38 vinp clk_chin_not inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -RT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -MM39 inch_n clk_chin vinp well_32 sg13_lv_pmos w=2u l=0.13u m=1 -RT33 vss sub ptap1 A=4e-12 P=8e-6 -MM4 fold_p vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -RT34 vss sub ptap1 A=4e-12 P=8e-6 -MM40 fbch_p clk_chfb_not voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -RT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -MM41 voutn clk_chfb fbch_p well_35 sg13_lv_pmos w=2u l=0.13u m=1 -RT36 vss sub ptap1 A=4e-12 P=8e-6 -MM42 fbch_n clk_chfb_not voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -RT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -MM43 voutp clk_chfb fbch_n well_37 sg13_lv_pmos w=2u l=0.13u m=1 -RT38 vss sub ptap1 A=4e-12 P=8e-6 -MM44 pfch_p clk_chpf_not voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -RT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -MM45 voutn clk_chpf pfch_p well_39 sg13_lv_pmos w=2u l=0.13u m=1 -RT40 vss sub ptap1 A=4e-12 P=8e-6 -MM46 pfch_n clk_chpf_not voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -RT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -MM47 voutp clk_chpf pfch_n well_41 sg13_lv_pmos w=2u l=0.13u m=1 -RT42 vss sub ptap1 A=4e-12 P=8e-6 -MM5 fold_n vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -RT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -MM6 casc_src_n vb4 vdd well_43 sg13_lv_pmos w=10u l=1u m=1 -RT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -MM7 casc_src_p vb4 vdd well_44 sg13_lv_pmos w=10u l=1u m=1 -RT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -MM8 voutp vb4 vdd well_45 sg13_lv_pmos w=6.2u l=1u m=1 -RT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -MM9 voutn vb4 vdd well_46 sg13_lv_pmos w=6.2u l=1u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM1 tail vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +MM10 out1_n vb3 casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM11 out1_p vb3 casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +MM12 out1_p vb2 fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +MM13 out1_n vb2 fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +MM14 voutp g2_p vss vss sg13_lv_nmos w=6u l=0.5u m=1 +MM15 voutn g2_n vss vss sg13_lv_nmos w=6u l=0.5u m=1 +MM16 out1_n clk_chout g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM17 g2_n clk_chout_not out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM18 out1_p clk_chout g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM19 g2_p clk_chout_not out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM2 fold_p vsum_p tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM20 fbch_p clk_chfb voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +MM21 voutp clk_chfb_not fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM22 fbch_n clk_chfb voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +MM23 voutn clk_chfb_not fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM24 vinn clk_chin inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM25 inch_n clk_chin_not vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM26 vinp clk_chin inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM27 inch_p clk_chin_not vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM28 pfch_p clk_chpf voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +MM29 voutp clk_chpf_not pfch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM3 fold_n vsum_n tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +MM30 pfch_n clk_chpf voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +MM31 voutn clk_chpf_not pfch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM32 out1_n clk_chout_not g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM33 g2_p clk_chout out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM34 out1_p clk_chout_not g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM35 g2_n clk_chout out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM36 vinn clk_chin_not inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +MM37 inch_p clk_chin vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM38 vinp clk_chin_not inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +MM39 inch_n clk_chin vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM4 fold_p vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +MM40 fbch_p clk_chfb_not voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +MM41 voutn clk_chfb fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM42 fbch_n clk_chfb_not voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +MM43 voutp clk_chfb fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM44 pfch_p clk_chpf_not voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +MM45 voutn clk_chpf pfch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM46 pfch_n clk_chpf_not voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +MM47 voutp clk_chpf pfch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +MM5 fold_n vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +MM6 casc_src_n vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM7 casc_src_p vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +MM8 voutp vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 +MM9 voutn vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 CFB1_0 fbch_p vsum_n cap_cmim w=23.04u l=23.04u m=1 CFB2_0 fbch_n vsum_p cap_cmim w=23.04u l=23.04u m=1 -CIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN1_1 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN1_2 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN1_3 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -CIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -CIN2_1 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -CIN2_2 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -CIN2_3 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 +CIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=4 +CIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=4 CM1_0 g2_p voutp cap_cmim w=25.77u l=25.77u m=1 CM2_0 g2_n voutn cap_cmim w=25.77u l=25.77u m=1 CPF1_0 pfch_p inch_p cap_cmim w=23.04u l=23.04u m=1 CPF2_0 pfch_n inch_n cap_cmim w=23.04u l=23.04u m=1 -RRB1_0 vsum_n RB1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_1 RB1_s1 RB1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_2 RB1_s2 RB1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_3 RB1_s3 RB1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_4 RB1_s4 RB1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_5 RB1_s5 RB1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_6 RB1_s6 RB1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_7 RB1_s7 RB1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_8 RB1_s8 RB1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_9 RB1_s9 RB1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_10 RB1_s10 RB1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_11 RB1_s11 RB1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_12 RB1_s12 RB1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_13 RB1_s13 RB1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_14 RB1_s14 RB1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_15 RB1_s15 RB1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_16 RB1_s16 RB1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_17 RB1_s17 RB1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_18 RB1_s18 RB1_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_19 RB1_s19 RB1_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_20 RB1_s20 RB1_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_21 RB1_s21 RB1_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_22 RB1_s22 RB1_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_23 RB1_s23 RB1_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_24 RB1_s24 RB1_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_25 RB1_s25 RB1_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_26 RB1_s26 RB1_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_27 RB1_s27 RB1_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_28 RB1_s28 RB1_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_29 RB1_s29 RB1_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_30 RB1_s30 RB1_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_31 RB1_s31 RB1_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_32 RB1_s32 RB1_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_33 RB1_s33 RB1_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_34 RB1_s34 RB1_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_35 RB1_s35 RB1_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_36 RB1_s36 RB1_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_37 RB1_s37 RB1_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_38 RB1_s38 RB1_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB1_39 RB1_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_0 vsum_p RB2_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_1 RB2_s1 RB2_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_2 RB2_s2 RB2_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_3 RB2_s3 RB2_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_4 RB2_s4 RB2_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_5 RB2_s5 RB2_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_6 RB2_s6 RB2_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_7 RB2_s7 RB2_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_8 RB2_s8 RB2_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_9 RB2_s9 RB2_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_10 RB2_s10 RB2_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_11 RB2_s11 RB2_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_12 RB2_s12 RB2_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_13 RB2_s13 RB2_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_14 RB2_s14 RB2_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_15 RB2_s15 RB2_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_16 RB2_s16 RB2_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_17 RB2_s17 RB2_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_18 RB2_s18 RB2_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_19 RB2_s19 RB2_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_20 RB2_s20 RB2_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_21 RB2_s21 RB2_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_22 RB2_s22 RB2_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_23 RB2_s23 RB2_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_24 RB2_s24 RB2_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_25 RB2_s25 RB2_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_26 RB2_s26 RB2_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_27 RB2_s27 RB2_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_28 RB2_s28 RB2_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_29 RB2_s29 RB2_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_30 RB2_s30 RB2_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_31 RB2_s31 RB2_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_32 RB2_s32 RB2_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_33 RB2_s33 RB2_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_34 RB2_s34 RB2_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_35 RB2_s35 RB2_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_36 RB2_s36 RB2_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_37 RB2_s37 RB2_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_38 RB2_s38 RB2_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -RRB2_39 RB2_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 +RRB1_0 vsum_n RB1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_1 RB1_s1 RB1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_2 RB1_s2 RB1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_3 RB1_s3 RB1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_4 RB1_s4 RB1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_5 RB1_s5 RB1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_6 RB1_s6 RB1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_7 RB1_s7 RB1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_8 RB1_s8 RB1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_9 RB1_s9 RB1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_10 RB1_s10 RB1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_11 RB1_s11 RB1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_12 RB1_s12 RB1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_13 RB1_s13 RB1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_14 RB1_s14 RB1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_15 RB1_s15 RB1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_16 RB1_s16 RB1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_17 RB1_s17 RB1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_18 RB1_s18 RB1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_19 RB1_s19 RB1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_20 RB1_s20 RB1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_21 RB1_s21 RB1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_22 RB1_s22 RB1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_23 RB1_s23 RB1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_24 RB1_s24 RB1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_25 RB1_s25 RB1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_26 RB1_s26 RB1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_27 RB1_s27 RB1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_28 RB1_s28 RB1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_29 RB1_s29 RB1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_30 RB1_s30 RB1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_31 RB1_s31 RB1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_32 RB1_s32 RB1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_33 RB1_s33 RB1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_34 RB1_s34 RB1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_35 RB1_s35 RB1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_36 RB1_s36 RB1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_37 RB1_s37 RB1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_38 RB1_s38 RB1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB1_39 RB1_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_0 vsum_p RB2_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_1 RB2_s1 RB2_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_2 RB2_s2 RB2_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_3 RB2_s3 RB2_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_4 RB2_s4 RB2_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_5 RB2_s5 RB2_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_6 RB2_s6 RB2_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_7 RB2_s7 RB2_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_8 RB2_s8 RB2_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_9 RB2_s9 RB2_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_10 RB2_s10 RB2_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_11 RB2_s11 RB2_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_12 RB2_s12 RB2_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_13 RB2_s13 RB2_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_14 RB2_s14 RB2_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_15 RB2_s15 RB2_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_16 RB2_s16 RB2_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_17 RB2_s17 RB2_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_18 RB2_s18 RB2_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_19 RB2_s19 RB2_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_20 RB2_s20 RB2_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_21 RB2_s21 RB2_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_22 RB2_s22 RB2_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_23 RB2_s23 RB2_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_24 RB2_s24 RB2_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_25 RB2_s25 RB2_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_26 RB2_s26 RB2_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_27 RB2_s27 RB2_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_28 RB2_s28 RB2_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_29 RB2_s29 RB2_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_30 RB2_s30 RB2_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_31 RB2_s31 RB2_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_32 RB2_s32 RB2_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_33 RB2_s33 RB2_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_34 RB2_s34 RB2_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_35 RB2_s35 RB2_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_36 RB2_s36 RB2_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_37 RB2_s37 RB2_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_38 RB2_s38 RB2_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +RRB2_39 RB2_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 .ends ia_003_fan_chopper_pf diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.spice index e0f2175ec5b186557dee6f55517306a6db32e29f..33ce7c10a6fef1e00dac8273beede368befa0d0e 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.spice @@ -1,193 +1,139 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt ia_003_fan_chopper_pf vinp vinn voutp voutn vref clk_chin clk_chin_not clk_chfb clk_chfb_not clk_chout clk_chout_not clk_chpf clk_chpf_not vdd vss vb1 vb2 vb3 vb4 inch_p inch_n fbch_p fbch_n g2_p g2_n vsum_p vsum_n pfch_p pfch_n -XT0 vdd well_0 ntap1 A=4e-12 P=8e-6 -XM1 tail vb4 vdd well_0 sg13_lv_pmos w=20u l=1u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM10 out1_n vb3 casc_src_n well_1 sg13_lv_pmos w=10u l=0.3u m=1 -XT2 vdd well_2 ntap1 A=4e-12 P=8e-6 -XM11 out1_p vb3 casc_src_p well_2 sg13_lv_pmos w=10u l=0.3u m=1 -XT3 vss sub ptap1 A=4e-12 P=8e-6 -XM12 out1_p vb2 fold_p sub sg13_lv_nmos w=5u l=0.3u m=1 -XT4 vss sub ptap1 A=4e-12 P=8e-6 -XM13 out1_n vb2 fold_n sub sg13_lv_nmos w=5u l=0.3u m=1 -XT5 vss sub ptap1 A=4e-12 P=8e-6 -XM14 voutp g2_p vss sub sg13_lv_nmos w=6u l=0.5u m=1 -XT6 vss sub ptap1 A=4e-12 P=8e-6 -XM15 voutn g2_n vss sub sg13_lv_nmos w=6u l=0.5u m=1 -XT7 vss sub ptap1 A=4e-12 P=8e-6 -XM16 out1_n clk_chout g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT8 vdd well_8 ntap1 A=4e-12 P=8e-6 -XM17 g2_n clk_chout_not out1_n well_8 sg13_lv_pmos w=2u l=0.13u m=1 -XT9 vss sub ptap1 A=4e-12 P=8e-6 -XM18 out1_p clk_chout g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT10 vdd well_10 ntap1 A=4e-12 P=8e-6 -XM19 g2_p clk_chout_not out1_p well_10 sg13_lv_pmos w=2u l=0.13u m=1 -XT11 vdd well_11 ntap1 A=4e-12 P=8e-6 -XM2 fold_p vsum_p tail well_11 sg13_lv_pmos w=20u l=0.5u m=1 -XT12 vss sub ptap1 A=4e-12 P=8e-6 -XM20 fbch_p clk_chfb voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -XT13 vdd well_13 ntap1 A=4e-12 P=8e-6 -XM21 voutp clk_chfb_not fbch_p well_13 sg13_lv_pmos w=2u l=0.13u m=1 -XT14 vss sub ptap1 A=4e-12 P=8e-6 -XM22 fbch_n clk_chfb voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -XT15 vdd well_15 ntap1 A=4e-12 P=8e-6 -XM23 voutn clk_chfb_not fbch_n well_15 sg13_lv_pmos w=2u l=0.13u m=1 -XT16 vss sub ptap1 A=4e-12 P=8e-6 -XM24 vinn clk_chin inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT17 vdd well_17 ntap1 A=4e-12 P=8e-6 -XM25 inch_n clk_chin_not vinn well_17 sg13_lv_pmos w=2u l=0.13u m=1 -XT18 vss sub ptap1 A=4e-12 P=8e-6 -XM26 vinp clk_chin inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT19 vdd well_19 ntap1 A=4e-12 P=8e-6 -XM27 inch_p clk_chin_not vinp well_19 sg13_lv_pmos w=2u l=0.13u m=1 -XT20 vss sub ptap1 A=4e-12 P=8e-6 -XM28 pfch_p clk_chpf voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -XT21 vdd well_21 ntap1 A=4e-12 P=8e-6 -XM29 voutp clk_chpf_not pfch_p well_21 sg13_lv_pmos w=2u l=0.13u m=1 -XT22 vdd well_22 ntap1 A=4e-12 P=8e-6 -XM3 fold_n vsum_n tail well_22 sg13_lv_pmos w=20u l=0.5u m=1 -XT23 vss sub ptap1 A=4e-12 P=8e-6 -XM30 pfch_n clk_chpf voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -XT24 vdd well_24 ntap1 A=4e-12 P=8e-6 -XM31 voutn clk_chpf_not pfch_n well_24 sg13_lv_pmos w=2u l=0.13u m=1 -XT25 vss sub ptap1 A=4e-12 P=8e-6 -XM32 out1_n clk_chout_not g2_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT26 vdd well_26 ntap1 A=4e-12 P=8e-6 -XM33 g2_p clk_chout out1_n well_26 sg13_lv_pmos w=2u l=0.13u m=1 -XT27 vss sub ptap1 A=4e-12 P=8e-6 -XM34 out1_p clk_chout_not g2_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT28 vdd well_28 ntap1 A=4e-12 P=8e-6 -XM35 g2_n clk_chout out1_p well_28 sg13_lv_pmos w=2u l=0.13u m=1 -XT29 vss sub ptap1 A=4e-12 P=8e-6 -XM36 vinn clk_chin_not inch_p sub sg13_lv_nmos w=2u l=0.13u m=1 -XT30 vdd well_30 ntap1 A=4e-12 P=8e-6 -XM37 inch_p clk_chin vinn well_30 sg13_lv_pmos w=2u l=0.13u m=1 -XT31 vss sub ptap1 A=4e-12 P=8e-6 -XM38 vinp clk_chin_not inch_n sub sg13_lv_nmos w=2u l=0.13u m=1 -XT32 vdd well_32 ntap1 A=4e-12 P=8e-6 -XM39 inch_n clk_chin vinp well_32 sg13_lv_pmos w=2u l=0.13u m=1 -XT33 vss sub ptap1 A=4e-12 P=8e-6 -XM4 fold_p vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -XT34 vss sub ptap1 A=4e-12 P=8e-6 -XM40 fbch_p clk_chfb_not voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -XT35 vdd well_35 ntap1 A=4e-12 P=8e-6 -XM41 voutn clk_chfb fbch_p well_35 sg13_lv_pmos w=2u l=0.13u m=1 -XT36 vss sub ptap1 A=4e-12 P=8e-6 -XM42 fbch_n clk_chfb_not voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -XT37 vdd well_37 ntap1 A=4e-12 P=8e-6 -XM43 voutp clk_chfb fbch_n well_37 sg13_lv_pmos w=2u l=0.13u m=1 -XT38 vss sub ptap1 A=4e-12 P=8e-6 -XM44 pfch_p clk_chpf_not voutn sub sg13_lv_nmos w=2u l=0.13u m=1 -XT39 vdd well_39 ntap1 A=4e-12 P=8e-6 -XM45 voutn clk_chpf pfch_p well_39 sg13_lv_pmos w=2u l=0.13u m=1 -XT40 vss sub ptap1 A=4e-12 P=8e-6 -XM46 pfch_n clk_chpf_not voutp sub sg13_lv_nmos w=2u l=0.13u m=1 -XT41 vdd well_41 ntap1 A=4e-12 P=8e-6 -XM47 voutp clk_chpf pfch_n well_41 sg13_lv_pmos w=2u l=0.13u m=1 -XT42 vss sub ptap1 A=4e-12 P=8e-6 -XM5 fold_n vb1 vss sub sg13_lv_nmos w=4.7u l=1u m=1 -XT43 vdd well_43 ntap1 A=4e-12 P=8e-6 -XM6 casc_src_n vb4 vdd well_43 sg13_lv_pmos w=10u l=1u m=1 -XT44 vdd well_44 ntap1 A=4e-12 P=8e-6 -XM7 casc_src_p vb4 vdd well_44 sg13_lv_pmos w=10u l=1u m=1 -XT45 vdd well_45 ntap1 A=4e-12 P=8e-6 -XM8 voutp vb4 vdd well_45 sg13_lv_pmos w=6.2u l=1u m=1 -XT46 vdd well_46 ntap1 A=4e-12 P=8e-6 -XM9 voutn vb4 vdd well_46 sg13_lv_pmos w=6.2u l=1u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM1 tail vb4 vdd vdd sg13_lv_pmos w=20u l=1u m=1 +XM10 out1_n vb3 casc_src_n vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM11 out1_p vb3 casc_src_p vdd sg13_lv_pmos w=10u l=0.3u m=1 +XM12 out1_p vb2 fold_p vss sg13_lv_nmos w=5u l=0.3u m=1 +XM13 out1_n vb2 fold_n vss sg13_lv_nmos w=5u l=0.3u m=1 +XM14 voutp g2_p vss vss sg13_lv_nmos w=6u l=0.5u m=1 +XM15 voutn g2_n vss vss sg13_lv_nmos w=6u l=0.5u m=1 +XM16 out1_n clk_chout g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM17 g2_n clk_chout_not out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM18 out1_p clk_chout g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM19 g2_p clk_chout_not out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM2 fold_p vsum_p tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM20 fbch_p clk_chfb voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +XM21 voutp clk_chfb_not fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM22 fbch_n clk_chfb voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +XM23 voutn clk_chfb_not fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM24 vinn clk_chin inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM25 inch_n clk_chin_not vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM26 vinp clk_chin inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM27 inch_p clk_chin_not vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM28 pfch_p clk_chpf voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +XM29 voutp clk_chpf_not pfch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM3 fold_n vsum_n tail vdd sg13_lv_pmos w=20u l=0.5u m=1 +XM30 pfch_n clk_chpf voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +XM31 voutn clk_chpf_not pfch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM32 out1_n clk_chout_not g2_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM33 g2_p clk_chout out1_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM34 out1_p clk_chout_not g2_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM35 g2_n clk_chout out1_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM36 vinn clk_chin_not inch_p vss sg13_lv_nmos w=2u l=0.13u m=1 +XM37 inch_p clk_chin vinn vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM38 vinp clk_chin_not inch_n vss sg13_lv_nmos w=2u l=0.13u m=1 +XM39 inch_n clk_chin vinp vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM4 fold_p vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +XM40 fbch_p clk_chfb_not voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +XM41 voutn clk_chfb fbch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM42 fbch_n clk_chfb_not voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +XM43 voutp clk_chfb fbch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM44 pfch_p clk_chpf_not voutn vss sg13_lv_nmos w=2u l=0.13u m=1 +XM45 voutn clk_chpf pfch_p vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM46 pfch_n clk_chpf_not voutp vss sg13_lv_nmos w=2u l=0.13u m=1 +XM47 voutp clk_chpf pfch_n vdd sg13_lv_pmos w=2u l=0.13u m=1 +XM5 fold_n vb1 vss vss sg13_lv_nmos w=4.7u l=1u m=1 +XM6 casc_src_n vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM7 casc_src_p vb4 vdd vdd sg13_lv_pmos w=10u l=1u m=1 +XM8 voutp vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 +XM9 voutn vb4 vdd vdd sg13_lv_pmos w=6.2u l=1u m=1 XCFB1_0 fbch_p vsum_n cap_cmim w=23.04u l=23.04u m=1 XCFB2_0 fbch_n vsum_p cap_cmim w=23.04u l=23.04u m=1 -XCIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN1_1 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN1_2 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN1_3 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=1 -XCIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -XCIN2_1 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -XCIN2_2 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 -XCIN2_3 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=1 +XCIN1_0 vsum_n inch_n cap_cmim w=51.59u l=51.59u m=4 +XCIN2_0 vsum_p inch_p cap_cmim w=51.59u l=51.59u m=4 XCM1_0 g2_p voutp cap_cmim w=25.77u l=25.77u m=1 XCM2_0 g2_n voutn cap_cmim w=25.77u l=25.77u m=1 XCPF1_0 pfch_p inch_p cap_cmim w=23.04u l=23.04u m=1 XCPF2_0 pfch_n inch_n cap_cmim w=23.04u l=23.04u m=1 -XRB1_0 vsum_n RB1_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_1 RB1_s1 RB1_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_2 RB1_s2 RB1_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_3 RB1_s3 RB1_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_4 RB1_s4 RB1_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_5 RB1_s5 RB1_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_6 RB1_s6 RB1_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_7 RB1_s7 RB1_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_8 RB1_s8 RB1_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_9 RB1_s9 RB1_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_10 RB1_s10 RB1_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_11 RB1_s11 RB1_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_12 RB1_s12 RB1_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_13 RB1_s13 RB1_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_14 RB1_s14 RB1_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_15 RB1_s15 RB1_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_16 RB1_s16 RB1_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_17 RB1_s17 RB1_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_18 RB1_s18 RB1_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_19 RB1_s19 RB1_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_20 RB1_s20 RB1_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_21 RB1_s21 RB1_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_22 RB1_s22 RB1_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_23 RB1_s23 RB1_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_24 RB1_s24 RB1_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_25 RB1_s25 RB1_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_26 RB1_s26 RB1_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_27 RB1_s27 RB1_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_28 RB1_s28 RB1_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_29 RB1_s29 RB1_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_30 RB1_s30 RB1_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_31 RB1_s31 RB1_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_32 RB1_s32 RB1_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_33 RB1_s33 RB1_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_34 RB1_s34 RB1_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_35 RB1_s35 RB1_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_36 RB1_s36 RB1_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_37 RB1_s37 RB1_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_38 RB1_s38 RB1_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB1_39 RB1_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_0 vsum_p RB2_s1 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_1 RB2_s1 RB2_s2 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_2 RB2_s2 RB2_s3 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_3 RB2_s3 RB2_s4 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_4 RB2_s4 RB2_s5 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_5 RB2_s5 RB2_s6 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_6 RB2_s6 RB2_s7 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_7 RB2_s7 RB2_s8 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_8 RB2_s8 RB2_s9 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_9 RB2_s9 RB2_s10 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_10 RB2_s10 RB2_s11 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_11 RB2_s11 RB2_s12 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_12 RB2_s12 RB2_s13 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_13 RB2_s13 RB2_s14 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_14 RB2_s14 RB2_s15 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_15 RB2_s15 RB2_s16 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_16 RB2_s16 RB2_s17 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_17 RB2_s17 RB2_s18 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_18 RB2_s18 RB2_s19 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_19 RB2_s19 RB2_s20 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_20 RB2_s20 RB2_s21 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_21 RB2_s21 RB2_s22 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_22 RB2_s22 RB2_s23 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_23 RB2_s23 RB2_s24 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_24 RB2_s24 RB2_s25 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_25 RB2_s25 RB2_s26 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_26 RB2_s26 RB2_s27 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_27 RB2_s27 RB2_s28 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_28 RB2_s28 RB2_s29 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_29 RB2_s29 RB2_s30 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_30 RB2_s30 RB2_s31 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_31 RB2_s31 RB2_s32 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_32 RB2_s32 RB2_s33 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_33 RB2_s33 RB2_s34 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_34 RB2_s34 RB2_s35 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_35 RB2_s35 RB2_s36 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_36 RB2_s36 RB2_s37 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_37 RB2_s37 RB2_s38 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_38 RB2_s38 RB2_s39 sub rhigh w=.5u l=84.45u m=1 b=0 -XRB2_39 RB2_s39 vref sub rhigh w=.5u l=84.45u m=1 b=0 +XRB1_0 vsum_n RB1_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_1 RB1_s1 RB1_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_2 RB1_s2 RB1_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_3 RB1_s3 RB1_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_4 RB1_s4 RB1_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_5 RB1_s5 RB1_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_6 RB1_s6 RB1_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_7 RB1_s7 RB1_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_8 RB1_s8 RB1_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_9 RB1_s9 RB1_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_10 RB1_s10 RB1_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_11 RB1_s11 RB1_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_12 RB1_s12 RB1_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_13 RB1_s13 RB1_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_14 RB1_s14 RB1_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_15 RB1_s15 RB1_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_16 RB1_s16 RB1_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_17 RB1_s17 RB1_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_18 RB1_s18 RB1_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_19 RB1_s19 RB1_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_20 RB1_s20 RB1_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_21 RB1_s21 RB1_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_22 RB1_s22 RB1_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_23 RB1_s23 RB1_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_24 RB1_s24 RB1_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_25 RB1_s25 RB1_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_26 RB1_s26 RB1_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_27 RB1_s27 RB1_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_28 RB1_s28 RB1_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_29 RB1_s29 RB1_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_30 RB1_s30 RB1_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_31 RB1_s31 RB1_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_32 RB1_s32 RB1_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_33 RB1_s33 RB1_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_34 RB1_s34 RB1_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_35 RB1_s35 RB1_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_36 RB1_s36 RB1_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_37 RB1_s37 RB1_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_38 RB1_s38 RB1_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB1_39 RB1_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_0 vsum_p RB2_s1 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_1 RB2_s1 RB2_s2 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_2 RB2_s2 RB2_s3 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_3 RB2_s3 RB2_s4 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_4 RB2_s4 RB2_s5 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_5 RB2_s5 RB2_s6 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_6 RB2_s6 RB2_s7 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_7 RB2_s7 RB2_s8 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_8 RB2_s8 RB2_s9 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_9 RB2_s9 RB2_s10 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_10 RB2_s10 RB2_s11 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_11 RB2_s11 RB2_s12 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_12 RB2_s12 RB2_s13 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_13 RB2_s13 RB2_s14 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_14 RB2_s14 RB2_s15 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_15 RB2_s15 RB2_s16 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_16 RB2_s16 RB2_s17 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_17 RB2_s17 RB2_s18 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_18 RB2_s18 RB2_s19 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_19 RB2_s19 RB2_s20 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_20 RB2_s20 RB2_s21 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_21 RB2_s21 RB2_s22 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_22 RB2_s22 RB2_s23 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_23 RB2_s23 RB2_s24 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_24 RB2_s24 RB2_s25 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_25 RB2_s25 RB2_s26 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_26 RB2_s26 RB2_s27 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_27 RB2_s27 RB2_s28 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_28 RB2_s28 RB2_s29 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_29 RB2_s29 RB2_s30 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_30 RB2_s30 RB2_s31 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_31 RB2_s31 RB2_s32 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_32 RB2_s32 RB2_s33 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_33 RB2_s33 RB2_s34 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_34 RB2_s34 RB2_s35 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_35 RB2_s35 RB2_s36 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_36 RB2_s36 RB2_s37 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_37 RB2_s37 RB2_s38 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_38 RB2_s38 RB2_s39 vss rhigh w=.5u l=84.45u m=1 b=0 +XRB2_39 RB2_s39 vref vss rhigh w=.5u l=84.45u m=1 b=0 .ends ia_003_fan_chopper_pf diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/schematic.svg deleted file mode 100644 index 257e078b8f018f1723c066d51a2d858a0d1afe3d..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ia_003_fan_chopper_pf{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.ia_003_fan_chopper_pf","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["ia_003_fan_chopper_pf","XRT3_bank1","XCIN1_bank2","XCIN2_bank3","XRRB1_bank4","XRRB2_bank5"],"banks":[{"name":"XRT3_bank1","devices":23,"source_references":["RT3","RT4","RT5","RT6","RT7","RT9","RT12","RT14","RT16","RT18","RT20","RT23","RT25","RT27","RT29","RT31","RT33","RT34","RT36","RT38","RT40","RT42","RTSUB"]},{"name":"XCIN1_bank2","devices":4,"source_references":["CIN1_0","CIN1_1","CIN1_2","CIN1_3"]},{"name":"XCIN2_bank3","devices":4,"source_references":["CIN2_0","CIN2_1","CIN2_2","CIN2_3"]},{"name":"XRRB1_bank4","devices":40,"source_references":["RRB1_0","RRB1_1","RRB1_2","RRB1_3","RRB1_4","RRB1_5","RRB1_6","RRB1_7","RRB1_8","RRB1_9","RRB1_10","RRB1_11","RRB1_12","RRB1_13","RRB1_14","RRB1_15","RRB1_16","RRB1_17","RRB1_18","RRB1_19","RRB1_20","RRB1_21","RRB1_22","RRB1_23","RRB1_24","RRB1_25","RRB1_26","RRB1_27","RRB1_28","RRB1_29","RRB1_30","RRB1_31","RRB1_32","RRB1_33","RRB1_34","RRB1_35","RRB1_36","RRB1_37","RRB1_38","RRB1_39"]},{"name":"XRRB2_bank5","devices":40,"source_references":["RRB2_0","RRB2_1","RRB2_2","RRB2_3","RRB2_4","RRB2_5","RRB2_6","RRB2_7","RRB2_8","RRB2_9","RRB2_10","RRB2_11","RRB2_12","RRB2_13","RRB2_14","RRB2_15","RRB2_16","RRB2_17","RRB2_18","RRB2_19","RRB2_20","RRB2_21","RRB2_22","RRB2_23","RRB2_24","RRB2_25","RRB2_26","RRB2_27","RRB2_28","RRB2_29","RRB2_30","RRB2_31","RRB2_32","RRB2_33","RRB2_34","RRB2_35","RRB2_36","RRB2_37","RRB2_38","RRB2_39"]}],"limitations":["The editable project uses external model bindings for physical R/C/Q cards. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":80},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ia_003_fan_chopper_pf"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/design/ia_003_fan_chopper_pf.icproj.json"}}Main-sheet overview; 5 child sheets are available in the editable .icproj.json project. Equal net labels connect.ia_003_fan_chopper_pfvrefvsum_nsubvrefvsum_psubinch_pvsum_pvsssubinch_nvsum_ninch_nwell_2well_32vb1subout1_psubvddwell_35voutnfbch_pwell_35subvddwell_37voutpfbch_nwell_37subvddwell_39voutnpfch_pwell_39subvddwell_41voutppfch_nwell_41well_0subsubfold_nvddwell_43casc_src_nwell_43vddwell_44casc_src_pwell_44vddwell_45voutpvddvb4well_45vddwell_46voutnvb2vddvb4well_46fbch_pvsum_nfbch_nvsum_pvoutpg2_pvoutng2_ninch_ppfch_pinch_npfch_nsubvsssubinch_nvsum_ninch_pvsum_pvrefvsum_nsubvrefvsum_psubvinpvinnvrefvddvoutpvssvb4inch_pinch_nfbch_pfbch_nvssvsum_pvsum_npfch_ppfch_nsubvoutnsubclk_choutsubvddwell_8clk_chout_notg2_nout1_nwell_8subvddwell_10g2_pwell_0out1_pwell_10vddwell_11vsum_ptailfold_pwell_11clk_chfbsubvddwell_13voutpclk_chfb_notfbch_pwell_13vddsubvddwell_15voutnfbch_nwell_15well_1clk_chininch_nsubvddwell_17clk_chin_notwell_17subvddwell_19vb3inch_pwell_19clk_chpfsubwell_1vddwell_21voutpclk_chpf_notpfch_pwell_21vddwell_22out1_nvsum_nwell_22subvddwell_24voutnpfch_nwell_24subvddvddwell_26vddout1_nwell_26subvddwell_28well_2out1_pwell_28subvddwell_30inch_pwell_30subvddwell_32Chopper instrumentation amplifier with positive feedbackRT0A=4e-12 P=8e-6MM1w=20u l=1uRT1A=4e-12 P=8e-6MM10w=10u l=0.3uRT2A=4e-12 P=8e-6MM11w=10u l=0.3uMM12w=5u l=0.3uMM13w=5u l=0.3uMM14w=6u l=0.5uMM15w=6u l=0.5uMM16w=2u l=0.13uRT8A=4e-12 P=8e-6MM17w=2u l=0.13uMM18w=2u l=0.13uRT10A=4e-12 P=8e-6MM19w=2u l=0.13uRT11A=4e-12 P=8e-6MM2w=20u l=0.5uMM20w=2u l=0.13uRT13A=4e-12 P=8e-6MM21w=2u l=0.13uMM22w=2u l=0.13uRT15A=4e-12 P=8e-6MM23w=2u l=0.13uMM24w=2u l=0.13uRT17A=4e-12 P=8e-6MM25w=2u l=0.13uMM26w=2u l=0.13uRT19A=4e-12 P=8e-6MM27w=2u l=0.13uMM28w=2u l=0.13uRT21A=4e-12 P=8e-6MM29w=2u l=0.13uRT22A=4e-12 P=8e-6MM3w=20u l=0.5uMM30w=2u l=0.13uRT24A=4e-12 P=8e-6MM31w=2u l=0.13uMM32w=2u l=0.13uRT26A=4e-12 P=8e-6MM33w=2u l=0.13uMM34w=2u l=0.13uRT28A=4e-12 P=8e-6MM35w=2u l=0.13uMM36w=2u l=0.13uRT30A=4e-12 P=8e-6MM37w=2u l=0.13uMM38w=2u l=0.13uRT32A=4e-12 P=8e-6MM39w=2u l=0.13uMM4w=4.7u l=1uMM40w=2u l=0.13uRT35A=4e-12 P=8e-6MM41w=2u l=0.13uMM42w=2u l=0.13uRT37A=4e-12 P=8e-6MM43w=2u l=0.13uMM44w=2u l=0.13uRT39A=4e-12 P=8e-6MM45w=2u l=0.13uMM46w=2u l=0.13uRT41A=4e-12 P=8e-6MM47w=2u l=0.13uMM5w=4.7u l=1uRT43A=4e-12 P=8e-6MM6w=10u l=1uRT44A=4e-12 P=8e-6MM7w=10u l=1uRT45A=4e-12 P=8e-6MM8w=6.2u l=1uRT46A=4e-12 P=8e-6MM9w=6.2u l=1uCFB1_0w=23.04u l=23.04uCFB2_0w=23.04u l=23.04uCM1_0w=25.77u l=25.77uCM2_0w=25.77u l=25.77uCPF1_0w=23.04u l=23.04uCPF2_0w=23.04u l=23.04uXXRT3_bank1XXCIN1_bank2XXCIN2_bank3XXRRB1_bank4XXRRB2_bank5Input chopperFolded differential core and active loadsOutput chopper and differential outputFeedback chopperPositive-feedback chopperCoupling, compensation and bias networksWell and substrate contacts - diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md index 6070748dc7327594d365bbb4762f8783dc7f331f..ee23fb93510fb8cb2391a39963977e4931180e97 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md @@ -23,7 +23,7 @@ TT, 27 C, VDD=1.2 V, input common mode and vref=0.6 V; vb1/vb2/vb3/vb4=0.5/0.75/ Submit nonempty GDSII of at most 10485760 bytes. Pass native IHP DRC and named-interface LVS without waivers. Functional bounds include devices, wells, contacts and all routing layers, excluding annotations, and are at most 5000 × 1000 um. Retain native physical contacts and all passive cells. -Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; source simulation retains finite contact models. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. +Magic extracts candidate interconnect RC and device junction geometry. Wells/substrate connect to physical-contact supply rails; Source simulation uses the declared logical body connections. The nominal contract excludes distributed substrate effects, statistical mismatch and manufacturing signoff. The scored functional layer/datatype pairs are `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]`. @@ -94,3 +94,5 @@ Solve budget: **10 hours**. Submit GDS top cell ia_003_fan_chopper_pf. Evaluation runs native DRC/LVS, geometry, Magic candidate-derived RC extraction and ngspice transient measurement using reviewed resources. Reference materials and source checkouts are not solver inputs. Discover the frozen task, resources and submission interface through `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`. Declared inputs are in `/task`. Write `/workspace/output/final.gds`, then run `python -I /protocol/submit.py` to submit explicitly; file generation alone is not submission. Feedback follows the capabilities provided by the current runtime protocol. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml b/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml index e7b8cde6ece9a6e1261f84d70e79a4ba83caffee..7a66840c0b1957ac960300b5616132af495b5a83 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 5 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "dd1784a44dd746072be5b93a7165da1eef226a10750bddee28f2900b8e8382c3" - [[assets]] path = "reference/ia_006_fan_chopper_cmfb.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/schematic.svg deleted file mode 100644 index 1d76fc66d1b45bb55d0dbc631d251936f80251e0..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ia_006_fan_chopper_cmfb{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.ia_006_fan_chopper_cmfb","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["ia_006_fan_chopper_cmfb","Bank1_41series_rhigh","Bank2_41series_rhigh"],"banks":[{"name":"Bank1_41series_rhigh","count":41,"model":"rhigh","kind":"series","members":["RRB1_0","RRB1_1","RRB1_2","RRB1_3","RRB1_4","RRB1_5","RRB1_6","RRB1_7","RRB1_8","RRB1_9","RRB1_10","RRB1_11","RRB1_12","RRB1_13","RRB1_14","RRB1_15","RRB1_16","RRB1_17","RRB1_18","RRB1_19","RRB1_20","RRB1_21","RRB1_22","RRB1_23","RRB1_24","RRB1_25","RRB1_26","RRB1_27","RRB1_28","RRB1_29","RRB1_30","RRB1_31","RRB1_32","RRB1_33","RRB1_34","RRB1_35","RRB1_36","RRB1_37","RRB1_38","RRB1_39","RRB1_40"]},{"name":"Bank2_41series_rhigh","count":41,"model":"rhigh","kind":"series","members":["RRB2_0","RRB2_1","RRB2_2","RRB2_3","RRB2_4","RRB2_5","RRB2_6","RRB2_7","RRB2_8","RRB2_9","RRB2_10","RRB2_11","RRB2_12","RRB2_13","RRB2_14","RRB2_15","RRB2_16","RRB2_17","RRB2_18","RRB2_19","RRB2_20","RRB2_21","RRB2_22","RRB2_23","RRB2_24","RRB2_25","RRB2_26","RRB2_27","RRB2_28","RRB2_29","RRB2_30","RRB2_31","RRB2_32","RRB2_33","RRB2_34","RRB2_35","RRB2_36","RRB2_37","RRB2_38","RRB2_39","RRB2_40"]}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":90},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ia_006_fan_chopper_cmfb"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/design/ia_006_fan_chopper_cmfb.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.ia_006_fan_chopper_cmfbcore__vsum_nvrefsubcore__vsum_pvrefsubcore__vsum_psubsubcore__fbch_pcore__fbch_ncore__g2_pvoutpcore__g2_nvoutncore__inch_ncore__inch_pcore__vsum_ncore__vsum_pvb4ovssvoutnvoutpRMN1RMN2RMN3cmfb__cm_senseRMP1RMP2RMP3vsssubvddwellcore__inch_nvinncore__inch_pclk_chincore__fold_pcore__fold_ncore__tailcore__fold_ncore__fold_pcore__casc_src_ncore__vb4vddcore__casc_src_pcore__out1_ncore__out1_pcore__g2_ncore__out1_ncore__g2_pcore__out1_pclk_choutcore__g2_pcore__g2_nvb4ovddvssvoutpcore__fbch_pvoutncore__fbch_nclk_chfbcmfb__biasvddcmfb__cm_sensevb4ovsscmfb__ptailcmfb__mirrvddvsscmfb__biascore__vsum_nvinpvinnvoutpvoutnvrefclk_chinclk_chin_notclk_chfbclk_chfb_notclk_choutclk_chout_notvddvsscore__vb1core__vb2core__vb3core__vb4vref_cmcore__vsum_pcore__vsum_nia_006_fan_chopper_cmfbihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresInput chopper — straight / crossed phaseMM25_CORE2/0.13MM27_CORE2/0.13MM33_CORE2/0.13MM35_CORE2/0.13MM24_CORE2/0.13MM26_CORE2/0.13MM32_CORE2/0.13MM34_CORE2/0.13P bulk → wellN bulk → subFolded differential coreMM1_CORE10/1 ×2MM2_CORE10/0.5 ×2MM3_CORE10/0.5 ×2MM4_CORE2.35/1 ×2MM5_CORE2.35/1 ×2P bulk → wellN bulk → subCascoded active loadsMM6_CORE5/1 ×2MM7_CORE5/1 ×2MM10_CORE5/0.3 ×2MM11_CORE5/0.3 ×2MM13_CORE2.5/0.3 ×2MM12_CORE2.5/0.3 ×2P bulk → wellN bulk → subOutput chopperMM17_CORE2/0.13MM19_CORE2/0.13MM29_CORE2/0.13MM31_CORE2/0.13MM16_CORE2/0.13MM18_CORE2/0.13MM28_CORE2/0.13MM30_CORE2/0.13P bulk → wellN bulk → subOutput stagesMM8O10/1 ×2MM9O10/1 ×2MM14_CORE3/0.5 ×2MM15_CORE3/0.5 ×2P bulk → wellN bulk → subFeedback chopperMM21_CORE2/0.13MM23_CORE2/0.13MM37_CORE2/0.13MM39_CORE2/0.13MM20_CORE2/0.13MM22_CORE2/0.13MM36_CORE2/0.13MM38_CORE2/0.13P bulk → wellN bulk → subCommon-mode error amplifierMM1_CMFB0.33/0.26MM4_CMFB1.42/0.27MM5_CMFB1.42/0.27MM6_CMFB2.32/1.31MM2_CMFB2.32/1.31P bulk → wellN bulk → subCommon-mode biasMM3_CMFB0.88/0.26MM7_CMFB0.29/0.22P bulk → wellN bulk → subSeries resistor networksXBANK1Bank1_41series_rhighXBANK2Bank2_41series_rhighCompensation and signal passivesCCIN1_051.6/51.6CCIN1_151.6/51.6CCIN1_251.6/51.6CCIN1_351.6/51.6CCIN2_051.6/51.6CCIN2_151.6/51.6CCIN2_251.6/51.6CCIN2_351.6/51.6CCFB1_023.1/23.1CCFB2_023.1/23.1CCM1_051.6/51.6CCM2_051.6/51.6CMFB and resistor compensationCCCM_025.9/25.9RRMN_01/180RRMN_11/180RRMN_21/180RRMN_31/180RRMP_01/180RRMP_11/180RRMP_21/180RRMP_31/180R substrate → subSubstrate contacts / repeated banksRRptap1A=899 µm²RRntap1A=498 µm² - diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml index fa0c0791006f8dbdcec12559119e9e0af457a1f7..1f8c82b86ed0817528be8c417767bb2db2eab2b1 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml @@ -4,13 +4,6 @@ title = "Multistage Error-Amplifier PMOS Regulator" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "6acb6ca3b7332133b475e3ebdb38230c8c2607e353821bdd7e8e6c0e1c7caaee" - [[assets]] path = "reference/ldo_001_analoggym_basic.gds" role = "physical-witness" @@ -28,23 +21,23 @@ environment = "ihp-sg13g2-ldo_001_analoggym_basic-nominal-rc" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "e7e9535ed99e956fd8a7ab21aa05ce5187394c0e6e85fb9693497974fba55647" +sha256 = "a00ac8869048c56042cccf932a370ab7a868880840389cf6ca2d9c14d9366fae" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "ldo_001_analoggym_basic" -sha256 = "eebb188d9aa510eb1d03395ad2a4fe8b12ca6e4e16d4172dbd4d72bad3d0d79b" +sha256 = "46bc249c1f72b4d0162bcef20f66deea9b729be29d63babe3c2f53cb47320796" [task.inputs.performance] path = "materials/testbench.spice" format = "spice" -sha256 = "afe7c38e8417384a73d95e634318fed67c45c973cad29a549070052d2d6b373d" +sha256 = "f7a1e178ce2bdfc55a194b29f6ef34ede9df9330b966b4d5236d3273d276270e" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +sha256 = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.inputs.startup] path = "materials/startup.spice" @@ -1566,10 +1559,10 @@ lower = 0 rationale = "The absolute error, voltage span, charge magnitude or recovery deviation has a nonnegative measurement domain; its positive value remains a continuously scored quality observation." [task.evaluation.pre_layout] -source_report_sha256 = "df195fb9db62a6e2d844704fe11086b04388656f3ee1156a6606fa035a5166c1" +source_report_sha256 = "d55217b40799ffbbba5e101fa186f43af87d8c956da761fb0e6fd374d05a6304" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"32c1c2e1587332ab435be4fd69607487361bf9ccb0bf92d5aa5b4f175e9723b0\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1616,27 +1609,27 @@ transient = "transient.raw" voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] -deck = "afe7c38e8417384a73d95e634318fed67c45c973cad29a549070052d2d6b373d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +deck = "f7a1e178ce2bdfc55a194b29f6ef34ede9df9330b966b4d5236d3273d276270e" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v] -value = 0.7047151436665 +value = 0.7047151474327 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.dc_gain_db] -value = 51.12367 +value = 51.3456 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_phase_margin_deg] -value = 87.35238 +value = 87.27068 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.final_unity_hz] -value = 401330.1 +value = 411286.7 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.hf_gain_db] -value = -78.37829 +value = -78.29514 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.loaded_ripple_v] @@ -1644,43 +1637,43 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.maximum_v] -value = 0.8974921 +value = 0.8976586 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.mean_power_w] -value = 0.0004651032 +value = 0.000465078 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_return_distance] -value = 0.9511315111529 +value = 0.9495813060646 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.minimum_v] -value = 0.877785 +value = 0.8779374 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.output_v] -value = 0.8880889483606 +value = 0.8882040963865 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.phase_margin_deg] -value = 87.35238 +value = 87.27068 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.power_w] -value = 0.0003421268108198 +value = 0.0003421015217156 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.quiescent_a] -value = 8.510567568318e-05 +value = 8.508460142971e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_load_v] -value = 0.01446227 +value = 0.01428184 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.recovery_release_v] -value = 0.01191179 +value = 0.0117959 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.released_ripple_v] @@ -1688,19 +1681,13 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.return_phase_excursion_deg] -value = 84.12297220332 +value = 84.20136625775 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.unity_hz] -value = 401330.1 +value = 411286.7 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "7a38ec1885e360e0761bed6fffcf613d659c102f86b1a614fd5d67cbb7994895" -ac = "ed962fc4125ad3de6025726e8f0003e53c7dd3fb23c0f1d3fbeb7c236d95d28f" -transient = "3a68c5d4fc8eeb7e413f29975fd074283281d347e5d9700e1377372a84f59c99" -voltage = "bce6edac0d8a71c45b9f5a8ab95eff2d1638e156b1c1c8eccb3f69b7d0c0d8fd" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1746,27 +1733,27 @@ transient = "transient.raw" voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] -deck = "afe7c38e8417384a73d95e634318fed67c45c973cad29a549070052d2d6b373d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +deck = "f7a1e178ce2bdfc55a194b29f6ef34ede9df9330b966b4d5236d3273d276270e" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v] -value = 0.7047151408821 +value = 0.7047151448009 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.dc_gain_db] -value = 50.32356 +value = 50.54171 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_phase_margin_deg] -value = 87.45723 +value = 87.37736 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.final_unity_hz] -value = 401519.5 +value = 411484.1 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.hf_gain_db] -value = -81.75554 +value = -82.04251 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.loaded_ripple_v] @@ -1774,43 +1761,43 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.maximum_v] -value = 0.8945545 +value = 0.89481 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.mean_power_w] -value = 0.001009535 +value = 0.00100951 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_return_distance] -value = 0.9543758166564 +value = 0.9529360252904 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.minimum_v] -value = 0.8736976 +value = 0.8739364 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.output_v] -value = 0.8846893803919 +value = 0.8848896950052 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.phase_margin_deg] -value = 87.45723 +value = 87.37736 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.power_w] -value = 0.0007020645057035 +value = 0.0007020394404182 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.quiescent_a] -value = 8.505375475293e-05 +value = 8.503286701521e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_load_v] -value = 0.01810482 +value = 0.01783408 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.recovery_release_v] -value = 0.01531135 +value = 0.01511031 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.released_ripple_v] @@ -1818,19 +1805,13 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.return_phase_excursion_deg] -value = 83.84234105733 +value = 83.92301220732 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.unity_hz] -value = 401519.5 +value = 411484.1 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "bdc7095af0bfb161b892a72c4fc76372c570e6c362973bb2db178bde49c832cc" -ac = "8fa36a84b86db8fa2f74d8da60eab58f090cc544320ba065ab464c16c640e11c" -transient = "fbaa0b032424ffbdee85faf8192c6ddde9fda61a838122fa4bdac91f27e25f1e" -voltage = "c7f50e1fa471ad2106f3292a4d6a99798e81db8b91be1cca44bb3a6baa9eb1aa" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1876,27 +1857,27 @@ transient = "transient.raw" voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] -deck = "afe7c38e8417384a73d95e634318fed67c45c973cad29a549070052d2d6b373d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +deck = "f7a1e178ce2bdfc55a194b29f6ef34ede9df9330b966b4d5236d3273d276270e" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v] -value = 0.8047150875244 +value = 0.8047150925952 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.dc_gain_db] -value = 52.69066 +value = 52.91829 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_phase_margin_deg] -value = 87.34981 +value = 87.27022 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.final_unity_hz] -value = 405881.0 +value = 415987.1 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.hf_gain_db] -value = -78.15391 +value = -78.06757 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.loaded_ripple_v] @@ -1904,43 +1885,43 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.maximum_v] -value = 0.8992763 +value = 0.8994164 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.mean_power_w] -value = 0.000504547 +value = 0.0005045235 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_return_distance] -value = 0.9511911593507 +value = 0.949633531719 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.minimum_v] -value = 0.8798426 +value = 0.8799802 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.output_v] -value = 0.8898397025828 +value = 0.8899395649893 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.phase_margin_deg] -value = 87.34981 +value = 87.27022 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.power_w] -value = 0.0003713168517682 +value = 0.0003712933683873 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.quiescent_a] -value = 8.5628347514e-05 +value = 8.561028337481e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_load_v] -value = 0.01237304 +value = 0.01221669 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.recovery_release_v] -value = 0.01015946 +value = 0.01006044 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.released_ripple_v] @@ -1948,19 +1929,13 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.return_phase_excursion_deg] -value = 84.62667835083 +value = 84.70007291832 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.unity_hz] -value = 405881.0 +value = 415987.1 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "4a96150e440dcd0a79b78b5e7361d8673cde348d396baa64a167be93e791d9a8" -ac = "5118f59669423049f343c8dbe681b0a72d1dc9fad2a4322181a8c82e821c1899" -transient = "375719f297d50bb669813bcae8b23f01ac100e3a58f06dac1aba239c895ede75" -voltage = "ffa60d7dd76df78e3e278436c0c17f1ca2e8ef11fab6349f14de7a69aaf6f242" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -2006,27 +1981,27 @@ transient = "transient.raw" voltage = "voltage.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] -deck = "afe7c38e8417384a73d95e634318fed67c45c973cad29a549070052d2d6b373d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +deck = "f7a1e178ce2bdfc55a194b29f6ef34ede9df9330b966b4d5236d3273d276270e" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.bias_v] -value = 0.8047150845636 +value = 0.8047150903851 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.dc_gain_db] -value = 52.04243 +value = 52.26604 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_phase_margin_deg] -value = 87.45031 +value = 87.37278 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.final_unity_hz] -value = 406136.2 +value = 416251.4 unit = "Hz" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.hf_gain_db] -value = -81.59094 +value = -81.87032 unit = "dB" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.loaded_ripple_v] @@ -2034,43 +2009,43 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.maximum_v] -value = 0.8967692 +value = 0.8969872 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.mean_power_w] -value = 0.001094364 +value = 0.001094341 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_return_distance] -value = 0.9544611459902 +value = 0.9530162601444 unit = "1" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.minimum_v] -value = 0.8762814 +value = 0.8764957 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.output_v] -value = 0.8868929199626 +value = 0.8870682424645 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.phase_margin_deg] -value = 87.45031 +value = 87.37278 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.power_w] -value = 0.0007612641059572 +value = 0.0007612408137195 unit = "W" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.quiescent_a] -value = 8.558777381323e-05 +value = 8.556985670728e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_load_v] -value = 0.01550758 +value = 0.01527189 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.recovery_release_v] -value = 0.01310627 +value = 0.01293176 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.released_ripple_v] @@ -2078,19 +2053,13 @@ value = 0.0 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.return_phase_excursion_deg] -value = 84.41864831693 +value = 84.49349980624 unit = "deg" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.unity_hz] -value = 406136.2 +value = 416251.4 unit = "Hz" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "2dc8f08f850c8cd84b40764fbbd49dfb30ba7347f3441b0a196aa45f7a0f5930" -ac = "c3d5174cf03ad969d01b653eff280f64343ce15cde9f13f87e6ef7e06358480b" -transient = "fca971704ec5bcf9d9353653d2031016055cfc49910351f1c77b090387abf60b" -voltage = "e4fbd25e05e86fede227b8ee0bab6bf50cb8032e82666135f90c2b06eac77976" - [task.evaluation.pre_layout.jobs.source_startup_0] operation = "circuit.simulate" @@ -2116,23 +2085,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_0.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_0.measurements.minimum_v] -value = 2.120662e-06 +value = 2.150723e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_0.measurements.peak_v] -value = 0.881984 +value = 0.8822508 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_0.measurements.startup_error_v] -value = 0.018016 +value = 0.01774925 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_0.output_sha256] -transient = "c064af25fa1800bcb4a61278c10149537acf230a6e7361f6e2da2a2ba16843e5" - [task.evaluation.pre_layout.jobs.source_startup_1] operation = "circuit.simulate" @@ -2158,23 +2124,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_1.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_1.measurements.minimum_v] -value = 1.060331e-06 +value = 1.075361e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_1.measurements.peak_v] -value = 0.881984 +value = 0.8822508 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_1.measurements.startup_error_v] -value = 0.018016 +value = 0.01774925 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_1.output_sha256] -transient = "505231bf55052da3ec4d5c4dd5e64bf952066fea2f924bdcd4afc2136d829a5e" - [task.evaluation.pre_layout.jobs.source_startup_2] operation = "circuit.simulate" @@ -2200,23 +2163,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_2.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_2.measurements.minimum_v] -value = 2.134161e-06 +value = 2.163249e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_2.measurements.peak_v] -value = 0.8881357 +value = 0.8882499 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_2.measurements.startup_error_v] -value = 0.01186432 +value = 0.01175008 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_2.output_sha256] -transient = "d10177dabb17d34abec3648cadbd6123c62acbd20bd05152ef8be1e66f103844" - [task.evaluation.pre_layout.jobs.source_startup_3] operation = "circuit.simulate" @@ -2242,23 +2202,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_3.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_3.measurements.minimum_v] -value = 1.06708e-06 +value = 1.081624e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_3.measurements.peak_v] -value = 0.8881357 +value = 0.8882499 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_3.measurements.startup_error_v] -value = 0.01186432 +value = 0.01175008 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_3.output_sha256] -transient = "172815865375232e540636881c1363f72d3d55de158f802421272a295d3c7686" - [task.evaluation.pre_layout.jobs.source_startup_4] operation = "circuit.simulate" @@ -2284,23 +2241,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_4.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_4.measurements.minimum_v] -value = 2.297079e-06 +value = 2.329694e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_4.measurements.peak_v] -value = 0.8845583 +value = 0.8847909 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_4.measurements.startup_error_v] -value = 0.01544172 +value = 0.01520914 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_4.output_sha256] -transient = "20aa11982e518fb2a84dfe8f2c398a8cf2283174cfdc90cfc5d6eb03dac3c4e7" - [task.evaluation.pre_layout.jobs.source_startup_5] operation = "circuit.simulate" @@ -2326,23 +2280,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_5.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_5.measurements.minimum_v] -value = 1.14854e-06 +value = 1.164847e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_5.measurements.peak_v] -value = 0.8845583 +value = 0.8847909 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_5.measurements.startup_error_v] -value = 0.01544172 +value = 0.01520914 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_5.output_sha256] -transient = "7f1c5854fb0acaf429af696ac8316eea36195e6bcc101b56b7fd31ab6da81505" - [task.evaluation.pre_layout.jobs.source_startup_6] operation = "circuit.simulate" @@ -2368,23 +2319,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_6.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_6.measurements.minimum_v] -value = 2.311701e-06 +value = 2.343263e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_6.measurements.peak_v] -value = 0.8898758 +value = 0.8899736 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_6.measurements.startup_error_v] -value = 0.01012422 +value = 0.01002644 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_6.output_sha256] -transient = "fc5bd394fc4eed7c7c1a30ef78e637a372d25addd0b36b3d52df2af8c6008de1" - [task.evaluation.pre_layout.jobs.source_startup_7] operation = "circuit.simulate" @@ -2410,23 +2358,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_startup_7.input_sha256] deck = "aa70d7d0598b0440d74931d76518cf55acae9241833aa7692bfa77d09de6761d" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_startup_7.measurements.minimum_v] -value = 1.15585e-06 +value = 1.171631e-06 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_7.measurements.peak_v] -value = 0.8898758 +value = 0.8899736 unit = "V" [task.evaluation.pre_layout.jobs.source_startup_7.measurements.startup_error_v] -value = 0.01012422 +value = 0.01002644 unit = "V" -[task.evaluation.pre_layout.jobs.source_startup_7.output_sha256] -transient = "6dfb5254b0280b930e1ba857437afff541d472044a56a54b167ea36cab1178c9" - [task.evaluation.pre_layout.jobs.source_sweeps_0] operation = "circuit.simulate" @@ -2454,28 +2399,24 @@ load = "load.raw" [task.evaluation.pre_layout.jobs.source_sweeps_0.input_sha256] deck = "d222de54ff3743322617628cf4f21675a38ee63043ee845c255c709fe20955ab" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_sweeps_0.measurements.headroom_v] -value = 0.0099225 +value = 0.0093324 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_0.measurements.line_span_v] -value = 0.0017513 +value = 0.0017355 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_0.measurements.load_span_v] -value = 0.006189 +value = 0.0060353 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_0.measurements.regulation_floor_v] -value = 0.8799225 +value = 0.8793324 unit = "V" -[task.evaluation.pre_layout.jobs.source_sweeps_0.output_sha256] -line = "597809c53194839108a1209e21df1b015ef7df9cfe039b5dbb996867c35ff607" -load = "fe674612280e097cb6522f3d07ebb952e224be7fa6fdb1641453e1f91b1e18a7" - [task.evaluation.pre_layout.jobs.source_sweeps_1] operation = "circuit.simulate" @@ -2503,28 +2444,24 @@ load = "load.raw" [task.evaluation.pre_layout.jobs.source_sweeps_1.input_sha256] deck = "d222de54ff3743322617628cf4f21675a38ee63043ee845c255c709fe20955ab" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_sweeps_1.measurements.headroom_v] -value = 0.0639764 +value = 0.0587418 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_1.measurements.line_span_v] -value = 0.0025942 +value = 0.002562 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_1.measurements.load_span_v] -value = 0.006189 +value = 0.0060353 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_1.measurements.regulation_floor_v] -value = 0.9339764 +value = 0.9287418 unit = "V" -[task.evaluation.pre_layout.jobs.source_sweeps_1.output_sha256] -line = "466c2c6190d83ddefe7a46527c509985d13ecc814f22f298964e631a28abf420" -load = "fe674612280e097cb6522f3d07ebb952e224be7fa6fdb1641453e1f91b1e18a7" - [task.evaluation.pre_layout.jobs.source_sweeps_2] operation = "circuit.simulate" @@ -2552,28 +2489,24 @@ load = "load.raw" [task.evaluation.pre_layout.jobs.source_sweeps_2.input_sha256] deck = "d222de54ff3743322617628cf4f21675a38ee63043ee845c255c709fe20955ab" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_sweeps_2.measurements.headroom_v] -value = 0.0099225 +value = 0.0093324 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_2.measurements.line_span_v] -value = 0.0017513 +value = 0.0017355 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_2.measurements.load_span_v] -value = 0.005342 +value = 0.0052088 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_2.measurements.regulation_floor_v] -value = 0.8799225 +value = 0.8793324 unit = "V" -[task.evaluation.pre_layout.jobs.source_sweeps_2.output_sha256] -line = "597809c53194839108a1209e21df1b015ef7df9cfe039b5dbb996867c35ff607" -load = "2567d259f02b81876dccb50ba8fd3202012e69a03294edc791037e75e1792c25" - [task.evaluation.pre_layout.jobs.source_sweeps_3] operation = "circuit.simulate" @@ -2601,28 +2534,24 @@ load = "load.raw" [task.evaluation.pre_layout.jobs.source_sweeps_3.input_sha256] deck = "d222de54ff3743322617628cf4f21675a38ee63043ee845c255c709fe20955ab" -dut = "c3fd219b0a6bbce731ff1ad104c26838925f3f5cd3db063c2c476fdd6718372d" +dut = "2458df821525c8dd286f3642ef9ecfc7fdbcea679fe5b3c850ac2b8ba78b238f" [task.evaluation.pre_layout.jobs.source_sweeps_3.measurements.headroom_v] -value = 0.0639764 +value = 0.0587418 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_3.measurements.line_span_v] -value = 0.0025942 +value = 0.002562 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_3.measurements.load_span_v] -value = 0.005342 +value = 0.0052088 unit = "V" [task.evaluation.pre_layout.jobs.source_sweeps_3.measurements.regulation_floor_v] -value = 0.9339764 +value = 0.9287418 unit = "V" -[task.evaluation.pre_layout.jobs.source_sweeps_3.output_sha256] -line = "466c2c6190d83ddefe7a46527c509985d13ecc814f22f298964e631a28abf420" -load = "2567d259f02b81876dccb50ba8fd3202012e69a03294edc791037e75e1792c25" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -2662,7 +2591,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/input-pair-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl index f7128ca21c003aba06bce270cd31e19f778be8c5..f7abd394b01eda00b006b7ad764c5123f8905b15 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl @@ -1,442 +1,46 @@ -* Derived from analog-db ldo_001_analoggym_basic, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified: equivalent fingering, explicit physical passives/taps; -* reference 0.225 V and added 4 pF net10-output MIM compensation. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt ldo_001_analoggym_basic vdd vout vss ib vref vfb sense -MM12 vb4 vb3 net28 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -MM13 dm_1 vb3 net31 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -MM14 vb3 vb3 vss sub sg13_lv_nmos w=7.5u l=1.5u m=2 -MM15 voutn vb3 dm_2 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -MM16 net10 vb3 net106 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -MM17 net28 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=8 -MM18 net31 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=8 -MM19 dm_2 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=16 -MM20 net106 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=16 -MM21 net12 net7 vss sub sg13_lv_nmos w=6u l=2u m=120 -MM22 net7 net7 vss sub sg13_lv_nmos w=6u l=2u m=120 -MM10 net12 net10 net1 well_net1 sg13_lv_pmos w=8u l=0.5u m=12 -RRtap_net1_0 net1 well_net1 ntap1 A=4e-12 P=8e-6 -RRtap_net1_1 net1 well_net1 ntap1 A=4e-12 P=8e-6 -RRtap_net1_2 net1 well_net1 ntap1 A=4e-12 P=8e-6 -RRtap_net1_3 net1 well_net1 ntap1 A=4e-12 P=8e-6 -MM8 dm_2 sense net20 well_net20 sg13_lv_pmos w=10u l=1u m=3 -MM9 net106 vref net20 well_net20 sg13_lv_pmos w=10u l=1u m=3 -RRtap_net20_0 net20 well_net20 ntap1 A=4e-12 P=8e-6 -RRtap_net20_1 net20 well_net20 ntap1 A=4e-12 P=8e-6 -RRtap_net20_2 net20 well_net20 ntap1 A=4e-12 P=8e-6 -MM0 ib ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM1 vb4 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM11 vout net1 vdd well_vdd sg13_lv_pmos w=9u l=0.15u m=464 -MM2 dm_1 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM24 net1 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM3 vb3 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM4 net20 ib vdd well_vdd sg13_lv_pmos w=10u l=2u m=3 -MM5 voutn voutn vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM6 net10 voutn vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -MM7 net7 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -RRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_18 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_19 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_20 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_21 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_22 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_23 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_24 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_25 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_26 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_27 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_28 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_29 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_30 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_31 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_32 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_33 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_34 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_35 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_36 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_37 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_38 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_39 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_40 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_41 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_42 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_43 vdd well_vdd ntap1 A=4e-12 P=8e-6 -RRtap_vdd_44 vdd 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sub ptap1 A=4e-12 P=8e-6 -RRptap_96 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_97 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_98 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_99 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_100 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_101 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_102 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_103 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_104 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_105 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_106 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_107 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_108 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_109 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_110 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_111 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_112 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_113 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_114 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_115 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_116 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_117 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_118 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_119 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_120 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_121 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_122 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_123 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_124 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_125 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_126 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_127 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_128 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_129 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_130 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_131 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_132 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_133 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_134 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_135 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_136 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_137 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_138 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_139 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_140 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_141 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_142 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_143 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_144 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_145 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_146 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_147 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_148 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_149 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_150 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_151 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_152 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_153 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_154 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_155 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_156 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_157 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_158 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_159 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_160 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_161 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_162 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_163 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_164 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_165 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_166 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_167 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_168 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_169 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_170 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_171 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_172 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_173 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_174 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_175 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_176 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_177 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_178 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_179 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_180 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_181 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_182 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_183 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_184 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_185 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_186 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_187 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_188 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_189 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_190 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_191 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_192 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_193 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_194 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_195 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_196 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_197 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_198 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_199 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_200 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_201 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_202 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_203 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_204 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_205 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_206 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_207 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_208 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_209 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_210 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_211 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_212 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_213 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_214 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_215 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_216 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_217 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_218 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_219 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_220 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_221 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_222 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_223 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_224 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_225 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_226 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_227 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_228 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_229 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_230 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_231 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_232 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_233 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_234 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_235 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_236 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_237 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_238 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_239 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_240 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_241 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_242 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_243 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_244 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_245 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_246 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_247 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_248 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_249 vss sub ptap1 A=4e-12 P=8e-6 -RRptap_250 vss sub ptap1 A=4e-12 P=8e-6 -CC0_0 net106 vout cap_cmim w=42.685u l=42.685u m=1 -CC0_1 net106 vout cap_cmim w=42.685u l=42.685u m=1 -CC0_2 net106 vout cap_cmim w=42.685u l=42.685u m=1 -CCLOCAL_0 net10 vout cap_cmim w=51.64u l=51.64u m=1 -RR1_0 vout r11 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_1 r11 r12 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_2 r12 r13 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_3 r13 r14 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_4 r14 r15 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_5 r15 r16 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_6 r16 r17 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_7 r17 r18 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_8 r18 r19 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_9 r19 r110 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_10 r110 r111 sub rhigh w=1u l=17.465u m=1 b=0 -RR1_11 r111 vfb sub rhigh w=1u l=17.465u m=1 b=0 -RR2_0 vfb r21 sub rhigh w=1u l=17.465u m=1 b=0 -RR2_1 r21 r22 sub rhigh w=1u l=17.465u m=1 b=0 -RR2_2 r22 r23 sub rhigh w=1u l=17.465u m=1 b=0 -RR2_3 r23 vss sub rhigh w=1u l=17.465u m=1 b=0 +MM0 ib ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM1 vb4 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM10 net12 net10 net1 net1 sg13_lv_pmos w=8u l=0.5u m=12 +MM11 vout net1 vdd vdd sg13_lv_pmos w=9u l=0.15u m=464 +MM12 vb4 vb3 net28 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +MM13 dm_1 vb3 net31 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +MM14 vb3 vb3 vss vss sg13_lv_nmos w=1.5u l=1.5u m=10 +MM15 voutn vb3 dm_2 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +MM16 net10 vb3 net106 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +MM17 net28 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=40 +MM18 net31 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=40 +MM19 dm_2 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=80 +MM2 dm_1 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM20 net106 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=80 +MM21 net12 net7 vss vss sg13_lv_nmos w=6u l=2u m=120 +MM22 net7 net7 vss vss sg13_lv_nmos w=6u l=2u m=120 +MM24 net1 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM3 vb3 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM4 net20 ib vdd vdd sg13_lv_pmos w=5u l=2u m=6 +MM5 voutn voutn vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM6 net10 voutn vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM7 net7 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +MM8 dm_2 sense net20 net20 sg13_lv_pmos w=5u l=1u m=6 +MM9 net106 vref net20 net20 sg13_lv_pmos w=5u l=1u m=6 +C0_0 net106 vout cap_cmim w=42.685u l=42.685u m=3 +CLOCAL_0 net10 vout cap_cmim w=51.64u l=51.64u m=1 +RR1_0 vout r11 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_1 r11 r12 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_2 r12 r13 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_3 r13 r14 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_4 r14 r15 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_5 r15 r16 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_6 r16 r17 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_7 r17 r18 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_8 r18 r19 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_9 r19 r110 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_10 r110 r111 vss rhigh w=1u l=17.465u m=1 b=0 +RR1_11 r111 vfb vss rhigh w=1u l=17.465u m=1 b=0 +RR2_0 vfb r21 vss rhigh w=1u l=17.465u m=1 b=0 +RR2_1 r21 r22 vss rhigh w=1u l=17.465u m=1 b=0 +RR2_2 r22 r23 vss rhigh w=1u l=17.465u m=1 b=0 +RR2_3 r23 vss vss rhigh w=1u l=17.465u m=1 b=0 .ends ldo_001_analoggym_basic diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.spice index 2dee978c2f1042d184e3ed810bcf19b83f86edb0..49e2c9053996a6aaa0551ea7248865b67aabd1b4 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.spice @@ -1,442 +1,46 @@ -* Derived from analog-db ldo_001_analoggym_basic, fixed snapshot -* 263d0322f8900dc331536fbbe6c0e804514fc454. Copyright 2026 Danial Noori Zadeh. -* Required Notice: Copyright 2026 Danial Noori Zadeh -* Modified: equivalent fingering, explicit physical passives/taps; -* reference 0.225 V and added 4 pF net10-output MIM compensation. -* Normalized material: PolyForm Noncommercial 1.0.0; CODA-Team BSD component. -* See collection LICENSE and NOTICE. +* Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt ldo_001_analoggym_basic vdd vout vss ib vref vfb sense -XM12 vb4 vb3 net28 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -XM13 dm_1 vb3 net31 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -XM14 vb3 vb3 vss sub sg13_lv_nmos w=7.5u l=1.5u m=2 -XM15 voutn vb3 dm_2 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -XM16 net10 vb3 net106 sub sg13_lv_nmos w=7.5u l=1.5u m=8 -XM17 net28 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=8 -XM18 net31 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=8 -XM19 dm_2 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=16 -XM20 net106 vb4 vss sub sg13_lv_nmos w=7.5u l=1.5u m=16 -XM21 net12 net7 vss sub sg13_lv_nmos w=6u l=2u m=120 -XM22 net7 net7 vss sub sg13_lv_nmos w=6u l=2u m=120 -XM10 net12 net10 net1 well_net1 sg13_lv_pmos w=8u l=0.5u m=12 -XRtap_net1_0 net1 well_net1 ntap1 A=4e-12 P=8e-6 -XRtap_net1_1 net1 well_net1 ntap1 A=4e-12 P=8e-6 -XRtap_net1_2 net1 well_net1 ntap1 A=4e-12 P=8e-6 -XRtap_net1_3 net1 well_net1 ntap1 A=4e-12 P=8e-6 -XM8 dm_2 sense net20 well_net20 sg13_lv_pmos w=10u l=1u m=3 -XM9 net106 vref net20 well_net20 sg13_lv_pmos w=10u l=1u m=3 -XRtap_net20_0 net20 well_net20 ntap1 A=4e-12 P=8e-6 -XRtap_net20_1 net20 well_net20 ntap1 A=4e-12 P=8e-6 -XRtap_net20_2 net20 well_net20 ntap1 A=4e-12 P=8e-6 -XM0 ib ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM1 vb4 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM11 vout net1 vdd well_vdd sg13_lv_pmos w=9u l=0.15u m=464 -XM2 dm_1 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM24 net1 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM3 vb3 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM4 net20 ib vdd well_vdd sg13_lv_pmos w=10u l=2u m=3 -XM5 voutn voutn vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM6 net10 voutn vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XM7 net7 ib vdd well_vdd sg13_lv_pmos w=5u l=2u m=3 -XRtap_vdd_0 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_1 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_2 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_3 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_4 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_5 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_6 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_7 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_8 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_9 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_10 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_11 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_12 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_13 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_14 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_15 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_16 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_17 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_18 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_19 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_20 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_21 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_22 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_23 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_24 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_25 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_26 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_27 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_28 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_29 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_30 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_31 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_32 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_33 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_34 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_35 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_36 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_37 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_38 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_39 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_40 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_41 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_42 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_43 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_44 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_45 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_46 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_47 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_48 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_49 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_50 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_51 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_52 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_53 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_54 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_55 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_56 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_57 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_58 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_59 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_60 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_61 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_62 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_63 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_64 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_65 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_66 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_67 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_68 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_69 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_70 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_71 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_72 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_73 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_74 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_75 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_76 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_77 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_78 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_79 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_80 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_81 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_82 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_83 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_84 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_85 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_86 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_87 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_88 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_89 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_90 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_91 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_92 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_93 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_94 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_95 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_96 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_97 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_98 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_99 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_100 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_101 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_102 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_103 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_104 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_105 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_106 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_107 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_108 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_109 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_110 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_111 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_112 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_113 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_114 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_115 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_116 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_117 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_118 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_119 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_120 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_121 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_122 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_123 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_124 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_125 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_126 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_127 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_128 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_129 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRtap_vdd_130 vdd well_vdd ntap1 A=4e-12 P=8e-6 -XRptap_0 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_1 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_2 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_3 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_4 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_5 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_6 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_7 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_8 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_9 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_10 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_11 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_12 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_13 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_14 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_15 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_16 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_17 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_18 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_19 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_20 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_21 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_22 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_23 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_24 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_25 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_26 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_27 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_28 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_29 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_30 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_31 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_32 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_33 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_34 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_35 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_36 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_37 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_38 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_39 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_40 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_41 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_42 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_43 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_44 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_45 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_46 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_47 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_48 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_49 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_50 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_51 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_52 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_53 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_54 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_55 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_56 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_57 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_58 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_59 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_60 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_61 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_62 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_63 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_64 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_65 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_66 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_67 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_68 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_69 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_70 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_71 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_72 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_73 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_74 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_75 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_76 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_77 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_78 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_79 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_80 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_81 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_82 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_83 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_84 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_85 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_86 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_87 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_88 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_89 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_90 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_91 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_92 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_93 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_94 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_95 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_96 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_97 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_98 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_99 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_100 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_101 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_102 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_103 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_104 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_105 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_106 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_107 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_108 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_109 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_110 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_111 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_112 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_113 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_114 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_115 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_116 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_117 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_118 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_119 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_120 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_121 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_122 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_123 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_124 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_125 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_126 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_127 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_128 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_129 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_130 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_131 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_132 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_133 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_134 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_135 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_136 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_137 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_138 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_139 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_140 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_141 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_142 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_143 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_144 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_145 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_146 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_147 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_148 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_149 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_150 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_151 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_152 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_153 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_154 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_155 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_156 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_157 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_158 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_159 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_160 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_161 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_162 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_163 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_164 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_165 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_166 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_167 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_168 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_169 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_170 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_171 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_172 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_173 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_174 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_175 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_176 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_177 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_178 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_179 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_180 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_181 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_182 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_183 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_184 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_185 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_186 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_187 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_188 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_189 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_190 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_191 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_192 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_193 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_194 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_195 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_196 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_197 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_198 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_199 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_200 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_201 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_202 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_203 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_204 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_205 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_206 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_207 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_208 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_209 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_210 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_211 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_212 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_213 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_214 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_215 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_216 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_217 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_218 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_219 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_220 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_221 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_222 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_223 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_224 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_225 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_226 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_227 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_228 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_229 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_230 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_231 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_232 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_233 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_234 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_235 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_236 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_237 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_238 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_239 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_240 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_241 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_242 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_243 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_244 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_245 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_246 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_247 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_248 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_249 vss sub ptap1 A=4e-12 P=8e-6 -XRptap_250 vss sub ptap1 A=4e-12 P=8e-6 -XC0_0 net106 vout cap_cmim w=42.685u l=42.685u m=1 -XC0_1 net106 vout cap_cmim w=42.685u l=42.685u m=1 -XC0_2 net106 vout cap_cmim w=42.685u l=42.685u m=1 +XM0 ib ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM1 vb4 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM10 net12 net10 net1 net1 sg13_lv_pmos w=8u l=0.5u m=12 +XM11 vout net1 vdd vdd sg13_lv_pmos w=9u l=0.15u m=464 +XM12 vb4 vb3 net28 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +XM13 dm_1 vb3 net31 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +XM14 vb3 vb3 vss vss sg13_lv_nmos w=1.5u l=1.5u m=10 +XM15 voutn vb3 dm_2 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +XM16 net10 vb3 net106 vss sg13_lv_nmos w=1.5u l=1.5u m=40 +XM17 net28 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=40 +XM18 net31 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=40 +XM19 dm_2 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=80 +XM2 dm_1 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM20 net106 vb4 vss vss sg13_lv_nmos w=1.5u l=1.5u m=80 +XM21 net12 net7 vss vss sg13_lv_nmos w=6u l=2u m=120 +XM22 net7 net7 vss vss sg13_lv_nmos w=6u l=2u m=120 +XM24 net1 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM3 vb3 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM4 net20 ib vdd vdd sg13_lv_pmos w=5u l=2u m=6 +XM5 voutn voutn vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM6 net10 voutn vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM7 net7 ib vdd vdd sg13_lv_pmos w=5u l=2u m=3 +XM8 dm_2 sense net20 net20 sg13_lv_pmos w=5u l=1u m=6 +XM9 net106 vref net20 net20 sg13_lv_pmos w=5u l=1u m=6 +XC0_0 net106 vout cap_cmim w=42.685u l=42.685u m=3 XCLOCAL_0 net10 vout cap_cmim w=51.64u l=51.64u m=1 -XR1_0 vout r11 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_1 r11 r12 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_2 r12 r13 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_3 r13 r14 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_4 r14 r15 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_5 r15 r16 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_6 r16 r17 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_7 r17 r18 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_8 r18 r19 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_9 r19 r110 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_10 r110 r111 sub rhigh w=1u l=17.465u m=1 b=0 -XR1_11 r111 vfb sub rhigh w=1u l=17.465u m=1 b=0 -XR2_0 vfb r21 sub rhigh w=1u l=17.465u m=1 b=0 -XR2_1 r21 r22 sub rhigh w=1u l=17.465u m=1 b=0 -XR2_2 r22 r23 sub rhigh w=1u l=17.465u m=1 b=0 -XR2_3 r23 vss sub rhigh w=1u l=17.465u m=1 b=0 +XR1_0 vout r11 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_1 r11 r12 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_2 r12 r13 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_3 r13 r14 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_4 r14 r15 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_5 r15 r16 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_6 r16 r17 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_7 r17 r18 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_8 r18 r19 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_9 r19 r110 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_10 r110 r111 vss rhigh w=1u l=17.465u m=1 b=0 +XR1_11 r111 vfb vss rhigh w=1u l=17.465u m=1 b=0 +XR2_0 vfb r21 vss rhigh w=1u l=17.465u m=1 b=0 +XR2_1 r21 r22 vss rhigh w=1u l=17.465u m=1 b=0 +XR2_2 r22 r23 vss rhigh w=1u l=17.465u m=1 b=0 +XR2_3 r23 vss vss rhigh w=1u l=17.465u m=1 b=0 .ends ldo_001_analoggym_basic diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/schematic.svg deleted file mode 100644 index d2100b112092dfd40d2ecc7296a1521c59bc9cde..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_001_analoggym_basic{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.ldo_001_analoggym_basic","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["ldo_001_analoggym_basic","Bank1_131x_ntap1","Bank2_251x_ptap1","Bank3_12series_rhigh"],"banks":[{"name":"Bank1_131x_ntap1","count":131,"model":"ntap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank2_251x_ptap1","count":251,"model":"ptap1","params":{"a":"4e-12","p":"8e-6"}},{"name":"Bank3_12series_rhigh","count":12,"model":"rhigh","kind":"series","members":["RR1_0","RR1_1","RR1_2","RR1_3","RR1_4","RR1_5","RR1_6","RR1_7","RR1_8","RR1_9","RR1_10","RR1_11"]}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":16},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_001_analoggym_basic"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/design/ldo_001_analoggym_basic.icproj.json"}}Main-sheet overview; 3 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_001_analoggym_basicvddwell_vddvsssubvoutvfbsubvddnet10net20vb3vb4vssdm_2net106voutnnet10ibnet12net1vssnet7net1vdddm_1net28net31vssvddvb4ibvb3net20ibvddvoutvfbsubnet10vssr21r22r23net106voutvddwell_vddvsssubnet20well_net20net1well_net1vddvoutvssibvrefvfbsenseldo_001_analoggym_basicDifferential input and folded branchesMM55/2 ×3MM65/2 ×3MM810/1 ×3MM910/1 ×3MM157.5/1.5 ×8MM167.5/1.5 ×8MM197.5/1.5 ×16MM207.5/1.5 ×16MM5, MM6: B → well_vddMM8, MM9: B → well_net20N bulk → subIntermediate gain stagesMM75/2 ×3MM108/0.5 ×12MM245/2 ×3MM226/2 ×120MM216/2 ×120MM7, MM24: B → well_vddMM10: B → well_net1N bulk → subOutput / local feedbackMM119/0.15 ×464P bulk → well_vddBias mirrors and tail sourcesMM05/2 ×3MM15/2 ×3MM25/2 ×3MM35/2 ×3MM127.5/1.5 ×8MM137.5/1.5 ×8MM147.5/1.5 ×2MM177.5/1.5 ×8MM187.5/1.5 ×8P bulk → well_vddN bulk → subBias referenceMM410/2 ×3P bulk → well_vddSeries resistor networksXBANK3Bank3_12series_rhighCompensation and signal passivesCC0_042.7/42.7CC0_142.7/42.7CC0_242.7/42.7CCLOCAL_051.6/51.6RR2_01/17.5RR2_11/17.5RR2_21/17.5RR2_31/17.5R substrate → subSubstrate contacts and repeated tapsRRtap_net1_0A=4 µm²RRtap_net1_1A=4 µm²RRtap_net1_2A=4 µm²RRtap_net1_3A=4 µm²RRtap_net20_0A=4 µm²RRtap_net20_1A=4 µm²RRtap_net20_2A=4 µm²XBANK1Bank1_131x_ntap1XBANK2Bank2_251x_ptap1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/testbench.spice b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/testbench.spice index 59e953e60ea3a2676146e548d551791c51a96f15..77249f10aa2f731720f0ec741e504486a85977c2 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/testbench.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/testbench.spice @@ -41,7 +41,9 @@ let denominator=1-2*delta+aa-dd let transfer=(2*delta-aa+dd)/denominator let forward=(delta-aa)/denominator let reverse=(delta+dd)/denominator -let gain_db=db(transfer) +* Preserve exact zero transfer samples without aborting the entire AC vector. +* 1e-150 only defines a finite -3000 dB numerical floor at zero magnitude. +let gain_db=20*log10(mag(transfer)+1e-150) let phase_deg=180*cph(transfer)/pi meas ac dc_gain_db find gain_db at=0.01 meas ac unity_hz when gain_db=0 fall=1 diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md index a865d1768c30d4fdf27bda957222bf4bb980773a..374b89ef532981a2fa7ae88535ea8a86f5ae3e19 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md @@ -14,7 +14,7 @@ are distinct from the simpler 5T and mirror-OTA regulator cases. ## Inputs and Interface - `materials/circuit.cdl`: authoritative native physical circuit. -- `materials/circuit.spice`: matching simulator circuit with finite taps. +- `materials/circuit.spice`: matching simulator circuit with logical body nets. - `materials/testbench.spice`: bilateral loop and current-load recovery. - `materials/startup.spice`: synchronized zero-state resistive startup. - `materials/sweeps.spice`: line/load and downward headroom sweeps. @@ -27,14 +27,10 @@ zero-volt injection link; no additional servo or feedback element is permitted. The source's zero-volt output measurement link is collapsed into VOUT and relocated to this explicitly declared divider/input boundary. -Retain all 24 source MOS groups. Integer regrouping converts 1,168 source -fingers into 831 physical fingers with <=10 um individual width, preserving -each original group's total W, L and body connection exactly. Individual W/m -and diffusion perimeter change, so the maintained simulator and extracted -candidate are qualified independently. Other PMOS bodies use the VDD well; +Retain all 24 source MOS groups. The declared inputs retain upstream W/L/m with the reviewed geometry-grid adaptation. Other PMOS bodies use the VDD well; NMOS bodies and physical high-poly backplates use the VSS substrate contact. -Explicit 2 x 2 um substrate/well taps use <=20 um pitch. Preserve the current -native circuit's dimensions and total multiplicities; equivalent parallel +Well/substrate contacts must meet the native PDK rules. Preserve the declared +MOS dimensions and total multiplicities; equivalent parallel fingering requires all physical and electrical checks to pass. All internal passives are physical DUT elements: @@ -107,16 +103,16 @@ The phase margins at the first and last crossings must both lie within [0, 180] Submit GDSII top cell `ldo_001_analoggym_basic`, at most 32 MiB. Pass native IHP main/maximal DRC without waivers (standalone density/antenna disabled), -strict named-interface LVS with explicit taps, and a 5500 × 360 um functional +strict named-interface LVS with physically verified body connections, and a 5500 × 360 um functional envelope. All device/contact/interconnect drawing layers in the runtime `outline` contribute to area; annotation and pin-purpose layers do not. Candidate-derived Magic RC includes both capacitor plates, every poly segment, MOS and interconnect parasitic. Half-grid import and zero parasitic thresholds -are explicit. Native LVS checks the original GDS's tap labels; the Magic +are explicit. Native LVS checks the original GDS and actual body connections; the Magic extraction copy retains only Metal3 interface text, avoiding internal well-name -aliases without altering geometry. Magic idealizes well/substrate taps while -source simulation includes their finite models. Distributed substrate +aliases without altering geometry. Source simulation and extraction +use the same logical body-net boundary. Distributed substrate resistance/noise and fabrication signoff remain unqualified. ## Electrical Requirements and Scoring @@ -164,7 +160,7 @@ The measurements below use the supplied SPICE node and source names. `v(n)` is a | `line_span_v` | DC sweep: `(max v(vout) from=1.3 to=1.2)-(min v(vout) from=1.3 to=1.2)`. | V | minimize / saturating_ratio | 0 … +∞ | 1e-06 | response | | `load_span_v` | DC sweep: `(max v(vout))-(min v(vout))`. | V | minimize / saturating_ratio | 0 … +∞ | 1e-06 | response | -Area reference: **42364.42 um2**. The expanded circuit has 1240 device instances, a sum of device/contact envelopes 27974.3733 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. +Area reference: **42364.42 um2**. The reference engineering estimate used 1240 device instances, a sum of device/contact envelopes 27974.3733 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. Reference MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area. The capability coefficient is **9**, independent of this task's reference-normalized score. @@ -211,3 +207,5 @@ Discover task/resources/feedback through `/protocol/task.json`, IHP primitives and KLayout/Magic/ngspice. Write `/workspace/output/final.gds` and explicitly submit via the harness protocol. Host configuration, source records and reference answers are excluded from standard solver inputs. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml b/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml index 8d305ea8a456ec3dde38b411571058a1f480f90a..04b2fbd6d6597645f60f345f554496369d1791d8 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 20 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "21f1e53dc4cea5bfb62be1b5cbf01b4327566ffcfc4e014a2a6734f469632547" - [[assets]] path = "reference/ldo_008_fer_mirror_ota.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/schematic.svg deleted file mode 100644 index ed1756df3551ce78dc52b244662a31b88de03b7a..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_008_fer_mirror_ota{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.ldo_008_fer_mirror_ota","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["ldo_008_fer_mirror_ota","Bank1_40x_cap_cmim"],"banks":[{"name":"Bank1_40x_cap_cmim","count":40,"model":"cap_cmim","params":{"w":"51.64u","l":"51.64u","m":"1"}}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":3},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_008_fer_mirror_ota"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/design/ldo_008_fer_mirror_ota.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_008_fer_mirror_otaczerovoutvssnbiasegatevddvssvoutfbegatevoutczeroczerovddwell_vddvsssubsensevrefnbiasvssvddegatetailldiodevddvoutvssnbiasvreffbsenseldo_008_fer_mirror_otaihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresError amplifierMMLD8/0.5 ×4MMLM8/0.5 ×4MMDF6/0.3 ×4MMDR6/0.3 ×4MMNT8/0.5 ×4P bulk → well_vddN bulk → subBias referenceMMNB8/0.5N bulk → subPass device and dividerMMP8/0.2 ×60RRT_01/6.24RRB_01/6.24P bulk → well_vddR substrate → subCompensationRRC_01/1.32XBANK1Bank1_40x_cap_cmimR substrate → subBulk ties and device bankRRtap_vddA=730 µm²RRptapA=942 µm²Models: sg13_lv_nmos · sg13_lv_pmos · ntap1 · ptap1 · rhigh - diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml b/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml index 40e53bd5377ec08eb7fb77c544fee075e944be50..cd9d98b1d450d63fda224f8c1330ca46262a77ba 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml @@ -4,13 +4,6 @@ title = "Unity-Feedback Regulator with Internal Output Storage" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "f4e11e7de05a4ed825aadc39c01100ba0c80d50e284936738d4eab157e3e49f6" - [[assets]] path = "reference/ldo_009_fer_5t_pass.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/schematic.svg deleted file mode 100644 index 13fb875c1b4c9a364f500362329e080a86872bb2..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -ldo_009_fer_5t_pass{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.ldo_009_fer_5t_pass","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["ldo_009_fer_5t_pass","Bank1_5x_cap_cmim","Bank2_13x_cap_cmim"],"banks":[{"name":"Bank1_5x_cap_cmim","count":5,"model":"cap_cmim","params":{"w":"36.515u","l":"36.515u","m":"1"}},{"name":"Bank2_13x_cap_cmim","count":13,"model":"cap_cmim","params":{"w":"50.635u","l":"50.635u","m":"1"}}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":5},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["ldo_009_fer_5t_pass"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/design/ldo_009_fer_5t_pass.icproj.json"}}Main-sheet overview; 2 child sheets are available in the editable .icproj.json project. Equal net labels connect.ldo_009_fer_5t_passvoutotaovoutvssvssref0vrefnbiasvddvssotaovoutvoutvoutvssrbld1rbld2rbld3vddwell_vddvsssubsensevrefnbiasvssvddotaotailotaxvddvoutvssnbiasref0senseldo_009_fer_5t_passihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresError amplifierMMLD4/0.4MMLM4/0.4MMIP8/0.4 ×2MMIN8/0.4 ×2MMNT4/0.4 ×2P bulk → well_vddN bulk → subReference and biasMMNB4/0.4RRREF_01/6.94N bulk → subR substrate → subPass device and compensationMMP8/0.2 ×20XBANK1Bank1_5x_cap_cmimXBANK2Bank2_13x_cap_cmimP bulk → well_vddBleeder chainRRBLD_01/17.5RRBLD_11/17.5RRBLD_21/17.5RRBLD_31/17.5R substrate → subBulk ties and device banksRRtap_vddA=248 µm²RRptapA=395 µm²Models: sg13_lv_nmos · sg13_lv_pmos · ntap1 · ptap1 · rhigh - diff --git a/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml b/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml index 59d0f460f1a3b03ce01b29a229230364a2806318..aa08e1417de95bcea8f9aee88d6d5f3ba8cf3725 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml @@ -5,13 +5,6 @@ status = "qualified" in_core = true core_order = 6 -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "30cbe250b9fc7222f5a975d96250268c43bcd02d8b0df95be4769dbb039399c8" - [[assets]] path = "reference/smp_001_nmos_th.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/schematic.svg deleted file mode 100644 index 71aac5ee2100e74aeed36d2b1ff5d4326970146c..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -smp_001_nmos_th{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.smp_001_nmos_th","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["smp_001_nmos_th"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["smp_001_nmos_th"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/design/smp_001_nmos_th.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.smp_001_nmos_thvinclkvssvoutvsssubvinclkvoutvsssmp_001_nmos_thihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresSampling switch and hold capacitorMM02/0.13CC018.2/18.2N bulk → subBulk tapRRPTAPA=16 µm²Models: sg13_lv_nmos · cap_cmim · ptap1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml index 108d26d71a69635549ea2f9456569f03e95b0346..c93e20801a3d68932aa23956728f35ec1f9a8d4a 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml @@ -4,13 +4,6 @@ title = "Bidirectional CMOS Transmission Gate" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "94f651d65e8c2a1196c895a51e88aba6cc0b8b5e1d3dc7e2ee67684dcd14e1fd" - [[assets]] path = "reference/sw_001_transmission_gate_pair.gds" role = "physical-witness" @@ -28,18 +21,18 @@ environment = "ihp-sg13g2-mos-rc-tt" [task.inputs.description] path = "problem.md" format = "text" -sha256 = "3c24869d3b94e3cc185342b56bedf9c15d0014bdfa58e0106c3d1032e17e0790" +sha256 = "d8fa4e8c666bc3e70f8b8ad81d64721ce74ed90dc3d5c819b5b9e01e76826981" [task.inputs.netlist] path = "materials/circuit.cdl" format = "spice" subcircuit = "sw_001_transmission_gate_pair" -sha256 = "541f878fd2a9d6f0eab4f125d64563a2a2e56b0deb4fa7adef4d2db88adc11cf" +sha256 = "876abf23efe2510080ab3e623bc794339d8920bf8a7d30a476b80cdad91e027a" [task.inputs.simulation] path = "materials/circuit.spice" format = "spice" -sha256 = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +sha256 = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.inputs.performance] path = "materials/testbench.spice" @@ -1050,10 +1043,10 @@ baseline = [ ] [task.evaluation.pre_layout] -source_report_sha256 = "1d0f8db8ba72d24f8caec35c2e7a77e23b9ad9df552b842e63c8ce19b42403c8" +source_report_sha256 = "b573e04ee2f5ad31854730e6f9010d2542588224cf1425919b99da85cbefc204" [task.evaluation.pre_layout.backends] -"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}" +"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"0f975b3ce7692fcbe19ec46cf8a89bcd3d7d718eed443f714afa3033f9e33834\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"4dcb5fbfc420852d288df50eeafd019882b16f848105d0f76b0e26f9e4d4de2a\", \"image_id\": \"sha256:6c47f91ee32beb0e182f754de40ad76299b3eb44f92ab09b526d11c14a17dbdb\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5d384a76e9c131bac2ca2ea8519a17d0769e9ef6e93bd9cad97f6294738568db\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Wed Oct 7 12:04:25 UTC 2026\\n******\"}" [task.evaluation.pre_layout.jobs.source_condition_0] operation = "circuit.simulate" @@ -1082,28 +1075,24 @@ off = "off.raw" [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256] deck = "864061d38ce90c87d8f9d9dd0025a54bc4f7f2932a45828b1c5bb20f4c6d4c0c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.kcl_a] -value = 5.467397528019297e-19 +value = 5.26598443836034e-19 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.leakage_a] -value = 5.225431085025349e-12 +value = 5.225431088990833e-12 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.on_current_a] -value = 3.418258019745907e-05 +value = 3.418258019721253e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_0.measurements.ron_ohm] -value = 292.5466697433025 +value = 292.5466697454125 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256] -op = "58a1abad666a07a6380b16818f0a8955d27cdb06ca7d490f1d51163a963d4953" -off = "12d4ae5c8439feb0476a94857e23ac797279e178f9b34011f8cb1edb718c5300" - [task.evaluation.pre_layout.jobs.source_condition_1] operation = "circuit.simulate" @@ -1131,28 +1120,24 @@ off = "off.raw" [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256] deck = "864061d38ce90c87d8f9d9dd0025a54bc4f7f2932a45828b1c5bb20f4c6d4c0c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.kcl_a] -value = 5.467397528019297e-19 +value = 5.265984439370082e-19 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.leakage_a] -value = 5.581069846117431e-12 +value = 5.581069850330555e-12 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.on_current_a] -value = 3.418272616321964e-05 +value = 3.418272616297337e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_1.measurements.ron_ohm] -value = 292.545420521782 +value = 292.5454205238896 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256] -op = "9adfd68a68f8901aad5d0329cae13bbddf8432401b3986dfc6efb3fc29df7889" -off = "dcc12d1fcb6de9bcc4d1784b778f6914910cfeb09455eac45e3a4d3cad4d159d" - [task.evaluation.pre_layout.jobs.source_condition_2] operation = "circuit.simulate" @@ -1180,28 +1165,24 @@ off = "off.raw" [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256] deck = "864061d38ce90c87d8f9d9dd0025a54bc4f7f2932a45828b1c5bb20f4c6d4c0c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.kcl_a] -value = 7.476084960740552e-19 +value = 5.573921119784795e-19 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.leakage_a] -value = 3.158730538795454e-13 +value = 3.158730541080645e-13 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.on_current_a] -value = 9.236300590761957e-06 +value = 9.236300589216235e-06 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_2.measurements.ron_ohm] -value = 1082.684555546178 +value = 1082.684555727368 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256] -op = "9a84dd32cccf53f0bdb4ea8666bc9ed26fa8ea74905de1e577cc82164f5bf7d8" -off = "4c0e855889c3168ef25a80099914be9056603ffd9b2eb1799031263a37f707d0" - [task.evaluation.pre_layout.jobs.source_condition_3] operation = "circuit.simulate" @@ -1229,28 +1210,24 @@ off = "off.raw" [task.evaluation.pre_layout.jobs.source_condition_3.input_sha256] deck = "864061d38ce90c87d8f9d9dd0025a54bc4f7f2932a45828b1c5bb20f4c6d4c0c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.kcl_a] -value = 7.476084936506745e-19 +value = 5.573921119784795e-19 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.leakage_a] -value = 3.693045767334869e-13 +value = 3.693045769620039e-13 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.on_current_a] -value = 9.236297929657803e-06 +value = 9.236297928112191e-06 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_3.measurements.ron_ohm] -value = 1082.684867482453 +value = 1082.68486766363 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_3.output_sha256] -op = "c35c96a5f8430fae7607df9bfd65f0883e8a1ef14c40810d6c7de55ce8e2ed46" -off = "e48a2d380ce6c3d79613779c8c31d9cfcd2be3b15f54325695ab791b1a5dedc0" - [task.evaluation.pre_layout.jobs.source_condition_4] operation = "circuit.simulate" @@ -1278,28 +1255,24 @@ off = "off.raw" [task.evaluation.pre_layout.jobs.source_condition_4.input_sha256] deck = "864061d38ce90c87d8f9d9dd0025a54bc4f7f2932a45828b1c5bb20f4c6d4c0c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.kcl_a] -value = 3.252646118728339e-18 +value = 2.717662669625013e-18 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.leakage_a] -value = 4.900553384477247e-12 +value = 4.900553384803136e-12 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.on_current_a] -value = 1.120145164079445e-05 +value = 1.120145164062236e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_4.measurements.ron_ohm] -value = 892.7414339388932 +value = 892.7414339526086 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_4.output_sha256] -op = "997038bc723798714cf85838bd33a2a280351a668c7ca6e285c07c0543aebee9" -off = "623ba8be477303609539d6322ce82895f768d6f38f5757cf5b2b341826773904" - [task.evaluation.pre_layout.jobs.source_condition_5] operation = "circuit.simulate" @@ -1327,28 +1300,24 @@ off = "off.raw" [task.evaluation.pre_layout.jobs.source_condition_5.input_sha256] deck = "864061d38ce90c87d8f9d9dd0025a54bc4f7f2932a45828b1c5bb20f4c6d4c0c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.kcl_a] -value = 3.035805684231238e-18 +value = 2.934503117046811e-18 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.leakage_a] -value = 4.591467734399066e-12 +value = 4.59146773472122e-12 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.on_current_a] -value = 1.12013990718516e-05 +value = 1.120139907167929e-05 unit = "A" [task.evaluation.pre_layout.jobs.source_condition_5.measurements.ron_ohm] -value = 892.7456236363698 +value = 892.7456236501026 unit = "ohm" -[task.evaluation.pre_layout.jobs.source_condition_5.output_sha256] -op = "8dc129194093ea5b94a5f5ab0bbfc57caee6e7eac06e27ad7c884163768f522b" -off = "f8eebd571895f5cd3ea6277b37202f4352e9e00e436b579086dafa00c52c4157" - [task.evaluation.pre_layout.jobs.source_condition_6] operation = "circuit.simulate" @@ -1375,24 +1344,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_6.input_sha256] deck = "d8ea737f5eb6ecf9db58db71c05a6dc11b214eaa01dec971b3526a9f55647d4c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_6.measurements.feedthrough_v] -value = 0.00102290435574412 +value = 0.001022874437882432 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_6.measurements.hold_shift_v] -value = -0.00099854892225 +value = -0.000998534922249999 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_6.measurements.tracking_error_v] value = 3.592214749999999e-08 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_6.output_sha256] -op = "3215aaf3ecbd84b8c454569b3e5ac517c0d771c8c00adf436d767812b47763cc" -transient = "3b57c22d10716375c7d16b2a1028be77433d23e76b02e41b04e740ad9fee5e2c" - [task.evaluation.pre_layout.jobs.source_condition_7] operation = "circuit.simulate" @@ -1419,24 +1384,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_7.input_sha256] deck = "d8ea737f5eb6ecf9db58db71c05a6dc11b214eaa01dec971b3526a9f55647d4c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_7.measurements.feedthrough_v] -value = 0.001018386045139097 +value = 0.001018371239270566 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_7.measurements.hold_shift_v] -value = 0.000187150000000004 +value = 0.0001871749999999978 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_7.measurements.tracking_error_v] -value = 0.0019943776825 +value = 0.0019943774325 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_7.output_sha256] -op = "8033f89bebcbf15c1ed0816b8ed959ee2c9f6239db4291c89c03880ab672c8f5" -transient = "9d7a9c5725ec168dd8c835ef95bc882ca624d2ef3008e81b9ea0f8f643e2d908" - [task.evaluation.pre_layout.jobs.source_condition_8] operation = "circuit.simulate" @@ -1463,24 +1424,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_8.input_sha256] deck = "d8ea737f5eb6ecf9db58db71c05a6dc11b214eaa01dec971b3526a9f55647d4c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_8.measurements.feedthrough_v] -value = 0.0003744137619038357 +value = 0.0003744022726748231 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_8.measurements.hold_shift_v] -value = -0.00036526649615 +value = -0.000365265896175 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_8.measurements.tracking_error_v] -value = 1.70384e-09 +value = 1.70383975e-09 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_8.output_sha256] -op = "9199e552f16eae6c38cab118fad5db54f66118058670bbedcaeef6571e3d7040" -transient = "369d8583ec42c4964d77859e3aa873345c9d438d21a0e0478454bf1337a1ced1" - [task.evaluation.pre_layout.jobs.source_condition_9] operation = "circuit.simulate" @@ -1507,10 +1464,10 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_9.input_sha256] deck = "d8ea737f5eb6ecf9db58db71c05a6dc11b214eaa01dec971b3526a9f55647d4c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_9.measurements.feedthrough_v] -value = 0.0004088747126308467 +value = 0.0004088713834445867 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_9.measurements.hold_shift_v] @@ -1521,10 +1478,6 @@ unit = "V" value = 0.006039576375 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_9.output_sha256] -op = "3cc141f8bcaeaf8d46785b407c59185cabe98eb53404279bfddd31557f4cc8cd" -transient = "5de5a90cc0d13f5a5d94357d45868c659c49320f4aaab98762ea4edadc80308c" - [task.evaluation.pre_layout.jobs.source_condition_10] operation = "circuit.simulate" @@ -1551,24 +1504,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_10.input_sha256] deck = "d8ea737f5eb6ecf9db58db71c05a6dc11b214eaa01dec971b3526a9f55647d4c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_10.measurements.feedthrough_v] -value = 0.0003484213252500368 +value = 0.0003483970832416361 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_10.measurements.hold_shift_v] -value = 0.0003000688905000002 +value = 0.00030006829075 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_10.measurements.tracking_error_v] value = 2.8690585e-08 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_10.output_sha256] -op = "41a051c87f0a3376c326115e6a218d2241ac0fae4b861555913913d8ec5ef4f4" -transient = "389714a1c97e9ee53e991123d469c9e95f7d819481ec7d52e9e22cac7aaa74e3" - [task.evaluation.pre_layout.jobs.source_condition_11] operation = "circuit.simulate" @@ -1595,24 +1544,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_11.input_sha256] deck = "d8ea737f5eb6ecf9db58db71c05a6dc11b214eaa01dec971b3526a9f55647d4c" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_11.measurements.feedthrough_v] -value = 0.0004957117103574493 +value = 0.0004957136656897898 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_11.measurements.hold_shift_v] -value = 0.001471475000000028 +value = 0.001471500000000028 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_11.measurements.tracking_error_v] -value = 0.005029772400000001 +value = 0.0050297699 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_11.output_sha256] -op = "252fe027f4dff9a47c0b9059335948891fccbeb3a35fc49d4f175db08587c515" -transient = "592b88d1d31e4229bb881150adf430cb7f945d7e4f3bba87f1f160175d8a605c" - [task.evaluation.pre_layout.jobs.source_condition_12] operation = "circuit.simulate" @@ -1639,24 +1584,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_12.input_sha256] deck = "6ddd7fbfd989ab09a10c4127ca4746a6b93f33e5469bb63375bf39c904ecafe2" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_12.measurements.feedthrough_v] -value = 0.001022904355744481 +value = 0.001022874437881988 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_12.measurements.hold_shift_v] -value = -0.00099854892225 +value = -0.000998534922249999 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_12.measurements.tracking_error_v] value = 3.592214749999999e-08 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_12.output_sha256] -op = "2c4ec32c2a61accac0b7d87da33c506655f0eea224679a664b75f6469473e673" -transient = "dfc3f4c18d072edec9c88862a47173f7dd01531301000579c05d9cadf31dfbf7" - [task.evaluation.pre_layout.jobs.source_condition_13] operation = "circuit.simulate" @@ -1683,24 +1624,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_13.input_sha256] deck = "6ddd7fbfd989ab09a10c4127ca4746a6b93f33e5469bb63375bf39c904ecafe2" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_13.measurements.feedthrough_v] -value = 0.001018386045139083 +value = 0.001018371239270538 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_13.measurements.hold_shift_v] -value = 0.000187150000000004 +value = 0.0001871749999999978 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_13.measurements.tracking_error_v] -value = 0.0019943776825 +value = 0.0019943774325 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_13.output_sha256] -op = "accdb669fafbf63248f81e5903b4e43deee4c63b986dce2991a69dcd00fd2d32" -transient = "15ec8310563b92c68c21c5ba54687b47c9309d93bd366f5a57e5ecebdf204f47" - [task.evaluation.pre_layout.jobs.source_condition_14] operation = "circuit.simulate" @@ -1727,24 +1664,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_14.input_sha256] deck = "6ddd7fbfd989ab09a10c4127ca4746a6b93f33e5469bb63375bf39c904ecafe2" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_14.measurements.feedthrough_v] -value = 0.0003744137619019483 +value = 0.0003744022726723806 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_14.measurements.hold_shift_v] -value = -0.00036526649615 +value = -0.000365265896175 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_14.measurements.tracking_error_v] -value = 1.70384e-09 +value = 1.703842e-09 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_14.output_sha256] -op = "d3234f6c8a21b253557130d1762e5c5ff4014ebee6063f4b1d4da1d727b78323" -transient = "71a914cb9218ca358843b036761baff0627b1ac76ce58b34f5b8782fb00003f8" - [task.evaluation.pre_layout.jobs.source_condition_15] operation = "circuit.simulate" @@ -1771,10 +1704,10 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_15.input_sha256] deck = "6ddd7fbfd989ab09a10c4127ca4746a6b93f33e5469bb63375bf39c904ecafe2" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_15.measurements.feedthrough_v] -value = 0.000408874712637175 +value = 0.0004088713834420332 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_15.measurements.hold_shift_v] @@ -1785,10 +1718,6 @@ unit = "V" value = 0.006039576375 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_15.output_sha256] -op = "27bbdbf492cf306ca15b6aaa1c98d99244246476fe3bc84fa5329bda89f54afa" -transient = "b71281f7e635f071e27510e4959776402ea76b401635b053fec5017ef6928f1b" - [task.evaluation.pre_layout.jobs.source_condition_16] operation = "circuit.simulate" @@ -1815,24 +1744,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_16.input_sha256] deck = "6ddd7fbfd989ab09a10c4127ca4746a6b93f33e5469bb63375bf39c904ecafe2" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_16.measurements.feedthrough_v] -value = 0.0003484213252475943 +value = 0.0003483970832378613 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_16.measurements.hold_shift_v] -value = 0.0003000688905000002 +value = 0.00030006829075 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_16.measurements.tracking_error_v] value = 2.8690585e-08 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_16.output_sha256] -op = "186291199664a48c1b92478fde7811377c28c6c8ac246050073249aa4b4cc72d" -transient = "ac18ae6f0e08a54c026ad7abd8a85fd36c6121cec9aa797f47d7b8a213d83beb" - [task.evaluation.pre_layout.jobs.source_condition_17] operation = "circuit.simulate" @@ -1859,24 +1784,20 @@ transient = "transient.raw" [task.evaluation.pre_layout.jobs.source_condition_17.input_sha256] deck = "6ddd7fbfd989ab09a10c4127ca4746a6b93f33e5469bb63375bf39c904ecafe2" -dut = "e8db280b7f1bff9218d038f96d04fc05491137bde1c0b57fac0430e3c5506a3e" +dut = "c5a3d9b82ed9eeb42d2c231cf9e39da2e761143253f8cd752b121d1d64da03e4" [task.evaluation.pre_layout.jobs.source_condition_17.measurements.feedthrough_v] -value = 0.0004957117103590036 +value = 0.0004957136656831285 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_17.measurements.hold_shift_v] -value = 0.001471475000000028 +value = 0.001471500000000028 unit = "V" [task.evaluation.pre_layout.jobs.source_condition_17.measurements.tracking_error_v] -value = 0.005029772400000001 +value = 0.0050297699 unit = "V" -[task.evaluation.pre_layout.jobs.source_condition_17.output_sha256] -op = "1b58ce40e4efc4576e14b2feaf387888c6565664854f4cf8ce7576d69c53df4f" -transient = "4cf320808877a9e28bf0b1ff6826508b8174ad574d54d574d18b7eb7f342d872" - [toolchain.bindings] "layout.artifact" = "artifact" "layout.drc" = "drc" @@ -1916,7 +1837,7 @@ support = "klayout" image = "iclayout-eda-open:local" check = "lvs" support = "build/support/analog-db-klayout" -profile = "lvs-upstream.json" +profile = "lvs-logical-mos.json" timeout_seconds = 600 [toolchain.backends.rc] diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl index db23df8301802e99c7e235d9e9b95ebbb3d2c112..388c089294e1f574ddd9d014bed5ac01f27e1774 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl +++ b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl @@ -1,9 +1,6 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt sw_001_transmission_gate_pair port_a port_b vctl vctl_not vdd vss -RT0 vss sub ptap1 A=4e-12 P=8e-6 -MM1 port_a vctl port_b sub sg13_lv_nmos w=2u l=0.13u m=1 -RT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -MM2 port_b vctl_not port_a well_1 sg13_lv_pmos w=2u l=0.13u m=1 -RTSUB vss sub ptap1 A=4e-12 P=8e-6 +MM1 port_a vctl port_b vss sg13_lv_nmos w=2u l=0.13u m=1 +MM2 port_b vctl_not port_a vdd sg13_lv_pmos w=2u l=0.13u m=1 .ends sw_001_transmission_gate_pair diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.spice b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.spice index ee8becc2fea3313c2ce1b9f275e1f9040a3888a6..7720beacf5a7c45dd826539317b3586a38b9205a 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.spice +++ b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.spice @@ -1,9 +1,6 @@ * Copyright 2026 Danial Noori Zadeh. See collection LICENSE and NOTICE. -* Fixed IHP binding; external bias ports and native physical taps. +* Logical upstream MOS W/L/m and body nets; reviewed native passives. .subckt sw_001_transmission_gate_pair port_a port_b vctl vctl_not vdd vss -XT0 vss sub ptap1 A=4e-12 P=8e-6 -XM1 port_a vctl port_b sub sg13_lv_nmos w=2u l=0.13u m=1 -XT1 vdd well_1 ntap1 A=4e-12 P=8e-6 -XM2 port_b vctl_not port_a well_1 sg13_lv_pmos w=2u l=0.13u m=1 -XTSUB vss sub ptap1 A=4e-12 P=8e-6 +XM1 port_a vctl port_b vss sg13_lv_nmos w=2u l=0.13u m=1 +XM2 port_b vctl_not port_a vdd sg13_lv_pmos w=2u l=0.13u m=1 .ends sw_001_transmission_gate_pair diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/schematic.svg deleted file mode 100644 index 459da922f634235cb84f9071c981580e2e9c56ce..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -sw_001_transmission_gate_pair{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.sw_001_transmission_gate_pair","source_netlist":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["sw_001_transmission_gate_pair"],"banks":[],"limitations":["Physical R/C/Q use external model bindings with X-prefixed internal references; the editable project retains the original terminals and model bindings. Exported decks are for connectivity inspection, not replacement simulation decks."],"known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["sw_001_transmission_gate_pair"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/design/sw_001_transmission_gate_pair.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.sw_001_transmission_gate_pairport_aport_bvctlvctl_notvssvddsubwell_1sw_001_transmission_gate_pairComplementary transmission pathMM1 · NMOSW/L 2/0.13 µm · m=1MM2 · PMOSW/L 2/0.13 µm · m=1NMOS bulk → subPMOS bulk → well_1Well and substrate contactsRT0ptap1 · A=4e-12 P=8e-6RTSUBptap1 · A=4e-12 P=8e-6RT1ntap1 · A=4e-12 P=8e-6 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md index d7236c16902e85ab395a9667c75e1b7591f2de58..98b45aa4da1cd231ce3f4b74a18f9cf5e82327ae 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md +++ b/tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md @@ -6,7 +6,7 @@ Implement `sw_001_transmission_gate_pair` with the complete fixed topology and m ## Inputs and Interface -`materials/circuit.cdl` is the authoritative physical netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/forward.spice`, `materials/reverse.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `port_a port_b vctl vctl_not vdd vss`. The fixture supplies complementary controls externally. Both signal/control ports stay within 0–1.5 V. Native body taps remain physically checked; finite well/substrate resistances are outside the Magic RC compact-model boundary. +`materials/circuit.cdl` is the authoritative logical circuit netlist; `materials/circuit.spice` is its simulator representation. `materials/testbench.spice`, `materials/forward.spice`, `materials/reverse.spice` supply the performance stimuli and measurements. `problem.md` is this contract. Ordered ports: `port_a port_b vctl vctl_not vdd vss`. The fixture supplies complementary controls externally. Both signal/control ports stay within 0–1.5 V. Native body taps remain physically checked; finite well/substrate resistances are outside the Magic RC compact-model boundary. ## Operating Conditions @@ -18,7 +18,7 @@ Source and candidate jobs use exactly the same test apparatus, parameters, nomin Submit a valid GDSII containing top cell `sw_001_transmission_gate_pair`, at most 10485760 bytes. Pass the pinned native DRC profile, named-interface LVS and functional outline checks. Maximum functional width/height are 5000/1000 um. The complete functional layer set is `[[1, 0], [3, 0], [5, 0], [6, 0], [7, 0], [8, 0], [10, 0], [11, 0], [13, 0], [14, 0], [19, 0], [24, 0], [26, 0], [28, 0], [29, 0], [30, 0], [31, 0], [32, 0], [33, 0], [35, 0], [36, 0], [40, 0], [44, 0], [46, 0], [49, 0], [50, 0], [51, 0], [52, 0], [53, 0], [55, 0], [58, 0], [66, 0], [67, 0], [90, 0], [101, 0], [111, 0], [125, 0], [126, 0], [128, 0], [129, 0], [133, 0], [134, 0], [139, 0], [152, 0]]` (layer/datatype pairs); text/annotation geometry is excluded. There are no case-local DRC waivers. Geometry bounds are generous task/resource limits, not an area score anchor. -Post-layout simulation uses distributed wire RC from native candidate GDS and retains physical MOS, resistors and capacitors; LVS cannot replace PEX. Magic idealizes well/substrate contacts while source simulation retains finite native contact models; no distributed substrate resistance or noise accuracy is claimed. +Post-layout simulation uses distributed wire RC from native candidate GDS and retains physical MOS, resistors and capacitors; LVS cannot replace PEX. Source and Magic extraction use logical well/substrate body nets; no distributed substrate resistance or noise accuracy is claimed. ## Electrical Requirements and Scoring @@ -77,3 +77,5 @@ The source and extracted-candidate decks require absolute external DC current conservation residual `kcl_a <= 1e-09 A`. A larger residual aborts simulation and produces an evaluator error with unknown score, rather than a functional rejection. The reported residual is an unscored diagnostic. + +The authoritative MOS input preserves the original logical groups, W/L/m and all four terminal nets. Verified unit arrays, multiple fingers, shared diffusion and shared wells on the same body net are allowed. Native LVS checks connectivity and equivalent device parameters; native DRC checks actual well/substrate contacts. Contact count, dimensions, area/perimeter and the reference well partition are not circuit constraints. PEX uses actual diffusion geometry and interconnect RC, with logical body nets as its boundary; distributed substrate/well resistance is outside this extraction model. diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml b/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml index bf04c33678788ddb4e5ec27df15ab6ed2e74deb4..ee3506a36895f0aecb3b54e91e165980a29e0e3a 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml @@ -4,13 +4,6 @@ title = "Differential Polarity-Commutating Switch" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "93ebbb5de37e1d03b341bd3092195b5ce758de94cb8371f422568b9fb44c99c4" - [[assets]] path = "reference/sw_002_chopper_diff.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/schematic.svg deleted file mode 100644 index fe792131ab4a6634c062cc4fc19b3adc0f4683bc..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -sw_002_chopper_diff{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.sw_002_chopper_diff","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["sw_002_chopper_diff"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["sw_002_chopper_diff"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/design/sw_002_chopper_diff.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.sw_002_chopper_diffvb_nvctlva_pvb_pva_nvctl_notvsssubvddwellvb_pvctl_notva_pvb_nva_nvctlva_pva_nvb_pvb_nvctlvctl_notvddvsssw_002_chopper_diffihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresStraight-through phaseMM22/0.13MM42/0.13MM12/0.13MM32/0.13P bulk → wellN bulk → subCross-connected phaseMM62/0.13MM82/0.13MM52/0.13MM72/0.13P bulk → wellN bulk → subBulk tapsRRptap1A=130 µm²RRntap1A=65 µm²Models: sg13_lv_nmos · sg13_lv_pmos · ptap1 · ntap1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml b/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml index fb245f55811a7a66a8382de3fbc0e8992291f762..30a29e56179fdf58bedecf9480644ef42d29d243 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml @@ -4,13 +4,6 @@ title = "Three-Bit MIM Capacitive Transfer Bank" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "3aa32a062f793570fe03d1565accf69434e99586adedbb8af23d6ac93b6b3db7" - [[assets]] path = "reference/sw_003_binary_capbank.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/schematic.svg deleted file mode 100644 index 9bac4328c98e6a1a8b5627ae4904490c928d26e2..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -sw_003_binary_capbank{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.sw_003_binary_capbank","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["sw_003_binary_capbank"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/circuit.cdl","known_editor_diagnostics":{},"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["sw_003_binary_capbank"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/design/sw_003_binary_capbank.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.sw_003_binary_capbankVCMbot0V_D1_NOTvinpV_D1VCMvoutbot1V_D2_NOTvinpV_D2VCMvoutbot2voutvinpVSSsubVDDwellvoutV_D0_NOTvinpV_D0vinpvoutVCMVDDVSSV_D0V_D0_NOTV_D1V_D1_NOTV_D2V_D2_NOTsw_003_binary_capbankihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresBit 0MM20.15/0.13MM40.15/0.13MM10.15/0.13MM30.15/0.13CC2_025.9/25.9P bulk → wellN bulk → subBit 1MM60.15/0.13MM80.15/0.13MM50.15/0.13MM70.15/0.13CC3_025.9/25.9CC3_125.9/25.9P bulk → wellN bulk → subBit 2MM100.15/0.13MM120.15/0.13MM90.15/0.13MM110.15/0.13CC4_025.9/25.9CC4_125.9/25.9CC4_225.9/25.9CC4_325.9/25.9P bulk → wellN bulk → subFixed capacitorCC1_025.9/25.9Bulk tiesRRptap1A=195 µm²RRntap1A=97.6 µm²Models: sg13_lv_nmos · sg13_lv_pmos · ptap1 · ntap1 · cap_cmim - diff --git a/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml b/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml index dc131beb8a0b022839e49f0f53c8de2786bc7477..2a137e9a6df21d784ca84831ca3c09bd5736b5ec 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml @@ -4,13 +4,6 @@ title = "Resistor-Pullup NMOS Shunt Trim" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "b883d8512d8989203231d48cefef7f73a6c12f8cfadf628b19bf13f6e185519d" - [[assets]] path = "reference/trm_001_vcr.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/schematic.svg deleted file mode 100644 index a33268fbe42bd8b3d83e63efd8cd36c4d870e019..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -trm_001_vcr{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.trm_001_vcr","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["trm_001_vcr","Bank1_8series_rhigh"],"banks":[{"name":"Bank1_8series_rhigh","count":8,"model":"rhigh","kind":"series","members":["RR0_0","RR0_1","RR0_2","RR0_3","RR0_4","RR0_5","RR0_6","RR0_7"]}],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/circuit.cdl","known_editor_diagnostics":{"ERC_ILLEGAL_PIN_NAME":8},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks.","The upstream ERC compares imported pins only with visible artwork pins, so it flags hidden resistor B / HBT S terminals. Full terminal connections are retained and independently checked against the source."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["trm_001_vcr"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/design/trm_001_vcr.icproj.json"}}Main-sheet overview; 1 child sheets are available in the editable .icproj.json project. Equal net labels connect.trm_001_vcrvddvoutsubvddvoutsubvoutvcodevssvsssubvddvcodevoutvsstrm_001_vcrihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresResistive pull-upXBANK1Bank1_8series_rhighVoltage-controlled shuntMM02/0.5N bulk → subBulk tapRRptapA=41 µm²Models: sg13_lv_nmos · ptap1 - diff --git a/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml b/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml index f4f1b46a0196e5857b8ab17554b2ada32a0aba95..60333c61abce09f8625340b3c05515b22692ee85 100644 --- a/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml +++ b/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml @@ -4,13 +4,6 @@ title = "Mixed LV/HV VGS Reference with Picoampere Load and Zero-State Recovery" status = "qualified" in_core = false -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "5b0e6a195c2e5d0303b6605f093d5f5a9c893a76ab6f81b1cb06e373c1842e94" - [[assets]] path = "reference/vref_001_vgs.gds" role = "physical-witness" diff --git a/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/schematic.svg b/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/schematic.svg deleted file mode 100644 index 51f67eedebf6ccd73e7d27ea0929da38087c95a7..0000000000000000000000000000000000000000 --- a/tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/schematic.svg +++ /dev/null @@ -1,2 +0,0 @@ -vref_001_vgs{"format":"iclayout-schematic","case_id":"ihp-sg13g2.analog-db.vref_001_vgs","authoring_tool":"Analog Canvas","tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","verification":"Editable project graph matches the source subcircuits, ordered ports, terminal nets, models and literal parameters.","license":"tasks/ihp-sg13g2/analog-db/","sheets":["vref_001_vgs"],"banks":[],"source_netlist":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/circuit.cdl","known_editor_diagnostics":{},"limitations":["Physical R/C/Q primitives are represented by external model bindings with X-prefixed internal references; schematic labels show the original references. Exports are for connectivity inspection, not replacement simulation decks."],"svg_export":{"tool_commit":"cbc18ee76ef91d88dd3e2dea9b47dd6d759f2d8f","rendered_sheets":["vref_001_vgs"],"scope":"main-sheet","editable_project":"tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/design/vref_001_vgs.icproj.json"}}Complete single-sheet circuit. Equal net labels connect.vref_001_vgsvddvssvrefvssvddvrefvssvref_001_vgsihp-sg13g2 · analog-db | W/L in µm · display rounded to 3 significant figuresVGS referenceM02.5/2M11/2N bulk → vssBulk tapRTAPA=80 µm²Models: sg13_lv_nmos · sg13_hv_nmos · ptap1 - diff --git a/tasks/ihp-sg13g2/pdk.toml b/tasks/ihp-sg13g2/pdk.toml index d55d01ba55237e9f3159dc01a5d4367ff7656d35..9eaba854652206f6ca76fe74087dd8a1e4f394fc 100644 --- a/tasks/ihp-sg13g2/pdk.toml +++ b/tasks/ihp-sg13g2/pdk.toml @@ -1314,3 +1314,6 @@ content = """ limitations under the License. """ format = "text" + +[profiles.klayout.generated."lvs-logical-mos.json"] +content = "{\n \"deck\": \"ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2.lvs\",\n \"variables\": {\n \"run_mode\": \"flat\",\n \"no_net_names\": \"false\",\n \"spice_comments\": \"false\",\n \"net_only\": \"false\",\n \"no_simplify\": \"false\",\n \"no_series_res\": \"false\",\n \"no_parallel_res\": \"false\",\n \"combine_devices\": \"false\",\n \"top_lvl_pins\": \"false\",\n \"purge\": \"false\",\n \"purge_nets\": \"false\",\n \"disable_tap_extraction\": \"true\",\n \"ignore_top_ports_mismatch\": \"false\"\n },\n \"scope\": \"SG13G2 logical MOS LVS: physical tap connections join well/substrate to their actual conductors; taps are not schematic devices. Native simplification compares parallel-equivalent MOS W/L and all four terminals, native passives, and strict named top-level ports.\",\n \"layer_names\": {\n \"metal1\": \"metal1_con\"\n }\n}\n" diff --git a/tasks/sky130A/OpenFASOC/cases/current_mirror/case.toml b/tasks/sky130A/OpenFASOC/cases/current_mirror/case.toml index 6a9a75533b8093de8358001f4c849cc1ef6044dc..1f3aaaf7adf01513edf974c305498ef820be7444 100644 --- a/tasks/sky130A/OpenFASOC/cases/current_mirror/case.toml +++ b/tasks/sky130A/OpenFASOC/cases/current_mirror/case.toml @@ -15,13 +15,6 @@ visibility = "maintainer" format = "gds" sha256 = "b8c3502e84339b0c676161e3d362e0345e5aadff601d0a020a0056b2540ddb29" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "b3e2638f76ea60891ff3b950fce10ba4b5b77743cc7514f3a1e767dd8ec03c86" - [task] kind = "netlist_to_gds" hours = 1 diff --git a/tasks/sky130A/OpenFASOC/cases/current_mirror/materials/schematic.svg b/tasks/sky130A/OpenFASOC/cases/current_mirror/materials/schematic.svg deleted file mode 100644 index 4767cfc9f24880a4cac9fbd7fcca45bc4677b85f..0000000000000000000000000000000000000000 --- a/tasks/sky130A/OpenFASOC/cases/current_mirror/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -CMIRRORVREFVSSVBVREFVCOPYVSSVBVBVBVBVBVREFVREFVCOPYVSSVBCMIRRORXAnfet_01v8l=2 w=3m=3XBnfet_01v8l=2 w=3m=3XDUMMYnfet_01v8l=2 w=3m=2 diff --git a/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/case.toml b/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/case.toml index 034419b6b2413adb23b3386c28848c0fc51a748b..bfd829a1a444584a1a7d862cb44896994f851af2 100644 --- a/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/case.toml +++ b/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/case.toml @@ -14,13 +14,6 @@ visibility = "maintainer" format = "gds" sha256 = "e7564dc65ad2636828d3f60f110400e10f41e11ac0a7ebb7e96d823dd509d995" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "c679fe969f7f390639e58bb8d601e109a7d11ff74656a2e5c10117206a49d682" - [task] kind = "netlist_to_gds" hours = 8 diff --git a/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/materials/schematic.svg b/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/materials/schematic.svg deleted file mode 100644 index a75ba6d83cc8e86e8f42e32d085187ccfdfcabba..0000000000000000000000000000000000000000 --- a/tasks/sky130A/OpenFASOC/cases/two_stage_opamp/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -OPAMP_TWO_STAGEGNDGNDDIFFPAIR_BIASDIFFPAIR_BIASGNDVNGNDDIFFPAIR_BIASn_X0_wire0VDDVDDn_wire0n_X1_X0_X0_V1VDDn_wire0VDDn_wire0n_X1_wire0VDDn_wire0n_wire0n_X1_X0_X0_V1VDDn_wire0n_X0_wire0n_wire1n_X1_wire0VDDVDDVOUTn_wire1VDDVDDVDDVDDVDDVDDVDDVDDGNDVDDVDDVOUTn_wire1VDDVDDVDDVDDVDDGNDVDDVDDVDDGNDGNDCS_BIASCS_BIASGNDGNDGNDCS_BIASVOUTVOUTn_X1_wire0VOUTn_X1_wire0VOUTGNDn_X1_wire0VOUTn_X1_wire0VOUTn_X1_wire0VOUTn_X1_wire0GNDGNDGNDGNDVDDVDDVDDVDDGNDVDDGNDDIFFPAIR_BIASVPVNCS_BIASVOUTVPn_X0_wire0n_wire1GNDGNDGNDGNDGNDOPAMP_TWO_STAGEX0nfet_01v8l=1.0 w=6.0m=8X1nfet_01v8l=1.0 w=6.0m=2X2nfet_01v8l=1.0 w=6.0m=8X3nfet_01v8l=1.0 w=6.0m=2X4nfet_01v8l=2.0 w=6.0m=4X5nfet_01v8l=2.0 w=6.0m=4X6pfet_01v8l=1 w=6m=8X7pfet_01v8l=1 w=6m=8X8pfet_01v8l=1 w=6m=12X9pfet_01v8l=1 w=6m=12X10pfet_01v8l=1 w=7m=30X11pfet_01v8l=1 w=7m=3X12pfet_01v8l=1 w=7m=3X13pfet_01v8l=1 w=7m=30X14pfet_01v8l=1 w=7m=3X15pfet_01v8l=1 w=7m=3X16nfet_01v8l=2 w=6m=16X17nfet_01v8l=2 w=6m=32X18cap_mim_m3_1l=12.0 w=12.0X19cap_mim_m3_1l=12.0 w=12.0X20cap_mim_m3_1l=12.0 w=12.0X21cap_mim_m3_1l=12.0 w=12.0X22cap_mim_m3_1l=12.0 w=12.0X23cap_mim_m3_1l=12.0 w=12.0XNDUMMYnfet_01v8l=2 w=6m=14XPDUMMYpfet_01v8l=1 w=6m=10 diff --git a/tasks/sky130A/README.md b/tasks/sky130A/README.md deleted file mode 100644 index 24604b32d577e8846de27bc5515b375f308b11b0..0000000000000000000000000000000000000000 --- a/tasks/sky130A/README.md +++ /dev/null @@ -1,26 +0,0 @@ -# SKY130A Process Scope - -The seven SKY130A tasks use the Ciel installation pinned in [pdk.toml](pdk.toml). -Each case contract defines its own supplies, loads, stimuli and electrical -bounds. The published fixtures use TT models at 27 C. The standard solver input -contains the declared circuit and testbenches; reference GDS and maintainer -schematics are not solver inputs. - -The evaluator runs artifact checks, full Magic DRC, Netgen LVS, geometry checks, -Magic distributed RC extraction and ngspice simulation through the declared -tool image and external process resources. The manifest retains drawn HVI, RPM -and URPM mask hints on GDS import. Its diode extraction adaptation avoids -applying SI-to-micrometre area and perimeter factors twice in the selected -`ngspice()` variants. These adaptations are part of the pinned resource -declaration, not changes to the installed PDK. - -The cases cover block-level behavior under their listed fixtures: current -mirroring, two amplifiers, a comparator, power-on reset, sample-and-hold and an -eight-bit buffered DAC. The two-stage amplifier is evaluated at noise gain 10; -the rail-to-rail amplifier uses its declared load range. The DAC evaluates all -256 static codes and full-scale transitions. These tests do not establish -PVT yield, mismatch, ESD, electromigration or manufacturing signoff. - -Core membership is set only by each case's `in_core` field. All seven cases -remain in the complete corpus; see the root [selection rationale](../../README.md#core-selection-rationale). -Collection-specific licenses and notices accompany the task materials. diff --git a/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/case.toml b/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/case.toml index 7887f0eb5f2987d6a5c02c3f82663afeaecef5d9..d8a1e31749ce4ca65110b30d05d90ca148df2ed5 100644 --- a/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/case.toml +++ b/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/case.toml @@ -11,13 +11,6 @@ visibility = "maintainer" format = "gds" sha256 = "b672f8dbc89b170681fb59d62561b11a1e500b690e788dc0bad00d2e02893a7b" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "4059a9a26dc6665306b7bc6a43e974e86653f885f8e200fa6523013307c38586" - [origin] url = "https://github.com/efabless/sky130_ef_ip__ccomp3v/tree/b051f6131efe5c1169e52a826f893c1a4f65eff0" diff --git a/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/materials/schematic.svg b/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/materials/schematic.svg deleted file mode 100644 index 5f434a2af470632115e41e2658f6a9bf5496ca95..0000000000000000000000000000000000000000 --- a/tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -sky130_ef_ip__ccomp3v_clALVPWRVGNDVNBVPBVPWRXVDDVSSVBPVBNena3v3VDDVBPVBNVSSVINPVOUTVINMDVDDCLOADena3v3DIODEVGNDVNBVPBVPWRVGNDVNBVPBVPWRVDDVDDVSSENAena3v3DVSSDVSSVDDVDDENADVSSDVSSVDDVBPVDDVOUTDVDDDVSSVDDVSSVINPVINMCLOADENAVBNena3v3VOUTDVDDVDDVSSVINPVINMVDDCLOADVBPVBNena3v3DVDDDVSSDVSSccomp3v_clx2comparator_biasx3comparator_core_cloadx1lsbuflv2hv_1x4diode_2x5decap_4 diff --git a/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/case.toml b/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/case.toml index 85a1989db475b77b619162944b47481f43066171..03be5b07b4e36657fb9d609486aeb07959494092 100644 --- a/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/case.toml +++ b/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/case.toml @@ -11,13 +11,6 @@ visibility = "maintainer" format = "gds" sha256 = "5c516a05ccbdfdcaf508963c885356f61b7fb0eaa337d7abec6a69746ec3bada" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "fb9d0c474edb448b2b9266d09c9492f936002fffb9019170f7efc5f76bd8da0e" - [origin] url = "https://github.com/efabless/sky130_ef_ip__opamp/tree/f0eb5cd47112d90fd6d7792ba68e763beacac8e7" diff --git a/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/materials/schematic.svg b/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/materials/schematic.svg deleted file mode 100644 index 0b2d02c3a10491a53eb1292ee6ce4eeaf0e98dac..0000000000000000000000000000000000000000 --- a/tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -sky130_ef_ip__opampvddnet4vddvddoutpdrv1vddoutvssvssndrvvssvssnbiaspbiaspdrv1vddvddpbiaspbiasvddvddpbiasvcompnet1vddinmvcompnet2vddinpndrvvcompvssvssndrvnet2vssvssnet2net2vddvssinmnet1vcomn1vssinppdrv1vcomn1vddvddvddpdrv2net3vddvddnet3net3net1vssvssnbiasvcomn2vssinmnet3vcomn2net1vssinppdrv2vcomn2vddvddoutpdrv2vssinpenavssnbiasnet4enavssvssvssinmvddoutenavssinpinmvssvcomn1nbiasvssvssvddnbiasnbiasopampXM4pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM5pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM9nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM10nfet_g5v0d10v5L=0.5 W=4nf=4 mult=1m=1XR1res_xhigh_po_0p35L=100 mult=1m=1Substrate: B=vssXM20pfet_g5v0d10v5L=0.5 W=200nf=200 mult=1m=1XM22nfet_g5v0d10v5L=0.5 W=120nf=120 mult=1m=1XM24nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM25pfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM26pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM27pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM28pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM29nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM30nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM1nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM2nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM3pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM6pfet_g5v0d10v5L=0.5 W=2nf=2 mult=1m=1XM7nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XM8nfet_03v3_nvtL=0.5 W=1nf=1 mult=1m=1XM11nfet_03v3_nvtL=0.5 W=1nf=1 mult=1m=1XM12pfet_g5v0d10v5L=0.5 W=200nf=200 mult=1m=1XXD1diode_pw2nd_05v5area=0.36 perim=2.4XM13nfet_g5v0d10v5L=0.5 W=1nf=1 mult=1m=1XXD2diode_pw2nd_05v5area=0.36 perim=2.4XXD3diode_pw2nd_05v5area=0.36 perim=2.4 diff --git a/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/case.toml b/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/case.toml index deacd6068662d31bcfa1ef875311832b30fceb5c..a4124ab695cc0779a06de0ce69d8477302046c87 100644 --- a/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/case.toml +++ b/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/case.toml @@ -12,13 +12,6 @@ visibility = "maintainer" format = "gds" sha256 = "b7df0ee8876a782b945760da0c570d1eba72ccda9d3bf5c9a5e99c50e75514a7" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "c3d2c3d9bf5e6fe722096ae4188b26ab1bedc4982531ca2428c4de43b5868952" - [origin] url = "https://github.com/efabless/sky130_ef_ip__rdac3v_8bit/tree/51a71b1af27fbb5e328536fa7c55e97698676015" diff --git a/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/materials/schematic.svg b/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/materials/schematic.svg deleted file mode 100644 index 0e3dcd234e5e957f8689b3b938bed79ce38f9df5..0000000000000000000000000000000000000000 --- a/tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -sky130_ef_ip__rdac3v_8bitvddvssb3b4b3bb4bb5res_inb6b0dum_inb6bb5bb0bb1b1bb2b2boutres_outdum_outvdddvddbit_outbitb_outbit_indvssvdddvddbit_outbitb_outbit_indvssvdddvddbit_outbitb_outbit_indvssvdddvddbit_outbitb_outbit_indvssvdddvddbit_outbitb_outbit_indvssvddenaboutinenavssvdddum_inres_inres_outvssdum_outvdddum_inres_inres_outvssdum_outvddvssb3b4b3bb4bb5res_inb6b0dum_inb6bb5bb0bb1b1bb2b2boutres_outdum_outvddenaboutinenavssvdddum_inres_inres_outvssdum_outvdddum_inres_inres_outvssdum_outvddoutenavssinvsubvdddvddbit_outbitb_outbit_indvssvdddvddbit_outbitb_outbit_indvssvdddvddbit_outbitb_outbit_indvssnet6net5avddavssavddVlowb3ab4ab3bb4bb5ab6ab0aVhighb6bb5bb0bb1ab1bb2ab2bnet6net5net2b3anet4avssavddnet1b7bout_unbufb7advdddvssb4aavddb[7]b7bb7advdddvssavddb[6]b6ab6bb3bdvdddvssavddb[5]b5ab5bdvdddvssavddb4bb[4]b4ab4bdvdddvssavddb[3]b3ab3bb5advdddvssavddb[2]b2ab2bdvdddvssavddb[1]b6ab1ab1bdvdddvssavddb[0]b0ab0bavssb0aavddnet2b7bout_unbufb7aavssavddVlownet4net3net7net8avssavddnet7net8net9net9avssavssavddb6bVhighnet3net10net11avssavddnet10net11net12b5bnet12avssdvssavddoutenaout_unbufdvddavssdvssb0bavddb[7]b[6]b[5]b[4]b[3]b[2]b[1]b[0]Vhighb1aoutenaVlowb1bb2ab2bnet1rdac3v_8bitx1dac_halfx2dac_halfx3passtransx7level_shifterx8level_shifterx9level_shifterx10level_shifterx11level_shifterx12level_shifterx13level_shifterx14level_shifterx15passtransx18dac_column_dummyx5dac_column_dummyx4dac_column_dummyx16dac_column_dummyx6follower_amp diff --git a/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/case.toml b/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/case.toml index 0ff0722f70e7b8257307ad570dc7fe81e8a71dc0..5ec631d693cc2317c24a8033134ed05aa60b6692 100644 --- a/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/case.toml +++ b/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/case.toml @@ -12,13 +12,6 @@ visibility = "maintainer" format = "gds" sha256 = "ecf8e4b7dfd4502f16b77b7994419310ce9eded44b4bc71f84cc2f96791accd4" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "2c2ade1c5379d83dbe491bd6e6b2c1fb7bc758e5174d9b55e46ee0b6d0e6450c" - [origin] url = "https://github.com/efabless/sky130_ef_ip__samplehold/tree/5d5c1e9e172c4afc1a48adc3fe18fbe62642ca39" diff --git a/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/materials/schematic.svg b/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/materials/schematic.svg deleted file mode 100644 index dde1e5bf7deb8bbd73bdc83e27497e7f8d575cf5..0000000000000000000000000000000000000000 --- a/tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -sky130_ef_ip__sampleholdholdvssoutinvddvddoutenavssinvsubvddoutenavssinvsubALVPWRVGNDVNBVPBVPWRXALVPWRVGNDVNBVPBVPWRXinvssnet1ena3vdvddholdvaldvssdvssholdvddvddhold3vdvssholddvdddvssdvssvddvddenaena3vdvssenavssdvdddvssholdvddoutinenavssholdvalvddvssholdvalhold3vnet1dvssvddoutvssvssholdvalena3vdvssvddsampleholdXC1cap_mim_m3_1W=5 L=5m=48XC2cap_mim_m3_2W=5 L=5m=48x1balanced_switchx2follower_ampx3follower_ampx4lsbuflv2hv_1XXD1diode_pw2nd_05v5area=0.36 perim=2.4x5lsbuflv2hv_1XXD2diode_pw2nd_05v5area=0.36 perim=2.4 diff --git a/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/case.toml b/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/case.toml index 01c863c595f4dbb240c34c9391715082d212181b..3cd80f7cec4ca2c65c5469d8bcd8c1262e87f3ca 100644 --- a/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/case.toml +++ b/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/case.toml @@ -15,13 +15,6 @@ visibility = "maintainer" format = "gds" sha256 = "35433f6de882b75252512575d1f917b52a1f462ebf1091c3aa3a4a46ad8af037" -[[assets]] -path = "materials/schematic.svg" -role = "schematic" -visibility = "maintainer" -format = "svg" -sha256 = "abd7761300329fe23cb7f0aadc30ddc594d64158262cccbf8110e9d48456d429" - [task] kind = "netlist_to_gds" hours = 1.5 diff --git a/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/materials/schematic.svg b/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/materials/schematic.svg deleted file mode 100644 index 9571d64c4251e2f4a2846ce82e0923453f664543..0000000000000000000000000000000000000000 --- a/tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/materials/schematic.svg +++ /dev/null @@ -1 +0,0 @@ -sky130_ef_ip__simple_porAVGNDVNBVPBVPWRXAVGNDVNBVPBVPWRXAVGNDVNBVPBVPWRYAVGNDVNBVPBVPWRXvdd3v3vdd3v3net5net6vssnet9vssnet3net3vssnet4vdd3v3net2net2net1vdd3v3vdd3v3net1net1vssvssvssnet7net4vdd3v3net7net7net6vdd3v3net9vdd3v3net6net6vdd3v3vdd3v3net1net8vdd3v3net9net2net8vssvssvdd3v3vdd3v3porb_hvssvdd3v3vssnet10vdd1v8vdd1v8porb_lvssvssnet10vdd1v8net3vdd1v8por_lvssvssnet10vdd3v3vdd3v3vssvssnet7net9net10vdd3v3vdd1v8porb_hporb_lpor_lvssnet5vssvssnet3net2vssvdd3v3net4simple_porXC1cap_mim_m3_1W=30 L=30m=1XC2cap_mim_m3_2W=30 L=30m=1XM1pfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XM2nfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XR1res_xhigh_po_0p69L=500 mult=1m=1Substrate: B=vssXM4pfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XM5nfet_g5v0d10v5L=0.8 W=14nf=7 mult=1m=1XR2res_xhigh_po_0p69L=150 mult=1m=1Substrate: B=vssXM7pfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XM8pfet_g5v0d10v5L=0.8 W=14nf=7 mult=1m=1XM10nfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XM9pfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XM11pfet_g5v0d10v5L=0.8 W=16nf=8 mult=1m=1XM12pfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XM13pfet_g5v0d10v5L=0.8 W=2nf=1 mult=1m=1XR3res_xhigh_po_0p69L=25 mult=2m=2Substrate: B=vssx2buf_8x3buf_8x4inv_8x5schmittbuf_1