id stringlengths 21 64 | in_core bool 2
classes | title stringlengths 8 71 | pdk stringclasses 4
values | core_order int64 1 21 ⌀ | category stringclasses 4
values | summary stringlengths 56 123 | source_url stringlengths 85 202 | status stringclasses 1
value | collection stringclasses 18
values | task_kind stringclasses 1
value | problem stringlengths 3.98k 18k | case_path stringlengths 46 74 | case_sha256 stringlengths 64 64 | pdk_path stringclasses 4
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values | description_path stringlengths 47 75 | netlist_path stringlengths 60 86 | netlist_sha256 stringlengths 64 64 | license_path stringlengths 31 47 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TO_Apr2025.160GHz_LNA | false | TO_Apr2025 160-derived four-stage LNA at 100 MHz | ihp-sg13g2 | null | Amplifiers & RF | Amplifies voltage through four direct-coupled SiGe HBT stages with emitter degeneration and interstage bias clamps. | https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/160GHz_LNA/design_data/qucs-s/160GHz_LNA(MAIN).sch | qualified | TO_Apr2025 | netlist_to_gds | # Four-Stage SiGe HBT Voltage Amplifier Layout Task
## Objective
Create a clean SG13G2 layout for the maintained four-stage direct-coupled
common-emitter voltage amplifier in `LNA160_FOUR_STAGE`. Preserve the circuit
connectivity, HBT multiplicities, passive dimensions and five external ports.
The submitted top cell ... | tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml | a59b36efe855ba0999cadb33ebaca83a6a47492a1ac6f77b2e4f243529001cb1 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/problem.md | tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/circuit.cdl | 26b815aa103d0d81b54e21c661b28860304a5d23be900d17192cbb92100be3c6 | tasks/ihp-sg13g2/TO_Apr2025/LICENSE |
TO_Apr2025.40_GHZ_LOW_NOISE_TIA | false | TO_Apr2025 40 GHz low-noise single-ended TIA | ihp-sg13g2 | null | Amplifiers & RF | Converts input current to voltage through three SiGe HBT stages with resistive feedback and emitter degeneration. | https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/40_GHZ_LOW_NOISE_TIA/design_data/qucs-s/40_GHz_Low_Noise_TIA.sch | qualified | TO_Apr2025 | netlist_to_gds | # Three-Stage SiGe HBT Transimpedance Amplifier Layout Task
## Objective
Create a clean SG13G2 layout for the maintained three-stage, single-ended
transimpedance amplifier in `FDM_QNC_00_LN_TIA`. Preserve the circuit
connectivity, device multiplicities, passive dimensions and six external
ports. The submitted top cel... | tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml | e547c6bcca5b539eef4e77bde2ea96179838781a6f6732af68ab180ae8dc6778 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/problem.md | tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/circuit.cdl | 17a094c09698acfbe6a25a50d3a0292ebb82fd82b7e21269442bcdd4fa3c0d45 | tasks/ihp-sg13g2/TO_Apr2025/LICENSE |
TO_Apr2025.97_GHZ_LINEAR_TIA | false | TO_Apr2025 97-derived multi-stage linear TIA | ihp-sg13g2 | null | Amplifiers & RF | Converts input current to voltage using three SiGe HBT stages and active emitter-follower feedback. | https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/97_GHZ_LINEAR_TIA/design_data/qucs-s/97_GHZ_LINEAR_TIA.sch | qualified | TO_Apr2025 | netlist_to_gds | # Linear SiGe HBT Transimpedance Amplifier Layout Task
## Objective
Create a clean SG13G2 layout for the maintained multi-stage linear
transimpedance amplifier in `FMD_QNC_01_LIN_TIA`. Preserve the circuit
connectivity, HBT multiplicities, passive dimensions and six external ports.
The submitted top cell must be `FMD... | tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml | adcf589b020b333b37c10bd6372efc696d953ca7bfcdba5b898d3ba7ca9efd60 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/problem.md | tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/circuit.cdl | 150ab19522eecccf2889ed62c07b14e15e29e97a75ce12563fcd95d846be9112 | tasks/ihp-sg13g2/TO_Apr2025/LICENSE |
TO_Apr2025.DC_to_130_GHz_TIA.design_1 | false | Two-stage SiGe HBT TIA with nominal AC/DC requirements | ihp-sg13g2 | null | Amplifiers & RF | Converts input current to voltage through two direct-coupled SiGe HBT stages with first-stage resistive feedback. | https://github.com/IHP-GmbH/TO_Apr2025/blob/63e203a0eccfb6028a1a0a8364553e4e979b55b3/DC_to_130_GHz_TIA/design_1/design_data/qucs-s/DC_to_130_GHz_TIA.sch | qualified | TO_Apr2025 | netlist_to_gds | # Two-Stage SiGe HBT Transimpedance Amplifier Layout Task
## Objective
Create a clean SG13G2 layout for the maintained two-stage transimpedance
amplifier in `FMD_QNC_03a_TIA_1`. Preserve the circuit connectivity, HBT
multiplicities, passive dimensions and five external ports. The submitted top
cell must be `FMD_QNC_0... | tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml | 4f2831cdc809a1b2b95d86ec6a53a35ae038a57edec95adadcde6cb33b4c6371 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/problem.md | tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/circuit.cdl | 41054606cd4c4845149df6c9a38a7d38d45ae4ba22afb5ff588d33051aaf06f3 | tasks/ihp-sg13g2/TO_Apr2025/LICENSE |
freepdk45.CircuitOpt.fd_ota | false | Fully Differential Telescopic OTA | freepdk45 | null | Amplifiers & RF | Amplifies differential inputs with a telescopic cascode stage and transistor-level common-mode feedback. | https://github.com/751K/circuit-optimization-lab/blob/a33c87e1db3223cf964a43c3a08da67e12b64723/examples/freepdk45_fd_ota.json | qualified | CircuitOpt | netlist_to_gds | # FreePDK45 Fully Differential Telescopic OTA Layout Task
## Objective
Implement the fully differential OTA from the supplied 16-transistor netlist, with a telescopic common-source/common-gate signal path and transistor-based continuous-time output common-mode feedback (CMFB). Evaluation uses extracted connectivity a... | tasks/freepdk45/CircuitOpt/cases/fd_ota/case.toml | 06639126367b61de0bb03725151b194cde17f5db8c3f0565791da6b6e717cf57 | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/CircuitOpt/cases/fd_ota/problem.md | tasks/freepdk45/CircuitOpt/cases/fd_ota/materials/circuit.spice | 4d3b70dc4275dec002434649f56fba42859326b377859bcc74dedaaab983502e | tasks/freepdk45/CircuitOpt/LICENSE |
freepdk45.OpenRAM.cell_6t | true | Six-Transistor SRAM Bitcell | freepdk45 | 10 | Logic & memory | Stores one bit using cross-coupled inverters and wordline-controlled access transistors. | https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/cell_6t.sp | qualified | OpenRAM | netlist_to_gds | # Six-Transistor SRAM Bitcell Layout Task
## Objective
Implement the supplied six-transistor SRAM bitcell, retaining cross-coupled storage, complementary bitlines and the shared wordline. Preserve authoritative netlist models, W/L, interface and connections; top cell is `cell_6t`.
## Inputs and Interface
Ordered SP... | tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml | 474266fbeec90e97c72b5016a2d8eaddbf86dba9f4782e1b45acf8dee0514422 | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md | tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice | 18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488 | tasks/freepdk45/OpenRAM/LICENSE |
freepdk45.OpenRAM.sense_amp | false | Clocked SRAM Sense Amplifier | freepdk45 | null | Logic & memory | Resolves a small bitline voltage difference into a clocked digital decision. | https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/sense_amp.sp | qualified | OpenRAM | netlist_to_gds | # Clocked SRAM Sense Amplifier Layout Task
## Objective
Implement the supplied clocked regenerative sense amplifier. Dout is low when sampled BL is below BR, and high for the opposite differential. Preserve authoritative netlist models, W/L, interface and connections; top cell is `sense_amp`.
## Inputs and Interface... | tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml | 75460f703a78a85e1530029ed21d4e0079600ecd76dd1b1ffc54305c66d63c8a | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md | tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice | f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f | tasks/freepdk45/OpenRAM/LICENSE |
freepdk45.OpenRAM.write_driver | true | Complementary SRAM Write Driver | freepdk45 | 12 | Logic & memory | Drives complementary bitlines during a write and releases them when disabled. | https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/write_driver.sp | qualified | OpenRAM | netlist_to_gds | # Complementary SRAM Write Driver Layout Task
## Objective
Implement the supplied complementary tri-state write driver: with WEN=1, BL=DIN and BR=NOT DIN; with WEN=0, both outputs are disabled. Preserve authoritative netlist models, W/L, interface and connections; top cell is `write_driver`.
## Inputs and Interface
... | tasks/freepdk45/OpenRAM/cases/write_driver/case.toml | 13fc4b2901b988014c77ee7164cc5cb5ec0d45e1191c47bab79551ff23836372 | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/OpenRAM/cases/write_driver/problem.md | tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice | 40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4 | tasks/freepdk45/OpenRAM/LICENSE |
freepdk45.nangate45-pdk.AOI21_X1 | false | AND-OR-Invert Gate | freepdk45 | null | Logic & memory | Implements AND-OR-invert logic in a fixed-height standard cell. | https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/AOI21_X1.spi | qualified | nangate45-pdk | netlist_to_gds | # AND-OR-Invert Gate Layout Task
## Objective
Implement ZN = NOT (A OR (B1 AND B2)) with the supplied VTL transistors, preserving authoritative netlist models, W/L, interface and connections; top cell is `AOI21_X1`.
## Inputs and Interface
Ordered SPICE ports: `A B1 B2 ZN VDD VSS`. Names are case-insensitive, but d... | tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml | c732832e4cfbe115e6a089febf6ff5571edf662e0c0a8972250d3a939b58d805 | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md | tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice | 07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e | tasks/freepdk45/nangate45-pdk/LICENSE |
freepdk45.nangate45-pdk.INV_X1 | false | Inverter | freepdk45 | null | Logic & memory | Inverts a digital input in a fixed-height standard cell. | https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/INV_X1.spi | qualified | nangate45-pdk | netlist_to_gds | # FreePDK45 INV_X1 Layout Task
## Objective
Implement the fixed-size transistor inverter `INV_X1` in FreePDK45. Preserve ordered ports A ZN VDD VSS, four-terminal connections, VTL models and fixed sizes, implementing A=0→ZN=1, A=1→ZN=0. Solve budget: **3 hours**.
## Inputs and Interface
Declared inputs are this des... | tasks/freepdk45/nangate45-pdk/cases/INV_X1/case.toml | b3577fc9b8b1fa9871ff3ab0ca398700a2ee8de9b7ff5779b2127322dc2a75b4 | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/nangate45-pdk/cases/INV_X1/problem.md | tasks/freepdk45/nangate45-pdk/cases/INV_X1/materials/circuit.spice | 18da14e782ffbc06bb5abf382f3f3b66cb4dfdb0e71d706668c1149819d22ca1 | tasks/freepdk45/nangate45-pdk/LICENSE |
freepdk45.nangate45-pdk.NAND2_X1 | true | Two-Input NAND | freepdk45 | 4 | Logic & memory | Implements two-input NAND logic in a fixed-height standard cell. | https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/NAND2_X1.spi | qualified | nangate45-pdk | netlist_to_gds | # Two-Input NAND Layout Task
## Objective
Implement ZN = NOT (A1 AND A2) with the supplied VTL transistors, preserving authoritative netlist models, W/L, interface and connections; top cell is `NAND2_X1`.
## Inputs and Interface
Ordered SPICE ports: `A1 A2 ZN VDD VSS`. Names are case-insensitive, but different name... | tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml | e393d3cc9a45adaedac49fd718b4ed966b11ce47cb098f669b9cac87edd7e45f | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md | tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice | 1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0 | tasks/freepdk45/nangate45-pdk/LICENSE |
freepdk45.nangate45-pdk.NOR2_X1 | false | Two-Input NOR | freepdk45 | null | Logic & memory | Implements two-input NOR logic in a fixed-height standard cell. | https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/NOR2_X1.spi | qualified | nangate45-pdk | netlist_to_gds | # FreePDK45 NOR2_X1 Layout Task
## Objective
Implement the fixed-size two-input NOR gate `NOR2_X1` in FreePDK45, preserving ports A1 A2 ZN VDD VSS, four-terminal connections, VTL models and fixed sizes, implementing 00→1, 01→0, 11→0, 10→0. Solve budget: **3 hours**.
## Inputs and Interface
Declared inputs are this ... | tasks/freepdk45/nangate45-pdk/cases/NOR2_X1/case.toml | 01537b81e1e560100552a4243a835cf9d0ad7f6030b374b4b88cf4920db2a60a | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/nangate45-pdk/cases/NOR2_X1/problem.md | tasks/freepdk45/nangate45-pdk/cases/NOR2_X1/materials/circuit.spice | 6521472bc3714e83d5fcf0ffa0e462c2439d863f31a7b20e6141056f2232c1cd | tasks/freepdk45/nangate45-pdk/LICENSE |
freepdk45.nangate45-pdk.XOR2_X1 | false | Two-Input XOR | freepdk45 | null | Logic & memory | Implements two-input XOR logic in a fixed-height standard cell. | https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/XOR2_X1.spi | qualified | nangate45-pdk | netlist_to_gds | # FreePDK45 XOR2_X1 Layout Task
## Objective
Implement the fixed-size two-input XOR gate `XOR2_X1` in FreePDK45, preserving ports A B Z VDD VSS, four-terminal connections, VTL models and fixed sizes, implementing 00→0, 01→1, 11→0, 10→1. Solve budget: **3 hours**.
## Inputs and Interface
Declared inputs are this des... | tasks/freepdk45/nangate45-pdk/cases/XOR2_X1/case.toml | c532b4de894581dda9128dc2e06115b6020d0440c7cf44445f6338a7a0b9f40e | tasks/freepdk45/pdk.toml | 7712cbf3df33d0877c035b3afa6283415b36da64ad4551d49b859d9601dffea3 | tasks/freepdk45/nangate45-pdk/cases/XOR2_X1/problem.md | tasks/freepdk45/nangate45-pdk/cases/XOR2_X1/materials/circuit.spice | d887f609291cad55b09d6ed77c06e2a327923084dfd4ff356abf53ece7a18f37 | tasks/freepdk45/nangate45-pdk/LICENSE |
gf180mcuD.2AMLogic-sar-adc.track_switch | false | Dummy-Compensated Track Switch | gf180mcuD | null | Mixed-signal | Tracks an analog input through a transmission gate with dummy compensation. | https://github.com/2AMLogic/gf180-sar-adc/tree/c32c8da53e52fbb7d75f6f628b8cc9f6f45a13fc/design/adc-top/adc_top.spice | qualified | 2AMLogic-sar-adc | netlist_to_gds | # Dummy-Compensated Track Switch Layout Task
## Objective
Implement `adc_tgate_dum` in GF180MCU D, preserving circuit, sizes and ordered interface. Measure tracking, settling and hold feedthrough for complementary-clock 0.5/2.5 V steps with 1 pF output capacitance.
## Inputs and Interface
Inputs are this descriptio... | tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml | 8a25dfca0a335386d528498a7612a648f9313f6b147126a97db50b5b2a85e52e | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md | tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice | 24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd | tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE |
gf180mcuD.Chipathon2023_ADC.comparator | false | Dynamic Comparator | gf180mcuD | null | Mixed-signal | Compares two input voltages using a clocked regenerative decision. | https://github.com/ishi-kai/Chipathon2023_ADC/tree/3dce439b2125a9d628e43be40c65cf8fce5d795c/gitefu/comp_20240331/comp_20240331.sch | qualified | Chipathon2023_ADC | netlist_to_gds | # Dynamic Comparator Layout Task
## Objective
Implement `comp_20240331` in GF180MCU D, preserving circuit, sizes and ordered interface. Complete clocked decisions in both directions with input common mode 1.65 V, differential input ±20 mV, clock 50 MHz and 50 fF per output.
## Inputs and Interface
Inputs are this d... | tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml | b73dc7a3bb684c4a3526b0d63a82730745d9a0a83621f236127df7e9b7209735 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/problem.md | tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice | 0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d | tasks/gf180mcuD/Chipathon2023_ADC/LICENSE |
gf180mcuD.Jianxun-OTA.ota_5t | true | Five-Transistor OTA with Bias and Dummies | gf180mcuD | 8 | Amplifiers & RF | Amplifies a differential input with a compact five-transistor OTA core and bias network. | https://github.com/Jianxun/iic-osic-tools-project-template/tree/178a401d847ce7a602d0ce70a1ba90a15b5f9536/designs/libs/core_analog/ota_5t/ota_5t.spice | qualified | Jianxun-OTA | netlist_to_gds | # Five-Transistor OTA with Bias and Dummies Layout Task
## Objective
Implement `ota_5t` in GF180MCU D, preserving circuit, sizes and ordered interface. Measure small-signal differential gain, common-mode rejection and unity-gain frequency at common mode 1.65 V, bias 10 uA and load 1 pF.
## Inputs and Interface
Inpu... | tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml | fb5a4100d5e222b9226307d83fab4861e226e4f2fa344c5ec5e327b1f9e29f2e | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md | tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/materials/circuit.spice | fe6966f64eb3bc72880adca79dac070e0c0e2ea05cdc46c83f49616611d36fac | tasks/gf180mcuD/Jianxun-OTA/LICENSE |
gf180mcuD.analog-db.amp_004_folded_cascode | false | Externally Biased PMOS-Input Folded-Cascode OTA | gf180mcuD | null | Amplifiers & RF | Amplifies differential inputs with an externally biased PMOS folded-cascode stage across three supply voltages. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_004_folded_cascode | qualified | analog-db | netlist_to_gds | # Externally Biased PMOS-Input Folded-Cascode OTA Layout Task
## Objective
Implement the fixed `amp_004_folded_cascode` circuit in GF180MCU D and submit self-contained GDS.
Fourteen MOS entries (17 instances after multiplicity expansion) form a PMOS-input folded-cascode OTA with a bias mirror and cascode branches. Th... | tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml | 127098bead279ffe44b1b11c6ba80a9a5b8a9f3c9cd224526743ab77a8af1af5 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/problem.md | tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/materials/circuit.spice | 0e1b5d28435e858dd108e6213f90505a7a33e067d9e9c728acbd5f61087912df | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.amp_017_tan_clia | false | Tan CLIA Three-Stage Amplifier | gf180mcuD | null | Amplifiers & RF | Amplifies differential signals through three stages with current inversion and physical R/C compensation. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_017_tan_clia | qualified | analog-db | netlist_to_gds | # Tan CLIA Three-Stage Amplifier Layout Task
## Objective
Implement `amp_017_tan_clia` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded NMOS branches drive voutn/net050. XM70 and XM71/XM72 form the current-inversion path through net3/net5; XM61 and the DM_1-controlled XM73 bias this p... | tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml | c1cf99ceacaef68e318769178b7e876d601faa3d1f6c1ebf5dabe1727d40a01d | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/problem.md | tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/materials/circuit.cdl | 59a4d962ade70da8bbdc21dffc81adf077c84baa2057b100deaed0c5f34e7dc2 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.amp_018_telescopic_cascode | false | Tail-Referenced Telescopic Cascode Amplifier | gf180mcuD | null | Amplifiers & RF | Amplifies differential inputs with an NMOS telescopic cascode and tail-referenced bias across three capacitive loads. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_018_telescopic_cascode | qualified | analog-db | netlist_to_gds | # Tail-Referenced Telescopic Cascode Amplifier Layout Task
## Objective
Implement `amp_018_telescopic_cascode` in gf180mcuD and submit self-contained GDS. Ten MOS devices form an NMOS-input telescopic cascode amplifier. Fixed upstream W/L/m are retained, including the single finger of XM5. The two ideal internal sour... | tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml | 0a181e246190eef423260dd9fc0f315c9061f3475c0e43b380622e52294eeae2 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/problem.md | tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/materials/circuit.spice | 6df66ed141e0b188eafe3f66c153bcd81d2b4186c9eb20f9f821bbe4f8d006fa | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.amp_019_ti_ldo_error | false | Externally Biased TI-Architecture Error Amplifier | gf180mcuD | null | Amplifiers & RF | Amplifies a differential error signal using external bias, level shifting and series Miller compensation. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_019_ti_ldo_error | qualified | analog-db | netlist_to_gds | # Externally Biased TI-Architecture Error Amplifier Layout Task
## Objective
Implement `amp_019_ti_ldo_error` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. All twelve MOS remain, including the externally driven NMOS reference diode, four sinks, NMOS ... | tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml | 546b4ce92ec1367784901b983911dce253e459c1516301fad9d5d3d35380beec | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/problem.md | tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/materials/circuit.cdl | 3af8b547c72e7e34d0f919ace84d1eafff32f9c4b7f1b6a0e60ca6d45bab8fcc | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.amp_032_ti_ldo_error_selfbias | false | Self-Biased LDO Error Amplifier | gf180mcuD | null | Amplifiers & RF | Amplifies an error signal with a self-biased two-stage core, level-shifted mirror and Miller compensation. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_032_ti_ldo_error_selfbias | qualified | analog-db | netlist_to_gds | # Self-Biased LDO Error Amplifier Layout Task
## Objective
Implement `amp_032_ti_ldo_error_selfbias` as a GF180MCU D layout. Eleven MOS devices form the fixed upstream two-stage amplifier, with a level-shifted PMOS mirror, its 500 kohm gate-rail tie, diode-connected self-bias and series Miller compensation. The fixed... | tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml | 6bc98a4eb833c2b6713b5e77dff6beb58cc62174baecd796fa1ac8a21917817c | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/problem.md | tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/materials/circuit.cdl | 9e9cb685378e09c43bf827a69c0189e83fb9ef47b6d96655c466e1bfa411b7d1 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.amp_033_ti_ldo_ref_selfbias | false | Self-Biased LDO Reference Amplifier | gf180mcuD | null | Amplifiers & RF | Buffers a reference through a self-biased two-stage Miller amplifier under external unity feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_033_ti_ldo_ref_selfbias | qualified | analog-db | netlist_to_gds | # Self-Biased LDO Reference Amplifier Layout Task
## Objective
Implement `amp_033_ti_ldo_ref_selfbias` as a GF180MCU D layout. Nine MOS devices form the fixed upstream two-stage Miller amplifier, with a matched PMOS mirror and diode-connected self-bias. External unity feedback tests the reference-buffer function; no ... | tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml | 018ec337ae7e04fe241178759679343677ed169030a2fce703355febc6b98746 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/problem.md | tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/materials/circuit.cdl | 9b965341e7687a517833fa3ffa030c708a3bcb2622a922f5edb74e959bbff646 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.cmfb_003_5t_nmos_input | false | Segmented-Resistor NMOS Common-Mode Controller | gf180mcuD | null | Amplifiers & RF | Controls common-mode voltage using an NMOS-input core and segmented resistors. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_003_5t_nmos_input | qualified | analog-db | netlist_to_gds | # Segmented-Resistor NMOS Common-Mode Controller Layout Task
## Objective
Implement `cmfb_003_5t_nmos_input` in gf180mcuD and submit self-contained GDS. Seven MOS devices form an NMOS-input common-mode error amplifier and self-bias network. Each ideal 5 Mohm sense arm is implemented as twenty series GF180 ppolyf_u_1k... | tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml | ef4b929d67b8e4db22beac7403bd094a719cab3a194b49d2aa3cc152d2a45dc6 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/problem.md | tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/materials/circuit.spice | ed1848c64b323f669f0af718f61dce96c389bfff34576f91940950242a100c5a | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.cmp_001_hyst_diffpair | false | Resistive-Feedback Hysteretic Comparator | gf180mcuD | null | Mixed-signal | Produces distinct rising and falling switching thresholds through resistive hysteresis. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_001_hyst_diffpair | qualified | analog-db | netlist_to_gds | # Resistive-Feedback Hysteretic Comparator Layout Task
## Objective
Implement the fixed `cmp_001_hyst_diffpair` circuit in GF180MCU D and submit self-contained GDS.
A differential input stage, resistive positive feedback and three output inverters form a hysteretic comparator. Twelve MOS entries expand to 28 physical... | tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml | 6e05fe34ebccaa8fa4409f48253d18a5a1931774da70ad6ee270b67fa88ebf6f | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/problem.md | tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/materials/circuit.spice | cdca67d855bfc4b89e55bcd53d1cab7a1c46a2fd78e97f3d1cc7b574c4f1dadd | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.cmp_002_strongarm | true | StrongARM Dynamic Comparator | gf180mcuD | 18 | Mixed-signal | Makes clocked differential decisions with a StrongARM regenerative latch. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmp_002_strongarm | qualified | analog-db | netlist_to_gds | # StrongARM Dynamic Comparator Layout Task
## Objective
Implement `cmp_002_strongarm` as a GF180MCU D layout. Fifteen upstream MOS instances implement the clocked StrongARM latch: differential input pair, clocked tail, cross-coupled regenerative devices, four precharge devices and two output inverters. The input pair... | tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml | 01a6c650c18221e2294404a753e56d9f6c2919fb6f21bed091f3150859ea7822 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md | tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/materials/circuit.cdl | 5b80e3a40ab19415481d51b8e6b4e4bcf45c4517ccc5071aa1b342038c94e14c | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.dp_001_resistive_load | false | Resistively Loaded Differential Pair | gf180mcuD | null | Amplifiers & RF | Produces differential gain with resistive loads and a fixed input pair. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/dp_001_resistive_load | qualified | analog-db | netlist_to_gds | # Resistively Loaded Differential Pair Layout Task
## Objective
Implement the fixed `dp_001_resistive_load` circuit in GF180MCU D and submit self-contained GDS.
Four NMOS devices form a differential input pair and tail-current mirror. Two physical GF180 ppolyf_u_1k loads each have width 2 um and length 44 um (22 squa... | tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml | 3ce00eb6370d491680113d98274df3b7891b275be9467c852bda4979a07551d6 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/problem.md | tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/materials/circuit.spice | 15f8f3ea58d21ec06d4a72fb79abe6f7be80102d06ae9819a892ac0ab96e2c71 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.gs_001_cascode_cs | false | Self-Biased Cascode Common-Source Gain Stage | gf180mcuD | null | Amplifiers & RF | Provides voltage gain through a self-biased cascode common-source stage. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/gs_001_cascode_cs | qualified | analog-db | netlist_to_gds | # Self-Biased Cascode Common-Source Gain Stage Layout Task
## Objective
Implement the fixed `gs_001_cascode_cs` circuit in GF180MCU D and submit self-contained GDS.
Nine MOS devices form a cascode common-source stage with PMOS and NMOS bias ladders. An external 20 uA sink biases the PMOS ladder. Total widths, lengths... | tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml | 691cc95d831fe61e808b30174b0c03e2695fdf2cb5307b0473598fa4b2ec3653 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/problem.md | tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/materials/circuit.spice | 59d815c21e17878429aab496b999cfcde2168c09f125d99e8b91644f5fd70299 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.ldo_002_analoggym_folded_cascode | false | Folded-Cascode LDO | gf180mcuD | null | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_002_analoggym_folded_cascode | qualified | analog-db | netlist_to_gds | # Folded-Cascode LDO Layout Task
## Objective
Implement `ldo_002_analoggym_folded_cascode` as a GDS layout preserving the complete declared circuit. Nine-MOS folded-cascode error amplifier and a PMOS pass array, with direct output feedback, series RZ/CC and the physical minimum-load bleed. The fixed GF180 6 V binding... | tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml | 363faded868a48651c7bdac3c8fa039c0db7bc2e72b4bbbc6cd7cc3244bdc521 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/problem.md | tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/materials/circuit.cdl | 7463ac0a1cc09ec1f522693a4e4e03b348a693a698cdfb71cade504ca6ff4681 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.ldo_003_analoggym_simple | false | Simple Unity-Feedback LDO | gf180mcuD | null | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_003_analoggym_simple | qualified | analog-db | netlist_to_gds | # Simple Unity-Feedback LDO Layout Task
## Objective
Implement `ldo_003_analoggym_simple` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. A five-transistor NMOS-input error amplifier drives the PMOS pass device, with direct output feedback, the complet... | tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml | 295ee04a81ff77093ce060db0e58f2bc8cff011ea962b9597621f441d3a2a871 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/problem.md | tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/materials/circuit.cdl | b3ed893165850ba59c078460a0c50ca3d808d92aeef5f73d166600b54f2cc176 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.ldo_004_basic_pmos | false | Externally Biased 1.8 V PMOS Regulator Core | gf180mcuD | null | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_004_basic_pmos | qualified | analog-db | netlist_to_gds | # Externally Biased 1.8 V PMOS Regulator Core Layout Task
## Objective
Implement the fixed `ldo_004_basic_pmos` regulator core in GF180MCU D and submit
self-contained GDS. The circuit contains an error amplifier, a PMOS pass array
and a physical feedback divider. Reference and tail-current generation are
external to ... | tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml | 010c12c0a95d4f42c618bcdf380691430f61fe4e0f6716ef46cfb44f35acff71 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md | tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/materials/circuit.spice | c6f1d28094341b66381edd0a83bc3d284c7ba5e2b5deb1e6996dba84a9daec35 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.ldo_005_buffered_ref | false | Buffered-Reference LDO | gf180mcuD | null | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_005_buffered_ref | qualified | analog-db | netlist_to_gds | # Buffered-Reference LDO Layout Task
## Objective
Implement `ldo_005_buffered_ref` as a GF180MCU D layout. The fixed upstream GF180 6 V circuit combines its self-biased reference amplifier, gain-two reference divider, RC low-pass filter, self-biased error amplifier, PMOS pass device, bleeder and on-die output capacit... | tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml | 83fb958ff26249fb0749191d7e80c205ecef2d7249141f44744d870ea11bbdc8 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/problem.md | tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/materials/circuit.cdl | 1e1c14a91036bf5d0069bcc2a22f99e65c5f6a0a963377cc1e0ff2120293c9ff | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.ldo_006_stub | false | Divider-Biased NMOS Source Follower | gf180mcuD | null | Amplifiers & RF | Tracks an input bias with a divider-biased NMOS source follower. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_006_stub | qualified | analog-db | netlist_to_gds | # Divider-Biased NMOS Source Follower Layout Task
## Objective
A single fixed 50/0.5 um nfet_03v3 (m=1) forms a source follower. Its drain connects to vdd, source to vout, body to vss, and gate to the midpoint of the internal 100 kohm/100 kohm supply divider. Each resistor uses two native ppolyf_u_1k segments, totali... | tasks/gf180mcuD/analog-db/cases/ldo_006_stub/case.toml | 6dfe6ea15b3bef1aa2da004cbcbb5467ff70eb8cecf9bd7e649f454ca2ce6951 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/ldo_006_stub/problem.md | tasks/gf180mcuD/analog-db/cases/ldo_006_stub/materials/circuit.cdl | b2cbf5b0cf0497af8ad62bded31556d61ed2d15ff665966e7e8e5e7772a58aa3 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.ldo_007_pmos | true | PMOS LDO with Feedforward Compensation | gf180mcuD | 11 | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_007_pmos | qualified | analog-db | netlist_to_gds | # PMOS LDO with Feedforward Compensation Layout Task
## Objective
Implement `ldo_007_pmos` as a GDS layout preserving the complete declared circuit. Five-transistor error amplifier, NMOS bias diode and PMOS pass array with complete resistive feedback divider, feedforward CFF across the upper divider, and series RZ/CC... | tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/case.toml | f8183b7ebdff3d4e49cd064207a1fc530c2df4a6d300c1f955ed6625abdf78e5 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md | tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/materials/circuit.cdl | 4b3f01ca7600933022e7730cc7cfb614b7abcc2808f7ef777b0019b27514382a | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.sup_001_vcm_detector | false | Passive Resistive Common-Mode Averager | gf180mcuD | null | Amplifiers & RF | Averages two input voltages through a passive resistive common-mode network. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sup_001_vcm_detector | qualified | analog-db | netlist_to_gds | # Passive Resistive Common-Mode Averager Layout Task
## Objective
Two matched 1 Mohm resistors join vinp to vcm_out and vcm_out to vinn. This is a passive average detector, without a buffer, amplifier or CMFB controller. The fixed IHP binding contains ideal R cards, not process-specific resistor models; the maintaine... | tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/case.toml | 4c8b37d6655c3e4068dc84c2b05892c57444e2a832c42036bd425af18dec6efb | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/problem.md | tasks/gf180mcuD/analog-db/cases/sup_001_vcm_detector/materials/circuit.cdl | c0cdf0e12dbdbfc2e7d1fd9fe3c061a29f745efd8656e1a85e100036489db523 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.tsn_001_ptat_2t | false | Two-NMOS Temperature-Response Core | gf180mcuD | null | Power & references | Produces a temperature-dependent response whose slope and curvature are measured across the declared range. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_001_ptat_2t | qualified | analog-db | netlist_to_gds | # Two-NMOS Temperature-Response Core Layout Task
## Objective
The fixed GF180 binding contains eight parallel 8/0.28 um upper NMOS with gates tied to their sources, and eight parallel 4/1 um diode-connected lower NMOS. Both groups have grounded bodies. This is a two-group temperature-response core; neither its PTAT n... | tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/case.toml | 26b788b5b9b2bce872fea280a992ce9f913d68eb47e198b8ed9753744d5898c7 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/problem.md | tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/materials/circuit.cdl | 534d2b4bdfe4354bd80c0db81495c5d60a73fe20912ba79f3ccb749fadaf7efc | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.tsn_002_ptat_classic | true | Self-Starting Isolated-Body PTAT Core | gf180mcuD | 14 | Power & references | Produces a temperature-dependent response whose slope and curvature are measured across the declared range. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_002_ptat_classic | qualified | analog-db | netlist_to_gds | # Self-Starting Isolated-Body PTAT Core Layout Task
## Objective
Implement `tsn_002_ptat_classic` in GF180MCU D and submit self-contained GDS.
The resistor-degenerated four-MOS source core has a positive temperature slope;
candidate slope is measured and source-paired without a positive-slope acceptance bound.
A main... | tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/case.toml | a82b39ccd59c40c43fffc5e3946d5c1d629c433cd255be43848a233f8e4580d1 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md | tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/materials/circuit.cdl | 1efc6b4da14d95c12ff19bd3a1e8a10a8c986a97befff37dadb44ce6f10ef5ea | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.analog-db.tsn_003_ptat_4t_xcoupled | false | Four-Transistor Positive-Temperature-Slope Core | gf180mcuD | null | Power & references | Produces a temperature-dependent response whose slope and curvature are measured across the declared range. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/tsn_003_ptat_4t_xcoupled | qualified | analog-db | netlist_to_gds | # Four-Transistor Positive-Temperature-Slope Core Layout Task
## Objective
Implement the fixed `tsn_003_ptat_4t_xcoupled` circuit in GF180MCU D and submit self-contained GDS.
Two NMOS and two PMOS devices form a resistorless temperature-dependent voltage core with cross-coupled bias connections. The fixed GF180 sizes... | tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/case.toml | 175a6c01e91bacbb1d6fd3929b31f2a88faf5ccd992bccee59a088117d4fe51b | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/problem.md | tasks/gf180mcuD/analog-db/cases/tsn_003_ptat_4t_xcoupled/materials/circuit.spice | f24cecfbc159437e3d72e808142dda1333ac70ddd16a0a956a9caee218b37c09 | tasks/gf180mcuD/analog-db/LICENSE |
gf180mcuD.gf-r2r-dac.r2r | true | Eight-Bit R-2R DAC Core | gf180mcuD | 16 | Mixed-signal | Converts an eight-bit digital code into an analog voltage through an R-2R network. | https://github.com/mattvenn/gf-r2r-dac/tree/1c5c8ddec54fc4e70ce03a19510d4d7461b919e9/xschem/simulation/r2r.spice | qualified | gf-r2r-dac | netlist_to_gds | # Eight-Bit R-2R DAC Core Layout Task
## Objective
Implement `r2r` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Eight-bit passive voltage conversion with ideal external bit drivers and a 1 pF output load; ten transient codes plus the complete static 256-code tr... | tasks/gf180mcuD/gf-r2r-dac/cases/r2r/case.toml | f52ddfb3f1a9d61b017ede2ac1f193d49e27c940359b873c818dc480b8737ce1 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md | tasks/gf180mcuD/gf-r2r-dac/cases/r2r/materials/circuit.spice | 64ee316b7953b9444c61d2ac5639e4ac4b32ddd83323e1cc5b190e4865e97957 | tasks/gf180mcuD/gf-r2r-dac/LICENSE |
gf180mcuD.tt_tnt_gf_vco.vco | true | Quadrature Voltage-Controlled Oscillator | gf180mcuD | 9 | Mixed-signal | Generates quadrature oscillation with a voltage-controlled tuning response. | https://github.com/smunaut/tt_tnt_gf_vco/tree/897b3ec12ed693161fb56f4205d1b19dc5e56c1a/xschem/vco.sch | qualified | tt_tnt_gf_vco | netlist_to_gds | # Quadrature Voltage-Controlled Oscillator Layout Task
## Objective
Implement `vco` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Four-phase oscillation, quadrature and frequency tuning at control voltages 1.65 V and 2.10 V, checked across typical-model temperat... | tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/case.toml | 3bd1d35ed20739279814b779384a8d7f29d267faa092a3101f0979a93c5a719b | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md | tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/materials/circuit.spice | 021943933973e205dfb533131232917d18d1ffe8b24bedc5e45534992e2a1615 | tasks/gf180mcuD/tt_tnt_gf_vco/LICENSE |
gf180mcuD.voidwalkers-scandff.scan_dff | true | Scan D Flip-Flop with Active-Low Reset | gf180mcuD | 17 | Logic & memory | Stores a clocked bit with scan selection and asynchronous active-low reset. | https://github.com/radityankn/voidwalkers-scandff-gf180mcu/tree/b136150cdcfd55a9568fe14a825c214c3af5dde4/designs/cells/gf180mcu_voidwalkers_sc_sdffrnq_4/sch/gf180mcu_voidwalkers_sc_sdffrnq_4.sch | qualified | voidwalkers-scandff | netlist_to_gds | # Scan D Flip-Flop with Active-Low Reset Layout Task
## Objective
Implement `gf180mcu_voidwalkers_sc_sdffrnq_4` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Functional data and scan selection, rising-edge storage, asynchronous active-low reset, and 50 MHz opera... | tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml | 99e5091d4974f939018a77c6e2e4109627af9267d5c4e4022490cd7f09044465 | tasks/gf180mcuD/pdk.toml | ce793ac96e84cb091d8042f1a02ba920f4999a4a1125befc6295abe342f3abde | tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md | tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/circuit.spice | 659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58 | tasks/gf180mcuD/voidwalkers-scandff/LICENSE |
ihp-sg13g2.analog-db.adc_001_inv1b | false | CMOS Inverter Threshold Core | ihp-sg13g2 | null | Mixed-signal | Characterizes an inverter switching threshold, output swing and timing. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/adc_001_inv1b | qualified | analog-db | netlist_to_gds | # CMOS Inverter Threshold Core Layout Task
## Objective
The fixed binding is a CMOS inverter: one 1/0.13 um NMOS and one 2.5/0.13 um PMOS, each m=1. Bodies connect to their respective rails through native physical contacts. It provides a threshold decision core; there is no sampling, independent reference, encoding o... | tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml | 3a04fa69272414d55f52a5a316c86c58ea614661589797e44e924b491fe1b4d5 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md | tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/circuit.cdl | abab97e938d458243277604a5dec9c2ac7a9648acc260d5012da4d4564b3c0ec | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_001_5t | false | Five-Transistor OTA Core with Bias Mirror | ihp-sg13g2 | null | Amplifiers & RF | Amplifies a differential input using an NMOS pair, PMOS mirror load and a separate bias reference. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_001_5t | qualified | analog-db | netlist_to_gds | # Five-Transistor OTA Core with Bias Mirror Layout Task
## Objective
Implement the fixed six-MOS `amp_001_5t` circuit in IHP SG13G2 and submit a
self-contained GDS. The circuit consists of a five-transistor OTA core and a
sixth, diode-connected bias-reference MOS. Device dimensions are fixed.
## Inputs and Interface... | tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml | 466d915b4be4942edaa8bbb675df11a7e8264953acebdfcb675c521c4e6abcdd | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/circuit.cdl | 55016e668fdcbc3087c98af6d92f196225fd586da3a9a8e049200fd0419c119f | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_002_alfio_raffc | false | Current-Buffer and Active-Feedforward OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with current-buffered compensation and an active feedforward path to the output. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_002_alfio_raffc | qualified | analog-db | netlist_to_gds | # Current-Buffer and Active-Feedforward OTA Layout Task
## Objective
Lay out `amp_002_alfio_raffc` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; a PMOS common-source stage
drives `ne... | tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml | bd138541d7ca733648fce30448cc347b58d60ab5b3f5979e00a24a8ec4f46cda | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/circuit.cdl | da8813082f4c6fb73b07d677efa730e1f1c250c9ebd438233f3f725346ac88f9 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_003_fan_smc | false | Single-Capacitor Three-Stage Feedforward OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through three stages with a single compensation capacitor and active feedforward. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_003_fan_smc | qualified | analog-db | netlist_to_gds | # Single-Capacitor Three-Stage Feedforward OTA Layout Task
## Objective
Lay out `amp_003_fan_smc` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; the PMOS stage at `net043`
and its NMO... | tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml | aa8f6daff1942773283c3b2363b1ab675e016c047528859cfdc1c550a84fed01 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/circuit.cdl | 5c0aa44f171b64424a7dc717a4d76f332bc9da6b39923f4ae527433622c43601 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_005_hoilee_affc | false | Current-Buffered Compensation OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with a folded input stage and two current-buffered compensation paths. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_005_hoilee_affc | qualified | analog-db | netlist_to_gds | # Current-Buffered Compensation OTA Layout Task
## Objective
Lay out `amp_005_hoilee_affc` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; a PMOS/diode/mirror stage
drives `net049`, fo... | tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/case.toml | efad519672b6efb33c116881de1904591dfa238839601263f5f29c773e9dac38 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_005_hoilee_affc/materials/circuit.cdl | d16b4edb2bff902499a0519b595961ad69cf940221b11f12a423ef2863685757 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_006_leung_dfcfc1 | true | Output-Controlled Auxiliary Compensation OTA | ihp-sg13g2 | 15 | Amplifiers & RF | Amplifies differential signals with dual compensation paths and an output-controlled auxiliary stage. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_006_leung_dfcfc1 | qualified | analog-db | netlist_to_gds | # Output-Controlled Auxiliary Compensation OTA Layout Task
## Objective
Lay out `amp_006_leung_dfcfc1`, retaining the complete folded PMOS-input stage,
three-stage signal path, direct output feedforward, and auxiliary compensation.
The folded stage drives `net050`, which drives the output PMOS and the
PMOS/diode/mirr... | tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/case.toml | 2bbd6b092729b2d5be8b9314e1171ff69de68752c746679c7b8dd6af99e36a27 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/materials/circuit.cdl | bd35a8a0dd5ae4b3b413ee2074eaa9fb35c8393daed8a1c38a55582d9dc10cc8 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_007_leung_dfcfc2 | false | Auxiliary-Stage Miller Compensation OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with active feedforward and a separate auxiliary Miller-compensation stage. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_007_leung_dfcfc2 | qualified | analog-db | netlist_to_gds | # Auxiliary-Stage Miller Compensation OTA Layout Task
## Objective
Lay out `amp_007_leung_dfcfc2` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; the PMOS/diode/mirror path
drives `net... | tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/case.toml | 7bc67596b209c140d4e73c01c284c65e9eb6b98fddff02539ca4352345c6ab30 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_007_leung_dfcfc2/materials/circuit.cdl | 3e1d203a196d5cf5f13d15a6c347fcf8c2a907ccddd8b352a845f0fbeff664c0 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_008_leung_nmcf | false | Dual-Capacitor Three-Stage OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through three stages with two compensation capacitors and output feedforward. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_008_leung_nmcf | qualified | analog-db | netlist_to_gds | # Dual-Capacitor Three-Stage OTA Layout Task
## Objective
Lay out `amp_008_leung_nmcf` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; a PMOS stage at `net043`
and its NMOS mirror driv... | tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/case.toml | f338aab3128661281c0ed2fa0e15a317cfc5f24a0838ae9a46b48b6920bac7ec | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_008_leung_nmcf/materials/circuit.cdl | 8e12afdcc86858f64dc3dab7effa448ef1cb877a1c235001b3db1406d36d132a | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_009_leung_nmcnr | false | Shared-Nulling-Resistor Three-Stage OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through three stages whose compensation capacitors share a nulling resistor. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_009_leung_nmcnr | qualified | analog-db | netlist_to_gds | # Shared-Nulling-Resistor Three-Stage OTA Layout Task
## Objective
Lay out `amp_009_leung_nmcnr` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; the PMOS stage at `net043`
and its NMOS... | tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/case.toml | 121a33161864f385994766df7de0864b79cd5a0292c47ac79fb142e27a493d45 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_009_leung_nmcnr/materials/circuit.cdl | 68c55b7866f4dd6640069867385394c0ed2c9b8c026a215df0b2dd381faab6ef | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_010_peng_acbc | false | Auxiliary-Branch Compensation OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with feedforward and a compensated auxiliary branch. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_010_peng_acbc | qualified | analog-db | netlist_to_gds | # Auxiliary-Branch Compensation OTA Layout Task
## Objective
Lay out `amp_010_peng_acbc` with its physical compensation and fixed transistor network,
for the declared loop response and sustained unity-feedback step recovery.
The folded PMOS-input stage drives `net050`; a PMOS/diode/mirror stage
drives `net049`, foll... | tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/case.toml | 36a9aca34e26e6d3fb57c12a15dc75e639d42b3aaac78340b8bf6cf56d1c4fd3 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_010_peng_acbc/materials/circuit.cdl | e8fcd5473160b4dd336813dfb86122e023e06285c6878100e717abe9a4f6aa6f | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_011_peng_iac | false | Peng IAC Three-Stage Amplifier | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through three stages with cascoded bias and auxiliary current paths. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_011_peng_iac | qualified | analog-db | netlist_to_gds | # Peng IAC Three-Stage Amplifier Layout Task
## Objective
Implement `amp_011_peng_iac` with the supplied fixed topology and dimensions. The PMOS input pair and cascoded branches feed voutn/voutp. The PMOS bias mirror is cascoded with vb2, generated by XM65/XM63/XM64. XM10 drives net043; XM67/XM68 and XM70 retain the ... | tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/case.toml | 23a21d8b9b8af79f3b6a129931f8e4fb4a01f533c4ea39a64e7dd0ac657fcf12 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_011_peng_iac/materials/circuit.cdl | e96cbf2422a28df546809a5b96a0039dc081caef58fc61c63a65d622bd042fda | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_012_peng_tcfc | false | Auxiliary Source-Driven Output-Control OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with a folded input stage and an auxiliary source-driven output-control path. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_012_peng_tcfc | qualified | analog-db | netlist_to_gds | # Auxiliary Source-Driven Output-Control OTA Layout Task
## Objective
Lay out `amp_012_peng_tcfc` with its complete transistor signal and bias paths.
The PMOS-input folded stage produces `voutp`, driving the output PMOS and
`net043` branch. The large PMOS path through `net049` feeds `net10`, while
`net043` controls i... | tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/case.toml | 382f0dc787f5b05de93c34a10a2e52842c93e0b0c93fe3a75821e958b37b7b63 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_012_peng_tcfc/materials/circuit.cdl | 164eba92a9ddf29a58abf956176b9008d07e746968e502e3c0a5926c888b08a2 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_013_qu2017_azc | false | Qu AZC Three-Stage Amplifier | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through a three-stage network with auxiliary output-control branches. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_013_qu2017_azc | qualified | analog-db | netlist_to_gds | # Qu AZC Three-Stage Amplifier Layout Task
## Objective
Implement `amp_013_qu2017_azc` without changing the declared circuit. XM9/XM10 form the PMOS input pair with their bodies tied to the common source net019. XM14–XM17 form the active NMOS load around DM_2/net063; XM4/XM5 convert this to net050. XM11 drives net094... | tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/case.toml | c51472773649c98d66a69f372ad7a64f2910b8e34e55f7a62a8af33cb2b7ed8b | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_013_qu2017_azc/materials/circuit.cdl | f1c405743131712ff44eafdf85b9f6e40c61ac65c538182a4bec0cf44579e616 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_014_ramos_pfc | true | Ramos PFC Three-Stage Amplifier | ihp-sg13g2 | 3 | Amplifiers & RF | Amplifies differential signals through a cascoded input and mirror stages into a single-ended output. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_014_ramos_pfc | qualified | analog-db | netlist_to_gds | # Ramos PFC Three-Stage Amplifier Layout Task
## Objective
Implement `amp_014_ramos_pfc` with the supplied fixed topology and dimensions. The PMOS input pair drives the cascoded NMOS branches at dm_2/net063; the voutn mirror produces net050. XM10 and the XM21/XM22 mirror drive net049, while XM11/XM23 drive the single... | tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/case.toml | 396ca49308f3a05bb5516fd06d591b7e674cad6ceccbf9b1ff6cdeed7841e8b7 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/materials/circuit.cdl | e68e4f2e2edd7f40f8c8087573462ffe9bbaa53f3e47db84932e0880233677c1 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_015_sau_cfcc | false | Input-Driven Active-Feedforward OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals using a folded input stage and direct input-driven active feedforward. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_015_sau_cfcc | qualified | analog-db | netlist_to_gds | # Input-Driven Active-Feedforward OTA Layout Task
## Objective
Lay out `amp_015_sau_cfcc` with its complete transistor signal and bias paths.
The PMOS-input folded stage produces `voutn`, controlling the mirror at
`net050` and the auxiliary PMOS at `net049`. The `net050 → net043 → net049`
path and direct input-driven... | tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/case.toml | 979587a7682747f5a8925610d563da3e8497da0ae2995d84fb35ac2c3c77aa2d | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_015_sau_cfcc/materials/circuit.cdl | 97d4a622ebdbebdeed5e1050e29ca4c1ab7496c39596180bec3270f7efc79901 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_016_song_dacfc | false | Song DACFC Three-Stage Amplifier | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals using a primary signal path and a separately biased auxiliary input pair. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_016_song_dacfc | qualified | analog-db | netlist_to_gds | # Song DACFC Three-Stage Amplifier Layout Task
## Objective
Implement `amp_016_song_dacfc` with the supplied fixed topology and dimensions. The primary PMOS input pair feeds the cascoded voutn/net4 path. The separate XM57/XM58 input pair, biased by XM59, feeds net043/net049 directly; XM7 also feeds net049 from voutn.... | tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/case.toml | 75b2c76f9a7e2d2c8d71ae8b308c611eb5944bba5d6eb9b3a14c8b024603bf97 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_016_song_dacfc/materials/circuit.cdl | 5658b9596b3ed2b28c97f87fc0b7df00533cd950b6a70a61b6d64a8d4f4701e3 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_021_yan_az | false | Yan AZ Three-Stage Amplifier | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through a cascoded input stage and separate mirror-driven internal branches. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_021_yan_az | qualified | analog-db | netlist_to_gds | # Yan AZ Three-Stage Amplifier Layout Task
## Objective
Implement `amp_021_yan_az` without changing the declared circuit. XM9/XM10 form the PMOS input pair with bodies tied to net019. XM14/XM15 are the cascoded load branches controlled by XM16/XM17 and the net078 resistive network; XM4/XM5 produce net050. XM11/XM22 d... | tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/case.toml | a65d2dab12ffe150948b31617626e7a17c8d62fbcb1e5d0b62b58898fb026c7b | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_021_yan_az/materials/circuit.cdl | bdff9e4ee79809ab2499f77c52d9269d6728db8319af616d650ed4a3163f4696 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_022_fer_two_stage | false | Fer Two-Stage Miller Amplifier | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals using a PMOS input pair, common-source second stage and Miller capacitor. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_022_fer_two_stage | qualified | analog-db | netlist_to_gds | # Fer Two-Stage Miller Amplifier Layout Task
## Objective
Implement `amp_022_fer_two_stage` as a GDS layout preserving the complete declared circuit. PMOS differential input pair, NMOS mirror load, NMOS common-source second stage and PMOS current-source load, retaining Miller CC and the complete NMOS-to-PMOS bias mir... | tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/case.toml | e816debe5450bcb66353602ec5c56b77f0cbd6603f9b38b0d465df21bbf65d2f | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_022_fer_two_stage/materials/circuit.cdl | 2a25c4caa82f7908ba955e77031391b2d2a98888c2a6f8e96643fc49802a0ab4 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_023_fer_fd2s | true | Two-Stage Fully Differential OTA with RC Common-Mode Feedback | ihp-sg13g2 | 19 | Amplifiers & RF | Amplifies fully differential signals with two output stages, physical R/C compensation and transistor common-mode feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_023_fer_fd2s | qualified | analog-db | netlist_to_gds | # Two-Stage Fully Differential OTA with RC Common-Mode Feedback Layout Task
## Objective
Implement `amp_023_fer_fd2s`: an NMOS-input folded first stage, two NMOS
common-source output stages, dual series R/C compensation and transistor
common-mode feedback sensing both outputs through physical R/C arms. Preserve
all d... | tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/case.toml | e37f8fbfd9d189ab02f68b75074bcec6a3fb1bb7c8b970359c0ea96b03c79e99 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/materials/circuit.cdl | 4c52bdbbe491a400eff644efb33e0e97af38d50073ccb1a5a5a76964931f569c | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_024_smcnr | false | Series-Nulling-Resistor Two-Stage OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals through two stages with a physical series nulling resistor in the Miller path. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_024_smcnr | qualified | analog-db | netlist_to_gds | # Series-Nulling-Resistor Two-Stage OTA Layout Task
## Objective
Lay out `amp_024_smcnr`, a PMOS-input two-stage OTA with series R/C Miller
compensation, for stable loaded unity-feedback response. Preserve the eight
MOS groups' fixed W/L/m, physical compensation network and explicit bias interface.
## Inputs and Int... | tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/case.toml | 7a788998129e2697cf79274c86b01791fe70522b4c619b9122b22d71259fcfd1 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_024_smcnr/materials/circuit.cdl | 0b9a0afed61b6479a3c7cb1b8c6581ab8ad8623db88c3d5515137be83de4399c | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_026_fan_chopper_ota | false | Fan Two-Stage OTA with Static Output Chopper | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with a two-stage core and an output chopper held in its straight-through state. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_026_fan_chopper_ota | qualified | analog-db | netlist_to_gds | # Fan Two-Stage OTA Layout Task
## Objective
Implement the supplied 23-MOS, two-capacitor two-stage OTA with its statically straight-through output chopper. Preserve all devices, connections and dimensions. The cross branches remain present and off; no CMFB exists or may be added. Four MIM units realize the two 6 pF ... | tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/case.toml | 4dbd1f4f0ef5f5635a7f3cea4906bc7856a16211725a4f45208b450451b43ab1 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_026_fan_chopper_ota/materials/circuit.cdl | e7f02597a0b80263ce7707ffcc520cd7cda3b89f5580fd1b7d5df215585b1158 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_027_fan_rrl_ota | false | Fan Telescopic OTA with Transistor DDA-CMFB | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals using a telescopic core with transistor common-mode feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_027_fan_rrl_ota | qualified | analog-db | netlist_to_gds | # Fan Telescopic OTA Layout Task
## Objective
Implement the supplied 16-MOS telescopic OTA with its transistor DDA-CMFB. Preserve all devices, connections and dimensions. This task contains only the OTA core.
## Inputs and Interface
- `problem.md`: task description.
- `materials/circuit.cdl`: physical netlist.
- `m... | tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/case.toml | 05d648306bcabf373905b4e21a7e0c6c7f531fe19ad30714a92a89487e1c6c5a | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_027_fan_rrl_ota/materials/circuit.cdl | 4bf3794124ddb9251f09ad02d608e6f4b15a5a4e57260a94676911b5904a9ddb | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_029_two_stage_miller_comp | false | Differential Two-Stage Miller Amplifier Without CMFB | ihp-sg13g2 | null | Amplifiers & RF | Amplifies fully differential signals through two Miller-compensated stages without common-mode feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_029_two_stage_miller_comp | qualified | analog-db | netlist_to_gds | # Differential Two-Stage Miller Amplifier Without CMFB Layout Task
## Objective
Implement `amp_029_two_stage_miller_comp` as a GDS layout preserving the complete declared circuit. Fully differential NMOS-input two-stage Miller amplifier without CMFB. Ten physical MOS retain both PMOS first-stage current sources, both... | tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/case.toml | 4e2e4d2a21c55711baff50628f787b34ab51a73c86c875c21f80386d776b7dba | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_029_two_stage_miller_comp/materials/circuit.cdl | c8709463f9bc4f0c0d858b246823449bf36470ad5e9fe9e067f3557936ef02cd | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_034_fan_chopper_cmfb | false | Fan Output CMFB OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with a folded first stage, static output chopper and output common-mode feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_034_fan_chopper_cmfb | qualified | analog-db | netlist_to_gds | # Fan Output CMFB OTA Layout Task
## Objective
Implement `amp_034_fan_chopper_cmfb` without changing the declared circuit. The fixed upstream flattened composite contains a PMOS input pair, folded-cascode first stage, statically straight-through transmission-gate output chopper and common-source second stage. Its own... | tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/case.toml | 94870038c4871a2d35a323450d87c29de2ebbad06a6b1d8ba400e90c80b1b0e8 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_034_fan_chopper_cmfb/materials/circuit.cdl | dcbb83aa8b8f5e038343c1bc8a52e4882169995747e809442136379ba0f33896 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.amp_035_fan_chopper_cmfb_dual | false | Fan Dual CMFB OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with a static output chopper and separate stage/output common-mode feedback loops. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/amp_035_fan_chopper_cmfb_dual | qualified | analog-db | netlist_to_gds | # Fan Dual CMFB OTA Layout Task
## Objective
Implement `amp_035_fan_chopper_cmfb_dual` without changing the declared circuit. The independently frozen flattened composite contains the PMOS input/folded-cascode first stage, static straight-through output chopper and common-source second stage. One seven-transistor CMF... | tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/case.toml | a27495067d352cad2b406e1bf000dc70d938ee7c21781edf9b55dbe9b5141240 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/problem.md | tasks/ihp-sg13g2/analog-db/cases/amp_035_fan_chopper_cmfb_dual/materials/circuit.cdl | 49c446a5ec68bdad0a70299c813709ca45fb59a4a99330d217c8d29e74a06af3 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.buf_001_super_follower | false | MIM-Compensated Local-Feedback Source Follower | ihp-sg13g2 | null | Amplifiers & RF | Buffers a signal with local feedback and physical MIM compensation. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/buf_001_super_follower | qualified | analog-db | netlist_to_gds | # MIM-Compensated Local-Feedback Source Follower Layout Task
## Objective
Implement `buf_001_super_follower` in ihp-sg13g2 and submit self-contained GDS. Six MOS entries expand to 17 physical MOS instances in a local-feedback source follower. Fixed IHP W/L/m are retained. The internal na-to-VSS 250 fF compensation is... | tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/case.toml | cc34c593f9945630e396f758660ae6423bf7429e14a993c076b10f4b571a52fe | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/problem.md | tasks/ihp-sg13g2/analog-db/cases/buf_001_super_follower/materials/circuit.cdl | 2f617c485f1bd1d94d47a1fc21c6c1e815fb9f4a4278ee93c2a1eb80b80a4404 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.cmfb_002_5t_pmos_input | false | PMOS-Input Common-Mode Detector and Controller | ihp-sg13g2 | null | Amplifiers & RF | Detects and controls common-mode voltage with a PMOS-input feedback core. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_002_5t_pmos_input | qualified | analog-db | netlist_to_gds | # PMOS-Input Common-Mode Detector and Controller Layout Task
## Objective
Implement `cmfb_002_5t_pmos_input` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. Seven MOS implement a PMOS-input five-transistor OTA plus the PMOS/NMOS diode bias branch. Two ... | tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/case.toml | 00354a00329bf4152ad32734811a0deaac4a05687a7910daa2735c2c67938ceb | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/problem.md | tasks/ihp-sg13g2/analog-db/cases/cmfb_002_5t_pmos_input/materials/circuit.cdl | e2c671312003fc7e6f8e86f593c3e04db6016f676dfa064a275c95fba54b641e | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.cmfb_004_output_switched_cap | false | MIM Switched-Capacitor Common-Mode Sampler | ihp-sg13g2 | null | Mixed-signal | Samples common-mode voltage using clocked switches and physical MIM capacitors. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/cmfb_004_output_switched_cap | qualified | analog-db | netlist_to_gds | # MIM Switched-Capacitor Common-Mode Sampler Layout Task
## Objective
Implement `cmfb_004_output_switched_cap` in IHP SG13G2 and submit a self-contained GDS. Sixteen minimum-size MOS (W/L = 0.15/0.13 um) implement eight transmission paths. Four internal MIM capacitors retain the original connections: two separate vbi... | tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/case.toml | a65e75c236aa7b1683570b8e12f7eba819855a6a9115c4d0683a3110e861e94c | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/problem.md | tasks/ihp-sg13g2/analog-db/cases/cmfb_004_output_switched_cap/materials/circuit.cdl | 3a3ca59eef1a93dd54f0e78087fccb7e250f354833ec52950e1b0f425daef481 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.drv_001_pam4_sige_dac | true | Upstream broadband SiGe PAM4 current-steering driver | ihp-sg13g2 | 21 | Amplifiers & RF | Combines weighted current-steering cells into a SiGe PAM4 driver. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/drv_001_pam4_sige_dac | qualified | analog-db | netlist_to_gds | # Broadband SiGe PAM4 Driver Layout Task
## Objective
Lay out the upstream inductorless, three-cell current-steering PAM4 driver as
`pam4drv_pam4_lay`. One LSB cell and two parallel MSB cells contain twelve
three-finger `npn13G2` HBTs, twelve physical `rsil` resistors and three physical
MIM degeneration capacitors. P... | tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/case.toml | da9d3a880b22e5e8039b0c74748d2383597a2ec7406dafa561097e7cc249b652 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md | tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/materials/circuit.cdl | 310d1f67d5d237cfc88525f26568c5bcf45680bb2e8141982600669ee81a2ead | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.ia_002_fan_chopper_simple | false | Fan Clocked Capacitive Instrumentation Amplifier | ihp-sg13g2 | null | Amplifiers & RF | Processes differential signals with a clocked, capacitively coupled instrumentation amplifier. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_002_fan_chopper_simple | qualified | analog-db | netlist_to_gds | # Fan Clocked Capacitive Instrumentation Amplifier Layout Task
## Objective
Implement the supplied 39 MOS, 2 R, 6 C circuit. Preserve the running input, feedback and output choppers. There is no CMFB. Do not add a servo, remove or disable signal/feedback branches, or change the fixed transistor sizing and bias contra... | tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/case.toml | 5a0cdffd99b3ce4a68842b0d390e9821378312985d797f9d9a33448aea574d6d | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/problem.md | tasks/ihp-sg13g2/analog-db/cases/ia_002_fan_chopper_simple/materials/circuit.cdl | 6849882e48941049efe869b0bb83e337b62e1f76d3d6d22a14038931fa7cdaa7 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.ia_003_fan_chopper_pf | false | Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback | ihp-sg13g2 | null | Amplifiers & RF | Combines clocked capacitive instrumentation amplification with positive feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_003_fan_chopper_pf | qualified | analog-db | netlist_to_gds | # Fan Clocked Capacitive Instrumentation Amplifier with Positive Feedback Layout Task
## Objective
Implement the supplied 47 MOS, 2 R, 8 C circuit. Preserve the running input, feedback and output choppers, including the positive-feedback chopper and capacitors. There is no CMFB. Do not add a servo, remove or disable ... | tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/case.toml | a456858c30aa6b4452fa28c965e9c66f98d43367fa00bf4546f64f70043c5265 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/problem.md | tasks/ihp-sg13g2/analog-db/cases/ia_003_fan_chopper_pf/materials/circuit.cdl | 2b15a77345aceac980332a2c9cab0e148238b01d04ddc633de4f178426b4e78c | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.ia_006_fan_chopper_cmfb | true | Clocked Capacitive Instrumentation Amplifier with Transistor CMFB | ihp-sg13g2 | 5 | Amplifiers & RF | Combines clocked capacitive instrumentation amplification with transistor common-mode feedback. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ia_006_fan_chopper_cmfb | qualified | analog-db | netlist_to_gds | # Clocked Capacitive Instrumentation Amplifier with CMFB Layout Task
## Objective
Implement `ia_006_fan_chopper_cmfb`: a complete capacitively coupled differential
instrumentation amplifier with input, feedback and interstage/output chopping,
a two-stage amplifier and transistor common-mode feedback (CMFB). Preserve ... | tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/case.toml | e6837e7ce82b02df2cbac3ed8f63cd098ad97765bb878c50471fcc42a90a6d90 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md | tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/materials/circuit.cdl | e5049836e133e951c36c34dd5eed0fe1c2492f1671930153c97cf4ccae786f1d | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.ldo_001_analoggym_basic | false | Multistage Error-Amplifier PMOS Regulator | ihp-sg13g2 | null | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_001_analoggym_basic | qualified | analog-db | netlist_to_gds | # Multistage Error-Amplifier PMOS Regulator Layout Task
## Objective
Lay out `ldo_001_analoggym_basic`: a PMOS pass regulator with a folded
PMOS-input error amplifier, cascoded bias branches, mirrored loads and an
additional PMOS/NMOS intermediate branch driving the pass-gate node `net1`.
The auxiliary PMOS source an... | tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/case.toml | d645686289b5fa6e613e3989d1d8362322a86a77778d368eaaa3418bb40a6b10 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/problem.md | tasks/ihp-sg13g2/analog-db/cases/ldo_001_analoggym_basic/materials/circuit.cdl | 46bc249c1f72b4d0162bcef20f66deea9b729be29d63babe3c2f53cb47320796 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.ldo_008_fer_mirror_ota | true | Mirror-OTA Regulator with Bilateral Return-Ratio Measurements | ihp-sg13g2 | 20 | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_008_fer_mirror_ota | qualified | analog-db | netlist_to_gds | # Mirror-OTA Regulator with Bilateral Return-Ratio Measurements Layout Task
## Objective
Implement `ldo_008_fer_mirror_ota`: a mirror-loaded NMOS-input error amplifier,
diode/tail bias network, PMOS pass device, feedback divider and series R/C
compensation. Preserve all seven source MOS groups as 81 physical fingers,... | tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/case.toml | f64f63c1b5efb2fcdd1557d2662dd7f73a9ac2581c0d4f279d046811a7df7346 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md | tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/materials/circuit.cdl | 810d7fc0b63340bbd097f338e2a5c7fed29aaa5a51370abe30fc28b80297e1db | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.ldo_009_fer_5t_pass | false | Unity-Feedback Regulator with Internal Output Storage | ihp-sg13g2 | null | Power & references | Regulates a loaded output through the declared feedback loop, with layout-dependent recovery and power. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/ldo_009_fer_5t_pass | qualified | analog-db | netlist_to_gds | # Unity-Feedback Regulator with Internal Output Storage Layout Task
## Objective
Lay out `ldo_009_fer_5t_pass` with the complete physical error amplifier, pass array,
compensation, output storage, bleeder and reference path.
A five-transistor NMOS-input error amplifier drives a PMOS pass array;
an on-chip diode-conn... | tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/case.toml | f4d45cd7afe88b560a782b1d19d48ffca4441903c0c66c04ad80340bee4ca69f | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/problem.md | tasks/ihp-sg13g2/analog-db/cases/ldo_009_fer_5t_pass/materials/circuit.cdl | 1788fa17f1811dd7e6596e6edc5c2edde837c878b590084fd239855c89ba50a4 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.smp_001_nmos_th | true | Physical NMOS Sample-and-Hold: Headroom and Retention | ihp-sg13g2 | 6 | Mixed-signal | Samples and holds a voltage with an NMOS switch and an internal storage capacitor. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/smp_001_nmos_th | qualified | analog-db | netlist_to_gds | # Physical NMOS Sample-and-Hold Layout Task
## Objective
Implement `smp_001_nmos_th`: a single-NMOS sampling switch with an internal
physical storage capacitor. Preserve the switch and stored-charge node, and
meet acquisition, turn-off pedestal, isolated-input feedthrough, hold drift
and reacquisition requirements at... | tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/case.toml | 56e176e477f0c2c0b4395d70d29c17450bb7cf3aafc9e7625b995950e99570ec | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md | tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/materials/circuit.cdl | 846cb6797fae4bca4b793d23239e778299f46ec0b3342e44d2a014ca5d6b3802 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.sw_001_transmission_gate_pair | false | Bidirectional CMOS Transmission Gate | ihp-sg13g2 | null | Mixed-signal | Transfers analog signals bidirectionally through a CMOS transmission gate. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_001_transmission_gate_pair | qualified | analog-db | netlist_to_gds | # Bidirectional CMOS Transmission Gate Layout Task
## Objective
Implement `sw_001_transmission_gate_pair` with the complete fixed topology and minimize layout-induced degradation under the declared nominal observations. The fixed IHP binding has one NMOS and one PMOS, each W=2 um, L=0.13 um, m=1. Both connect the bid... | tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/case.toml | 19a211c5f0da89715ee0e0bdca2c95eb8daad2cf5536e9264b74032a0c6a7d17 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/problem.md | tasks/ihp-sg13g2/analog-db/cases/sw_001_transmission_gate_pair/materials/circuit.cdl | 876abf23efe2510080ab3e623bc794339d8920bf8a7d30a476b80cdad91e027a | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.sw_002_chopper_diff | false | Differential Polarity-Commutating Switch | ihp-sg13g2 | null | Mixed-signal | Commutates differential signal polarity with a clock-controlled switch network. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_002_chopper_diff | qualified | analog-db | netlist_to_gds | # Differential Polarity-Commutating Switch Layout Task
## Objective
Implement `sw_002_chopper_diff` in ihp-sg13g2 and submit self-contained GDS. Eight MOS devices form four transmission paths that connect a differential input directly or with reversed polarity. The two complementary clock nets are independent layout ... | tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/case.toml | 834088a5a80f06bc520857d5c6d5441aa9b310a69ce354bcf0f6a72b1c9265a4 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/problem.md | tasks/ihp-sg13g2/analog-db/cases/sw_002_chopper_diff/materials/circuit.cdl | e0b1c58cdd6e35af46612beae826db9d950ca0e83ddb0297ee224699fd9c3c7a | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.sw_003_binary_capbank | false | Three-Bit MIM Capacitive Transfer Bank | ihp-sg13g2 | null | Mixed-signal | Selects capacitive transfer using a three-bit bank of physical MIM capacitors. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/sw_003_binary_capbank | qualified | analog-db | netlist_to_gds | # Three-Bit MIM Capacitive Transfer Bank Layout Task
## Objective
Implement `sw_003_binary_capbank` in IHP SG13G2 and submit a self-contained GDS. Twelve minimum-size MOS (W/L = 0.15/0.13 um) select the bottom plates of a 1:1:2:4 MIM capacitor bank between vinp and VCM. Eight identical 25.85 by 25.85 um cap_cmim unit... | tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/case.toml | e3636e9dae05314e67fe3c06116ab3aadff2f4ce3d46b043bfaee23c490af722 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/problem.md | tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/materials/circuit.cdl | dec8a6b73b1345482fdf6cf69f3065c000b7cf50ddebe04ee1738603f0b24c77 | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.trm_001_vcr | false | Resistor-Pullup NMOS Shunt Trim | ihp-sg13g2 | null | Mixed-signal | Controls a resistor-pulled output using an NMOS shunt driven by an analog voltage. | https://github.com/MacAnalog/spicexplorer-release/tree/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/circuits/trm_001_vcr | qualified | analog-db | netlist_to_gds | # Resistor-Pullup NMOS Shunt Trim Layout Task
## Objective
Implement `trm_001_vcr`, a voltage-controlled NMOS shunt with a physical
approximately 200 kohm supply pullup. Preserve the source W=2 um / L=0.5 um
NMOS, eight series high-poly segments and explicit substrate tap. Qualification
measures loaded trim range, mo... | tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/case.toml | f087d9d92231c5e304660862aefe1f391b9d5878e54e191fcc4184519471a4a7 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/problem.md | tasks/ihp-sg13g2/analog-db/cases/trm_001_vcr/materials/circuit.cdl | ed94062ae8c8856ffe51593d5134a9926c266e6620767f13d491a21ad288136a | tasks/ihp-sg13g2/analog-db/LICENSE |
ihp-sg13g2.analog-db.vref_001_vgs | false | Mixed LV/HV VGS Reference with Picoampere Load and Zero-State Recovery | ihp-sg13g2 | null | Power & references | Establishes a voltage reference using a mixed low/high-voltage two-transistor core. | https://github.com/MacAnalog/spicexplorer-release/blob/263d0322f8900dc331536fbbe6c0e804514fc454/analog-db/raw/vref_001_vgs/ihp-sg13g2/_dut.spice | qualified | analog-db | netlist_to_gds | # Mixed LV/HV VGS Reference Layout Task
## Objective
Implement the two-transistor `vref_001_vgs` reference with its original device
sizes and connections. An upper LV NMOS has gate and source at VREF; a lower
HV NMOS is diode-connected. The maintained function is a high-impedance,
approximately 0.36 V reference for p... | tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/case.toml | 251fbb86e82ce2f65a070f7c9befcb733699ea5ada5cf4205cee58ee8e6e44c8 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/problem.md | tasks/ihp-sg13g2/analog-db/cases/vref_001_vgs/materials/circuit.cdl | 4352aeb85c2a7bfb00181738a742d0ccbd5033b422393bafa6a82bd84c1e84b9 | tasks/ihp-sg13g2/analog-db/LICENSE |
module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA | false | IHP AnalogAcademy full_OTA | ihp-sg13g2 | null | Amplifiers & RF | Amplifies differential signals with a two-stage CMOS OTA. | https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch | qualified | IHP-AnalogAcademy | netlist_to_gds | # Two-Stage CMOS OTA Layout Task
## Objective
Create an IHP SG13G2 layout for the `two_stage_OTA_layout` two-stage CMOS
operational transconductance amplifier. Preserve the MOS and MIM devices,
dimensions, connectivity, well and substrate connections, and six-port
interface in the authoritative materials. The submitt... | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml | 90afcf143abb7975b8e540091777a26b280a97e1a9efdbbeb8cf0837bb5ef52a | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/circuit.cdl | b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409 | tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE |
module_1_bandgap_reference.part_3_layout.OTA_layout.input_pair | false | IHP AnalogAcademy input_pair | ihp-sg13g2 | null | Amplifiers & RF | Converts a differential input into a balanced response using a matched PMOS pair. | https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch | qualified | IHP-AnalogAcademy | netlist_to_gds | # PMOS Differential Input Pair Layout Task
## Objective
Create an IHP SG13G2 layout for the `input_common_centroid` matched PMOS
differential input pair. Preserve the device topology, dimensions, dummy
devices, explicit well and substrate connections, and six-port interface in the
authoritative materials. The submitt... | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml | fa3b7226821903f087f0b049b5408c7ccd71d7a957c7c07b1a3da19c24c49f06 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/problem.md | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/circuit.cdl | 25456f0316c22ee5586ad3e306f0d513fd35e48f32ee67ce9cb0dc373d306f3d | tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE |
module_1_bandgap_reference.part_3_layout.OTA_layout.output_stage | false | IHP AnalogAcademy output_stage | ihp-sg13g2 | null | Amplifiers & RF | Provides the loaded output response of a two-stage CMOS OTA. | https://github.com/IHP-GmbH/IHP-AnalogAcademy/blob/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/output_stage/schematic_mod/output_stage.sch | qualified | IHP-AnalogAcademy | netlist_to_gds | # CMOS OTA Output Stage Layout Task
## Objective
Create an IHP SG13G2 layout for the `output_stage` output stage of a two-stage
CMOS operational transconductance amplifier. Preserve the device topology,
dimensions, compensation capacitor, explicit well and substrate connections,
and five-port interface in the authori... | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml | 2b7cc5b73f6683b09165760071b31c7df1302ddf6b6c5f942aa795ade25f9f02 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/problem.md | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/circuit.cdl | 81620ebba529edccd1beddbcb1349c0e3e7ee58b9e3749d8235433610bd98ad5 | tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE |
module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator | false | IHP AnalogAcademy comparator | ihp-sg13g2 | null | Mixed-signal | Compares two input voltages using a clocked regenerative decision. | https://github.com/IHP-GmbH/IHP-AnalogAcademy/tree/133ecf657572e021b5921b5a1b7693abfb209623/modules/module_3_8_bit_SAR_ADC/part_5_analog_layout/comparator | qualified | IHP-AnalogAcademy | netlist_to_gds | # Dynamic Comparator Layout Task
## Objective
Create an IHP SG13G2 layout for the `DIFF_COMPARATOR` dynamic differential
comparator. Preserve the topology, device parameters, explicit well and
substrate connections, and eight-port interface in the authoritative materials.
The submitted GDS must pass the physical chec... | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml | b85594863f25ca0960b89924f9b3b414661ead958c1f0254f4cad696e22317e8 | tasks/ihp-sg13g2/pdk.toml | 37c308dab7bf60e1b6f621aac194e913866c36304e8a8a0ba799c274e3dc7ed6 | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md | tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/materials/circuit.cdl | 0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c | tasks/ihp-sg13g2/IHP-AnalogAcademy/LICENSE |
sky130A.OpenFASOC.current_mirror | true | SKY130 1:1 Interdigitated Current Mirror | sky130A | 2 | Power & references | Copies a reference current with a 1:1 interdigitated current mirror across the declared output-voltage range. | https://github.com/idea-fasoc/OpenFASOC/tree/426c17025c7c01d6e7d4d259fb7f9e7d741cc5c4/openfasoc/generators/glayout | qualified | OpenFASOC | netlist_to_gds | # SKY130 1:1 Interdigitated Current Mirror Layout Task
## Objective
Implement `CMIRROR` from the supplied transistor-level circuit, preserving topology, fixed device parameters, four-terminal body connections and the ordered interface. Submit a candidate GDS for electrical evaluation of its distributed RC extraction.... | tasks/sky130A/OpenFASOC/cases/current_mirror/case.toml | 0779716c43f0598aa22d8d431e70419de535da3670db2a1cee62c12113c3358a | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/OpenFASOC/cases/current_mirror/problem.md | tasks/sky130A/OpenFASOC/cases/current_mirror/materials/circuit.spice | d4466dab26872619dd7ef0f5e9848ad2af1d517836be300a7f49a531d5047c42 | tasks/sky130A/OpenFASOC/LICENSE |
sky130A.OpenFASOC.two_stage_opamp | false | SKY130 Two-Stage Miller Operational Amplifier | sky130A | null | Amplifiers & RF | Amplifies differential inputs with a two-stage Miller amplifier characterized at noise gain ten. | https://github.com/idea-fasoc/OpenFASOC/tree/426c17025c7c01d6e7d4d259fb7f9e7d741cc5c4 | qualified | OpenFASOC | netlist_to_gds | # SKY130 Two-Stage Miller Operational Amplifier Layout Task
## Objective
Implement `OPAMP_TWO_STAGE` from the supplied transistor-level circuit, preserving topology, fixed device parameters, four-terminal body connections and the ordered interface. Submit a candidate GDS for electrical evaluation of its distributed R... | tasks/sky130A/OpenFASOC/cases/two_stage_opamp/case.toml | 1648f670c0796c2d4fb71c1405f9bbe5a327b3f13dd0a6ca337dfe208d58d512 | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/OpenFASOC/cases/two_stage_opamp/problem.md | tasks/sky130A/OpenFASOC/cases/two_stage_opamp/materials/circuit.spice | f49f855271aef32cc4b890fd261f376a632d2d389b936a73f944de8d50503b89 | tasks/sky130A/OpenFASOC/LICENSE |
sky130A.sky130_ef_ip__ccomp3v.ccomp3v | false | SKY130 Continuous Comparator with Complementary Input Load | sky130A | null | Mixed-signal | Compares differential inputs across three common-mode voltages with a complementary input load. | https://github.com/efabless/sky130_ef_ip__ccomp3v/tree/b051f6131efe5c1169e52a826f893c1a4f65eff0 | qualified | sky130_ef_ip__ccomp3v | netlist_to_gds | # SKY130 Continuous Comparator with Complementary Input Load Layout Task
## Objective
Implement `sky130_ef_ip__ccomp3v_cl` from the supplied transistor-level circuit, preserving topology, fixed device parameters, four-terminal body connections and the ordered interface. Submit a candidate GDS for electrical evaluatio... | tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/case.toml | b8a2bb4391815224953974a251c255ca7a498053175c333f826f35d22cddeea9 | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/problem.md | tasks/sky130A/sky130_ef_ip__ccomp3v/cases/ccomp3v/materials/circuit.spice | 7fd17ed297a1e263a2169ee7965be2d7dcb5adfb9efc97ec1d62a17f9d9d59c5 | tasks/sky130A/sky130_ef_ip__ccomp3v/LICENSE |
sky130A.sky130_ef_ip__opamp.opamp | false | SKY130 3.3 V Rail-to-Rail Operational Amplifier | sky130A | null | Amplifiers & RF | Amplifies differential inputs with a 3.3 V rail-to-rail operational amplifier under the declared capacitive loads. | https://github.com/efabless/sky130_ef_ip__opamp/tree/f0eb5cd47112d90fd6d7792ba68e763beacac8e7 | qualified | sky130_ef_ip__opamp | netlist_to_gds | # SKY130 3.3 V Operational Amplifier Layout Task
## Objective
Implement `sky130_ef_ip__opamp` from the supplied transistor-level circuit, preserving topology, fixed device parameters, four-terminal body connections and the ordered interface. Submit a candidate GDS for electrical evaluation of its distributed RC extra... | tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/case.toml | 2349e7c575fde891c4bf0d5ea500133a6c7eee1a992a025bbed26272af428ca7 | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/problem.md | tasks/sky130A/sky130_ef_ip__opamp/cases/opamp/materials/circuit.spice | 12b9a110d6e630c1d51f61891154997f19672dce63c6d65883c740d4ae67882a | tasks/sky130A/sky130_ef_ip__opamp/LICENSE |
sky130A.sky130_ef_ip__rdac3v_8bit.rdac3v_8bit | true | SKY130 8-Bit Buffered Resistor DAC | sky130A | 1 | Mixed-signal | Converts all 256 digital codes to buffered analog voltages within the characterized reference interval. | https://github.com/efabless/sky130_ef_ip__rdac3v_8bit/tree/51a71b1af27fbb5e328536fa7c55e97698676015 | qualified | sky130_ef_ip__rdac3v_8bit | netlist_to_gds | # SKY130 Eight-Bit Buffered Resistor DAC Layout Task
## Objective
Implement `sky130_ef_ip__rdac3v_8bit` from the supplied transistor-level circuit, preserving topology, fixed device parameters, four-terminal body connections and the ordered interface. Submit a candidate GDS for electrical evaluation of its distribute... | tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/case.toml | 5547831c4885f92c64402a465eebd0cdb815cdf4b0d868a898bb8042011ceb66 | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/problem.md | tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/materials/circuit.spice | 1b3ee3925d5039310ed0b43b71db844f42f701245c81f6b90094a60e1b6d03e5 | tasks/sky130A/sky130_ef_ip__rdac3v_8bit/LICENSE |
sky130A.sky130_ef_ip__samplehold.samplehold | true | SKY130 Buffered Sample and Hold | sky130A | 7 | Mixed-signal | Tracks, holds and reacquires an analog input using a buffered sample-and-hold circuit. | https://github.com/efabless/sky130_ef_ip__samplehold/tree/5d5c1e9e172c4afc1a48adc3fe18fbe62642ca39 | qualified | sky130_ef_ip__samplehold | netlist_to_gds | # SKY130 Buffered Sample-and-Hold Layout Task
## Objective
Implement the supplied transistor-level buffered sample-and-hold in SKY130A, preserving topology, device parameters, body connections and ordered ports; perform acquisition in both directions, hold during input reversal, and reacquisition.
## Inputs and Inte... | tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/case.toml | 2e046267838ee72cbfb4f5242a709caa72d80fe5212d0ee93cd1d474d130c4db | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/problem.md | tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/materials/circuit.spice | a21526db3ce690a5ba08ef84f7af7a3679523c79024654357708880e0801f8cb | tasks/sky130A/sky130_ef_ip__samplehold/LICENSE |
sky130A.sky130_ef_ip__simple_por.simple_por | true | SKY130 Dual-Supply Power-On Reset | sky130A | 13 | Power & references | Generates reset outputs during staggered dual-supply startup and releases them after the supply ramps. | https://github.com/efabless/sky130_ef_ip__simple_por/tree/d8a9581533238bdb99cb0389fd4387587969dc12 | qualified | sky130_ef_ip__simple_por | netlist_to_gds | # SKY130 Dual-Supply Power-On Reset Layout Task
## Objective
Implement `sky130_ef_ip__simple_por` from the supplied transistor-level circuit, preserving topology, fixed device parameters, four-terminal body connections and the ordered interface. Submit a candidate GDS for electrical evaluation of its distributed RC e... | tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/case.toml | 9ded45c869910e10b3dd64eb26acbf79a4db64e54fa43a9bb56b749c2096454a | tasks/sky130A/pdk.toml | a016e7b0ef729a996a358f0ad6d62609f1a1f8cb26d354d26505f8eb23009d8f | tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/problem.md | tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/materials/circuit.spice | f90ab6095d6c49a8009519251c598c9ed91da9a69c08b0b55f6ed0bf14780bda | tasks/sky130A/sky130_ef_ip__simple_por/LICENSE |
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