target:
object ConfMuxMain extends App {
  println("Generating the hardware")
  (new chisel3.stage.ChiselStage).emitVerilog(new ConfMux(2, 1), Array("--target-dir", "generated"))
}


target:
  extends BlackBox(Map("dataWidth" -> dataWidth, "fifoDepth" -> fifoDepth)) with HasBlackBoxResource{
  val io = IO(new Bundle {


target_type: block

target:
  when (io.doutReady === true.B) {
    data := io.din
    valid := io.dinValid
  }


target:
object FsMain extends App {
    println("Generating the hardware")
    (new chisel3.stage.ChiselStage).emitVerilog(new Fs(5), Array("--target-dir", "generated"))
}


target:
object JoinMain extends App {
  println("Generating the hardware")
  (new chisel3.stage.ChiselStage).emitVerilog(new Join(32), Array("--target-dir", "generated"))
}


target:
  when (io.cellConfig(191) === 1.U){
    catchConfig(unsignedCellConfig) := 1.B
  }


target:
        for (i <- 1 until numOfTests) {
          dut.io.din1.poke((-(i*2)).S)
          dut.io.din2.poke(i.S)
          dut.clock.step(1)
        }


target:
      dut.io.eastDinValid.poke(eastDinValid)

      dut.io.southDin.poke(southDin)
      dut.io.southDinValid.poke(southDinValid)


target:
      dut.clock.step(1)
      selector = 2
      muxInput = 53


target:
          println("An: " + dut.io.doutReady.peek().toString)
          dut.clock.step(1)
          dut.clock.step(1)
          dut.io.dinValid.poke(false.B)
          dut.clock.step(1)


target:
                dut.io.din.poke(i.S)
                dut.io.dinValid.poke(true.B)


target:
            var doutReady = false.B
            var dinValid = false.B


target:
            var validIn = "b11011".U
            var readyOut = "b11011".U
            var validMuxSel = "b10".U
            var forkMask = "b11011".U


target:
            dut.io.readyOut.poke("b00000".U)
            dut.io.forkMask.poke("b00000".U)


target:
      dut.io.dataOutReady.poke(dataOutReady)
      dut.clock.step(1)

      var cellConfig: UInt = 0.U


target:
      for( i <- 0 to 10){
        dut.clock.step(1)
      }


target: when(isOne) { state := State.sTwo1s }.otherwise { state := State.sNone }


target: when(io.loadValues) { x := io.a; y := io.b }


target:
          fsm.clock.step(10)
          fsm.io.inputState.poke(MyFSMStates.StateA)
          fsm.clock.step(10)


target: class Generated_0_7_d3p7qsW3_29 extends BitsEl(64.W)


target: def generated_0_7_Tc5SbYQz_27 = UInt(64.W)


target: def getTopModuleName: Option[String] = topModuleName.name


target: def getFirtoolArgs:       Seq[String] = _firtoolArgs


target:
      settings: Seq[SimulatorSettings] = Seq(),
      simName:  String = "defaultSimulation",
  )(body: T => Unit): Unit = {
    if (_resetSimulationBeforeRun)
      reset()


target: private[simulator] case class FirtoolArgs(args: Seq[String]) extends SimulatorSettings


target:
      if (exitCode != 0)
        throw new Exception(s"$program not found on the PATH! Please install it running: make all\n")
    }


target: private[simulator] case class Tywaves(runWaves: Boolean, waitFor: Boolean) extends SimulatorSettings


target:
    this.foreach { case (key, value) =>
      bw.write(s"$key: $value\n")
    }
    bw.close()
  }


target:
  val cable =
    Wire(Bool()) // do not use reserved verilog words as val names (val wire) -> tywaves-demo does not work for them yet
  cable := io.a & io.b


target:
    simulate(new Foo, Seq(VcdTraceWithUnderscore), simName = "trace_with_underscore") {
      println("Running test: " + it)
      RunFoo(_)
    }


target:
        gcd.io.a.poke(24.U)
        gcd.io.b.poke(36.U)


target:
  when(io.enable) {
    when(cnt.inc() && cnt.value === (period - 1).U) {
      ledReg := ~ledReg
    }
  }


target:
        simName = "blink_with_tywaves_sim_should_work",
      ) { dut =>
        blinkTb(dut)
      }


target:
    ChiselStage.emitSystemVerilog(
      new AMultiBlink,
      firtoolOpts = Array(
        "-O=debug",
        "-g",


target:
    dut.clock.step() // 5
    dut.clock.step() // 6
    dut.clock.step()


target:
  val wrAddr = Input(UInt(log2Ceil(depth).W))
}


target: object SelType extends ChiselEnum { val A, B, C = Value }


target:
  describe("Issue 27") {
    it("Should import chisel before tywaves") {
      import chisel3._
      import tywaves.simulator.TywavesSimulator._


target:
    it("save the workdir with a name") {
      simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile("myWorkdir")))(gcd => gcdTb(gcd))
      assert(Files.exists(Paths.get("test_run_dir/GCD/ParametricSimulator/defaultSimulation/myWorkdir")))
    }


target:
      simulate(new GCD(), Seq(VcdTrace, NameTrace("gcdTb1")), simName = "use_a_name_for_the_simulation")(gcd =>
        gcdTb(gcd)
      )
      assert(Files.exists(Paths.get("test_run_dir/GCD/TywavesSimulator/use_a_name_for_the_simulation/gcdTb1.vcd")))


target:
    ramMasterRegs(ramId).Cmd := RegNext(Mux(ramId.U === wrRamIdReg && ocpSelRam, OcpCmd.WR, Mux(ocpRamRdEn, OcpCmd.RD, OcpCmd.IDLE)))
    ramMasterRegs(ramId).Data := RegNext(ethByteReg)


target:
      }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoEmpty")("Addr")) {
        ocpDataReg := ethTxCtrlRegMap("fifoEmpty")("Reg")
      }.elsewhen(ocpMasterReg.Addr(5, 0) === ethTxCtrlRegMap("fifoFull")("Addr")) {


target:
  when(~transmittingReg && serializeByteToNibble.io.dv) {
    transmittingReg := true.B
  }.elsewhen(~serializeByteToNibble.io.dv && serializeByteToNibble.io.done) {


target:
  val clk = Bool(INPUT)
  /** Received data valid */


target:
  /** Management input data */
  val mdi = Bool(INPUT)


target: val constVLANt1 = Bits("h8100", width = 16)


target: def ethTypeNibbles: Array[Int] = EthernetUtils.dataBytesToNibbles(ethType, msbFirst = false)


target: def toBytes(xs: Int*) = xs.map(_.toByte).toArray


target:
    } else {
      shiftReg(outputWidth - inputWidth - 1, 0) := shiftReg(outputWidth - 1, inputWidth)
      shiftReg(outputWidth - 1, outputWidth - inputWidth) := io.shiftIn


target:
  if (sampleRisingEdge) {
    extClkEdge := extClkSyncedReg & ~extClkSyncedOldReg //check for a rising edge
  } else {
    extClkEdge := ~extClkSyncedReg & extClkSyncedOldReg //or check for a falling edge


target:
    }.otherwise {
      countReg := countReg - 1.U
      doneReg := false.B
    }
  }.elsewhen(doneReg) {


target:
        stateReg := sWrite
        burstCntReg := UInt(0)


target:
  def slotTable(i: Int): UInt = {
    (cntReg === UInt(i * slotLen)).toUInt
  }


target:
    for (i <- 0 until master.burstLength - 1) {
      MBuffer(i) := MBuffer(i + 1)
    }
    MBuffer(master.burstLength - 1) := master.M
  }


target:
class OcpCacheSlavePort(addrWidth: Int, dataWidth: Int) extends Bundle() {
  // Clk is implicit in Chisel
  val M = new OcpCacheMasterSignals(addrWidth, dataWidth).asInput
  val S = new OcpSlaveSignals(dataWidth).asOutput
}


target:
  // This does not really clone, but Data.clone doesn't either
  override def clone() = {
    val res = new OcpCoreMasterPort(addrWidth, dataWidth)
    res.asInstanceOf[this.type]


target:
  when(masterReg.Cmd === OcpCmd.IDLE || slave.S.CmdAccept === Bits(1)) {
    masterReg := master.M
  }


target:
  // This does not really clone, but Data.clone doesn't either
  override def clone() = {
    val res = new OcpNISlaveSignals(dataWidth)


target:
  when(cnt =/= UInt(0)) {
    cnt := cnt - UInt(1)
    io.S.Resp := OcpResp.DVA
  }


target:
      when(io.slave.S.Resp === OcpResp.DVA) {
        stateReg(i) := sIdle
      }


target:
    val master = Vec.fill(cnt) {
      new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)
    }


target:
    for (nibble <- frame.dstMacNibbles ++ frame.srcMacNibbles ++ frame.ethTypeNibbles) {
      txPHY2MIIData(nibble, 6)
      peekEthRxStatus()
    }


target:
      if (byteCnt == 8) {
        byteCnt = 1
        ocpAddr += 0x1
      } else {


target:
  poke(dut.io.miiChannel.dv, 0)
  step(3)


target:
      () => Module(new MIITx())) {
      dut => new MIITxTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)
    }
  } finally {


target:
    override val ptpSuffix: Array[Byte] = Array.emptyByteArray
    override val fcs: Array[Byte] = Array.emptyByteArray
    override val igp: Array[Byte] = Array.emptyByteArray


target:
    peek(dut.io.shiftOut)
    peek(dut.io.done)
    step(1)


target:
      () => Module(new Serializer(false, 8, 4))) {
      dut => new SerializerTester(dut, EthernetTesting.mockupPTPEthFrameOverIpUDP)
    }


target: val shamt = (if (bitWidth == 32) 5 else if (bitWidth == 64) 6 else 0) - 1


target:
  when(counterWrap) {
    led := ~led
  }


target:
    when(decoder.io.inst === LW) {
      dataSize := 3.U
      dataOut  := memoryIOManager.io.MemoryIOPort.readData
    }


target:
object InstructionType extends ChiselEnum {
  val IN_ERR, INST_R, INST_I, INST_S, INST_B, INST_U, INST_J, INST_Z = Value
}


target: if (debugMsg) println(s"  Load memory file: " + memoryFile)


target:
    case INST_R => 0.S
    case INST_I => Cat(Fill(20, inst(31)), inst(31, 20)).asSInt
    case INST_S => Cat(Fill(20, inst(31)), inst(31, 25), inst(11, 7)).asSInt
    case INST_B => Cat(Fill(19, inst(31)), inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt


target: |  output  [${numGPIO - 1}:0] dataOut,


target:
  if (memoryFile.trim().nonEmpty) {
    loadMemoryFromFileInline(mem, memoryFile)
  }


target:
          }
          is(2.U) { // Write halfword
            switch(io.DataMemPort.writeAddress(1).asUInt) {
              is(1.U) { // Write half word 1
                dataToWrite := Cat(io.MemoryIOPort.writeData(15, 0).asUInt, Fill(16, 0.U))


target:
    val lock = Output(Clock())
  })

  val filename = "pll_" + board + ".v"
  val verilog  = Source.fromResource(filename).getLines().mkString("\n")


target:
  val PC          = Output(UInt(bitWidth.W))
  val PC4         = Output(UInt(bitWidth.W))


target:
  val regwr_addr  = Input(UInt(log2Ceil(bitWidth).W))
  val regwr_data  = Input(UInt(bitWidth.W))


target:
  if (numGPIO > 0) {
    core.io.GPIO0External <> io.GPIO0External
  }


target:
class SysconPort(val bitWidth: Int) extends Bundle {
  val Address = Input(UInt(12.W))
  val DataOut = Output(UInt(bitWidth.W))
}


target:
    when(counterWrap) {
      counter := counter + 1.U
    }


target: val customReset = if (invReset) ~reset.asBool else reset


target:
          when(rx === 1.U) {
            /* We might overflow the queue if we can't keep up */
            rxQueue.io.enq.bits  := rxByte.reverse.reduce(_ ## _)
            rxQueue.io.enq.valid := true.B
            rxState              := sRxIdle


target: case GTE          => if (a.toInt >= b.toInt) 1 else 0


target:
    defaultDut(filename) { c =>
      c.clock.setTimeout(3000)
      c.clock.step(2000)
    }


target:
      c.clock.step(1 + writeLatency) // sw
      // Check Memory read at address 0x80000000


target:
      c.registers(3).peekInt() should be(0)
      c.clock.step(1)      // bne
      c.clock.step(2 * ms) // wait 2ms
      c.timerCounter.peekInt() should be(2)
      c.registers(3).peekInt() should be(2)


target:
      jal x1, +8
      nop
      jalr x2, x1, +2044
      """
    defaultDut(prog) { c =>


target:
    test(new Decoder) { c =>
      c.io.op.poke(makeBin("lbu x1, 16(x2)"))
      c.clock.step()


target:
    )

  it should "read GPIO output and direction as 0 when initialized" in {


target:
      addresses.foreach { address =>
        values.foreach { value =>
          c.io.writeEnable.poke(true)
          c.io.writeAddress.poke(addressOffset + address)
          c.io.readAddress.poke(addressOffset + address)


target:
    test(new RegisterBank) { c =>
      c.io.rs1_addr.poke(0.U)
      c.io.rs1.expect(0.U)
    }


target:
      c.clock.step()
      c.io.DataOut.peekInt() should be(1)
    }
  }


target:
      c.io.dataOut.peekInt() should be(0)
      c.obs_counter.peekInt() should be(0)
      c.clock.step(ms)
      c.io.dataOut.peekInt() should be(1)


target: def clockSerial(clk: Clock) = clk.step(fpgaClock / baudRate)