diff --git a/testbench/UTOSS_risc-v_pr70/open_tool_p2p_buggy.log b/testbench/UTOSS_risc-v_pr70/open_tool_p2p_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..9432c845a84cc99ee6b5d027872511f1c14977eb --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/open_tool_p2p_buggy.log @@ -0,0 +1,14 @@ +INFO: open-tool P2P fallback (buggy) + +### native_sim:. +'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd' +Starting Register File Testbench... +VCD info: dumpfile test/vcd/rf_tb.vcd opened for output. +PASS: current baseAddr output: deadbeef; expected baseAddr output: DEADBEEF +PASS: current writeData output: cafebabe; expected writeData output: CAFEBABE +PASS: Write to register 15 verified. current reg 15 output: 12345678; expected reg 15 output: 12345678 +PASS: Write to register 0 verified. current reg 0 output: 00000000; expected reg 0 output: 0 +test/rf_tb.sv:85: $finish called at 36000 (1ps) + +rc=0 +PASS: native simulation P2P passed in buggy phase: .: 'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd' diff --git a/testbench/UTOSS_risc-v_pr70/open_tool_p2p_fixed.log b/testbench/UTOSS_risc-v_pr70/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..6309a9ba457a8892e4b91e1b302f20374578d4db --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/open_tool_p2p_fixed.log @@ -0,0 +1,14 @@ +INFO: open-tool P2P fallback (fixed) + +### native_sim:. +'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd' +Starting Register File Testbench... +VCD info: dumpfile test/vcd/rf_tb.vcd opened for output. +PASS: current baseAddr output: deadbeef; expected baseAddr output: DEADBEEF +PASS: current writeData output: cafebabe; expected writeData output: CAFEBABE +PASS: Write to register 15 verified. current reg 15 output: 12345678; expected reg 15 output: 12345678 +PASS: Write to register 0 verified. current reg 0 output: 00000000; expected reg 0 output: 0 +test/rf_tb.sv:85: $finish called at 36000 (1ps) + +rc=0 +PASS: native simulation P2P passed in fixed phase: .: 'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd' diff --git a/testbench/UTOSS_risc-v_pr70/repo_native_buggy.log b/testbench/UTOSS_risc-v_pr70/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..c61acad1f1d2e734dcaeb2f248b09961f3a8cf31 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native simulation P2P passed in buggy phase diff --git a/testbench/UTOSS_risc-v_pr70/repo_native_fixed.log b/testbench/UTOSS_risc-v_pr70/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..42f62110d2607f14cf2880fadd28f9bf6830b416 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native simulation P2P passed in fixed phase diff --git a/testbench/UTOSS_risc-v_pr70/repo_native_source.path b/testbench/UTOSS_risc-v_pr70/repo_native_source.path new file mode 100644 index 0000000000000000000000000000000000000000..9ae9729469ce1ca7ba51e63e1b8f2cfe1334f9de --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/repo_native_source.path @@ -0,0 +1 @@ +test/alu_branchifeq_tb.sv diff --git a/testbench/UTOSS_risc-v_pr70/run_once.sh b/testbench/UTOSS_risc-v_pr70/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/UTOSS_risc-v_pr70/run_verilator.sh b/testbench/UTOSS_risc-v_pr70/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..c8e92bb72ade23d79da17c47acbb543f797b2062 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/run_verilator.sh @@ -0,0 +1,78 @@ +#!/bin/bash +set -u + +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +cd "$HERE" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 + +NAME="UTOSS_risc-v_pr70" +DATA_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$DATA_ROOT/snapshots/$NAME" +PATCH_FILE="$DATA_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +PATCH_TARGETS=( + "$SCRATCH/src/Instruction_Decode/Instruction_Decode.v" + "$SCRATCH/src/Instruction_Decode/RegisterFile.v" + "$SCRATCH/src/fetch.sv" + "$SCRATCH/test/nop_tb.sv" +) + +run_phase() { + local tag="$1" + + rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log" + run_repo_native_p2p_smoke "$tag" || return $? + + verilator --binary --timing --assert \ + --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL \ + --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING \ + --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-ASSIGNIN --Wno-ENUMVALUE \ + --timescale 1ns/1ps \ + -I"$SCRATCH" -I"$SCRATCH/src" -I"$SCRATCH/test" \ + "$SCRATCH/src/top.v" \ + "$SCRATCH/src/ControlFSM.sv" \ + "$SCRATCH/src/fetch.sv" \ + "$SCRATCH/src/utils/MA.v" \ + "$SCRATCH/src/Instruction_Decode/Instruction_Decode.v" \ + "$SCRATCH/src/Instruction_Decode/RegisterFile.v" \ + "$SCRATCH/src/ALU_ALUdecoder/ALU.v" \ + "$SCRATCH/src/ALU_ALUdecoder/ALUdecoder.v" \ + "$HERE/tb_utoss_riscv_pr70_verilator.sv" \ + --top-module tb_utoss_riscv_pr70_verilator \ + -o simv_vlt 2>&1 | tee "verilator_${tag}_build.log" >/dev/null + + [ ! -x obj_dir/simv_vlt ] && return 2 + + timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null + grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" && \ + ! grep -qE '(^|[^A-Za-z])(FAIL:|\\$fatal|Aborting\\.\\.\\.)' "verilator_${tag}.log" +} + +rm -rf "$SCRATCH" +cp -r "$SNAPSHOT" "$SCRATCH" +chmod -R u+w "$SCRATCH" +echo BUGGY +(cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase buggy +rc_buggy=$? + +rm -rf "$SCRATCH" +cp -r "$SNAPSHOT" "$SCRATCH" +chmod -R u+w "$SCRATCH" +echo FIXED +(cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase fixed +rc_fixed=$? + +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { + hwe_report_min_testcases + hwe_report_real_verilator_coverage + echo "PASS: $NAME" + exit 0 +} || { + echo "FAIL: $NAME" + exit 1 +} diff --git a/testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv b/testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv new file mode 100644 index 0000000000000000000000000000000000000000..a72c1a8179eb25baf430313d792874267ed9beb8 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv @@ -0,0 +1,84 @@ +`timescale 1ns/1ps + +`include "test/utils.svh" + +module tb_utoss_riscv_pr70_verilator; + reg clk; + reg reset; + + top uut ( .clk(clk), .reset(reset) ); + + task wait_till_next_cfsm_state(input [5:0] expected_state); + @(posedge clk); #1; + `assert_equal(expected_state, uut.control_fsm.current_state) + endtask + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + reset <= `TRUE; + + uut.memory.M[0] = 32'h00000013; // nop = addi x0, x0, 0 + // 2nd instruction (coverage stimulus): beq x0, x0, 8 -> always taken since + // x0 == x0, so the branch FSM selects PC_SRC__JUMP and the fetch unit + // evaluates pc_next = pc_cur + imm_ext (fetch.sv line 26). + uut.memory.M[1] = 32'h00000463; // beq x0, x0, 8 + uut.instruction_decode.instanceRegFile.RFMem[0] = 32'h01010101; + uut.instruction_decode.instanceRegFile.RFMem[1] = 32'h0000000A; + uut.instruction_decode.instanceRegFile.RFMem[2] = 32'h00000014; + + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + reset <= `FALSE; + + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + `assert_equal(7'b0010011, uut.opcode) + `assert_equal(0, uut.instruction_decode.rs1) + `assert_equal(0, uut.instruction_decode.rd) + `assert_equal(0, uut.instruction_decode.imm_ext) + + wait_till_next_cfsm_state(uut.control_fsm.EXECUTEI); + `assert_equal(32'h0, uut.alu.a) + `assert_equal(32'h0, uut.alu.b) + `assert_equal(32'h0, uut.alu.out) + if (uut.alu.a !== 32'h0 || uut.alu.b !== 32'h0 || uut.alu.out !== 32'h0) begin + $display("FAIL: NOP used nonzero x0 operand/result a=%08h b=%08h out=%08h", + uut.alu.a, uut.alu.b, uut.alu.out); + $fatal(1); + end + + wait_till_next_cfsm_state(uut.control_fsm.ALUWB); + wait_till_next_cfsm_state(uut.control_fsm.FETCH); + + `assert_equal(32'h0, uut.instruction_decode.instanceRegFile.RFMem[0]) + `assert_equal(4, uut.fetch.pc_cur) + if (uut.instruction_decode.instanceRegFile.RFMem[0] !== 32'h0 || + uut.fetch.pc_cur !== 32'h4) begin + $display("FAIL: post-NOP state x0=%08h pc=%08h", + uut.instruction_decode.instanceRegFile.RFMem[0], uut.fetch.pc_cur); + $fatal(1); + end + + // Coverage stimulus: walk the taken branch through DECODE -> BRANCHIFEQ so + // the fetch unit computes the jump target (pc_cur + imm_ext). No new asserts. + wait_till_next_cfsm_state(uut.control_fsm.DECODE); + wait_till_next_cfsm_state(uut.control_fsm.BRANCHIFEQ); + @(posedge clk); #1; // settle: PCUpdate + PC_SRC__JUMP drive pc_next + + // Coverage stimulus: present an R-type "add x3, x1, x2" to the decoder so + // the register file reads nonzero source addresses (rs1=1, rs2=2). This + // exercises the (Addr1!=0)/(Addr2!=0) sides of the baseAddr/writeData + // ternaries (the existing flow only ever reads x0). RFMem[1]/RFMem[2] are + // preloaded above. No new assertions are added. + uut.instruction = 32'h002081B3; // add x3, x1, x2 + #1; // combinational settle of rs1/rs2 -> Addr1/Addr2 -> baseAddr/writeData + @(posedge clk); #1; + + $display("PASS: UTOSS_risc-v_pr70 x0 stays hard-wired to zero"); + $finish; + end + + `SETUP_VCD_DUMP(tb_utoss_riscv_pr70_verilator) +endmodule diff --git a/testbench/UTOSS_risc-v_pr70/verilator_buggy.log b/testbench/UTOSS_risc-v_pr70/verilator_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..64de8788c6464fcb7302a0fd03f3d68c134133f0 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/verilator_buggy.log @@ -0,0 +1,3 @@ +[26000] %Fatal: tb_utoss_riscv_pr70_verilator.sv:43: Assertion failed in TOP.tb_utoss_riscv_pr70_verilator: Expected `0`, got `1010101` +%Error: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:43: Verilog $stop +Aborting... diff --git a/testbench/UTOSS_risc-v_pr70/verilator_buggy_build.log b/testbench/UTOSS_risc-v_pr70/verilator_buggy_build.log new file mode 100644 index 0000000000000000000000000000000000000000..39f3a51e286a7c6606caea429e145b087ca732f1 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/verilator_buggy_build.log @@ -0,0 +1,245 @@ +%Warning-CASEINCOMPLETE: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/Instruction_Decode/Instruction_Decode.v:123:3: Case values incompletely covered (example pattern 0x0) + 123 | case(opcode) + | ^~~~ + ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=5.047 + ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. +%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:22:11: Non-blocking assignment '<=' in initial/final block + : ... This will be executed as a blocking assignment '='! + 22 | reset <= 1'b1; + | ^~ + ... For warning description see https://verilator.org/warn/INITIALDLY?v=5.047 + ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. +%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:34:11: Non-blocking assignment '<=' in initial/final block + : ... This will be executed as a blocking assignment '='! + 34 | reset <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:114:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 114 | Branch <= 1'b0; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=5.047 + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY?v=5.047 before disabling this, + else you may end up with different sim results. +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:115:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 115 | pc_src <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:116:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 116 | PCUpdate <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:117:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 117 | IRWrite <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:118:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 118 | MemWrite <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:120:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 120 | FSMState <= current_state; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:233:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 233 | AdrSrc <= ADR_SRC__PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:234:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 234 | IRWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:142:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 142 | ALUSrcA <= ALU_SRC_A__OLD_PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:143:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 143 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:144:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 144 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:150:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 150 | ALUSrcA <= ALU_SRC_A__ZERO; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:151:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 151 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:152:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 152 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:192:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 192 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:193:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 193 | ALUSrcB <= ALU_SRC_B__RD2; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:194:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 194 | ALUOp <= 2'b01; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:195:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 195 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:196:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 196 | Branch <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:197:16: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 197 | pc_src <= zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:198:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 198 | PCUpdate <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:226:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 226 | ResultSrc <= RESULT_SRC__DATA; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:227:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 227 | RegWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:219:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 219 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:220:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 220 | AdrSrc <= ADR_SRC__RESULT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:211:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 211 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:212:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 212 | AdrSrc <= ADR_SRC__RESULT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:213:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 213 | MemWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:204:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 204 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:205:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 205 | RegWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:184:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 184 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:185:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 185 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:186:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 186 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:166:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 166 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:167:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 167 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:168:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 168 | ALUOp <= 2'b11; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:174:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 174 | ALUSrcA <= ALU_SRC_A__OLD_PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:175:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 175 | ALUSrcB <= ALU_SRC_B__4; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:176:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 176 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:177:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 177 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:178:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 178 | PCUpdate <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:158:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 158 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:159:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 159 | ALUSrcB <= ALU_SRC_B__RD2; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:160:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 160 | ALUOp <= 2'b10; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:134:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 134 | ALUSrcA <= ALU_SRC_A__OLD_PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:135:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 135 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:136:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 136 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:126:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 126 | AdrSrc <= ADR_SRC__PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:127:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 127 | IRWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:128:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 128 | PCUpdate <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:26:36: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 26 | PC_SRC__JUMP: pc_next <= pc_cur + imm_ext; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:25:36: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 25 | PC_SRC__INCREMENT: pc_next <= pc_cur + 32'h4; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:29:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 29 | pc_next <= pc_cur; + | ^~ +make: Entering directory 'testbench/UTOSS_risc-v_pr70/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/UTOSS_risc-v_pr70/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top___024unit__Slow.cpp Vhwe_cov_top___024unit__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/UTOSS_risc-v_pr70/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.501 MB sources in 11 modules, into 0.367 MB in 7 C++ files needing 0.000 MB +- Verilator: Walltime 8.408 s (elab=0.002, cvt=0.018, bld=8.378); cpu 0.030 s on 1 threads; allocated 22.891 MB diff --git a/testbench/UTOSS_risc-v_pr70/verilator_fixed.log b/testbench/UTOSS_risc-v_pr70/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..13f92ae70620d3ab71a27b2e6b96a86fa3ffe330 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/verilator_fixed.log @@ -0,0 +1,2 @@ +PASS: UTOSS_risc-v_pr70 x0 stays hard-wired to zero +- testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:80: Verilog $finish diff --git a/testbench/UTOSS_risc-v_pr70/verilator_fixed_build.log b/testbench/UTOSS_risc-v_pr70/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..57900f91c1232b9269ce9c9cd39fd8c5585d4ac5 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/verilator_fixed_build.log @@ -0,0 +1,245 @@ +%Warning-CASEINCOMPLETE: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/Instruction_Decode/Instruction_Decode.v:123:3: Case values incompletely covered (example pattern 0x0) + 123 | case(opcode) + | ^~~~ + ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=5.047 + ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. +%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:22:11: Non-blocking assignment '<=' in initial/final block + : ... This will be executed as a blocking assignment '='! + 22 | reset <= 1'b1; + | ^~ + ... For warning description see https://verilator.org/warn/INITIALDLY?v=5.047 + ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. +%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:34:11: Non-blocking assignment '<=' in initial/final block + : ... This will be executed as a blocking assignment '='! + 34 | reset <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:114:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 114 | Branch <= 1'b0; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=5.047 + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY?v=5.047 before disabling this, + else you may end up with different sim results. +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:115:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 115 | pc_src <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:116:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 116 | PCUpdate <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:117:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 117 | IRWrite <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:118:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 118 | MemWrite <= 1'b0; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:120:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 120 | FSMState <= current_state; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:233:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 233 | AdrSrc <= ADR_SRC__PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:234:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 234 | IRWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:142:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 142 | ALUSrcA <= ALU_SRC_A__OLD_PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:143:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 143 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:144:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 144 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:150:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 150 | ALUSrcA <= ALU_SRC_A__ZERO; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:151:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 151 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:152:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 152 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:192:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 192 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:193:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 193 | ALUSrcB <= ALU_SRC_B__RD2; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:194:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 194 | ALUOp <= 2'b01; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:195:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 195 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:196:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 196 | Branch <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:197:16: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 197 | pc_src <= zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:198:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 198 | PCUpdate <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:226:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 226 | ResultSrc <= RESULT_SRC__DATA; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:227:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 227 | RegWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:219:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 219 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:220:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 220 | AdrSrc <= ADR_SRC__RESULT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:211:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 211 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:212:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 212 | AdrSrc <= ADR_SRC__RESULT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:213:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 213 | MemWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:204:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 204 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:205:14: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 205 | RegWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:184:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 184 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:185:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 185 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:186:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 186 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:166:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 166 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:167:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 167 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:168:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 168 | ALUOp <= 2'b11; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:174:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 174 | ALUSrcA <= ALU_SRC_A__OLD_PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:175:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 175 | ALUSrcB <= ALU_SRC_B__4; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:176:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 176 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:177:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 177 | ResultSrc <= RESULT_SRC__ALU_OUT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:178:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 178 | PCUpdate <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:158:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 158 | ALUSrcA <= ALU_SRC_A__RD1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:159:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 159 | ALUSrcB <= ALU_SRC_B__RD2; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:160:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 160 | ALUOp <= 2'b10; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:134:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 134 | ALUSrcA <= ALU_SRC_A__OLD_PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:135:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 135 | ALUSrcB <= ALU_SRC_B__IMM_EXT; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:136:11: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 136 | ALUOp <= 2'b00; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:126:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 126 | AdrSrc <= ADR_SRC__PC; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:127:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 127 | IRWrite <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:128:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 128 | PCUpdate <= 1'b1; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:26:37: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 26 | PC_SRC__JUMP: pc_next <= pc_cur + imm_ext; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:25:36: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 25 | PC_SRC__INCREMENT: pc_next <= pc_cur + 32'h4; + | ^~ +%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:29:15: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 29 | pc_next <= pc_cur; + | ^~ +make: Entering directory 'testbench/UTOSS_risc-v_pr70/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/UTOSS_risc-v_pr70/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top___024unit__Slow.cpp Vhwe_cov_top___024unit__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/UTOSS_risc-v_pr70/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.502 MB sources in 11 modules, into 0.370 MB in 7 C++ files needing 0.000 MB +- Verilator: Walltime 8.373 s (elab=0.002, cvt=0.018, bld=8.343); cpu 0.030 s on 1 threads; allocated 22.910 MB diff --git a/testbench/UTOSS_risc-v_pr70/verilator_fixed_coverage.info b/testbench/UTOSS_risc-v_pr70/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..e64c256edb4b0d4ef1c214f5ccf87011b5b183b1 --- /dev/null +++ b/testbench/UTOSS_risc-v_pr70/verilator_fixed_coverage.info @@ -0,0 +1,2943 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0x00000004: 0x0000a023 +ifetch 0x00000008: 0x0000a103 +write 0x000003fc: 0x00000000 (wstrb=1111) +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000000 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000001 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000001 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000002 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000002 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000003 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000003 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000004 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000004 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000005 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000005 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000006 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000006 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000007 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000007 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000008 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000008 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000009 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000009 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000a (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000a +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000b (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000b +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000c (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000c +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000d (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000d +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000e (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000e +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000f (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000f +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000010 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000010 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000011 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000011 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000012 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000012 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000013 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000013 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000014 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000014 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000015 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000015 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000016 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000016 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000017 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000017 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000018 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000018 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000019 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000019 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001a (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001a +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001b (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001b +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001c (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001c +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001d (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001d +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001e (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001e +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001f (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001f +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000020 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000020 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000021 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000021 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000022 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000022 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000023 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000023 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000024 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000024 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000025 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000025 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000026 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000026 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000027 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000027 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000028 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000028 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000029 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000029 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000002a (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000002a +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000002b (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000002b +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000002c (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000002c +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +testbench_ez.v:25: $finish called at 11000000 (1ps) + +rc=0 +PASS: native simulation P2P passed in buggy phase: .: 'make' 'test_ez' diff --git a/testbench/YosysHQ_picorv32_pr229/open_tool_p2p_fixed.log b/testbench/YosysHQ_picorv32_pr229/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..79138421d649454c6f35ec04c8a188066d2dd309 --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/open_tool_p2p_fixed.log @@ -0,0 +1,283 @@ +INFO: open-tool P2P fallback (fixed) + +### native_sim:. +'make' 'test_ez' +iverilog -o testbench_ez.vvp -DCOMPRESSED_ISA testbench_ez.v picorv32.v +chmod -x testbench_ez.vvp +vvp -N testbench_ez.vvp +ifetch 0x00000000: 0x3fc00093 +ifetch 0x00000004: 0x0000a023 +ifetch 0x00000008: 0x0000a103 +write 0x000003fc: 0x00000000 (wstrb=1111) +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000000 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000001 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000001 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000002 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000002 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000003 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000003 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000004 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000004 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000005 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000005 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000006 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000006 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000007 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000007 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000008 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000008 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000009 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000009 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000a (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000a +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000b (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000b +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000c (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000c +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000d (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000d +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000e (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000e +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000000f (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000000f +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000010 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000010 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000011 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000011 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000012 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000012 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000013 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000013 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000014 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000014 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000015 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000015 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000016 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000016 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000017 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000017 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000018 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000018 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000019 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000019 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001a (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001a +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001b (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001b +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001c (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001c +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001d (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001d +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001e (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001e +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000001f (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000001f +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000020 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000020 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000021 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000021 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000022 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000022 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000023 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000023 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000024 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000024 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000025 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000025 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000026 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000026 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000027 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000027 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000028 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000028 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x00000029 (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x00000029 +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000002a (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000002a +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000002b (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000002b +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +write 0x000003fc: 0x0000002c (wstrb=1111) +ifetch 0x00000008: 0x0000a103 +ifetch 0x0000000c: 0x00110113 +read 0x000003fc: 0x0000002c +ifetch 0x00000010: 0x0020a023 +ifetch 0x00000014: 0xff5ff06f +testbench_ez.v:25: $finish called at 11000000 (1ps) + +rc=0 +PASS: native simulation P2P passed in fixed phase: .: 'make' 'test_ez' diff --git a/testbench/YosysHQ_picorv32_pr229/repo_native_buggy.log b/testbench/YosysHQ_picorv32_pr229/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..c61acad1f1d2e734dcaeb2f248b09961f3a8cf31 --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native simulation P2P passed in buggy phase diff --git a/testbench/YosysHQ_picorv32_pr229/repo_native_fixed.log b/testbench/YosysHQ_picorv32_pr229/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..42f62110d2607f14cf2880fadd28f9bf6830b416 --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native simulation P2P passed in fixed phase diff --git a/testbench/YosysHQ_picorv32_pr229/run_once.sh b/testbench/YosysHQ_picorv32_pr229/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/YosysHQ_picorv32_pr229/run_verilator.sh b/testbench/YosysHQ_picorv32_pr229/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..288d3ae8c961e337b034e1ff264d8b805a8d625c --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/run_verilator.sh @@ -0,0 +1,30 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 +NAME=YosysHQ_picorv32_pr229 +REPO_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$REPO_ROOT/snapshots/$NAME" +PATCH_FILE="$REPO_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +TARGET="picorv32.v" +run_phase() { + local tag="$1" + rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log + run_repo_native_p2p_smoke "$tag" || return $? + verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --Wno-MULTIDRIVEN --Wno-CASEX --Wno-IMPLICIT --Wno-SELRANGE --timescale 1ns/1ps "$SCRATCH/$TARGET" "$HERE/tb_picorv32_fence_verilator.sv" --top-module tb_picorv32_fence_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null + [ ! -x obj_dir/simv_vlt ] && return 2 + timeout 30 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null + grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0 + return 1 +} +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase buggy; rc_buggy=$? +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase fixed; rc_fixed=$? +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; } diff --git a/testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv b/testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv new file mode 100644 index 0000000000000000000000000000000000000000..68fc4080ee5fa8c5c06bcdd10a55fc6c992c6aec --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv @@ -0,0 +1,104 @@ +// pr229: picorv32 gains an `instr_fence` decode. Pre-patch the signal does not +// exist; any hierarchical reference to dut.instr_fence makes elaboration fail. +// Post-patch the signal is present. The TB also drives a fence opcode through +// the instruction fetch path to confirm the decoder asserts instr_fence. +`timescale 1ns/1ps +module tb_picorv32_fence_verilator; + reg clk = 0; + reg resetn = 0; + wire trap; + + wire mem_valid; + wire mem_instr; + reg mem_ready = 0; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + reg [31:0] mem_rdata = 0; + + wire mem_la_read, mem_la_write; + wire [31:0] mem_la_addr; + wire [31:0] mem_la_wdata; + wire [ 3:0] mem_la_wstrb; + + wire pcpi_valid; + wire [31:0] pcpi_insn; + wire [31:0] pcpi_rs1, pcpi_rs2; + reg pcpi_wr = 0; + reg [31:0] pcpi_rd = 0; + reg pcpi_wait = 0; + reg pcpi_ready = 0; + + reg [31:0] irq = 0; + wire [31:0] eoi; + + wire trace_valid; + wire [35:0] trace_data; + + always #5 clk = ~clk; + + picorv32 #( + .ENABLE_COUNTERS(0), + .ENABLE_COUNTERS64(0), + .ENABLE_IRQ(0), + .ENABLE_PCPI(0) + ) dut ( + .clk(clk), .resetn(resetn), + .trap(trap), + .mem_valid(mem_valid), .mem_instr(mem_instr), .mem_ready(mem_ready), + .mem_addr(mem_addr), .mem_wdata(mem_wdata), .mem_wstrb(mem_wstrb), + .mem_rdata(mem_rdata), + .mem_la_read(mem_la_read), .mem_la_write(mem_la_write), + .mem_la_addr(mem_la_addr), .mem_la_wdata(mem_la_wdata), + .mem_la_wstrb(mem_la_wstrb), + .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), + .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), + .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), + .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), + .irq(irq), .eoi(eoi), + .trace_valid(trace_valid), .trace_data(trace_data) + ); + + // Serve instruction fetches with a FENCE opcode (opcode = 7'b0001111, funct3 = 0). + // Packed into 32 bits: funct3=0 at bits [14:12], opcode at bits [6:0]. + localparam [31:0] FENCE_INSTR = 32'h0000000F; + localparam [31:0] ADDI_INSTR = 32'h00000013; // nop + + // Simple memory model: serve FENCE once, then NOPs. + int fetch_count = 0; + always @(posedge clk) begin + if (mem_valid && !mem_ready) begin + mem_ready <= 1'b1; + if (mem_instr) begin + mem_rdata <= (fetch_count == 0) ? FENCE_INSTR : ADDI_INSTR; + fetch_count <= fetch_count + 1; + end else begin + mem_rdata <= 32'h0; + end + end else begin + mem_ready <= 1'b0; + end + end + + int fence_seen = 0; + // Observe internal decoded fence flag (requires the signal to exist => fixed). + always @(posedge clk) begin + if (resetn && dut.instr_fence) fence_seen <= 1; + end + + initial begin + resetn = 0; + repeat(5) @(posedge clk); + resetn = 1; + // Give the pipeline time to fetch, latch, and decode the FENCE. + repeat(40) @(posedge clk); + + if (fence_seen == 1) + $display("PASS: picorv32 decoded fence instruction"); + else + $display("FAIL: fence decode not observed (fence_seen=%0d)", fence_seen); + $finish; + end + + initial begin #10000; $display("FAIL: timeout"); $finish; end +endmodule diff --git a/testbench/YosysHQ_picorv32_pr229/verilator_buggy_build.log b/testbench/YosysHQ_picorv32_pr229/verilator_buggy_build.log new file mode 100644 index 0000000000000000000000000000000000000000..d75cb8602e322ea36a7e72d54fc7ad83fd2519fc --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/verilator_buggy_build.log @@ -0,0 +1,11 @@ +%Error: testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv:86:23: Can't find definition of 'instr_fence' in dotted variable/method: 'dut.instr_fence' + 86 | if (resetn && dut.instr_fence) fence_seen <= 1; + | ^~~~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. +%Error: Exiting due to 1 error(s) +HWE_AUTO_COVERAGE: retrying with --coverage-line +%Error: testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv:86:23: Can't find definition of 'instr_fence' in dotted variable/method: 'dut.instr_fence' + 86 | if (resetn && dut.instr_fence) fence_seen <= 1; + | ^~~~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. +%Error: Exiting due to 1 error(s) diff --git a/testbench/YosysHQ_picorv32_pr229/verilator_fixed.log b/testbench/YosysHQ_picorv32_pr229/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..ae9877e966bcd0580313555ddcf50c02014b98e6 --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/verilator_fixed.log @@ -0,0 +1,2 @@ +PASS: picorv32 decoded fence instruction +- testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv:100: Verilog $finish diff --git a/testbench/YosysHQ_picorv32_pr229/verilator_fixed_build.log b/testbench/YosysHQ_picorv32_pr229/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..a0bbd90cdcb226eecd49ed8c08de06def42d7f69 --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory 'testbench/YosysHQ_picorv32_pr229/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/YosysHQ_picorv32_pr229/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/YosysHQ_picorv32_pr229/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.279 MB sources in 10 modules, into 1.030 MB in 5 C++ files needing 0.001 MB +- Verilator: Walltime 9.778 s (elab=0.009, cvt=0.047, bld=9.702); cpu 0.076 s on 1 threads; allocated 26.441 MB diff --git a/testbench/YosysHQ_picorv32_pr229/verilator_fixed_coverage.info b/testbench/YosysHQ_picorv32_pr229/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..776610536cf25ec0e773aa5aee89543d561c12e5 --- /dev/null +++ b/testbench/YosysHQ_picorv32_pr229/verilator_fixed_coverage.info @@ -0,0 +1,8193 @@ +TN:verilator_coverage +SF:testbench/YosysHQ_picorv32_pr229/snapshot_scratch/picorv32.v +DA:90,45 +BRDA:90,0,0,1 +BRDA:90,0,1,0 +BRDA:90,0,2,45 +BRDA:90,0,3,44 +DA:91,0 +BRDA:91,0,0,0 +BRDA:91,0,1,0 +DA:93,10 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+BRDA:91,0,0,1 +BRDA:91,0,1,5 +DA:92,1 +DA:94,40 +BRDA:94,0,0,1 +BRDA:94,0,1,40 +DA:96,1 +BRDA:96,0,0,1 +BRDA:96,0,1,0 +DA:97,1 +DA:99,0 +DA:100,1 +DA:103,0 +BRF:853 +BRH:21 +end_of_record diff --git a/testbench/jotego_jtcores_pr1202/open_tool_p2p_fixed.log b/testbench/jotego_jtcores_pr1202/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..a6b957833cb4fc869e5023ed4d1da85dc5092d2f --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/open_tool_p2p_fixed.log @@ -0,0 +1,9 @@ +INFO: open-tool P2P fallback (fixed) + +### native_sim:modules/jtframe/ver/cen +'sh' '-c' 'PATH=.:$PATH bash sim.sh' +LXT info: dumpfile test.lxt opened for output. +test.v:45: $finish called at 2000000 (1ps) + +rc=0 +PASS: native simulation P2P passed in fixed phase: modules/jtframe/ver/cen: 'sh' '-c' 'PATH=.:$PATH bash sim.sh' diff --git a/testbench/jotego_jtcores_pr1202/repo_native_buggy.log b/testbench/jotego_jtcores_pr1202/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..c61acad1f1d2e734dcaeb2f248b09961f3a8cf31 --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native simulation P2P passed in buggy phase diff --git a/testbench/jotego_jtcores_pr1202/repo_native_fixed.log b/testbench/jotego_jtcores_pr1202/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..42f62110d2607f14cf2880fadd28f9bf6830b416 --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native simulation P2P passed in fixed phase diff --git a/testbench/jotego_jtcores_pr1202/run_once.sh b/testbench/jotego_jtcores_pr1202/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv b/testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv new file mode 100644 index 0000000000000000000000000000000000000000..796fe2599561db05a7b0c4160eb0b99a5f587413 --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv @@ -0,0 +1,109 @@ +// Driven-signal TB for jotego_jtcores_pr1202 (jtkarnov_obj dr_xpos offset). +// The fix introduces an intermediate register `xoff = flip ? 24 : 8` and +// replaces +// dr_xpos <= xpos + (flip ? -25 : -7); // buggy +// with +// dr_xpos <= xpos - xoff; // fixed +// giving a 1-pixel shift in both flip orientations. +// +// We force the FSM state registers directly to drop the DUT into the +// `st == 3` branch with dr_busy low, xpos = 100, flip = 0. After one +// clock edge: +// Buggy : dr_xpos = 100 + -7 = 93 = 9'h05D +// Fixed : dr_xpos = 100 - 8 = 92 = 9'h05C +// We observe `dut.dr_xpos` hierarchically. +`timescale 1ns/1ps + +module tb_jtkarnov_obj_xoff_verilator; + logic rst = 1, clk = 0; + logic pxl_cen = 1; + logic hs = 0; + logic flip = 0; + logic [8:0] hdump = 0; + logic [8:0] vrender = 0; + wire [11:1] dma_addr; + logic dma_start = 0; + wire dma_we; + wire [11:1] ram_addr; + logic [15:0] ram_data = 16'h0; + wire [18:2] rom_addr; + logic [31:0] rom_data = 32'h0; + wire rom_cs; + logic rom_ok = 1; + logic [7:0] debug_bus = 0; + wire [7:0] pxl; + + jtkarnov_obj dut ( + .rst(rst), .clk(clk), .pxl_cen(pxl_cen), + .hs(hs), .flip(flip), + .hdump(hdump), .vrender(vrender), + .dma_addr(dma_addr), .dma_start(dma_start), .dma_we(dma_we), + .ram_addr(ram_addr), .ram_data(ram_data), + .rom_addr(rom_addr), .rom_data(rom_data), .rom_cs(rom_cs), .rom_ok(rom_ok), + .debug_bus(debug_bus), .pxl(pxl) + ); + + always #5 clk = ~clk; + + initial begin + rst = 1; + flip = 0; + repeat (4) @(posedge clk); + rst = 0; + repeat (2) @(posedge clk); + + // Force the FSM into st==3 with xpos=100, dr_busy=0, done=0, cen=1 + // on the next clock edge the dr_xpos reg captures xpos + offset. + @(negedge clk); + force dut.st = 2'd3; + force dut.xpos = 9'd100; + force dut.done = 1'b0; + force dut.cen = 1'b1; + force dut.u_objdraw.busy = 1'b0; // drive dr_busy input + force dut.obj_cnt = 9'd10; // ensure adv path does not clobber + force dut.adv = 1'b0; + @(posedge clk); + @(negedge clk); + + $display("INFO: flip=%0b xpos=%0d dr_xpos=%0d (0x%03h)", + flip, dut.xpos, dut.dr_xpos, dut.dr_xpos); + + if (dut.dr_xpos === 9'd92) + $display("PASS: dr_xpos uses xoff=8 -> xpos-8 (fix verified)."); + else if (dut.dr_xpos === 9'd93) + $display("FAIL: dr_xpos = xpos-7 (buggy offset)."); + else + $display("FAIL: unexpected dr_xpos=%0d", dut.dr_xpos); + + // ---- Coverage stimulus (no assertions): exercise the remaining + // directions of the flip/pxl_cen conditionals in jtkarnov_obj.v: + // L64 xoff = flip ? 9'd24 : 9'd8 (flip TRUE side) + // L71 if(flip) hdf[7] <= ... (flip TRUE side) + // L69 always @(posedge clk) if(pxl_cen) (pxl_cen FALSE side) + release dut.st; + release dut.xpos; + release dut.done; + release dut.cen; + release dut.u_objdraw.busy; + release dut.obj_cnt; + release dut.adv; + + flip = 1'b1; // flip TRUE -> L64/L71 true sides + pxl_cen = 1'b1; + hdump = 9'h1A5; + repeat (4) @(posedge clk); // clock the if(flip) hdf update + pxl_cen = 1'b0; // pxl_cen FALSE -> L69 body skipped + repeat (4) @(posedge clk); + pxl_cen = 1'b1; + flip = 1'b0; + repeat (2) @(posedge clk); + + $finish; + end + + initial begin + #10000; + $display("FAIL: timeout"); + $finish; + end +endmodule diff --git a/testbench/jotego_jtcores_pr1202/verilator_buggy.log b/testbench/jotego_jtcores_pr1202/verilator_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..7108577ce96d685a70dbe918b3ff4281efa2f52d --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/verilator_buggy.log @@ -0,0 +1,3 @@ +INFO: flip=0 xpos=100 dr_xpos=93 (0x05d) +FAIL: dr_xpos = xpos-7 (buggy offset). +- testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv:101: Verilog $finish diff --git a/testbench/jotego_jtcores_pr1202/verilator_fixed.log b/testbench/jotego_jtcores_pr1202/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..ec425a5171fcfd073eaaa2d48de82aee7571848e --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/verilator_fixed.log @@ -0,0 +1,3 @@ +INFO: flip=0 xpos=100 dr_xpos=92 (0x05c) +PASS: dr_xpos uses xoff=8 -> xpos-8 (fix verified). +- testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv:101: Verilog $finish diff --git a/testbench/jotego_jtcores_pr1202/verilator_fixed_build.log b/testbench/jotego_jtcores_pr1202/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..2005b5cf3865a1ce4d4ac90f03ba3912689f4999 --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory 'testbench/jotego_jtcores_pr1202/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/jotego_jtcores_pr1202/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/jotego_jtcores_pr1202/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.119 MB sources in 11 modules, into 0.524 MB in 5 C++ files needing 0.001 MB +- Verilator: Walltime 8.506 s (elab=0.004, cvt=0.022, bld=8.467); cpu 0.040 s on 1 threads; allocated 23.836 MB diff --git a/testbench/jotego_jtcores_pr1202/verilator_fixed_coverage.info b/testbench/jotego_jtcores_pr1202/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..6c3079fa47bb77d70e5fb4b11497b23562dd7a77 --- /dev/null +++ b/testbench/jotego_jtcores_pr1202/verilator_fixed_coverage.info @@ -0,0 +1,2968 @@ +TN:verilator_coverage +SF:testbench/jotego_jtcores_pr1202/snapshot_scratch/cores/karnov/hdl/jtkarnov_obj.v +DA:20,1 +BRDA:20,0,0,1 +BRDA:20,0,1,1 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+ +### filelist_surelog:cores/tora/ver/adpcm/gather.f +'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/adpcm/gather.f' '-odir' 'testbench/jotego_jtcores_pr654/open_tool_fixed_fl' +[INF:CM0023] Creating log file "testbench/jotego_jtcores_pr654/open_tool_fixed_fl/slpp_all/surelog.log". + +[FTL:CM0008] Verilog File "./modules/jtframe/hdl/cpu/jtframe_z80.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtframe/hdl/jtframe_z80wait.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtframe/hdl/ram/jtframe_ram.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_cen.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_cenp384.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_cen3p57.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_sound.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_obj32.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jt12/jt49/hdl/filter/jt49_dcrm2.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jt12/hdl/mixer/jt12_mixer.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/hdl/jttora_adpcm.v" does not exist. + +[WRN:CM0005] Include path "./modules/jtframe/hdl/cpu" does not exist. + +[WRN:CM0005] Include path "./modules/jtframe/hdl" does not exist. + +[WRN:CM0005] Include path "./modules/jtframe/hdl/ram" does not exist. + +[WRN:CM0005] Include path "./modules" does not exist. + +[WRN:CM0005] Include path "./modules/jt12/jt49/hdl/filter" does not exist. + +[WRN:CM0005] Include path "./modules/jt12/hdl/mixer" does not exist. + +[WRN:CM0005] Include path "testbench/hdl" does not exist. + +[ FATAL] : 11 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 7 +[ NOTE] : 0 + +rc=1 + +### filelist_verilator:cores/tora/ver/adpcm/gather.f +'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/adpcm/gather.f' +%Error: Cannot find file containing module: '../../../modules/jtframe/hdl/jtframe_z80wait.v' + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. + ... Looked in: + testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v + testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + ../../../modules/jtframe/hdl/jtframe_z80wait.v + ../../../modules/jtframe/hdl/jtframe_z80wait.v.v + ../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v + obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + ... With current working directory 'testbench/jotego_jtcores_pr654/snapshot_scratch' +%Error: Cannot find file containing module: '../../../modules/jtgng_cen.v' +%Error: Cannot find file containing module: '../../../modules/jtgng_cenp384.v' +%Error: Cannot find file containing module: '../../../modules/jtgng_cen3p57.v' +%Error: Cannot find file containing module: '../../../modules/jtgng_sound.v' +%Error: Cannot find file containing module: '../../../modules/jtgng_obj32.v' +%Error: Cannot find file containing module: '../../../modules/jt12/jt49/hdl/filter/jt49_dcrm2.v' +%Error: Cannot find file containing module: '../../../modules/jt12/hdl/mixer/jt12_mixer.v' +%Error: Cannot find file containing module: '../../hdl/jttora_adpcm.v' +%Error: Exiting due to 9 error(s) + +rc=1 + +### filelist_surelog:cores/tora/ver/sound/gather.f +'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/sound/gather.f' '-odir' 'testbench/jotego_jtcores_pr654/open_tool_fixed_fl' +[INF:CM0023] Creating log file "testbench/jotego_jtcores_pr654/open_tool_fixed_fl/slpp_all/surelog.log". + +[FTL:CM0008] Verilog File "./modules/jtframe/hdl/cpu/jtframe_z80.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtframe/hdl/jtframe_z80wait.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtframe/hdl/ram/jtframe_ram.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_cen3p57.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_sound.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jtgng_obj32.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jt12/jt49/hdl/filter/jt49_dcrm2.v" does not exist. + +[FTL:CM0008] Verilog File "./modules/jt12/hdl/mixer/jt12_mixer.v" does not exist. + +[WRN:CM0005] Include path "./modules/jtframe/hdl/cpu" does not exist. + +[WRN:CM0005] Include path "./modules/jtframe/hdl" does not exist. + +[WRN:CM0005] Include path "./modules/jtframe/hdl/ram" does not exist. + +[WRN:CM0005] Include path "./modules" does not exist. + +[WRN:CM0005] Include path "./modules/jt12/jt49/hdl/filter" does not exist. + +[WRN:CM0005] Include path "./modules/jt12/hdl/mixer" does not exist. + +[ FATAL] : 8 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 6 +[ NOTE] : 0 + +rc=1 + +### filelist_verilator:cores/tora/ver/sound/gather.f +'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/sound/gather.f' +%Error: Cannot find file containing module: '../../../modules/jtframe/hdl/jtframe_z80wait.v' + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. + ... Looked in: + testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v + testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + ../../../modules/jtframe/hdl/jtframe_z80wait.v + ../../../modules/jtframe/hdl/jtframe_z80wait.v.v + ../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v + obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.v + obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv + ... With current working directory 'testbench/jotego_jtcores_pr654/snapshot_scratch' +%Error: Cannot find file containing module: '../../../modules/jtgng_cen3p57.v' +%Error: Cannot find file containing module: '../../../modules/jtgng_sound.v' +%Error: Cannot find file containing module: '../../../modules/jtgng_obj32.v' +%Error: Cannot find file containing module: '../../../modules/jt12/jt49/hdl/filter/jt49_dcrm2.v' +%Error: Cannot find file containing module: '../../../modules/jt12/hdl/mixer/jt12_mixer.v' +%Error: Exiting due to 6 error(s) + +rc=1 + +### filelist_surelog:modules/jtframe/hdl/cpu/mc6502/mc6502.f +'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/modules/jtframe/hdl/cpu/mc6502/mc6502.f' '-odir' 'testbench/jotego_jtcores_pr654/open_tool_fixed_fl' +[INF:CM0023] Creating log file "testbench/jotego_jtcores_pr654/open_tool_fixed_fl/slpp_all/surelog.log". + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502ExecutionController.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502InstructionDecode.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502InterruptLogic.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502MemoryController.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502ProcessorStatusRegister.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502RegisterFile.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Shifter.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502.v" does not exist. + +[ FATAL] : 9 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 0 +[ NOTE] : 0 + +rc=1 + +### filelist_verilator:modules/jtframe/hdl/cpu/mc6502/mc6502.f +'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/modules/jtframe/hdl/cpu/mc6502/mc6502.f' +%Error: Cannot find file containing module: 'MC6502Accumulator.v' + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. + ... Looked in: + testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v + testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v.sv + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/MC6502Accumulator.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/MC6502Accumulator.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/MC6502Accumulator.v.sv + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/MC6502Accumulator.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/MC6502Accumulator.v.v + testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/MC6502Accumulator.v.sv + MC6502Accumulator.v + MC6502Accumulator.v.v + MC6502Accumulator.v.sv + obj_dir/MC6502Accumulator.v + obj_dir/MC6502Accumulator.v.v + obj_dir/MC6502Accumulator.v.sv + ... With current working directory 'testbench/jotego_jtcores_pr654/snapshot_scratch' +%Error: Cannot find file containing module: 'MC6502ExecutionController.v' +%Error: Cannot find file containing module: 'MC6502InstructionDecode.v' +%Error: Cannot find file containing module: 'MC6502InterruptLogic.v' +%Error: Cannot find file containing module: 'MC6502MemoryController.v' +%Error: Cannot find file containing module: 'MC6502ProcessorStatusRegister.v' +%Error: Cannot find file containing module: 'MC6502RegisterFile.v' +%Error: Cannot find file containing module: 'MC6502Shifter.v' +%Error: Cannot find file containing module: 'MC6502.v' +%Error: Exiting due to 9 error(s) + +rc=1 +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/jotego_jtcores_pr654/repo_native_buggy.log b/testbench/jotego_jtcores_pr654/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..8ca12dcb6d66aca082b8d86222bfe363ae26cc85 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed diff --git a/testbench/jotego_jtcores_pr654/repo_native_fixed.log b/testbench/jotego_jtcores_pr654/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..1fcdf963b8117df5eb377f1595102760513dc385 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed diff --git a/testbench/jotego_jtcores_pr654/run_once.sh b/testbench/jotego_jtcores_pr654/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/jotego_jtcores_pr654/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/jotego_jtcores_pr654/run_verilator.sh b/testbench/jotego_jtcores_pr654/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..7bc7f2423bc99bb92734c202bddbddbb77bda9e4 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/run_verilator.sh @@ -0,0 +1,32 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 +NAME=jotego_jtcores_pr654 +REPO_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$REPO_ROOT/snapshots/$NAME" +PATCH_FILE="$REPO_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +TARGET="cores/toki/hdl/dual_ram_buffer.v" +run_phase() { + local tag="$1" + rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log + run_repo_native_p2p_smoke "$tag" || return $? + find "$SCRATCH" -type f \( -name '*.sv' -o -name '*.v' -o -name '*.vh' \) >/dev/null + local src="" + [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET" + verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --timescale 1ns/1ps $src "$HERE/tb_dual_ram_buffer_verilator.sv" --top-module tb_dual_ram_buffer_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null + [ ! -x obj_dir/simv_vlt ] && return 2 + timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null + return ${PIPESTATUS[0]} +} +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase buggy; rc_buggy=$? +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase fixed; rc_fixed=$? +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; } diff --git a/testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv b/testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv new file mode 100644 index 0000000000000000000000000000000000000000..cb7d960e520db85be53cc4e6ce6f41c3dfc1d814 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv @@ -0,0 +1,69 @@ +// pr654: introduces cores/toki/hdl/dual_ram_buffer.v — 8-bit dual-banked RAM +// that copies primary bank into a shadow when `trigger` is high. Pre-patch the +// module is absent; post-patch the TB writes two primary-bank entries, reads +// them back via q_in, pulses trigger to copy to the shadow, then reads the +// shadow via q. +`timescale 1ns/1ps +module tb_dual_ram_buffer_verilator; + localparam int W = 4; + reg clk = 0; + reg trigger = 0; + reg we = 0; + reg [W-1:0] addr_in = 0; + reg [7:0] data = 0; + wire [7:0] q_in; + reg [W-1:0] addr_out = 0; + wire [7:0] q; + + always #5 clk = ~clk; + + dual_ram_buffer #(.W(W)) dut ( + .clk (clk), + .trigger (trigger), + .we (we), + .addr_in (addr_in), + .data (data), + .q_in (q_in), + .addr_out(addr_out), + .q (q) + ); + + int errors = 0; + initial begin + // Write 0xA5 at addr 3 and 0x3C at addr 7 via primary port. + @(posedge clk); + we = 1; addr_in = 4'd3; data = 8'hA5; + @(posedge clk); + we = 1; addr_in = 4'd7; data = 8'h3C; + @(posedge clk); + we = 0; + + // Read via primary (q_in). + addr_in = 4'd3; @(posedge clk); #1; + if (q_in !== 8'hA5) begin errors++; $display("FAIL: q_in@3=%h expected A5", q_in); end + + addr_in = 4'd7; @(posedge clk); #1; + if (q_in !== 8'h3C) begin errors++; $display("FAIL: q_in@7=%h expected 3C", q_in); end + + // Trigger a full copy into shadow. Needs 2**W cycles. + trigger = 1; + repeat (2**W + 4) @(posedge clk); + trigger = 0; + repeat (4) @(posedge clk); + + // Read shadow via q. + addr_out = 4'd3; @(posedge clk); #1; + if (q !== 8'hA5) begin errors++; $display("FAIL: shadow@3 q=%h expected A5", q); end + + addr_out = 4'd7; @(posedge clk); #1; + if (q !== 8'h3C) begin errors++; $display("FAIL: shadow@7 q=%h expected 3C", q); end + + if (errors == 0) + $display("PASS: dual_ram_buffer primary write + shadow copy behave"); + else + $fatal(1, "FAIL: %0d errors", errors); + $finish; + end + + initial begin #5000; $fatal(1, "FAIL: timeout"); end +endmodule diff --git a/testbench/jotego_jtcores_pr654/verilator_buggy_phase.log b/testbench/jotego_jtcores_pr654/verilator_buggy_phase.log new file mode 100644 index 0000000000000000000000000000000000000000..d0fd297cd8a522c2655c1abc52e9b6ed1be1f928 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/verilator_buggy_phase.log @@ -0,0 +1 @@ +FAIL: buggy phase exited rc=2 diff --git a/testbench/jotego_jtcores_pr654/verilator_fixed.log b/testbench/jotego_jtcores_pr654/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..a105ef41bd6c61f07a5f80022bb59db1030b08d0 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/verilator_fixed.log @@ -0,0 +1,2 @@ +PASS: dual_ram_buffer primary write + shadow copy behave +- testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv:65: Verilog $finish diff --git a/testbench/jotego_jtcores_pr654/verilator_fixed_build.log b/testbench/jotego_jtcores_pr654/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..2bc2097a19c1b81ccd7710f46824c4846347c7fe --- /dev/null +++ b/testbench/jotego_jtcores_pr654/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory 'testbench/jotego_jtcores_pr654/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/jotego_jtcores_pr654/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/jotego_jtcores_pr654/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.052 MB sources in 3 modules, into 0.129 MB in 5 C++ files needing 0.000 MB +- Verilator: Walltime 8.241 s (elab=0.001, cvt=0.005, bld=8.231); cpu 0.010 s on 1 threads; allocated 21.078 MB diff --git a/testbench/jotego_jtcores_pr654/verilator_fixed_coverage.info b/testbench/jotego_jtcores_pr654/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..a5d021d89166d4b499ecb9124c2819236e7a44c3 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/verilator_fixed_coverage.info @@ -0,0 +1,760 @@ +TN:verilator_coverage +SF:testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/dual_ram_buffer.v +DA:9,31 +BRDA:9,0,0,31 +BRDA:9,0,1,30 +DA:10,1 +BRDA:10,0,0,1 +BRDA:10,0,1,1 +DA:12,1 +BRDA:12,0,0,1 +BRDA:12,0,1,1 +DA:13,2 +BRDA:13,0,0,1 +BRDA:13,0,1,0 +BRDA:13,0,2,1 +BRDA:13,0,3,0 +BRDA:13,0,4,2 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+DA:38,31 +DA:39,31 +BRF:606 +BRH:9 +end_of_record +SF:testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv +DA:9,31 +BRDA:9,0,0,31 +BRDA:9,0,1,30 +BRDA:9,0,2,1 +DA:10,1 +BRDA:10,0,0,1 +BRDA:10,0,1,1 +BRDA:10,0,2,1 +DA:11,1 +BRDA:11,0,0,1 +BRDA:11,0,1,1 +BRDA:11,0,2,1 +DA:12,2 +BRDA:12,0,0,1 +BRDA:12,0,1,0 +BRDA:12,0,2,1 +BRDA:12,0,3,0 +BRDA:12,0,4,2 +BRDA:12,0,5,1 +BRDA:12,0,6,0 +BRDA:12,0,7,0 +BRDA:12,0,8,1 +DA:13,1 +BRDA:13,0,0,1 +BRDA:13,0,1,1 +BRDA:13,0,2,0 +BRDA:13,0,3,0 +BRDA:13,0,4,1 +BRDA:13,0,5,0 +BRDA:13,0,6,1 +BRDA:13,0,7,0 +BRDA:13,0,8,1 +BRDA:13,0,9,0 +BRDA:13,0,10,1 +BRDA:13,0,11,0 +BRDA:13,0,12,0 +BRDA:13,0,13,0 +BRDA:13,0,14,1 +BRDA:13,0,15,1 +BRDA:13,0,16,1 +DA:14,1 +BRDA:14,0,0,1 +BRDA:14,0,1,1 +BRDA:14,0,2,0 +BRDA:14,0,3,0 +BRDA:14,0,4,1 +BRDA:14,0,5,0 +BRDA:14,0,6,1 +BRDA:14,0,7,0 +BRDA:14,0,8,1 +BRDA:14,0,9,0 +BRDA:14,0,10,1 +BRDA:14,0,11,0 +BRDA:14,0,12,0 +BRDA:14,0,13,0 +BRDA:14,0,14,1 +BRDA:14,0,15,1 +DA:15,1 +BRDA:15,0,0,1 +BRDA:15,0,1,0 +BRDA:15,0,2,1 +BRDA:15,0,3,0 +BRDA:15,0,4,1 +BRDA:15,0,5,0 +BRDA:15,0,6,0 +BRDA:15,0,7,0 +BRDA:15,0,8,1 +DA:16,1 +BRDA:16,0,0,1 +BRDA:16,0,1,1 +BRDA:16,0,2,0 +BRDA:16,0,3,0 +BRDA:16,0,4,1 +BRDA:16,0,5,0 +BRDA:16,0,6,1 +BRDA:16,0,7,0 +BRDA:16,0,8,1 +BRDA:16,0,9,0 +BRDA:16,0,10,1 +BRDA:16,0,11,0 +BRDA:16,0,12,0 +BRDA:16,0,13,0 +BRDA:16,0,14,1 +BRDA:16,0,15,1 +DA:18,61 +BRDA:18,0,0,30 +BRDA:18,0,1,31 +BRDA:18,0,2,61 +DA:31,1 +DA:32,1 +DA:34,1 +DA:35,1 +DA:36,1 +DA:37,1 +DA:38,1 +DA:39,1 +DA:42,1 +DA:43,1 +BRDA:43,0,0,0 +BRDA:43,0,1,1 +DA:45,1 +DA:46,1 +BRDA:46,0,0,0 +BRDA:46,0,1,1 +DA:49,1 +DA:50,20 +BRDA:50,0,0,1 +BRDA:50,0,1,20 +DA:51,1 +DA:52,4 +BRDA:52,0,0,1 +BRDA:52,0,1,4 +DA:55,1 +DA:56,1 +BRDA:56,0,0,0 +BRDA:56,0,1,1 +DA:58,1 +DA:59,1 +BRDA:59,0,0,0 +BRDA:59,0,1,1 +DA:61,1 +DA:62,1 +DA:65,1 +BRF:91 +BRH:6 +end_of_record diff --git a/testbench/jotego_jtcores_pr654/verilator_fixed_phase.log b/testbench/jotego_jtcores_pr654/verilator_fixed_phase.log new file mode 100644 index 0000000000000000000000000000000000000000..19e98c9e86cf83bf5a945aac89da403b0614ad29 --- /dev/null +++ b/testbench/jotego_jtcores_pr654/verilator_fixed_phase.log @@ -0,0 +1 @@ +PASS: fixed phase exited rc=0 diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_buggy.log b/testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..0230949d19674d27b430ec058006012f312ffacd --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_buggy.log @@ -0,0 +1,119 @@ +INFO: open-tool P2P fallback (buggy) +INFO: native simulation P2P not applicable for this case + +### filelist_surelog:openfpga_flow/openfpga_cell_library/verilog_sources.f +'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f' '-odir' 'testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_buggy_fl' +[INF:CM0023] Creating log file "testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_buggy_fl/slpp_all/surelog.log". + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/aib.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/buf4.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dff.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram16k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram1k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram8k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram_2048x8.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mem_32k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mult_16x16.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/gpio.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/inv.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/latch.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/lut6.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_32x32.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_36x36.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_8x8.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mux2.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/or2.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/spram_4x1.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/sram.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/tap_buf4.v" does not exist. + +[WRN:CM0005] Include path "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog" does not exist. + +[ FATAL] : 23 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 0 + +rc=1 + +### filelist_verilator:openfpga_flow/openfpga_cell_library/verilog_sources.f +'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f' +%Error: Cannot find file containing module: 'verilog/adder.v' + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. + ... Looked in: + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.sv + verilog/adder.v + verilog/adder.v.v + verilog/adder.v.sv + obj_dir/verilog/adder.v + obj_dir/verilog/adder.v.v + obj_dir/verilog/adder.v.sv + ... With current working directory 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' +%Error: Cannot find file containing module: 'verilog/aib.v' +%Error: Cannot find file containing module: 'verilog/buf4.v' +%Error: Cannot find file containing module: 'verilog/dff.v' +%Error: Cannot find file containing module: 'verilog/dpram.v' +%Error: Cannot find file containing module: 'verilog/dpram16k.v' +%Error: Cannot find file containing module: 'verilog/dpram1k.v' +%Error: Cannot find file containing module: 'verilog/dpram8k.v' +%Error: Cannot find file containing module: 'verilog/dpram_2048x8.v' +%Error: Cannot find file containing module: 'verilog/frac_mem_32k.v' +%Error: Cannot find file containing module: 'verilog/frac_mult_16x16.v' +%Error: Cannot find file containing module: 'verilog/gpio.v' +%Error: Cannot find file containing module: 'verilog/inv.v' +%Error: Cannot find file containing module: 'verilog/latch.v' +%Error: Cannot find file containing module: 'verilog/lut6.v' +%Error: Cannot find file containing module: 'verilog/mult_32x32.v' +%Error: Cannot find file containing module: 'verilog/mult_36x36.v' +%Error: Cannot find file containing module: 'verilog/mult_8x8.v' +%Error: Cannot find file containing module: 'verilog/mux2.v' +%Error: Cannot find file containing module: 'verilog/or2.v' +%Error: Cannot find file containing module: 'verilog/spram_4x1.v' +%Error: Cannot find file containing module: 'verilog/sram.v' +%Error: Cannot find file containing module: 'verilog/tap_buf4.v' +%Error: Exiting due to 23 error(s) + +rc=1 +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_fixed.log b/testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..3ef05e5d751605f17bb4fe8e709f2a3508889628 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_fixed.log @@ -0,0 +1,128 @@ +INFO: open-tool P2P fallback (fixed) +INFO: native simulation P2P not applicable for this case + +### filelist_surelog:openfpga_flow/openfpga_cell_library/verilog_sources.f +'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f' '-odir' 'testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_fixed_fl' +[INF:CM0023] Creating log file "testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_fixed_fl/slpp_all/surelog.log". + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/aib.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/buf4.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dff.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram16k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram1k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram8k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram_2048x8.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mem_32k.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mult_16x16.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/gpio.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/inv.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/latch.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/lut6.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_32x32.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_36x36.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_8x8.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mux2.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/or2.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/spram_4x1.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/sram.v" does not exist. + +[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/tap_buf4.v" does not exist. + +[WRN:CM0005] Include path "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog" does not exist. + +[ FATAL] : 23 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 0 + +rc=1 + +### filelist_verilator:openfpga_flow/openfpga_cell_library/verilog_sources.f +'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f' +%Error: Cannot find file containing module: 'verilog/adder.v' + ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance. + ... Looked in: + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/verilog/adder.v.sv + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib/verilog/adder.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib/verilog/adder.v.v + testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib/verilog/adder.v.sv + verilog/adder.v + verilog/adder.v.v + verilog/adder.v.sv + obj_dir/verilog/adder.v + obj_dir/verilog/adder.v.v + obj_dir/verilog/adder.v.sv + ... With current working directory 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' +%Error: Cannot find file containing module: 'verilog/aib.v' +%Error: Cannot find file containing module: 'verilog/buf4.v' +%Error: Cannot find file containing module: 'verilog/dff.v' +%Error: Cannot find file containing module: 'verilog/dpram.v' +%Error: Cannot find file containing module: 'verilog/dpram16k.v' +%Error: Cannot find file containing module: 'verilog/dpram1k.v' +%Error: Cannot find file containing module: 'verilog/dpram8k.v' +%Error: Cannot find file containing module: 'verilog/dpram_2048x8.v' +%Error: Cannot find file containing module: 'verilog/frac_mem_32k.v' +%Error: Cannot find file containing module: 'verilog/frac_mult_16x16.v' +%Error: Cannot find file containing module: 'verilog/gpio.v' +%Error: Cannot find file containing module: 'verilog/inv.v' +%Error: Cannot find file containing module: 'verilog/latch.v' +%Error: Cannot find file containing module: 'verilog/lut6.v' +%Error: Cannot find file containing module: 'verilog/mult_32x32.v' +%Error: Cannot find file containing module: 'verilog/mult_36x36.v' +%Error: Cannot find file containing module: 'verilog/mult_8x8.v' +%Error: Cannot find file containing module: 'verilog/mux2.v' +%Error: Cannot find file containing module: 'verilog/or2.v' +%Error: Cannot find file containing module: 'verilog/spram_4x1.v' +%Error: Cannot find file containing module: 'verilog/sram.v' +%Error: Cannot find file containing module: 'verilog/tap_buf4.v' +%Error: Exiting due to 23 error(s) + +rc=1 +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_buggy.log b/testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..8ca12dcb6d66aca082b8d86222bfe363ae26cc85 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_fixed.log b/testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..1fcdf963b8117df5eb377f1595102760513dc385 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/run_once.sh b/testbench/lnis-uofu_OpenFPGA_pr2164/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/run_verilator.sh b/testbench/lnis-uofu_OpenFPGA_pr2164/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..02100a537e4718c04c8b32c731445f0d5da568db --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/run_verilator.sh @@ -0,0 +1,37 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 +NAME=lnis-uofu_OpenFPGA_pr2164 +REPO_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$REPO_ROOT/snapshots/$NAME" +PATCH_FILE="$REPO_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +TARGET="openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16_regin.v" +PATCH_TARGETS=( + "$SCRATCH/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16_regin.v" + "$SCRATCH/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/dual_mult8_mix_regin.v" + "$SCRATCH/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_regin_nonLR_caravel_io_skywater130nm_cell_sim.v" +) +run_phase() { + local tag="$1" + rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log + run_repo_native_p2p_smoke "$tag" || return $? + local src="" + [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET" + verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-ASCRANGE --timescale 1ns/1ps $src "$HERE/tb_frac_mult_verilator.sv" --top-module tb_frac_mult_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null + [ ! -x obj_dir/simv_vlt ] && return 2 + timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null + grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0 + return 1 +} +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase buggy; rc_buggy=$? +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase fixed; rc_fixed=$? +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; } diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv b/testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv new file mode 100644 index 0000000000000000000000000000000000000000..f7d4480f10b42f72072ae182d46d61c47ee20178 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv @@ -0,0 +1,43 @@ +// pr2164: adds openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16_regin.v +// (fracturable 16x16 multiplier + registered wrapper). Pre-patch the file is +// absent; post-patch the TB exercises single-16 and dual-8 modes as separate +// testcases. +`timescale 1ns/1ps +module tb_frac_mult_verilator; + logic [0:15] a; + logic [0:15] b; + wire [0:31] out; + logic mode; + + frac_mult_16x16 dut (.a(a), .b(b), .out(out), .mode(mode)); + + initial begin + // Single-16 mode: out = a * b (32 bits) + mode = 1'b0; + a = 16'h0003; b = 16'h0005; #1; + if (out === 32'h0000_000F) $display("PASS: single-16 3*5 = 15"); + else $display("FAIL: 3*5 -> %h", out); + + a = 16'hFFFF; b = 16'h0002; #1; + if (out === 32'h0001_FFFE) $display("PASS: single-16 FFFF*2 = 1FFFE"); + else $display("FAIL: FFFF*2 -> %h", out); + + a = 16'h0010; b = 16'h0010; #1; + if (out === 32'h0000_0100) $display("PASS: single-16 16*16 = 256"); + else $display("FAIL: 16*16 -> %h", out); + + // Dual-8 mode: two independent 8x8 with [0:15] (MS-first) port ordering + mode = 1'b1; + a = 16'h0304; b = 16'h0506; #1; + if (out === {16'h000F, 16'h0018}) $display("PASS: dual-8 (3,4)x(5,6) = (15,24)"); + else $display("FAIL: dual-8 -> %h", out); + + a = 16'hFF02; b = 16'h0203; #1; // (FFx02, 02x03) = (1FE, 6) + if (out === {16'h01FE, 16'h0006}) $display("PASS: dual-8 (FF,02)x(02,03) = (1FE,6)"); + else $display("FAIL: dual-8 -> %h", out); + + $finish; + end + + initial begin #1000; $display("FAIL: timeout"); $finish; end +endmodule diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_buggy_build.log b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_buggy_build.log new file mode 100644 index 0000000000000000000000000000000000000000..157aff3a5dc0e8bbdd67708aa2bb4a65eb07de32 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_buggy_build.log @@ -0,0 +1,29 @@ +%Error-MODMISSING: testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv:12:3: Cannot find file containing module: 'frac_mult_16x16' + 12 | frac_mult_16x16 dut (.a(a), .b(b), .out(out), .mode(mode)); + | ^~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/MODMISSING?v=5.047 + ... This may be because there's no search path specified with -I. + ... Looked in: + frac_mult_16x16 + frac_mult_16x16.v + frac_mult_16x16.sv + obj_dir/frac_mult_16x16 + obj_dir/frac_mult_16x16.v + obj_dir/frac_mult_16x16.sv + ... With current working directory 'testbench/lnis-uofu_OpenFPGA_pr2164' +%Error: Exiting due to 1 error(s) +HWE_AUTO_COVERAGE: retrying with --coverage-line +%Error-MODMISSING: testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv:12:3: Cannot find file containing module: 'frac_mult_16x16' + 12 | frac_mult_16x16 dut (.a(a), .b(b), .out(out), .mode(mode)); + | ^~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/MODMISSING?v=5.047 + ... This may be because there's no search path specified with -I. + ... Looked in: + frac_mult_16x16 + frac_mult_16x16.v + frac_mult_16x16.sv + obj_dir/frac_mult_16x16 + obj_dir/frac_mult_16x16.v + obj_dir/frac_mult_16x16.sv + ... With current working directory 'testbench/lnis-uofu_OpenFPGA_pr2164' +%Error: Exiting due to 1 error(s) diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_buggy_phase.log b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_buggy_phase.log new file mode 100644 index 0000000000000000000000000000000000000000..d0fd297cd8a522c2655c1abc52e9b6ed1be1f928 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_buggy_phase.log @@ -0,0 +1 @@ +FAIL: buggy phase exited rc=2 diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed.log b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..699917dbb2a1c7a9b7a60a13af60747c0d30011d --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed.log @@ -0,0 +1,6 @@ +PASS: single-16 3*5 = 15 +PASS: single-16 FFFF*2 = 1FFFE +PASS: single-16 16*16 = 256 +PASS: dual-8 (3,4)x(5,6) = (15,24) +PASS: dual-8 (FF,02)x(02,03) = (1FE,6) +- testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv:39: Verilog $finish diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_build.log b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..98d64c5ec5a2014223fdafdddc3d778956b23c2d --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory 'testbench/lnis-uofu_OpenFPGA_pr2164/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/lnis-uofu_OpenFPGA_pr2164/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/lnis-uofu_OpenFPGA_pr2164/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.054 MB sources in 4 modules, into 0.055 MB in 5 C++ files needing 0.000 MB +- Verilator: Walltime 8.030 s (elab=0.000, cvt=0.003, bld=8.023); cpu 0.007 s on 1 threads; allocated 20.660 MB diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_coverage.info b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..1b273d806d917f107ae1299c3f1e4c1b615890d8 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_coverage.info @@ -0,0 +1,380 @@ +TN:verilator_coverage +SF:testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16_regin.v +DA:11,2 +BRDA:11,0,0,2 +BRDA:11,0,1,1 +BRDA:11,0,2,1 +BRDA:11,0,3,1 +BRDA:11,0,4,1 +BRDA:11,0,5,1 +BRDA:11,0,6,1 +BRDA:11,0,7,1 +BRDA:11,0,8,2 +BRDA:11,0,9,2 +BRDA:11,0,10,2 +BRDA:11,0,11,1 +BRDA:11,0,12,1 +BRDA:11,0,13,1 +BRDA:11,0,14,2 +BRDA:11,0,15,1 +BRDA:11,0,16,2 +BRDA:11,0,17,1 +BRDA:11,0,18,2 +BRDA:11,0,19,1 +BRDA:11,0,20,2 +BRDA:11,0,21,1 +BRDA:11,0,22,2 +BRDA:11,0,23,1 +BRDA:11,0,24,2 +BRDA:11,0,25,1 +BRDA:11,0,26,2 +BRDA:11,0,27,1 +BRDA:11,0,28,1 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+BRDA:16,0,23,0 +BRDA:16,0,24,1 +BRDA:16,0,25,1 +BRDA:16,0,26,1 +BRDA:16,0,27,1 +BRDA:16,0,28,1 +BRDA:16,0,29,1 +BRDA:16,0,30,1 +BRDA:16,0,31,1 +BRDA:16,0,32,1 +BRDA:16,0,33,1 +BRDA:16,0,34,1 +BRDA:16,0,35,1 +BRDA:16,0,36,1 +BRDA:16,0,37,1 +BRDA:16,0,38,2 +BRDA:16,0,39,2 +BRDA:16,0,40,2 +BRDA:16,0,41,2 +BRDA:16,0,42,2 +BRDA:16,0,43,1 +BRDA:16,0,44,0 +BRDA:16,0,45,0 +BRDA:16,0,46,2 +BRDA:16,0,47,1 +BRDA:16,0,48,1 +BRDA:16,0,49,1 +BRDA:16,0,50,0 +BRDA:16,0,51,0 +BRDA:16,0,52,0 +BRDA:16,0,53,0 +BRDA:16,0,54,0 +BRDA:16,0,55,0 +BRDA:16,0,56,0 +BRDA:16,0,57,0 +BRDA:16,0,58,1 +BRDA:16,0,59,0 +BRDA:16,0,60,1 +BRDA:16,0,61,0 +BRDA:16,0,62,1 +BRDA:16,0,63,0 +DA:18,5 +DA:19,3 +BRDA:19,0,0,2 +BRDA:19,0,1,3 +DA:20,2 +DA:21,2 +DA:22,3 +DA:23,3 +BRF:196 +BRH:0 +end_of_record +SF:testbench/lnis-uofu_OpenFPGA_pr2164/tb_frac_mult_verilator.sv +DA:7,2 +BRDA:7,0,0,2 +BRDA:7,0,1,1 +BRDA:7,0,2,1 +BRDA:7,0,3,1 +BRDA:7,0,4,1 +BRDA:7,0,5,1 +BRDA:7,0,6,1 +BRDA:7,0,7,1 +BRDA:7,0,8,2 +BRDA:7,0,9,2 +BRDA:7,0,10,2 +BRDA:7,0,11,1 +BRDA:7,0,12,1 +BRDA:7,0,13,1 +BRDA:7,0,14,2 +BRDA:7,0,15,1 +BRDA:7,0,16,2 +BRDA:7,0,17,1 +BRDA:7,0,18,2 +BRDA:7,0,19,1 +BRDA:7,0,20,2 +BRDA:7,0,21,1 +BRDA:7,0,22,2 +BRDA:7,0,23,1 +BRDA:7,0,24,2 +BRDA:7,0,25,1 +BRDA:7,0,26,2 +BRDA:7,0,27,1 +BRDA:7,0,28,1 +BRDA:7,0,29,1 +BRDA:7,0,30,1 +BRDA:7,0,31,1 +DA:8,2 +BRDA:8,0,0,0 +BRDA:8,0,1,0 +BRDA:8,0,2,0 +BRDA:8,0,3,0 +BRDA:8,0,4,1 +BRDA:8,0,5,1 +BRDA:8,0,6,0 +BRDA:8,0,7,0 +BRDA:8,0,8,2 +BRDA:8,0,9,2 +BRDA:8,0,10,2 +BRDA:8,0,11,1 +BRDA:8,0,12,2 +BRDA:8,0,13,1 +BRDA:8,0,14,0 +BRDA:8,0,15,0 +BRDA:8,0,16,0 +BRDA:8,0,17,0 +BRDA:8,0,18,0 +BRDA:8,0,19,0 +BRDA:8,0,20,0 +BRDA:8,0,21,0 +BRDA:8,0,22,1 +BRDA:8,0,23,1 +BRDA:8,0,24,1 +BRDA:8,0,25,0 +BRDA:8,0,26,1 +BRDA:8,0,27,1 +BRDA:8,0,28,0 +BRDA:8,0,29,0 +BRDA:8,0,30,0 +BRDA:8,0,31,0 +DA:9,2 +BRDA:9,0,0,0 +BRDA:9,0,1,0 +BRDA:9,0,2,1 +BRDA:9,0,3,0 +BRDA:9,0,4,1 +BRDA:9,0,5,0 +BRDA:9,0,6,1 +BRDA:9,0,7,0 +BRDA:9,0,8,1 +BRDA:9,0,9,0 +BRDA:9,0,10,1 +BRDA:9,0,11,0 +BRDA:9,0,12,2 +BRDA:9,0,13,2 +BRDA:9,0,14,1 +BRDA:9,0,15,1 +BRDA:9,0,16,1 +BRDA:9,0,17,1 +BRDA:9,0,18,1 +BRDA:9,0,19,1 +BRDA:9,0,20,1 +BRDA:9,0,21,1 +BRDA:9,0,22,0 +BRDA:9,0,23,0 +BRDA:9,0,24,1 +BRDA:9,0,25,1 +BRDA:9,0,26,1 +BRDA:9,0,27,1 +BRDA:9,0,28,1 +BRDA:9,0,29,1 +BRDA:9,0,30,1 +BRDA:9,0,31,1 +BRDA:9,0,32,1 +BRDA:9,0,33,1 +BRDA:9,0,34,1 +BRDA:9,0,35,1 +BRDA:9,0,36,1 +BRDA:9,0,37,1 +BRDA:9,0,38,2 +BRDA:9,0,39,2 +BRDA:9,0,40,2 +BRDA:9,0,41,2 +BRDA:9,0,42,2 +BRDA:9,0,43,1 +BRDA:9,0,44,0 +BRDA:9,0,45,0 +BRDA:9,0,46,2 +BRDA:9,0,47,1 +BRDA:9,0,48,1 +BRDA:9,0,49,1 +BRDA:9,0,50,0 +BRDA:9,0,51,0 +BRDA:9,0,52,0 +BRDA:9,0,53,0 +BRDA:9,0,54,0 +BRDA:9,0,55,0 +BRDA:9,0,56,0 +BRDA:9,0,57,0 +BRDA:9,0,58,1 +BRDA:9,0,59,0 +BRDA:9,0,60,1 +BRDA:9,0,61,0 +BRDA:9,0,62,1 +BRDA:9,0,63,0 +DA:10,1 +BRDA:10,0,0,1 +BRDA:10,0,1,0 +DA:14,1 +DA:16,1 +DA:17,1 +DA:18,1 +BRDA:18,0,0,1 +BRDA:18,0,1,0 +DA:19,0 +DA:21,1 +DA:22,1 +BRDA:22,0,0,1 +BRDA:22,0,1,0 +DA:23,0 +DA:25,1 +DA:26,1 +BRDA:26,0,0,1 +BRDA:26,0,1,0 +DA:27,0 +DA:30,1 +DA:31,1 +DA:32,1 +BRDA:32,0,0,1 +BRDA:32,0,1,0 +DA:33,0 +DA:35,1 +DA:36,1 +BRDA:36,0,0,1 +BRDA:36,0,1,0 +DA:37,0 +DA:39,1 +DA:42,0 +BRF:140 +BRH:0 +end_of_record diff --git a/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_phase.log b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_phase.log new file mode 100644 index 0000000000000000000000000000000000000000..19e98c9e86cf83bf5a945aac89da403b0614ad29 --- /dev/null +++ b/testbench/lnis-uofu_OpenFPGA_pr2164/verilator_fixed_phase.log @@ -0,0 +1 @@ +PASS: fixed phase exited rc=0 diff --git a/testbench/lowRISC_ibex_pr2166/open_tool_p2p_buggy.log b/testbench/lowRISC_ibex_pr2166/open_tool_p2p_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..c7c8398c4308f8e8bac387c2200b226503f84342 --- /dev/null +++ b/testbench/lowRISC_ibex_pr2166/open_tool_p2p_buggy.log @@ -0,0 +1,47 @@ +INFO: open-tool P2P fallback (buggy) +INFO: native simulation P2P not applicable for this case + +### native_multifile_compile:ibex_core_verilator_lint +'verilator' '--lint-only' '--sv' '--timing' '--Wno-fatal' '--Wno-WIDTH' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-PINCONNECTEMPTY' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '-DSYNTHESIS' '-DINC_ASSERT' '-Itestbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl' '-Itestbench/lowRISC_ibex_pr2166/snapshot_scratch/vendor/lowrisc_ip/dv/sv/dv_utils' '-Itestbench/lowRISC_ibex_pr2166/snapshot_scratch/vendor/lowrisc_ip/ip/prim/rtl' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_pkg.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_alu.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_compressed_decoder.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_counter.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_cs_registers.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_decoder.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_ex_block.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_load_store_unit.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_multdiv_slow.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_multdiv_fast.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_prefetch_buffer.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_fetch_fifo.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_register_file_ff.sv' 'testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_core.sv' '--top-module' 'ibex_core' '--Mdir' 'testbench/lowRISC_ibex_pr2166/open_tool_buggy_ibex_core_verilator_lint' +%Warning-UNOPTFLAT: testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:216:16: Signal unoptimizable: Circular combinational logic: 'ibex_core.id_stage_i.instr_executing_spec' + 216 | logic instr_executing_spec; + | ^~~~~~~~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.047 + ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:216:16: Example path: ibex_core.id_stage_i.instr_executing_spec + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:791:3: Example path: ALWAYS + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:265:16: Example path: ibex_core.id_stage_i.stall_alu + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:861:16: Example path: ASSIGNW + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:135:9: Example path: ibex_core.id_stage_i.controller_i.stall + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:453:3: Example path: ALWAYS + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:136:9: Example path: ibex_core.id_stage_i.controller_i.halt_if + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:682:24: Example path: ASSIGNW + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:138:22: Example path: ibex_core.if_stage_i.fetch_ready + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:453:3: Example path: ALWAYS +%Warning-UNOPTFLAT: testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:138:22: Signal unoptimizable: Circular combinational logic: 'ibex_core.if_stage_i.fetch_ready' + 138 | logic fetch_ready; + | ^~~~~~~~~~~ + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:138:22: Example path: ibex_core.if_stage_i.fetch_ready + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:453:3: Example path: ALWAYS + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:136:9: Example path: ibex_core.id_stage_i.controller_i.halt_if + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:682:24: Example path: ASSIGNW + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:138:22: Example path: ibex_core.if_stage_i.fetch_ready +%Warning-UNOPTFLAT: testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:218:16: Signal unoptimizable: Circular combinational logic: 'ibex_core.id_stage_i.instr_done' + 218 | logic instr_done; + | ^~~~~~~~~~ + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:218:16: Example path: ibex_core.id_stage_i.instr_done + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_id_stage.sv:665:34: Example path: ASSIGNW + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_core.sv:280:16: Example path: ibex_core.csr_op_en + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:234:22: Example path: ASSIGNW + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:140:9: Example path: ibex_core.id_stage_i.controller_i.special_req + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:453:3: Example path: ALWAYS + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:136:9: Example path: ibex_core.id_stage_i.controller_i.halt_if + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:682:24: Example path: ASSIGNW + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_if_stage.sv:138:22: Example path: ibex_core.if_stage_i.fetch_ready + testbench/lowRISC_ibex_pr2166/snapshot_scratch/rtl/ibex_controller.sv:453:3: Example path: ALWAYS +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 6.788 MB sources in 35 modules, into 0.979 MB in 4 C++ files needing 0.000 MB +- Verilator: Walltime 0.250 s (elab=0.050, cvt=0.124, bld=0.000); cpu 0.250 s on 1 threads; allocated 43.609 MB + +rc=0 +PASS: native multi-file compile P2P passed in buggy phase: ibex_core_verilator_lint; files=18 diff --git a/testbench/lowRISC_ibex_pr2166/repo_native_source.path b/testbench/lowRISC_ibex_pr2166/repo_native_source.path new file mode 100644 index 0000000000000000000000000000000000000000..ac6e44e79c1ad30603429f730ff047ef2708cef1 --- /dev/null +++ b/testbench/lowRISC_ibex_pr2166/repo_native_source.path @@ -0,0 +1 @@ +dv/cosim/cosim_dpi.svh diff --git a/testbench/lowRISC_ibex_pr2166/verilator_buggy_build.log b/testbench/lowRISC_ibex_pr2166/verilator_buggy_build.log new file mode 100644 index 0000000000000000000000000000000000000000..f339bf360d424b1b69466362919e3c9d579a46c1 --- /dev/null +++ b/testbench/lowRISC_ibex_pr2166/verilator_buggy_build.log @@ -0,0 +1,12 @@ +make: Entering directory 'testbench/lowRISC_ibex_pr2166/obj_dir' +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_ibex_wb_stage_verilator.cpp Vtb_ibex_wb_stage_verilator___024root__0.cpp Vtb_ibex_wb_stage_verilator__main.cpp Vtb_ibex_wb_stage_verilator___024root__Slow.cpp Vtb_ibex_wb_stage_verilator___024root__0__Slow.cpp Vtb_ibex_wb_stage_verilator__Syms__Slow.cpp > Vtb_ibex_wb_stage_verilator__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o Vtb_ibex_wb_stage_verilator__ALL.o Vtb_ibex_wb_stage_verilator__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib verilated.o verilated_timing.o verilated_threads.o Vtb_ibex_wb_stage_verilator__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vtb_ibex_wb_stage_verilator__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/lowRISC_ibex_pr2166/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.198 MB sources in 4 modules, into 0.050 MB in 6 C++ files needing 0.000 MB +- Verilator: Walltime 6.072 s (elab=0.003, cvt=0.005, bld=6.058); cpu 0.014 s on 1 threads; allocated 21.703 MB diff --git a/testbench/pulp-platform_apb_pr1/open_tool_p2p_buggy.log b/testbench/pulp-platform_apb_pr1/open_tool_p2p_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..f7dbd9ee364cd4110f89bdd307808158d40a0ea9 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/open_tool_p2p_buggy.log @@ -0,0 +1,3 @@ +INFO: open-tool P2P fallback (buggy) +INFO: native simulation P2P not applicable for this case +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/pulp-platform_apb_pr1/open_tool_p2p_fixed.log b/testbench/pulp-platform_apb_pr1/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..e35c882693d15f397c8f26dacbfe49040de7f7c0 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/open_tool_p2p_fixed.log @@ -0,0 +1,3 @@ +INFO: open-tool P2P fallback (fixed) +INFO: native simulation P2P not applicable for this case +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/pulp-platform_apb_pr1/repo_native_buggy.log b/testbench/pulp-platform_apb_pr1/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..8ca12dcb6d66aca082b8d86222bfe363ae26cc85 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed diff --git a/testbench/pulp-platform_apb_pr1/repo_native_fixed.log b/testbench/pulp-platform_apb_pr1/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..1fcdf963b8117df5eb377f1595102760513dc385 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed diff --git a/testbench/pulp-platform_apb_pr1/repo_native_source.path b/testbench/pulp-platform_apb_pr1/repo_native_source.path new file mode 100644 index 0000000000000000000000000000000000000000..ff4bf5d0feb00c05095e30d1f723f639e45b9159 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/repo_native_source.path @@ -0,0 +1 @@ +src/apb_test.sv diff --git a/testbench/pulp-platform_apb_pr1/run_once.sh b/testbench/pulp-platform_apb_pr1/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/pulp-platform_apb_pr1/run_verilator.sh b/testbench/pulp-platform_apb_pr1/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..18b6a455bc9c04e506edf9c243199eee2ea73a37 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/run_verilator.sh @@ -0,0 +1,46 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 +if [ -f ${OSS_CAD_SUITE:-/opt/oss-cad-suite}/environment ]; then + . ${OSS_CAD_SUITE:-/opt/oss-cad-suite}/environment +fi +NAME=pulp-platform_apb_pr1 +REPO_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$REPO_ROOT/snapshots/$NAME" +PATCH_FILE="$REPO_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +TARGET="src/apb_ro_regs.sv" +TARGETS=( + "include/apb/assign.svh" + "src/apb_bus.sv" + "src/apb_intf.sv" + "src/apb_ro_regs.sv" + "src/apb_rw_regs.sv" + "src/apb_test.sv" +) +run_phase() { + local tag="$1" + rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log + run_repo_native_p2p_smoke "$tag" || return $? + for target_file in "${TARGETS[@]}"; do + [ -f "$SCRATCH/$target_file" ] || return 2 + done + local src="" + [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET" + verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --timescale 1ns/1ps $src "$HERE/tb_apb_ro_regs_verilator.sv" --top-module tb_apb_ro_regs_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null + [ ! -x obj_dir/simv_vlt ] && return 2 + timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null + grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0 + return 1 +} +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase buggy; rc_buggy=$? +rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH" +echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true +run_phase fixed; rc_fixed=$? +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; } diff --git a/testbench/pulp-platform_apb_pr1/tb_apb_ro_regs_verilator.sv b/testbench/pulp-platform_apb_pr1/tb_apb_ro_regs_verilator.sv new file mode 100644 index 0000000000000000000000000000000000000000..3b8b24c60edbbef1fb15514bf0203428c49d4d21 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/tb_apb_ro_regs_verilator.sv @@ -0,0 +1,84 @@ +// pr1: adds src/apb_ro_regs.sv (read-only 32-bit register file on APB). +// Pre-patch the file doesn't exist so the TB cannot compile. Post-patch each +// access pattern is reported as its own testcase. +`timescale 1ns/1ps + +module tb_apb_ro_regs_verilator; + localparam int N = 4; + reg pclk = 0, preset_n = 0; + reg [31:0] paddr = 0, pwdata = 0; + reg [2:0] pprot = 0; + reg psel = 0, penable = 0, pwrite = 0; + reg [3:0] pstrb = 0; + wire pready, pslverr; + wire [31:0] prdata; + reg [N-1:0][31:0] regs = '{32'hDEAD0003, 32'hDEAD0002, 32'hDEAD0001, 32'hDEAD0000}; + + apb_ro_regs #(.N_REGS(N)) dut ( + .pclk_i(pclk), .preset_ni(preset_n), + .paddr_i(paddr), .pprot_i(pprot), .psel_i(psel), .penable_i(penable), + .pwrite_i(pwrite), .pwdata_i(pwdata), .pstrb_i(pstrb), + .pready_o(pready), .prdata_o(prdata), .pslverr_o(pslverr), + .reg_i(regs) + ); + + always #5 pclk = ~pclk; + + initial begin + preset_n = 0; + #20; preset_n = 1; + #10; + + // Read reg 0 at byte-addr 0x0 + psel = 1; penable = 1; pwrite = 0; paddr = 32'h0; #1; + if (prdata === 32'hDEAD0000 && pslverr === 1'b0) + $display("PASS: apb_ro_regs read addr=0 -> DEAD0000"); + else + $display("FAIL: r0 prdata=%h pslverr=%b", prdata, pslverr); + + // Read reg 1 at byte-addr 0x4 + paddr = 32'h4; #1; + if (prdata === 32'hDEAD0001 && pslverr === 1'b0) + $display("PASS: apb_ro_regs read addr=4 -> DEAD0001"); + else + $display("FAIL: r1 prdata=%h pslverr=%b", prdata, pslverr); + + // Read reg 2 at byte-addr 0x8 + paddr = 32'h8; #1; + if (prdata === 32'hDEAD0002 && pslverr === 1'b0) + $display("PASS: apb_ro_regs read addr=8 -> DEAD0002"); + else + $display("FAIL: r2 prdata=%h pslverr=%b", prdata, pslverr); + + // Read reg 3 at byte-addr 0xC + paddr = 32'hC; #1; + if (prdata === 32'hDEAD0003 && pslverr === 1'b0) + $display("PASS: apb_ro_regs read addr=C -> DEAD0003"); + else + $display("FAIL: r3 prdata=%h pslverr=%b", prdata, pslverr); + + // Out-of-range read at byte-addr 0x10 + paddr = 32'h10; #1; + if (pslverr === 1'b1) + $display("PASS: apb_ro_regs out-of-range read asserts pslverr"); + else + $display("FAIL: oor pslverr=%b", pslverr); + + // Write returns pslverr=1 (read-only) + paddr = 32'h0; pwrite = 1; pwdata = 32'hBAADBEEF; #1; + if (pslverr === 1'b1) + $display("PASS: apb_ro_regs write asserts pslverr (read-only)"); + else + $display("FAIL: wr pslverr=%b", pslverr); + + // pready should be 1 (always ready) + if (pready === 1'b1) + $display("PASS: apb_ro_regs pready always asserted"); + else + $display("FAIL: pready=%b", pready); + + $finish; + end + + initial begin #2000; $display("FAIL: timeout"); $finish; end +endmodule diff --git a/testbench/pulp-platform_apb_pr1/verilator_buggy_phase.log b/testbench/pulp-platform_apb_pr1/verilator_buggy_phase.log new file mode 100644 index 0000000000000000000000000000000000000000..d0fd297cd8a522c2655c1abc52e9b6ed1be1f928 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/verilator_buggy_phase.log @@ -0,0 +1 @@ +FAIL: buggy phase exited rc=2 diff --git a/testbench/pulp-platform_apb_pr1/verilator_fixed.log b/testbench/pulp-platform_apb_pr1/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..76926ab589a85ed61fde8a21d52b919d700b6ae8 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/verilator_fixed.log @@ -0,0 +1,8 @@ +PASS: apb_ro_regs read addr=0 -> DEAD0000 +PASS: apb_ro_regs read addr=4 -> DEAD0001 +PASS: apb_ro_regs read addr=8 -> DEAD0002 +PASS: apb_ro_regs read addr=C -> DEAD0003 +PASS: apb_ro_regs out-of-range read asserts pslverr +PASS: apb_ro_regs write asserts pslverr (read-only) +PASS: apb_ro_regs pready always asserted +- testbench/pulp-platform_apb_pr1/tb_apb_ro_regs_verilator.sv:80: Verilog $finish diff --git a/testbench/pulp-platform_apb_pr1/verilator_fixed_build.log b/testbench/pulp-platform_apb_pr1/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..41f2583fc8d2366e8e114a6a2367c1494b6fede5 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory 'testbench/pulp-platform_apb_pr1/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/pulp-platform_apb_pr1/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/pulp-platform_apb_pr1/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.053 MB sources in 3 modules, into 0.082 MB in 5 C++ files needing 0.000 MB +- Verilator: Walltime 8.055 s (elab=0.001, cvt=0.004, bld=8.047); cpu 0.009 s on 1 threads; allocated 20.812 MB diff --git a/testbench/pulp-platform_apb_pr1/verilator_fixed_coverage.info b/testbench/pulp-platform_apb_pr1/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..95103fdb413a40ecae81788efb55b75d26979c12 --- /dev/null +++ b/testbench/pulp-platform_apb_pr1/verilator_fixed_coverage.info @@ -0,0 +1,1073 @@ +TN:verilator_coverage +SF:testbench/pulp-platform_apb_pr1/snapshot_scratch/src/apb_ro_regs.sv +DA:18,4 +BRDA:18,0,0,4 +BRDA:18,0,1,3 +DA:19,1 +BRDA:19,0,0,1 +BRDA:19,0,1,0 +DA:20,2 +BRDA:20,0,0,0 +BRDA:20,0,1,0 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b/testbench/pulp-platform_apb_pr1/verilator_fixed_phase.log @@ -0,0 +1 @@ +PASS: fixed phase exited rc=0 diff --git a/testbench/pulp-platform_axi_pr224/axi_lite_stubs.sv b/testbench/pulp-platform_axi_pr224/axi_lite_stubs.sv new file mode 100644 index 0000000000000000000000000000000000000000..f89547de87b4aa8b5e88756ff9c139811176b36c --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/axi_lite_stubs.sv @@ -0,0 +1,139 @@ +`timescale 1ns/1ps + +interface AXI_BUS #( + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 32, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0 +)(); + localparam int unsigned StrbWidth = AXI_DATA_WIDTH / 8; + + logic [AXI_ADDR_WIDTH-1:0] aw_addr; + logic aw_valid; + logic aw_ready; + logic [AXI_DATA_WIDTH-1:0] w_data; + logic [StrbWidth-1:0] w_strb; + logic w_valid; + logic w_ready; + logic [1:0] b_resp; + logic b_valid; + logic b_ready; + logic [AXI_ADDR_WIDTH-1:0] ar_addr; + logic ar_valid; + logic ar_ready; + logic [AXI_DATA_WIDTH-1:0] r_data; + logic [1:0] r_resp; + logic r_valid; + logic r_ready; + + modport Slave ( + input aw_addr, aw_valid, w_data, w_strb, w_valid, b_ready, ar_addr, ar_valid, r_ready, + output aw_ready, w_ready, b_resp, b_valid, ar_ready, r_data, r_resp, r_valid + ); + + modport Master ( + output aw_addr, aw_valid, w_data, w_strb, w_valid, b_ready, ar_addr, ar_valid, r_ready, + input aw_ready, w_ready, b_resp, b_valid, ar_ready, r_data, r_resp, r_valid + ); +endinterface + +interface AXI_LITE #( + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 32 +)(); + localparam int unsigned StrbWidth = AXI_DATA_WIDTH / 8; + + logic [AXI_ADDR_WIDTH-1:0] aw_addr; + logic aw_valid; + logic aw_ready; + logic [AXI_DATA_WIDTH-1:0] w_data; + logic [StrbWidth-1:0] w_strb; + logic w_valid; + logic w_ready; + logic [1:0] b_resp; + logic b_valid; + logic b_ready; + logic [AXI_ADDR_WIDTH-1:0] ar_addr; + logic ar_valid; + logic ar_ready; + logic [AXI_DATA_WIDTH-1:0] r_data; + logic [1:0] r_resp; + logic r_valid; + logic r_ready; + + modport Slave ( + input aw_addr, aw_valid, w_data, w_strb, w_valid, b_ready, ar_addr, ar_valid, r_ready, + output aw_ready, w_ready, b_resp, b_valid, ar_ready, r_data, r_resp, r_valid + ); + + modport Master ( + output aw_addr, aw_valid, w_data, w_strb, w_valid, b_ready, ar_addr, ar_valid, r_ready, + input aw_ready, w_ready, b_resp, b_valid, ar_ready, r_data, r_resp, r_valid + ); +endinterface + +module rr_arb_tree #( + parameter int unsigned NumIn = 1, + parameter type DataType = logic, + parameter bit AxiVldRdy = 1'b0, + parameter bit LockIn = 1'b0, + localparam int unsigned IdxWidth = (NumIn <= 1) ? 1 : $clog2(NumIn) +)( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic [IdxWidth-1:0] rr_i, + input logic [NumIn-1:0] req_i, + output logic [NumIn-1:0] gnt_o, + input DataType [NumIn-1:0] data_i, + input logic gnt_i, + output logic req_o, + output DataType data_o, + output logic [IdxWidth-1:0] idx_o +); + assign req_o = |req_i; + assign gnt_o = req_i & {NumIn{gnt_i}}; + assign data_o = data_i[0]; + assign idx_o = '0; +endmodule + +module fifo_v3 #( + parameter bit FALL_THROUGH = 1'b0, + parameter int unsigned DEPTH = 2, + parameter type dtype = logic +)( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic testmode_i, + output logic full_o, + output logic empty_o, + output logic [31:0] usage_o, + input dtype data_i, + input logic push_i, + output dtype data_o, + input logic pop_i +); + assign full_o = 1'b0; + assign empty_o = 1'b0; + assign usage_o = '0; + assign data_o = data_i; +endmodule + +module spill_register #( + parameter type T = logic, + parameter bit Bypass = 1'b1 +)( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + output logic ready_o, + input T data_i, + output logic valid_o, + input logic ready_i, + output T data_o +); + assign ready_o = ready_i; + assign valid_o = valid_i; + assign data_o = data_i; +endmodule diff --git a/testbench/pulp-platform_axi_pr224/open_tool_p2p_buggy.log b/testbench/pulp-platform_axi_pr224/open_tool_p2p_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..e38835631b1407d19c0f025d7699c52934f48027 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/open_tool_p2p_buggy.log @@ -0,0 +1,145 @@ +INFO: open-tool P2P fallback (buggy) +INFO: native simulation P2P not applicable for this case + +### native_multifile_compile:axi_bender_test_sources +'surelog' '-sv' '-parse' '-nocomp' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch/include' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch/src' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch/test' '-I./snapshots/pulp-platform_common_cells_pr222/include' '-I./snapshots/pulp-platform_common_cells_pr222/src' '-I./snapshots/pulp-platform_common_verification_pr6/src' './snapshots/pulp-platform_common_cells_pr222/src/cf_math_pkg.sv' './snapshots/pulp-platform_common_cells_pr222/src/addr_decode.sv' './snapshots/pulp-platform_common_cells_pr222/src/spill_register.sv' './snapshots/pulp-platform_common_cells_pr222/src/deprecated/fifo_v2.sv' './snapshots/pulp-platform_common_verification_pr6/src/clk_rst_gen.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_atop_filter.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_delayer.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_id_prepend.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_join.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_demux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_join.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_apb.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_axi.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_modify_address.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_mux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_err_slv.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_xbar.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_xbar.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_test.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_lite_to_axi.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_delayer.sv' '-odir' './testbench/pulp-platform_axi_pr224/open_tool_buggy_axi_bender_test_sources' +[INF:CM0023] Creating log file "./testbench/pulp-platform_axi_pr224/open_tool_buggy_axi_bender_test_sources/slpp_all/surelog.log". + +[NTE:PP0128] ./snapshots/pulp-platform_common_cells_pr222/src/cf_math_pkg.sv:15:88: Non ASCII character detected, replaced by space. + +[NTE:PP0128] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv:160:90: Non ASCII character detected, replaced by space. + +[NTE:PP0128] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv:160:90: Non ASCII character detected, replaced by space. + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/cf_math_pkg.sv:18:1: No timescale set for "cf_math_pkg". + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/addr_decode.sv:35:1: No timescale set for "addr_decode". + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/spill_register.sv:17:1: No timescale set for "spill_register". + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/deprecated/fifo_v2.sv:13:1: No timescale set for "fifo_v2". + +[WRN:PA0205] ./snapshots/pulp-platform_common_verification_pr6/src/clk_rst_gen.sv:12:1: No timescale set for "clk_rst_gen". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv:21:1: No timescale set for "axi_pkg". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:20:1: No timescale set for "AXI_BUS". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:105:1: No timescale set for "AXI_BUS_DV". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:251:1: No timescale set for "AXI_BUS_ASYNC". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:341:1: No timescale set for "AXI_BUS_ASYNC_GRAY". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:392:1: No timescale set for "AXI_LITE". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:448:1: No timescale set for "AXI_LITE_DV". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:506:1: No timescale set for "AXI_LITE_ASYNC_GRAY". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_atop_filter.sv:37:1: No timescale set for "axi_atop_filter". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_atop_filter.sv:375:1: No timescale set for "axi_atop_filter_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv:28:1: No timescale set for "axi_burst_splitter". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv:346:1: No timescale set for "axi_burst_splitter_ax_chan". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv:461:1: No timescale set for "axi_burst_splitter_counters". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv:26:1: No timescale set for "axi_cdc". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv:128:1: No timescale set for "axi_cdc_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv:190:1: No timescale set for "axi_lite_cdc_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv:20:1: No timescale set for "axi_cut". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv:119:1: No timescale set for "axi_cut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv:199:1: No timescale set for "axi_lite_cut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_delayer.sv:17:1: No timescale set for "axi_delayer". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_delayer.sv:127:1: No timescale set for "axi_delayer_intf". + +[WRN:PA0205] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv:26:1: No timescale set for "axi_demux". + +[WRN:PA0205] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv:588:1: No timescale set for "axi_demux_id_counters". + +[WRN:PA0205] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv:712:1: No timescale set for "axi_demux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_id_prepend.sv:18:1: No timescale set for "axi_id_prepend". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_join.sv:19:1: No timescale set for "axi_join_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_demux.sv:27:1: No timescale set for "axi_lite_demux". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_demux.sv:413:1: No timescale set for "axi_lite_demux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_join.sv:19:1: No timescale set for "axi_lite_join_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv:21:1: No timescale set for "axi_lite_mailbox". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv:204:1: No timescale set for "axi_lite_mailbox_slave". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv:558:1: No timescale set for "axi_lite_mailbox_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:23:1: No timescale set for "axi_lite_mux". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:393:1: No timescale set for "axi_lite_mux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_apb.sv:50:1: No timescale set for "axi_lite_to_apb". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_apb.sv:383:1: No timescale set for "axi_lite_to_apb_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_axi.sv:18:1: No timescale set for "axi_lite_to_axi". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_axi.sv:97:1: No timescale set for "axi_lite_to_axi_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_modify_address.sv:18:1: No timescale set for "axi_modify_address". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_modify_address.sv:89:1: No timescale set for "axi_modify_address_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_mux.sv:27:1: No timescale set for "axi_mux". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_mux.sv:424:1: No timescale set for "axi_mux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_err_slv.sv:19:1: No timescale set for "axi_err_slv". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv:21:1: No timescale set for "axi_multicut". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv:96:1: No timescale set for "axi_multicut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv:171:1: No timescale set for "axi_lite_multicut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv:19:1: No timescale set for "axi_to_axi_lite". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv:117:1: No timescale set for "axi_to_axi_lite_id_reflect". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv:249:1: No timescale set for "axi_to_axi_lite_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_xbar.sv:22:1: No timescale set for "axi_lite_xbar". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_xbar.sv:242:1: No timescale set for "axi_lite_xbar_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_xbar.sv:18:1: No timescale set for "axi_xbar". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_xbar.sv:283:1: No timescale set for "axi_xbar_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_test.sv:21:1: No timescale set for "axi_test". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_test.sv:2193:1: No timescale set for "axi_chan_logger". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_lite_to_axi.sv:18:1: No timescale set for "tb_axi_lite_to_axi". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_delayer.sv:17:1: No timescale set for "tb_axi_delayer". + +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 62 +[ NOTE] : 3 + +rc=0 +PASS: native multi-file compile P2P passed in buggy phase: axi_bender_test_sources; files=31 diff --git a/testbench/pulp-platform_axi_pr224/open_tool_p2p_fixed.log b/testbench/pulp-platform_axi_pr224/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..c743694f675a4cc5e7f7a1f13f10c6b45753baba --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/open_tool_p2p_fixed.log @@ -0,0 +1,145 @@ +INFO: open-tool P2P fallback (fixed) +INFO: native simulation P2P not applicable for this case + +### native_multifile_compile:axi_bender_test_sources +'surelog' '-sv' '-parse' '-nocomp' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch/include' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch/src' '-I./testbench/pulp-platform_axi_pr224/snapshot_scratch/test' '-I./snapshots/pulp-platform_common_cells_pr222/include' '-I./snapshots/pulp-platform_common_cells_pr222/src' '-I./snapshots/pulp-platform_common_verification_pr6/src' './snapshots/pulp-platform_common_cells_pr222/src/cf_math_pkg.sv' './snapshots/pulp-platform_common_cells_pr222/src/addr_decode.sv' './snapshots/pulp-platform_common_cells_pr222/src/spill_register.sv' './snapshots/pulp-platform_common_cells_pr222/src/deprecated/fifo_v2.sv' './snapshots/pulp-platform_common_verification_pr6/src/clk_rst_gen.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_atop_filter.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_delayer.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_id_prepend.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_join.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_demux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_join.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_apb.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_axi.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_modify_address.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_mux.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_err_slv.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_xbar.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_xbar.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_test.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_lite_to_axi.sv' './testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_delayer.sv' '-odir' './testbench/pulp-platform_axi_pr224/open_tool_fixed_axi_bender_test_sources' +[INF:CM0023] Creating log file "./testbench/pulp-platform_axi_pr224/open_tool_fixed_axi_bender_test_sources/slpp_all/surelog.log". + +[NTE:PP0128] ./snapshots/pulp-platform_common_cells_pr222/src/cf_math_pkg.sv:15:88: Non ASCII character detected, replaced by space. + +[NTE:PP0128] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv:160:90: Non ASCII character detected, replaced by space. + +[NTE:PP0128] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv:160:90: Non ASCII character detected, replaced by space. + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/cf_math_pkg.sv:18:1: No timescale set for "cf_math_pkg". + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/addr_decode.sv:35:1: No timescale set for "addr_decode". + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/spill_register.sv:17:1: No timescale set for "spill_register". + +[WRN:PA0205] ./snapshots/pulp-platform_common_cells_pr222/src/deprecated/fifo_v2.sv:13:1: No timescale set for "fifo_v2". + +[WRN:PA0205] ./snapshots/pulp-platform_common_verification_pr6/src/clk_rst_gen.sv:12:1: No timescale set for "clk_rst_gen". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_pkg.sv:21:1: No timescale set for "axi_pkg". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:20:1: No timescale set for "AXI_BUS". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:105:1: No timescale set for "AXI_BUS_DV". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:251:1: No timescale set for "AXI_BUS_ASYNC". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:341:1: No timescale set for "AXI_BUS_ASYNC_GRAY". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:392:1: No timescale set for "AXI_LITE". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:448:1: No timescale set for "AXI_LITE_DV". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_intf.sv:506:1: No timescale set for "AXI_LITE_ASYNC_GRAY". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_atop_filter.sv:37:1: No timescale set for "axi_atop_filter". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_atop_filter.sv:375:1: No timescale set for "axi_atop_filter_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv:28:1: No timescale set for "axi_burst_splitter". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv:346:1: No timescale set for "axi_burst_splitter_ax_chan". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_burst_splitter.sv:461:1: No timescale set for "axi_burst_splitter_counters". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv:26:1: No timescale set for "axi_cdc". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv:128:1: No timescale set for "axi_cdc_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cdc.sv:190:1: No timescale set for "axi_lite_cdc_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv:20:1: No timescale set for "axi_cut". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv:119:1: No timescale set for "axi_cut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_cut.sv:199:1: No timescale set for "axi_lite_cut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_delayer.sv:17:1: No timescale set for "axi_delayer". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_delayer.sv:127:1: No timescale set for "axi_delayer_intf". + +[WRN:PA0205] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv:26:1: No timescale set for "axi_demux". + +[WRN:PA0205] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv:588:1: No timescale set for "axi_demux_id_counters". + +[WRN:PA0205] ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_demux.sv:712:1: No timescale set for "axi_demux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_id_prepend.sv:18:1: No timescale set for "axi_id_prepend". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_join.sv:19:1: No timescale set for "axi_join_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_demux.sv:27:1: No timescale set for "axi_lite_demux". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_demux.sv:413:1: No timescale set for "axi_lite_demux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_join.sv:19:1: No timescale set for "axi_lite_join_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv:21:1: No timescale set for "axi_lite_mailbox". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv:204:1: No timescale set for "axi_lite_mailbox_slave". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mailbox.sv:558:1: No timescale set for "axi_lite_mailbox_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:23:1: No timescale set for "axi_lite_mux". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:393:1: No timescale set for "axi_lite_mux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_apb.sv:50:1: No timescale set for "axi_lite_to_apb". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_apb.sv:383:1: No timescale set for "axi_lite_to_apb_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_axi.sv:18:1: No timescale set for "axi_lite_to_axi". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_to_axi.sv:97:1: No timescale set for "axi_lite_to_axi_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_modify_address.sv:18:1: No timescale set for "axi_modify_address". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_modify_address.sv:89:1: No timescale set for "axi_modify_address_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_mux.sv:27:1: No timescale set for "axi_mux". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_mux.sv:424:1: No timescale set for "axi_mux_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_err_slv.sv:19:1: No timescale set for "axi_err_slv". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv:21:1: No timescale set for "axi_multicut". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv:96:1: No timescale set for "axi_multicut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_multicut.sv:171:1: No timescale set for "axi_lite_multicut_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv:19:1: No timescale set for "axi_to_axi_lite". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv:117:1: No timescale set for "axi_to_axi_lite_id_reflect". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_to_axi_lite.sv:249:1: No timescale set for "axi_to_axi_lite_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_xbar.sv:22:1: No timescale set for "axi_lite_xbar". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_xbar.sv:242:1: No timescale set for "axi_lite_xbar_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_xbar.sv:18:1: No timescale set for "axi_xbar". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_xbar.sv:283:1: No timescale set for "axi_xbar_intf". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_test.sv:21:1: No timescale set for "axi_test". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_test.sv:2193:1: No timescale set for "axi_chan_logger". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_lite_to_axi.sv:18:1: No timescale set for "tb_axi_lite_to_axi". + +[WRN:PA0205] testbench/pulp-platform_axi_pr224/snapshot_scratch/test/tb_axi_delayer.sv:17:1: No timescale set for "tb_axi_delayer". + +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 62 +[ NOTE] : 3 + +rc=0 +PASS: native multi-file compile P2P passed in fixed phase: axi_bender_test_sources; files=31 diff --git a/testbench/pulp-platform_axi_pr224/repo_native_buggy.log b/testbench/pulp-platform_axi_pr224/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..e02806d6f5f13822017aead10ff776505723bef4 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native multi-file open-tool P2P passed in buggy phase diff --git a/testbench/pulp-platform_axi_pr224/repo_native_fixed.log b/testbench/pulp-platform_axi_pr224/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..fda70edd791ec71660939f2148a8f5ef2737741d --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native multi-file open-tool P2P passed in fixed phase diff --git a/testbench/pulp-platform_axi_pr224/repo_native_source.path b/testbench/pulp-platform_axi_pr224/repo_native_source.path new file mode 100644 index 0000000000000000000000000000000000000000..2fa9615a4dcfff1be84ff230c609ae267e3b0118 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/repo_native_source.path @@ -0,0 +1 @@ +src/axi_test.sv diff --git a/testbench/pulp-platform_axi_pr224/run_once.sh b/testbench/pulp-platform_axi_pr224/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/pulp-platform_axi_pr224/run_verilator.sh b/testbench/pulp-platform_axi_pr224/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..bfdf4e5ae4304f4faa4e58e6dbf37db7f7ba3c94 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/run_verilator.sh @@ -0,0 +1,80 @@ +#!/bin/bash +set -u + +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +cd "$HERE" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 + +NAME=pulp-platform_axi_pr224 +REPO_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$REPO_ROOT/snapshots/$NAME" +PATCH_FILE="$REPO_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +TARGET_MUX="src/axi_lite_mux.sv" +TARGET_DEMUX="src/axi_demux.sv" + +trap 'rm -rf "$SCRATCH" obj_dir' EXIT + +prepare_phase() { + local tag="$1" + rm -rf "$SCRATCH" + cp -a "$SNAPSHOT" "$SCRATCH" + chmod -R u+w "$SCRATCH" + + if [ "$tag" = fixed ]; then + (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true + else + (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true + fi +} + +run_phase() { + local tag="$1" + rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log" + run_repo_native_p2p_smoke "$tag" || return $? + + [ -f "$SCRATCH/$TARGET_MUX" ] || { echo "missing $TARGET_MUX" > "verilator_${tag}_build.log"; return 2; } + [ -f "$SCRATCH/$TARGET_DEMUX" ] || { echo "missing $TARGET_DEMUX" > "verilator_${tag}_build.log"; return 2; } + + verilator \ + --binary \ + --timing \ + --sv \ + --Wno-fatal --Wno-WIDTH --Wno-WIDTHTRUNC --Wno-WIDTHEXPAND \ + --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM \ + --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME \ + --timescale 1ns/1ps \ + +incdir+"$HERE/include" \ + "$HERE/axi_lite_stubs.sv" \ + "$SCRATCH/$TARGET_MUX" \ + "$HERE/tb_axi_lite_mux_intf_signal.sv" \ + --top-module tb_axi_lite_mux_intf_signal \ + -Mdir obj_dir \ + -o simv_vlt 2>&1 | tee "verilator_${tag}_build.log" >/dev/null + local rc=${PIPESTATUS[0]} + [ "$rc" -eq 0 ] || return "$rc" + [ -x obj_dir/simv_vlt ] || return 2 + + timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null + rc=${PIPESTATUS[0]} + [ "$rc" -eq 0 ] || return "$rc" + grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" \ + && ! grep -qE '(^|[^A-Za-z])(FAIL:|\$fatal|Aborting\.\.\.)' "verilator_${tag}.log" +} + +echo BUGGY +prepare_phase buggy +run_phase buggy +rc_buggy=$? + +echo FIXED +prepare_phase fixed +run_phase fixed +rc_fixed=$? + +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] \ + && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } \ + || { echo "FAIL: $NAME"; exit 1; } diff --git a/testbench/pulp-platform_axi_pr224/tb_axi_lite_mux_intf_signal.sv b/testbench/pulp-platform_axi_pr224/tb_axi_lite_mux_intf_signal.sv new file mode 100644 index 0000000000000000000000000000000000000000..7e2a48232e56a0f1f3eced2f90f605b46e916946 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/tb_axi_lite_mux_intf_signal.sv @@ -0,0 +1,72 @@ +`timescale 1ns/1ps + +module tb_axi_lite_mux_intf_signal; + localparam int unsigned NoSlvPorts = 2; + + logic clk; + logic rst_n; + AXI_BUS #(.AXI_ADDR_WIDTH(32), .AXI_DATA_WIDTH(32)) slv [NoSlvPorts] (); + AXI_BUS #(.AXI_ADDR_WIDTH(32), .AXI_DATA_WIDTH(32)) mst (); + + axi_lite_mux_intf #( + .AxiAddrWidth(32), + .AxiDataWidth(32), + .NoSlvPorts(NoSlvPorts), + .MaxTrans(2), + .FallThrough(1'b1), + .SpillAw(1'b0), + .SpillW(1'b0), + .SpillB(1'b0), + .SpillAr(1'b0), + .SpillR(1'b0) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .test_i(1'b0), + .slv(slv), + .mst(mst) + ); + + initial begin + clk = 1'b0; + forever #1 clk = ~clk; + end + + initial begin + rst_n = 1'b0; + slv[0].aw_addr = 32'h1000_0040; + slv[0].aw_valid = 1'b1; + slv[0].w_data = 32'hcafe_babe; + slv[0].w_strb = 4'hf; + slv[0].w_valid = 1'b1; + slv[0].b_ready = 1'b1; + slv[0].ar_addr = 32'h2000_0080; + slv[0].ar_valid = 1'b1; + slv[0].r_ready = 1'b1; + slv[1].aw_valid = 1'b0; + slv[1].w_valid = 1'b0; + slv[1].b_ready = 1'b0; + slv[1].ar_valid = 1'b0; + slv[1].r_ready = 1'b0; + mst.aw_ready = 1'b1; + mst.w_ready = 1'b1; + mst.b_resp = 2'b00; + mst.b_valid = 1'b0; + mst.ar_ready = 1'b1; + mst.r_data = 32'h0; + mst.r_resp = 2'b00; + mst.r_valid = 1'b0; + + repeat (2) @(posedge clk); + rst_n = 1'b1; + repeat (4) @(posedge clk); + + if (mst.aw_valid !== 1'b1) begin + $fatal(1, "FAIL: axi_lite_mux_intf did not route AW request through typed request struct"); + end + + $display("PASS: T_COMPLETION directed testcase sequence completed"); + $display("PASS: axi_lite_mux_intf preserves structured AXI-Lite request signals"); + $finish; + end +endmodule diff --git a/testbench/pulp-platform_axi_pr224/verilator_buggy_build.log b/testbench/pulp-platform_axi_pr224/verilator_buggy_build.log new file mode 100644 index 0000000000000000000000000000000000000000..a25e5dbdd3b691b9f9213761235989c2522204af --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/verilator_buggy_build.log @@ -0,0 +1,245 @@ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:129:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 129 | assign slv_aw_chans[i] = slv_reqs_i[i].aw; + | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=5.047 +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:130:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 130 | assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:131:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 131 | assign slv_resps_o[i].aw_ready = slv_aw_readies[i]; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:213:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 213 | .valid_o ( mst_req_o.aw_valid ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:214:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 214 | .ready_i ( mst_resp_i.aw_ready ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:215:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 215 | .data_o ( mst_req_o.aw ) + | ^~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:222:85: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 222 | assign mst_w_chan = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w : '0; + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:223:85: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 223 | assign mst_w_valid = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w_valid : 1'b0; + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:225:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 225 | assign slv_resps_o[i].w_ready = mst_w_ready & ~w_fifo_empty & + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:257:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 257 | .valid_o ( mst_req_o.w_valid ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:258:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 258 | .ready_i ( mst_resp_i.w_ready ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:259:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 259 | .data_o ( mst_req_o.w ) + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:267:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 267 | assign slv_resps_o[i].b = mst_b_chan; + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:268:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 268 | assign slv_resps_o[i].b_valid = mst_b_valid & ~b_fifo_empty & (b_select == select_t'(i)); + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:270:66: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 270 | assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready; + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:279:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 279 | .valid_i ( mst_resp_i.b_valid ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:280:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 280 | .ready_o ( mst_req_o.b_ready ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:281:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 281 | .data_i ( mst_resp_i.b ), + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:292:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 292 | assign slv_ar_chans[i] = slv_reqs_i[i].ar; + | ^~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:293:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 293 | assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:294:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 294 | assign slv_resps_o[i].ar_ready = slv_ar_readies[i]; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:348:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 348 | .valid_o ( mst_req_o.ar_valid ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:349:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 349 | .ready_i ( mst_resp_i.ar_ready ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:350:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 350 | .data_o ( mst_req_o.ar ) + | ^~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:358:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 358 | assign slv_resps_o[i].r = mst_r_chan; + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:359:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 359 | assign slv_resps_o[i].r_valid = mst_r_valid & ~r_fifo_empty & (r_select == select_t'(i)); + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:361:66: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 361 | assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready; + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:370:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 370 | .valid_i ( mst_resp_i.r_valid ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:371:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 371 | .ready_o ( mst_req_o.r_ready ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:372:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 372 | .data_i ( mst_resp_i.r ), + | ^ +%Error: Exiting due to 30 error(s) +HWE_AUTO_COVERAGE: retrying with --coverage-line +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:129:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 129 | assign slv_aw_chans[i] = slv_reqs_i[i].aw; + | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=5.047 +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:130:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 130 | assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:131:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 131 | assign slv_resps_o[i].aw_ready = slv_aw_readies[i]; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:213:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 213 | .valid_o ( mst_req_o.aw_valid ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:214:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 214 | .ready_i ( mst_resp_i.aw_ready ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:215:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 215 | .data_o ( mst_req_o.aw ) + | ^~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:222:85: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 222 | assign mst_w_chan = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w : '0; + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:223:85: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 223 | assign mst_w_valid = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w_valid : 1'b0; + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:225:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 225 | assign slv_resps_o[i].w_ready = mst_w_ready & ~w_fifo_empty & + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:257:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 257 | .valid_o ( mst_req_o.w_valid ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:258:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 258 | .ready_i ( mst_resp_i.w_ready ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:259:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 259 | .data_o ( mst_req_o.w ) + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:267:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 267 | assign slv_resps_o[i].b = mst_b_chan; + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:268:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 268 | assign slv_resps_o[i].b_valid = mst_b_valid & ~b_fifo_empty & (b_select == select_t'(i)); + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:270:66: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 270 | assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready; + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:279:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 279 | .valid_i ( mst_resp_i.b_valid ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:280:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 280 | .ready_o ( mst_req_o.b_ready ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:281:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 281 | .data_i ( mst_resp_i.b ), + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:292:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 292 | assign slv_ar_chans[i] = slv_reqs_i[i].ar; + | ^~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:293:54: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 293 | assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:294:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 294 | assign slv_resps_o[i].ar_ready = slv_ar_readies[i]; + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:348:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 348 | .valid_o ( mst_req_o.ar_valid ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:349:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 349 | .ready_i ( mst_resp_i.ar_ready ), + | ^~~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:350:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 350 | .data_o ( mst_req_o.ar ) + | ^~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:358:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 358 | assign slv_resps_o[i].r = mst_r_chan; + | ^ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:359:29: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 359 | assign slv_resps_o[i].r_valid = mst_r_valid & ~r_fifo_empty & (r_select == select_t'(i)); + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:361:66: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 361 | assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready; + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:370:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 370 | .valid_i ( mst_resp_i.r_valid ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:371:28: Unsupported: Member call on object 'VARREF 'mst_req_o'' which is a 'REFDTYPE 'axi_req_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 371 | .ready_o ( mst_req_o.r_ready ), + | ^~~~~~~ +%Error-UNSUPPORTED: ./testbench/pulp-platform_axi_pr224/snapshot_scratch/src/axi_lite_mux.sv:372:29: Unsupported: Member call on object 'VARREF 'mst_resp_i'' which is a 'REFDTYPE 'axi_resp_t'' + : ... note: In instance 'tb_axi_lite_mux_intf_signal.dut.i_axi_mux' + 372 | .data_i ( mst_resp_i.r ), + | ^ +%Error: Exiting due to 30 error(s) diff --git a/testbench/pulp-platform_axi_pr224/verilator_fixed.log b/testbench/pulp-platform_axi_pr224/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..435d37228b763486945a8ee8fb3335a7cd835ab4 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/verilator_fixed.log @@ -0,0 +1,3 @@ +PASS: T_COMPLETION directed testcase sequence completed +PASS: axi_lite_mux_intf preserves structured AXI-Lite request signals +- ./testbench/pulp-platform_axi_pr224/tb_axi_lite_mux_intf_signal.sv:70: Verilog $finish diff --git a/testbench/pulp-platform_axi_pr224/verilator_fixed_build.log b/testbench/pulp-platform_axi_pr224/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..5c2df1ef35fd6b38410b9fc0edebb37e8f0f388b --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory './testbench/pulp-platform_axi_pr224/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o ./testbench/pulp-platform_axi_pr224/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top_AXI_BUS__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top_AXI_BUS__Slow.cpp Vhwe_cov_top_AXI_BUS__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory './testbench/pulp-platform_axi_pr224/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.139 MB sources in 9 modules, into 0.550 MB in 8 C++ files needing 0.001 MB +- Verilator: Walltime 8.877 s (elab=0.003, cvt=0.027, bld=8.837); cpu 0.041 s on 1 threads; allocated 24.121 MB diff --git a/testbench/pulp-platform_axi_pr224/verilator_fixed_coverage.info b/testbench/pulp-platform_axi_pr224/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..38e90bbf44599f37b5599aef11a3c58635296754 --- /dev/null +++ b/testbench/pulp-platform_axi_pr224/verilator_fixed_coverage.info @@ -0,0 +1,3983 @@ +TN:verilator_coverage +SF:./testbench/pulp-platform_axi_pr224/axi_lite_stubs.sv +DA:11,1 +BRDA:11,0,0,0 +BRDA:11,0,1,0 +BRDA:11,0,2,0 +BRDA:11,0,3,0 +BRDA:11,0,4,0 +BRDA:11,0,5,0 +BRDA:11,0,6,0 +BRDA:11,0,7,0 +BRDA:11,0,8,0 +BRDA:11,0,9,0 +BRDA:11,0,10,0 +BRDA:11,0,11,0 +BRDA:11,0,12,0 +BRDA:11,0,13,0 +BRDA:11,0,14,0 +BRDA:11,0,15,0 +BRDA:11,0,16,0 +BRDA:11,0,17,0 +BRDA:11,0,18,0 +BRDA:11,0,19,0 +BRDA:11,0,20,0 +BRDA:11,0,21,0 +BRDA:11,0,22,0 +BRDA:11,0,23,0 +BRDA:11,0,24,0 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b/testbench/pulp-platform_axi_riscv_atomics_pr33/open_tool_p2p_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..f7dbd9ee364cd4110f89bdd307808158d40a0ea9 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/open_tool_p2p_buggy.log @@ -0,0 +1,3 @@ +INFO: open-tool P2P fallback (buggy) +INFO: native simulation P2P not applicable for this case +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/open_tool_p2p_fixed.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/open_tool_p2p_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..e35c882693d15f397c8f26dacbfe49040de7f7c0 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/open_tool_p2p_fixed.log @@ -0,0 +1,3 @@ +INFO: open-tool P2P fallback (fixed) +INFO: native simulation P2P not applicable for this case +PASS: open-tool P2P fallback not applicable: no open-tool check passed diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/pr33_stubs.sv b/testbench/pulp-platform_axi_riscv_atomics_pr33/pr33_stubs.sv new file mode 100644 index 0000000000000000000000000000000000000000..a1bfaf24199aef86c8e61ca5339aabd3f0facae5 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/pr33_stubs.sv @@ -0,0 +1,262 @@ +`default_nettype none + +package axi_pkg; + localparam logic [1:0] RESP_OKAY = 2'b00; +endpackage + +module id_queue #( + parameter int ID_WIDTH = 0, + parameter int CAPACITY = 0, + parameter bit FULL_BW = 0, + parameter bit CUT_OUP_POP_INP_GNT = 0, + parameter int NUM_CMP_PORTS = 1, + parameter type data_t = logic [31:0], + localparam type id_t = logic [ID_WIDTH-1:0] +) ( + input logic clk_i, + input logic rst_ni, + input id_t inp_id_i, + input data_t inp_data_i, + input logic inp_req_i, + output logic inp_gnt_o, + input data_t [NUM_CMP_PORTS-1:0] exists_data_i, + input data_t [NUM_CMP_PORTS-1:0] exists_mask_i, + input logic [NUM_CMP_PORTS-1:0] exists_req_i, + output logic [NUM_CMP_PORTS-1:0] exists_o, + output logic [NUM_CMP_PORTS-1:0] exists_gnt_o, + input id_t oup_id_i, + input logic oup_pop_i, + input logic oup_req_i, + output data_t oup_data_o, + output logic oup_data_valid_o, + output logic oup_gnt_o, + output logic full_o, + output logic empty_o +); + typedef struct packed { + logic valid; + id_t id; + data_t data; + } entry_t; + + localparam int CountWidth = (CAPACITY <= 1) ? 1 : $clog2(CAPACITY + 1); + + entry_t [CAPACITY-1:0] entries_q; + logic [CountWidth-1:0] count_q; + logic match; + int unsigned match_idx; + logic will_pop; + + always_comb begin + match = 1'b0; + match_idx = 0; + for (int unsigned i = 0; i < CAPACITY; i++) begin + if (entries_q[i].valid && entries_q[i].id == oup_id_i && !match) begin + match = 1'b1; + match_idx = i; + end + end + end + + assign full_o = (count_q == CAPACITY[CountWidth-1:0]); + assign empty_o = (count_q == '0); + assign oup_gnt_o = oup_req_i && match; + assign oup_data_valid_o = oup_req_i && match; + assign oup_data_o = match ? entries_q[match_idx].data : data_t'('0); + assign will_pop = oup_req_i && oup_pop_i && match; + assign inp_gnt_o = !full_o || (FULL_BW && !CUT_OUP_POP_INP_GNT && will_pop); + + always_comb begin + exists_o = '0; + exists_gnt_o = exists_req_i; + for (int unsigned p = 0; p < NUM_CMP_PORTS; p++) begin + for (int unsigned i = 0; i < CAPACITY; i++) begin + if (entries_q[i].valid && ((entries_q[i].data & exists_mask_i[p]) == + (exists_data_i[p] & exists_mask_i[p]))) begin + exists_o[p] = 1'b1; + end + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + count_q <= '0; + for (int unsigned i = 0; i < CAPACITY; i++) entries_q[i] <= '0; + end else begin + logic pop_hs; + logic push_hs; + int unsigned free_idx; + + pop_hs = will_pop; + push_hs = inp_req_i && inp_gnt_o; + free_idx = CAPACITY; + + if (pop_hs) begin + entries_q[match_idx].valid <= 1'b0; + end + + for (int unsigned i = 0; i < CAPACITY; i++) begin + if (!entries_q[i].valid && free_idx == CAPACITY) free_idx = i; + end + if (pop_hs && free_idx == CAPACITY) free_idx = match_idx; + + if (push_hs) begin + entries_q[free_idx].valid <= 1'b1; + entries_q[free_idx].id <= inp_id_i; + entries_q[free_idx].data <= inp_data_i; + end + + unique case ({push_hs, pop_hs}) + 2'b10: count_q <= count_q + 1'b1; + 2'b01: count_q <= count_q - 1'b1; + default: count_q <= count_q; + endcase + end + end +endmodule + +module stream_fork #( + parameter int N_OUP = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + output logic ready_o, + output logic [N_OUP-1:0] valid_o, + input logic [N_OUP-1:0] ready_i +); + assign valid_o = {N_OUP{valid_i}}; + assign ready_o = &ready_i; +endmodule + +module stream_filter ( + input logic valid_i, + output logic ready_o, + input logic drop_i, + output logic valid_o, + input logic ready_i +); + assign valid_o = valid_i && !drop_i; + assign ready_o = drop_i || ready_i; +endmodule + +module stream_arbiter #( + parameter type DATA_T = logic, + parameter int N_INP = 0 +) ( + input logic clk_i, + input logic rst_ni, + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + assign oup_valid_o = |inp_valid_i; + assign oup_data_o = inp_data_i[0]; + assign inp_ready_o = {N_INP{oup_ready_i}}; +endmodule + +module fifo_v3 #( + parameter bit FALL_THROUGH = 1'b0, + parameter type dtype = logic, + parameter int unsigned DEPTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic testmode_i, + output logic full_o, + output logic empty_o, + output logic [$clog2(DEPTH+1)-1:0] usage_o, + input dtype data_i, + input logic push_i, + output dtype data_o, + input logic pop_i +); + assign full_o = 1'b0; + assign empty_o = 1'b0; + assign usage_o = '0; + assign data_o = data_i; +endmodule + +module fall_through_register #( + parameter type T = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic clr_i, + input logic testmode_i, + input logic valid_i, + output logic ready_o, + input T data_i, + output logic valid_o, + input logic ready_i, + output T data_o +); + assign ready_o = ready_i; + assign valid_o = valid_i; + assign data_o = data_i; +endmodule + +module stream_register #( + parameter type T = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic clr_i, + input logic testmode_i, + input logic valid_i, + output logic ready_o, + input T data_i, + output logic valid_o, + input logic ready_i, + output T data_o +); + assign ready_o = ready_i; + assign valid_o = valid_i; + assign data_o = data_i; +endmodule + +module spill_register #( + parameter type T = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + output logic ready_o, + input T data_i, + output logic valid_o, + input logic ready_i, + output T data_o +); + assign ready_o = ready_i; + assign valid_o = valid_i; + assign data_o = data_i; +endmodule + +module axi_res_tbl #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic [AXI_ADDR_WIDTH-1:0] check_clr_addr_i, + input logic [AXI_ID_WIDTH-1:0] check_id_i, + input logic check_clr_excl_i, + output logic check_res_o, + input logic check_clr_req_i, + output logic check_clr_gnt_o, + input logic [AXI_ADDR_WIDTH-1:0] set_addr_i, + input logic [AXI_ID_WIDTH-1:0] set_id_i, + input logic set_req_i, + output logic set_gnt_o +); + assign check_res_o = 1'b0; + assign check_clr_gnt_o = 1'b1; + assign set_gnt_o = 1'b1; +endmodule + +`default_nettype wire diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_buggy.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..8ca12dcb6d66aca082b8d86222bfe363ae26cc85 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_buggy.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_fixed.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..1fcdf963b8117df5eb377f1595102760513dc385 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_fixed.log @@ -0,0 +1 @@ +PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_source.path b/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_source.path new file mode 100644 index 0000000000000000000000000000000000000000..28881a8fba169eb3c1be2b56d8e82681a9d44256 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/repo_native_source.path @@ -0,0 +1 @@ +src/axi_res_tbl.sv diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/run_once.sh b/testbench/pulp-platform_axi_riscv_atomics_pr33/run_once.sh new file mode 100644 index 0000000000000000000000000000000000000000..73ead83d55e3b5e4350865e3a96345775772c04b --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/run_once.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh" diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/run_verilator.sh b/testbench/pulp-platform_axi_riscv_atomics_pr33/run_verilator.sh new file mode 100644 index 0000000000000000000000000000000000000000..656b13103c33ad2ddd4ead8fc5abb01b45b9f5e9 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/run_verilator.sh @@ -0,0 +1,105 @@ +#!/bin/bash +set -u +HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)" +cd "$HERE" +NAME=pulp-platform_axi_riscv_atomics_pr33 +TOP=tb_axi_riscv_lrsc_full_bw_param +REPO_ROOT="$(cd "$HERE/../.." && pwd)" +SNAPSHOT="$REPO_ROOT/snapshots/$NAME" +PATCH_FILE="$REPO_ROOT/patches/$NAME.patch" +SCRATCH="$HERE/snapshot_scratch" +. "$HERE/../_testcase_minimum.sh" +. "$HERE/../_repo_native_p2p_smoke.sh" +export HWE_AUTO_COVERAGE=1 + +trap 'rm -rf "$SCRATCH" obj_dir' EXIT + +prepare_phase() { + local tag="$1" + rm -rf "$SCRATCH" + cp -a "$SNAPSHOT" "$SCRATCH" + chmod -R u+w "$SCRATCH" + if [ "$tag" = fixed ]; then + (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true + else + (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true + fi +} + +run_phase() { + local tag="$1" + rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log" + run_repo_native_p2p_smoke "$tag" || return $? + rm -f coverage.dat "verilator_${tag}_coverage.dat" "verilator_${tag}_coverage.info" + + local cov_args=() + local extra_src=() + if [ "$tag" = fixed ]; then + cov_args=(--coverage --prefix Vhwe_cov_top) + extra_src=("$HERE/../_coverage_main.cpp") + verilator --cc --exe --build --timing --sv "${cov_args[@]}" \ + -Wno-fatal \ + --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME --Wno-UNOPTFLAT \ + --Wno-CASEINCOMPLETE --Wno-PINMISSING --Wno-UNSIGNED \ + --timescale 1ns/1ps \ + -I"$HERE" \ + "$HERE/pr33_stubs.sv" \ + "$SCRATCH/src/axi_riscv_lrsc.sv" \ + "$SCRATCH/src/axi_riscv_atomics.sv" \ + "$SCRATCH/src/axi_riscv_lrsc_wrap.sv" \ + "$SCRATCH/src/axi_riscv_atomics_wrap.sv" \ + "$SCRATCH/src/axi_riscv_atomics_structs.sv" \ + "$HERE/tb_axi_riscv_lrsc_full_bw_param.sv" \ + "${extra_src[@]}" \ + --top-module "$TOP" \ + -Mdir obj_dir -o simv_vlt 2>&1 | tee "verilator_${tag}_build.log" >/dev/null + else + verilator --binary --timing --sv \ + -Wno-fatal \ + --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME --Wno-UNOPTFLAT \ + --Wno-CASEINCOMPLETE --Wno-PINMISSING --Wno-UNSIGNED \ + --timescale 1ns/1ps \ + -I"$HERE" \ + "$HERE/pr33_stubs.sv" \ + "$SCRATCH/src/axi_riscv_lrsc.sv" \ + "$SCRATCH/src/axi_riscv_atomics.sv" \ + "$SCRATCH/src/axi_riscv_lrsc_wrap.sv" \ + "$SCRATCH/src/axi_riscv_atomics_wrap.sv" \ + "$SCRATCH/src/axi_riscv_atomics_structs.sv" \ + "$HERE/tb_axi_riscv_lrsc_full_bw_param.sv" \ + --top-module "$TOP" \ + -Mdir obj_dir -o simv_vlt 2>&1 | tee "verilator_${tag}_build.log" >/dev/null + fi + local rc=${PIPESTATUS[0]} + [ "$rc" -eq 0 ] || return "$rc" + + timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null + rc=${PIPESTATUS[0]} + [ "$rc" -eq 0 ] || return "$rc" + if [ "$tag" = fixed ] && [ -s coverage.dat ]; then + mv coverage.dat "verilator_${tag}_coverage.dat" + verilator_coverage --write-info "verilator_${tag}_coverage.info" "verilator_${tag}_coverage.dat" >/dev/null 2>&1 || true + fi + grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" \ + && ! grep -qE '(^|[^A-Za-z])(FAIL:|\$fatal|Aborting\.\.\.)' "verilator_${tag}.log" +} + +echo BUGGY +prepare_phase buggy +run_phase buggy +rc_buggy=$? +if [ "$rc_buggy" != "0" ]; then + touch verilator_buggy.log + grep -qE '^\s*(\[FAIL\]|FAIL)\b' verilator_buggy.log \ + || echo "FAIL: $NAME buggy state failed as expected" >> verilator_buggy.log +fi + +echo FIXED +prepare_phase fixed +run_phase fixed +rc_fixed=$? + +echo "buggy:$rc_buggy fixed:$rc_fixed" +([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] \ + && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } \ + || { echo "FAIL: $NAME"; exit 1; } diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/tb_axi_riscv_lrsc_full_bw_param.sv b/testbench/pulp-platform_axi_riscv_atomics_pr33/tb_axi_riscv_lrsc_full_bw_param.sv new file mode 100644 index 0000000000000000000000000000000000000000..fe341b71817f37283d3e7474c980787aea5362d6 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/tb_axi_riscv_lrsc_full_bw_param.sv @@ -0,0 +1,315 @@ +`default_nettype none + +module tb_axi_riscv_lrsc_full_bw_param; + localparam int unsigned AxiAddrWidth = 32; + localparam int unsigned AxiDataWidth = 64; + localparam int unsigned AxiIdWidth = 1; + localparam int unsigned AxiUserWidth = 1; + localparam int unsigned AxiStrbWidth = AxiDataWidth / 8; + + logic clk; + logic rst_n; + + logic [AxiAddrWidth-1:0] slv_aw_addr; + logic [2:0] slv_aw_prot; + logic [3:0] slv_aw_region; + logic [5:0] slv_aw_atop; + logic [7:0] slv_aw_len; + logic [2:0] slv_aw_size; + logic [1:0] slv_aw_burst; + logic slv_aw_lock; + logic [3:0] slv_aw_cache; + logic [3:0] slv_aw_qos; + logic [AxiIdWidth-1:0] slv_aw_id; + logic [AxiUserWidth-1:0] slv_aw_user; + logic slv_aw_ready; + logic slv_aw_valid; + + logic [AxiAddrWidth-1:0] slv_ar_addr; + logic [2:0] slv_ar_prot; + logic [3:0] slv_ar_region; + logic [7:0] slv_ar_len; + logic [2:0] slv_ar_size; + logic [1:0] slv_ar_burst; + logic slv_ar_lock; + logic [3:0] slv_ar_cache; + logic [3:0] slv_ar_qos; + logic [AxiIdWidth-1:0] slv_ar_id; + logic [AxiUserWidth-1:0] slv_ar_user; + logic slv_ar_ready; + logic slv_ar_valid; + + logic [AxiDataWidth-1:0] slv_w_data; + logic [AxiStrbWidth-1:0] slv_w_strb; + logic [AxiUserWidth-1:0] slv_w_user; + logic slv_w_last; + logic slv_w_ready; + logic slv_w_valid; + + logic [AxiDataWidth-1:0] slv_r_data; + logic [1:0] slv_r_resp; + logic slv_r_last; + logic [AxiIdWidth-1:0] slv_r_id; + logic [AxiUserWidth-1:0] slv_r_user; + logic slv_r_ready; + logic slv_r_valid; + + logic [1:0] slv_b_resp; + logic [AxiIdWidth-1:0] slv_b_id; + logic [AxiUserWidth-1:0] slv_b_user; + logic slv_b_ready; + logic slv_b_valid; + + logic [AxiAddrWidth-1:0] mst_aw_addr; + logic [2:0] mst_aw_prot; + logic [3:0] mst_aw_region; + logic [5:0] mst_aw_atop; + logic [7:0] mst_aw_len; + logic [2:0] mst_aw_size; + logic [1:0] mst_aw_burst; + logic mst_aw_lock; + logic [3:0] mst_aw_cache; + logic [3:0] mst_aw_qos; + logic [AxiIdWidth-1:0] mst_aw_id; + logic [AxiUserWidth-1:0] mst_aw_user; + logic mst_aw_ready; + logic mst_aw_valid; + + logic [AxiAddrWidth-1:0] mst_ar_addr; + logic [2:0] mst_ar_prot; + logic [3:0] mst_ar_region; + logic [7:0] mst_ar_len; + logic [2:0] mst_ar_size; + logic [1:0] mst_ar_burst; + logic mst_ar_lock; + logic [3:0] mst_ar_cache; + logic [3:0] mst_ar_qos; + logic [AxiIdWidth-1:0] mst_ar_id; + logic [AxiUserWidth-1:0] mst_ar_user; + logic mst_ar_ready; + logic mst_ar_valid; + + logic [AxiDataWidth-1:0] mst_w_data; + logic [AxiStrbWidth-1:0] mst_w_strb; + logic [AxiUserWidth-1:0] mst_w_user; + logic mst_w_last; + logic mst_w_ready; + logic mst_w_valid; + + logic [AxiDataWidth-1:0] mst_r_data; + logic [1:0] mst_r_resp; + logic mst_r_last; + logic [AxiIdWidth-1:0] mst_r_id; + logic [AxiUserWidth-1:0] mst_r_user; + logic mst_r_ready; + logic mst_r_valid; + + logic [1:0] mst_b_resp; + logic [AxiIdWidth-1:0] mst_b_id; + logic [AxiUserWidth-1:0] mst_b_user; + logic mst_b_ready; + logic mst_b_valid; + + axi_riscv_lrsc #( + .ADDR_BEGIN (32'h0000_0000), + .ADDR_END (32'h0000_ffff), + .AXI_ADDR_WIDTH (AxiAddrWidth), + .AXI_DATA_WIDTH (AxiDataWidth), + .AXI_ID_WIDTH (AxiIdWidth), + .AXI_USER_WIDTH (AxiUserWidth), + .AXI_MAX_READ_TXNS (1), + .AXI_MAX_WRITE_TXNS (1), + .AXI_USER_AS_ID (1'b0), + .AXI_USER_ID_MSB (0), + .AXI_USER_ID_LSB (0), + .FULL_BANDWIDTH (1'b0) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .slv_aw_addr_i(slv_aw_addr), + .slv_aw_prot_i(slv_aw_prot), + .slv_aw_region_i(slv_aw_region), + .slv_aw_atop_i(slv_aw_atop), + .slv_aw_len_i(slv_aw_len), + .slv_aw_size_i(slv_aw_size), + .slv_aw_burst_i(slv_aw_burst), + .slv_aw_lock_i(slv_aw_lock), + .slv_aw_cache_i(slv_aw_cache), + .slv_aw_qos_i(slv_aw_qos), + .slv_aw_id_i(slv_aw_id), + .slv_aw_user_i(slv_aw_user), + .slv_aw_ready_o(slv_aw_ready), + .slv_aw_valid_i(slv_aw_valid), + .slv_ar_addr_i(slv_ar_addr), + .slv_ar_prot_i(slv_ar_prot), + .slv_ar_region_i(slv_ar_region), + .slv_ar_len_i(slv_ar_len), + .slv_ar_size_i(slv_ar_size), + .slv_ar_burst_i(slv_ar_burst), + .slv_ar_lock_i(slv_ar_lock), + .slv_ar_cache_i(slv_ar_cache), + .slv_ar_qos_i(slv_ar_qos), + .slv_ar_id_i(slv_ar_id), + .slv_ar_user_i(slv_ar_user), + .slv_ar_ready_o(slv_ar_ready), + .slv_ar_valid_i(slv_ar_valid), + .slv_w_data_i(slv_w_data), + .slv_w_strb_i(slv_w_strb), + .slv_w_user_i(slv_w_user), + .slv_w_last_i(slv_w_last), + .slv_w_ready_o(slv_w_ready), + .slv_w_valid_i(slv_w_valid), + .slv_r_data_o(slv_r_data), + .slv_r_resp_o(slv_r_resp), + .slv_r_last_o(slv_r_last), + .slv_r_id_o(slv_r_id), + .slv_r_user_o(slv_r_user), + .slv_r_ready_i(slv_r_ready), + .slv_r_valid_o(slv_r_valid), + .slv_b_resp_o(slv_b_resp), + .slv_b_id_o(slv_b_id), + .slv_b_user_o(slv_b_user), + .slv_b_ready_i(slv_b_ready), + .slv_b_valid_o(slv_b_valid), + .mst_aw_addr_o(mst_aw_addr), + .mst_aw_prot_o(mst_aw_prot), + .mst_aw_region_o(mst_aw_region), + .mst_aw_atop_o(mst_aw_atop), + .mst_aw_len_o(mst_aw_len), + .mst_aw_size_o(mst_aw_size), + .mst_aw_burst_o(mst_aw_burst), + .mst_aw_lock_o(mst_aw_lock), + .mst_aw_cache_o(mst_aw_cache), + .mst_aw_qos_o(mst_aw_qos), + .mst_aw_id_o(mst_aw_id), + .mst_aw_user_o(mst_aw_user), + .mst_aw_ready_i(mst_aw_ready), + .mst_aw_valid_o(mst_aw_valid), + .mst_ar_addr_o(mst_ar_addr), + .mst_ar_prot_o(mst_ar_prot), + .mst_ar_region_o(mst_ar_region), + .mst_ar_len_o(mst_ar_len), + .mst_ar_size_o(mst_ar_size), + .mst_ar_burst_o(mst_ar_burst), + .mst_ar_lock_o(mst_ar_lock), + .mst_ar_cache_o(mst_ar_cache), + .mst_ar_qos_o(mst_ar_qos), + .mst_ar_id_o(mst_ar_id), + .mst_ar_user_o(mst_ar_user), + .mst_ar_ready_i(mst_ar_ready), + .mst_ar_valid_o(mst_ar_valid), + .mst_w_data_o(mst_w_data), + .mst_w_strb_o(mst_w_strb), + .mst_w_user_o(mst_w_user), + .mst_w_last_o(mst_w_last), + .mst_w_ready_i(mst_w_ready), + .mst_w_valid_o(mst_w_valid), + .mst_r_data_i(mst_r_data), + .mst_r_resp_i(mst_r_resp), + .mst_r_last_i(mst_r_last), + .mst_r_id_i(mst_r_id), + .mst_r_user_i(mst_r_user), + .mst_r_ready_o(mst_r_ready), + .mst_r_valid_i(mst_r_valid), + .mst_b_resp_i(mst_b_resp), + .mst_b_id_i(mst_b_id), + .mst_b_user_i(mst_b_user), + .mst_b_ready_o(mst_b_ready), + .mst_b_valid_i(mst_b_valid) + ); + + always #5 clk = ~clk; + + task automatic clear_inputs; + begin + slv_aw_addr = '0; + slv_aw_prot = '0; + slv_aw_region = '0; + slv_aw_atop = '0; + slv_aw_len = '0; + slv_aw_size = 3'd3; + slv_aw_burst = '0; + slv_aw_lock = 1'b0; + slv_aw_cache = '0; + slv_aw_qos = '0; + slv_aw_id = '0; + slv_aw_user = '0; + slv_aw_valid = 1'b0; + slv_ar_addr = 32'h1000; + slv_ar_prot = '0; + slv_ar_region = '0; + slv_ar_len = '0; + slv_ar_size = 3'd3; + slv_ar_burst = '0; + slv_ar_lock = 1'b0; + slv_ar_cache = '0; + slv_ar_qos = '0; + slv_ar_id = '0; + slv_ar_user = '0; + slv_ar_valid = 1'b0; + slv_w_data = '0; + slv_w_strb = '0; + slv_w_user = '0; + slv_w_last = 1'b1; + slv_w_valid = 1'b0; + slv_r_ready = 1'b1; + slv_b_ready = 1'b1; + mst_aw_ready = 1'b1; + mst_ar_ready = 1'b1; + mst_w_ready = 1'b1; + mst_r_data = 64'h1234_5678_9abc_def0; + mst_r_resp = 2'b00; + mst_r_last = 1'b1; + mst_r_id = '0; + mst_r_user = '0; + mst_r_valid = 1'b0; + mst_b_resp = 2'b00; + mst_b_id = '0; + mst_b_user = '0; + mst_b_valid = 1'b0; + end + endtask + + initial begin + clk = 1'b0; + rst_n = 1'b0; + clear_inputs(); + repeat (3) @(posedge clk); + rst_n = 1'b1; + @(posedge clk); + + @(negedge clk); + slv_ar_valid = 1'b1; + #1; + if (slv_ar_ready !== 1'b1 || mst_ar_valid !== 1'b1) begin + $display("FAIL: initial AR did not fill the read in-flight ID queue"); + $fatal(1); + end + @(posedge clk); + #1; + + slv_ar_valid = 1'b0; + @(negedge clk); + + slv_ar_valid = 1'b1; + mst_r_valid = 1'b1; + #1; + if (mst_r_ready !== 1'b1 || slv_r_valid !== 1'b1) begin + $display("FAIL: queued R response was not popped"); + $fatal(1); + end + if (slv_ar_ready !== 1'b0 || mst_ar_valid !== 1'b0) begin + $display("FAIL: FULL_BANDWIDTH=0 did not block a same-cycle push into a full read ID queue"); + $fatal(1); + end + + @(posedge clk); + #1; + slv_ar_valid = 1'b0; + mst_r_valid = 1'b0; + $display("PASS: axi_riscv_lrsc exposes FULL_BANDWIDTH=0 and disables same-cycle ID queue reuse"); + $finish; + end +endmodule + +`default_nettype wire diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_buggy.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_buggy.log new file mode 100644 index 0000000000000000000000000000000000000000..345aaf454b31a7f1a8bacd3a4cef8975a4a23cb5 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_buggy.log @@ -0,0 +1 @@ +FAIL: pulp-platform_axi_riscv_atomics_pr33 buggy state failed as expected diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_buggy_build.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_buggy_build.log new file mode 100644 index 0000000000000000000000000000000000000000..d0618dd606c8646af3653371b639e7d3bf3e1767 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_buggy_build.log @@ -0,0 +1,17 @@ +%Error-PINNOTFOUND: testbench/pulp-platform_axi_riscv_atomics_pr33/tb_axi_riscv_lrsc_full_bw_param.sv:125:6: Parameter not found: 'FULL_BANDWIDTH' + 125 | .FULL_BANDWIDTH (1'b0) + | ^~~~~~~~~~~~~~ + : ... Location of instance's module declaration + 30 | module axi_riscv_lrsc #( + | ^~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=5.047 +%Error: Exiting due to 1 error(s) +HWE_AUTO_COVERAGE: retrying with --coverage-line +%Error-PINNOTFOUND: testbench/pulp-platform_axi_riscv_atomics_pr33/tb_axi_riscv_lrsc_full_bw_param.sv:125:6: Parameter not found: 'FULL_BANDWIDTH' + 125 | .FULL_BANDWIDTH (1'b0) + | ^~~~~~~~~~~~~~ + : ... Location of instance's module declaration + 30 | module axi_riscv_lrsc #( + | ^~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=5.047 +%Error: Exiting due to 1 error(s) diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed.log new file mode 100644 index 0000000000000000000000000000000000000000..1dd7ec347936c7582995ed89c7e9629b838d7910 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed.log @@ -0,0 +1,2 @@ +PASS: axi_riscv_lrsc exposes FULL_BANDWIDTH=0 and disables same-cycle ID queue reuse +- testbench/pulp-platform_axi_riscv_atomics_pr33/tb_axi_riscv_lrsc_full_bw_param.sv:311: Verilog $finish diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed_build.log b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed_build.log new file mode 100644 index 0000000000000000000000000000000000000000..acca24cc56c44f83cf443f5c58c8328c8531c659 --- /dev/null +++ b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed_build.log @@ -0,0 +1,14 @@ +make: Entering directory 'testbench/pulp-platform_axi_riscv_atomics_pr33/obj_dir' +g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/pulp-platform_axi_riscv_atomics_pr33/../_coverage_main.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp +python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp +g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp +g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt +rm Vhwe_cov_top__ALL.verilator_deplist.tmp +make: Leaving directory 'testbench/pulp-platform_axi_riscv_atomics_pr33/obj_dir' +- V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod) +- Verilator: Built from 0.728 MB sources in 20 modules, into 0.866 MB in 5 C++ files needing 0.001 MB +- Verilator: Walltime 9.089 s (elab=0.006, cvt=0.046, bld=9.018); cpu 0.072 s on 1 threads; allocated 26.152 MB diff --git a/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed_coverage.info b/testbench/pulp-platform_axi_riscv_atomics_pr33/verilator_fixed_coverage.info new file mode 100644 index 0000000000000000000000000000000000000000..6534cae613d4223e3e2a94519241e997b495250a --- /dev/null +++ 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